1 ///===-- FastISel.cpp - Implementation of the FastISel class --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the implementation of the FastISel class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Instructions.h"
15 #include "llvm/CodeGen/FastISel.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/Target/TargetData.h"
19 #include "llvm/Target/TargetInstrInfo.h"
20 #include "llvm/Target/TargetLowering.h"
21 #include "llvm/Target/TargetMachine.h"
24 /// SelectBinaryOp - Select and emit code for a binary operator instruction,
25 /// which has an opcode which directly corresponds to the given ISD opcode.
27 bool FastISel::SelectBinaryOp(Instruction *I, ISD::NodeType ISDOpcode,
28 DenseMap<const Value*, unsigned> &ValueMap) {
29 MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
30 if (VT == MVT::Other || !VT.isSimple())
31 // Unhandled type. Halt "fast" selection and bail.
33 // We only handle legal types. For example, on x86-32 the instruction
34 // selector contains all of the 64-bit instructions from x86-64,
35 // under the assumption that i64 won't be used if the target doesn't
37 if (!TLI.isTypeLegal(VT))
40 unsigned Op0 = ValueMap[I->getOperand(0)];
42 // Unhandled operand. Halt "fast" selection and bail.
45 // Check if the second operand is a constant and handle it appropriately.
46 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
47 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0,
48 CI->getZExtValue(), VT.getSimpleVT());
50 // Target-specific code wasn't able to find a machine opcode for
51 // the given ISD opcode and type. Halt "fast" selection and bail.
54 // We successfully emitted code for the given LLVM Instruction.
55 ValueMap[I] = ResultReg;
59 unsigned Op1 = ValueMap[I->getOperand(1)];
61 // Unhandled operand. Halt "fast" selection and bail.
64 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
67 // Target-specific code wasn't able to find a machine opcode for
68 // the given ISD opcode and type. Halt "fast" selection and bail.
71 // We successfully emitted code for the given LLVM Instruction.
72 ValueMap[I] = ResultReg;
76 bool FastISel::SelectGetElementPtr(Instruction *I,
77 DenseMap<const Value*, unsigned> &ValueMap) {
78 unsigned N = ValueMap[I->getOperand(0)];
80 // Unhandled operand. Halt "fast" selection and bail.
83 const Type *Ty = I->getOperand(0)->getType();
84 MVT::SimpleValueType VT = TLI.getPointerTy().getSimpleVT();
85 for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end();
88 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
89 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
92 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field);
93 // FIXME: This can be optimized by combining the add with a
95 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
97 // Unhandled operand. Halt "fast" selection and bail.
100 Ty = StTy->getElementType(Field);
102 Ty = cast<SequentialType>(Ty)->getElementType();
104 // If this is a constant subscript, handle it quickly.
105 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
106 if (CI->getZExtValue() == 0) continue;
108 TD.getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
109 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
111 // Unhandled operand. Halt "fast" selection and bail.
116 // N = N + Idx * ElementSize;
117 uint64_t ElementSize = TD.getABITypeSize(Ty);
118 unsigned IdxN = ValueMap[Idx];
120 // Unhandled operand. Halt "fast" selection and bail.
123 // If the index is smaller or larger than intptr_t, truncate or extend
125 MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false);
126 if (IdxVT.bitsLT(VT))
127 IdxN = FastEmit_r(VT, VT, ISD::SIGN_EXTEND, IdxN);
128 else if (IdxVT.bitsGT(VT))
129 IdxN = FastEmit_r(VT, VT, ISD::TRUNCATE, IdxN);
131 // Unhandled operand. Halt "fast" selection and bail.
134 if (ElementSize != 1)
135 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT);
137 // Unhandled operand. Halt "fast" selection and bail.
139 N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN);
141 // Unhandled operand. Halt "fast" selection and bail.
146 // We successfully emitted code for the given LLVM Instruction.
152 FastISel::SelectInstructions(BasicBlock::iterator Begin,
153 BasicBlock::iterator End,
154 DenseMap<const Value*, unsigned> &ValueMap,
155 DenseMap<const BasicBlock*,
156 MachineBasicBlock *> &MBBMap,
157 MachineBasicBlock *mbb) {
159 BasicBlock::iterator I = Begin;
161 for (; I != End; ++I) {
162 switch (I->getOpcode()) {
163 case Instruction::Add: {
164 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FADD : ISD::ADD;
165 if (!SelectBinaryOp(I, Opc, ValueMap)) return I; break;
167 case Instruction::Sub: {
168 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FSUB : ISD::SUB;
169 if (!SelectBinaryOp(I, Opc, ValueMap)) return I; break;
171 case Instruction::Mul: {
172 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FMUL : ISD::MUL;
173 if (!SelectBinaryOp(I, Opc, ValueMap)) return I; break;
175 case Instruction::SDiv:
176 if (!SelectBinaryOp(I, ISD::SDIV, ValueMap)) return I; break;
177 case Instruction::UDiv:
178 if (!SelectBinaryOp(I, ISD::UDIV, ValueMap)) return I; break;
179 case Instruction::FDiv:
180 if (!SelectBinaryOp(I, ISD::FDIV, ValueMap)) return I; break;
181 case Instruction::SRem:
182 if (!SelectBinaryOp(I, ISD::SREM, ValueMap)) return I; break;
183 case Instruction::URem:
184 if (!SelectBinaryOp(I, ISD::UREM, ValueMap)) return I; break;
185 case Instruction::FRem:
186 if (!SelectBinaryOp(I, ISD::FREM, ValueMap)) return I; break;
187 case Instruction::Shl:
188 if (!SelectBinaryOp(I, ISD::SHL, ValueMap)) return I; break;
189 case Instruction::LShr:
190 if (!SelectBinaryOp(I, ISD::SRL, ValueMap)) return I; break;
191 case Instruction::AShr:
192 if (!SelectBinaryOp(I, ISD::SRA, ValueMap)) return I; break;
193 case Instruction::And:
194 if (!SelectBinaryOp(I, ISD::AND, ValueMap)) return I; break;
195 case Instruction::Or:
196 if (!SelectBinaryOp(I, ISD::OR, ValueMap)) return I; break;
197 case Instruction::Xor:
198 if (!SelectBinaryOp(I, ISD::XOR, ValueMap)) return I; break;
200 case Instruction::GetElementPtr:
201 if (!SelectGetElementPtr(I, ValueMap)) return I;
204 case Instruction::Br: {
205 BranchInst *BI = cast<BranchInst>(I);
207 if (BI->isUnconditional()) {
208 MachineFunction::iterator NextMBB =
209 next(MachineFunction::iterator(MBB));
210 BasicBlock *LLVMSucc = BI->getSuccessor(0);
211 MachineBasicBlock *MSucc = MBBMap[LLVMSucc];
213 if (NextMBB != MF.end() && MSucc == NextMBB) {
214 // The unconditional fall-through case, which needs no instructions.
216 // The unconditional branch case.
217 TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>());
219 MBB->addSuccessor(MSucc);
223 // Conditional branches are not handed yet.
224 // Halt "fast" selection and bail.
228 case Instruction::PHI:
229 // PHI nodes are already emitted.
232 case Instruction::BitCast:
233 // BitCast consists of either an immediate to register move
234 // or a register to register move.
235 if (ConstantInt* CI = dyn_cast<ConstantInt>(I->getOperand(0))) {
236 if (I->getType()->isInteger()) {
237 MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/false);
238 unsigned result = FastEmit_i(VT.getSimpleVT(), VT.getSimpleVT(),
244 ValueMap[I] = result;
247 // TODO: Support vector and fp constants.
249 } else if (!isa<Constant>(I->getOperand(0))) {
250 // Bitcasts of non-constant values become reg-reg copies.
251 MVT SrcVT = MVT::getMVT(I->getOperand(0)->getType());
252 MVT DstVT = MVT::getMVT(I->getType());
254 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
255 DstVT == MVT::Other || !DstVT.isSimple() ||
256 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
257 // Unhandled type. Halt "fast" selection and bail.
260 unsigned Op0 = ValueMap[I->getOperand(0)];
262 // Unhandled operand. Halt "fast" selection and bail.
265 // First, try to perform the bitcast by inserting a reg-reg copy.
266 unsigned ResultReg = 0;
267 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
268 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
269 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
270 ResultReg = createResultReg(DstClass);
272 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
273 Op0, DstClass, SrcClass);
278 // If the reg-reg copy failed, select a BIT_CONVERT opcode.
280 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
281 ISD::BIT_CONVERT, Op0);
286 ValueMap[I] = ResultReg;
289 // TODO: Casting a non-integral constant?
292 case Instruction::FPToSI:
293 if (!isa<ConstantFP>(I->getOperand(0))) {
294 MVT SrcVT = MVT::getMVT(I->getOperand(0)->getType());
295 MVT DstVT = MVT::getMVT(I->getType());
297 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
298 DstVT == MVT::Other || !DstVT.isSimple() ||
299 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
300 // Unhandled type. Halt "fast" selection and bail.
303 unsigned InputReg = ValueMap[I->getOperand(0)];
305 // Unhandled operand. Halt "fast" selection and bail.
308 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
315 ValueMap[I] = ResultReg;
318 // TODO: Materialize the FP constant and then convert,
319 // or attempt constant folding.
322 case Instruction::SIToFP:
323 if (!isa<ConstantInt>(I->getOperand(0))) {
324 MVT SrcVT = MVT::getMVT(I->getOperand(0)->getType());
325 MVT DstVT = MVT::getMVT(I->getType());
327 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
328 DstVT == MVT::Other || !DstVT.isSimple() ||
329 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
330 // Unhandled type. Halt "fast" selection and bail.
333 unsigned InputReg = ValueMap[I->getOperand(0)];
335 // Unhandled operan. Halt "fast" selection and bail.
338 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
345 ValueMap[I] = ResultReg;
348 // TODO: Materialize constant and convert to FP.
351 // Unhandled instruction. Halt "fast" selection and bail.
359 FastISel::FastISel(MachineFunction &mf)
361 MRI(mf.getRegInfo()),
363 TD(*TM.getTargetData()),
364 TII(*TM.getInstrInfo()),
365 TLI(*TM.getTargetLowering()) {
368 FastISel::~FastISel() {}
370 unsigned FastISel::FastEmit_(MVT::SimpleValueType, MVT::SimpleValueType, ISD::NodeType) {
374 unsigned FastISel::FastEmit_r(MVT::SimpleValueType, MVT::SimpleValueType,
375 ISD::NodeType, unsigned /*Op0*/) {
379 unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, MVT::SimpleValueType,
380 ISD::NodeType, unsigned /*Op0*/,
385 unsigned FastISel::FastEmit_i(MVT::SimpleValueType, MVT::SimpleValueType,
386 ISD::NodeType, uint64_t /*Imm*/) {
390 unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, MVT::SimpleValueType,
391 ISD::NodeType, unsigned /*Op0*/,
396 unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, MVT::SimpleValueType,
398 unsigned /*Op0*/, unsigned /*Op1*/,
403 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
404 /// to emit an instruction with an immediate operand using FastEmit_ri.
405 /// If that fails, it materializes the immediate into a register and try
406 /// FastEmit_rr instead.
407 unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
408 unsigned Op0, uint64_t Imm,
409 MVT::SimpleValueType ImmType) {
410 unsigned ResultReg = 0;
411 // First check if immediate type is legal. If not, we can't use the ri form.
412 if (TLI.getOperationAction(ISD::Constant, ImmType) == TargetLowering::Legal)
413 ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm);
416 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
417 if (MaterialReg == 0)
419 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
422 unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
423 return MRI.createVirtualRegister(RC);
426 unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
427 const TargetRegisterClass* RC) {
428 unsigned ResultReg = createResultReg(RC);
429 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
431 BuildMI(MBB, II, ResultReg);
435 unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
436 const TargetRegisterClass *RC,
438 unsigned ResultReg = createResultReg(RC);
439 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
441 BuildMI(MBB, II, ResultReg).addReg(Op0);
445 unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
446 const TargetRegisterClass *RC,
447 unsigned Op0, unsigned Op1) {
448 unsigned ResultReg = createResultReg(RC);
449 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
451 BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1);
455 unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
456 const TargetRegisterClass *RC,
457 unsigned Op0, uint64_t Imm) {
458 unsigned ResultReg = createResultReg(RC);
459 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
461 BuildMI(MBB, II, ResultReg).addReg(Op0).addImm(Imm);
465 unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
466 const TargetRegisterClass *RC,
467 unsigned Op0, unsigned Op1, uint64_t Imm) {
468 unsigned ResultReg = createResultReg(RC);
469 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
471 BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm);
475 unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
476 const TargetRegisterClass *RC,
478 unsigned ResultReg = createResultReg(RC);
479 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
481 BuildMI(MBB, II, ResultReg).addImm(Imm);