1 ///===-- FastISel.cpp - Implementation of the FastISel class --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the implementation of the FastISel class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Instructions.h"
15 #include "llvm/CodeGen/FastISel.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/Target/TargetData.h"
19 #include "llvm/Target/TargetInstrInfo.h"
20 #include "llvm/Target/TargetLowering.h"
21 #include "llvm/Target/TargetMachine.h"
24 unsigned FastISel::getRegForValue(Value *V) {
25 // Look up the value to see if we already have a register for it. We
26 // cache values defined by Instructions across blocks, and other values
27 // only locally. This is because Instructions already have the SSA
28 // def-dominatess-use requirement enforced.
29 if (ValueMap.count(V))
31 unsigned Reg = LocalValueMap[V];
35 MVT::SimpleValueType VT = TLI.getValueType(V->getType()).getSimpleVT();
36 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
37 if (CI->getValue().getActiveBits() > 64)
38 return TargetMaterializeConstant(CI,
39 MBB->getParent()->getConstantPool());
40 // Don't cache constant materializations. To do so would require
41 // tracking what uses they dominate.
42 if (!TLI.isTypeLegal(VT))
44 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
45 } else if (isa<GlobalValue>(V)) {
46 return TargetMaterializeConstant(dyn_cast<Constant>(V),
47 MBB->getParent()->getConstantPool());
48 } else if (isa<ConstantPointerNull>(V)) {
49 Reg = FastEmit_i(VT, VT, ISD::Constant, 0);
50 } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
51 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
54 const APFloat &Flt = CF->getValueAPF();
55 MVT IntVT = TLI.getPointerTy();
58 uint32_t IntBitWidth = IntVT.getSizeInBits();
59 if (Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
60 APFloat::rmTowardZero) != APFloat::opOK)
61 return TargetMaterializeConstant(CF,
62 MBB->getParent()->getConstantPool());
63 APInt IntVal(IntBitWidth, 2, x);
65 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
66 ISD::Constant, IntVal.getZExtValue());
68 return TargetMaterializeConstant(CF,
69 MBB->getParent()->getConstantPool());
70 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg);
72 return TargetMaterializeConstant(CF,
73 MBB->getParent()->getConstantPool());;
75 } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) {
76 if (!SelectOperator(CE, CE->getOpcode())) return 0;
77 Reg = LocalValueMap[CE];
78 } else if (isa<UndefValue>(V)) {
79 Reg = createResultReg(TLI.getRegClassFor(VT));
80 BuildMI(MBB, TII.get(TargetInstrInfo::IMPLICIT_DEF), Reg);
85 if (!Reg && isa<Constant>(V))
86 return TargetMaterializeConstant(cast<Constant>(V),
87 MBB->getParent()->getConstantPool());
89 LocalValueMap[V] = Reg;
93 unsigned FastISel::lookUpRegForValue(Value *V) {
94 // Look up the value to see if we already have a register for it. We
95 // cache values defined by Instructions across blocks, and other values
96 // only locally. This is because Instructions already have the SSA
97 // def-dominatess-use requirement enforced.
98 if (ValueMap.count(V))
100 return LocalValueMap[V];
103 /// UpdateValueMap - Update the value map to include the new mapping for this
104 /// instruction, or insert an extra copy to get the result in a previous
105 /// determined register.
106 /// NOTE: This is only necessary because we might select a block that uses
107 /// a value before we select the block that defines the value. It might be
108 /// possible to fix this by selecting blocks in reverse postorder.
109 void FastISel::UpdateValueMap(Value* I, unsigned Reg) {
110 if (!isa<Instruction>(I)) {
111 LocalValueMap[I] = Reg;
114 if (!ValueMap.count(I))
117 TII.copyRegToReg(*MBB, MBB->end(), ValueMap[I],
118 Reg, MRI.getRegClass(Reg), MRI.getRegClass(Reg));
121 /// SelectBinaryOp - Select and emit code for a binary operator instruction,
122 /// which has an opcode which directly corresponds to the given ISD opcode.
124 bool FastISel::SelectBinaryOp(User *I, ISD::NodeType ISDOpcode) {
125 MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
126 if (VT == MVT::Other || !VT.isSimple())
127 // Unhandled type. Halt "fast" selection and bail.
130 // We only handle legal types. For example, on x86-32 the instruction
131 // selector contains all of the 64-bit instructions from x86-64,
132 // under the assumption that i64 won't be used if the target doesn't
134 if (!TLI.isTypeLegal(VT)) {
135 // MVT::i1 is special. Allow AND and OR (but not XOR) because they
136 // don't require additional zeroing, which makes them easy.
138 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR))
139 VT = TLI.getTypeToTransformTo(VT);
144 unsigned Op0 = getRegForValue(I->getOperand(0));
146 // Unhandled operand. Halt "fast" selection and bail.
149 // Check if the second operand is a constant and handle it appropriately.
150 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
151 unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(),
152 ISDOpcode, Op0, CI->getZExtValue());
153 if (ResultReg != 0) {
154 // We successfully emitted code for the given LLVM Instruction.
155 UpdateValueMap(I, ResultReg);
160 // Check if the second operand is a constant float.
161 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
162 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
164 if (ResultReg != 0) {
165 // We successfully emitted code for the given LLVM Instruction.
166 UpdateValueMap(I, ResultReg);
171 unsigned Op1 = getRegForValue(I->getOperand(1));
173 // Unhandled operand. Halt "fast" selection and bail.
176 // Now we have both operands in registers. Emit the instruction.
177 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
178 ISDOpcode, Op0, Op1);
180 // Target-specific code wasn't able to find a machine opcode for
181 // the given ISD opcode and type. Halt "fast" selection and bail.
184 // We successfully emitted code for the given LLVM Instruction.
185 UpdateValueMap(I, ResultReg);
189 bool FastISel::SelectGetElementPtr(User *I) {
190 unsigned N = getRegForValue(I->getOperand(0));
192 // Unhandled operand. Halt "fast" selection and bail.
195 const Type *Ty = I->getOperand(0)->getType();
196 MVT::SimpleValueType VT = TLI.getPointerTy().getSimpleVT();
197 for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end();
200 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
201 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
204 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field);
205 // FIXME: This can be optimized by combining the add with a
207 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
209 // Unhandled operand. Halt "fast" selection and bail.
212 Ty = StTy->getElementType(Field);
214 Ty = cast<SequentialType>(Ty)->getElementType();
216 // If this is a constant subscript, handle it quickly.
217 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
218 if (CI->getZExtValue() == 0) continue;
220 TD.getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
221 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
223 // Unhandled operand. Halt "fast" selection and bail.
228 // N = N + Idx * ElementSize;
229 uint64_t ElementSize = TD.getABITypeSize(Ty);
230 unsigned IdxN = getRegForValue(Idx);
232 // Unhandled operand. Halt "fast" selection and bail.
235 // If the index is smaller or larger than intptr_t, truncate or extend
237 MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false);
238 if (IdxVT.bitsLT(VT))
239 IdxN = FastEmit_r(IdxVT.getSimpleVT(), VT, ISD::SIGN_EXTEND, IdxN);
240 else if (IdxVT.bitsGT(VT))
241 IdxN = FastEmit_r(IdxVT.getSimpleVT(), VT, ISD::TRUNCATE, IdxN);
243 // Unhandled operand. Halt "fast" selection and bail.
246 if (ElementSize != 1) {
247 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT);
249 // Unhandled operand. Halt "fast" selection and bail.
252 N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN);
254 // Unhandled operand. Halt "fast" selection and bail.
259 // We successfully emitted code for the given LLVM Instruction.
260 UpdateValueMap(I, N);
264 bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) {
265 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
266 MVT DstVT = TLI.getValueType(I->getType());
268 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
269 DstVT == MVT::Other || !DstVT.isSimple() ||
270 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
271 // Unhandled type. Halt "fast" selection and bail.
274 unsigned InputReg = getRegForValue(I->getOperand(0));
276 // Unhandled operand. Halt "fast" selection and bail.
279 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
286 UpdateValueMap(I, ResultReg);
290 bool FastISel::SelectBitCast(User *I) {
291 // If the bitcast doesn't change the type, just use the operand value.
292 if (I->getType() == I->getOperand(0)->getType()) {
293 unsigned Reg = getRegForValue(I->getOperand(0));
296 UpdateValueMap(I, Reg);
300 // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators.
301 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
302 MVT DstVT = TLI.getValueType(I->getType());
304 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
305 DstVT == MVT::Other || !DstVT.isSimple() ||
306 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
307 // Unhandled type. Halt "fast" selection and bail.
310 unsigned Op0 = getRegForValue(I->getOperand(0));
312 // Unhandled operand. Halt "fast" selection and bail.
315 // First, try to perform the bitcast by inserting a reg-reg copy.
316 unsigned ResultReg = 0;
317 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
318 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
319 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
320 ResultReg = createResultReg(DstClass);
322 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
323 Op0, DstClass, SrcClass);
328 // If the reg-reg copy failed, select a BIT_CONVERT opcode.
330 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
331 ISD::BIT_CONVERT, Op0);
336 UpdateValueMap(I, ResultReg);
341 FastISel::SelectInstruction(Instruction *I) {
342 return SelectOperator(I, I->getOpcode());
346 FastISel::SelectOperator(User *I, unsigned Opcode) {
348 case Instruction::Add: {
349 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FADD : ISD::ADD;
350 return SelectBinaryOp(I, Opc);
352 case Instruction::Sub: {
353 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FSUB : ISD::SUB;
354 return SelectBinaryOp(I, Opc);
356 case Instruction::Mul: {
357 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FMUL : ISD::MUL;
358 return SelectBinaryOp(I, Opc);
360 case Instruction::SDiv:
361 return SelectBinaryOp(I, ISD::SDIV);
362 case Instruction::UDiv:
363 return SelectBinaryOp(I, ISD::UDIV);
364 case Instruction::FDiv:
365 return SelectBinaryOp(I, ISD::FDIV);
366 case Instruction::SRem:
367 return SelectBinaryOp(I, ISD::SREM);
368 case Instruction::URem:
369 return SelectBinaryOp(I, ISD::UREM);
370 case Instruction::FRem:
371 return SelectBinaryOp(I, ISD::FREM);
372 case Instruction::Shl:
373 return SelectBinaryOp(I, ISD::SHL);
374 case Instruction::LShr:
375 return SelectBinaryOp(I, ISD::SRL);
376 case Instruction::AShr:
377 return SelectBinaryOp(I, ISD::SRA);
378 case Instruction::And:
379 return SelectBinaryOp(I, ISD::AND);
380 case Instruction::Or:
381 return SelectBinaryOp(I, ISD::OR);
382 case Instruction::Xor:
383 return SelectBinaryOp(I, ISD::XOR);
385 case Instruction::GetElementPtr:
386 return SelectGetElementPtr(I);
388 case Instruction::Br: {
389 BranchInst *BI = cast<BranchInst>(I);
391 if (BI->isUnconditional()) {
392 MachineFunction::iterator NextMBB =
393 next(MachineFunction::iterator(MBB));
394 BasicBlock *LLVMSucc = BI->getSuccessor(0);
395 MachineBasicBlock *MSucc = MBBMap[LLVMSucc];
397 if (NextMBB != MF.end() && MSucc == NextMBB) {
398 // The unconditional fall-through case, which needs no instructions.
400 // The unconditional branch case.
401 TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>());
403 MBB->addSuccessor(MSucc);
407 // Conditional branches are not handed yet.
408 // Halt "fast" selection and bail.
412 case Instruction::Unreachable:
416 case Instruction::PHI:
417 // PHI nodes are already emitted.
420 case Instruction::BitCast:
421 return SelectBitCast(I);
423 case Instruction::FPToSI:
424 return SelectCast(I, ISD::FP_TO_SINT);
425 case Instruction::ZExt:
426 return SelectCast(I, ISD::ZERO_EXTEND);
427 case Instruction::SExt:
428 return SelectCast(I, ISD::SIGN_EXTEND);
429 case Instruction::Trunc:
430 return SelectCast(I, ISD::TRUNCATE);
431 case Instruction::SIToFP:
432 return SelectCast(I, ISD::SINT_TO_FP);
434 case Instruction::IntToPtr: // Deliberate fall-through.
435 case Instruction::PtrToInt: {
436 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
437 MVT DstVT = TLI.getValueType(I->getType());
438 if (DstVT.bitsGT(SrcVT))
439 return SelectCast(I, ISD::ZERO_EXTEND);
440 if (DstVT.bitsLT(SrcVT))
441 return SelectCast(I, ISD::TRUNCATE);
442 unsigned Reg = getRegForValue(I->getOperand(0));
443 if (Reg == 0) return false;
444 UpdateValueMap(I, Reg);
449 // Unhandled instruction. Halt "fast" selection and bail.
454 FastISel::FastISel(MachineFunction &mf,
455 DenseMap<const Value *, unsigned> &vm,
456 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm)
461 MRI(MF.getRegInfo()),
463 TD(*TM.getTargetData()),
464 TII(*TM.getInstrInfo()),
465 TLI(*TM.getTargetLowering()) {
468 FastISel::~FastISel() {}
470 unsigned FastISel::FastEmit_(MVT::SimpleValueType, MVT::SimpleValueType,
475 unsigned FastISel::FastEmit_r(MVT::SimpleValueType, MVT::SimpleValueType,
476 ISD::NodeType, unsigned /*Op0*/) {
480 unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, MVT::SimpleValueType,
481 ISD::NodeType, unsigned /*Op0*/,
486 unsigned FastISel::FastEmit_i(MVT::SimpleValueType, MVT::SimpleValueType,
487 ISD::NodeType, uint64_t /*Imm*/) {
491 unsigned FastISel::FastEmit_f(MVT::SimpleValueType, MVT::SimpleValueType,
492 ISD::NodeType, ConstantFP * /*FPImm*/) {
496 unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, MVT::SimpleValueType,
497 ISD::NodeType, unsigned /*Op0*/,
502 unsigned FastISel::FastEmit_rf(MVT::SimpleValueType, MVT::SimpleValueType,
503 ISD::NodeType, unsigned /*Op0*/,
504 ConstantFP * /*FPImm*/) {
508 unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, MVT::SimpleValueType,
510 unsigned /*Op0*/, unsigned /*Op1*/,
515 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
516 /// to emit an instruction with an immediate operand using FastEmit_ri.
517 /// If that fails, it materializes the immediate into a register and try
518 /// FastEmit_rr instead.
519 unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
520 unsigned Op0, uint64_t Imm,
521 MVT::SimpleValueType ImmType) {
522 // First check if immediate type is legal. If not, we can't use the ri form.
523 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm);
526 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
527 if (MaterialReg == 0)
529 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
532 /// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries
533 /// to emit an instruction with a floating-point immediate operand using
534 /// FastEmit_rf. If that fails, it materializes the immediate into a register
535 /// and try FastEmit_rr instead.
536 unsigned FastISel::FastEmit_rf_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
537 unsigned Op0, ConstantFP *FPImm,
538 MVT::SimpleValueType ImmType) {
539 // First check if immediate type is legal. If not, we can't use the rf form.
540 unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm);
544 // Materialize the constant in a register.
545 unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm);
546 if (MaterialReg == 0) {
547 // If the target doesn't have a way to directly enter a floating-point
548 // value into a register, use an alternate approach.
549 // TODO: The current approach only supports floating-point constants
550 // that can be constructed by conversion from integer values. This should
551 // be replaced by code that creates a load from a constant-pool entry,
552 // which will require some target-specific work.
553 const APFloat &Flt = FPImm->getValueAPF();
554 MVT IntVT = TLI.getPointerTy();
557 uint32_t IntBitWidth = IntVT.getSizeInBits();
558 if (Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
559 APFloat::rmTowardZero) != APFloat::opOK)
561 APInt IntVal(IntBitWidth, 2, x);
563 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
564 ISD::Constant, IntVal.getZExtValue());
567 MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT,
568 ISD::SINT_TO_FP, IntegerReg);
569 if (MaterialReg == 0)
572 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
575 unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
576 return MRI.createVirtualRegister(RC);
579 unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
580 const TargetRegisterClass* RC) {
581 unsigned ResultReg = createResultReg(RC);
582 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
584 BuildMI(MBB, II, ResultReg);
588 unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
589 const TargetRegisterClass *RC,
591 unsigned ResultReg = createResultReg(RC);
592 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
594 if (II.getNumDefs() >= 1)
595 BuildMI(MBB, II, ResultReg).addReg(Op0);
597 BuildMI(MBB, II).addReg(Op0);
598 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
599 II.ImplicitDefs[0], RC, RC);
607 unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
608 const TargetRegisterClass *RC,
609 unsigned Op0, unsigned Op1) {
610 unsigned ResultReg = createResultReg(RC);
611 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
613 if (II.getNumDefs() >= 1)
614 BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1);
616 BuildMI(MBB, II).addReg(Op0).addReg(Op1);
617 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
618 II.ImplicitDefs[0], RC, RC);
625 unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
626 const TargetRegisterClass *RC,
627 unsigned Op0, uint64_t Imm) {
628 unsigned ResultReg = createResultReg(RC);
629 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
631 if (II.getNumDefs() >= 1)
632 BuildMI(MBB, II, ResultReg).addReg(Op0).addImm(Imm);
634 BuildMI(MBB, II).addReg(Op0).addImm(Imm);
635 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
636 II.ImplicitDefs[0], RC, RC);
643 unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
644 const TargetRegisterClass *RC,
645 unsigned Op0, ConstantFP *FPImm) {
646 unsigned ResultReg = createResultReg(RC);
647 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
649 if (II.getNumDefs() >= 1)
650 BuildMI(MBB, II, ResultReg).addReg(Op0).addFPImm(FPImm);
652 BuildMI(MBB, II).addReg(Op0).addFPImm(FPImm);
653 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
654 II.ImplicitDefs[0], RC, RC);
661 unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
662 const TargetRegisterClass *RC,
663 unsigned Op0, unsigned Op1, uint64_t Imm) {
664 unsigned ResultReg = createResultReg(RC);
665 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
667 if (II.getNumDefs() >= 1)
668 BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm);
670 BuildMI(MBB, II).addReg(Op0).addReg(Op1).addImm(Imm);
671 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
672 II.ImplicitDefs[0], RC, RC);
679 unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
680 const TargetRegisterClass *RC,
682 unsigned ResultReg = createResultReg(RC);
683 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
685 if (II.getNumDefs() >= 1)
686 BuildMI(MBB, II, ResultReg).addImm(Imm);
688 BuildMI(MBB, II).addImm(Imm);
689 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
690 II.ImplicitDefs[0], RC, RC);
697 unsigned FastISel::FastEmitInst_extractsubreg(unsigned Op0, uint32_t Idx) {
698 const TargetRegisterClass* RC = MRI.getRegClass(Op0);
699 const TargetRegisterClass* SRC = *(RC->subregclasses_begin()+Idx-1);
701 unsigned ResultReg = createResultReg(SRC);
702 const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG);
704 if (II.getNumDefs() >= 1)
705 BuildMI(MBB, II, ResultReg).addReg(Op0).addImm(Idx);
707 BuildMI(MBB, II).addReg(Op0).addImm(Idx);
708 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
709 II.ImplicitDefs[0], RC, RC);