1 ///===-- FastISel.cpp - Implementation of the FastISel class --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the implementation of the FastISel class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Instructions.h"
15 #include "llvm/CodeGen/FastISel.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/Target/TargetData.h"
19 #include "llvm/Target/TargetInstrInfo.h"
20 #include "llvm/Target/TargetLowering.h"
21 #include "llvm/Target/TargetMachine.h"
24 /// SelectBinaryOp - Select and emit code for a binary operator instruction,
25 /// which has an opcode which directly corresponds to the given ISD opcode.
27 bool FastISel::SelectBinaryOp(Instruction *I, ISD::NodeType ISDOpcode,
28 DenseMap<const Value*, unsigned> &ValueMap) {
29 MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
30 if (VT == MVT::Other || !VT.isSimple())
31 // Unhandled type. Halt "fast" selection and bail.
34 unsigned Op0 = ValueMap[I->getOperand(0)];
36 // Unhandled operand. Halt "fast" selection and bail.
39 // Check if the second operand is a constant and handle it appropriately.
40 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
41 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0,
42 CI->getZExtValue(), VT.getSimpleVT());
44 // Target-specific code wasn't able to find a machine opcode for
45 // the given ISD opcode and type. Halt "fast" selection and bail.
48 // We successfully emitted code for the given LLVM Instruction.
49 ValueMap[I] = ResultReg;
53 unsigned Op1 = ValueMap[I->getOperand(1)];
55 // Unhandled operand. Halt "fast" selection and bail.
58 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), ISDOpcode, Op0, Op1);
60 // Target-specific code wasn't able to find a machine opcode for
61 // the given ISD opcode and type. Halt "fast" selection and bail.
64 // We successfully emitted code for the given LLVM Instruction.
65 ValueMap[I] = ResultReg;
69 bool FastISel::SelectGetElementPtr(Instruction *I,
70 DenseMap<const Value*, unsigned> &ValueMap) {
71 unsigned N = ValueMap[I->getOperand(0)];
73 // Unhandled operand. Halt "fast" selection and bail.
76 const Type *Ty = I->getOperand(0)->getType();
77 MVT::SimpleValueType VT = TLI.getPointerTy().getSimpleVT();
78 for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end();
81 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
82 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
85 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field);
86 // FIXME: This can be optimized by combining the add with a
88 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
90 // Unhandled operand. Halt "fast" selection and bail.
93 Ty = StTy->getElementType(Field);
95 Ty = cast<SequentialType>(Ty)->getElementType();
97 // If this is a constant subscript, handle it quickly.
98 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
99 if (CI->getZExtValue() == 0) continue;
101 TD.getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
102 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
104 // Unhandled operand. Halt "fast" selection and bail.
109 // N = N + Idx * ElementSize;
110 uint64_t ElementSize = TD.getABITypeSize(Ty);
111 unsigned IdxN = ValueMap[Idx];
113 // Unhandled operand. Halt "fast" selection and bail.
116 // If the index is smaller or larger than intptr_t, truncate or extend
118 MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false);
119 if (IdxVT.bitsLT(VT))
120 IdxN = FastEmit_r(VT, ISD::SIGN_EXTEND, IdxN);
121 else if (IdxVT.bitsGT(VT))
122 IdxN = FastEmit_r(VT, ISD::TRUNCATE, IdxN);
124 // Unhandled operand. Halt "fast" selection and bail.
127 if (ElementSize != 1)
128 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT);
130 // Unhandled operand. Halt "fast" selection and bail.
132 N = FastEmit_rr(VT, ISD::ADD, N, IdxN);
134 // Unhandled operand. Halt "fast" selection and bail.
139 // We successfully emitted code for the given LLVM Instruction.
145 FastISel::SelectInstructions(BasicBlock::iterator Begin,
146 BasicBlock::iterator End,
147 DenseMap<const Value*, unsigned> &ValueMap,
148 std::map<const BasicBlock*,
149 MachineBasicBlock *> &MBBMap,
150 MachineBasicBlock *mbb) {
152 BasicBlock::iterator I = Begin;
154 for (; I != End; ++I) {
155 switch (I->getOpcode()) {
156 case Instruction::Add: {
157 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FADD : ISD::ADD;
158 if (!SelectBinaryOp(I, Opc, ValueMap)) return I; break;
160 case Instruction::Sub: {
161 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FSUB : ISD::SUB;
162 if (!SelectBinaryOp(I, Opc, ValueMap)) return I; break;
164 case Instruction::Mul: {
165 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FMUL : ISD::MUL;
166 if (!SelectBinaryOp(I, Opc, ValueMap)) return I; break;
168 case Instruction::SDiv:
169 if (!SelectBinaryOp(I, ISD::SDIV, ValueMap)) return I; break;
170 case Instruction::UDiv:
171 if (!SelectBinaryOp(I, ISD::UDIV, ValueMap)) return I; break;
172 case Instruction::FDiv:
173 if (!SelectBinaryOp(I, ISD::FDIV, ValueMap)) return I; break;
174 case Instruction::SRem:
175 if (!SelectBinaryOp(I, ISD::SREM, ValueMap)) return I; break;
176 case Instruction::URem:
177 if (!SelectBinaryOp(I, ISD::UREM, ValueMap)) return I; break;
178 case Instruction::FRem:
179 if (!SelectBinaryOp(I, ISD::FREM, ValueMap)) return I; break;
180 case Instruction::Shl:
181 if (!SelectBinaryOp(I, ISD::SHL, ValueMap)) return I; break;
182 case Instruction::LShr:
183 if (!SelectBinaryOp(I, ISD::SRL, ValueMap)) return I; break;
184 case Instruction::AShr:
185 if (!SelectBinaryOp(I, ISD::SRA, ValueMap)) return I; break;
186 case Instruction::And:
187 if (!SelectBinaryOp(I, ISD::AND, ValueMap)) return I; break;
188 case Instruction::Or:
189 if (!SelectBinaryOp(I, ISD::OR, ValueMap)) return I; break;
190 case Instruction::Xor:
191 if (!SelectBinaryOp(I, ISD::XOR, ValueMap)) return I; break;
193 case Instruction::GetElementPtr:
194 if (!SelectGetElementPtr(I, ValueMap)) return I;
197 case Instruction::Br: {
198 BranchInst *BI = cast<BranchInst>(I);
200 if (BI->isUnconditional()) {
201 MachineFunction::iterator NextMBB =
202 next(MachineFunction::iterator(MBB));
203 BasicBlock *LLVMSucc = BI->getSuccessor(0);
204 MachineBasicBlock *MSucc = MBBMap[LLVMSucc];
206 if (NextMBB != MF.end() && MSucc == NextMBB) {
207 // The unconditional fall-through case, which needs no instructions.
209 // The unconditional branch case.
210 const SmallVector<MachineOperand, 0> NoCond(0);
211 TII.InsertBranch(*MBB, MSucc, NULL, NoCond);
213 MBB->addSuccessor(MSucc);
217 // Conditional branches are not handed yet.
218 // Halt "fast" selection and bail.
222 case Instruction::PHI:
223 // PHI nodes are already emitted.
227 // Unhandled instruction. Halt "fast" selection and bail.
235 FastISel::FastISel(MachineFunction &mf)
237 MRI(mf.getRegInfo()),
239 TD(*TM.getTargetData()),
240 TII(*TM.getInstrInfo()),
241 TLI(*TM.getTargetLowering()) {
244 FastISel::~FastISel() {}
246 unsigned FastISel::FastEmit_(MVT::SimpleValueType, ISD::NodeType) {
250 unsigned FastISel::FastEmit_r(MVT::SimpleValueType, ISD::NodeType,
255 unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, ISD::NodeType,
256 unsigned /*Op0*/, unsigned /*Op0*/) {
260 unsigned FastISel::FastEmit_i(MVT::SimpleValueType, uint64_t /*Imm*/) {
264 unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, ISD::NodeType,
265 unsigned /*Op0*/, uint64_t /*Imm*/) {
269 unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, ISD::NodeType,
270 unsigned /*Op0*/, unsigned /*Op1*/,
275 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
276 /// to emit an instruction with an immediate operand using FastEmit_ri.
277 /// If that fails, it materializes the immediate into a register and try
278 /// FastEmit_rr instead.
279 unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
280 unsigned Op0, uint64_t Imm,
281 MVT::SimpleValueType ImmType) {
282 unsigned ResultReg = 0;
283 // First check if immediate type is legal. If not, we can't use the ri form.
284 if (TLI.getOperationAction(ISD::Constant, ImmType) == TargetLowering::Legal)
285 ResultReg = FastEmit_ri(VT, Opcode, Op0, Imm);
288 unsigned MaterialReg = FastEmit_i(ImmType, Imm);
289 if (MaterialReg == 0)
291 return FastEmit_rr(VT, Opcode, Op0, MaterialReg);
294 unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
295 return MRI.createVirtualRegister(RC);
298 unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
299 const TargetRegisterClass* RC) {
300 unsigned ResultReg = createResultReg(RC);
301 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
303 BuildMI(MBB, II, ResultReg);
307 unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
308 const TargetRegisterClass *RC,
310 unsigned ResultReg = createResultReg(RC);
311 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
313 BuildMI(MBB, II, ResultReg).addReg(Op0);
317 unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
318 const TargetRegisterClass *RC,
319 unsigned Op0, unsigned Op1) {
320 unsigned ResultReg = createResultReg(RC);
321 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
323 BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1);
327 unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
328 const TargetRegisterClass *RC,
329 unsigned Op0, uint64_t Imm) {
330 unsigned ResultReg = createResultReg(RC);
331 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
333 BuildMI(MBB, II, ResultReg).addReg(Op0).addImm(Imm);
337 unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
338 const TargetRegisterClass *RC,
339 unsigned Op0, unsigned Op1, uint64_t Imm) {
340 unsigned ResultReg = createResultReg(RC);
341 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
343 BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm);