1 ///===-- FastISel.cpp - Implementation of the FastISel class --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the implementation of the FastISel class.
12 // "Fast" instruction selection is designed to emit very poor code quickly.
13 // Also, it is not designed to be able to do much lowering, so most illegal
14 // types (e.g. i64 on 32-bit targets) and operations are not supported. It is
15 // also not intended to be able to do much optimization, except in a few cases
16 // where doing optimizations reduces overall compile time. For example, folding
17 // constants into immediate fields is often done, because it's cheap and it
18 // reduces the number of instructions later phases have to examine.
20 // "Fast" instruction selection is able to fail gracefully and transfer
21 // control to the SelectionDAG selector for operations that it doesn't
22 // support. In many cases, this allows us to avoid duplicating a lot of
23 // the complicated lowering logic that SelectionDAG currently has.
25 // The intended use for "fast" instruction selection is "-O0" mode
26 // compilation, where the quality of the generated code is irrelevant when
27 // weighed against the speed at which the code can be generated. Also,
28 // at -O0, the LLVM optimizers are not running, and this makes the
29 // compile time of codegen a much higher portion of the overall compile
30 // time. Despite its limitations, "fast" instruction selection is able to
31 // handle enough code on its own to provide noticeable overall speedups
34 // Basic operations are supported in a target-independent way, by reading
35 // the same instruction descriptions that the SelectionDAG selector reads,
36 // and identifying simple arithmetic operations that can be directly selected
37 // from simple operators. More complicated operations currently require
38 // target-specific code.
40 //===----------------------------------------------------------------------===//
42 #include "llvm/Function.h"
43 #include "llvm/GlobalVariable.h"
44 #include "llvm/Instructions.h"
45 #include "llvm/IntrinsicInst.h"
46 #include "llvm/CodeGen/FastISel.h"
47 #include "llvm/CodeGen/MachineInstrBuilder.h"
48 #include "llvm/CodeGen/MachineModuleInfo.h"
49 #include "llvm/CodeGen/MachineRegisterInfo.h"
50 #include "llvm/CodeGen/DwarfWriter.h"
51 #include "llvm/Analysis/DebugInfo.h"
52 #include "llvm/Target/TargetData.h"
53 #include "llvm/Target/TargetInstrInfo.h"
54 #include "llvm/Target/TargetLowering.h"
55 #include "llvm/Target/TargetMachine.h"
56 #include "SelectionDAGBuild.h"
59 unsigned FastISel::getRegForValue(Value *V) {
60 MVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true);
61 // Don't handle non-simple values in FastISel.
62 if (!RealVT.isSimple())
65 // Ignore illegal types. We must do this before looking up the value
66 // in ValueMap because Arguments are given virtual registers regardless
67 // of whether FastISel can handle them.
68 MVT::SimpleValueType VT = RealVT.getSimpleVT();
69 if (!TLI.isTypeLegal(VT)) {
70 // Promote MVT::i1 to a legal type though, because it's common and easy.
72 VT = TLI.getTypeToTransformTo(VT).getSimpleVT();
77 // Look up the value to see if we already have a register for it. We
78 // cache values defined by Instructions across blocks, and other values
79 // only locally. This is because Instructions already have the SSA
80 // def-dominatess-use requirement enforced.
81 if (ValueMap.count(V))
83 unsigned Reg = LocalValueMap[V];
87 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
88 if (CI->getValue().getActiveBits() <= 64)
89 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
90 } else if (isa<AllocaInst>(V)) {
91 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V));
92 } else if (isa<ConstantPointerNull>(V)) {
93 // Translate this as an integer zero so that it can be
94 // local-CSE'd with actual integer zeros.
95 Reg = getRegForValue(V->getContext().getNullValue(TD.getIntPtrType()));
96 } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
97 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
100 const APFloat &Flt = CF->getValueAPF();
101 MVT IntVT = TLI.getPointerTy();
104 uint32_t IntBitWidth = IntVT.getSizeInBits();
106 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
107 APFloat::rmTowardZero, &isExact);
109 APInt IntVal(IntBitWidth, 2, x);
111 unsigned IntegerReg =
112 getRegForValue(V->getContext().getConstantInt(IntVal));
114 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg);
117 } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) {
118 if (!SelectOperator(CE, CE->getOpcode())) return 0;
119 Reg = LocalValueMap[CE];
120 } else if (isa<UndefValue>(V)) {
121 Reg = createResultReg(TLI.getRegClassFor(VT));
122 BuildMI(MBB, DL, TII.get(TargetInstrInfo::IMPLICIT_DEF), Reg);
125 // If target-independent code couldn't handle the value, give target-specific
127 if (!Reg && isa<Constant>(V))
128 Reg = TargetMaterializeConstant(cast<Constant>(V));
130 // Don't cache constant materializations in the general ValueMap.
131 // To do so would require tracking what uses they dominate.
133 LocalValueMap[V] = Reg;
137 unsigned FastISel::lookUpRegForValue(Value *V) {
138 // Look up the value to see if we already have a register for it. We
139 // cache values defined by Instructions across blocks, and other values
140 // only locally. This is because Instructions already have the SSA
141 // def-dominatess-use requirement enforced.
142 if (ValueMap.count(V))
144 return LocalValueMap[V];
147 /// UpdateValueMap - Update the value map to include the new mapping for this
148 /// instruction, or insert an extra copy to get the result in a previous
149 /// determined register.
150 /// NOTE: This is only necessary because we might select a block that uses
151 /// a value before we select the block that defines the value. It might be
152 /// possible to fix this by selecting blocks in reverse postorder.
153 unsigned FastISel::UpdateValueMap(Value* I, unsigned Reg) {
154 if (!isa<Instruction>(I)) {
155 LocalValueMap[I] = Reg;
159 unsigned &AssignedReg = ValueMap[I];
160 if (AssignedReg == 0)
162 else if (Reg != AssignedReg) {
163 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg);
164 TII.copyRegToReg(*MBB, MBB->end(), AssignedReg,
165 Reg, RegClass, RegClass);
170 unsigned FastISel::getRegForGEPIndex(Value *Idx) {
171 unsigned IdxN = getRegForValue(Idx);
173 // Unhandled operand. Halt "fast" selection and bail.
176 // If the index is smaller or larger than intptr_t, truncate or extend it.
177 MVT PtrVT = TLI.getPointerTy();
178 MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false);
179 if (IdxVT.bitsLT(PtrVT))
180 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(),
181 ISD::SIGN_EXTEND, IdxN);
182 else if (IdxVT.bitsGT(PtrVT))
183 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(),
184 ISD::TRUNCATE, IdxN);
188 /// SelectBinaryOp - Select and emit code for a binary operator instruction,
189 /// which has an opcode which directly corresponds to the given ISD opcode.
191 bool FastISel::SelectBinaryOp(User *I, ISD::NodeType ISDOpcode) {
192 MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
193 if (VT == MVT::Other || !VT.isSimple())
194 // Unhandled type. Halt "fast" selection and bail.
197 // We only handle legal types. For example, on x86-32 the instruction
198 // selector contains all of the 64-bit instructions from x86-64,
199 // under the assumption that i64 won't be used if the target doesn't
201 if (!TLI.isTypeLegal(VT)) {
202 // MVT::i1 is special. Allow AND, OR, or XOR because they
203 // don't require additional zeroing, which makes them easy.
205 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
206 ISDOpcode == ISD::XOR))
207 VT = TLI.getTypeToTransformTo(VT);
212 unsigned Op0 = getRegForValue(I->getOperand(0));
214 // Unhandled operand. Halt "fast" selection and bail.
217 // Check if the second operand is a constant and handle it appropriately.
218 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
219 unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(),
220 ISDOpcode, Op0, CI->getZExtValue());
221 if (ResultReg != 0) {
222 // We successfully emitted code for the given LLVM Instruction.
223 UpdateValueMap(I, ResultReg);
228 // Check if the second operand is a constant float.
229 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
230 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
232 if (ResultReg != 0) {
233 // We successfully emitted code for the given LLVM Instruction.
234 UpdateValueMap(I, ResultReg);
239 unsigned Op1 = getRegForValue(I->getOperand(1));
241 // Unhandled operand. Halt "fast" selection and bail.
244 // Now we have both operands in registers. Emit the instruction.
245 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
246 ISDOpcode, Op0, Op1);
248 // Target-specific code wasn't able to find a machine opcode for
249 // the given ISD opcode and type. Halt "fast" selection and bail.
252 // We successfully emitted code for the given LLVM Instruction.
253 UpdateValueMap(I, ResultReg);
257 bool FastISel::SelectGetElementPtr(User *I) {
258 unsigned N = getRegForValue(I->getOperand(0));
260 // Unhandled operand. Halt "fast" selection and bail.
263 const Type *Ty = I->getOperand(0)->getType();
264 MVT::SimpleValueType VT = TLI.getPointerTy().getSimpleVT();
265 for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end();
268 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
269 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
272 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field);
273 // FIXME: This can be optimized by combining the add with a
275 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
277 // Unhandled operand. Halt "fast" selection and bail.
280 Ty = StTy->getElementType(Field);
282 Ty = cast<SequentialType>(Ty)->getElementType();
284 // If this is a constant subscript, handle it quickly.
285 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
286 if (CI->getZExtValue() == 0) continue;
288 TD.getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
289 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
291 // Unhandled operand. Halt "fast" selection and bail.
296 // N = N + Idx * ElementSize;
297 uint64_t ElementSize = TD.getTypeAllocSize(Ty);
298 unsigned IdxN = getRegForGEPIndex(Idx);
300 // Unhandled operand. Halt "fast" selection and bail.
303 if (ElementSize != 1) {
304 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT);
306 // Unhandled operand. Halt "fast" selection and bail.
309 N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN);
311 // Unhandled operand. Halt "fast" selection and bail.
316 // We successfully emitted code for the given LLVM Instruction.
317 UpdateValueMap(I, N);
321 bool FastISel::SelectCall(User *I) {
322 Function *F = cast<CallInst>(I)->getCalledFunction();
323 if (!F) return false;
325 unsigned IID = F->getIntrinsicID();
328 case Intrinsic::dbg_stoppoint: {
329 DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
330 if (isValidDebugInfoIntrinsic(*SPI, CodeGenOpt::None))
331 setCurDebugLoc(ExtractDebugLocation(*SPI, MF.getDebugLocInfo()));
334 case Intrinsic::dbg_region_start: {
335 DbgRegionStartInst *RSI = cast<DbgRegionStartInst>(I);
336 if (isValidDebugInfoIntrinsic(*RSI, CodeGenOpt::None) && DW
337 && DW->ShouldEmitDwarfDebug()) {
339 DW->RecordRegionStart(cast<GlobalVariable>(RSI->getContext()));
340 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
341 BuildMI(MBB, DL, II).addImm(ID);
345 case Intrinsic::dbg_region_end: {
346 DbgRegionEndInst *REI = cast<DbgRegionEndInst>(I);
347 if (isValidDebugInfoIntrinsic(*REI, CodeGenOpt::None) && DW
348 && DW->ShouldEmitDwarfDebug()) {
350 DISubprogram Subprogram(cast<GlobalVariable>(REI->getContext()));
351 if (isInlinedFnEnd(*REI, MF.getFunction())) {
352 // This is end of an inlined function.
353 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
354 ID = DW->RecordInlinedFnEnd(Subprogram);
356 // Returned ID is 0 if this is unbalanced "end of inlined
357 // scope". This could happen if optimizer eats dbg intrinsics
358 // or "beginning of inlined scope" is not recoginized due to
359 // missing location info. In such cases, ignore this region.end.
360 BuildMI(MBB, DL, II).addImm(ID);
362 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
363 ID = DW->RecordRegionEnd(cast<GlobalVariable>(REI->getContext()));
364 BuildMI(MBB, DL, II).addImm(ID);
369 case Intrinsic::dbg_func_start: {
370 DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
371 if (!isValidDebugInfoIntrinsic(*FSI, CodeGenOpt::None) || !DW
372 || !DW->ShouldEmitDwarfDebug())
375 if (isInlinedFnStart(*FSI, MF.getFunction())) {
376 // This is a beginning of an inlined function.
378 // If llvm.dbg.func.start is seen in a new block before any
379 // llvm.dbg.stoppoint intrinsic then the location info is unknown.
380 // FIXME : Why DebugLoc is reset at the beginning of each block ?
381 DebugLoc PrevLoc = DL;
382 if (PrevLoc.isUnknown())
384 // Record the source line.
385 setCurDebugLoc(ExtractDebugLocation(*FSI, MF.getDebugLocInfo()));
387 DebugLocTuple PrevLocTpl = MF.getDebugLocTuple(PrevLoc);
388 DISubprogram SP(cast<GlobalVariable>(FSI->getSubprogram()));
389 unsigned LabelID = DW->RecordInlinedFnStart(SP,
390 DICompileUnit(PrevLocTpl.CompileUnit),
393 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
394 BuildMI(MBB, DL, II).addImm(LabelID);
398 // This is a beginning of a new function.
399 MF.setDefaultDebugLoc(ExtractDebugLocation(*FSI, MF.getDebugLocInfo()));
401 // llvm.dbg.func_start also defines beginning of function scope.
402 DW->RecordRegionStart(cast<GlobalVariable>(FSI->getSubprogram()));
405 case Intrinsic::dbg_declare: {
406 DbgDeclareInst *DI = cast<DbgDeclareInst>(I);
407 if (!isValidDebugInfoIntrinsic(*DI, CodeGenOpt::None) || !DW
408 || !DW->ShouldEmitDwarfDebug())
411 Value *Variable = DI->getVariable();
412 Value *Address = DI->getAddress();
413 if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
414 Address = BCI->getOperand(0);
415 AllocaInst *AI = dyn_cast<AllocaInst>(Address);
416 // Don't handle byval struct arguments or VLAs, for example.
418 DenseMap<const AllocaInst*, int>::iterator SI =
419 StaticAllocaMap.find(AI);
420 if (SI == StaticAllocaMap.end()) break; // VLAs.
423 // Determine the debug globalvariable.
424 GlobalValue *GV = cast<GlobalVariable>(Variable);
426 // Build the DECLARE instruction.
427 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DECLARE);
428 MachineInstr *DeclareMI
429 = BuildMI(MBB, DL, II).addFrameIndex(FI).addGlobalAddress(GV);
430 DIVariable DV(cast<GlobalVariable>(GV));
431 DW->RecordVariableScope(DV, DeclareMI);
434 case Intrinsic::eh_exception: {
435 MVT VT = TLI.getValueType(I->getType());
436 switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) {
438 case TargetLowering::Expand: {
439 assert(MBB->isLandingPad() && "Call to eh.exception not in landing pad!");
440 unsigned Reg = TLI.getExceptionAddressRegister();
441 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
442 unsigned ResultReg = createResultReg(RC);
443 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
445 assert(InsertedCopy && "Can't copy address registers!");
446 InsertedCopy = InsertedCopy;
447 UpdateValueMap(I, ResultReg);
453 case Intrinsic::eh_selector_i32:
454 case Intrinsic::eh_selector_i64: {
455 MVT VT = TLI.getValueType(I->getType());
456 switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) {
458 case TargetLowering::Expand: {
459 MVT VT = (IID == Intrinsic::eh_selector_i32 ?
460 MVT::i32 : MVT::i64);
463 if (MBB->isLandingPad())
464 AddCatchInfo(*cast<CallInst>(I), MMI, MBB);
467 CatchInfoLost.insert(cast<CallInst>(I));
469 // FIXME: Mark exception selector register as live in. Hack for PR1508.
470 unsigned Reg = TLI.getExceptionSelectorRegister();
471 if (Reg) MBB->addLiveIn(Reg);
474 unsigned Reg = TLI.getExceptionSelectorRegister();
475 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
476 unsigned ResultReg = createResultReg(RC);
477 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
479 assert(InsertedCopy && "Can't copy address registers!");
480 InsertedCopy = InsertedCopy;
481 UpdateValueMap(I, ResultReg);
484 getRegForValue(I->getContext().getNullValue(I->getType()));
485 UpdateValueMap(I, ResultReg);
496 bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) {
497 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
498 MVT DstVT = TLI.getValueType(I->getType());
500 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
501 DstVT == MVT::Other || !DstVT.isSimple())
502 // Unhandled type. Halt "fast" selection and bail.
505 // Check if the destination type is legal. Or as a special case,
506 // it may be i1 if we're doing a truncate because that's
507 // easy and somewhat common.
508 if (!TLI.isTypeLegal(DstVT))
509 if (DstVT != MVT::i1 || Opcode != ISD::TRUNCATE)
510 // Unhandled type. Halt "fast" selection and bail.
513 // Check if the source operand is legal. Or as a special case,
514 // it may be i1 if we're doing zero-extension because that's
515 // easy and somewhat common.
516 if (!TLI.isTypeLegal(SrcVT))
517 if (SrcVT != MVT::i1 || Opcode != ISD::ZERO_EXTEND)
518 // Unhandled type. Halt "fast" selection and bail.
521 unsigned InputReg = getRegForValue(I->getOperand(0));
523 // Unhandled operand. Halt "fast" selection and bail.
526 // If the operand is i1, arrange for the high bits in the register to be zero.
527 if (SrcVT == MVT::i1) {
528 SrcVT = TLI.getTypeToTransformTo(SrcVT);
529 InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg);
533 // If the result is i1, truncate to the target's type for i1 first.
534 if (DstVT == MVT::i1)
535 DstVT = TLI.getTypeToTransformTo(DstVT);
537 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
544 UpdateValueMap(I, ResultReg);
548 bool FastISel::SelectBitCast(User *I) {
549 // If the bitcast doesn't change the type, just use the operand value.
550 if (I->getType() == I->getOperand(0)->getType()) {
551 unsigned Reg = getRegForValue(I->getOperand(0));
554 UpdateValueMap(I, Reg);
558 // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators.
559 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
560 MVT DstVT = TLI.getValueType(I->getType());
562 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
563 DstVT == MVT::Other || !DstVT.isSimple() ||
564 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
565 // Unhandled type. Halt "fast" selection and bail.
568 unsigned Op0 = getRegForValue(I->getOperand(0));
570 // Unhandled operand. Halt "fast" selection and bail.
573 // First, try to perform the bitcast by inserting a reg-reg copy.
574 unsigned ResultReg = 0;
575 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
576 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
577 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
578 ResultReg = createResultReg(DstClass);
580 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
581 Op0, DstClass, SrcClass);
586 // If the reg-reg copy failed, select a BIT_CONVERT opcode.
588 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
589 ISD::BIT_CONVERT, Op0);
594 UpdateValueMap(I, ResultReg);
599 FastISel::SelectInstruction(Instruction *I) {
600 return SelectOperator(I, I->getOpcode());
603 /// FastEmitBranch - Emit an unconditional branch to the given block,
604 /// unless it is the immediate (fall-through) successor, and update
607 FastISel::FastEmitBranch(MachineBasicBlock *MSucc) {
608 MachineFunction::iterator NextMBB =
609 next(MachineFunction::iterator(MBB));
611 if (MBB->isLayoutSuccessor(MSucc)) {
612 // The unconditional fall-through case, which needs no instructions.
614 // The unconditional branch case.
615 TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>());
617 MBB->addSuccessor(MSucc);
621 FastISel::SelectOperator(User *I, unsigned Opcode) {
623 case Instruction::Add:
624 return SelectBinaryOp(I, ISD::ADD);
625 case Instruction::FAdd:
626 return SelectBinaryOp(I, ISD::FADD);
627 case Instruction::Sub:
628 return SelectBinaryOp(I, ISD::SUB);
629 case Instruction::FSub:
630 return SelectBinaryOp(I, ISD::FSUB);
631 case Instruction::Mul:
632 return SelectBinaryOp(I, ISD::MUL);
633 case Instruction::FMul:
634 return SelectBinaryOp(I, ISD::FMUL);
635 case Instruction::SDiv:
636 return SelectBinaryOp(I, ISD::SDIV);
637 case Instruction::UDiv:
638 return SelectBinaryOp(I, ISD::UDIV);
639 case Instruction::FDiv:
640 return SelectBinaryOp(I, ISD::FDIV);
641 case Instruction::SRem:
642 return SelectBinaryOp(I, ISD::SREM);
643 case Instruction::URem:
644 return SelectBinaryOp(I, ISD::UREM);
645 case Instruction::FRem:
646 return SelectBinaryOp(I, ISD::FREM);
647 case Instruction::Shl:
648 return SelectBinaryOp(I, ISD::SHL);
649 case Instruction::LShr:
650 return SelectBinaryOp(I, ISD::SRL);
651 case Instruction::AShr:
652 return SelectBinaryOp(I, ISD::SRA);
653 case Instruction::And:
654 return SelectBinaryOp(I, ISD::AND);
655 case Instruction::Or:
656 return SelectBinaryOp(I, ISD::OR);
657 case Instruction::Xor:
658 return SelectBinaryOp(I, ISD::XOR);
660 case Instruction::GetElementPtr:
661 return SelectGetElementPtr(I);
663 case Instruction::Br: {
664 BranchInst *BI = cast<BranchInst>(I);
666 if (BI->isUnconditional()) {
667 BasicBlock *LLVMSucc = BI->getSuccessor(0);
668 MachineBasicBlock *MSucc = MBBMap[LLVMSucc];
669 FastEmitBranch(MSucc);
673 // Conditional branches are not handed yet.
674 // Halt "fast" selection and bail.
678 case Instruction::Unreachable:
682 case Instruction::PHI:
683 // PHI nodes are already emitted.
686 case Instruction::Alloca:
687 // FunctionLowering has the static-sized case covered.
688 if (StaticAllocaMap.count(cast<AllocaInst>(I)))
691 // Dynamic-sized alloca is not handled yet.
694 case Instruction::Call:
695 return SelectCall(I);
697 case Instruction::BitCast:
698 return SelectBitCast(I);
700 case Instruction::FPToSI:
701 return SelectCast(I, ISD::FP_TO_SINT);
702 case Instruction::ZExt:
703 return SelectCast(I, ISD::ZERO_EXTEND);
704 case Instruction::SExt:
705 return SelectCast(I, ISD::SIGN_EXTEND);
706 case Instruction::Trunc:
707 return SelectCast(I, ISD::TRUNCATE);
708 case Instruction::SIToFP:
709 return SelectCast(I, ISD::SINT_TO_FP);
711 case Instruction::IntToPtr: // Deliberate fall-through.
712 case Instruction::PtrToInt: {
713 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
714 MVT DstVT = TLI.getValueType(I->getType());
715 if (DstVT.bitsGT(SrcVT))
716 return SelectCast(I, ISD::ZERO_EXTEND);
717 if (DstVT.bitsLT(SrcVT))
718 return SelectCast(I, ISD::TRUNCATE);
719 unsigned Reg = getRegForValue(I->getOperand(0));
720 if (Reg == 0) return false;
721 UpdateValueMap(I, Reg);
726 // Unhandled instruction. Halt "fast" selection and bail.
731 FastISel::FastISel(MachineFunction &mf,
732 MachineModuleInfo *mmi,
734 DenseMap<const Value *, unsigned> &vm,
735 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
736 DenseMap<const AllocaInst *, int> &am
738 , SmallSet<Instruction*, 8> &cil
751 MRI(MF.getRegInfo()),
752 MFI(*MF.getFrameInfo()),
753 MCP(*MF.getConstantPool()),
755 TD(*TM.getTargetData()),
756 TII(*TM.getInstrInfo()),
757 TLI(*TM.getTargetLowering()) {
760 FastISel::~FastISel() {}
762 unsigned FastISel::FastEmit_(MVT::SimpleValueType, MVT::SimpleValueType,
767 unsigned FastISel::FastEmit_r(MVT::SimpleValueType, MVT::SimpleValueType,
768 ISD::NodeType, unsigned /*Op0*/) {
772 unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, MVT::SimpleValueType,
773 ISD::NodeType, unsigned /*Op0*/,
778 unsigned FastISel::FastEmit_i(MVT::SimpleValueType, MVT::SimpleValueType,
779 ISD::NodeType, uint64_t /*Imm*/) {
783 unsigned FastISel::FastEmit_f(MVT::SimpleValueType, MVT::SimpleValueType,
784 ISD::NodeType, ConstantFP * /*FPImm*/) {
788 unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, MVT::SimpleValueType,
789 ISD::NodeType, unsigned /*Op0*/,
794 unsigned FastISel::FastEmit_rf(MVT::SimpleValueType, MVT::SimpleValueType,
795 ISD::NodeType, unsigned /*Op0*/,
796 ConstantFP * /*FPImm*/) {
800 unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, MVT::SimpleValueType,
802 unsigned /*Op0*/, unsigned /*Op1*/,
807 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
808 /// to emit an instruction with an immediate operand using FastEmit_ri.
809 /// If that fails, it materializes the immediate into a register and try
810 /// FastEmit_rr instead.
811 unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
812 unsigned Op0, uint64_t Imm,
813 MVT::SimpleValueType ImmType) {
814 // First check if immediate type is legal. If not, we can't use the ri form.
815 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm);
818 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
819 if (MaterialReg == 0)
821 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
824 /// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries
825 /// to emit an instruction with a floating-point immediate operand using
826 /// FastEmit_rf. If that fails, it materializes the immediate into a register
827 /// and try FastEmit_rr instead.
828 unsigned FastISel::FastEmit_rf_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
829 unsigned Op0, ConstantFP *FPImm,
830 MVT::SimpleValueType ImmType) {
831 // First check if immediate type is legal. If not, we can't use the rf form.
832 unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm);
836 // Materialize the constant in a register.
837 unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm);
838 if (MaterialReg == 0) {
839 // If the target doesn't have a way to directly enter a floating-point
840 // value into a register, use an alternate approach.
841 // TODO: The current approach only supports floating-point constants
842 // that can be constructed by conversion from integer values. This should
843 // be replaced by code that creates a load from a constant-pool entry,
844 // which will require some target-specific work.
845 const APFloat &Flt = FPImm->getValueAPF();
846 MVT IntVT = TLI.getPointerTy();
849 uint32_t IntBitWidth = IntVT.getSizeInBits();
851 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
852 APFloat::rmTowardZero, &isExact);
855 APInt IntVal(IntBitWidth, 2, x);
857 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
858 ISD::Constant, IntVal.getZExtValue());
861 MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT,
862 ISD::SINT_TO_FP, IntegerReg);
863 if (MaterialReg == 0)
866 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
869 unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
870 return MRI.createVirtualRegister(RC);
873 unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
874 const TargetRegisterClass* RC) {
875 unsigned ResultReg = createResultReg(RC);
876 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
878 BuildMI(MBB, DL, II, ResultReg);
882 unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
883 const TargetRegisterClass *RC,
885 unsigned ResultReg = createResultReg(RC);
886 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
888 if (II.getNumDefs() >= 1)
889 BuildMI(MBB, DL, II, ResultReg).addReg(Op0);
891 BuildMI(MBB, DL, II).addReg(Op0);
892 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
893 II.ImplicitDefs[0], RC, RC);
901 unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
902 const TargetRegisterClass *RC,
903 unsigned Op0, unsigned Op1) {
904 unsigned ResultReg = createResultReg(RC);
905 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
907 if (II.getNumDefs() >= 1)
908 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1);
910 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1);
911 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
912 II.ImplicitDefs[0], RC, RC);
919 unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
920 const TargetRegisterClass *RC,
921 unsigned Op0, uint64_t Imm) {
922 unsigned ResultReg = createResultReg(RC);
923 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
925 if (II.getNumDefs() >= 1)
926 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Imm);
928 BuildMI(MBB, DL, II).addReg(Op0).addImm(Imm);
929 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
930 II.ImplicitDefs[0], RC, RC);
937 unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
938 const TargetRegisterClass *RC,
939 unsigned Op0, ConstantFP *FPImm) {
940 unsigned ResultReg = createResultReg(RC);
941 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
943 if (II.getNumDefs() >= 1)
944 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addFPImm(FPImm);
946 BuildMI(MBB, DL, II).addReg(Op0).addFPImm(FPImm);
947 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
948 II.ImplicitDefs[0], RC, RC);
955 unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
956 const TargetRegisterClass *RC,
957 unsigned Op0, unsigned Op1, uint64_t Imm) {
958 unsigned ResultReg = createResultReg(RC);
959 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
961 if (II.getNumDefs() >= 1)
962 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm);
964 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1).addImm(Imm);
965 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
966 II.ImplicitDefs[0], RC, RC);
973 unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
974 const TargetRegisterClass *RC,
976 unsigned ResultReg = createResultReg(RC);
977 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
979 if (II.getNumDefs() >= 1)
980 BuildMI(MBB, DL, II, ResultReg).addImm(Imm);
982 BuildMI(MBB, DL, II).addImm(Imm);
983 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
984 II.ImplicitDefs[0], RC, RC);
991 unsigned FastISel::FastEmitInst_extractsubreg(MVT::SimpleValueType RetVT,
992 unsigned Op0, uint32_t Idx) {
993 const TargetRegisterClass* RC = MRI.getRegClass(Op0);
995 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
996 const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG);
998 if (II.getNumDefs() >= 1)
999 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Idx);
1001 BuildMI(MBB, DL, II).addReg(Op0).addImm(Idx);
1002 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1003 II.ImplicitDefs[0], RC, RC);
1010 /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
1011 /// with all but the least significant bit set to zero.
1012 unsigned FastISel::FastEmitZExtFromI1(MVT::SimpleValueType VT, unsigned Op) {
1013 return FastEmit_ri(VT, VT, ISD::AND, Op, 1);