1 ///===-- FastISel.cpp - Implementation of the FastISel class --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the implementation of the FastISel class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Instructions.h"
15 #include "llvm/CodeGen/FastISel.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/Target/TargetInstrInfo.h"
19 #include "llvm/Target/TargetMachine.h"
22 /// SelectBinaryOp - Select and emit code for a binary operator instruction,
23 /// which has an opcode which directly corresponds to the given ISD opcode.
25 bool FastISel::SelectBinaryOp(Instruction *I, ISD::NodeType ISDOpcode,
26 DenseMap<const Value*, unsigned> &ValueMap) {
27 unsigned Op0 = ValueMap[I->getOperand(0)];
28 unsigned Op1 = ValueMap[I->getOperand(1)];
29 if (Op0 == 0 || Op1 == 0)
30 // Unhandled operand. Halt "fast" selection and bail.
33 MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
34 if (VT == MVT::Other || !VT.isSimple())
35 // Unhandled type. Halt "fast" selection and bail.
38 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), ISDOpcode, Op0, Op1);
40 // Target-specific code wasn't able to find a machine opcode for
41 // the given ISD opcode and type. Halt "fast" selection and bail.
44 // We successfully emitted code for the given LLVM Instruction.
45 ValueMap[I] = ResultReg;
49 bool FastISel::SelectGetElementPtr(Instruction *I,
50 DenseMap<const Value*, unsigned> &ValueMap) {
56 FastISel::SelectInstructions(BasicBlock::iterator Begin,
57 BasicBlock::iterator End,
58 DenseMap<const Value*, unsigned> &ValueMap,
59 MachineBasicBlock *mbb) {
61 BasicBlock::iterator I = Begin;
63 for (; I != End; ++I) {
64 switch (I->getOpcode()) {
65 case Instruction::Add: {
66 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FADD : ISD::ADD;
67 if (!SelectBinaryOp(I, Opc, ValueMap)) return I; break;
69 case Instruction::Sub: {
70 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FSUB : ISD::SUB;
71 if (!SelectBinaryOp(I, Opc, ValueMap)) return I; break;
73 case Instruction::Mul: {
74 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FMUL : ISD::MUL;
75 if (!SelectBinaryOp(I, Opc, ValueMap)) return I; break;
77 case Instruction::SDiv:
78 if (!SelectBinaryOp(I, ISD::SDIV, ValueMap)) return I; break;
79 case Instruction::UDiv:
80 if (!SelectBinaryOp(I, ISD::UDIV, ValueMap)) return I; break;
81 case Instruction::FDiv:
82 if (!SelectBinaryOp(I, ISD::FDIV, ValueMap)) return I; break;
83 case Instruction::SRem:
84 if (!SelectBinaryOp(I, ISD::SREM, ValueMap)) return I; break;
85 case Instruction::URem:
86 if (!SelectBinaryOp(I, ISD::UREM, ValueMap)) return I; break;
87 case Instruction::FRem:
88 if (!SelectBinaryOp(I, ISD::FREM, ValueMap)) return I; break;
89 case Instruction::Shl:
90 if (!SelectBinaryOp(I, ISD::SHL, ValueMap)) return I; break;
91 case Instruction::LShr:
92 if (!SelectBinaryOp(I, ISD::SRL, ValueMap)) return I; break;
93 case Instruction::AShr:
94 if (!SelectBinaryOp(I, ISD::SRA, ValueMap)) return I; break;
95 case Instruction::And:
96 if (!SelectBinaryOp(I, ISD::AND, ValueMap)) return I; break;
98 if (!SelectBinaryOp(I, ISD::OR, ValueMap)) return I; break;
99 case Instruction::Xor:
100 if (!SelectBinaryOp(I, ISD::XOR, ValueMap)) return I; break;
102 case Instruction::GetElementPtr:
103 if (!SelectGetElementPtr(I, ValueMap)) return I;
106 case Instruction::Br: {
107 BranchInst *BI = cast<BranchInst>(I);
109 // For now, check for and handle just the most trivial case: an
110 // unconditional fall-through branch.
111 if (BI->isUnconditional()) {
112 MachineFunction::iterator NextMBB =
113 next(MachineFunction::iterator(MBB));
114 if (NextMBB != MF.end() &&
115 NextMBB->getBasicBlock() == BI->getSuccessor(0)) {
116 MBB->addSuccessor(NextMBB);
121 // Something more complicated. Halt "fast" selection and bail.
125 // Unhandled instruction. Halt "fast" selection and bail.
133 FastISel::FastISel(MachineFunction &mf)
134 : MF(mf), MRI(mf.getRegInfo()), TII(*mf.getTarget().getInstrInfo()) {
137 FastISel::~FastISel() {}
139 unsigned FastISel::FastEmit_(MVT::SimpleValueType, ISD::NodeType) {
143 unsigned FastISel::FastEmit_r(MVT::SimpleValueType, ISD::NodeType,
148 unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, ISD::NodeType,
149 unsigned /*Op0*/, unsigned /*Op0*/) {
153 unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
154 const TargetRegisterClass* RC) {
155 unsigned ResultReg = MRI.createVirtualRegister(RC);
156 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
158 MachineInstr *MI = BuildMI(MBB, II, ResultReg);
162 unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
163 const TargetRegisterClass *RC,
165 unsigned ResultReg = MRI.createVirtualRegister(RC);
166 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
168 MachineInstr *MI = BuildMI(MBB, II, ResultReg).addReg(Op0);
172 unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
173 const TargetRegisterClass *RC,
174 unsigned Op0, unsigned Op1) {
175 unsigned ResultReg = MRI.createVirtualRegister(RC);
176 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
178 MachineInstr *MI = BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1);