1 //===-- FunctionLoweringInfo.cpp ------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating functions from LLVM IR into
13 //===----------------------------------------------------------------------===//
15 #include "llvm/CodeGen/FunctionLoweringInfo.h"
16 #include "llvm/ADT/PostOrderIterator.h"
17 #include "llvm/CodeGen/Analysis.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/IR/DataLayout.h"
24 #include "llvm/IR/DebugInfo.h"
25 #include "llvm/IR/DerivedTypes.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/IR/Instructions.h"
28 #include "llvm/IR/IntrinsicInst.h"
29 #include "llvm/IR/LLVMContext.h"
30 #include "llvm/IR/Module.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/MathExtras.h"
34 #include "llvm/Target/TargetFrameLowering.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetLowering.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetSubtargetInfo.h"
43 #define DEBUG_TYPE "function-lowering-info"
45 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
46 /// PHI nodes or outside of the basic block that defines it, or used by a
47 /// switch or atomic instruction, which may expand to multiple basic blocks.
48 static bool isUsedOutsideOfDefiningBlock(const Instruction *I) {
49 if (I->use_empty()) return false;
50 if (isa<PHINode>(I)) return true;
51 const BasicBlock *BB = I->getParent();
52 for (const User *U : I->users())
53 if (cast<Instruction>(U)->getParent() != BB || isa<PHINode>(U))
59 static ISD::NodeType getPreferredExtendForValue(const Value *V) {
60 // For the users of the source value being used for compare instruction, if
61 // the number of signed predicate is greater than unsigned predicate, we
62 // prefer to use SIGN_EXTEND.
64 // With this optimization, we would be able to reduce some redundant sign or
65 // zero extension instruction, and eventually more machine CSE opportunities
67 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
68 unsigned NumOfSigned = 0, NumOfUnsigned = 0;
69 for (const User *U : V->users()) {
70 if (const auto *CI = dyn_cast<CmpInst>(U)) {
71 NumOfSigned += CI->isSigned();
72 NumOfUnsigned += CI->isUnsigned();
75 if (NumOfSigned > NumOfUnsigned)
76 ExtendKind = ISD::SIGN_EXTEND;
81 void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf,
85 TLI = MF->getSubtarget().getTargetLowering();
86 RegInfo = &MF->getRegInfo();
88 // Check whether the function can return without sret-demotion.
89 SmallVector<ISD::OutputArg, 4> Outs;
90 GetReturnInfo(Fn->getReturnType(), Fn->getAttributes(), Outs, *TLI);
91 CanLowerReturn = TLI->CanLowerReturn(Fn->getCallingConv(), *MF,
92 Fn->isVarArg(), Outs, Fn->getContext());
94 // Initialize the mapping of values to registers. This is only set up for
95 // instruction values that are used outside of the block that defines
97 Function::const_iterator BB = Fn->begin(), EB = Fn->end();
98 for (; BB != EB; ++BB)
99 for (BasicBlock::const_iterator I = BB->begin(), E = BB->end();
101 if (const AllocaInst *AI = dyn_cast<AllocaInst>(I)) {
102 // Static allocas can be folded into the initial stack frame adjustment.
103 if (AI->isStaticAlloca()) {
104 const ConstantInt *CUI = cast<ConstantInt>(AI->getArraySize());
105 Type *Ty = AI->getAllocatedType();
106 uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(Ty);
108 std::max((unsigned)TLI->getDataLayout()->getPrefTypeAlignment(Ty),
111 TySize *= CUI->getZExtValue(); // Get total allocated size.
112 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
114 StaticAllocaMap[AI] =
115 MF->getFrameInfo()->CreateStackObject(TySize, Align, false, AI);
118 unsigned Align = std::max(
119 (unsigned)TLI->getDataLayout()->getPrefTypeAlignment(
120 AI->getAllocatedType()),
122 unsigned StackAlign =
123 MF->getSubtarget().getFrameLowering()->getStackAlignment();
124 if (Align <= StackAlign)
126 // Inform the Frame Information that we have variable-sized objects.
127 MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1, AI);
131 // Look for inline asm that clobbers the SP register.
132 if (isa<CallInst>(I) || isa<InvokeInst>(I)) {
133 ImmutableCallSite CS(I);
134 if (isa<InlineAsm>(CS.getCalledValue())) {
135 unsigned SP = TLI->getStackPointerRegisterToSaveRestore();
136 std::vector<TargetLowering::AsmOperandInfo> Ops =
137 TLI->ParseConstraints(CS);
138 for (size_t I = 0, E = Ops.size(); I != E; ++I) {
139 TargetLowering::AsmOperandInfo &Op = Ops[I];
140 if (Op.Type == InlineAsm::isClobber) {
141 // Clobbers don't have SDValue operands, hence SDValue().
142 TLI->ComputeConstraintToUse(Op, SDValue(), DAG);
143 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
144 TLI->getRegForInlineAsmConstraint(Op.ConstraintCode,
146 if (PhysReg.first == SP)
147 MF->getFrameInfo()->setHasInlineAsmWithSPAdjust(true);
153 // Look for calls to the @llvm.va_start intrinsic. We can omit some
154 // prologue boilerplate for variadic functions that don't examine their
156 if (const auto *II = dyn_cast<IntrinsicInst>(I)) {
157 if (II->getIntrinsicID() == Intrinsic::vastart)
158 MF->getFrameInfo()->setHasVAStart(true);
161 // If we have a musttail call in a variadic funciton, we need to ensure we
162 // forward implicit register parameters.
163 if (const auto *CI = dyn_cast<CallInst>(I)) {
164 if (CI->isMustTailCall() && Fn->isVarArg())
165 MF->getFrameInfo()->setHasMustTailInVarArgFunc(true);
168 // Mark values used outside their block as exported, by allocating
169 // a virtual register for them.
170 if (isUsedOutsideOfDefiningBlock(I))
171 if (!isa<AllocaInst>(I) ||
172 !StaticAllocaMap.count(cast<AllocaInst>(I)))
173 InitializeRegForValue(I);
175 // Collect llvm.dbg.declare information. This is done now instead of
176 // during the initial isel pass through the IR so that it is done
177 // in a predictable order.
178 if (const DbgDeclareInst *DI = dyn_cast<DbgDeclareInst>(I)) {
179 MachineModuleInfo &MMI = MF->getMMI();
180 DIVariable DIVar(DI->getVariable());
181 assert((!DIVar || DIVar.isVariable()) &&
182 "Variable in DbgDeclareInst should be either null or a DIVariable.");
183 if (MMI.hasDebugInfo() &&
185 !DI->getDebugLoc().isUnknown()) {
186 // Don't handle byval struct arguments or VLAs, for example.
187 // Non-byval arguments are handled here (they refer to the stack
188 // temporary alloca at this point).
189 const Value *Address = DI->getAddress();
191 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
192 Address = BCI->getOperand(0);
193 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
194 DenseMap<const AllocaInst *, int>::iterator SI =
195 StaticAllocaMap.find(AI);
196 if (SI != StaticAllocaMap.end()) { // Check for VLAs.
198 MMI.setVariableDbgInfo(DI->getVariable(), DI->getExpression(),
199 FI, DI->getDebugLoc());
206 // Decide the preferred extend type for a value.
207 PreferredExtendType[I] = getPreferredExtendForValue(I);
210 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
211 // also creates the initial PHI MachineInstrs, though none of the input
212 // operands are populated.
213 for (BB = Fn->begin(); BB != EB; ++BB) {
214 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
218 // Transfer the address-taken flag. This is necessary because there could
219 // be multiple MachineBasicBlocks corresponding to one BasicBlock, and only
220 // the first one should be marked.
221 if (BB->hasAddressTaken())
222 MBB->setHasAddressTaken();
224 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
226 for (BasicBlock::const_iterator I = BB->begin();
227 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
228 if (PN->use_empty()) continue;
231 if (PN->getType()->isEmptyTy())
234 DebugLoc DL = PN->getDebugLoc();
235 unsigned PHIReg = ValueMap[PN];
236 assert(PHIReg && "PHI node does not have an assigned virtual register!");
238 SmallVector<EVT, 4> ValueVTs;
239 ComputeValueVTs(*TLI, PN->getType(), ValueVTs);
240 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
241 EVT VT = ValueVTs[vti];
242 unsigned NumRegisters = TLI->getNumRegisters(Fn->getContext(), VT);
243 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
244 for (unsigned i = 0; i != NumRegisters; ++i)
245 BuildMI(MBB, DL, TII->get(TargetOpcode::PHI), PHIReg + i);
246 PHIReg += NumRegisters;
251 // Mark landing pad blocks.
252 for (BB = Fn->begin(); BB != EB; ++BB)
253 if (const InvokeInst *Invoke = dyn_cast<InvokeInst>(BB->getTerminator()))
254 MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
257 /// clear - Clear out all the function-specific state. This returns this
258 /// FunctionLoweringInfo to an empty state, ready to be used for a
259 /// different function.
260 void FunctionLoweringInfo::clear() {
261 assert(CatchInfoFound.size() == CatchInfoLost.size() &&
262 "Not all catch info was assigned to a landing pad!");
266 StaticAllocaMap.clear();
268 CatchInfoLost.clear();
269 CatchInfoFound.clear();
271 LiveOutRegInfo.clear();
273 ArgDbgValues.clear();
274 ByValArgFrameIndexMap.clear();
276 StatepointStackSlots.clear();
277 PreferredExtendType.clear();
280 /// CreateReg - Allocate a single virtual register for the given type.
281 unsigned FunctionLoweringInfo::CreateReg(MVT VT) {
282 return RegInfo->createVirtualRegister(
283 MF->getSubtarget().getTargetLowering()->getRegClassFor(VT));
286 /// CreateRegs - Allocate the appropriate number of virtual registers of
287 /// the correctly promoted or expanded types. Assign these registers
288 /// consecutive vreg numbers and return the first assigned number.
290 /// In the case that the given value has struct or array type, this function
291 /// will assign registers for each member or element.
293 unsigned FunctionLoweringInfo::CreateRegs(Type *Ty) {
294 const TargetLowering *TLI = MF->getSubtarget().getTargetLowering();
296 SmallVector<EVT, 4> ValueVTs;
297 ComputeValueVTs(*TLI, Ty, ValueVTs);
299 unsigned FirstReg = 0;
300 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
301 EVT ValueVT = ValueVTs[Value];
302 MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT);
304 unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT);
305 for (unsigned i = 0; i != NumRegs; ++i) {
306 unsigned R = CreateReg(RegisterVT);
307 if (!FirstReg) FirstReg = R;
313 /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
314 /// register is a PHI destination and the PHI's LiveOutInfo is not valid. If
315 /// the register's LiveOutInfo is for a smaller bit width, it is extended to
316 /// the larger bit width by zero extension. The bit width must be no smaller
317 /// than the LiveOutInfo's existing bit width.
318 const FunctionLoweringInfo::LiveOutInfo *
319 FunctionLoweringInfo::GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth) {
320 if (!LiveOutRegInfo.inBounds(Reg))
323 LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
327 if (BitWidth > LOI->KnownZero.getBitWidth()) {
328 LOI->NumSignBits = 1;
329 LOI->KnownZero = LOI->KnownZero.zextOrTrunc(BitWidth);
330 LOI->KnownOne = LOI->KnownOne.zextOrTrunc(BitWidth);
336 /// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination
337 /// register based on the LiveOutInfo of its operands.
338 void FunctionLoweringInfo::ComputePHILiveOutRegInfo(const PHINode *PN) {
339 Type *Ty = PN->getType();
340 if (!Ty->isIntegerTy() || Ty->isVectorTy())
343 SmallVector<EVT, 1> ValueVTs;
344 ComputeValueVTs(*TLI, Ty, ValueVTs);
345 assert(ValueVTs.size() == 1 &&
346 "PHIs with non-vector integer types should have a single VT.");
347 EVT IntVT = ValueVTs[0];
349 if (TLI->getNumRegisters(PN->getContext(), IntVT) != 1)
351 IntVT = TLI->getTypeToTransformTo(PN->getContext(), IntVT);
352 unsigned BitWidth = IntVT.getSizeInBits();
354 unsigned DestReg = ValueMap[PN];
355 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
357 LiveOutRegInfo.grow(DestReg);
358 LiveOutInfo &DestLOI = LiveOutRegInfo[DestReg];
360 Value *V = PN->getIncomingValue(0);
361 if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
362 DestLOI.NumSignBits = 1;
363 APInt Zero(BitWidth, 0);
364 DestLOI.KnownZero = Zero;
365 DestLOI.KnownOne = Zero;
369 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
370 APInt Val = CI->getValue().zextOrTrunc(BitWidth);
371 DestLOI.NumSignBits = Val.getNumSignBits();
372 DestLOI.KnownZero = ~Val;
373 DestLOI.KnownOne = Val;
375 assert(ValueMap.count(V) && "V should have been placed in ValueMap when its"
376 "CopyToReg node was created.");
377 unsigned SrcReg = ValueMap[V];
378 if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
379 DestLOI.IsValid = false;
382 const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
384 DestLOI.IsValid = false;
390 assert(DestLOI.KnownZero.getBitWidth() == BitWidth &&
391 DestLOI.KnownOne.getBitWidth() == BitWidth &&
392 "Masks should have the same bit width as the type.");
394 for (unsigned i = 1, e = PN->getNumIncomingValues(); i != e; ++i) {
395 Value *V = PN->getIncomingValue(i);
396 if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
397 DestLOI.NumSignBits = 1;
398 APInt Zero(BitWidth, 0);
399 DestLOI.KnownZero = Zero;
400 DestLOI.KnownOne = Zero;
404 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
405 APInt Val = CI->getValue().zextOrTrunc(BitWidth);
406 DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, Val.getNumSignBits());
407 DestLOI.KnownZero &= ~Val;
408 DestLOI.KnownOne &= Val;
412 assert(ValueMap.count(V) && "V should have been placed in ValueMap when "
413 "its CopyToReg node was created.");
414 unsigned SrcReg = ValueMap[V];
415 if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
416 DestLOI.IsValid = false;
419 const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
421 DestLOI.IsValid = false;
424 DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, SrcLOI->NumSignBits);
425 DestLOI.KnownZero &= SrcLOI->KnownZero;
426 DestLOI.KnownOne &= SrcLOI->KnownOne;
430 /// setArgumentFrameIndex - Record frame index for the byval
431 /// argument. This overrides previous frame index entry for this argument,
433 void FunctionLoweringInfo::setArgumentFrameIndex(const Argument *A,
435 ByValArgFrameIndexMap[A] = FI;
438 /// getArgumentFrameIndex - Get frame index for the byval argument.
439 /// If the argument does not have any assigned frame index then 0 is
441 int FunctionLoweringInfo::getArgumentFrameIndex(const Argument *A) {
442 DenseMap<const Argument *, int>::iterator I =
443 ByValArgFrameIndexMap.find(A);
444 if (I != ByValArgFrameIndexMap.end())
446 DEBUG(dbgs() << "Argument does not have assigned frame index!\n");
450 /// ComputeUsesVAFloatArgument - Determine if any floating-point values are
451 /// being passed to this variadic function, and set the MachineModuleInfo's
452 /// usesVAFloatArgument flag if so. This flag is used to emit an undefined
453 /// reference to _fltused on Windows, which will link in MSVCRT's
454 /// floating-point support.
455 void llvm::ComputeUsesVAFloatArgument(const CallInst &I,
456 MachineModuleInfo *MMI)
458 FunctionType *FT = cast<FunctionType>(
459 I.getCalledValue()->getType()->getContainedType(0));
460 if (FT->isVarArg() && !MMI->usesVAFloatArgument()) {
461 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
462 Type* T = I.getArgOperand(i)->getType();
463 for (po_iterator<Type*> i = po_begin(T), e = po_end(T);
465 if (i->isFloatingPointTy()) {
466 MMI->setUsesVAFloatArgument(true);
474 /// AddCatchInfo - Extract the personality and type infos from an eh.selector
475 /// call, and add them to the specified machine basic block.
476 void llvm::AddCatchInfo(const CallInst &I, MachineModuleInfo *MMI,
477 MachineBasicBlock *MBB) {
478 // Inform the MachineModuleInfo of the personality for this landing pad.
479 const ConstantExpr *CE = cast<ConstantExpr>(I.getArgOperand(1));
480 assert(CE->getOpcode() == Instruction::BitCast &&
481 isa<Function>(CE->getOperand(0)) &&
482 "Personality should be a function");
483 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
485 // Gather all the type infos for this landing pad and pass them along to
486 // MachineModuleInfo.
487 std::vector<const GlobalValue *> TyInfo;
488 unsigned N = I.getNumArgOperands();
490 for (unsigned i = N - 1; i > 1; --i) {
491 if (const ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(i))) {
492 unsigned FilterLength = CI->getZExtValue();
493 unsigned FirstCatch = i + FilterLength + !FilterLength;
494 assert(FirstCatch <= N && "Invalid filter length");
496 if (FirstCatch < N) {
497 TyInfo.reserve(N - FirstCatch);
498 for (unsigned j = FirstCatch; j < N; ++j)
499 TyInfo.push_back(ExtractTypeInfo(I.getArgOperand(j)));
500 MMI->addCatchTypeInfo(MBB, TyInfo);
506 MMI->addCleanup(MBB);
509 TyInfo.reserve(FilterLength - 1);
510 for (unsigned j = i + 1; j < FirstCatch; ++j)
511 TyInfo.push_back(ExtractTypeInfo(I.getArgOperand(j)));
512 MMI->addFilterTypeInfo(MBB, TyInfo);
521 TyInfo.reserve(N - 2);
522 for (unsigned j = 2; j < N; ++j)
523 TyInfo.push_back(ExtractTypeInfo(I.getArgOperand(j)));
524 MMI->addCatchTypeInfo(MBB, TyInfo);
528 /// AddLandingPadInfo - Extract the exception handling information from the
529 /// landingpad instruction and add them to the specified machine module info.
530 void llvm::AddLandingPadInfo(const LandingPadInst &I, MachineModuleInfo &MMI,
531 MachineBasicBlock *MBB) {
532 MMI.addPersonality(MBB,
533 cast<Function>(I.getPersonalityFn()->stripPointerCasts()));
538 // FIXME: New EH - Add the clauses in reverse order. This isn't 100% correct,
539 // but we need to do it this way because of how the DWARF EH emitter
540 // processes the clauses.
541 for (unsigned i = I.getNumClauses(); i != 0; --i) {
542 Value *Val = I.getClause(i - 1);
543 if (I.isCatch(i - 1)) {
544 MMI.addCatchTypeInfo(MBB,
545 dyn_cast<GlobalValue>(Val->stripPointerCasts()));
547 // Add filters in a list.
548 Constant *CVal = cast<Constant>(Val);
549 SmallVector<const GlobalValue*, 4> FilterList;
550 for (User::op_iterator
551 II = CVal->op_begin(), IE = CVal->op_end(); II != IE; ++II)
552 FilterList.push_back(cast<GlobalValue>((*II)->stripPointerCasts()));
554 MMI.addFilterTypeInfo(MBB, FilterList);