1 //===-- FunctionLoweringInfo.h - Lower functions from LLVM IR to CodeGen --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating functions from LLVM IR into
13 //===----------------------------------------------------------------------===//
15 #ifndef FUNCTIONLOWERINGINFO_H
16 #define FUNCTIONLOWERINGINFO_H
18 #include "llvm/InlineAsm.h"
19 #include "llvm/Instructions.h"
20 #include "llvm/ADT/APInt.h"
21 #include "llvm/ADT/DenseMap.h"
23 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/ISDOpcodes.h"
27 #include "llvm/Support/CallSite.h"
38 class MachineBasicBlock;
39 class MachineFunction;
40 class MachineModuleInfo;
41 class MachineRegisterInfo;
45 //===--------------------------------------------------------------------===//
46 /// FunctionLoweringInfo - This contains information that is global to a
47 /// function that is used when lowering a region of the function.
49 class FunctionLoweringInfo {
51 const TargetLowering &TLI;
54 MachineRegisterInfo *RegInfo;
56 /// CanLowerReturn - true iff the function's return value can be lowered to
60 /// DemoteRegister - if CanLowerReturn is false, DemoteRegister is a vreg
61 /// allocated to hold a pointer to the hidden sret parameter.
62 unsigned DemoteRegister;
64 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
65 DenseMap<const BasicBlock*, MachineBasicBlock *> MBBMap;
67 /// ValueMap - Since we emit code for the function a basic block at a time,
68 /// we must remember which virtual registers hold the values for
69 /// cross-basic-block values.
70 DenseMap<const Value*, unsigned> ValueMap;
72 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
73 /// the entry block. This allows the allocas to be efficiently referenced
74 /// anywhere in the function.
75 DenseMap<const AllocaInst*, int> StaticAllocaMap;
78 SmallSet<const Instruction *, 8> CatchInfoLost;
79 SmallSet<const Instruction *, 8> CatchInfoFound;
84 APInt KnownOne, KnownZero;
85 LiveOutInfo() : NumSignBits(0), KnownOne(1, 0), KnownZero(1, 0) {}
88 /// LiveOutRegInfo - Information about live out vregs, indexed by their
89 /// register number offset by 'FirstVirtualRegister'.
90 std::vector<LiveOutInfo> LiveOutRegInfo;
92 explicit FunctionLoweringInfo(const TargetLowering &TLI);
94 /// set - Initialize this FunctionLoweringInfo with the given Function
95 /// and its associated MachineFunction.
97 void set(const Function &Fn, MachineFunction &MF, bool EnableFastISel);
99 /// clear - Clear out all the function-specific state. This returns this
100 /// FunctionLoweringInfo to an empty state, ready to be used for a
101 /// different function.
104 unsigned MakeReg(EVT VT);
106 /// isExportedInst - Return true if the specified value is an instruction
107 /// exported from its block.
108 bool isExportedInst(const Value *V) {
109 return ValueMap.count(V);
112 unsigned CreateRegForValue(const Value *V);
114 unsigned InitializeRegForValue(const Value *V) {
115 unsigned &R = ValueMap[V];
116 assert(R == 0 && "Already initialized this value register!");
117 return R = CreateRegForValue(V);
121 /// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence
122 /// of insertvalue or extractvalue indices that identify a member, return
123 /// the linearized index of the start of the member.
125 unsigned ComputeLinearIndex(const TargetLowering &TLI, const Type *Ty,
126 const unsigned *Indices,
127 const unsigned *IndicesEnd,
128 unsigned CurIndex = 0);
130 /// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
131 /// EVTs that represent all the individual underlying
132 /// non-aggregate types that comprise it.
134 /// If Offsets is non-null, it points to a vector to be filled in
135 /// with the in-memory offsets of each of the individual values.
137 void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty,
138 SmallVectorImpl<EVT> &ValueVTs,
139 SmallVectorImpl<uint64_t> *Offsets = 0,
140 uint64_t StartingOffset = 0);
142 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
143 GlobalVariable *ExtractTypeInfo(Value *V);
145 /// AddCatchInfo - Extract the personality and type infos from an eh.selector
146 /// call, and add them to the specified machine basic block.
147 void AddCatchInfo(const CallInst &I,
148 MachineModuleInfo *MMI, MachineBasicBlock *MBB);
150 /// CopyCatchInfo - Copy catch information from DestBB to SrcBB.
151 void CopyCatchInfo(const BasicBlock *SrcBB, const BasicBlock *DestBB,
152 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI);
154 /// hasInlineAsmMemConstraint - Return true if the inline asm instruction being
155 /// processed uses a memory 'm' constraint.
156 bool hasInlineAsmMemConstraint(std::vector<InlineAsm::ConstraintInfo> &CInfos,
157 const TargetLowering &TLI);
159 /// getFCmpCondCode - Return the ISD condition code corresponding to
160 /// the given LLVM IR floating-point condition code. This includes
161 /// consideration of global floating-point math flags.
163 ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred);
165 /// getICmpCondCode - Return the ISD condition code corresponding to
166 /// the given LLVM IR integer condition code.
168 ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred);
170 /// Test if the given instruction is in a position to be optimized
171 /// with a tail-call. This roughly means that it's in a block with
172 /// a return and there's nothing that needs to be scheduled
173 /// between it and the return.
175 /// This function only tests target-independent requirements.
176 bool isInTailCallPosition(ImmutableCallSite CS, Attributes CalleeRetAttr,
177 const TargetLowering &TLI);
179 } // end namespace llvm