1 //==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the Emit routines for the SelectionDAG class, which creates
11 // MachineInstrs based on the decisions of the SelectionDAG instruction
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "instr-emitter"
17 #include "InstrEmitter.h"
18 #include "SDNodeDbgValue.h"
19 #include "llvm/CodeGen/MachineConstantPool.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/Target/TargetData.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Target/TargetInstrInfo.h"
26 #include "llvm/Target/TargetLowering.h"
27 #include "llvm/ADT/Statistic.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/MathExtras.h"
33 /// CountResults - The results of target nodes have register or immediate
34 /// operands first, then an optional chain, and optional flag operands (which do
35 /// not go into the resulting MachineInstr).
36 unsigned InstrEmitter::CountResults(SDNode *Node) {
37 unsigned N = Node->getNumValues();
38 while (N && Node->getValueType(N - 1) == MVT::Flag)
40 if (N && Node->getValueType(N - 1) == MVT::Other)
41 --N; // Skip over chain result.
45 /// CountOperands - The inputs to target nodes have any actual inputs first,
46 /// followed by an optional chain operand, then an optional flag operand.
47 /// Compute the number of actual operands that will go into the resulting
49 unsigned InstrEmitter::CountOperands(SDNode *Node) {
50 unsigned N = Node->getNumOperands();
51 while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag)
53 if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
54 --N; // Ignore chain if it exists.
58 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
59 /// implicit physical register output.
61 EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
62 unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) {
64 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
65 // Just use the input register directly!
66 SDValue Op(Node, ResNo);
69 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
70 isNew = isNew; // Silence compiler warning.
71 assert(isNew && "Node emitted out of order - early");
75 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
76 // the CopyToReg'd destination register instead of creating a new vreg.
78 const TargetRegisterClass *UseRC = NULL;
79 if (!IsClone && !IsCloned)
80 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
84 if (User->getOpcode() == ISD::CopyToReg &&
85 User->getOperand(2).getNode() == Node &&
86 User->getOperand(2).getResNo() == ResNo) {
87 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
88 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
91 } else if (DestReg != SrcReg)
94 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
95 SDValue Op = User->getOperand(i);
96 if (Op.getNode() != Node || Op.getResNo() != ResNo)
98 EVT VT = Node->getValueType(Op.getResNo());
99 if (VT == MVT::Other || VT == MVT::Flag)
102 if (User->isMachineOpcode()) {
103 const TargetInstrDesc &II = TII->get(User->getMachineOpcode());
104 const TargetRegisterClass *RC = 0;
105 if (i+II.getNumDefs() < II.getNumOperands())
106 RC = II.OpInfo[i+II.getNumDefs()].getRegClass(TRI);
110 const TargetRegisterClass *ComRC = getCommonSubClass(UseRC, RC);
111 // If multiple uses expect disjoint register classes, we emit
112 // copies in AddRegisterOperand.
124 EVT VT = Node->getValueType(ResNo);
125 const TargetRegisterClass *SrcRC = 0, *DstRC = 0;
126 SrcRC = TRI->getPhysicalRegisterRegClass(SrcReg, VT);
128 // Figure out the register class to create for the destreg.
130 DstRC = MRI->getRegClass(VRBase);
132 assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!");
135 DstRC = TLI->getRegClassFor(VT);
138 // If all uses are reading from the src physical register and copying the
139 // register is either impossible or very expensive, then don't create a copy.
140 if (MatchReg && SrcRC->getCopyCost() < 0) {
143 // Create the reg, emit the copy.
144 VRBase = MRI->createVirtualRegister(DstRC);
145 bool Emitted = TII->copyRegToReg(*MBB, InsertPos, VRBase, SrcReg,
146 DstRC, SrcRC, Node->getDebugLoc());
148 assert(Emitted && "Unable to issue a copy instruction!\n");
152 SDValue Op(Node, ResNo);
155 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
156 isNew = isNew; // Silence compiler warning.
157 assert(isNew && "Node emitted out of order - early");
160 /// getDstOfCopyToRegUse - If the only use of the specified result number of
161 /// node is a CopyToReg, return its destination register. Return 0 otherwise.
162 unsigned InstrEmitter::getDstOfOnlyCopyToRegUse(SDNode *Node,
163 unsigned ResNo) const {
164 if (!Node->hasOneUse())
167 SDNode *User = *Node->use_begin();
168 if (User->getOpcode() == ISD::CopyToReg &&
169 User->getOperand(2).getNode() == Node &&
170 User->getOperand(2).getResNo() == ResNo) {
171 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
172 if (TargetRegisterInfo::isVirtualRegister(Reg))
178 void InstrEmitter::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
179 const TargetInstrDesc &II,
180 bool IsClone, bool IsCloned,
181 DenseMap<SDValue, unsigned> &VRBaseMap) {
182 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
183 "IMPLICIT_DEF should have been handled as a special case elsewhere!");
185 for (unsigned i = 0; i < II.getNumDefs(); ++i) {
186 // If the specific node value is only used by a CopyToReg and the dest reg
187 // is a vreg in the same register class, use the CopyToReg'd destination
188 // register instead of creating a new vreg.
190 const TargetRegisterClass *RC = II.OpInfo[i].getRegClass(TRI);
191 if (II.OpInfo[i].isOptionalDef()) {
192 // Optional def must be a physical register.
193 unsigned NumResults = CountResults(Node);
194 VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg();
195 assert(TargetRegisterInfo::isPhysicalRegister(VRBase));
196 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
199 if (!VRBase && !IsClone && !IsCloned)
200 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
203 if (User->getOpcode() == ISD::CopyToReg &&
204 User->getOperand(2).getNode() == Node &&
205 User->getOperand(2).getResNo() == i) {
206 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
207 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
208 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
211 MI->addOperand(MachineOperand::CreateReg(Reg, true));
218 // Create the result registers for this node and add the result regs to
219 // the machine instruction.
221 assert(RC && "Isn't a register operand!");
222 VRBase = MRI->createVirtualRegister(RC);
223 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
229 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
230 isNew = isNew; // Silence compiler warning.
231 assert(isNew && "Node emitted out of order - early");
235 /// getVR - Return the virtual register corresponding to the specified result
236 /// of the specified node.
237 unsigned InstrEmitter::getVR(SDValue Op,
238 DenseMap<SDValue, unsigned> &VRBaseMap) {
239 if (Op.isMachineOpcode() &&
240 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
241 // Add an IMPLICIT_DEF instruction before every use.
242 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo());
243 // IMPLICIT_DEF can produce any type of result so its TargetInstrDesc
244 // does not include operand register class info.
246 const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getValueType());
247 VReg = MRI->createVirtualRegister(RC);
249 BuildMI(MBB, Op.getDebugLoc(),
250 TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
254 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
255 assert(I != VRBaseMap.end() && "Node emitted out of order - late");
260 /// AddRegisterOperand - Add the specified register as an operand to the
261 /// specified machine instr. Insert register copies if the register is
262 /// not in the required register class.
264 InstrEmitter::AddRegisterOperand(MachineInstr *MI, SDValue Op,
266 const TargetInstrDesc *II,
267 DenseMap<SDValue, unsigned> &VRBaseMap,
268 bool IsDebug, bool IsClone, bool IsCloned) {
269 assert(Op.getValueType() != MVT::Other &&
270 Op.getValueType() != MVT::Flag &&
271 "Chain and flag operands should occur at end of operand list!");
272 // Get/emit the operand.
273 unsigned VReg = getVR(Op, VRBaseMap);
274 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
276 const TargetInstrDesc &TID = MI->getDesc();
277 bool isOptDef = IIOpNum < TID.getNumOperands() &&
278 TID.OpInfo[IIOpNum].isOptionalDef();
280 // If the instruction requires a register in a different class, create
281 // a new virtual register and copy the value into it.
283 const TargetRegisterClass *SrcRC = MRI->getRegClass(VReg);
284 const TargetRegisterClass *DstRC = 0;
285 if (IIOpNum < II->getNumOperands())
286 DstRC = II->OpInfo[IIOpNum].getRegClass(TRI);
287 assert((DstRC || (TID.isVariadic() && IIOpNum >= TID.getNumOperands())) &&
288 "Don't have operand info for this instruction!");
289 if (DstRC && SrcRC != DstRC && !SrcRC->hasSuperClass(DstRC)) {
290 unsigned NewVReg = MRI->createVirtualRegister(DstRC);
291 bool Emitted = TII->copyRegToReg(*MBB, InsertPos, NewVReg, VReg,
292 DstRC, SrcRC, Op.getNode()->getDebugLoc());
293 assert(Emitted && "Unable to issue a copy instruction!\n");
299 // If this value has only one use, that use is a kill. This is a
300 // conservative approximation. InstrEmitter does trivial coalescing
301 // with CopyFromReg nodes, so don't emit kill flags for them.
302 // Avoid kill flags on Schedule cloned nodes, since there will be
304 // Tied operands are never killed, so we need to check that. And that
305 // means we need to determine the index of the operand.
306 bool isKill = Op.hasOneUse() &&
307 Op.getNode()->getOpcode() != ISD::CopyFromReg &&
309 !(IsClone || IsCloned);
311 unsigned Idx = MI->getNumOperands();
313 MI->getOperand(Idx-1).isReg() && MI->getOperand(Idx-1).isImplicit())
315 bool isTied = MI->getDesc().getOperandConstraint(Idx, TOI::TIED_TO) != -1;
320 MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef,
321 false/*isImp*/, isKill,
322 false/*isDead*/, false/*isUndef*/,
323 false/*isEarlyClobber*/,
324 0/*SubReg*/, IsDebug));
327 /// AddOperand - Add the specified operand to the specified machine instr. II
328 /// specifies the instruction information for the node, and IIOpNum is the
329 /// operand number (in the II) that we are adding. IIOpNum and II are used for
331 void InstrEmitter::AddOperand(MachineInstr *MI, SDValue Op,
333 const TargetInstrDesc *II,
334 DenseMap<SDValue, unsigned> &VRBaseMap,
335 bool IsDebug, bool IsClone, bool IsCloned) {
336 if (Op.isMachineOpcode()) {
337 AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap,
338 IsDebug, IsClone, IsCloned);
339 } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
340 MI->addOperand(MachineOperand::CreateImm(C->getSExtValue()));
341 } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
342 const ConstantFP *CFP = F->getConstantFPValue();
343 MI->addOperand(MachineOperand::CreateFPImm(CFP));
344 } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
345 MI->addOperand(MachineOperand::CreateReg(R->getReg(), false));
346 } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
347 MI->addOperand(MachineOperand::CreateGA(TGA->getGlobal(), TGA->getOffset(),
348 TGA->getTargetFlags()));
349 } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) {
350 MI->addOperand(MachineOperand::CreateMBB(BBNode->getBasicBlock()));
351 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
352 MI->addOperand(MachineOperand::CreateFI(FI->getIndex()));
353 } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
354 MI->addOperand(MachineOperand::CreateJTI(JT->getIndex(),
355 JT->getTargetFlags()));
356 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
357 int Offset = CP->getOffset();
358 unsigned Align = CP->getAlignment();
359 const Type *Type = CP->getType();
360 // MachineConstantPool wants an explicit alignment.
362 Align = TM->getTargetData()->getPrefTypeAlignment(Type);
364 // Alignment of vector types. FIXME!
365 Align = TM->getTargetData()->getTypeAllocSize(Type);
370 MachineConstantPool *MCP = MF->getConstantPool();
371 if (CP->isMachineConstantPoolEntry())
372 Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align);
374 Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align);
375 MI->addOperand(MachineOperand::CreateCPI(Idx, Offset,
376 CP->getTargetFlags()));
377 } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
378 MI->addOperand(MachineOperand::CreateES(ES->getSymbol(),
379 ES->getTargetFlags()));
380 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) {
381 MI->addOperand(MachineOperand::CreateBA(BA->getBlockAddress(),
382 BA->getTargetFlags()));
384 assert(Op.getValueType() != MVT::Other &&
385 Op.getValueType() != MVT::Flag &&
386 "Chain and flag operands should occur at end of operand list!");
387 AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap,
388 IsDebug, IsClone, IsCloned);
392 /// getSuperRegisterRegClass - Returns the register class of a superreg A whose
393 /// "SubIdx"'th sub-register class is the specified register class and whose
394 /// type matches the specified type.
395 static const TargetRegisterClass*
396 getSuperRegisterRegClass(const TargetRegisterClass *TRC,
397 unsigned SubIdx, EVT VT) {
398 // Pick the register class of the superegister for this type
399 for (TargetRegisterInfo::regclass_iterator I = TRC->superregclasses_begin(),
400 E = TRC->superregclasses_end(); I != E; ++I)
401 if ((*I)->hasType(VT) && (*I)->getSubRegisterRegClass(SubIdx) == TRC)
403 assert(false && "Couldn't find the register class");
407 /// EmitSubregNode - Generate machine code for subreg nodes.
409 void InstrEmitter::EmitSubregNode(SDNode *Node,
410 DenseMap<SDValue, unsigned> &VRBaseMap,
411 bool IsClone, bool IsCloned) {
413 unsigned Opc = Node->getMachineOpcode();
415 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
416 // the CopyToReg'd destination register instead of creating a new vreg.
417 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
420 if (User->getOpcode() == ISD::CopyToReg &&
421 User->getOperand(2).getNode() == Node) {
422 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
423 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
430 if (Opc == TargetOpcode::EXTRACT_SUBREG) {
431 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
433 // Create the extract_subreg machine instruction.
434 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(),
435 TII->get(TargetOpcode::EXTRACT_SUBREG));
437 // Figure out the register class to create for the destreg.
438 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
439 const TargetRegisterClass *TRC = MRI->getRegClass(VReg);
440 const TargetRegisterClass *SRC = TRC->getSubRegisterRegClass(SubIdx);
441 assert(SRC && "Invalid subregister index in EXTRACT_SUBREG");
443 // Figure out the register class to create for the destreg.
444 // Note that if we're going to directly use an existing register,
445 // it must be precisely the required class, and not a subclass
447 if (VRBase == 0 || SRC != MRI->getRegClass(VRBase)) {
449 assert(SRC && "Couldn't find source register class");
450 VRBase = MRI->createVirtualRegister(SRC);
453 // Add def, source, and subreg index
454 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
455 AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap, /*IsDebug=*/false,
457 MI->addOperand(MachineOperand::CreateImm(SubIdx));
458 MBB->insert(InsertPos, MI);
459 } else if (Opc == TargetOpcode::INSERT_SUBREG ||
460 Opc == TargetOpcode::SUBREG_TO_REG) {
461 SDValue N0 = Node->getOperand(0);
462 SDValue N1 = Node->getOperand(1);
463 SDValue N2 = Node->getOperand(2);
464 unsigned SubReg = getVR(N1, VRBaseMap);
465 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
466 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
467 const TargetRegisterClass *SRC =
468 getSuperRegisterRegClass(TRC, SubIdx, Node->getValueType(0));
470 // Figure out the register class to create for the destreg.
471 // Note that if we're going to directly use an existing register,
472 // it must be precisely the required class, and not a subclass
474 if (VRBase == 0 || SRC != MRI->getRegClass(VRBase)) {
476 assert(SRC && "Couldn't find source register class");
477 VRBase = MRI->createVirtualRegister(SRC);
480 // Create the insert_subreg or subreg_to_reg machine instruction.
481 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc));
482 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
484 // If creating a subreg_to_reg, then the first input operand
485 // is an implicit value immediate, otherwise it's a register
486 if (Opc == TargetOpcode::SUBREG_TO_REG) {
487 const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
488 MI->addOperand(MachineOperand::CreateImm(SD->getZExtValue()));
490 AddOperand(MI, N0, 0, 0, VRBaseMap, /*IsDebug=*/false,
492 // Add the subregster being inserted
493 AddOperand(MI, N1, 0, 0, VRBaseMap, /*IsDebug=*/false,
495 MI->addOperand(MachineOperand::CreateImm(SubIdx));
496 MBB->insert(InsertPos, MI);
498 llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
501 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
502 isNew = isNew; // Silence compiler warning.
503 assert(isNew && "Node emitted out of order - early");
506 /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
507 /// COPY_TO_REGCLASS is just a normal copy, except that the destination
508 /// register is constrained to be in a particular register class.
511 InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
512 DenseMap<SDValue, unsigned> &VRBaseMap) {
513 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
514 const TargetRegisterClass *SrcRC = MRI->getRegClass(VReg);
516 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
517 const TargetRegisterClass *DstRC = TRI->getRegClass(DstRCIdx);
519 // Create the new VReg in the destination class and emit a copy.
520 unsigned NewVReg = MRI->createVirtualRegister(DstRC);
521 bool Emitted = TII->copyRegToReg(*MBB, InsertPos, NewVReg, VReg,
522 DstRC, SrcRC, Node->getDebugLoc());
524 "Unable to issue a copy instruction for a COPY_TO_REGCLASS node!\n");
528 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
529 isNew = isNew; // Silence compiler warning.
530 assert(isNew && "Node emitted out of order - early");
533 /// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
535 void InstrEmitter::EmitRegSequence(SDNode *Node,
536 DenseMap<SDValue, unsigned> &VRBaseMap,
537 bool IsClone, bool IsCloned) {
538 const TargetRegisterClass *RC = TLI->getRegClassFor(Node->getValueType(0));
539 unsigned NewVReg = MRI->createVirtualRegister(RC);
540 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(),
541 TII->get(TargetOpcode::REG_SEQUENCE), NewVReg);
542 unsigned NumOps = Node->getNumOperands();
543 assert((NumOps & 1) == 0 &&
544 "REG_SEQUENCE must have an even number of operands!");
545 const TargetInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
546 for (unsigned i = 0; i != NumOps; ++i) {
547 SDValue Op = Node->getOperand(i);
549 unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue();
550 unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap);
551 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
552 const TargetRegisterClass *SRC =
553 TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);
555 llvm_unreachable("Invalid subregister index in REG_SEQUENCE");
557 MRI->setRegClass(NewVReg, SRC);
561 AddOperand(MI, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false,
565 MBB->insert(InsertPos, MI);
567 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
568 isNew = isNew; // Silence compiler warning.
569 assert(isNew && "Node emitted out of order - early");
572 /// EmitDbgValue - Generate machine instruction for a dbg_value node.
575 InstrEmitter::EmitDbgValue(SDDbgValue *SD,
576 DenseMap<SDValue, unsigned> &VRBaseMap) {
577 uint64_t Offset = SD->getOffset();
578 MDNode* MDPtr = SD->getMDPtr();
579 DebugLoc DL = SD->getDebugLoc();
581 if (SD->getKind() == SDDbgValue::FRAMEIX) {
582 // Stack address; this needs to be lowered in target-dependent fashion.
583 // EmitTargetCodeForFrameDebugValue is responsible for allocation.
584 unsigned FrameIx = SD->getFrameIx();
585 return TII->emitFrameIndexDebugValue(*MF, FrameIx, Offset, MDPtr, DL);
587 // Otherwise, we're going to create an instruction here.
588 const TargetInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
589 MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
590 if (SD->getKind() == SDDbgValue::SDNODE) {
591 SDNode *Node = SD->getSDNode();
592 SDValue Op = SDValue(Node, SD->getResNo());
593 // It's possible we replaced this SDNode with other(s) and therefore
594 // didn't generate code for it. It's better to catch these cases where
595 // they happen and transfer the debug info, but trying to guarantee that
596 // in all cases would be very fragile; this is a safeguard for any
598 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
599 if (I==VRBaseMap.end())
600 MIB.addReg(0U); // undef
602 AddOperand(&*MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap,
603 /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false);
604 } else if (SD->getKind() == SDDbgValue::CONST) {
605 const Value *V = SD->getConst();
606 if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
607 // FIXME: SDDbgValues aren't updated with legalization, so it's possible
608 // to have i128 values in them at this point. As a crude workaround, just
609 // drop the debug info if this happens.
610 if (!CI->getValue().isSignedIntN(64))
613 MIB.addImm(CI->getSExtValue());
614 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
617 // Could be an Undef. In any case insert an Undef so we can see what we
622 // Insert an Undef so we can see what we dropped.
626 MIB.addImm(Offset).addMetadata(MDPtr);
630 /// EmitMachineNode - Generate machine code for a target-specific node and
631 /// needed dependencies.
634 EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
635 DenseMap<SDValue, unsigned> &VRBaseMap) {
636 unsigned Opc = Node->getMachineOpcode();
638 // Handle subreg insert/extract specially
639 if (Opc == TargetOpcode::EXTRACT_SUBREG ||
640 Opc == TargetOpcode::INSERT_SUBREG ||
641 Opc == TargetOpcode::SUBREG_TO_REG) {
642 EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned);
646 // Handle COPY_TO_REGCLASS specially.
647 if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
648 EmitCopyToRegClassNode(Node, VRBaseMap);
652 // Handle REG_SEQUENCE specially.
653 if (Opc == TargetOpcode::REG_SEQUENCE) {
654 EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned);
658 if (Opc == TargetOpcode::IMPLICIT_DEF)
659 // We want a unique VR for each IMPLICIT_DEF use.
662 const TargetInstrDesc &II = TII->get(Opc);
663 unsigned NumResults = CountResults(Node);
664 unsigned NodeOperands = CountOperands(Node);
665 bool HasPhysRegOuts = NumResults > II.getNumDefs() && II.getImplicitDefs()!=0;
667 unsigned NumMIOperands = NodeOperands + NumResults;
669 assert(NumMIOperands >= II.getNumOperands() &&
670 "Too few operands for a variadic node!");
672 assert(NumMIOperands >= II.getNumOperands() &&
673 NumMIOperands <= II.getNumOperands()+II.getNumImplicitDefs() &&
674 "#operands for dag node doesn't match .td file!");
677 // Create the new machine instruction.
678 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), II);
680 // Add result register values for things that are defined by this
683 CreateVirtualRegisters(Node, MI, II, IsClone, IsCloned, VRBaseMap);
685 // Emit all of the actual operands of this instruction, adding them to the
686 // instruction as appropriate.
687 bool HasOptPRefs = II.getNumDefs() > NumResults;
688 assert((!HasOptPRefs || !HasPhysRegOuts) &&
689 "Unable to cope with optional defs and phys regs defs!");
690 unsigned NumSkip = HasOptPRefs ? II.getNumDefs() - NumResults : 0;
691 for (unsigned i = NumSkip; i != NodeOperands; ++i)
692 AddOperand(MI, Node->getOperand(i), i-NumSkip+II.getNumDefs(), &II,
693 VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned);
695 // Transfer all of the memory reference descriptions of this instruction.
696 MI->setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(),
697 cast<MachineSDNode>(Node)->memoperands_end());
699 if (II.usesCustomInsertionHook()) {
700 // Insert this instruction into the basic block using a target
701 // specific inserter which may returns a new basic block.
702 MBB = TLI->EmitInstrWithCustomInserter(MI, MBB);
703 InsertPos = MBB->end();
707 MBB->insert(InsertPos, MI);
709 // Additional results must be an physical register def.
710 if (HasPhysRegOuts) {
711 for (unsigned i = II.getNumDefs(); i < NumResults; ++i) {
712 unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()];
713 if (Node->hasAnyUseOfValue(i))
714 EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
715 // If there are no uses, mark the register as dead now, so that
716 // MachineLICM/Sink can see that it's dead. Don't do this if the
717 // node has a Flag value, for the benefit of targets still using
718 // Flag for values in physregs.
719 else if (Node->getValueType(Node->getNumValues()-1) != MVT::Flag)
720 MI->addRegisterDead(Reg, TRI);
724 // If the instruction has implicit defs and the node doesn't, mark the
725 // implicit def as dead. If the node has any flag outputs, we don't do this
726 // because we don't know what implicit defs are being used by flagged nodes.
727 if (Node->getValueType(Node->getNumValues()-1) != MVT::Flag)
728 if (const unsigned *IDList = II.getImplicitDefs()) {
729 for (unsigned i = NumResults, e = II.getNumDefs()+II.getNumImplicitDefs();
731 MI->addRegisterDead(IDList[i-II.getNumDefs()], TRI);
735 /// EmitSpecialNode - Generate machine code for a target-independent node and
736 /// needed dependencies.
738 EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
739 DenseMap<SDValue, unsigned> &VRBaseMap) {
740 switch (Node->getOpcode()) {
745 llvm_unreachable("This target-independent node should have been selected!");
747 case ISD::EntryToken:
748 llvm_unreachable("EntryToken should have been excluded from the schedule!");
750 case ISD::MERGE_VALUES:
751 case ISD::TokenFactor: // fall thru
753 case ISD::CopyToReg: {
755 SDValue SrcVal = Node->getOperand(2);
756 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
757 SrcReg = R->getReg();
759 SrcReg = getVR(SrcVal, VRBaseMap);
761 unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
762 if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
765 const TargetRegisterClass *SrcTRC = 0, *DstTRC = 0;
766 // Get the register classes of the src/dst.
767 if (TargetRegisterInfo::isVirtualRegister(SrcReg))
768 SrcTRC = MRI->getRegClass(SrcReg);
770 SrcTRC = TRI->getPhysicalRegisterRegClass(SrcReg,SrcVal.getValueType());
772 if (TargetRegisterInfo::isVirtualRegister(DestReg))
773 DstTRC = MRI->getRegClass(DestReg);
775 DstTRC = TRI->getPhysicalRegisterRegClass(DestReg,
776 Node->getOperand(1).getValueType());
778 bool Emitted = TII->copyRegToReg(*MBB, InsertPos, DestReg, SrcReg,
779 DstTRC, SrcTRC, Node->getDebugLoc());
780 assert(Emitted && "Unable to issue a copy instruction!\n");
784 case ISD::CopyFromReg: {
785 unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
786 EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap);
789 case ISD::EH_LABEL: {
790 MCSymbol *S = cast<EHLabelSDNode>(Node)->getLabel();
791 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
792 TII->get(TargetOpcode::EH_LABEL)).addSym(S);
796 case ISD::INLINEASM: {
797 unsigned NumOps = Node->getNumOperands();
798 if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag)
799 --NumOps; // Ignore the flag operand.
801 // Create the inline asm machine instruction.
802 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(),
803 TII->get(TargetOpcode::INLINEASM));
805 // Add the asm string as an external symbol operand.
806 SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString);
807 const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol();
808 MI->addOperand(MachineOperand::CreateES(AsmStr));
810 // Add all of the operand registers to the instruction.
811 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
813 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
814 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
816 MI->addOperand(MachineOperand::CreateImm(Flags));
817 ++i; // Skip the ID value.
819 switch (InlineAsm::getKind(Flags)) {
820 default: llvm_unreachable("Bad flags!");
821 case InlineAsm::Kind_RegDef:
822 for (; NumVals; --NumVals, ++i) {
823 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
824 MI->addOperand(MachineOperand::CreateReg(Reg, true));
827 case InlineAsm::Kind_RegDefEarlyClobber:
828 for (; NumVals; --NumVals, ++i) {
829 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
830 MI->addOperand(MachineOperand::CreateReg(Reg, true, false, false,
831 false, false, true));
834 case InlineAsm::Kind_RegUse: // Use of register.
835 case InlineAsm::Kind_Imm: // Immediate.
836 case InlineAsm::Kind_Mem: // Addressing mode.
837 // The addressing mode has been selected, just add all of the
838 // operands to the machine instruction.
839 for (; NumVals; --NumVals, ++i)
840 AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap,
841 /*IsDebug=*/false, IsClone, IsCloned);
846 // Get the mdnode from the asm if it exists and add it to the instruction.
847 SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode);
848 const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD();
850 MI->addOperand(MachineOperand::CreateMetadata(MD));
852 MBB->insert(InsertPos, MI);
858 /// InstrEmitter - Construct an InstrEmitter and set it to start inserting
859 /// at the given position in the given block.
860 InstrEmitter::InstrEmitter(MachineBasicBlock *mbb,
861 MachineBasicBlock::iterator insertpos)
862 : MF(mbb->getParent()),
863 MRI(&MF->getRegInfo()),
864 TM(&MF->getTarget()),
865 TII(TM->getInstrInfo()),
866 TRI(TM->getRegisterInfo()),
867 TLI(TM->getTargetLowering()),
868 MBB(mbb), InsertPos(insertpos) {