1 //==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the Emit routines for the SelectionDAG class, which creates
11 // MachineInstrs based on the decisions of the SelectionDAG instruction
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "instr-emitter"
17 #include "InstrEmitter.h"
18 #include "SDNodeDbgValue.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/CodeGen/MachineConstantPool.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/StackMaps.h"
25 #include "llvm/IR/DataLayout.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/MathExtras.h"
29 #include "llvm/Target/TargetInstrInfo.h"
30 #include "llvm/Target/TargetLowering.h"
31 #include "llvm/Target/TargetMachine.h"
34 /// MinRCSize - Smallest register class we allow when constraining virtual
35 /// registers. If satisfying all register class constraints would require
36 /// using a smaller register class, emit a COPY to a new virtual register
38 const unsigned MinRCSize = 4;
40 /// CountResults - The results of target nodes have register or immediate
41 /// operands first, then an optional chain, and optional glue operands (which do
42 /// not go into the resulting MachineInstr).
43 unsigned InstrEmitter::CountResults(SDNode *Node) {
44 unsigned N = Node->getNumValues();
45 while (N && Node->getValueType(N - 1) == MVT::Glue)
47 if (N && Node->getValueType(N - 1) == MVT::Other)
48 --N; // Skip over chain result.
52 /// countOperands - The inputs to target nodes have any actual inputs first,
53 /// followed by an optional chain operand, then an optional glue operand.
54 /// Compute the number of actual operands that will go into the resulting
57 /// Also count physreg RegisterSDNode and RegisterMaskSDNode operands preceding
58 /// the chain and glue. These operands may be implicit on the machine instr.
59 static unsigned countOperands(SDNode *Node, unsigned NumExpUses,
60 unsigned &NumImpUses) {
61 unsigned N = Node->getNumOperands();
62 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
64 if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
65 --N; // Ignore chain if it exists.
67 // Count RegisterSDNode and RegisterMaskSDNode operands for NumImpUses.
68 NumImpUses = N - NumExpUses;
69 for (unsigned I = N; I > NumExpUses; --I) {
70 if (isa<RegisterMaskSDNode>(Node->getOperand(I - 1)))
72 if (RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Node->getOperand(I - 1)))
73 if (TargetRegisterInfo::isPhysicalRegister(RN->getReg()))
82 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
83 /// implicit physical register output.
85 EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
86 unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) {
88 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
89 // Just use the input register directly!
90 SDValue Op(Node, ResNo);
93 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
94 (void)isNew; // Silence compiler warning.
95 assert(isNew && "Node emitted out of order - early");
99 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
100 // the CopyToReg'd destination register instead of creating a new vreg.
101 bool MatchReg = true;
102 const TargetRegisterClass *UseRC = NULL;
103 MVT VT = Node->getSimpleValueType(ResNo);
105 // Stick to the preferred register classes for legal types.
106 if (TLI->isTypeLegal(VT))
107 UseRC = TLI->getRegClassFor(VT);
109 if (!IsClone && !IsCloned)
110 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
114 if (User->getOpcode() == ISD::CopyToReg &&
115 User->getOperand(2).getNode() == Node &&
116 User->getOperand(2).getResNo() == ResNo) {
117 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
118 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
121 } else if (DestReg != SrcReg)
124 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
125 SDValue Op = User->getOperand(i);
126 if (Op.getNode() != Node || Op.getResNo() != ResNo)
128 MVT VT = Node->getSimpleValueType(Op.getResNo());
129 if (VT == MVT::Other || VT == MVT::Glue)
132 if (User->isMachineOpcode()) {
133 const MCInstrDesc &II = TII->get(User->getMachineOpcode());
134 const TargetRegisterClass *RC = 0;
135 if (i+II.getNumDefs() < II.getNumOperands()) {
136 RC = TRI->getAllocatableClass(
137 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF));
142 const TargetRegisterClass *ComRC =
143 TRI->getCommonSubClass(UseRC, RC);
144 // If multiple uses expect disjoint register classes, we emit
145 // copies in AddRegisterOperand.
157 const TargetRegisterClass *SrcRC = 0, *DstRC = 0;
158 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
160 // Figure out the register class to create for the destreg.
162 DstRC = MRI->getRegClass(VRBase);
164 assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!");
167 DstRC = TLI->getRegClassFor(VT);
170 // If all uses are reading from the src physical register and copying the
171 // register is either impossible or very expensive, then don't create a copy.
172 if (MatchReg && SrcRC->getCopyCost() < 0) {
175 // Create the reg, emit the copy.
176 VRBase = MRI->createVirtualRegister(DstRC);
177 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
178 VRBase).addReg(SrcReg);
181 SDValue Op(Node, ResNo);
184 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
185 (void)isNew; // Silence compiler warning.
186 assert(isNew && "Node emitted out of order - early");
189 /// getDstOfCopyToRegUse - If the only use of the specified result number of
190 /// node is a CopyToReg, return its destination register. Return 0 otherwise.
191 unsigned InstrEmitter::getDstOfOnlyCopyToRegUse(SDNode *Node,
192 unsigned ResNo) const {
193 if (!Node->hasOneUse())
196 SDNode *User = *Node->use_begin();
197 if (User->getOpcode() == ISD::CopyToReg &&
198 User->getOperand(2).getNode() == Node &&
199 User->getOperand(2).getResNo() == ResNo) {
200 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
201 if (TargetRegisterInfo::isVirtualRegister(Reg))
207 void InstrEmitter::CreateVirtualRegisters(SDNode *Node,
208 MachineInstrBuilder &MIB,
209 const MCInstrDesc &II,
210 bool IsClone, bool IsCloned,
211 DenseMap<SDValue, unsigned> &VRBaseMap) {
212 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
213 "IMPLICIT_DEF should have been handled as a special case elsewhere!");
215 unsigned NumResults = CountResults(Node);
216 for (unsigned i = 0; i < II.getNumDefs(); ++i) {
217 // If the specific node value is only used by a CopyToReg and the dest reg
218 // is a vreg in the same register class, use the CopyToReg'd destination
219 // register instead of creating a new vreg.
221 const TargetRegisterClass *RC =
222 TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF));
223 // If the register class is unknown for the given definition, then try to
224 // infer one from the value type.
225 if (!RC && i < NumResults)
226 RC = TLI->getRegClassFor(Node->getSimpleValueType(i));
227 if (II.OpInfo[i].isOptionalDef()) {
228 // Optional def must be a physical register.
229 unsigned NumResults = CountResults(Node);
230 VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg();
231 assert(TargetRegisterInfo::isPhysicalRegister(VRBase));
232 MIB.addReg(VRBase, RegState::Define);
235 if (!VRBase && !IsClone && !IsCloned)
236 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
239 if (User->getOpcode() == ISD::CopyToReg &&
240 User->getOperand(2).getNode() == Node &&
241 User->getOperand(2).getResNo() == i) {
242 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
243 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
244 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
247 MIB.addReg(VRBase, RegState::Define);
254 // Create the result registers for this node and add the result regs to
255 // the machine instruction.
257 assert(RC && "Isn't a register operand!");
258 VRBase = MRI->createVirtualRegister(RC);
259 MIB.addReg(VRBase, RegState::Define);
265 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
266 (void)isNew; // Silence compiler warning.
267 assert(isNew && "Node emitted out of order - early");
271 /// getVR - Return the virtual register corresponding to the specified result
272 /// of the specified node.
273 unsigned InstrEmitter::getVR(SDValue Op,
274 DenseMap<SDValue, unsigned> &VRBaseMap) {
275 if (Op.isMachineOpcode() &&
276 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
277 // Add an IMPLICIT_DEF instruction before every use.
278 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo());
279 // IMPLICIT_DEF can produce any type of result so its MCInstrDesc
280 // does not include operand register class info.
282 const TargetRegisterClass *RC =
283 TLI->getRegClassFor(Op.getSimpleValueType());
284 VReg = MRI->createVirtualRegister(RC);
286 BuildMI(*MBB, InsertPos, Op.getDebugLoc(),
287 TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
291 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
292 assert(I != VRBaseMap.end() && "Node emitted out of order - late");
297 /// AddRegisterOperand - Add the specified register as an operand to the
298 /// specified machine instr. Insert register copies if the register is
299 /// not in the required register class.
301 InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
304 const MCInstrDesc *II,
305 DenseMap<SDValue, unsigned> &VRBaseMap,
306 bool IsDebug, bool IsClone, bool IsCloned) {
307 assert(Op.getValueType() != MVT::Other &&
308 Op.getValueType() != MVT::Glue &&
309 "Chain and glue operands should occur at end of operand list!");
310 // Get/emit the operand.
311 unsigned VReg = getVR(Op, VRBaseMap);
312 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
314 const MCInstrDesc &MCID = MIB->getDesc();
315 bool isOptDef = IIOpNum < MCID.getNumOperands() &&
316 MCID.OpInfo[IIOpNum].isOptionalDef();
318 // If the instruction requires a register in a different class, create
319 // a new virtual register and copy the value into it, but first attempt to
320 // shrink VReg's register class within reason. For example, if VReg == GR32
321 // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
323 const TargetRegisterClass *DstRC = 0;
324 if (IIOpNum < II->getNumOperands())
325 DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF));
326 if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) {
327 unsigned NewVReg = MRI->createVirtualRegister(DstRC);
328 BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
329 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
334 // If this value has only one use, that use is a kill. This is a
335 // conservative approximation. InstrEmitter does trivial coalescing
336 // with CopyFromReg nodes, so don't emit kill flags for them.
337 // Avoid kill flags on Schedule cloned nodes, since there will be
339 // Tied operands are never killed, so we need to check that. And that
340 // means we need to determine the index of the operand.
341 bool isKill = Op.hasOneUse() &&
342 Op.getNode()->getOpcode() != ISD::CopyFromReg &&
344 !(IsClone || IsCloned);
346 unsigned Idx = MIB->getNumOperands();
348 MIB->getOperand(Idx-1).isReg() &&
349 MIB->getOperand(Idx-1).isImplicit())
351 bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1;
356 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) |
357 getDebugRegState(IsDebug));
360 /// AddOperand - Add the specified operand to the specified machine instr. II
361 /// specifies the instruction information for the node, and IIOpNum is the
362 /// operand number (in the II) that we are adding.
363 void InstrEmitter::AddOperand(MachineInstrBuilder &MIB,
366 const MCInstrDesc *II,
367 DenseMap<SDValue, unsigned> &VRBaseMap,
368 bool IsDebug, bool IsClone, bool IsCloned) {
369 if (Op.isMachineOpcode()) {
370 AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
371 IsDebug, IsClone, IsCloned);
372 } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
373 MIB.addImm(C->getSExtValue());
374 } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
375 MIB.addFPImm(F->getConstantFPValue());
376 } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
377 // Turn additional physreg operands into implicit uses on non-variadic
378 // instructions. This is used by call and return instructions passing
379 // arguments in registers.
380 bool Imp = II && (IIOpNum >= II->getNumOperands() && !II->isVariadic());
381 MIB.addReg(R->getReg(), getImplRegState(Imp));
382 } else if (RegisterMaskSDNode *RM = dyn_cast<RegisterMaskSDNode>(Op)) {
383 MIB.addRegMask(RM->getRegMask());
384 } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
385 MIB.addGlobalAddress(TGA->getGlobal(), TGA->getOffset(),
386 TGA->getTargetFlags());
387 } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) {
388 MIB.addMBB(BBNode->getBasicBlock());
389 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
390 MIB.addFrameIndex(FI->getIndex());
391 } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
392 MIB.addJumpTableIndex(JT->getIndex(), JT->getTargetFlags());
393 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
394 int Offset = CP->getOffset();
395 unsigned Align = CP->getAlignment();
396 Type *Type = CP->getType();
397 // MachineConstantPool wants an explicit alignment.
399 Align = TM->getDataLayout()->getPrefTypeAlignment(Type);
401 // Alignment of vector types. FIXME!
402 Align = TM->getDataLayout()->getTypeAllocSize(Type);
407 MachineConstantPool *MCP = MF->getConstantPool();
408 if (CP->isMachineConstantPoolEntry())
409 Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align);
411 Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align);
412 MIB.addConstantPoolIndex(Idx, Offset, CP->getTargetFlags());
413 } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
414 MIB.addExternalSymbol(ES->getSymbol(), ES->getTargetFlags());
415 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) {
416 MIB.addBlockAddress(BA->getBlockAddress(),
418 BA->getTargetFlags());
419 } else if (TargetIndexSDNode *TI = dyn_cast<TargetIndexSDNode>(Op)) {
420 MIB.addTargetIndex(TI->getIndex(), TI->getOffset(), TI->getTargetFlags());
422 assert(Op.getValueType() != MVT::Other &&
423 Op.getValueType() != MVT::Glue &&
424 "Chain and glue operands should occur at end of operand list!");
425 AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
426 IsDebug, IsClone, IsCloned);
430 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
431 MVT VT, DebugLoc DL) {
432 const TargetRegisterClass *VRC = MRI->getRegClass(VReg);
433 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx);
435 // RC is a sub-class of VRC that supports SubIdx. Try to constrain VReg
438 RC = MRI->constrainRegClass(VReg, RC, MinRCSize);
440 // VReg has been adjusted. It can be used with SubIdx operands now.
444 // VReg couldn't be reasonably constrained. Emit a COPY to a new virtual
446 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx);
447 assert(RC && "No legal register class for VT supports that SubIdx");
448 unsigned NewReg = MRI->createVirtualRegister(RC);
449 BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg)
454 /// EmitSubregNode - Generate machine code for subreg nodes.
456 void InstrEmitter::EmitSubregNode(SDNode *Node,
457 DenseMap<SDValue, unsigned> &VRBaseMap,
458 bool IsClone, bool IsCloned) {
460 unsigned Opc = Node->getMachineOpcode();
462 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
463 // the CopyToReg'd destination register instead of creating a new vreg.
464 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
467 if (User->getOpcode() == ISD::CopyToReg &&
468 User->getOperand(2).getNode() == Node) {
469 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
470 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
477 if (Opc == TargetOpcode::EXTRACT_SUBREG) {
478 // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub. There are no
479 // constraints on the %dst register, COPY can target all legal register
481 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
482 const TargetRegisterClass *TRC =
483 TLI->getRegClassFor(Node->getSimpleValueType(0));
485 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
486 MachineInstr *DefMI = MRI->getVRegDef(VReg);
487 unsigned SrcReg, DstReg, DefSubIdx;
489 TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) &&
490 SubIdx == DefSubIdx &&
491 TRC == MRI->getRegClass(SrcReg)) {
493 // r1025 = s/zext r1024, 4
494 // r1026 = extract_subreg r1025, 4
496 // r1026 = copy r1024
497 VRBase = MRI->createVirtualRegister(TRC);
498 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
499 TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg);
500 MRI->clearKillFlags(SrcReg);
502 // VReg may not support a SubIdx sub-register, and we may need to
503 // constrain its register class or issue a COPY to a compatible register
505 VReg = ConstrainForSubReg(VReg, SubIdx,
506 Node->getOperand(0).getSimpleValueType(),
507 Node->getDebugLoc());
509 // Create the destreg if it is missing.
511 VRBase = MRI->createVirtualRegister(TRC);
513 // Create the extract_subreg machine instruction.
514 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
515 TII->get(TargetOpcode::COPY), VRBase).addReg(VReg, 0, SubIdx);
517 } else if (Opc == TargetOpcode::INSERT_SUBREG ||
518 Opc == TargetOpcode::SUBREG_TO_REG) {
519 SDValue N0 = Node->getOperand(0);
520 SDValue N1 = Node->getOperand(1);
521 SDValue N2 = Node->getOperand(2);
522 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
524 // Figure out the register class to create for the destreg. It should be
525 // the largest legal register class supporting SubIdx sub-registers.
526 // RegisterCoalescer will constrain it further if it decides to eliminate
527 // the INSERT_SUBREG instruction.
529 // %dst = INSERT_SUBREG %src, %sub, SubIdx
531 // is lowered by TwoAddressInstructionPass to:
534 // %dst:SubIdx = COPY %sub
536 // There is no constraint on the %src register class.
538 const TargetRegisterClass *SRC = TLI->getRegClassFor(Node->getSimpleValueType(0));
539 SRC = TRI->getSubClassWithSubReg(SRC, SubIdx);
540 assert(SRC && "No register class supports VT and SubIdx for INSERT_SUBREG");
542 if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase)))
543 VRBase = MRI->createVirtualRegister(SRC);
545 // Create the insert_subreg or subreg_to_reg machine instruction.
546 MachineInstrBuilder MIB =
547 BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc), VRBase);
549 // If creating a subreg_to_reg, then the first input operand
550 // is an implicit value immediate, otherwise it's a register
551 if (Opc == TargetOpcode::SUBREG_TO_REG) {
552 const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
553 MIB.addImm(SD->getZExtValue());
555 AddOperand(MIB, N0, 0, 0, VRBaseMap, /*IsDebug=*/false,
557 // Add the subregster being inserted
558 AddOperand(MIB, N1, 0, 0, VRBaseMap, /*IsDebug=*/false,
561 MBB->insert(InsertPos, MIB);
563 llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
566 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
567 (void)isNew; // Silence compiler warning.
568 assert(isNew && "Node emitted out of order - early");
571 /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
572 /// COPY_TO_REGCLASS is just a normal copy, except that the destination
573 /// register is constrained to be in a particular register class.
576 InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
577 DenseMap<SDValue, unsigned> &VRBaseMap) {
578 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
580 // Create the new VReg in the destination class and emit a copy.
581 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
582 const TargetRegisterClass *DstRC =
583 TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx));
584 unsigned NewVReg = MRI->createVirtualRegister(DstRC);
585 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
586 NewVReg).addReg(VReg);
589 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
590 (void)isNew; // Silence compiler warning.
591 assert(isNew && "Node emitted out of order - early");
594 /// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
596 void InstrEmitter::EmitRegSequence(SDNode *Node,
597 DenseMap<SDValue, unsigned> &VRBaseMap,
598 bool IsClone, bool IsCloned) {
599 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
600 const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
601 unsigned NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC));
602 const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
603 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II, NewVReg);
604 unsigned NumOps = Node->getNumOperands();
605 assert((NumOps & 1) == 1 &&
606 "REG_SEQUENCE must have an odd number of operands!");
607 for (unsigned i = 1; i != NumOps; ++i) {
608 SDValue Op = Node->getOperand(i);
610 RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(i-1));
611 // Skip physical registers as they don't have a vreg to get and we'll
612 // insert copies for them in TwoAddressInstructionPass anyway.
613 if (!R || !TargetRegisterInfo::isPhysicalRegister(R->getReg())) {
614 unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue();
615 unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap);
616 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
617 const TargetRegisterClass *SRC =
618 TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);
619 if (SRC && SRC != RC) {
620 MRI->setRegClass(NewVReg, SRC);
625 AddOperand(MIB, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false,
629 MBB->insert(InsertPos, MIB);
631 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
632 (void)isNew; // Silence compiler warning.
633 assert(isNew && "Node emitted out of order - early");
636 /// EmitDbgValue - Generate machine instruction for a dbg_value node.
639 InstrEmitter::EmitDbgValue(SDDbgValue *SD,
640 DenseMap<SDValue, unsigned> &VRBaseMap) {
641 uint64_t Offset = SD->getOffset();
642 MDNode* MDPtr = SD->getMDPtr();
643 DebugLoc DL = SD->getDebugLoc();
645 if (SD->getKind() == SDDbgValue::FRAMEIX) {
646 // Stack address; this needs to be lowered in target-dependent fashion.
647 // EmitTargetCodeForFrameDebugValue is responsible for allocation.
648 return BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE))
649 .addFrameIndex(SD->getFrameIx()).addImm(Offset).addMetadata(MDPtr);
651 // Otherwise, we're going to create an instruction here.
652 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
653 MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
654 if (SD->getKind() == SDDbgValue::SDNODE) {
655 SDNode *Node = SD->getSDNode();
656 SDValue Op = SDValue(Node, SD->getResNo());
657 // It's possible we replaced this SDNode with other(s) and therefore
658 // didn't generate code for it. It's better to catch these cases where
659 // they happen and transfer the debug info, but trying to guarantee that
660 // in all cases would be very fragile; this is a safeguard for any
662 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
663 if (I==VRBaseMap.end())
664 MIB.addReg(0U); // undef
666 AddOperand(MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap,
667 /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false);
668 } else if (SD->getKind() == SDDbgValue::CONST) {
669 const Value *V = SD->getConst();
670 if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
671 if (CI->getBitWidth() > 64)
674 MIB.addImm(CI->getSExtValue());
675 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
678 // Could be an Undef. In any case insert an Undef so we can see what we
683 // Insert an Undef so we can see what we dropped.
687 if (Offset != 0) // Indirect addressing.
690 MIB.addReg(0U, RegState::Debug);
692 MIB.addMetadata(MDPtr);
697 /// EmitMachineNode - Generate machine code for a target-specific node and
698 /// needed dependencies.
701 EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
702 DenseMap<SDValue, unsigned> &VRBaseMap) {
703 unsigned Opc = Node->getMachineOpcode();
705 // Handle subreg insert/extract specially
706 if (Opc == TargetOpcode::EXTRACT_SUBREG ||
707 Opc == TargetOpcode::INSERT_SUBREG ||
708 Opc == TargetOpcode::SUBREG_TO_REG) {
709 EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned);
713 // Handle COPY_TO_REGCLASS specially.
714 if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
715 EmitCopyToRegClassNode(Node, VRBaseMap);
719 // Handle REG_SEQUENCE specially.
720 if (Opc == TargetOpcode::REG_SEQUENCE) {
721 EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned);
725 if (Opc == TargetOpcode::IMPLICIT_DEF)
726 // We want a unique VR for each IMPLICIT_DEF use.
729 const MCInstrDesc &II = TII->get(Opc);
730 unsigned NumResults = CountResults(Node);
731 unsigned NumDefs = II.getNumDefs();
732 const uint16_t *ScratchRegs = NULL;
734 // Handle PATCHPOINT specially and then use the generic code.
735 if (Opc == TargetOpcode::PATCHPOINT) {
736 unsigned CC = Node->getConstantOperandVal(PatchPointOpers::CCPos);
737 NumDefs = NumResults;
738 ScratchRegs = TLI->getScratchRegisters((CallingConv::ID) CC);
741 unsigned NumImpUses = 0;
742 unsigned NodeOperands =
743 countOperands(Node, II.getNumOperands() - NumDefs, NumImpUses);
744 bool HasPhysRegOuts = NumResults > NumDefs && II.getImplicitDefs()!=0;
746 unsigned NumMIOperands = NodeOperands + NumResults;
748 assert(NumMIOperands >= II.getNumOperands() &&
749 "Too few operands for a variadic node!");
751 assert(NumMIOperands >= II.getNumOperands() &&
752 NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() +
754 "#operands for dag node doesn't match .td file!");
757 // Create the new machine instruction.
758 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II);
760 // Add result register values for things that are defined by this
763 CreateVirtualRegisters(Node, MIB, II, IsClone, IsCloned, VRBaseMap);
765 // Emit all of the actual operands of this instruction, adding them to the
766 // instruction as appropriate.
767 bool HasOptPRefs = NumDefs > NumResults;
768 assert((!HasOptPRefs || !HasPhysRegOuts) &&
769 "Unable to cope with optional defs and phys regs defs!");
770 unsigned NumSkip = HasOptPRefs ? NumDefs - NumResults : 0;
771 for (unsigned i = NumSkip; i != NodeOperands; ++i)
772 AddOperand(MIB, Node->getOperand(i), i-NumSkip+NumDefs, &II,
773 VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned);
775 // Add scratch registers as implicit def and early clobber
777 for (unsigned i = 0; ScratchRegs[i]; ++i)
778 MIB.addReg(ScratchRegs[i], RegState::ImplicitDefine |
779 RegState::EarlyClobber);
781 // Transfer all of the memory reference descriptions of this instruction.
782 MIB.setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(),
783 cast<MachineSDNode>(Node)->memoperands_end());
785 // Insert the instruction into position in the block. This needs to
786 // happen before any custom inserter hook is called so that the
787 // hook knows where in the block to insert the replacement code.
788 MBB->insert(InsertPos, MIB);
790 // The MachineInstr may also define physregs instead of virtregs. These
791 // physreg values can reach other instructions in different ways:
793 // 1. When there is a use of a Node value beyond the explicitly defined
794 // virtual registers, we emit a CopyFromReg for one of the implicitly
795 // defined physregs. This only happens when HasPhysRegOuts is true.
797 // 2. A CopyFromReg reading a physreg may be glued to this instruction.
799 // 3. A glued instruction may implicitly use a physreg.
801 // 4. A glued instruction may use a RegisterSDNode operand.
803 // Collect all the used physreg defs, and make sure that any unused physreg
804 // defs are marked as dead.
805 SmallVector<unsigned, 8> UsedRegs;
807 // Additional results must be physical register defs.
808 if (HasPhysRegOuts) {
809 for (unsigned i = NumDefs; i < NumResults; ++i) {
810 unsigned Reg = II.getImplicitDefs()[i - NumDefs];
811 if (!Node->hasAnyUseOfValue(i))
813 // This implicitly defined physreg has a use.
814 UsedRegs.push_back(Reg);
815 EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
819 // Scan the glue chain for any used physregs.
820 if (Node->getValueType(Node->getNumValues()-1) == MVT::Glue) {
821 for (SDNode *F = Node->getGluedUser(); F; F = F->getGluedUser()) {
822 if (F->getOpcode() == ISD::CopyFromReg) {
823 UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg());
825 } else if (F->getOpcode() == ISD::CopyToReg) {
826 // Skip CopyToReg nodes that are internal to the glue chain.
829 // Collect declared implicit uses.
830 const MCInstrDesc &MCID = TII->get(F->getMachineOpcode());
831 UsedRegs.append(MCID.getImplicitUses(),
832 MCID.getImplicitUses() + MCID.getNumImplicitUses());
833 // In addition to declared implicit uses, we must also check for
834 // direct RegisterSDNode operands.
835 for (unsigned i = 0, e = F->getNumOperands(); i != e; ++i)
836 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) {
837 unsigned Reg = R->getReg();
838 if (TargetRegisterInfo::isPhysicalRegister(Reg))
839 UsedRegs.push_back(Reg);
844 // Finally mark unused registers as dead.
845 if (!UsedRegs.empty() || II.getImplicitDefs())
846 MIB->setPhysRegsDeadExcept(UsedRegs, *TRI);
848 // Run post-isel target hook to adjust this instruction if needed.
850 if (II.hasPostISelHook())
852 TLI->AdjustInstrPostInstrSelection(MIB, Node);
855 /// EmitSpecialNode - Generate machine code for a target-independent node and
856 /// needed dependencies.
858 EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
859 DenseMap<SDValue, unsigned> &VRBaseMap) {
860 switch (Node->getOpcode()) {
865 llvm_unreachable("This target-independent node should have been selected!");
866 case ISD::EntryToken:
867 llvm_unreachable("EntryToken should have been excluded from the schedule!");
868 case ISD::MERGE_VALUES:
869 case ISD::TokenFactor: // fall thru
871 case ISD::CopyToReg: {
873 SDValue SrcVal = Node->getOperand(2);
874 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
875 SrcReg = R->getReg();
877 SrcReg = getVR(SrcVal, VRBaseMap);
879 unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
880 if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
883 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
884 DestReg).addReg(SrcReg);
887 case ISD::CopyFromReg: {
888 unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
889 EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap);
892 case ISD::EH_LABEL: {
893 MCSymbol *S = cast<EHLabelSDNode>(Node)->getLabel();
894 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
895 TII->get(TargetOpcode::EH_LABEL)).addSym(S);
899 case ISD::LIFETIME_START:
900 case ISD::LIFETIME_END: {
901 unsigned TarOp = (Node->getOpcode() == ISD::LIFETIME_START) ?
902 TargetOpcode::LIFETIME_START : TargetOpcode::LIFETIME_END;
904 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Node->getOperand(1));
905 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TarOp))
906 .addFrameIndex(FI->getIndex());
910 case ISD::INLINEASM: {
911 unsigned NumOps = Node->getNumOperands();
912 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
913 --NumOps; // Ignore the glue operand.
915 // Create the inline asm machine instruction.
916 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(),
917 TII->get(TargetOpcode::INLINEASM));
919 // Add the asm string as an external symbol operand.
920 SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString);
921 const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol();
922 MIB.addExternalSymbol(AsmStr);
924 // Add the HasSideEffect, isAlignStack, AsmDialect, MayLoad and MayStore
927 cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_ExtraInfo))->
929 MIB.addImm(ExtraInfo);
931 // Remember to operand index of the group flags.
932 SmallVector<unsigned, 8> GroupIdx;
934 // Add all of the operand registers to the instruction.
935 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
937 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
938 const unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
940 GroupIdx.push_back(MIB->getNumOperands());
942 ++i; // Skip the ID value.
944 switch (InlineAsm::getKind(Flags)) {
945 default: llvm_unreachable("Bad flags!");
946 case InlineAsm::Kind_RegDef:
947 for (unsigned j = 0; j != NumVals; ++j, ++i) {
948 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
949 // FIXME: Add dead flags for physical and virtual registers defined.
950 // For now, mark physical register defs as implicit to help fast
951 // regalloc. This makes inline asm look a lot like calls.
952 MIB.addReg(Reg, RegState::Define |
953 getImplRegState(TargetRegisterInfo::isPhysicalRegister(Reg)));
956 case InlineAsm::Kind_RegDefEarlyClobber:
957 case InlineAsm::Kind_Clobber:
958 for (unsigned j = 0; j != NumVals; ++j, ++i) {
959 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
960 MIB.addReg(Reg, RegState::Define | RegState::EarlyClobber |
961 getImplRegState(TargetRegisterInfo::isPhysicalRegister(Reg)));
964 case InlineAsm::Kind_RegUse: // Use of register.
965 case InlineAsm::Kind_Imm: // Immediate.
966 case InlineAsm::Kind_Mem: // Addressing mode.
967 // The addressing mode has been selected, just add all of the
968 // operands to the machine instruction.
969 for (unsigned j = 0; j != NumVals; ++j, ++i)
970 AddOperand(MIB, Node->getOperand(i), 0, 0, VRBaseMap,
971 /*IsDebug=*/false, IsClone, IsCloned);
973 // Manually set isTied bits.
974 if (InlineAsm::getKind(Flags) == InlineAsm::Kind_RegUse) {
975 unsigned DefGroup = 0;
976 if (InlineAsm::isUseOperandTiedToDef(Flags, DefGroup)) {
977 unsigned DefIdx = GroupIdx[DefGroup] + 1;
978 unsigned UseIdx = GroupIdx.back() + 1;
979 for (unsigned j = 0; j != NumVals; ++j)
980 MIB->tieOperands(DefIdx + j, UseIdx + j);
987 // Get the mdnode from the asm if it exists and add it to the instruction.
988 SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode);
989 const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD();
993 MBB->insert(InsertPos, MIB);
999 /// InstrEmitter - Construct an InstrEmitter and set it to start inserting
1000 /// at the given position in the given block.
1001 InstrEmitter::InstrEmitter(MachineBasicBlock *mbb,
1002 MachineBasicBlock::iterator insertpos)
1003 : MF(mbb->getParent()),
1004 MRI(&MF->getRegInfo()),
1005 TM(&MF->getTarget()),
1006 TII(TM->getInstrInfo()),
1007 TRI(TM->getRegisterInfo()),
1008 TLI(TM->getTargetLowering()),
1009 MBB(mbb), InsertPos(insertpos) {