1 //==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the Emit routines for the SelectionDAG class, which creates
11 // MachineInstrs based on the decisions of the SelectionDAG instruction
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "instr-emitter"
17 #include "InstrEmitter.h"
18 #include "SDNodeDbgValue.h"
19 #include "llvm/CodeGen/MachineConstantPool.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/Target/TargetData.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Target/TargetInstrInfo.h"
26 #include "llvm/Target/TargetLowering.h"
27 #include "llvm/ADT/Statistic.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/MathExtras.h"
33 /// CountResults - The results of target nodes have register or immediate
34 /// operands first, then an optional chain, and optional flag operands (which do
35 /// not go into the resulting MachineInstr).
36 unsigned InstrEmitter::CountResults(SDNode *Node) {
37 unsigned N = Node->getNumValues();
38 while (N && Node->getValueType(N - 1) == MVT::Flag)
40 if (N && Node->getValueType(N - 1) == MVT::Other)
41 --N; // Skip over chain result.
45 /// CountOperands - The inputs to target nodes have any actual inputs first,
46 /// followed by an optional chain operand, then an optional flag operand.
47 /// Compute the number of actual operands that will go into the resulting
49 unsigned InstrEmitter::CountOperands(SDNode *Node) {
50 unsigned N = Node->getNumOperands();
51 while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag)
53 if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
54 --N; // Ignore chain if it exists.
58 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
59 /// implicit physical register output.
61 EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
62 unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) {
64 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
65 // Just use the input register directly!
66 SDValue Op(Node, ResNo);
69 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
70 isNew = isNew; // Silence compiler warning.
71 assert(isNew && "Node emitted out of order - early");
75 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
76 // the CopyToReg'd destination register instead of creating a new vreg.
78 const TargetRegisterClass *UseRC = NULL;
79 if (!IsClone && !IsCloned)
80 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
84 if (User->getOpcode() == ISD::CopyToReg &&
85 User->getOperand(2).getNode() == Node &&
86 User->getOperand(2).getResNo() == ResNo) {
87 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
88 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
91 } else if (DestReg != SrcReg)
94 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
95 SDValue Op = User->getOperand(i);
96 if (Op.getNode() != Node || Op.getResNo() != ResNo)
98 EVT VT = Node->getValueType(Op.getResNo());
99 if (VT == MVT::Other || VT == MVT::Flag)
102 if (User->isMachineOpcode()) {
103 const TargetInstrDesc &II = TII->get(User->getMachineOpcode());
104 const TargetRegisterClass *RC = 0;
105 if (i+II.getNumDefs() < II.getNumOperands())
106 RC = II.OpInfo[i+II.getNumDefs()].getRegClass(TRI);
110 const TargetRegisterClass *ComRC = getCommonSubClass(UseRC, RC);
111 // If multiple uses expect disjoint register classes, we emit
112 // copies in AddRegisterOperand.
124 EVT VT = Node->getValueType(ResNo);
125 const TargetRegisterClass *SrcRC = 0, *DstRC = 0;
126 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
128 // Figure out the register class to create for the destreg.
130 DstRC = MRI->getRegClass(VRBase);
132 assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!");
135 DstRC = TLI->getRegClassFor(VT);
138 // If all uses are reading from the src physical register and copying the
139 // register is either impossible or very expensive, then don't create a copy.
140 if (MatchReg && SrcRC->getCopyCost() < 0) {
143 // Create the reg, emit the copy.
144 VRBase = MRI->createVirtualRegister(DstRC);
145 bool Emitted = TII->copyRegToReg(*MBB, InsertPos, VRBase, SrcReg,
146 DstRC, SrcRC, Node->getDebugLoc());
148 assert(Emitted && "Unable to issue a copy instruction!\n");
152 SDValue Op(Node, ResNo);
155 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
156 isNew = isNew; // Silence compiler warning.
157 assert(isNew && "Node emitted out of order - early");
160 /// getDstOfCopyToRegUse - If the only use of the specified result number of
161 /// node is a CopyToReg, return its destination register. Return 0 otherwise.
162 unsigned InstrEmitter::getDstOfOnlyCopyToRegUse(SDNode *Node,
163 unsigned ResNo) const {
164 if (!Node->hasOneUse())
167 SDNode *User = *Node->use_begin();
168 if (User->getOpcode() == ISD::CopyToReg &&
169 User->getOperand(2).getNode() == Node &&
170 User->getOperand(2).getResNo() == ResNo) {
171 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
172 if (TargetRegisterInfo::isVirtualRegister(Reg))
178 void InstrEmitter::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
179 const TargetInstrDesc &II,
180 bool IsClone, bool IsCloned,
181 DenseMap<SDValue, unsigned> &VRBaseMap) {
182 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
183 "IMPLICIT_DEF should have been handled as a special case elsewhere!");
185 for (unsigned i = 0; i < II.getNumDefs(); ++i) {
186 // If the specific node value is only used by a CopyToReg and the dest reg
187 // is a vreg in the same register class, use the CopyToReg'd destination
188 // register instead of creating a new vreg.
190 const TargetRegisterClass *RC = II.OpInfo[i].getRegClass(TRI);
191 if (II.OpInfo[i].isOptionalDef()) {
192 // Optional def must be a physical register.
193 unsigned NumResults = CountResults(Node);
194 VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg();
195 assert(TargetRegisterInfo::isPhysicalRegister(VRBase));
196 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
199 if (!VRBase && !IsClone && !IsCloned)
200 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
203 if (User->getOpcode() == ISD::CopyToReg &&
204 User->getOperand(2).getNode() == Node &&
205 User->getOperand(2).getResNo() == i) {
206 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
207 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
208 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
211 MI->addOperand(MachineOperand::CreateReg(Reg, true));
218 // Create the result registers for this node and add the result regs to
219 // the machine instruction.
221 assert(RC && "Isn't a register operand!");
222 VRBase = MRI->createVirtualRegister(RC);
223 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
229 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
230 isNew = isNew; // Silence compiler warning.
231 assert(isNew && "Node emitted out of order - early");
235 /// getVR - Return the virtual register corresponding to the specified result
236 /// of the specified node.
237 unsigned InstrEmitter::getVR(SDValue Op,
238 DenseMap<SDValue, unsigned> &VRBaseMap) {
239 if (Op.isMachineOpcode() &&
240 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
241 // Add an IMPLICIT_DEF instruction before every use.
242 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo());
243 // IMPLICIT_DEF can produce any type of result so its TargetInstrDesc
244 // does not include operand register class info.
246 const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getValueType());
247 VReg = MRI->createVirtualRegister(RC);
249 BuildMI(MBB, Op.getDebugLoc(),
250 TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
254 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
255 assert(I != VRBaseMap.end() && "Node emitted out of order - late");
260 /// AddRegisterOperand - Add the specified register as an operand to the
261 /// specified machine instr. Insert register copies if the register is
262 /// not in the required register class.
264 InstrEmitter::AddRegisterOperand(MachineInstr *MI, SDValue Op,
266 const TargetInstrDesc *II,
267 DenseMap<SDValue, unsigned> &VRBaseMap,
268 bool IsDebug, bool IsClone, bool IsCloned) {
269 assert(Op.getValueType() != MVT::Other &&
270 Op.getValueType() != MVT::Flag &&
271 "Chain and flag operands should occur at end of operand list!");
272 // Get/emit the operand.
273 unsigned VReg = getVR(Op, VRBaseMap);
274 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
276 const TargetInstrDesc &TID = MI->getDesc();
277 bool isOptDef = IIOpNum < TID.getNumOperands() &&
278 TID.OpInfo[IIOpNum].isOptionalDef();
280 // If the instruction requires a register in a different class, create
281 // a new virtual register and copy the value into it.
283 const TargetRegisterClass *SrcRC = MRI->getRegClass(VReg);
284 const TargetRegisterClass *DstRC = 0;
285 if (IIOpNum < II->getNumOperands())
286 DstRC = II->OpInfo[IIOpNum].getRegClass(TRI);
287 assert((DstRC || (TID.isVariadic() && IIOpNum >= TID.getNumOperands())) &&
288 "Don't have operand info for this instruction!");
289 if (DstRC && SrcRC != DstRC && !SrcRC->hasSuperClass(DstRC)) {
290 unsigned NewVReg = MRI->createVirtualRegister(DstRC);
291 bool Emitted = TII->copyRegToReg(*MBB, InsertPos, NewVReg, VReg,
292 DstRC, SrcRC, Op.getNode()->getDebugLoc());
293 assert(Emitted && "Unable to issue a copy instruction!\n");
299 // If this value has only one use, that use is a kill. This is a
300 // conservative approximation. InstrEmitter does trivial coalescing
301 // with CopyFromReg nodes, so don't emit kill flags for them.
302 // Avoid kill flags on Schedule cloned nodes, since there will be
304 // Tied operands are never killed, so we need to check that. And that
305 // means we need to determine the index of the operand.
306 bool isKill = Op.hasOneUse() &&
307 Op.getNode()->getOpcode() != ISD::CopyFromReg &&
309 !(IsClone || IsCloned);
311 unsigned Idx = MI->getNumOperands();
313 MI->getOperand(Idx-1).isReg() && MI->getOperand(Idx-1).isImplicit())
315 bool isTied = MI->getDesc().getOperandConstraint(Idx, TOI::TIED_TO) != -1;
320 MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef,
321 false/*isImp*/, isKill,
322 false/*isDead*/, false/*isUndef*/,
323 false/*isEarlyClobber*/,
324 0/*SubReg*/, IsDebug));
327 /// AddOperand - Add the specified operand to the specified machine instr. II
328 /// specifies the instruction information for the node, and IIOpNum is the
329 /// operand number (in the II) that we are adding. IIOpNum and II are used for
331 void InstrEmitter::AddOperand(MachineInstr *MI, SDValue Op,
333 const TargetInstrDesc *II,
334 DenseMap<SDValue, unsigned> &VRBaseMap,
335 bool IsDebug, bool IsClone, bool IsCloned) {
336 if (Op.isMachineOpcode()) {
337 AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap,
338 IsDebug, IsClone, IsCloned);
339 } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
340 MI->addOperand(MachineOperand::CreateImm(C->getSExtValue()));
341 } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
342 const ConstantFP *CFP = F->getConstantFPValue();
343 MI->addOperand(MachineOperand::CreateFPImm(CFP));
344 } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
345 MI->addOperand(MachineOperand::CreateReg(R->getReg(), false));
346 } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
347 MI->addOperand(MachineOperand::CreateGA(TGA->getGlobal(), TGA->getOffset(),
348 TGA->getTargetFlags()));
349 } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) {
350 MI->addOperand(MachineOperand::CreateMBB(BBNode->getBasicBlock()));
351 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
352 MI->addOperand(MachineOperand::CreateFI(FI->getIndex()));
353 } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
354 MI->addOperand(MachineOperand::CreateJTI(JT->getIndex(),
355 JT->getTargetFlags()));
356 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
357 int Offset = CP->getOffset();
358 unsigned Align = CP->getAlignment();
359 const Type *Type = CP->getType();
360 // MachineConstantPool wants an explicit alignment.
362 Align = TM->getTargetData()->getPrefTypeAlignment(Type);
364 // Alignment of vector types. FIXME!
365 Align = TM->getTargetData()->getTypeAllocSize(Type);
370 MachineConstantPool *MCP = MF->getConstantPool();
371 if (CP->isMachineConstantPoolEntry())
372 Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align);
374 Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align);
375 MI->addOperand(MachineOperand::CreateCPI(Idx, Offset,
376 CP->getTargetFlags()));
377 } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
378 MI->addOperand(MachineOperand::CreateES(ES->getSymbol(),
379 ES->getTargetFlags()));
380 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) {
381 MI->addOperand(MachineOperand::CreateBA(BA->getBlockAddress(),
382 BA->getTargetFlags()));
384 assert(Op.getValueType() != MVT::Other &&
385 Op.getValueType() != MVT::Flag &&
386 "Chain and flag operands should occur at end of operand list!");
387 AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap,
388 IsDebug, IsClone, IsCloned);
392 /// getSuperRegisterRegClass - Returns the register class of a superreg A whose
393 /// "SubIdx"'th sub-register class is the specified register class and whose
394 /// type matches the specified type.
395 static const TargetRegisterClass*
396 getSuperRegisterRegClass(const TargetRegisterClass *TRC,
397 unsigned SubIdx, EVT VT) {
398 // Pick the register class of the superegister for this type
399 for (TargetRegisterInfo::regclass_iterator I = TRC->superregclasses_begin(),
400 E = TRC->superregclasses_end(); I != E; ++I)
401 if ((*I)->hasType(VT) && (*I)->getSubRegisterRegClass(SubIdx) == TRC)
403 assert(false && "Couldn't find the register class");
407 /// EmitSubregNode - Generate machine code for subreg nodes.
409 void InstrEmitter::EmitSubregNode(SDNode *Node,
410 DenseMap<SDValue, unsigned> &VRBaseMap,
411 bool IsClone, bool IsCloned) {
413 unsigned Opc = Node->getMachineOpcode();
415 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
416 // the CopyToReg'd destination register instead of creating a new vreg.
417 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
420 if (User->getOpcode() == ISD::CopyToReg &&
421 User->getOperand(2).getNode() == Node) {
422 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
423 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
430 if (Opc == TargetOpcode::EXTRACT_SUBREG) {
431 // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub
432 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
434 // Figure out the register class to create for the destreg.
435 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
436 const TargetRegisterClass *TRC = MRI->getRegClass(VReg);
437 const TargetRegisterClass *SRC = TRC->getSubRegisterRegClass(SubIdx);
438 assert(SRC && "Invalid subregister index in EXTRACT_SUBREG");
440 // Figure out the register class to create for the destreg.
441 // Note that if we're going to directly use an existing register,
442 // it must be precisely the required class, and not a subclass
444 if (VRBase == 0 || SRC != MRI->getRegClass(VRBase)) {
446 assert(SRC && "Couldn't find source register class");
447 VRBase = MRI->createVirtualRegister(SRC);
450 // Create the extract_subreg machine instruction.
451 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(),
452 TII->get(TargetOpcode::COPY), VRBase);
454 // Add source, and subreg index
455 AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap, /*IsDebug=*/false,
457 assert(TargetRegisterInfo::isVirtualRegister(MI->getOperand(1).getReg()) &&
458 "Cannot yet extract from physregs");
459 MI->getOperand(1).setSubReg(SubIdx);
460 MBB->insert(InsertPos, MI);
461 } else if (Opc == TargetOpcode::INSERT_SUBREG ||
462 Opc == TargetOpcode::SUBREG_TO_REG) {
463 SDValue N0 = Node->getOperand(0);
464 SDValue N1 = Node->getOperand(1);
465 SDValue N2 = Node->getOperand(2);
466 unsigned SubReg = getVR(N1, VRBaseMap);
467 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
468 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
469 const TargetRegisterClass *SRC =
470 getSuperRegisterRegClass(TRC, SubIdx, Node->getValueType(0));
472 // Figure out the register class to create for the destreg.
473 // Note that if we're going to directly use an existing register,
474 // it must be precisely the required class, and not a subclass
476 if (VRBase == 0 || SRC != MRI->getRegClass(VRBase)) {
478 assert(SRC && "Couldn't find source register class");
479 VRBase = MRI->createVirtualRegister(SRC);
482 // Create the insert_subreg or subreg_to_reg machine instruction.
483 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc));
484 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
486 // If creating a subreg_to_reg, then the first input operand
487 // is an implicit value immediate, otherwise it's a register
488 if (Opc == TargetOpcode::SUBREG_TO_REG) {
489 const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
490 MI->addOperand(MachineOperand::CreateImm(SD->getZExtValue()));
492 AddOperand(MI, N0, 0, 0, VRBaseMap, /*IsDebug=*/false,
494 // Add the subregster being inserted
495 AddOperand(MI, N1, 0, 0, VRBaseMap, /*IsDebug=*/false,
497 MI->addOperand(MachineOperand::CreateImm(SubIdx));
498 MBB->insert(InsertPos, MI);
500 llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
503 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
504 isNew = isNew; // Silence compiler warning.
505 assert(isNew && "Node emitted out of order - early");
508 /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
509 /// COPY_TO_REGCLASS is just a normal copy, except that the destination
510 /// register is constrained to be in a particular register class.
513 InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
514 DenseMap<SDValue, unsigned> &VRBaseMap) {
515 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
516 const TargetRegisterClass *SrcRC = MRI->getRegClass(VReg);
518 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
519 const TargetRegisterClass *DstRC = TRI->getRegClass(DstRCIdx);
521 // Create the new VReg in the destination class and emit a copy.
522 unsigned NewVReg = MRI->createVirtualRegister(DstRC);
523 bool Emitted = TII->copyRegToReg(*MBB, InsertPos, NewVReg, VReg,
524 DstRC, SrcRC, Node->getDebugLoc());
526 "Unable to issue a copy instruction for a COPY_TO_REGCLASS node!\n");
530 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
531 isNew = isNew; // Silence compiler warning.
532 assert(isNew && "Node emitted out of order - early");
535 /// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
537 void InstrEmitter::EmitRegSequence(SDNode *Node,
538 DenseMap<SDValue, unsigned> &VRBaseMap,
539 bool IsClone, bool IsCloned) {
540 const TargetRegisterClass *RC = TLI->getRegClassFor(Node->getValueType(0));
541 unsigned NewVReg = MRI->createVirtualRegister(RC);
542 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(),
543 TII->get(TargetOpcode::REG_SEQUENCE), NewVReg);
544 unsigned NumOps = Node->getNumOperands();
545 assert((NumOps & 1) == 0 &&
546 "REG_SEQUENCE must have an even number of operands!");
547 const TargetInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
548 for (unsigned i = 0; i != NumOps; ++i) {
549 SDValue Op = Node->getOperand(i);
551 unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue();
552 unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap);
553 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
554 const TargetRegisterClass *SRC =
555 TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);
557 llvm_unreachable("Invalid subregister index in REG_SEQUENCE");
559 MRI->setRegClass(NewVReg, SRC);
563 AddOperand(MI, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false,
567 MBB->insert(InsertPos, MI);
569 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
570 isNew = isNew; // Silence compiler warning.
571 assert(isNew && "Node emitted out of order - early");
574 /// EmitDbgValue - Generate machine instruction for a dbg_value node.
577 InstrEmitter::EmitDbgValue(SDDbgValue *SD,
578 DenseMap<SDValue, unsigned> &VRBaseMap) {
579 uint64_t Offset = SD->getOffset();
580 MDNode* MDPtr = SD->getMDPtr();
581 DebugLoc DL = SD->getDebugLoc();
583 if (SD->getKind() == SDDbgValue::FRAMEIX) {
584 // Stack address; this needs to be lowered in target-dependent fashion.
585 // EmitTargetCodeForFrameDebugValue is responsible for allocation.
586 unsigned FrameIx = SD->getFrameIx();
587 return TII->emitFrameIndexDebugValue(*MF, FrameIx, Offset, MDPtr, DL);
589 // Otherwise, we're going to create an instruction here.
590 const TargetInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
591 MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
592 if (SD->getKind() == SDDbgValue::SDNODE) {
593 SDNode *Node = SD->getSDNode();
594 SDValue Op = SDValue(Node, SD->getResNo());
595 // It's possible we replaced this SDNode with other(s) and therefore
596 // didn't generate code for it. It's better to catch these cases where
597 // they happen and transfer the debug info, but trying to guarantee that
598 // in all cases would be very fragile; this is a safeguard for any
600 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
601 if (I==VRBaseMap.end())
602 MIB.addReg(0U); // undef
604 AddOperand(&*MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap,
605 /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false);
606 } else if (SD->getKind() == SDDbgValue::CONST) {
607 const Value *V = SD->getConst();
608 if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
609 // FIXME: SDDbgValue constants aren't updated with legalization, so it's
610 // possible to have i128 constants in them at this point. Dwarf writer
611 // does not handle i128 constants at the moment so, as a crude workaround,
612 // just drop the debug info if this happens.
613 if (!CI->getValue().isSignedIntN(64))
616 MIB.addImm(CI->getSExtValue());
617 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
620 // Could be an Undef. In any case insert an Undef so we can see what we
625 // Insert an Undef so we can see what we dropped.
629 MIB.addImm(Offset).addMetadata(MDPtr);
633 /// EmitMachineNode - Generate machine code for a target-specific node and
634 /// needed dependencies.
637 EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
638 DenseMap<SDValue, unsigned> &VRBaseMap) {
639 unsigned Opc = Node->getMachineOpcode();
641 // Handle subreg insert/extract specially
642 if (Opc == TargetOpcode::EXTRACT_SUBREG ||
643 Opc == TargetOpcode::INSERT_SUBREG ||
644 Opc == TargetOpcode::SUBREG_TO_REG) {
645 EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned);
649 // Handle COPY_TO_REGCLASS specially.
650 if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
651 EmitCopyToRegClassNode(Node, VRBaseMap);
655 // Handle REG_SEQUENCE specially.
656 if (Opc == TargetOpcode::REG_SEQUENCE) {
657 EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned);
661 if (Opc == TargetOpcode::IMPLICIT_DEF)
662 // We want a unique VR for each IMPLICIT_DEF use.
665 const TargetInstrDesc &II = TII->get(Opc);
666 unsigned NumResults = CountResults(Node);
667 unsigned NodeOperands = CountOperands(Node);
668 bool HasPhysRegOuts = NumResults > II.getNumDefs() && II.getImplicitDefs()!=0;
670 unsigned NumMIOperands = NodeOperands + NumResults;
672 assert(NumMIOperands >= II.getNumOperands() &&
673 "Too few operands for a variadic node!");
675 assert(NumMIOperands >= II.getNumOperands() &&
676 NumMIOperands <= II.getNumOperands()+II.getNumImplicitDefs() &&
677 "#operands for dag node doesn't match .td file!");
680 // Create the new machine instruction.
681 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), II);
683 // The MachineInstr constructor adds implicit-def operands. Scan through
684 // these to determine which are dead.
685 if (MI->getNumOperands() != 0 &&
686 Node->getValueType(Node->getNumValues()-1) == MVT::Flag) {
687 // First, collect all used registers.
688 SmallVector<unsigned, 8> UsedRegs;
689 for (SDNode *F = Node->getFlaggedUser(); F; F = F->getFlaggedUser())
690 if (F->getOpcode() == ISD::CopyFromReg)
691 UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg());
693 // Collect declared implicit uses.
694 const TargetInstrDesc &TID = TII->get(F->getMachineOpcode());
695 UsedRegs.append(TID.getImplicitUses(),
696 TID.getImplicitUses() + TID.getNumImplicitUses());
697 // In addition to declared implicit uses, we must also check for
698 // direct RegisterSDNode operands.
699 for (unsigned i = 0, e = F->getNumOperands(); i != e; ++i)
700 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) {
701 unsigned Reg = R->getReg();
702 if (Reg != 0 && TargetRegisterInfo::isPhysicalRegister(Reg))
703 UsedRegs.push_back(Reg);
706 // Then mark unused registers as dead.
707 MI->setPhysRegsDeadExcept(UsedRegs, *TRI);
710 // Add result register values for things that are defined by this
713 CreateVirtualRegisters(Node, MI, II, IsClone, IsCloned, VRBaseMap);
715 // Emit all of the actual operands of this instruction, adding them to the
716 // instruction as appropriate.
717 bool HasOptPRefs = II.getNumDefs() > NumResults;
718 assert((!HasOptPRefs || !HasPhysRegOuts) &&
719 "Unable to cope with optional defs and phys regs defs!");
720 unsigned NumSkip = HasOptPRefs ? II.getNumDefs() - NumResults : 0;
721 for (unsigned i = NumSkip; i != NodeOperands; ++i)
722 AddOperand(MI, Node->getOperand(i), i-NumSkip+II.getNumDefs(), &II,
723 VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned);
725 // Transfer all of the memory reference descriptions of this instruction.
726 MI->setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(),
727 cast<MachineSDNode>(Node)->memoperands_end());
729 // Insert the instruction into position in the block. This needs to
730 // happen before any custom inserter hook is called so that the
731 // hook knows where in the block to insert the replacement code.
732 MBB->insert(InsertPos, MI);
734 if (II.usesCustomInsertionHook()) {
735 // Insert this instruction into the basic block using a target
736 // specific inserter which may returns a new basic block.
737 bool AtEnd = InsertPos == MBB->end();
738 MachineBasicBlock *NewMBB = TLI->EmitInstrWithCustomInserter(MI, MBB);
741 InsertPos = NewMBB->end();
747 // Additional results must be an physical register def.
748 if (HasPhysRegOuts) {
749 for (unsigned i = II.getNumDefs(); i < NumResults; ++i) {
750 unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()];
751 if (Node->hasAnyUseOfValue(i))
752 EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
753 // If there are no uses, mark the register as dead now, so that
754 // MachineLICM/Sink can see that it's dead. Don't do this if the
755 // node has a Flag value, for the benefit of targets still using
756 // Flag for values in physregs.
757 else if (Node->getValueType(Node->getNumValues()-1) != MVT::Flag)
758 MI->addRegisterDead(Reg, TRI);
762 // If the instruction has implicit defs and the node doesn't, mark the
763 // implicit def as dead. If the node has any flag outputs, we don't do this
764 // because we don't know what implicit defs are being used by flagged nodes.
765 if (Node->getValueType(Node->getNumValues()-1) != MVT::Flag)
766 if (const unsigned *IDList = II.getImplicitDefs()) {
767 for (unsigned i = NumResults, e = II.getNumDefs()+II.getNumImplicitDefs();
769 MI->addRegisterDead(IDList[i-II.getNumDefs()], TRI);
773 /// EmitSpecialNode - Generate machine code for a target-independent node and
774 /// needed dependencies.
776 EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
777 DenseMap<SDValue, unsigned> &VRBaseMap) {
778 switch (Node->getOpcode()) {
783 llvm_unreachable("This target-independent node should have been selected!");
785 case ISD::EntryToken:
786 llvm_unreachable("EntryToken should have been excluded from the schedule!");
788 case ISD::MERGE_VALUES:
789 case ISD::TokenFactor: // fall thru
791 case ISD::CopyToReg: {
793 SDValue SrcVal = Node->getOperand(2);
794 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
795 SrcReg = R->getReg();
797 SrcReg = getVR(SrcVal, VRBaseMap);
799 unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
800 if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
803 const TargetRegisterClass *SrcTRC = 0, *DstTRC = 0;
804 // Get the register classes of the src/dst.
805 if (TargetRegisterInfo::isVirtualRegister(SrcReg))
806 SrcTRC = MRI->getRegClass(SrcReg);
808 SrcTRC = TRI->getMinimalPhysRegClass(SrcReg,SrcVal.getValueType());
810 if (TargetRegisterInfo::isVirtualRegister(DestReg))
811 DstTRC = MRI->getRegClass(DestReg);
813 DstTRC = TRI->getMinimalPhysRegClass(DestReg,
814 Node->getOperand(1).getValueType());
816 bool Emitted = TII->copyRegToReg(*MBB, InsertPos, DestReg, SrcReg,
817 DstTRC, SrcTRC, Node->getDebugLoc());
818 assert(Emitted && "Unable to issue a copy instruction!\n");
822 case ISD::CopyFromReg: {
823 unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
824 EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap);
827 case ISD::EH_LABEL: {
828 MCSymbol *S = cast<EHLabelSDNode>(Node)->getLabel();
829 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
830 TII->get(TargetOpcode::EH_LABEL)).addSym(S);
834 case ISD::INLINEASM: {
835 unsigned NumOps = Node->getNumOperands();
836 if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag)
837 --NumOps; // Ignore the flag operand.
839 // Create the inline asm machine instruction.
840 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(),
841 TII->get(TargetOpcode::INLINEASM));
843 // Add the asm string as an external symbol operand.
844 SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString);
845 const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol();
846 MI->addOperand(MachineOperand::CreateES(AsmStr));
848 // Add the isAlignStack bit.
849 int64_t isAlignStack =
850 cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_IsAlignStack))->
852 MI->addOperand(MachineOperand::CreateImm(isAlignStack));
854 // Add all of the operand registers to the instruction.
855 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
857 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
858 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
860 MI->addOperand(MachineOperand::CreateImm(Flags));
861 ++i; // Skip the ID value.
863 switch (InlineAsm::getKind(Flags)) {
864 default: llvm_unreachable("Bad flags!");
865 case InlineAsm::Kind_RegDef:
866 for (; NumVals; --NumVals, ++i) {
867 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
868 // FIXME: Add dead flags for physical and virtual registers defined.
869 // For now, mark physical register defs as implicit to help fast
870 // regalloc. This makes inline asm look a lot like calls.
871 MI->addOperand(MachineOperand::CreateReg(Reg, true,
872 /*isImp=*/ TargetRegisterInfo::isPhysicalRegister(Reg)));
875 case InlineAsm::Kind_RegDefEarlyClobber:
876 for (; NumVals; --NumVals, ++i) {
877 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
878 MI->addOperand(MachineOperand::CreateReg(Reg, /*isDef=*/ true,
879 /*isImp=*/ TargetRegisterInfo::isPhysicalRegister(Reg),
883 /*isEarlyClobber=*/ true));
886 case InlineAsm::Kind_RegUse: // Use of register.
887 case InlineAsm::Kind_Imm: // Immediate.
888 case InlineAsm::Kind_Mem: // Addressing mode.
889 // The addressing mode has been selected, just add all of the
890 // operands to the machine instruction.
891 for (; NumVals; --NumVals, ++i)
892 AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap,
893 /*IsDebug=*/false, IsClone, IsCloned);
898 // Get the mdnode from the asm if it exists and add it to the instruction.
899 SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode);
900 const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD();
902 MI->addOperand(MachineOperand::CreateMetadata(MD));
904 MBB->insert(InsertPos, MI);
910 /// InstrEmitter - Construct an InstrEmitter and set it to start inserting
911 /// at the given position in the given block.
912 InstrEmitter::InstrEmitter(MachineBasicBlock *mbb,
913 MachineBasicBlock::iterator insertpos)
914 : MF(mbb->getParent()),
915 MRI(&MF->getRegInfo()),
916 TM(&MF->getTarget()),
917 TII(TM->getInstrInfo()),
918 TRI(TM->getRegisterInfo()),
919 TLI(TM->getTargetLowering()),
920 MBB(mbb), InsertPos(insertpos) {