1 //==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the Emit routines for the SelectionDAG class, which creates
11 // MachineInstrs based on the decisions of the SelectionDAG instruction
14 //===----------------------------------------------------------------------===//
16 #include "InstrEmitter.h"
17 #include "SDNodeDbgValue.h"
18 #include "llvm/ADT/Statistic.h"
19 #include "llvm/CodeGen/MachineConstantPool.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/StackMaps.h"
24 #include "llvm/IR/DataLayout.h"
25 #include "llvm/Support/Debug.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/MathExtras.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Target/TargetLowering.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Target/TargetSubtargetInfo.h"
34 #define DEBUG_TYPE "instr-emitter"
36 /// MinRCSize - Smallest register class we allow when constraining virtual
37 /// registers. If satisfying all register class constraints would require
38 /// using a smaller register class, emit a COPY to a new virtual register
40 const unsigned MinRCSize = 4;
42 /// CountResults - The results of target nodes have register or immediate
43 /// operands first, then an optional chain, and optional glue operands (which do
44 /// not go into the resulting MachineInstr).
45 unsigned InstrEmitter::CountResults(SDNode *Node) {
46 unsigned N = Node->getNumValues();
47 while (N && Node->getValueType(N - 1) == MVT::Glue)
49 if (N && Node->getValueType(N - 1) == MVT::Other)
50 --N; // Skip over chain result.
54 /// countOperands - The inputs to target nodes have any actual inputs first,
55 /// followed by an optional chain operand, then an optional glue operand.
56 /// Compute the number of actual operands that will go into the resulting
59 /// Also count physreg RegisterSDNode and RegisterMaskSDNode operands preceding
60 /// the chain and glue. These operands may be implicit on the machine instr.
61 static unsigned countOperands(SDNode *Node, unsigned NumExpUses,
62 unsigned &NumImpUses) {
63 unsigned N = Node->getNumOperands();
64 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
66 if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
67 --N; // Ignore chain if it exists.
69 // Count RegisterSDNode and RegisterMaskSDNode operands for NumImpUses.
70 NumImpUses = N - NumExpUses;
71 for (unsigned I = N; I > NumExpUses; --I) {
72 if (isa<RegisterMaskSDNode>(Node->getOperand(I - 1)))
74 if (RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Node->getOperand(I - 1)))
75 if (TargetRegisterInfo::isPhysicalRegister(RN->getReg()))
84 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
85 /// implicit physical register output.
87 EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
88 unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) {
90 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
91 // Just use the input register directly!
92 SDValue Op(Node, ResNo);
95 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
96 (void)isNew; // Silence compiler warning.
97 assert(isNew && "Node emitted out of order - early");
101 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
102 // the CopyToReg'd destination register instead of creating a new vreg.
103 bool MatchReg = true;
104 const TargetRegisterClass *UseRC = nullptr;
105 MVT VT = Node->getSimpleValueType(ResNo);
107 // Stick to the preferred register classes for legal types.
108 if (TLI->isTypeLegal(VT))
109 UseRC = TLI->getRegClassFor(VT);
111 if (!IsClone && !IsCloned)
112 for (SDNode *User : Node->uses()) {
114 if (User->getOpcode() == ISD::CopyToReg &&
115 User->getOperand(2).getNode() == Node &&
116 User->getOperand(2).getResNo() == ResNo) {
117 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
118 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
121 } else if (DestReg != SrcReg)
124 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
125 SDValue Op = User->getOperand(i);
126 if (Op.getNode() != Node || Op.getResNo() != ResNo)
128 MVT VT = Node->getSimpleValueType(Op.getResNo());
129 if (VT == MVT::Other || VT == MVT::Glue)
132 if (User->isMachineOpcode()) {
133 const MCInstrDesc &II = TII->get(User->getMachineOpcode());
134 const TargetRegisterClass *RC = nullptr;
135 if (i+II.getNumDefs() < II.getNumOperands()) {
136 RC = TRI->getAllocatableClass(
137 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF));
142 const TargetRegisterClass *ComRC =
143 TRI->getCommonSubClass(UseRC, RC);
144 // If multiple uses expect disjoint register classes, we emit
145 // copies in AddRegisterOperand.
157 const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr;
158 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
160 // Figure out the register class to create for the destreg.
162 DstRC = MRI->getRegClass(VRBase);
164 assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!");
167 DstRC = TLI->getRegClassFor(VT);
170 // If all uses are reading from the src physical register and copying the
171 // register is either impossible or very expensive, then don't create a copy.
172 if (MatchReg && SrcRC->getCopyCost() < 0) {
175 // Create the reg, emit the copy.
176 VRBase = MRI->createVirtualRegister(DstRC);
177 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
178 VRBase).addReg(SrcReg);
181 SDValue Op(Node, ResNo);
184 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
185 (void)isNew; // Silence compiler warning.
186 assert(isNew && "Node emitted out of order - early");
189 /// getDstOfCopyToRegUse - If the only use of the specified result number of
190 /// node is a CopyToReg, return its destination register. Return 0 otherwise.
191 unsigned InstrEmitter::getDstOfOnlyCopyToRegUse(SDNode *Node,
192 unsigned ResNo) const {
193 if (!Node->hasOneUse())
196 SDNode *User = *Node->use_begin();
197 if (User->getOpcode() == ISD::CopyToReg &&
198 User->getOperand(2).getNode() == Node &&
199 User->getOperand(2).getResNo() == ResNo) {
200 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
201 if (TargetRegisterInfo::isVirtualRegister(Reg))
207 void InstrEmitter::CreateVirtualRegisters(SDNode *Node,
208 MachineInstrBuilder &MIB,
209 const MCInstrDesc &II,
210 bool IsClone, bool IsCloned,
211 DenseMap<SDValue, unsigned> &VRBaseMap) {
212 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
213 "IMPLICIT_DEF should have been handled as a special case elsewhere!");
215 unsigned NumResults = CountResults(Node);
216 for (unsigned i = 0; i < II.getNumDefs(); ++i) {
217 // If the specific node value is only used by a CopyToReg and the dest reg
218 // is a vreg in the same register class, use the CopyToReg'd destination
219 // register instead of creating a new vreg.
221 const TargetRegisterClass *RC =
222 TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF));
223 // Always let the value type influence the used register class. The
224 // constraints on the instruction may be too lax to represent the value
225 // type correctly. For example, a 64-bit float (X86::FR64) can't live in
226 // the 32-bit float super-class (X86::FR32).
227 if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(i))) {
228 const TargetRegisterClass *VTRC =
229 TLI->getRegClassFor(Node->getSimpleValueType(i));
231 VTRC = TRI->getCommonSubClass(RC, VTRC);
236 if (II.OpInfo[i].isOptionalDef()) {
237 // Optional def must be a physical register.
238 unsigned NumResults = CountResults(Node);
239 VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg();
240 assert(TargetRegisterInfo::isPhysicalRegister(VRBase));
241 MIB.addReg(VRBase, RegState::Define);
244 if (!VRBase && !IsClone && !IsCloned)
245 for (SDNode *User : Node->uses()) {
246 if (User->getOpcode() == ISD::CopyToReg &&
247 User->getOperand(2).getNode() == Node &&
248 User->getOperand(2).getResNo() == i) {
249 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
250 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
251 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
254 MIB.addReg(VRBase, RegState::Define);
261 // Create the result registers for this node and add the result regs to
262 // the machine instruction.
264 assert(RC && "Isn't a register operand!");
265 VRBase = MRI->createVirtualRegister(RC);
266 MIB.addReg(VRBase, RegState::Define);
269 // If this def corresponds to a result of the SDNode insert the VRBase into
271 if (i < NumResults) {
275 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
276 (void)isNew; // Silence compiler warning.
277 assert(isNew && "Node emitted out of order - early");
282 /// getVR - Return the virtual register corresponding to the specified result
283 /// of the specified node.
284 unsigned InstrEmitter::getVR(SDValue Op,
285 DenseMap<SDValue, unsigned> &VRBaseMap) {
286 if (Op.isMachineOpcode() &&
287 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
288 // Add an IMPLICIT_DEF instruction before every use.
289 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo());
290 // IMPLICIT_DEF can produce any type of result so its MCInstrDesc
291 // does not include operand register class info.
293 const TargetRegisterClass *RC =
294 TLI->getRegClassFor(Op.getSimpleValueType());
295 VReg = MRI->createVirtualRegister(RC);
297 BuildMI(*MBB, InsertPos, Op.getDebugLoc(),
298 TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
302 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
303 assert(I != VRBaseMap.end() && "Node emitted out of order - late");
308 /// AddRegisterOperand - Add the specified register as an operand to the
309 /// specified machine instr. Insert register copies if the register is
310 /// not in the required register class.
312 InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
315 const MCInstrDesc *II,
316 DenseMap<SDValue, unsigned> &VRBaseMap,
317 bool IsDebug, bool IsClone, bool IsCloned) {
318 assert(Op.getValueType() != MVT::Other &&
319 Op.getValueType() != MVT::Glue &&
320 "Chain and glue operands should occur at end of operand list!");
321 // Get/emit the operand.
322 unsigned VReg = getVR(Op, VRBaseMap);
323 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
325 const MCInstrDesc &MCID = MIB->getDesc();
326 bool isOptDef = IIOpNum < MCID.getNumOperands() &&
327 MCID.OpInfo[IIOpNum].isOptionalDef();
329 // If the instruction requires a register in a different class, create
330 // a new virtual register and copy the value into it, but first attempt to
331 // shrink VReg's register class within reason. For example, if VReg == GR32
332 // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
334 const TargetRegisterClass *DstRC = nullptr;
335 if (IIOpNum < II->getNumOperands())
336 DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF));
337 if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) {
338 unsigned NewVReg = MRI->createVirtualRegister(DstRC);
339 BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
340 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
345 // If this value has only one use, that use is a kill. This is a
346 // conservative approximation. InstrEmitter does trivial coalescing
347 // with CopyFromReg nodes, so don't emit kill flags for them.
348 // Avoid kill flags on Schedule cloned nodes, since there will be
350 // Tied operands are never killed, so we need to check that. And that
351 // means we need to determine the index of the operand.
352 bool isKill = Op.hasOneUse() &&
353 Op.getNode()->getOpcode() != ISD::CopyFromReg &&
355 !(IsClone || IsCloned);
357 unsigned Idx = MIB->getNumOperands();
359 MIB->getOperand(Idx-1).isReg() &&
360 MIB->getOperand(Idx-1).isImplicit())
362 bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1;
367 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) |
368 getDebugRegState(IsDebug));
371 /// AddOperand - Add the specified operand to the specified machine instr. II
372 /// specifies the instruction information for the node, and IIOpNum is the
373 /// operand number (in the II) that we are adding.
374 void InstrEmitter::AddOperand(MachineInstrBuilder &MIB,
377 const MCInstrDesc *II,
378 DenseMap<SDValue, unsigned> &VRBaseMap,
379 bool IsDebug, bool IsClone, bool IsCloned) {
380 if (Op.isMachineOpcode()) {
381 AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
382 IsDebug, IsClone, IsCloned);
383 } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
384 MIB.addImm(C->getSExtValue());
385 } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
386 MIB.addFPImm(F->getConstantFPValue());
387 } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
388 // Turn additional physreg operands into implicit uses on non-variadic
389 // instructions. This is used by call and return instructions passing
390 // arguments in registers.
391 bool Imp = II && (IIOpNum >= II->getNumOperands() && !II->isVariadic());
392 MIB.addReg(R->getReg(), getImplRegState(Imp));
393 } else if (RegisterMaskSDNode *RM = dyn_cast<RegisterMaskSDNode>(Op)) {
394 MIB.addRegMask(RM->getRegMask());
395 } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
396 MIB.addGlobalAddress(TGA->getGlobal(), TGA->getOffset(),
397 TGA->getTargetFlags());
398 } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) {
399 MIB.addMBB(BBNode->getBasicBlock());
400 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
401 MIB.addFrameIndex(FI->getIndex());
402 } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
403 MIB.addJumpTableIndex(JT->getIndex(), JT->getTargetFlags());
404 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
405 int Offset = CP->getOffset();
406 unsigned Align = CP->getAlignment();
407 Type *Type = CP->getType();
408 // MachineConstantPool wants an explicit alignment.
411 TM->getSubtargetImpl()->getDataLayout()->getPrefTypeAlignment(Type);
413 // Alignment of vector types. FIXME!
414 Align = TM->getSubtargetImpl()->getDataLayout()->getTypeAllocSize(Type);
419 MachineConstantPool *MCP = MF->getConstantPool();
420 if (CP->isMachineConstantPoolEntry())
421 Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align);
423 Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align);
424 MIB.addConstantPoolIndex(Idx, Offset, CP->getTargetFlags());
425 } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
426 MIB.addExternalSymbol(ES->getSymbol(), ES->getTargetFlags());
427 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) {
428 MIB.addBlockAddress(BA->getBlockAddress(),
430 BA->getTargetFlags());
431 } else if (TargetIndexSDNode *TI = dyn_cast<TargetIndexSDNode>(Op)) {
432 MIB.addTargetIndex(TI->getIndex(), TI->getOffset(), TI->getTargetFlags());
434 assert(Op.getValueType() != MVT::Other &&
435 Op.getValueType() != MVT::Glue &&
436 "Chain and glue operands should occur at end of operand list!");
437 AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
438 IsDebug, IsClone, IsCloned);
442 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
443 MVT VT, DebugLoc DL) {
444 const TargetRegisterClass *VRC = MRI->getRegClass(VReg);
445 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx);
447 // RC is a sub-class of VRC that supports SubIdx. Try to constrain VReg
450 RC = MRI->constrainRegClass(VReg, RC, MinRCSize);
452 // VReg has been adjusted. It can be used with SubIdx operands now.
456 // VReg couldn't be reasonably constrained. Emit a COPY to a new virtual
458 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx);
459 assert(RC && "No legal register class for VT supports that SubIdx");
460 unsigned NewReg = MRI->createVirtualRegister(RC);
461 BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg)
466 /// EmitSubregNode - Generate machine code for subreg nodes.
468 void InstrEmitter::EmitSubregNode(SDNode *Node,
469 DenseMap<SDValue, unsigned> &VRBaseMap,
470 bool IsClone, bool IsCloned) {
472 unsigned Opc = Node->getMachineOpcode();
474 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
475 // the CopyToReg'd destination register instead of creating a new vreg.
476 for (SDNode *User : Node->uses()) {
477 if (User->getOpcode() == ISD::CopyToReg &&
478 User->getOperand(2).getNode() == Node) {
479 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
480 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
487 if (Opc == TargetOpcode::EXTRACT_SUBREG) {
488 // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub. There are no
489 // constraints on the %dst register, COPY can target all legal register
491 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
492 const TargetRegisterClass *TRC =
493 TLI->getRegClassFor(Node->getSimpleValueType(0));
495 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
496 MachineInstr *DefMI = MRI->getVRegDef(VReg);
497 unsigned SrcReg, DstReg, DefSubIdx;
499 TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) &&
500 SubIdx == DefSubIdx &&
501 TRC == MRI->getRegClass(SrcReg)) {
503 // r1025 = s/zext r1024, 4
504 // r1026 = extract_subreg r1025, 4
506 // r1026 = copy r1024
507 VRBase = MRI->createVirtualRegister(TRC);
508 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
509 TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg);
510 MRI->clearKillFlags(SrcReg);
512 // VReg may not support a SubIdx sub-register, and we may need to
513 // constrain its register class or issue a COPY to a compatible register
515 VReg = ConstrainForSubReg(VReg, SubIdx,
516 Node->getOperand(0).getSimpleValueType(),
517 Node->getDebugLoc());
519 // Create the destreg if it is missing.
521 VRBase = MRI->createVirtualRegister(TRC);
523 // Create the extract_subreg machine instruction.
524 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
525 TII->get(TargetOpcode::COPY), VRBase).addReg(VReg, 0, SubIdx);
527 } else if (Opc == TargetOpcode::INSERT_SUBREG ||
528 Opc == TargetOpcode::SUBREG_TO_REG) {
529 SDValue N0 = Node->getOperand(0);
530 SDValue N1 = Node->getOperand(1);
531 SDValue N2 = Node->getOperand(2);
532 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
534 // Figure out the register class to create for the destreg. It should be
535 // the largest legal register class supporting SubIdx sub-registers.
536 // RegisterCoalescer will constrain it further if it decides to eliminate
537 // the INSERT_SUBREG instruction.
539 // %dst = INSERT_SUBREG %src, %sub, SubIdx
541 // is lowered by TwoAddressInstructionPass to:
544 // %dst:SubIdx = COPY %sub
546 // There is no constraint on the %src register class.
548 const TargetRegisterClass *SRC = TLI->getRegClassFor(Node->getSimpleValueType(0));
549 SRC = TRI->getSubClassWithSubReg(SRC, SubIdx);
550 assert(SRC && "No register class supports VT and SubIdx for INSERT_SUBREG");
552 if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase)))
553 VRBase = MRI->createVirtualRegister(SRC);
555 // Create the insert_subreg or subreg_to_reg machine instruction.
556 MachineInstrBuilder MIB =
557 BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc), VRBase);
559 // If creating a subreg_to_reg, then the first input operand
560 // is an implicit value immediate, otherwise it's a register
561 if (Opc == TargetOpcode::SUBREG_TO_REG) {
562 const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
563 MIB.addImm(SD->getZExtValue());
565 AddOperand(MIB, N0, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
567 // Add the subregster being inserted
568 AddOperand(MIB, N1, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
571 MBB->insert(InsertPos, MIB);
573 llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
576 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
577 (void)isNew; // Silence compiler warning.
578 assert(isNew && "Node emitted out of order - early");
581 /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
582 /// COPY_TO_REGCLASS is just a normal copy, except that the destination
583 /// register is constrained to be in a particular register class.
586 InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
587 DenseMap<SDValue, unsigned> &VRBaseMap) {
588 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
590 // Create the new VReg in the destination class and emit a copy.
591 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
592 const TargetRegisterClass *DstRC =
593 TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx));
594 unsigned NewVReg = MRI->createVirtualRegister(DstRC);
595 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
596 NewVReg).addReg(VReg);
599 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
600 (void)isNew; // Silence compiler warning.
601 assert(isNew && "Node emitted out of order - early");
604 /// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
606 void InstrEmitter::EmitRegSequence(SDNode *Node,
607 DenseMap<SDValue, unsigned> &VRBaseMap,
608 bool IsClone, bool IsCloned) {
609 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
610 const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
611 unsigned NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC));
612 const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
613 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II, NewVReg);
614 unsigned NumOps = Node->getNumOperands();
615 assert((NumOps & 1) == 1 &&
616 "REG_SEQUENCE must have an odd number of operands!");
617 for (unsigned i = 1; i != NumOps; ++i) {
618 SDValue Op = Node->getOperand(i);
620 RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(i-1));
621 // Skip physical registers as they don't have a vreg to get and we'll
622 // insert copies for them in TwoAddressInstructionPass anyway.
623 if (!R || !TargetRegisterInfo::isPhysicalRegister(R->getReg())) {
624 unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue();
625 unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap);
626 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
627 const TargetRegisterClass *SRC =
628 TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);
629 if (SRC && SRC != RC) {
630 MRI->setRegClass(NewVReg, SRC);
635 AddOperand(MIB, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false,
639 MBB->insert(InsertPos, MIB);
641 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
642 (void)isNew; // Silence compiler warning.
643 assert(isNew && "Node emitted out of order - early");
646 /// EmitDbgValue - Generate machine instruction for a dbg_value node.
649 InstrEmitter::EmitDbgValue(SDDbgValue *SD,
650 DenseMap<SDValue, unsigned> &VRBaseMap) {
651 uint64_t Offset = SD->getOffset();
652 MDNode* MDPtr = SD->getMDPtr();
653 DebugLoc DL = SD->getDebugLoc();
655 if (SD->getKind() == SDDbgValue::FRAMEIX) {
656 // Stack address; this needs to be lowered in target-dependent fashion.
657 // EmitTargetCodeForFrameDebugValue is responsible for allocation.
658 return BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE))
659 .addFrameIndex(SD->getFrameIx()).addImm(Offset).addMetadata(MDPtr);
661 // Otherwise, we're going to create an instruction here.
662 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
663 MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
664 if (SD->getKind() == SDDbgValue::SDNODE) {
665 SDNode *Node = SD->getSDNode();
666 SDValue Op = SDValue(Node, SD->getResNo());
667 // It's possible we replaced this SDNode with other(s) and therefore
668 // didn't generate code for it. It's better to catch these cases where
669 // they happen and transfer the debug info, but trying to guarantee that
670 // in all cases would be very fragile; this is a safeguard for any
672 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
673 if (I==VRBaseMap.end())
674 MIB.addReg(0U); // undef
676 AddOperand(MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap,
677 /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false);
678 } else if (SD->getKind() == SDDbgValue::CONST) {
679 const Value *V = SD->getConst();
680 if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
681 if (CI->getBitWidth() > 64)
684 MIB.addImm(CI->getSExtValue());
685 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
688 // Could be an Undef. In any case insert an Undef so we can see what we
693 // Insert an Undef so we can see what we dropped.
697 // Indirect addressing is indicated by an Imm as the second parameter.
698 if (SD->isIndirect())
701 assert(Offset == 0 && "direct value cannot have an offset");
702 MIB.addReg(0U, RegState::Debug);
705 MIB.addMetadata(MDPtr);
710 /// EmitMachineNode - Generate machine code for a target-specific node and
711 /// needed dependencies.
714 EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
715 DenseMap<SDValue, unsigned> &VRBaseMap) {
716 unsigned Opc = Node->getMachineOpcode();
718 // Handle subreg insert/extract specially
719 if (Opc == TargetOpcode::EXTRACT_SUBREG ||
720 Opc == TargetOpcode::INSERT_SUBREG ||
721 Opc == TargetOpcode::SUBREG_TO_REG) {
722 EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned);
726 // Handle COPY_TO_REGCLASS specially.
727 if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
728 EmitCopyToRegClassNode(Node, VRBaseMap);
732 // Handle REG_SEQUENCE specially.
733 if (Opc == TargetOpcode::REG_SEQUENCE) {
734 EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned);
738 if (Opc == TargetOpcode::IMPLICIT_DEF)
739 // We want a unique VR for each IMPLICIT_DEF use.
742 const MCInstrDesc &II = TII->get(Opc);
743 unsigned NumResults = CountResults(Node);
744 unsigned NumDefs = II.getNumDefs();
745 const MCPhysReg *ScratchRegs = nullptr;
747 // Handle STACKMAP and PATCHPOINT specially and then use the generic code.
748 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
749 // Stackmaps do not have arguments and do not preserve their calling
750 // convention. However, to simplify runtime support, they clobber the same
751 // scratch registers as AnyRegCC.
752 unsigned CC = CallingConv::AnyReg;
753 if (Opc == TargetOpcode::PATCHPOINT) {
754 CC = Node->getConstantOperandVal(PatchPointOpers::CCPos);
755 NumDefs = NumResults;
757 ScratchRegs = TLI->getScratchRegisters((CallingConv::ID) CC);
760 unsigned NumImpUses = 0;
761 unsigned NodeOperands =
762 countOperands(Node, II.getNumOperands() - NumDefs, NumImpUses);
763 bool HasPhysRegOuts = NumResults > NumDefs && II.getImplicitDefs()!=nullptr;
765 unsigned NumMIOperands = NodeOperands + NumResults;
767 assert(NumMIOperands >= II.getNumOperands() &&
768 "Too few operands for a variadic node!");
770 assert(NumMIOperands >= II.getNumOperands() &&
771 NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() +
773 "#operands for dag node doesn't match .td file!");
776 // Create the new machine instruction.
777 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II);
779 // Add result register values for things that are defined by this
782 CreateVirtualRegisters(Node, MIB, II, IsClone, IsCloned, VRBaseMap);
784 // Emit all of the actual operands of this instruction, adding them to the
785 // instruction as appropriate.
786 bool HasOptPRefs = NumDefs > NumResults;
787 assert((!HasOptPRefs || !HasPhysRegOuts) &&
788 "Unable to cope with optional defs and phys regs defs!");
789 unsigned NumSkip = HasOptPRefs ? NumDefs - NumResults : 0;
790 for (unsigned i = NumSkip; i != NodeOperands; ++i)
791 AddOperand(MIB, Node->getOperand(i), i-NumSkip+NumDefs, &II,
792 VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned);
794 // Add scratch registers as implicit def and early clobber
796 for (unsigned i = 0; ScratchRegs[i]; ++i)
797 MIB.addReg(ScratchRegs[i], RegState::ImplicitDefine |
798 RegState::EarlyClobber);
800 // Transfer all of the memory reference descriptions of this instruction.
801 MIB.setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(),
802 cast<MachineSDNode>(Node)->memoperands_end());
804 // Insert the instruction into position in the block. This needs to
805 // happen before any custom inserter hook is called so that the
806 // hook knows where in the block to insert the replacement code.
807 MBB->insert(InsertPos, MIB);
809 // The MachineInstr may also define physregs instead of virtregs. These
810 // physreg values can reach other instructions in different ways:
812 // 1. When there is a use of a Node value beyond the explicitly defined
813 // virtual registers, we emit a CopyFromReg for one of the implicitly
814 // defined physregs. This only happens when HasPhysRegOuts is true.
816 // 2. A CopyFromReg reading a physreg may be glued to this instruction.
818 // 3. A glued instruction may implicitly use a physreg.
820 // 4. A glued instruction may use a RegisterSDNode operand.
822 // Collect all the used physreg defs, and make sure that any unused physreg
823 // defs are marked as dead.
824 SmallVector<unsigned, 8> UsedRegs;
826 // Additional results must be physical register defs.
827 if (HasPhysRegOuts) {
828 for (unsigned i = NumDefs; i < NumResults; ++i) {
829 unsigned Reg = II.getImplicitDefs()[i - NumDefs];
830 if (!Node->hasAnyUseOfValue(i))
832 // This implicitly defined physreg has a use.
833 UsedRegs.push_back(Reg);
834 EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
838 // Scan the glue chain for any used physregs.
839 if (Node->getValueType(Node->getNumValues()-1) == MVT::Glue) {
840 for (SDNode *F = Node->getGluedUser(); F; F = F->getGluedUser()) {
841 if (F->getOpcode() == ISD::CopyFromReg) {
842 UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg());
844 } else if (F->getOpcode() == ISD::CopyToReg) {
845 // Skip CopyToReg nodes that are internal to the glue chain.
848 // Collect declared implicit uses.
849 const MCInstrDesc &MCID = TII->get(F->getMachineOpcode());
850 UsedRegs.append(MCID.getImplicitUses(),
851 MCID.getImplicitUses() + MCID.getNumImplicitUses());
852 // In addition to declared implicit uses, we must also check for
853 // direct RegisterSDNode operands.
854 for (unsigned i = 0, e = F->getNumOperands(); i != e; ++i)
855 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) {
856 unsigned Reg = R->getReg();
857 if (TargetRegisterInfo::isPhysicalRegister(Reg))
858 UsedRegs.push_back(Reg);
863 // Finally mark unused registers as dead.
864 if (!UsedRegs.empty() || II.getImplicitDefs())
865 MIB->setPhysRegsDeadExcept(UsedRegs, *TRI);
867 // Run post-isel target hook to adjust this instruction if needed.
869 if (II.hasPostISelHook())
871 TLI->AdjustInstrPostInstrSelection(MIB, Node);
874 /// EmitSpecialNode - Generate machine code for a target-independent node and
875 /// needed dependencies.
877 EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
878 DenseMap<SDValue, unsigned> &VRBaseMap) {
879 switch (Node->getOpcode()) {
884 llvm_unreachable("This target-independent node should have been selected!");
885 case ISD::EntryToken:
886 llvm_unreachable("EntryToken should have been excluded from the schedule!");
887 case ISD::MERGE_VALUES:
888 case ISD::TokenFactor: // fall thru
890 case ISD::CopyToReg: {
892 SDValue SrcVal = Node->getOperand(2);
893 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
894 SrcReg = R->getReg();
896 SrcReg = getVR(SrcVal, VRBaseMap);
898 unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
899 if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
902 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
903 DestReg).addReg(SrcReg);
906 case ISD::CopyFromReg: {
907 unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
908 EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap);
911 case ISD::EH_LABEL: {
912 MCSymbol *S = cast<EHLabelSDNode>(Node)->getLabel();
913 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
914 TII->get(TargetOpcode::EH_LABEL)).addSym(S);
918 case ISD::LIFETIME_START:
919 case ISD::LIFETIME_END: {
920 unsigned TarOp = (Node->getOpcode() == ISD::LIFETIME_START) ?
921 TargetOpcode::LIFETIME_START : TargetOpcode::LIFETIME_END;
923 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Node->getOperand(1));
924 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TarOp))
925 .addFrameIndex(FI->getIndex());
929 case ISD::INLINEASM: {
930 unsigned NumOps = Node->getNumOperands();
931 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
932 --NumOps; // Ignore the glue operand.
934 // Create the inline asm machine instruction.
935 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(),
936 TII->get(TargetOpcode::INLINEASM));
938 // Add the asm string as an external symbol operand.
939 SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString);
940 const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol();
941 MIB.addExternalSymbol(AsmStr);
943 // Add the HasSideEffect, isAlignStack, AsmDialect, MayLoad and MayStore
946 cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_ExtraInfo))->
948 MIB.addImm(ExtraInfo);
950 // Remember to operand index of the group flags.
951 SmallVector<unsigned, 8> GroupIdx;
953 // Add all of the operand registers to the instruction.
954 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
956 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
957 const unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
959 GroupIdx.push_back(MIB->getNumOperands());
961 ++i; // Skip the ID value.
963 switch (InlineAsm::getKind(Flags)) {
964 default: llvm_unreachable("Bad flags!");
965 case InlineAsm::Kind_RegDef:
966 for (unsigned j = 0; j != NumVals; ++j, ++i) {
967 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
968 // FIXME: Add dead flags for physical and virtual registers defined.
969 // For now, mark physical register defs as implicit to help fast
970 // regalloc. This makes inline asm look a lot like calls.
971 MIB.addReg(Reg, RegState::Define |
972 getImplRegState(TargetRegisterInfo::isPhysicalRegister(Reg)));
975 case InlineAsm::Kind_RegDefEarlyClobber:
976 case InlineAsm::Kind_Clobber:
977 for (unsigned j = 0; j != NumVals; ++j, ++i) {
978 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
979 MIB.addReg(Reg, RegState::Define | RegState::EarlyClobber |
980 getImplRegState(TargetRegisterInfo::isPhysicalRegister(Reg)));
983 case InlineAsm::Kind_RegUse: // Use of register.
984 case InlineAsm::Kind_Imm: // Immediate.
985 case InlineAsm::Kind_Mem: // Addressing mode.
986 // The addressing mode has been selected, just add all of the
987 // operands to the machine instruction.
988 for (unsigned j = 0; j != NumVals; ++j, ++i)
989 AddOperand(MIB, Node->getOperand(i), 0, nullptr, VRBaseMap,
990 /*IsDebug=*/false, IsClone, IsCloned);
992 // Manually set isTied bits.
993 if (InlineAsm::getKind(Flags) == InlineAsm::Kind_RegUse) {
994 unsigned DefGroup = 0;
995 if (InlineAsm::isUseOperandTiedToDef(Flags, DefGroup)) {
996 unsigned DefIdx = GroupIdx[DefGroup] + 1;
997 unsigned UseIdx = GroupIdx.back() + 1;
998 for (unsigned j = 0; j != NumVals; ++j)
999 MIB->tieOperands(DefIdx + j, UseIdx + j);
1006 // Get the mdnode from the asm if it exists and add it to the instruction.
1007 SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode);
1008 const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD();
1010 MIB.addMetadata(MD);
1012 MBB->insert(InsertPos, MIB);
1018 /// InstrEmitter - Construct an InstrEmitter and set it to start inserting
1019 /// at the given position in the given block.
1020 InstrEmitter::InstrEmitter(MachineBasicBlock *mbb,
1021 MachineBasicBlock::iterator insertpos)
1022 : MF(mbb->getParent()), MRI(&MF->getRegInfo()), TM(&MF->getTarget()),
1023 TII(TM->getSubtargetImpl()->getInstrInfo()),
1024 TRI(TM->getSubtargetImpl()->getRegisterInfo()),
1025 TLI(TM->getSubtargetImpl()->getTargetLowering()), MBB(mbb),
1026 InsertPos(insertpos) {}