1 //==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the Emit routines for the SelectionDAG class, which creates
11 // MachineInstrs based on the decisions of the SelectionDAG instruction
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "instr-emitter"
17 #include "InstrEmitter.h"
18 #include "SDNodeDbgValue.h"
19 #include "llvm/CodeGen/MachineConstantPool.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/Target/TargetData.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Target/TargetInstrInfo.h"
26 #include "llvm/Target/TargetLowering.h"
27 #include "llvm/ADT/Statistic.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/MathExtras.h"
33 /// CountResults - The results of target nodes have register or immediate
34 /// operands first, then an optional chain, and optional flag operands (which do
35 /// not go into the resulting MachineInstr).
36 unsigned InstrEmitter::CountResults(SDNode *Node) {
37 unsigned N = Node->getNumValues();
38 while (N && Node->getValueType(N - 1) == MVT::Glue)
40 if (N && Node->getValueType(N - 1) == MVT::Other)
41 --N; // Skip over chain result.
45 /// CountOperands - The inputs to target nodes have any actual inputs first,
46 /// followed by an optional chain operand, then an optional flag operand.
47 /// Compute the number of actual operands that will go into the resulting
49 unsigned InstrEmitter::CountOperands(SDNode *Node) {
50 unsigned N = Node->getNumOperands();
51 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
53 if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
54 --N; // Ignore chain if it exists.
58 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
59 /// implicit physical register output.
61 EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
62 unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) {
64 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
65 // Just use the input register directly!
66 SDValue Op(Node, ResNo);
69 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
70 isNew = isNew; // Silence compiler warning.
71 assert(isNew && "Node emitted out of order - early");
75 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
76 // the CopyToReg'd destination register instead of creating a new vreg.
78 const TargetRegisterClass *UseRC = NULL;
79 if (!IsClone && !IsCloned)
80 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
84 if (User->getOpcode() == ISD::CopyToReg &&
85 User->getOperand(2).getNode() == Node &&
86 User->getOperand(2).getResNo() == ResNo) {
87 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
88 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
91 } else if (DestReg != SrcReg)
94 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
95 SDValue Op = User->getOperand(i);
96 if (Op.getNode() != Node || Op.getResNo() != ResNo)
98 EVT VT = Node->getValueType(Op.getResNo());
99 if (VT == MVT::Other || VT == MVT::Glue)
102 if (User->isMachineOpcode()) {
103 const TargetInstrDesc &II = TII->get(User->getMachineOpcode());
104 const TargetRegisterClass *RC = 0;
105 if (i+II.getNumDefs() < II.getNumOperands())
106 RC = II.OpInfo[i+II.getNumDefs()].getRegClass(TRI);
110 const TargetRegisterClass *ComRC = getCommonSubClass(UseRC, RC);
111 // If multiple uses expect disjoint register classes, we emit
112 // copies in AddRegisterOperand.
124 EVT VT = Node->getValueType(ResNo);
125 const TargetRegisterClass *SrcRC = 0, *DstRC = 0;
126 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
128 // Figure out the register class to create for the destreg.
130 DstRC = MRI->getRegClass(VRBase);
132 assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!");
135 DstRC = TLI->getRegClassFor(VT);
138 // If all uses are reading from the src physical register and copying the
139 // register is either impossible or very expensive, then don't create a copy.
140 if (MatchReg && SrcRC->getCopyCost() < 0) {
143 // Create the reg, emit the copy.
144 VRBase = MRI->createVirtualRegister(DstRC);
145 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
146 VRBase).addReg(SrcReg);
149 SDValue Op(Node, ResNo);
152 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
153 isNew = isNew; // Silence compiler warning.
154 assert(isNew && "Node emitted out of order - early");
157 /// getDstOfCopyToRegUse - If the only use of the specified result number of
158 /// node is a CopyToReg, return its destination register. Return 0 otherwise.
159 unsigned InstrEmitter::getDstOfOnlyCopyToRegUse(SDNode *Node,
160 unsigned ResNo) const {
161 if (!Node->hasOneUse())
164 SDNode *User = *Node->use_begin();
165 if (User->getOpcode() == ISD::CopyToReg &&
166 User->getOperand(2).getNode() == Node &&
167 User->getOperand(2).getResNo() == ResNo) {
168 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
169 if (TargetRegisterInfo::isVirtualRegister(Reg))
175 void InstrEmitter::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
176 const TargetInstrDesc &II,
177 bool IsClone, bool IsCloned,
178 DenseMap<SDValue, unsigned> &VRBaseMap) {
179 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
180 "IMPLICIT_DEF should have been handled as a special case elsewhere!");
182 for (unsigned i = 0; i < II.getNumDefs(); ++i) {
183 // If the specific node value is only used by a CopyToReg and the dest reg
184 // is a vreg in the same register class, use the CopyToReg'd destination
185 // register instead of creating a new vreg.
187 const TargetRegisterClass *RC = II.OpInfo[i].getRegClass(TRI);
188 if (II.OpInfo[i].isOptionalDef()) {
189 // Optional def must be a physical register.
190 unsigned NumResults = CountResults(Node);
191 VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg();
192 assert(TargetRegisterInfo::isPhysicalRegister(VRBase));
193 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
196 if (!VRBase && !IsClone && !IsCloned)
197 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
200 if (User->getOpcode() == ISD::CopyToReg &&
201 User->getOperand(2).getNode() == Node &&
202 User->getOperand(2).getResNo() == i) {
203 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
204 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
205 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
208 MI->addOperand(MachineOperand::CreateReg(Reg, true));
215 // Create the result registers for this node and add the result regs to
216 // the machine instruction.
218 assert(RC && "Isn't a register operand!");
219 VRBase = MRI->createVirtualRegister(RC);
220 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
226 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
227 isNew = isNew; // Silence compiler warning.
228 assert(isNew && "Node emitted out of order - early");
232 /// getVR - Return the virtual register corresponding to the specified result
233 /// of the specified node.
234 unsigned InstrEmitter::getVR(SDValue Op,
235 DenseMap<SDValue, unsigned> &VRBaseMap) {
236 if (Op.isMachineOpcode() &&
237 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
238 // Add an IMPLICIT_DEF instruction before every use.
239 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo());
240 // IMPLICIT_DEF can produce any type of result so its TargetInstrDesc
241 // does not include operand register class info.
243 const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getValueType());
244 VReg = MRI->createVirtualRegister(RC);
246 BuildMI(*MBB, InsertPos, Op.getDebugLoc(),
247 TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
251 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
252 assert(I != VRBaseMap.end() && "Node emitted out of order - late");
257 /// AddRegisterOperand - Add the specified register as an operand to the
258 /// specified machine instr. Insert register copies if the register is
259 /// not in the required register class.
261 InstrEmitter::AddRegisterOperand(MachineInstr *MI, SDValue Op,
263 const TargetInstrDesc *II,
264 DenseMap<SDValue, unsigned> &VRBaseMap,
265 bool IsDebug, bool IsClone, bool IsCloned) {
266 assert(Op.getValueType() != MVT::Other &&
267 Op.getValueType() != MVT::Glue &&
268 "Chain and flag operands should occur at end of operand list!");
269 // Get/emit the operand.
270 unsigned VReg = getVR(Op, VRBaseMap);
271 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
273 const TargetInstrDesc &TID = MI->getDesc();
274 bool isOptDef = IIOpNum < TID.getNumOperands() &&
275 TID.OpInfo[IIOpNum].isOptionalDef();
277 // If the instruction requires a register in a different class, create
278 // a new virtual register and copy the value into it.
280 const TargetRegisterClass *SrcRC = MRI->getRegClass(VReg);
281 const TargetRegisterClass *DstRC = 0;
282 if (IIOpNum < II->getNumOperands())
283 DstRC = II->OpInfo[IIOpNum].getRegClass(TRI);
284 assert((DstRC || (TID.isVariadic() && IIOpNum >= TID.getNumOperands())) &&
285 "Don't have operand info for this instruction!");
286 if (DstRC && SrcRC != DstRC && !SrcRC->hasSuperClass(DstRC)) {
287 unsigned NewVReg = MRI->createVirtualRegister(DstRC);
288 BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
289 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
294 // If this value has only one use, that use is a kill. This is a
295 // conservative approximation. InstrEmitter does trivial coalescing
296 // with CopyFromReg nodes, so don't emit kill flags for them.
297 // Avoid kill flags on Schedule cloned nodes, since there will be
299 // Tied operands are never killed, so we need to check that. And that
300 // means we need to determine the index of the operand.
301 bool isKill = Op.hasOneUse() &&
302 Op.getNode()->getOpcode() != ISD::CopyFromReg &&
304 !(IsClone || IsCloned);
306 unsigned Idx = MI->getNumOperands();
308 MI->getOperand(Idx-1).isReg() && MI->getOperand(Idx-1).isImplicit())
310 bool isTied = MI->getDesc().getOperandConstraint(Idx, TOI::TIED_TO) != -1;
315 MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef,
316 false/*isImp*/, isKill,
317 false/*isDead*/, false/*isUndef*/,
318 false/*isEarlyClobber*/,
319 0/*SubReg*/, IsDebug));
322 /// AddOperand - Add the specified operand to the specified machine instr. II
323 /// specifies the instruction information for the node, and IIOpNum is the
324 /// operand number (in the II) that we are adding. IIOpNum and II are used for
326 void InstrEmitter::AddOperand(MachineInstr *MI, SDValue Op,
328 const TargetInstrDesc *II,
329 DenseMap<SDValue, unsigned> &VRBaseMap,
330 bool IsDebug, bool IsClone, bool IsCloned) {
331 if (Op.isMachineOpcode()) {
332 AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap,
333 IsDebug, IsClone, IsCloned);
334 } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
335 MI->addOperand(MachineOperand::CreateImm(C->getSExtValue()));
336 } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
337 const ConstantFP *CFP = F->getConstantFPValue();
338 MI->addOperand(MachineOperand::CreateFPImm(CFP));
339 } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
340 MI->addOperand(MachineOperand::CreateReg(R->getReg(), false));
341 } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
342 MI->addOperand(MachineOperand::CreateGA(TGA->getGlobal(), TGA->getOffset(),
343 TGA->getTargetFlags()));
344 } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) {
345 MI->addOperand(MachineOperand::CreateMBB(BBNode->getBasicBlock()));
346 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
347 MI->addOperand(MachineOperand::CreateFI(FI->getIndex()));
348 } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
349 MI->addOperand(MachineOperand::CreateJTI(JT->getIndex(),
350 JT->getTargetFlags()));
351 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
352 int Offset = CP->getOffset();
353 unsigned Align = CP->getAlignment();
354 const Type *Type = CP->getType();
355 // MachineConstantPool wants an explicit alignment.
357 Align = TM->getTargetData()->getPrefTypeAlignment(Type);
359 // Alignment of vector types. FIXME!
360 Align = TM->getTargetData()->getTypeAllocSize(Type);
365 MachineConstantPool *MCP = MF->getConstantPool();
366 if (CP->isMachineConstantPoolEntry())
367 Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align);
369 Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align);
370 MI->addOperand(MachineOperand::CreateCPI(Idx, Offset,
371 CP->getTargetFlags()));
372 } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
373 MI->addOperand(MachineOperand::CreateES(ES->getSymbol(),
374 ES->getTargetFlags()));
375 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) {
376 MI->addOperand(MachineOperand::CreateBA(BA->getBlockAddress(),
377 BA->getTargetFlags()));
379 assert(Op.getValueType() != MVT::Other &&
380 Op.getValueType() != MVT::Glue &&
381 "Chain and flag operands should occur at end of operand list!");
382 AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap,
383 IsDebug, IsClone, IsCloned);
387 /// getSuperRegisterRegClass - Returns the register class of a superreg A whose
388 /// "SubIdx"'th sub-register class is the specified register class and whose
389 /// type matches the specified type.
390 static const TargetRegisterClass*
391 getSuperRegisterRegClass(const TargetRegisterClass *TRC,
392 unsigned SubIdx, EVT VT) {
393 // Pick the register class of the superegister for this type
394 for (TargetRegisterInfo::regclass_iterator I = TRC->superregclasses_begin(),
395 E = TRC->superregclasses_end(); I != E; ++I)
396 if ((*I)->hasType(VT) && (*I)->getSubRegisterRegClass(SubIdx) == TRC)
398 assert(false && "Couldn't find the register class");
402 /// EmitSubregNode - Generate machine code for subreg nodes.
404 void InstrEmitter::EmitSubregNode(SDNode *Node,
405 DenseMap<SDValue, unsigned> &VRBaseMap,
406 bool IsClone, bool IsCloned) {
408 unsigned Opc = Node->getMachineOpcode();
410 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
411 // the CopyToReg'd destination register instead of creating a new vreg.
412 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
415 if (User->getOpcode() == ISD::CopyToReg &&
416 User->getOperand(2).getNode() == Node) {
417 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
418 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
425 if (Opc == TargetOpcode::EXTRACT_SUBREG) {
426 // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub
427 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
429 // Figure out the register class to create for the destreg.
430 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
431 const TargetRegisterClass *TRC = MRI->getRegClass(VReg);
432 const TargetRegisterClass *SRC = TRC->getSubRegisterRegClass(SubIdx);
433 assert(SRC && "Invalid subregister index in EXTRACT_SUBREG");
435 // Figure out the register class to create for the destreg.
436 // Note that if we're going to directly use an existing register,
437 // it must be precisely the required class, and not a subclass
439 if (VRBase == 0 || SRC != MRI->getRegClass(VRBase)) {
441 assert(SRC && "Couldn't find source register class");
442 VRBase = MRI->createVirtualRegister(SRC);
445 // Create the extract_subreg machine instruction.
446 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(),
447 TII->get(TargetOpcode::COPY), VRBase);
449 // Add source, and subreg index
450 AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap, /*IsDebug=*/false,
452 assert(TargetRegisterInfo::isVirtualRegister(MI->getOperand(1).getReg()) &&
453 "Cannot yet extract from physregs");
454 MI->getOperand(1).setSubReg(SubIdx);
455 MBB->insert(InsertPos, MI);
456 } else if (Opc == TargetOpcode::INSERT_SUBREG ||
457 Opc == TargetOpcode::SUBREG_TO_REG) {
458 SDValue N0 = Node->getOperand(0);
459 SDValue N1 = Node->getOperand(1);
460 SDValue N2 = Node->getOperand(2);
461 unsigned SubReg = getVR(N1, VRBaseMap);
462 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
463 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
464 const TargetRegisterClass *SRC =
465 getSuperRegisterRegClass(TRC, SubIdx, Node->getValueType(0));
467 // Figure out the register class to create for the destreg.
468 // Note that if we're going to directly use an existing register,
469 // it must be precisely the required class, and not a subclass
471 if (VRBase == 0 || SRC != MRI->getRegClass(VRBase)) {
473 assert(SRC && "Couldn't find source register class");
474 VRBase = MRI->createVirtualRegister(SRC);
477 // Create the insert_subreg or subreg_to_reg machine instruction.
478 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc));
479 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
481 // If creating a subreg_to_reg, then the first input operand
482 // is an implicit value immediate, otherwise it's a register
483 if (Opc == TargetOpcode::SUBREG_TO_REG) {
484 const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
485 MI->addOperand(MachineOperand::CreateImm(SD->getZExtValue()));
487 AddOperand(MI, N0, 0, 0, VRBaseMap, /*IsDebug=*/false,
489 // Add the subregster being inserted
490 AddOperand(MI, N1, 0, 0, VRBaseMap, /*IsDebug=*/false,
492 MI->addOperand(MachineOperand::CreateImm(SubIdx));
493 MBB->insert(InsertPos, MI);
495 llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
498 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
499 isNew = isNew; // Silence compiler warning.
500 assert(isNew && "Node emitted out of order - early");
503 /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
504 /// COPY_TO_REGCLASS is just a normal copy, except that the destination
505 /// register is constrained to be in a particular register class.
508 InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
509 DenseMap<SDValue, unsigned> &VRBaseMap) {
510 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
512 // Create the new VReg in the destination class and emit a copy.
513 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
514 const TargetRegisterClass *DstRC = TRI->getRegClass(DstRCIdx);
515 unsigned NewVReg = MRI->createVirtualRegister(DstRC);
516 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
517 NewVReg).addReg(VReg);
520 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
521 isNew = isNew; // Silence compiler warning.
522 assert(isNew && "Node emitted out of order - early");
525 /// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
527 void InstrEmitter::EmitRegSequence(SDNode *Node,
528 DenseMap<SDValue, unsigned> &VRBaseMap,
529 bool IsClone, bool IsCloned) {
530 const TargetRegisterClass *RC = TLI->getRegClassFor(Node->getValueType(0));
531 unsigned NewVReg = MRI->createVirtualRegister(RC);
532 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(),
533 TII->get(TargetOpcode::REG_SEQUENCE), NewVReg);
534 unsigned NumOps = Node->getNumOperands();
535 assert((NumOps & 1) == 0 &&
536 "REG_SEQUENCE must have an even number of operands!");
537 const TargetInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
538 for (unsigned i = 0; i != NumOps; ++i) {
539 SDValue Op = Node->getOperand(i);
541 unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue();
542 unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap);
543 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
544 const TargetRegisterClass *SRC =
545 TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);
546 if (SRC && SRC != RC) {
547 MRI->setRegClass(NewVReg, SRC);
551 AddOperand(MI, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false,
555 MBB->insert(InsertPos, MI);
557 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
558 isNew = isNew; // Silence compiler warning.
559 assert(isNew && "Node emitted out of order - early");
562 /// EmitDbgValue - Generate machine instruction for a dbg_value node.
565 InstrEmitter::EmitDbgValue(SDDbgValue *SD,
566 DenseMap<SDValue, unsigned> &VRBaseMap) {
567 uint64_t Offset = SD->getOffset();
568 MDNode* MDPtr = SD->getMDPtr();
569 DebugLoc DL = SD->getDebugLoc();
571 if (SD->getKind() == SDDbgValue::FRAMEIX) {
572 // Stack address; this needs to be lowered in target-dependent fashion.
573 // EmitTargetCodeForFrameDebugValue is responsible for allocation.
574 unsigned FrameIx = SD->getFrameIx();
575 return TII->emitFrameIndexDebugValue(*MF, FrameIx, Offset, MDPtr, DL);
577 // Otherwise, we're going to create an instruction here.
578 const TargetInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
579 MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
580 if (SD->getKind() == SDDbgValue::SDNODE) {
581 SDNode *Node = SD->getSDNode();
582 SDValue Op = SDValue(Node, SD->getResNo());
583 // It's possible we replaced this SDNode with other(s) and therefore
584 // didn't generate code for it. It's better to catch these cases where
585 // they happen and transfer the debug info, but trying to guarantee that
586 // in all cases would be very fragile; this is a safeguard for any
588 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
589 if (I==VRBaseMap.end())
590 MIB.addReg(0U); // undef
592 AddOperand(&*MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap,
593 /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false);
594 } else if (SD->getKind() == SDDbgValue::CONST) {
595 const Value *V = SD->getConst();
596 if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
597 // FIXME: SDDbgValue constants aren't updated with legalization, so it's
598 // possible to have i128 constants in them at this point. Dwarf writer
599 // does not handle i128 constants at the moment so, as a crude workaround,
600 // just drop the debug info if this happens.
601 if (!CI->getValue().isSignedIntN(64))
604 MIB.addImm(CI->getSExtValue());
605 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
608 // Could be an Undef. In any case insert an Undef so we can see what we
613 // Insert an Undef so we can see what we dropped.
617 MIB.addImm(Offset).addMetadata(MDPtr);
621 /// EmitMachineNode - Generate machine code for a target-specific node and
622 /// needed dependencies.
625 EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
626 DenseMap<SDValue, unsigned> &VRBaseMap) {
627 unsigned Opc = Node->getMachineOpcode();
629 // Handle subreg insert/extract specially
630 if (Opc == TargetOpcode::EXTRACT_SUBREG ||
631 Opc == TargetOpcode::INSERT_SUBREG ||
632 Opc == TargetOpcode::SUBREG_TO_REG) {
633 EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned);
637 // Handle COPY_TO_REGCLASS specially.
638 if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
639 EmitCopyToRegClassNode(Node, VRBaseMap);
643 // Handle REG_SEQUENCE specially.
644 if (Opc == TargetOpcode::REG_SEQUENCE) {
645 EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned);
649 if (Opc == TargetOpcode::IMPLICIT_DEF)
650 // We want a unique VR for each IMPLICIT_DEF use.
653 const TargetInstrDesc &II = TII->get(Opc);
654 unsigned NumResults = CountResults(Node);
655 unsigned NodeOperands = CountOperands(Node);
656 bool HasPhysRegOuts = NumResults > II.getNumDefs() && II.getImplicitDefs()!=0;
658 unsigned NumMIOperands = NodeOperands + NumResults;
660 assert(NumMIOperands >= II.getNumOperands() &&
661 "Too few operands for a variadic node!");
663 assert(NumMIOperands >= II.getNumOperands() &&
664 NumMIOperands <= II.getNumOperands()+II.getNumImplicitDefs() &&
665 "#operands for dag node doesn't match .td file!");
668 // Create the new machine instruction.
669 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), II);
671 // The MachineInstr constructor adds implicit-def operands. Scan through
672 // these to determine which are dead.
673 if (MI->getNumOperands() != 0 &&
674 Node->getValueType(Node->getNumValues()-1) == MVT::Glue) {
675 // First, collect all used registers.
676 SmallVector<unsigned, 8> UsedRegs;
677 for (SDNode *F = Node->getFlaggedUser(); F; F = F->getFlaggedUser())
678 if (F->getOpcode() == ISD::CopyFromReg)
679 UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg());
681 // Collect declared implicit uses.
682 const TargetInstrDesc &TID = TII->get(F->getMachineOpcode());
683 UsedRegs.append(TID.getImplicitUses(),
684 TID.getImplicitUses() + TID.getNumImplicitUses());
685 // In addition to declared implicit uses, we must also check for
686 // direct RegisterSDNode operands.
687 for (unsigned i = 0, e = F->getNumOperands(); i != e; ++i)
688 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) {
689 unsigned Reg = R->getReg();
690 if (Reg != 0 && TargetRegisterInfo::isPhysicalRegister(Reg))
691 UsedRegs.push_back(Reg);
694 // Then mark unused registers as dead.
695 MI->setPhysRegsDeadExcept(UsedRegs, *TRI);
698 // Add result register values for things that are defined by this
701 CreateVirtualRegisters(Node, MI, II, IsClone, IsCloned, VRBaseMap);
703 // Emit all of the actual operands of this instruction, adding them to the
704 // instruction as appropriate.
705 bool HasOptPRefs = II.getNumDefs() > NumResults;
706 assert((!HasOptPRefs || !HasPhysRegOuts) &&
707 "Unable to cope with optional defs and phys regs defs!");
708 unsigned NumSkip = HasOptPRefs ? II.getNumDefs() - NumResults : 0;
709 for (unsigned i = NumSkip; i != NodeOperands; ++i)
710 AddOperand(MI, Node->getOperand(i), i-NumSkip+II.getNumDefs(), &II,
711 VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned);
713 // Transfer all of the memory reference descriptions of this instruction.
714 MI->setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(),
715 cast<MachineSDNode>(Node)->memoperands_end());
717 // Insert the instruction into position in the block. This needs to
718 // happen before any custom inserter hook is called so that the
719 // hook knows where in the block to insert the replacement code.
720 MBB->insert(InsertPos, MI);
722 // Additional results must be physical register defs.
723 if (HasPhysRegOuts) {
724 for (unsigned i = II.getNumDefs(); i < NumResults; ++i) {
725 unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()];
726 if (Node->hasAnyUseOfValue(i))
727 EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
728 // If there are no uses, mark the register as dead now, so that
729 // MachineLICM/Sink can see that it's dead. Don't do this if the
730 // node has a Flag value, for the benefit of targets still using
731 // Flag for values in physregs.
732 else if (Node->getValueType(Node->getNumValues()-1) != MVT::Glue)
733 MI->addRegisterDead(Reg, TRI);
737 // If the instruction has implicit defs and the node doesn't, mark the
738 // implicit def as dead. If the node has any flag outputs, we don't do this
739 // because we don't know what implicit defs are being used by flagged nodes.
740 if (Node->getValueType(Node->getNumValues()-1) != MVT::Glue)
741 if (const unsigned *IDList = II.getImplicitDefs()) {
742 for (unsigned i = NumResults, e = II.getNumDefs()+II.getNumImplicitDefs();
744 MI->addRegisterDead(IDList[i-II.getNumDefs()], TRI);
748 /// EmitSpecialNode - Generate machine code for a target-independent node and
749 /// needed dependencies.
751 EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
752 DenseMap<SDValue, unsigned> &VRBaseMap) {
753 switch (Node->getOpcode()) {
758 llvm_unreachable("This target-independent node should have been selected!");
760 case ISD::EntryToken:
761 llvm_unreachable("EntryToken should have been excluded from the schedule!");
763 case ISD::MERGE_VALUES:
764 case ISD::TokenFactor: // fall thru
766 case ISD::CopyToReg: {
768 SDValue SrcVal = Node->getOperand(2);
769 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
770 SrcReg = R->getReg();
772 SrcReg = getVR(SrcVal, VRBaseMap);
774 unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
775 if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
778 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
779 DestReg).addReg(SrcReg);
782 case ISD::CopyFromReg: {
783 unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
784 EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap);
787 case ISD::EH_LABEL: {
788 MCSymbol *S = cast<EHLabelSDNode>(Node)->getLabel();
789 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
790 TII->get(TargetOpcode::EH_LABEL)).addSym(S);
794 case ISD::INLINEASM: {
795 unsigned NumOps = Node->getNumOperands();
796 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
797 --NumOps; // Ignore the flag operand.
799 // Create the inline asm machine instruction.
800 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(),
801 TII->get(TargetOpcode::INLINEASM));
803 // Add the asm string as an external symbol operand.
804 SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString);
805 const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol();
806 MI->addOperand(MachineOperand::CreateES(AsmStr));
808 // Add the isAlignStack bit.
809 int64_t isAlignStack =
810 cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_IsAlignStack))->
812 MI->addOperand(MachineOperand::CreateImm(isAlignStack));
814 // Add all of the operand registers to the instruction.
815 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
817 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
818 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
820 MI->addOperand(MachineOperand::CreateImm(Flags));
821 ++i; // Skip the ID value.
823 switch (InlineAsm::getKind(Flags)) {
824 default: llvm_unreachable("Bad flags!");
825 case InlineAsm::Kind_RegDef:
826 for (; NumVals; --NumVals, ++i) {
827 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
828 // FIXME: Add dead flags for physical and virtual registers defined.
829 // For now, mark physical register defs as implicit to help fast
830 // regalloc. This makes inline asm look a lot like calls.
831 MI->addOperand(MachineOperand::CreateReg(Reg, true,
832 /*isImp=*/ TargetRegisterInfo::isPhysicalRegister(Reg)));
835 case InlineAsm::Kind_RegDefEarlyClobber:
836 for (; NumVals; --NumVals, ++i) {
837 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
838 MI->addOperand(MachineOperand::CreateReg(Reg, /*isDef=*/ true,
839 /*isImp=*/ TargetRegisterInfo::isPhysicalRegister(Reg),
843 /*isEarlyClobber=*/ true));
846 case InlineAsm::Kind_RegUse: // Use of register.
847 case InlineAsm::Kind_Imm: // Immediate.
848 case InlineAsm::Kind_Mem: // Addressing mode.
849 // The addressing mode has been selected, just add all of the
850 // operands to the machine instruction.
851 for (; NumVals; --NumVals, ++i)
852 AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap,
853 /*IsDebug=*/false, IsClone, IsCloned);
858 // Get the mdnode from the asm if it exists and add it to the instruction.
859 SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode);
860 const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD();
862 MI->addOperand(MachineOperand::CreateMetadata(MD));
864 MBB->insert(InsertPos, MI);
870 /// InstrEmitter - Construct an InstrEmitter and set it to start inserting
871 /// at the given position in the given block.
872 InstrEmitter::InstrEmitter(MachineBasicBlock *mbb,
873 MachineBasicBlock::iterator insertpos)
874 : MF(mbb->getParent()),
875 MRI(&MF->getRegInfo()),
876 TM(&MF->getTarget()),
877 TII(TM->getInstrInfo()),
878 TRI(TM->getRegisterInfo()),
879 TLI(TM->getTargetLowering()),
880 MBB(mbb), InsertPos(insertpos) {