1 //==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the Emit routines for the SelectionDAG class, which creates
11 // MachineInstrs based on the decisions of the SelectionDAG instruction
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "instr-emitter"
17 #include "InstrEmitter.h"
18 #include "SDDbgValue.h"
19 #include "llvm/CodeGen/MachineConstantPool.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/Target/TargetData.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Target/TargetInstrInfo.h"
26 #include "llvm/Target/TargetLowering.h"
27 #include "llvm/ADT/Statistic.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/MathExtras.h"
33 /// CountResults - The results of target nodes have register or immediate
34 /// operands first, then an optional chain, and optional flag operands (which do
35 /// not go into the resulting MachineInstr).
36 unsigned InstrEmitter::CountResults(SDNode *Node) {
37 unsigned N = Node->getNumValues();
38 while (N && Node->getValueType(N - 1) == MVT::Flag)
40 if (N && Node->getValueType(N - 1) == MVT::Other)
41 --N; // Skip over chain result.
45 /// CountOperands - The inputs to target nodes have any actual inputs first,
46 /// followed by an optional chain operand, then an optional flag operand.
47 /// Compute the number of actual operands that will go into the resulting
49 unsigned InstrEmitter::CountOperands(SDNode *Node) {
50 unsigned N = Node->getNumOperands();
51 while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag)
53 if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
54 --N; // Ignore chain if it exists.
58 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
59 /// implicit physical register output.
61 EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
62 unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) {
64 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
65 // Just use the input register directly!
66 SDValue Op(Node, ResNo);
69 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
70 isNew = isNew; // Silence compiler warning.
71 assert(isNew && "Node emitted out of order - early");
75 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
76 // the CopyToReg'd destination register instead of creating a new vreg.
78 const TargetRegisterClass *UseRC = NULL;
79 if (!IsClone && !IsCloned)
80 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
84 if (User->getOpcode() == ISD::CopyToReg &&
85 User->getOperand(2).getNode() == Node &&
86 User->getOperand(2).getResNo() == ResNo) {
87 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
88 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
91 } else if (DestReg != SrcReg)
94 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
95 SDValue Op = User->getOperand(i);
96 if (Op.getNode() != Node || Op.getResNo() != ResNo)
98 EVT VT = Node->getValueType(Op.getResNo());
99 if (VT == MVT::Other || VT == MVT::Flag)
102 if (User->isMachineOpcode()) {
103 const TargetInstrDesc &II = TII->get(User->getMachineOpcode());
104 const TargetRegisterClass *RC = 0;
105 if (i+II.getNumDefs() < II.getNumOperands())
106 RC = II.OpInfo[i+II.getNumDefs()].getRegClass(TRI);
110 const TargetRegisterClass *ComRC = getCommonSubClass(UseRC, RC);
111 // If multiple uses expect disjoint register classes, we emit
112 // copies in AddRegisterOperand.
124 EVT VT = Node->getValueType(ResNo);
125 const TargetRegisterClass *SrcRC = 0, *DstRC = 0;
126 SrcRC = TRI->getPhysicalRegisterRegClass(SrcReg, VT);
128 // Figure out the register class to create for the destreg.
130 DstRC = MRI->getRegClass(VRBase);
132 assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!");
135 DstRC = TLI->getRegClassFor(VT);
138 // If all uses are reading from the src physical register and copying the
139 // register is either impossible or very expensive, then don't create a copy.
140 if (MatchReg && SrcRC->getCopyCost() < 0) {
143 // Create the reg, emit the copy.
144 VRBase = MRI->createVirtualRegister(DstRC);
145 bool Emitted = TII->copyRegToReg(*MBB, InsertPos, VRBase, SrcReg,
148 assert(Emitted && "Unable to issue a copy instruction!\n");
152 SDValue Op(Node, ResNo);
155 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
156 isNew = isNew; // Silence compiler warning.
157 assert(isNew && "Node emitted out of order - early");
160 /// getDstOfCopyToRegUse - If the only use of the specified result number of
161 /// node is a CopyToReg, return its destination register. Return 0 otherwise.
162 unsigned InstrEmitter::getDstOfOnlyCopyToRegUse(SDNode *Node,
163 unsigned ResNo) const {
164 if (!Node->hasOneUse())
167 SDNode *User = *Node->use_begin();
168 if (User->getOpcode() == ISD::CopyToReg &&
169 User->getOperand(2).getNode() == Node &&
170 User->getOperand(2).getResNo() == ResNo) {
171 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
172 if (TargetRegisterInfo::isVirtualRegister(Reg))
178 void InstrEmitter::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
179 const TargetInstrDesc &II,
180 bool IsClone, bool IsCloned,
181 DenseMap<SDValue, unsigned> &VRBaseMap) {
182 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
183 "IMPLICIT_DEF should have been handled as a special case elsewhere!");
185 for (unsigned i = 0; i < II.getNumDefs(); ++i) {
186 // If the specific node value is only used by a CopyToReg and the dest reg
187 // is a vreg in the same register class, use the CopyToReg'd destination
188 // register instead of creating a new vreg.
190 const TargetRegisterClass *RC = II.OpInfo[i].getRegClass(TRI);
191 if (II.OpInfo[i].isOptionalDef()) {
192 // Optional def must be a physical register.
193 unsigned NumResults = CountResults(Node);
194 VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg();
195 assert(TargetRegisterInfo::isPhysicalRegister(VRBase));
196 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
199 if (!VRBase && !IsClone && !IsCloned)
200 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
203 if (User->getOpcode() == ISD::CopyToReg &&
204 User->getOperand(2).getNode() == Node &&
205 User->getOperand(2).getResNo() == i) {
206 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
207 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
208 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
211 MI->addOperand(MachineOperand::CreateReg(Reg, true));
218 // Create the result registers for this node and add the result regs to
219 // the machine instruction.
221 assert(RC && "Isn't a register operand!");
222 VRBase = MRI->createVirtualRegister(RC);
223 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
229 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
230 isNew = isNew; // Silence compiler warning.
231 assert(isNew && "Node emitted out of order - early");
235 /// getVR - Return the virtual register corresponding to the specified result
236 /// of the specified node.
237 unsigned InstrEmitter::getVR(SDValue Op,
238 DenseMap<SDValue, unsigned> &VRBaseMap) {
239 if (Op.isMachineOpcode() &&
240 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
241 // Add an IMPLICIT_DEF instruction before every use.
242 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo());
243 // IMPLICIT_DEF can produce any type of result so its TargetInstrDesc
244 // does not include operand register class info.
246 const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getValueType());
247 VReg = MRI->createVirtualRegister(RC);
249 BuildMI(MBB, Op.getDebugLoc(),
250 TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
254 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
255 assert(I != VRBaseMap.end() && "Node emitted out of order - late");
260 /// AddRegisterOperand - Add the specified register as an operand to the
261 /// specified machine instr. Insert register copies if the register is
262 /// not in the required register class.
264 InstrEmitter::AddRegisterOperand(MachineInstr *MI, SDValue Op,
266 const TargetInstrDesc *II,
267 DenseMap<SDValue, unsigned> &VRBaseMap) {
268 assert(Op.getValueType() != MVT::Other &&
269 Op.getValueType() != MVT::Flag &&
270 "Chain and flag operands should occur at end of operand list!");
271 // Get/emit the operand.
272 unsigned VReg = getVR(Op, VRBaseMap);
273 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
275 const TargetInstrDesc &TID = MI->getDesc();
276 bool isOptDef = IIOpNum < TID.getNumOperands() &&
277 TID.OpInfo[IIOpNum].isOptionalDef();
279 // If the instruction requires a register in a different class, create
280 // a new virtual register and copy the value into it.
282 const TargetRegisterClass *SrcRC = MRI->getRegClass(VReg);
283 const TargetRegisterClass *DstRC = 0;
284 if (IIOpNum < II->getNumOperands())
285 DstRC = II->OpInfo[IIOpNum].getRegClass(TRI);
286 assert((DstRC || (TID.isVariadic() && IIOpNum >= TID.getNumOperands())) &&
287 "Don't have operand info for this instruction!");
288 if (DstRC && SrcRC != DstRC && !SrcRC->hasSuperClass(DstRC)) {
289 unsigned NewVReg = MRI->createVirtualRegister(DstRC);
290 bool Emitted = TII->copyRegToReg(*MBB, InsertPos, NewVReg, VReg,
292 assert(Emitted && "Unable to issue a copy instruction!\n");
298 MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef));
301 /// AddOperand - Add the specified operand to the specified machine instr. II
302 /// specifies the instruction information for the node, and IIOpNum is the
303 /// operand number (in the II) that we are adding. IIOpNum and II are used for
305 void InstrEmitter::AddOperand(MachineInstr *MI, SDValue Op,
307 const TargetInstrDesc *II,
308 DenseMap<SDValue, unsigned> &VRBaseMap) {
309 if (Op.isMachineOpcode()) {
310 AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap);
311 } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
312 MI->addOperand(MachineOperand::CreateImm(C->getSExtValue()));
313 } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
314 const ConstantFP *CFP = F->getConstantFPValue();
315 MI->addOperand(MachineOperand::CreateFPImm(CFP));
316 } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
317 MI->addOperand(MachineOperand::CreateReg(R->getReg(), false));
318 } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
319 MI->addOperand(MachineOperand::CreateGA(TGA->getGlobal(), TGA->getOffset(),
320 TGA->getTargetFlags()));
321 } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) {
322 MI->addOperand(MachineOperand::CreateMBB(BBNode->getBasicBlock()));
323 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
324 MI->addOperand(MachineOperand::CreateFI(FI->getIndex()));
325 } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
326 MI->addOperand(MachineOperand::CreateJTI(JT->getIndex(),
327 JT->getTargetFlags()));
328 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
329 int Offset = CP->getOffset();
330 unsigned Align = CP->getAlignment();
331 const Type *Type = CP->getType();
332 // MachineConstantPool wants an explicit alignment.
334 Align = TM->getTargetData()->getPrefTypeAlignment(Type);
336 // Alignment of vector types. FIXME!
337 Align = TM->getTargetData()->getTypeAllocSize(Type);
342 MachineConstantPool *MCP = MF->getConstantPool();
343 if (CP->isMachineConstantPoolEntry())
344 Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align);
346 Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align);
347 MI->addOperand(MachineOperand::CreateCPI(Idx, Offset,
348 CP->getTargetFlags()));
349 } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
350 MI->addOperand(MachineOperand::CreateES(ES->getSymbol(),
351 ES->getTargetFlags()));
352 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) {
353 MI->addOperand(MachineOperand::CreateBA(BA->getBlockAddress(),
354 BA->getTargetFlags()));
356 assert(Op.getValueType() != MVT::Other &&
357 Op.getValueType() != MVT::Flag &&
358 "Chain and flag operands should occur at end of operand list!");
359 AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap);
363 /// getSuperRegisterRegClass - Returns the register class of a superreg A whose
364 /// "SubIdx"'th sub-register class is the specified register class and whose
365 /// type matches the specified type.
366 static const TargetRegisterClass*
367 getSuperRegisterRegClass(const TargetRegisterClass *TRC,
368 unsigned SubIdx, EVT VT) {
369 // Pick the register class of the superegister for this type
370 for (TargetRegisterInfo::regclass_iterator I = TRC->superregclasses_begin(),
371 E = TRC->superregclasses_end(); I != E; ++I)
372 if ((*I)->hasType(VT) && (*I)->getSubRegisterRegClass(SubIdx) == TRC)
374 assert(false && "Couldn't find the register class");
378 /// EmitSubregNode - Generate machine code for subreg nodes.
380 void InstrEmitter::EmitSubregNode(SDNode *Node,
381 DenseMap<SDValue, unsigned> &VRBaseMap){
383 unsigned Opc = Node->getMachineOpcode();
385 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
386 // the CopyToReg'd destination register instead of creating a new vreg.
387 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
390 if (User->getOpcode() == ISD::CopyToReg &&
391 User->getOperand(2).getNode() == Node) {
392 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
393 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
400 if (Opc == TargetOpcode::EXTRACT_SUBREG) {
401 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
403 // Create the extract_subreg machine instruction.
404 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(),
405 TII->get(TargetOpcode::EXTRACT_SUBREG));
407 // Figure out the register class to create for the destreg.
408 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
409 const TargetRegisterClass *TRC = MRI->getRegClass(VReg);
410 const TargetRegisterClass *SRC = TRC->getSubRegisterRegClass(SubIdx);
411 assert(SRC && "Invalid subregister index in EXTRACT_SUBREG");
413 // Figure out the register class to create for the destreg.
414 // Note that if we're going to directly use an existing register,
415 // it must be precisely the required class, and not a subclass
417 if (VRBase == 0 || SRC != MRI->getRegClass(VRBase)) {
419 assert(SRC && "Couldn't find source register class");
420 VRBase = MRI->createVirtualRegister(SRC);
423 // Add def, source, and subreg index
424 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
425 AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap);
426 MI->addOperand(MachineOperand::CreateImm(SubIdx));
427 MBB->insert(InsertPos, MI);
428 } else if (Opc == TargetOpcode::INSERT_SUBREG ||
429 Opc == TargetOpcode::SUBREG_TO_REG) {
430 SDValue N0 = Node->getOperand(0);
431 SDValue N1 = Node->getOperand(1);
432 SDValue N2 = Node->getOperand(2);
433 unsigned SubReg = getVR(N1, VRBaseMap);
434 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
435 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
436 const TargetRegisterClass *SRC =
437 getSuperRegisterRegClass(TRC, SubIdx,
438 Node->getValueType(0));
440 // Figure out the register class to create for the destreg.
441 // Note that if we're going to directly use an existing register,
442 // it must be precisely the required class, and not a subclass
444 if (VRBase == 0 || SRC != MRI->getRegClass(VRBase)) {
446 assert(SRC && "Couldn't find source register class");
447 VRBase = MRI->createVirtualRegister(SRC);
450 // Create the insert_subreg or subreg_to_reg machine instruction.
451 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc));
452 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
454 // If creating a subreg_to_reg, then the first input operand
455 // is an implicit value immediate, otherwise it's a register
456 if (Opc == TargetOpcode::SUBREG_TO_REG) {
457 const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
458 MI->addOperand(MachineOperand::CreateImm(SD->getZExtValue()));
460 AddOperand(MI, N0, 0, 0, VRBaseMap);
461 // Add the subregster being inserted
462 AddOperand(MI, N1, 0, 0, VRBaseMap);
463 MI->addOperand(MachineOperand::CreateImm(SubIdx));
464 MBB->insert(InsertPos, MI);
466 llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
469 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
470 isNew = isNew; // Silence compiler warning.
471 assert(isNew && "Node emitted out of order - early");
474 /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
475 /// COPY_TO_REGCLASS is just a normal copy, except that the destination
476 /// register is constrained to be in a particular register class.
479 InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
480 DenseMap<SDValue, unsigned> &VRBaseMap) {
481 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
482 const TargetRegisterClass *SrcRC = MRI->getRegClass(VReg);
484 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
485 const TargetRegisterClass *DstRC = TRI->getRegClass(DstRCIdx);
487 // Create the new VReg in the destination class and emit a copy.
488 unsigned NewVReg = MRI->createVirtualRegister(DstRC);
489 bool Emitted = TII->copyRegToReg(*MBB, InsertPos, NewVReg, VReg,
492 "Unable to issue a copy instruction for a COPY_TO_REGCLASS node!\n");
496 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
497 isNew = isNew; // Silence compiler warning.
498 assert(isNew && "Node emitted out of order - early");
501 /// EmitDbgValue - Generate any debug info that refers to this Node. Constant
502 /// dbg_value is not handled here.
504 InstrEmitter::EmitDbgValue(SDNode *Node,
505 DenseMap<SDValue, unsigned> &VRBaseMap,
507 if (!Node->getHasDebugValue())
511 unsigned VReg = getVR(SDValue(sd->getSDNode(), sd->getResNo()), VRBaseMap);
512 const TargetInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
513 DebugLoc DL = sd->getDebugLoc();
516 MI = BuildMI(*MF, DL, II).addReg(VReg, RegState::Debug).
517 addImm(sd->getOffset()).
518 addMetadata(sd->getMDPtr());
520 // Insert an Undef so we can see what we dropped.
521 MI = BuildMI(*MF, DL, II).addReg(0U).addImm(sd->getOffset()).
522 addMetadata(sd->getMDPtr());
524 MBB->insert(InsertPos, MI);
527 /// EmitDbgValue - Generate constant debug info. No SDNode is involved.
529 InstrEmitter::EmitDbgValue(SDDbgValue *sd) {
532 const TargetInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
533 DebugLoc DL = sd->getDebugLoc();
535 Value *V = sd->getConst();
536 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
537 MI = BuildMI(*MF, DL, II).addImm(CI->getZExtValue()).
538 addImm(sd->getOffset()).
539 addMetadata(sd->getMDPtr());
540 } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
541 MI = BuildMI(*MF, DL, II).addFPImm(CF).addImm(sd->getOffset()).
542 addMetadata(sd->getMDPtr());
544 // Insert an Undef so we can see what we dropped.
545 MI = BuildMI(*MF, DL, II).addReg(0U).addImm(sd->getOffset()).
546 addMetadata(sd->getMDPtr());
548 MBB->insert(InsertPos, MI);
551 /// EmitNode - Generate machine code for a node and needed dependencies.
553 void InstrEmitter::EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
554 DenseMap<SDValue, unsigned> &VRBaseMap,
555 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) {
556 // If machine instruction
557 if (Node->isMachineOpcode()) {
558 unsigned Opc = Node->getMachineOpcode();
560 // Handle subreg insert/extract specially
561 if (Opc == TargetOpcode::EXTRACT_SUBREG ||
562 Opc == TargetOpcode::INSERT_SUBREG ||
563 Opc == TargetOpcode::SUBREG_TO_REG) {
564 EmitSubregNode(Node, VRBaseMap);
568 // Handle COPY_TO_REGCLASS specially.
569 if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
570 EmitCopyToRegClassNode(Node, VRBaseMap);
574 if (Opc == TargetOpcode::IMPLICIT_DEF)
575 // We want a unique VR for each IMPLICIT_DEF use.
578 const TargetInstrDesc &II = TII->get(Opc);
579 unsigned NumResults = CountResults(Node);
580 unsigned NodeOperands = CountOperands(Node);
581 bool HasPhysRegOuts = (NumResults > II.getNumDefs()) &&
582 II.getImplicitDefs() != 0;
584 unsigned NumMIOperands = NodeOperands + NumResults;
585 assert((II.getNumOperands() == NumMIOperands ||
586 HasPhysRegOuts || II.isVariadic()) &&
587 "#operands for dag node doesn't match .td file!");
590 // Create the new machine instruction.
591 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), II);
593 // Add result register values for things that are defined by this
596 CreateVirtualRegisters(Node, MI, II, IsClone, IsCloned, VRBaseMap);
598 // Emit all of the actual operands of this instruction, adding them to the
599 // instruction as appropriate.
600 bool HasOptPRefs = II.getNumDefs() > NumResults;
601 assert((!HasOptPRefs || !HasPhysRegOuts) &&
602 "Unable to cope with optional defs and phys regs defs!");
603 unsigned NumSkip = HasOptPRefs ? II.getNumDefs() - NumResults : 0;
604 for (unsigned i = NumSkip; i != NodeOperands; ++i)
605 AddOperand(MI, Node->getOperand(i), i-NumSkip+II.getNumDefs(), &II,
608 // Transfer all of the memory reference descriptions of this instruction.
609 MI->setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(),
610 cast<MachineSDNode>(Node)->memoperands_end());
612 if (II.usesCustomInsertionHook()) {
613 // Insert this instruction into the basic block using a target
614 // specific inserter which may returns a new basic block.
615 MBB = TLI->EmitInstrWithCustomInserter(MI, MBB, EM);
616 InsertPos = MBB->end();
618 MBB->insert(InsertPos, MI);
621 // Additional results must be an physical register def.
622 if (HasPhysRegOuts) {
623 for (unsigned i = II.getNumDefs(); i < NumResults; ++i) {
624 unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()];
625 if (Node->hasAnyUseOfValue(i))
626 EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
627 // If there are no uses, mark the register as dead now, so that
628 // MachineLICM/Sink can see that it's dead. Don't do this if the
629 // node has a Flag value, for the benefit of targets still using
630 // Flag for values in physregs.
631 else if (Node->getValueType(Node->getNumValues()-1) != MVT::Flag)
632 MI->addRegisterDead(Reg, TRI);
638 switch (Node->getOpcode()) {
643 llvm_unreachable("This target-independent node should have been selected!");
645 case ISD::EntryToken:
646 llvm_unreachable("EntryToken should have been excluded from the schedule!");
648 case ISD::MERGE_VALUES:
649 case ISD::TokenFactor: // fall thru
651 case ISD::CopyToReg: {
653 SDValue SrcVal = Node->getOperand(2);
654 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
655 SrcReg = R->getReg();
657 SrcReg = getVR(SrcVal, VRBaseMap);
659 unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
660 if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
663 const TargetRegisterClass *SrcTRC = 0, *DstTRC = 0;
664 // Get the register classes of the src/dst.
665 if (TargetRegisterInfo::isVirtualRegister(SrcReg))
666 SrcTRC = MRI->getRegClass(SrcReg);
668 SrcTRC = TRI->getPhysicalRegisterRegClass(SrcReg,SrcVal.getValueType());
670 if (TargetRegisterInfo::isVirtualRegister(DestReg))
671 DstTRC = MRI->getRegClass(DestReg);
673 DstTRC = TRI->getPhysicalRegisterRegClass(DestReg,
674 Node->getOperand(1).getValueType());
676 bool Emitted = TII->copyRegToReg(*MBB, InsertPos, DestReg, SrcReg,
678 assert(Emitted && "Unable to issue a copy instruction!\n");
682 case ISD::CopyFromReg: {
683 unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
684 EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap);
687 case ISD::INLINEASM: {
688 unsigned NumOps = Node->getNumOperands();
689 if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag)
690 --NumOps; // Ignore the flag operand.
692 // Create the inline asm machine instruction.
693 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(),
694 TII->get(TargetOpcode::INLINEASM));
696 // Add the asm string as an external symbol operand.
698 cast<ExternalSymbolSDNode>(Node->getOperand(1))->getSymbol();
699 MI->addOperand(MachineOperand::CreateES(AsmStr));
701 // Add all of the operand registers to the instruction.
702 for (unsigned i = 2; i != NumOps;) {
704 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
705 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
707 MI->addOperand(MachineOperand::CreateImm(Flags));
708 ++i; // Skip the ID value.
711 default: llvm_unreachable("Bad flags!");
712 case 2: // Def of register.
713 for (; NumVals; --NumVals, ++i) {
714 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
715 MI->addOperand(MachineOperand::CreateReg(Reg, true));
718 case 6: // Def of earlyclobber register.
719 for (; NumVals; --NumVals, ++i) {
720 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
721 MI->addOperand(MachineOperand::CreateReg(Reg, true, false, false,
722 false, false, true));
725 case 1: // Use of register.
726 case 3: // Immediate.
727 case 4: // Addressing mode.
728 // The addressing mode has been selected, just add all of the
729 // operands to the machine instruction.
730 for (; NumVals; --NumVals, ++i)
731 AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap);
735 MBB->insert(InsertPos, MI);
741 /// InstrEmitter - Construct an InstrEmitter and set it to start inserting
742 /// at the given position in the given block.
743 InstrEmitter::InstrEmitter(MachineBasicBlock *mbb,
744 MachineBasicBlock::iterator insertpos)
745 : MF(mbb->getParent()),
746 MRI(&MF->getRegInfo()),
747 TM(&MF->getTarget()),
748 TII(TM->getInstrInfo()),
749 TRI(TM->getRegisterInfo()),
750 TLI(TM->getTargetLowering()),
751 MBB(mbb), InsertPos(insertpos) {