1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/CodeGen/PseudoSourceValue.h"
20 #include "llvm/Target/TargetFrameInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/Target/TargetData.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/Target/TargetSubtarget.h"
26 #include "llvm/CallingConv.h"
27 #include "llvm/Constants.h"
28 #include "llvm/DerivedTypes.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Compiler.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/ADT/DenseMap.h"
33 #include "llvm/ADT/SmallVector.h"
34 #include "llvm/ADT/SmallPtrSet.h"
38 //===----------------------------------------------------------------------===//
39 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
40 /// hacks on it until the target machine can handle it. This involves
41 /// eliminating value sizes the machine cannot handle (promoting small sizes to
42 /// large sizes or splitting up large values into small values) as well as
43 /// eliminating operations the machine cannot handle.
45 /// This code also does a small amount of optimization and recognition of idioms
46 /// as part of its processing. For example, if a target does not support a
47 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
48 /// will attempt merge setcc and brc instructions into brcc's.
51 class VISIBILITY_HIDDEN SelectionDAGLegalize {
55 // Libcall insertion helpers.
57 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
58 /// legalized. We use this to ensure that calls are properly serialized
59 /// against each other, including inserted libcalls.
60 SDValue LastCALLSEQ_END;
62 /// IsLegalizingCall - This member is used *only* for purposes of providing
63 /// helpful assertions that a libcall isn't created while another call is
64 /// being legalized (which could lead to non-serialized call sequences).
65 bool IsLegalizingCall;
68 Legal, // The target natively supports this operation.
69 Promote, // This operation should be executed in a larger type.
70 Expand // Try to expand this to other ops, otherwise use a libcall.
73 /// ValueTypeActions - This is a bitvector that contains two bits for each
74 /// value type, where the two bits correspond to the LegalizeAction enum.
75 /// This can be queried with "getTypeAction(VT)".
76 TargetLowering::ValueTypeActionImpl ValueTypeActions;
78 /// LegalizedNodes - For nodes that are of legal width, and that have more
79 /// than one use, this map indicates what regularized operand to use. This
80 /// allows us to avoid legalizing the same thing more than once.
81 DenseMap<SDValue, SDValue> LegalizedNodes;
83 /// PromotedNodes - For nodes that are below legal width, and that have more
84 /// than one use, this map indicates what promoted value to use. This allows
85 /// us to avoid promoting the same thing more than once.
86 DenseMap<SDValue, SDValue> PromotedNodes;
88 /// ExpandedNodes - For nodes that need to be expanded this map indicates
89 /// which which operands are the expanded version of the input. This allows
90 /// us to avoid expanding the same node more than once.
91 DenseMap<SDValue, std::pair<SDValue, SDValue> > ExpandedNodes;
93 /// SplitNodes - For vector nodes that need to be split, this map indicates
94 /// which which operands are the split version of the input. This allows us
95 /// to avoid splitting the same node more than once.
96 std::map<SDValue, std::pair<SDValue, SDValue> > SplitNodes;
98 /// ScalarizedNodes - For nodes that need to be converted from vector types to
99 /// scalar types, this contains the mapping of ones we have already
100 /// processed to the result.
101 std::map<SDValue, SDValue> ScalarizedNodes;
103 void AddLegalizedOperand(SDValue From, SDValue To) {
104 LegalizedNodes.insert(std::make_pair(From, To));
105 // If someone requests legalization of the new node, return itself.
107 LegalizedNodes.insert(std::make_pair(To, To));
109 void AddPromotedOperand(SDValue From, SDValue To) {
110 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
111 assert(isNew && "Got into the map somehow?");
112 // If someone requests legalization of the new node, return itself.
113 LegalizedNodes.insert(std::make_pair(To, To));
117 explicit SelectionDAGLegalize(SelectionDAG &DAG);
119 /// getTypeAction - Return how we should legalize values of this type, either
120 /// it is already legal or we need to expand it into multiple registers of
121 /// smaller integer type, or we need to promote it to a larger type.
122 LegalizeAction getTypeAction(MVT VT) const {
123 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
126 /// isTypeLegal - Return true if this type is legal on this target.
128 bool isTypeLegal(MVT VT) const {
129 return getTypeAction(VT) == Legal;
135 /// HandleOp - Legalize, Promote, or Expand the specified operand as
136 /// appropriate for its type.
137 void HandleOp(SDValue Op);
139 /// LegalizeOp - We know that the specified value has a legal type.
140 /// Recursively ensure that the operands have legal types, then return the
142 SDValue LegalizeOp(SDValue O);
144 /// UnrollVectorOp - We know that the given vector has a legal type, however
145 /// the operation it performs is not legal and is an operation that we have
146 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
147 /// operating on each element individually.
148 SDValue UnrollVectorOp(SDValue O);
150 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
151 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
152 /// is necessary to spill the vector being inserted into to memory, perform
153 /// the insert there, and then read the result back.
154 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
157 /// PromoteOp - Given an operation that produces a value in an invalid type,
158 /// promote it to compute the value into a larger type. The produced value
159 /// will have the correct bits for the low portion of the register, but no
160 /// guarantee is made about the top bits: it may be zero, sign-extended, or
162 SDValue PromoteOp(SDValue O);
164 /// ExpandOp - Expand the specified SDValue into its two component pieces
165 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
166 /// the LegalizedNodes map is filled in for any results that are not expanded,
167 /// the ExpandedNodes map is filled in for any results that are expanded, and
168 /// the Lo/Hi values are returned. This applies to integer types and Vector
170 void ExpandOp(SDValue O, SDValue &Lo, SDValue &Hi);
172 /// SplitVectorOp - Given an operand of vector type, break it down into
173 /// two smaller values.
174 void SplitVectorOp(SDValue O, SDValue &Lo, SDValue &Hi);
176 /// ScalarizeVectorOp - Given an operand of single-element vector type
177 /// (e.g. v1f32), convert it into the equivalent operation that returns a
178 /// scalar (e.g. f32) value.
179 SDValue ScalarizeVectorOp(SDValue O);
181 /// isShuffleLegal - Return non-null if a vector shuffle is legal with the
182 /// specified mask and type. Targets can specify exactly which masks they
183 /// support and the code generator is tasked with not creating illegal masks.
185 /// Note that this will also return true for shuffles that are promoted to a
188 /// If this is a legal shuffle, this method returns the (possibly promoted)
189 /// build_vector Mask. If it's not a legal shuffle, it returns null.
190 SDNode *isShuffleLegal(MVT VT, SDValue Mask) const;
192 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
193 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
195 void LegalizeSetCCOperands(SDValue &LHS, SDValue &RHS, SDValue &CC);
197 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned,
199 SDValue ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source);
201 SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT);
202 SDValue ExpandBUILD_VECTOR(SDNode *Node);
203 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
204 SDValue LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op);
205 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT);
206 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, bool isSigned);
207 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned);
209 SDValue ExpandBSWAP(SDValue Op);
210 SDValue ExpandBitCount(unsigned Opc, SDValue Op);
211 bool ExpandShift(unsigned Opc, SDValue Op, SDValue Amt,
212 SDValue &Lo, SDValue &Hi);
213 void ExpandShiftParts(unsigned NodeOp, SDValue Op, SDValue Amt,
214 SDValue &Lo, SDValue &Hi);
216 SDValue ExpandEXTRACT_SUBVECTOR(SDValue Op);
217 SDValue ExpandEXTRACT_VECTOR_ELT(SDValue Op);
221 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
222 /// specified mask and type. Targets can specify exactly which masks they
223 /// support and the code generator is tasked with not creating illegal masks.
225 /// Note that this will also return true for shuffles that are promoted to a
227 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDValue Mask) const {
228 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
230 case TargetLowering::Legal:
231 case TargetLowering::Custom:
233 case TargetLowering::Promote: {
234 // If this is promoted to a different type, convert the shuffle mask and
235 // ask if it is legal in the promoted type!
236 MVT NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
237 MVT EltVT = NVT.getVectorElementType();
239 // If we changed # elements, change the shuffle mask.
240 unsigned NumEltsGrowth =
241 NVT.getVectorNumElements() / VT.getVectorNumElements();
242 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
243 if (NumEltsGrowth > 1) {
244 // Renumber the elements.
245 SmallVector<SDValue, 8> Ops;
246 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
247 SDValue InOp = Mask.getOperand(i);
248 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
249 if (InOp.getOpcode() == ISD::UNDEF)
250 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
252 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getZExtValue();
253 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, EltVT));
257 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
263 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.getNode() : 0;
266 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
267 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
268 ValueTypeActions(TLI.getValueTypeActions()) {
269 assert(MVT::LAST_VALUETYPE <= 32 &&
270 "Too many value types for ValueTypeActions to hold!");
273 void SelectionDAGLegalize::LegalizeDAG() {
274 LastCALLSEQ_END = DAG.getEntryNode();
275 IsLegalizingCall = false;
277 // The legalize process is inherently a bottom-up recursive process (users
278 // legalize their uses before themselves). Given infinite stack space, we
279 // could just start legalizing on the root and traverse the whole graph. In
280 // practice however, this causes us to run out of stack space on large basic
281 // blocks. To avoid this problem, compute an ordering of the nodes where each
282 // node is only legalized after all of its operands are legalized.
283 DAG.AssignTopologicalOrder();
284 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
285 E = prior(DAG.allnodes_end()); I != next(E); ++I)
286 HandleOp(SDValue(I, 0));
288 // Finally, it's possible the root changed. Get the new root.
289 SDValue OldRoot = DAG.getRoot();
290 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
291 DAG.setRoot(LegalizedNodes[OldRoot]);
293 ExpandedNodes.clear();
294 LegalizedNodes.clear();
295 PromotedNodes.clear();
297 ScalarizedNodes.clear();
299 // Remove dead nodes now.
300 DAG.RemoveDeadNodes();
304 /// FindCallEndFromCallStart - Given a chained node that is part of a call
305 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
306 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
307 if (Node->getOpcode() == ISD::CALLSEQ_END)
309 if (Node->use_empty())
310 return 0; // No CallSeqEnd
312 // The chain is usually at the end.
313 SDValue TheChain(Node, Node->getNumValues()-1);
314 if (TheChain.getValueType() != MVT::Other) {
315 // Sometimes it's at the beginning.
316 TheChain = SDValue(Node, 0);
317 if (TheChain.getValueType() != MVT::Other) {
318 // Otherwise, hunt for it.
319 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
320 if (Node->getValueType(i) == MVT::Other) {
321 TheChain = SDValue(Node, i);
325 // Otherwise, we walked into a node without a chain.
326 if (TheChain.getValueType() != MVT::Other)
331 for (SDNode::use_iterator UI = Node->use_begin(),
332 E = Node->use_end(); UI != E; ++UI) {
334 // Make sure to only follow users of our token chain.
336 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
337 if (User->getOperand(i) == TheChain)
338 if (SDNode *Result = FindCallEndFromCallStart(User))
344 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
345 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
346 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
347 assert(Node && "Didn't find callseq_start for a call??");
348 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
350 assert(Node->getOperand(0).getValueType() == MVT::Other &&
351 "Node doesn't have a token chain argument!");
352 return FindCallStartFromCallEnd(Node->getOperand(0).getNode());
355 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
356 /// see if any uses can reach Dest. If no dest operands can get to dest,
357 /// legalize them, legalize ourself, and return false, otherwise, return true.
359 /// Keep track of the nodes we fine that actually do lead to Dest in
360 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
362 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
363 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
364 if (N == Dest) return true; // N certainly leads to Dest :)
366 // If we've already processed this node and it does lead to Dest, there is no
367 // need to reprocess it.
368 if (NodesLeadingTo.count(N)) return true;
370 // If the first result of this node has been already legalized, then it cannot
372 switch (getTypeAction(N->getValueType(0))) {
374 if (LegalizedNodes.count(SDValue(N, 0))) return false;
377 if (PromotedNodes.count(SDValue(N, 0))) return false;
380 if (ExpandedNodes.count(SDValue(N, 0))) return false;
384 // Okay, this node has not already been legalized. Check and legalize all
385 // operands. If none lead to Dest, then we can legalize this node.
386 bool OperandsLeadToDest = false;
387 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
388 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
389 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo);
391 if (OperandsLeadToDest) {
392 NodesLeadingTo.insert(N);
396 // Okay, this node looks safe, legalize it and return false.
397 HandleOp(SDValue(N, 0));
401 /// HandleOp - Legalize, Promote, or Expand the specified operand as
402 /// appropriate for its type.
403 void SelectionDAGLegalize::HandleOp(SDValue Op) {
404 MVT VT = Op.getValueType();
405 switch (getTypeAction(VT)) {
406 default: assert(0 && "Bad type action!");
407 case Legal: (void)LegalizeOp(Op); break;
408 case Promote: (void)PromoteOp(Op); break;
410 if (!VT.isVector()) {
411 // If this is an illegal scalar, expand it into its two component
414 if (Op.getOpcode() == ISD::TargetConstant)
415 break; // Allow illegal target nodes.
417 } else if (VT.getVectorNumElements() == 1) {
418 // If this is an illegal single element vector, convert it to a
420 (void)ScalarizeVectorOp(Op);
422 // Otherwise, this is an illegal multiple element vector.
423 // Split it in half and legalize both parts.
425 SplitVectorOp(Op, X, Y);
431 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
432 /// a load from the constant pool.
433 static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
434 SelectionDAG &DAG, TargetLowering &TLI) {
437 // If a FP immediate is precise when represented as a float and if the
438 // target can do an extending load from float to double, we put it into
439 // the constant pool as a float, even if it's is statically typed as a
440 // double. This shrinks FP constants and canonicalizes them for targets where
441 // an FP extending load is the same cost as a normal load (such as on the x87
442 // fp stack or PPC FP unit).
443 MVT VT = CFP->getValueType(0);
444 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
446 if (VT!=MVT::f64 && VT!=MVT::f32)
447 assert(0 && "Invalid type expansion");
448 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt(),
449 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
454 while (SVT != MVT::f32) {
455 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1);
456 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
457 // Only do this if the target has a native EXTLOAD instruction from
459 TLI.isLoadXLegal(ISD::EXTLOAD, SVT) &&
460 TLI.ShouldShrinkFPConstant(OrigVT)) {
461 const Type *SType = SVT.getTypeForMVT();
462 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
468 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
469 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
471 return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, DAG.getEntryNode(),
472 CPIdx, PseudoSourceValue::getConstantPool(),
473 0, VT, false, Alignment);
474 return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx,
475 PseudoSourceValue::getConstantPool(), 0, false, Alignment);
479 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
482 SDValue ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT,
483 SelectionDAG &DAG, TargetLowering &TLI) {
484 MVT VT = Node->getValueType(0);
485 MVT SrcVT = Node->getOperand(1).getValueType();
486 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
487 "fcopysign expansion only supported for f32 and f64");
488 MVT SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
490 // First get the sign bit of second operand.
491 SDValue Mask1 = (SrcVT == MVT::f64)
492 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
493 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
494 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
495 SDValue SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
496 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
497 // Shift right or sign-extend it if the two operands have different types.
498 int SizeDiff = SrcNVT.getSizeInBits() - NVT.getSizeInBits();
500 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
501 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
502 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
503 } else if (SizeDiff < 0) {
504 SignBit = DAG.getNode(ISD::ZERO_EXTEND, NVT, SignBit);
505 SignBit = DAG.getNode(ISD::SHL, NVT, SignBit,
506 DAG.getConstant(-SizeDiff, TLI.getShiftAmountTy()));
509 // Clear the sign bit of first operand.
510 SDValue Mask2 = (VT == MVT::f64)
511 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
512 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
513 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
514 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
515 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
517 // Or the value with the sign bit.
518 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
522 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
524 SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
525 TargetLowering &TLI) {
526 SDValue Chain = ST->getChain();
527 SDValue Ptr = ST->getBasePtr();
528 SDValue Val = ST->getValue();
529 MVT VT = Val.getValueType();
530 int Alignment = ST->getAlignment();
531 int SVOffset = ST->getSrcValueOffset();
532 if (ST->getMemoryVT().isFloatingPoint() ||
533 ST->getMemoryVT().isVector()) {
534 // Expand to a bitconvert of the value to the integer type of the
535 // same size, then a (misaligned) int store.
537 if (VT.is128BitVector() || VT == MVT::ppcf128 || VT == MVT::f128)
539 else if (VT.is64BitVector() || VT==MVT::f64)
541 else if (VT==MVT::f32)
544 assert(0 && "Unaligned store of unsupported type");
546 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val);
547 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(),
548 SVOffset, ST->isVolatile(), Alignment);
550 assert(ST->getMemoryVT().isInteger() &&
551 !ST->getMemoryVT().isVector() &&
552 "Unaligned store of unknown type.");
553 // Get the half-size VT
555 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1);
556 int NumBits = NewStoredVT.getSizeInBits();
557 int IncrementSize = NumBits / 8;
559 // Divide the stored value in two parts.
560 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
562 SDValue Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
564 // Store the two parts
565 SDValue Store1, Store2;
566 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr,
567 ST->getSrcValue(), SVOffset, NewStoredVT,
568 ST->isVolatile(), Alignment);
569 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
570 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
571 Alignment = MinAlign(Alignment, IncrementSize);
572 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr,
573 ST->getSrcValue(), SVOffset + IncrementSize,
574 NewStoredVT, ST->isVolatile(), Alignment);
576 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2);
579 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
581 SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
582 TargetLowering &TLI) {
583 int SVOffset = LD->getSrcValueOffset();
584 SDValue Chain = LD->getChain();
585 SDValue Ptr = LD->getBasePtr();
586 MVT VT = LD->getValueType(0);
587 MVT LoadedVT = LD->getMemoryVT();
588 if (VT.isFloatingPoint() || VT.isVector()) {
589 // Expand to a (misaligned) integer load of the same size,
590 // then bitconvert to floating point or vector.
592 if (LoadedVT.is128BitVector() ||
593 LoadedVT == MVT::ppcf128 || LoadedVT == MVT::f128)
595 else if (LoadedVT.is64BitVector() || LoadedVT == MVT::f64)
597 else if (LoadedVT == MVT::f32)
600 assert(0 && "Unaligned load of unsupported type");
602 SDValue newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(),
603 SVOffset, LD->isVolatile(),
605 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad);
606 if (VT.isFloatingPoint() && LoadedVT != VT)
607 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result);
609 SDValue Ops[] = { Result, Chain };
610 return DAG.getMergeValues(Ops, 2);
612 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
613 "Unaligned load of unsupported type.");
615 // Compute the new VT that is half the size of the old one. This is an
617 unsigned NumBits = LoadedVT.getSizeInBits();
619 NewLoadedVT = MVT::getIntegerVT(NumBits/2);
622 unsigned Alignment = LD->getAlignment();
623 unsigned IncrementSize = NumBits / 8;
624 ISD::LoadExtType HiExtType = LD->getExtensionType();
626 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
627 if (HiExtType == ISD::NON_EXTLOAD)
628 HiExtType = ISD::ZEXTLOAD;
630 // Load the value in two parts
632 if (TLI.isLittleEndian()) {
633 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
634 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
635 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
636 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
637 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(),
638 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
639 MinAlign(Alignment, IncrementSize));
641 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset,
642 NewLoadedVT,LD->isVolatile(), Alignment);
643 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
644 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
645 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
646 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
647 MinAlign(Alignment, IncrementSize));
650 // aggregate the two parts
651 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
652 SDValue Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
653 Result = DAG.getNode(ISD::OR, VT, Result, Lo);
655 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
658 SDValue Ops[] = { Result, TF };
659 return DAG.getMergeValues(Ops, 2);
662 /// UnrollVectorOp - We know that the given vector has a legal type, however
663 /// the operation it performs is not legal and is an operation that we have
664 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
665 /// operating on each element individually.
666 SDValue SelectionDAGLegalize::UnrollVectorOp(SDValue Op) {
667 MVT VT = Op.getValueType();
668 assert(isTypeLegal(VT) &&
669 "Caller should expand or promote operands that are not legal!");
670 assert(Op.getNode()->getNumValues() == 1 &&
671 "Can't unroll a vector with multiple results!");
672 unsigned NE = VT.getVectorNumElements();
673 MVT EltVT = VT.getVectorElementType();
675 SmallVector<SDValue, 8> Scalars;
676 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
677 for (unsigned i = 0; i != NE; ++i) {
678 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
679 SDValue Operand = Op.getOperand(j);
680 MVT OperandVT = Operand.getValueType();
681 if (OperandVT.isVector()) {
682 // A vector operand; extract a single element.
683 MVT OperandEltVT = OperandVT.getVectorElementType();
684 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
687 DAG.getConstant(i, MVT::i32));
689 // A scalar operand; just use it as is.
690 Operands[j] = Operand;
693 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT,
694 &Operands[0], Operands.size()));
697 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size());
700 /// GetFPLibCall - Return the right libcall for the given floating point type.
701 static RTLIB::Libcall GetFPLibCall(MVT VT,
702 RTLIB::Libcall Call_F32,
703 RTLIB::Libcall Call_F64,
704 RTLIB::Libcall Call_F80,
705 RTLIB::Libcall Call_PPCF128) {
707 VT == MVT::f32 ? Call_F32 :
708 VT == MVT::f64 ? Call_F64 :
709 VT == MVT::f80 ? Call_F80 :
710 VT == MVT::ppcf128 ? Call_PPCF128 :
711 RTLIB::UNKNOWN_LIBCALL;
714 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
715 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
716 /// is necessary to spill the vector being inserted into to memory, perform
717 /// the insert there, and then read the result back.
718 SDValue SelectionDAGLegalize::
719 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx) {
724 // If the target doesn't support this, we have to spill the input vector
725 // to a temporary stack slot, update the element, then reload it. This is
726 // badness. We could also load the value into a vector register (either
727 // with a "move to register" or "extload into register" instruction, then
728 // permute it into place, if the idx is a constant and if the idx is
729 // supported by the target.
730 MVT VT = Tmp1.getValueType();
731 MVT EltVT = VT.getVectorElementType();
732 MVT IdxVT = Tmp3.getValueType();
733 MVT PtrVT = TLI.getPointerTy();
734 SDValue StackPtr = DAG.CreateStackTemporary(VT);
736 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
739 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr,
740 PseudoSourceValue::getFixedStack(SPFI), 0);
742 // Truncate or zero extend offset to target pointer type.
743 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
744 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
745 // Add the offset to the index.
746 unsigned EltSize = EltVT.getSizeInBits()/8;
747 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
748 SDValue StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
749 // Store the scalar value.
750 Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2,
751 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT);
752 // Load the updated vector.
753 return DAG.getLoad(VT, Ch, StackPtr,
754 PseudoSourceValue::getFixedStack(SPFI), 0);
757 /// LegalizeOp - We know that the specified value has a legal type, and
758 /// that its operands are legal. Now ensure that the operation itself
759 /// is legal, recursively ensuring that the operands' operations remain
761 SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
762 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
765 assert(isTypeLegal(Op.getValueType()) &&
766 "Caller should expand or promote operands that are not legal!");
767 SDNode *Node = Op.getNode();
769 // If this operation defines any values that cannot be represented in a
770 // register on this target, make sure to expand or promote them.
771 if (Node->getNumValues() > 1) {
772 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
773 if (getTypeAction(Node->getValueType(i)) != Legal) {
774 HandleOp(Op.getValue(i));
775 assert(LegalizedNodes.count(Op) &&
776 "Handling didn't add legal operands!");
777 return LegalizedNodes[Op];
781 // Note that LegalizeOp may be reentered even from single-use nodes, which
782 // means that we always must cache transformed nodes.
783 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
784 if (I != LegalizedNodes.end()) return I->second;
786 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
788 bool isCustom = false;
790 switch (Node->getOpcode()) {
791 case ISD::FrameIndex:
792 case ISD::EntryToken:
794 case ISD::BasicBlock:
795 case ISD::TargetFrameIndex:
796 case ISD::TargetJumpTable:
797 case ISD::TargetConstant:
798 case ISD::TargetConstantFP:
799 case ISD::TargetConstantPool:
800 case ISD::TargetGlobalAddress:
801 case ISD::TargetGlobalTLSAddress:
802 case ISD::TargetExternalSymbol:
805 case ISD::MEMOPERAND:
808 // Primitives must all be legal.
809 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
810 "This must be legal!");
813 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
814 // If this is a target node, legalize it by legalizing the operands then
815 // passing it through.
816 SmallVector<SDValue, 8> Ops;
817 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
818 Ops.push_back(LegalizeOp(Node->getOperand(i)));
820 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
822 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
823 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
824 return Result.getValue(Op.getResNo());
826 // Otherwise this is an unhandled builtin node. splat.
828 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
830 assert(0 && "Do not know how to legalize this operator!");
832 case ISD::GLOBAL_OFFSET_TABLE:
833 case ISD::GlobalAddress:
834 case ISD::GlobalTLSAddress:
835 case ISD::ExternalSymbol:
836 case ISD::ConstantPool:
837 case ISD::JumpTable: // Nothing to do.
838 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
839 default: assert(0 && "This action is not supported yet!");
840 case TargetLowering::Custom:
841 Tmp1 = TLI.LowerOperation(Op, DAG);
842 if (Tmp1.getNode()) Result = Tmp1;
843 // FALLTHROUGH if the target doesn't want to lower this op after all.
844 case TargetLowering::Legal:
849 case ISD::RETURNADDR:
850 // The only option for these nodes is to custom lower them. If the target
851 // does not custom lower them, then return zero.
852 Tmp1 = TLI.LowerOperation(Op, DAG);
856 Result = DAG.getConstant(0, TLI.getPointerTy());
858 case ISD::FRAME_TO_ARGS_OFFSET: {
859 MVT VT = Node->getValueType(0);
860 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
861 default: assert(0 && "This action is not supported yet!");
862 case TargetLowering::Custom:
863 Result = TLI.LowerOperation(Op, DAG);
864 if (Result.getNode()) break;
866 case TargetLowering::Legal:
867 Result = DAG.getConstant(0, VT);
872 case ISD::EXCEPTIONADDR: {
873 Tmp1 = LegalizeOp(Node->getOperand(0));
874 MVT VT = Node->getValueType(0);
875 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
876 default: assert(0 && "This action is not supported yet!");
877 case TargetLowering::Expand: {
878 unsigned Reg = TLI.getExceptionAddressRegister();
879 Result = DAG.getCopyFromReg(Tmp1, Reg, VT);
882 case TargetLowering::Custom:
883 Result = TLI.LowerOperation(Op, DAG);
884 if (Result.getNode()) break;
886 case TargetLowering::Legal: {
887 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp1 };
888 Result = DAG.getMergeValues(Ops, 2);
893 if (Result.getNode()->getNumValues() == 1) break;
895 assert(Result.getNode()->getNumValues() == 2 &&
896 "Cannot return more than two values!");
898 // Since we produced two values, make sure to remember that we
899 // legalized both of them.
900 Tmp1 = LegalizeOp(Result);
901 Tmp2 = LegalizeOp(Result.getValue(1));
902 AddLegalizedOperand(Op.getValue(0), Tmp1);
903 AddLegalizedOperand(Op.getValue(1), Tmp2);
904 return Op.getResNo() ? Tmp2 : Tmp1;
905 case ISD::EHSELECTION: {
906 Tmp1 = LegalizeOp(Node->getOperand(0));
907 Tmp2 = LegalizeOp(Node->getOperand(1));
908 MVT VT = Node->getValueType(0);
909 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
910 default: assert(0 && "This action is not supported yet!");
911 case TargetLowering::Expand: {
912 unsigned Reg = TLI.getExceptionSelectorRegister();
913 Result = DAG.getCopyFromReg(Tmp2, Reg, VT);
916 case TargetLowering::Custom:
917 Result = TLI.LowerOperation(Op, DAG);
918 if (Result.getNode()) break;
920 case TargetLowering::Legal: {
921 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp2 };
922 Result = DAG.getMergeValues(Ops, 2);
927 if (Result.getNode()->getNumValues() == 1) break;
929 assert(Result.getNode()->getNumValues() == 2 &&
930 "Cannot return more than two values!");
932 // Since we produced two values, make sure to remember that we
933 // legalized both of them.
934 Tmp1 = LegalizeOp(Result);
935 Tmp2 = LegalizeOp(Result.getValue(1));
936 AddLegalizedOperand(Op.getValue(0), Tmp1);
937 AddLegalizedOperand(Op.getValue(1), Tmp2);
938 return Op.getResNo() ? Tmp2 : Tmp1;
939 case ISD::EH_RETURN: {
940 MVT VT = Node->getValueType(0);
941 // The only "good" option for this node is to custom lower it.
942 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
943 default: assert(0 && "This action is not supported at all!");
944 case TargetLowering::Custom:
945 Result = TLI.LowerOperation(Op, DAG);
946 if (Result.getNode()) break;
948 case TargetLowering::Legal:
949 // Target does not know, how to lower this, lower to noop
950 Result = LegalizeOp(Node->getOperand(0));
955 case ISD::AssertSext:
956 case ISD::AssertZext:
957 Tmp1 = LegalizeOp(Node->getOperand(0));
958 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
960 case ISD::MERGE_VALUES:
961 // Legalize eliminates MERGE_VALUES nodes.
962 Result = Node->getOperand(Op.getResNo());
964 case ISD::CopyFromReg:
965 Tmp1 = LegalizeOp(Node->getOperand(0));
966 Result = Op.getValue(0);
967 if (Node->getNumValues() == 2) {
968 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
970 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
971 if (Node->getNumOperands() == 3) {
972 Tmp2 = LegalizeOp(Node->getOperand(2));
973 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
975 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
977 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
979 // Since CopyFromReg produces two values, make sure to remember that we
980 // legalized both of them.
981 AddLegalizedOperand(Op.getValue(0), Result);
982 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
983 return Result.getValue(Op.getResNo());
985 MVT VT = Op.getValueType();
986 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
987 default: assert(0 && "This action is not supported yet!");
988 case TargetLowering::Expand:
990 Result = DAG.getConstant(0, VT);
991 else if (VT.isFloatingPoint())
992 Result = DAG.getConstantFP(APFloat(APInt(VT.getSizeInBits(), 0)),
995 assert(0 && "Unknown value type!");
997 case TargetLowering::Legal:
1003 case ISD::INTRINSIC_W_CHAIN:
1004 case ISD::INTRINSIC_WO_CHAIN:
1005 case ISD::INTRINSIC_VOID: {
1006 SmallVector<SDValue, 8> Ops;
1007 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1008 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1009 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1011 // Allow the target to custom lower its intrinsics if it wants to.
1012 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
1013 TargetLowering::Custom) {
1014 Tmp3 = TLI.LowerOperation(Result, DAG);
1015 if (Tmp3.getNode()) Result = Tmp3;
1018 if (Result.getNode()->getNumValues() == 1) break;
1020 // Must have return value and chain result.
1021 assert(Result.getNode()->getNumValues() == 2 &&
1022 "Cannot return more than two values!");
1024 // Since loads produce two values, make sure to remember that we
1025 // legalized both of them.
1026 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1027 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1028 return Result.getValue(Op.getResNo());
1031 case ISD::DBG_STOPPOINT:
1032 assert(Node->getNumOperands() == 1 && "Invalid DBG_STOPPOINT node!");
1033 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
1035 switch (TLI.getOperationAction(ISD::DBG_STOPPOINT, MVT::Other)) {
1036 case TargetLowering::Promote:
1037 default: assert(0 && "This action is not supported yet!");
1038 case TargetLowering::Expand: {
1039 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
1040 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
1041 bool useLABEL = TLI.isOperationLegal(ISD::DBG_LABEL, MVT::Other);
1043 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node);
1044 if (MMI && (useDEBUG_LOC || useLABEL)) {
1045 const CompileUnitDesc *CompileUnit = DSP->getCompileUnit();
1046 unsigned SrcFile = MMI->RecordSource(CompileUnit);
1048 unsigned Line = DSP->getLine();
1049 unsigned Col = DSP->getColumn();
1052 SDValue Ops[] = { Tmp1, DAG.getConstant(Line, MVT::i32),
1053 DAG.getConstant(Col, MVT::i32),
1054 DAG.getConstant(SrcFile, MVT::i32) };
1055 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops, 4);
1057 unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile);
1058 Result = DAG.getLabel(ISD::DBG_LABEL, Tmp1, ID);
1061 Result = Tmp1; // chain
1065 case TargetLowering::Legal: {
1066 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1067 if (Action == Legal && Tmp1 == Node->getOperand(0))
1070 SmallVector<SDValue, 8> Ops;
1071 Ops.push_back(Tmp1);
1072 if (Action == Legal) {
1073 Ops.push_back(Node->getOperand(1)); // line # must be legal.
1074 Ops.push_back(Node->getOperand(2)); // col # must be legal.
1076 // Otherwise promote them.
1077 Ops.push_back(PromoteOp(Node->getOperand(1)));
1078 Ops.push_back(PromoteOp(Node->getOperand(2)));
1080 Ops.push_back(Node->getOperand(3)); // filename must be legal.
1081 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
1082 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1089 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!");
1090 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) {
1091 default: assert(0 && "This action is not supported yet!");
1092 case TargetLowering::Legal:
1093 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1094 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1095 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable.
1096 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1098 case TargetLowering::Expand:
1099 Result = LegalizeOp(Node->getOperand(0));
1104 case ISD::DEBUG_LOC:
1105 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
1106 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
1107 default: assert(0 && "This action is not supported yet!");
1108 case TargetLowering::Legal: {
1109 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1110 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1111 if (Action == Legal && Tmp1 == Node->getOperand(0))
1113 if (Action == Legal) {
1114 Tmp2 = Node->getOperand(1);
1115 Tmp3 = Node->getOperand(2);
1116 Tmp4 = Node->getOperand(3);
1118 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1119 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1120 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1122 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1128 case ISD::DBG_LABEL:
1130 assert(Node->getNumOperands() == 1 && "Invalid LABEL node!");
1131 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
1132 default: assert(0 && "This action is not supported yet!");
1133 case TargetLowering::Legal:
1134 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1135 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1137 case TargetLowering::Expand:
1138 Result = LegalizeOp(Node->getOperand(0));
1144 assert(Node->getNumOperands() == 4 && "Invalid Prefetch node!");
1145 switch (TLI.getOperationAction(ISD::PREFETCH, MVT::Other)) {
1146 default: assert(0 && "This action is not supported yet!");
1147 case TargetLowering::Legal:
1148 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1149 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1150 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the rw specifier.
1151 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize locality specifier.
1152 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1154 case TargetLowering::Expand:
1156 Result = LegalizeOp(Node->getOperand(0));
1161 case ISD::MEMBARRIER: {
1162 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!");
1163 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) {
1164 default: assert(0 && "This action is not supported yet!");
1165 case TargetLowering::Legal: {
1167 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1168 for (int x = 1; x < 6; ++x) {
1169 Ops[x] = Node->getOperand(x);
1170 if (!isTypeLegal(Ops[x].getValueType()))
1171 Ops[x] = PromoteOp(Ops[x]);
1173 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6);
1176 case TargetLowering::Expand:
1177 //There is no libgcc call for this op
1178 Result = Node->getOperand(0); // Noop
1184 case ISD::ATOMIC_CMP_SWAP_8:
1185 case ISD::ATOMIC_CMP_SWAP_16:
1186 case ISD::ATOMIC_CMP_SWAP_32:
1187 case ISD::ATOMIC_CMP_SWAP_64: {
1188 unsigned int num_operands = 4;
1189 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1191 for (unsigned int x = 0; x < num_operands; ++x)
1192 Ops[x] = LegalizeOp(Node->getOperand(x));
1193 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1195 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1196 default: assert(0 && "This action is not supported yet!");
1197 case TargetLowering::Custom:
1198 Result = TLI.LowerOperation(Result, DAG);
1200 case TargetLowering::Legal:
1203 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1204 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1205 return Result.getValue(Op.getResNo());
1207 case ISD::ATOMIC_LOAD_ADD_8:
1208 case ISD::ATOMIC_LOAD_SUB_8:
1209 case ISD::ATOMIC_LOAD_AND_8:
1210 case ISD::ATOMIC_LOAD_OR_8:
1211 case ISD::ATOMIC_LOAD_XOR_8:
1212 case ISD::ATOMIC_LOAD_NAND_8:
1213 case ISD::ATOMIC_LOAD_MIN_8:
1214 case ISD::ATOMIC_LOAD_MAX_8:
1215 case ISD::ATOMIC_LOAD_UMIN_8:
1216 case ISD::ATOMIC_LOAD_UMAX_8:
1217 case ISD::ATOMIC_SWAP_8:
1218 case ISD::ATOMIC_LOAD_ADD_16:
1219 case ISD::ATOMIC_LOAD_SUB_16:
1220 case ISD::ATOMIC_LOAD_AND_16:
1221 case ISD::ATOMIC_LOAD_OR_16:
1222 case ISD::ATOMIC_LOAD_XOR_16:
1223 case ISD::ATOMIC_LOAD_NAND_16:
1224 case ISD::ATOMIC_LOAD_MIN_16:
1225 case ISD::ATOMIC_LOAD_MAX_16:
1226 case ISD::ATOMIC_LOAD_UMIN_16:
1227 case ISD::ATOMIC_LOAD_UMAX_16:
1228 case ISD::ATOMIC_SWAP_16:
1229 case ISD::ATOMIC_LOAD_ADD_32:
1230 case ISD::ATOMIC_LOAD_SUB_32:
1231 case ISD::ATOMIC_LOAD_AND_32:
1232 case ISD::ATOMIC_LOAD_OR_32:
1233 case ISD::ATOMIC_LOAD_XOR_32:
1234 case ISD::ATOMIC_LOAD_NAND_32:
1235 case ISD::ATOMIC_LOAD_MIN_32:
1236 case ISD::ATOMIC_LOAD_MAX_32:
1237 case ISD::ATOMIC_LOAD_UMIN_32:
1238 case ISD::ATOMIC_LOAD_UMAX_32:
1239 case ISD::ATOMIC_SWAP_32:
1240 case ISD::ATOMIC_LOAD_ADD_64:
1241 case ISD::ATOMIC_LOAD_SUB_64:
1242 case ISD::ATOMIC_LOAD_AND_64:
1243 case ISD::ATOMIC_LOAD_OR_64:
1244 case ISD::ATOMIC_LOAD_XOR_64:
1245 case ISD::ATOMIC_LOAD_NAND_64:
1246 case ISD::ATOMIC_LOAD_MIN_64:
1247 case ISD::ATOMIC_LOAD_MAX_64:
1248 case ISD::ATOMIC_LOAD_UMIN_64:
1249 case ISD::ATOMIC_LOAD_UMAX_64:
1250 case ISD::ATOMIC_SWAP_64: {
1251 unsigned int num_operands = 3;
1252 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1254 for (unsigned int x = 0; x < num_operands; ++x)
1255 Ops[x] = LegalizeOp(Node->getOperand(x));
1256 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1258 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1259 default: assert(0 && "This action is not supported yet!");
1260 case TargetLowering::Custom:
1261 Result = TLI.LowerOperation(Result, DAG);
1263 case TargetLowering::Legal:
1266 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1267 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1268 return Result.getValue(Op.getResNo());
1270 case ISD::Constant: {
1271 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1273 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1275 // We know we don't need to expand constants here, constants only have one
1276 // value and we check that it is fine above.
1278 if (opAction == TargetLowering::Custom) {
1279 Tmp1 = TLI.LowerOperation(Result, DAG);
1285 case ISD::ConstantFP: {
1286 // Spill FP immediates to the constant pool if the target cannot directly
1287 // codegen them. Targets often have some immediate values that can be
1288 // efficiently generated into an FP register without a load. We explicitly
1289 // leave these constants as ConstantFP nodes for the target to deal with.
1290 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1292 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1293 default: assert(0 && "This action is not supported yet!");
1294 case TargetLowering::Legal:
1296 case TargetLowering::Custom:
1297 Tmp3 = TLI.LowerOperation(Result, DAG);
1298 if (Tmp3.getNode()) {
1303 case TargetLowering::Expand: {
1304 // Check to see if this FP immediate is already legal.
1305 bool isLegal = false;
1306 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1307 E = TLI.legal_fpimm_end(); I != E; ++I) {
1308 if (CFP->isExactlyValue(*I)) {
1313 // If this is a legal constant, turn it into a TargetConstantFP node.
1316 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1321 case ISD::TokenFactor:
1322 if (Node->getNumOperands() == 2) {
1323 Tmp1 = LegalizeOp(Node->getOperand(0));
1324 Tmp2 = LegalizeOp(Node->getOperand(1));
1325 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1326 } else if (Node->getNumOperands() == 3) {
1327 Tmp1 = LegalizeOp(Node->getOperand(0));
1328 Tmp2 = LegalizeOp(Node->getOperand(1));
1329 Tmp3 = LegalizeOp(Node->getOperand(2));
1330 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1332 SmallVector<SDValue, 8> Ops;
1333 // Legalize the operands.
1334 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1335 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1336 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1340 case ISD::FORMAL_ARGUMENTS:
1342 // The only option for this is to custom lower it.
1343 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1344 assert(Tmp3.getNode() && "Target didn't custom lower this node!");
1345 // A call within a calling sequence must be legalized to something
1346 // other than the normal CALLSEQ_END. Violating this gets Legalize
1347 // into an infinite loop.
1348 assert ((!IsLegalizingCall ||
1349 Node->getOpcode() != ISD::CALL ||
1350 Tmp3.getNode()->getOpcode() != ISD::CALLSEQ_END) &&
1351 "Nested CALLSEQ_START..CALLSEQ_END not supported.");
1353 // The number of incoming and outgoing values should match; unless the final
1354 // outgoing value is a flag.
1355 assert((Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() ||
1356 (Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() + 1 &&
1357 Tmp3.getNode()->getValueType(Tmp3.getNode()->getNumValues() - 1) ==
1359 "Lowering call/formal_arguments produced unexpected # results!");
1361 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1362 // remember that we legalized all of them, so it doesn't get relegalized.
1363 for (unsigned i = 0, e = Tmp3.getNode()->getNumValues(); i != e; ++i) {
1364 if (Tmp3.getNode()->getValueType(i) == MVT::Flag)
1366 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1367 if (Op.getResNo() == i)
1369 AddLegalizedOperand(SDValue(Node, i), Tmp1);
1372 case ISD::EXTRACT_SUBREG: {
1373 Tmp1 = LegalizeOp(Node->getOperand(0));
1374 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1375 assert(idx && "Operand must be a constant");
1376 Tmp2 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0));
1377 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1380 case ISD::INSERT_SUBREG: {
1381 Tmp1 = LegalizeOp(Node->getOperand(0));
1382 Tmp2 = LegalizeOp(Node->getOperand(1));
1383 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1384 assert(idx && "Operand must be a constant");
1385 Tmp3 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0));
1386 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1389 case ISD::BUILD_VECTOR:
1390 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1391 default: assert(0 && "This action is not supported yet!");
1392 case TargetLowering::Custom:
1393 Tmp3 = TLI.LowerOperation(Result, DAG);
1394 if (Tmp3.getNode()) {
1399 case TargetLowering::Expand:
1400 Result = ExpandBUILD_VECTOR(Result.getNode());
1404 case ISD::INSERT_VECTOR_ELT:
1405 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1406 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1408 // The type of the value to insert may not be legal, even though the vector
1409 // type is legal. Legalize/Promote accordingly. We do not handle Expand
1411 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1412 default: assert(0 && "Cannot expand insert element operand");
1413 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
1414 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
1416 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1418 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1419 Node->getValueType(0))) {
1420 default: assert(0 && "This action is not supported yet!");
1421 case TargetLowering::Legal:
1423 case TargetLowering::Custom:
1424 Tmp4 = TLI.LowerOperation(Result, DAG);
1425 if (Tmp4.getNode()) {
1430 case TargetLowering::Expand: {
1431 // If the insert index is a constant, codegen this as a scalar_to_vector,
1432 // then a shuffle that inserts it into the right position in the vector.
1433 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1434 // SCALAR_TO_VECTOR requires that the type of the value being inserted
1435 // match the element type of the vector being created.
1436 if (Tmp2.getValueType() ==
1437 Op.getValueType().getVectorElementType()) {
1438 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
1439 Tmp1.getValueType(), Tmp2);
1441 unsigned NumElts = Tmp1.getValueType().getVectorNumElements();
1443 MVT::getIntVectorWithNumElements(NumElts);
1444 MVT ShufMaskEltVT = ShufMaskVT.getVectorElementType();
1446 // We generate a shuffle of InVec and ScVec, so the shuffle mask
1447 // should be 0,1,2,3,4,5... with the appropriate element replaced with
1448 // elt 0 of the RHS.
1449 SmallVector<SDValue, 8> ShufOps;
1450 for (unsigned i = 0; i != NumElts; ++i) {
1451 if (i != InsertPos->getZExtValue())
1452 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1454 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1456 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1457 &ShufOps[0], ShufOps.size());
1459 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1460 Tmp1, ScVec, ShufMask);
1461 Result = LegalizeOp(Result);
1465 Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3);
1470 case ISD::SCALAR_TO_VECTOR:
1471 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1472 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1476 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1477 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1478 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1479 Node->getValueType(0))) {
1480 default: assert(0 && "This action is not supported yet!");
1481 case TargetLowering::Legal:
1483 case TargetLowering::Custom:
1484 Tmp3 = TLI.LowerOperation(Result, DAG);
1485 if (Tmp3.getNode()) {
1490 case TargetLowering::Expand:
1491 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1495 case ISD::VECTOR_SHUFFLE:
1496 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1497 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1498 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1500 // Allow targets to custom lower the SHUFFLEs they support.
1501 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1502 default: assert(0 && "Unknown operation action!");
1503 case TargetLowering::Legal:
1504 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1505 "vector shuffle should not be created if not legal!");
1507 case TargetLowering::Custom:
1508 Tmp3 = TLI.LowerOperation(Result, DAG);
1509 if (Tmp3.getNode()) {
1514 case TargetLowering::Expand: {
1515 MVT VT = Node->getValueType(0);
1516 MVT EltVT = VT.getVectorElementType();
1517 MVT PtrVT = TLI.getPointerTy();
1518 SDValue Mask = Node->getOperand(2);
1519 unsigned NumElems = Mask.getNumOperands();
1520 SmallVector<SDValue,8> Ops;
1521 for (unsigned i = 0; i != NumElems; ++i) {
1522 SDValue Arg = Mask.getOperand(i);
1523 if (Arg.getOpcode() == ISD::UNDEF) {
1524 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1526 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1527 unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
1529 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1530 DAG.getConstant(Idx, PtrVT)));
1532 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1533 DAG.getConstant(Idx - NumElems, PtrVT)));
1536 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1539 case TargetLowering::Promote: {
1540 // Change base type to a different vector type.
1541 MVT OVT = Node->getValueType(0);
1542 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1544 // Cast the two input vectors.
1545 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1546 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1548 // Convert the shuffle mask to the right # elements.
1549 Tmp3 = SDValue(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1550 assert(Tmp3.getNode() && "Shuffle not legal?");
1551 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1552 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1558 case ISD::EXTRACT_VECTOR_ELT:
1559 Tmp1 = Node->getOperand(0);
1560 Tmp2 = LegalizeOp(Node->getOperand(1));
1561 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1562 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1565 case ISD::EXTRACT_SUBVECTOR:
1566 Tmp1 = Node->getOperand(0);
1567 Tmp2 = LegalizeOp(Node->getOperand(1));
1568 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1569 Result = ExpandEXTRACT_SUBVECTOR(Result);
1572 case ISD::CALLSEQ_START: {
1573 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1575 // Recursively Legalize all of the inputs of the call end that do not lead
1576 // to this call start. This ensures that any libcalls that need be inserted
1577 // are inserted *before* the CALLSEQ_START.
1578 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1579 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1580 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
1584 // Now that we legalized all of the inputs (which may have inserted
1585 // libcalls) create the new CALLSEQ_START node.
1586 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1588 // Merge in the last call, to ensure that this call start after the last
1590 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1591 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1592 Tmp1 = LegalizeOp(Tmp1);
1595 // Do not try to legalize the target-specific arguments (#1+).
1596 if (Tmp1 != Node->getOperand(0)) {
1597 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1599 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1602 // Remember that the CALLSEQ_START is legalized.
1603 AddLegalizedOperand(Op.getValue(0), Result);
1604 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1605 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1607 // Now that the callseq_start and all of the non-call nodes above this call
1608 // sequence have been legalized, legalize the call itself. During this
1609 // process, no libcalls can/will be inserted, guaranteeing that no calls
1611 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1612 // Note that we are selecting this call!
1613 LastCALLSEQ_END = SDValue(CallEnd, 0);
1614 IsLegalizingCall = true;
1616 // Legalize the call, starting from the CALLSEQ_END.
1617 LegalizeOp(LastCALLSEQ_END);
1618 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1621 case ISD::CALLSEQ_END:
1622 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1623 // will cause this node to be legalized as well as handling libcalls right.
1624 if (LastCALLSEQ_END.getNode() != Node) {
1625 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
1626 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1627 assert(I != LegalizedNodes.end() &&
1628 "Legalizing the call start should have legalized this node!");
1632 // Otherwise, the call start has been legalized and everything is going
1633 // according to plan. Just legalize ourselves normally here.
1634 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1635 // Do not try to legalize the target-specific arguments (#1+), except for
1636 // an optional flag input.
1637 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1638 if (Tmp1 != Node->getOperand(0)) {
1639 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1641 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1644 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1645 if (Tmp1 != Node->getOperand(0) ||
1646 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1647 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1650 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1653 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1654 // This finishes up call legalization.
1655 IsLegalizingCall = false;
1657 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1658 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1659 if (Node->getNumValues() == 2)
1660 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1661 return Result.getValue(Op.getResNo());
1662 case ISD::DYNAMIC_STACKALLOC: {
1663 MVT VT = Node->getValueType(0);
1664 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1665 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1666 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1667 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1669 Tmp1 = Result.getValue(0);
1670 Tmp2 = Result.getValue(1);
1671 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1672 default: assert(0 && "This action is not supported yet!");
1673 case TargetLowering::Expand: {
1674 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1675 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1676 " not tell us which reg is the stack pointer!");
1677 SDValue Chain = Tmp1.getOperand(0);
1679 // Chain the dynamic stack allocation so that it doesn't modify the stack
1680 // pointer when other instructions are using the stack.
1681 Chain = DAG.getCALLSEQ_START(Chain,
1682 DAG.getConstant(0, TLI.getPointerTy()));
1684 SDValue Size = Tmp2.getOperand(1);
1685 SDValue SP = DAG.getCopyFromReg(Chain, SPReg, VT);
1686 Chain = SP.getValue(1);
1687 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1688 unsigned StackAlign =
1689 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1690 if (Align > StackAlign)
1691 SP = DAG.getNode(ISD::AND, VT, SP,
1692 DAG.getConstant(-(uint64_t)Align, VT));
1693 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value
1694 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
1697 DAG.getCALLSEQ_END(Chain,
1698 DAG.getConstant(0, TLI.getPointerTy()),
1699 DAG.getConstant(0, TLI.getPointerTy()),
1702 Tmp1 = LegalizeOp(Tmp1);
1703 Tmp2 = LegalizeOp(Tmp2);
1706 case TargetLowering::Custom:
1707 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1708 if (Tmp3.getNode()) {
1709 Tmp1 = LegalizeOp(Tmp3);
1710 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1713 case TargetLowering::Legal:
1716 // Since this op produce two values, make sure to remember that we
1717 // legalized both of them.
1718 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
1719 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
1720 return Op.getResNo() ? Tmp2 : Tmp1;
1722 case ISD::INLINEASM: {
1723 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1724 bool Changed = false;
1725 // Legalize all of the operands of the inline asm, in case they are nodes
1726 // that need to be expanded or something. Note we skip the asm string and
1727 // all of the TargetConstant flags.
1728 SDValue Op = LegalizeOp(Ops[0]);
1729 Changed = Op != Ops[0];
1732 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1733 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1734 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getZExtValue() >> 3;
1735 for (++i; NumVals; ++i, --NumVals) {
1736 SDValue Op = LegalizeOp(Ops[i]);
1745 Op = LegalizeOp(Ops.back());
1746 Changed |= Op != Ops.back();
1751 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1753 // INLINE asm returns a chain and flag, make sure to add both to the map.
1754 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1755 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1756 return Result.getValue(Op.getResNo());
1759 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1760 // Ensure that libcalls are emitted before a branch.
1761 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1762 Tmp1 = LegalizeOp(Tmp1);
1763 LastCALLSEQ_END = DAG.getEntryNode();
1765 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1768 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1769 // Ensure that libcalls are emitted before a branch.
1770 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1771 Tmp1 = LegalizeOp(Tmp1);
1772 LastCALLSEQ_END = DAG.getEntryNode();
1774 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1775 default: assert(0 && "Indirect target must be legal type (pointer)!");
1777 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1780 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1783 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1784 // Ensure that libcalls are emitted before a branch.
1785 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1786 Tmp1 = LegalizeOp(Tmp1);
1787 LastCALLSEQ_END = DAG.getEntryNode();
1789 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1790 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1792 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1793 default: assert(0 && "This action is not supported yet!");
1794 case TargetLowering::Legal: break;
1795 case TargetLowering::Custom:
1796 Tmp1 = TLI.LowerOperation(Result, DAG);
1797 if (Tmp1.getNode()) Result = Tmp1;
1799 case TargetLowering::Expand: {
1800 SDValue Chain = Result.getOperand(0);
1801 SDValue Table = Result.getOperand(1);
1802 SDValue Index = Result.getOperand(2);
1804 MVT PTy = TLI.getPointerTy();
1805 MachineFunction &MF = DAG.getMachineFunction();
1806 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
1807 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1808 SDValue Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1811 switch (EntrySize) {
1812 default: assert(0 && "Size of jump table not supported yet."); break;
1813 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr,
1814 PseudoSourceValue::getJumpTable(), 0); break;
1815 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr,
1816 PseudoSourceValue::getJumpTable(), 0); break;
1820 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1821 // For PIC, the sequence is:
1822 // BRIND(load(Jumptable + index) + RelocBase)
1823 // RelocBase can be JumpTable, GOT or some sort of global base.
1824 if (PTy != MVT::i32)
1825 Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr);
1826 Addr = DAG.getNode(ISD::ADD, PTy, Addr,
1827 TLI.getPICJumpTableRelocBase(Table, DAG));
1829 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1834 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1835 // Ensure that libcalls are emitted before a return.
1836 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1837 Tmp1 = LegalizeOp(Tmp1);
1838 LastCALLSEQ_END = DAG.getEntryNode();
1840 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1841 case Expand: assert(0 && "It's impossible to expand bools");
1843 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1846 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1848 // The top bits of the promoted condition are not necessarily zero, ensure
1849 // that the value is properly zero extended.
1850 unsigned BitWidth = Tmp2.getValueSizeInBits();
1851 if (!DAG.MaskedValueIsZero(Tmp2,
1852 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
1853 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1858 // Basic block destination (Op#2) is always legal.
1859 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1861 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1862 default: assert(0 && "This action is not supported yet!");
1863 case TargetLowering::Legal: break;
1864 case TargetLowering::Custom:
1865 Tmp1 = TLI.LowerOperation(Result, DAG);
1866 if (Tmp1.getNode()) Result = Tmp1;
1868 case TargetLowering::Expand:
1869 // Expand brcond's setcc into its constituent parts and create a BR_CC
1871 if (Tmp2.getOpcode() == ISD::SETCC) {
1872 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1873 Tmp2.getOperand(0), Tmp2.getOperand(1),
1874 Node->getOperand(2));
1876 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1877 DAG.getCondCode(ISD::SETNE), Tmp2,
1878 DAG.getConstant(0, Tmp2.getValueType()),
1879 Node->getOperand(2));
1885 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1886 // Ensure that libcalls are emitted before a branch.
1887 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1888 Tmp1 = LegalizeOp(Tmp1);
1889 Tmp2 = Node->getOperand(2); // LHS
1890 Tmp3 = Node->getOperand(3); // RHS
1891 Tmp4 = Node->getOperand(1); // CC
1893 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1894 LastCALLSEQ_END = DAG.getEntryNode();
1896 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1897 // the LHS is a legal SETCC itself. In this case, we need to compare
1898 // the result against zero to select between true and false values.
1899 if (Tmp3.getNode() == 0) {
1900 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1901 Tmp4 = DAG.getCondCode(ISD::SETNE);
1904 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1905 Node->getOperand(4));
1907 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1908 default: assert(0 && "Unexpected action for BR_CC!");
1909 case TargetLowering::Legal: break;
1910 case TargetLowering::Custom:
1911 Tmp4 = TLI.LowerOperation(Result, DAG);
1912 if (Tmp4.getNode()) Result = Tmp4;
1917 LoadSDNode *LD = cast<LoadSDNode>(Node);
1918 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1919 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1921 ISD::LoadExtType ExtType = LD->getExtensionType();
1922 if (ExtType == ISD::NON_EXTLOAD) {
1923 MVT VT = Node->getValueType(0);
1924 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1925 Tmp3 = Result.getValue(0);
1926 Tmp4 = Result.getValue(1);
1928 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1929 default: assert(0 && "This action is not supported yet!");
1930 case TargetLowering::Legal:
1931 // If this is an unaligned load and the target doesn't support it,
1933 if (!TLI.allowsUnalignedMemoryAccesses()) {
1934 unsigned ABIAlignment = TLI.getTargetData()->
1935 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
1936 if (LD->getAlignment() < ABIAlignment){
1937 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
1939 Tmp3 = Result.getOperand(0);
1940 Tmp4 = Result.getOperand(1);
1941 Tmp3 = LegalizeOp(Tmp3);
1942 Tmp4 = LegalizeOp(Tmp4);
1946 case TargetLowering::Custom:
1947 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1948 if (Tmp1.getNode()) {
1949 Tmp3 = LegalizeOp(Tmp1);
1950 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1953 case TargetLowering::Promote: {
1954 // Only promote a load of vector type to another.
1955 assert(VT.isVector() && "Cannot promote this load!");
1956 // Change base type to a different vector type.
1957 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1959 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1960 LD->getSrcValueOffset(),
1961 LD->isVolatile(), LD->getAlignment());
1962 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1963 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1967 // Since loads produce two values, make sure to remember that we
1968 // legalized both of them.
1969 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
1970 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
1971 return Op.getResNo() ? Tmp4 : Tmp3;
1973 MVT SrcVT = LD->getMemoryVT();
1974 unsigned SrcWidth = SrcVT.getSizeInBits();
1975 int SVOffset = LD->getSrcValueOffset();
1976 unsigned Alignment = LD->getAlignment();
1977 bool isVolatile = LD->isVolatile();
1979 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
1980 // Some targets pretend to have an i1 loading operation, and actually
1981 // load an i8. This trick is correct for ZEXTLOAD because the top 7
1982 // bits are guaranteed to be zero; it helps the optimizers understand
1983 // that these bits are zero. It is also useful for EXTLOAD, since it
1984 // tells the optimizers that those bits are undefined. It would be
1985 // nice to have an effective generic way of getting these benefits...
1986 // Until such a way is found, don't insist on promoting i1 here.
1987 (SrcVT != MVT::i1 ||
1988 TLI.getLoadXAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
1989 // Promote to a byte-sized load if not loading an integral number of
1990 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
1991 unsigned NewWidth = SrcVT.getStoreSizeInBits();
1992 MVT NVT = MVT::getIntegerVT(NewWidth);
1995 // The extra bits are guaranteed to be zero, since we stored them that
1996 // way. A zext load from NVT thus automatically gives zext from SrcVT.
1998 ISD::LoadExtType NewExtType =
1999 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
2001 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0),
2002 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
2003 NVT, isVolatile, Alignment);
2005 Ch = Result.getValue(1); // The chain.
2007 if (ExtType == ISD::SEXTLOAD)
2008 // Having the top bits zero doesn't help when sign extending.
2009 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2010 Result, DAG.getValueType(SrcVT));
2011 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
2012 // All the top bits are guaranteed to be zero - inform the optimizers.
2013 Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result,
2014 DAG.getValueType(SrcVT));
2016 Tmp1 = LegalizeOp(Result);
2017 Tmp2 = LegalizeOp(Ch);
2018 } else if (SrcWidth & (SrcWidth - 1)) {
2019 // If not loading a power-of-2 number of bits, expand as two loads.
2020 assert(SrcVT.isExtended() && !SrcVT.isVector() &&
2021 "Unsupported extload!");
2022 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
2023 assert(RoundWidth < SrcWidth);
2024 unsigned ExtraWidth = SrcWidth - RoundWidth;
2025 assert(ExtraWidth < RoundWidth);
2026 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2027 "Load size not an integral number of bytes!");
2028 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2029 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2031 unsigned IncrementSize;
2033 if (TLI.isLittleEndian()) {
2034 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
2035 // Load the bottom RoundWidth bits.
2036 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2037 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2040 // Load the remaining ExtraWidth bits.
2041 IncrementSize = RoundWidth / 8;
2042 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2043 DAG.getIntPtrConstant(IncrementSize));
2044 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2045 LD->getSrcValue(), SVOffset + IncrementSize,
2046 ExtraVT, isVolatile,
2047 MinAlign(Alignment, IncrementSize));
2049 // Build a factor node to remember that this load is independent of the
2051 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2054 // Move the top bits to the right place.
2055 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2056 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2058 // Join the hi and lo parts.
2059 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2061 // Big endian - avoid unaligned loads.
2062 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
2063 // Load the top RoundWidth bits.
2064 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2065 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2068 // Load the remaining ExtraWidth bits.
2069 IncrementSize = RoundWidth / 8;
2070 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2071 DAG.getIntPtrConstant(IncrementSize));
2072 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2073 LD->getSrcValue(), SVOffset + IncrementSize,
2074 ExtraVT, isVolatile,
2075 MinAlign(Alignment, IncrementSize));
2077 // Build a factor node to remember that this load is independent of the
2079 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2082 // Move the top bits to the right place.
2083 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2084 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2086 // Join the hi and lo parts.
2087 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2090 Tmp1 = LegalizeOp(Result);
2091 Tmp2 = LegalizeOp(Ch);
2093 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
2094 default: assert(0 && "This action is not supported yet!");
2095 case TargetLowering::Custom:
2098 case TargetLowering::Legal:
2099 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2100 Tmp1 = Result.getValue(0);
2101 Tmp2 = Result.getValue(1);
2104 Tmp3 = TLI.LowerOperation(Result, DAG);
2105 if (Tmp3.getNode()) {
2106 Tmp1 = LegalizeOp(Tmp3);
2107 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2110 // If this is an unaligned load and the target doesn't support it,
2112 if (!TLI.allowsUnalignedMemoryAccesses()) {
2113 unsigned ABIAlignment = TLI.getTargetData()->
2114 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
2115 if (LD->getAlignment() < ABIAlignment){
2116 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
2118 Tmp1 = Result.getOperand(0);
2119 Tmp2 = Result.getOperand(1);
2120 Tmp1 = LegalizeOp(Tmp1);
2121 Tmp2 = LegalizeOp(Tmp2);
2126 case TargetLowering::Expand:
2127 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
2128 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
2129 SDValue Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
2130 LD->getSrcValueOffset(),
2131 LD->isVolatile(), LD->getAlignment());
2132 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
2133 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
2134 Tmp2 = LegalizeOp(Load.getValue(1));
2137 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
2138 // Turn the unsupported load into an EXTLOAD followed by an explicit
2139 // zero/sign extend inreg.
2140 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2141 Tmp1, Tmp2, LD->getSrcValue(),
2142 LD->getSrcValueOffset(), SrcVT,
2143 LD->isVolatile(), LD->getAlignment());
2145 if (ExtType == ISD::SEXTLOAD)
2146 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2147 Result, DAG.getValueType(SrcVT));
2149 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
2150 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
2151 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
2156 // Since loads produce two values, make sure to remember that we legalized
2158 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2159 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2160 return Op.getResNo() ? Tmp2 : Tmp1;
2163 case ISD::EXTRACT_ELEMENT: {
2164 MVT OpTy = Node->getOperand(0).getValueType();
2165 switch (getTypeAction(OpTy)) {
2166 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
2168 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
2170 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
2171 DAG.getConstant(OpTy.getSizeInBits()/2,
2172 TLI.getShiftAmountTy()));
2173 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
2176 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
2177 Node->getOperand(0));
2181 // Get both the low and high parts.
2182 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2183 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
2184 Result = Tmp2; // 1 -> Hi
2186 Result = Tmp1; // 0 -> Lo
2192 case ISD::CopyToReg:
2193 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2195 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
2196 "Register type must be legal!");
2197 // Legalize the incoming value (must be a legal type).
2198 Tmp2 = LegalizeOp(Node->getOperand(2));
2199 if (Node->getNumValues() == 1) {
2200 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
2202 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
2203 if (Node->getNumOperands() == 4) {
2204 Tmp3 = LegalizeOp(Node->getOperand(3));
2205 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
2208 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
2211 // Since this produces two values, make sure to remember that we legalized
2213 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
2214 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
2220 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2222 // Ensure that libcalls are emitted before a return.
2223 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2224 Tmp1 = LegalizeOp(Tmp1);
2225 LastCALLSEQ_END = DAG.getEntryNode();
2227 switch (Node->getNumOperands()) {
2229 Tmp2 = Node->getOperand(1);
2230 Tmp3 = Node->getOperand(2); // Signness
2231 switch (getTypeAction(Tmp2.getValueType())) {
2233 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
2236 if (!Tmp2.getValueType().isVector()) {
2238 ExpandOp(Tmp2, Lo, Hi);
2240 // Big endian systems want the hi reg first.
2241 if (TLI.isBigEndian())
2245 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2247 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
2248 Result = LegalizeOp(Result);
2250 SDNode *InVal = Tmp2.getNode();
2251 int InIx = Tmp2.getResNo();
2252 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
2253 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
2255 // Figure out if there is a simple type corresponding to this Vector
2256 // type. If so, convert to the vector type.
2257 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2258 if (TLI.isTypeLegal(TVT)) {
2259 // Turn this into a return of the vector type.
2260 Tmp2 = LegalizeOp(Tmp2);
2261 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2262 } else if (NumElems == 1) {
2263 // Turn this into a return of the scalar type.
2264 Tmp2 = ScalarizeVectorOp(Tmp2);
2265 Tmp2 = LegalizeOp(Tmp2);
2266 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2268 // FIXME: Returns of gcc generic vectors smaller than a legal type
2269 // should be returned in integer registers!
2271 // The scalarized value type may not be legal, e.g. it might require
2272 // promotion or expansion. Relegalize the return.
2273 Result = LegalizeOp(Result);
2275 // FIXME: Returns of gcc generic vectors larger than a legal vector
2276 // type should be returned by reference!
2278 SplitVectorOp(Tmp2, Lo, Hi);
2279 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2280 Result = LegalizeOp(Result);
2285 Tmp2 = PromoteOp(Node->getOperand(1));
2286 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2287 Result = LegalizeOp(Result);
2292 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2294 default: { // ret <values>
2295 SmallVector<SDValue, 8> NewValues;
2296 NewValues.push_back(Tmp1);
2297 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
2298 switch (getTypeAction(Node->getOperand(i).getValueType())) {
2300 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
2301 NewValues.push_back(Node->getOperand(i+1));
2305 assert(!Node->getOperand(i).getValueType().isExtended() &&
2306 "FIXME: TODO: implement returning non-legal vector types!");
2307 ExpandOp(Node->getOperand(i), Lo, Hi);
2308 NewValues.push_back(Lo);
2309 NewValues.push_back(Node->getOperand(i+1));
2311 NewValues.push_back(Hi);
2312 NewValues.push_back(Node->getOperand(i+1));
2317 assert(0 && "Can't promote multiple return value yet!");
2320 if (NewValues.size() == Node->getNumOperands())
2321 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
2323 Result = DAG.getNode(ISD::RET, MVT::Other,
2324 &NewValues[0], NewValues.size());
2329 if (Result.getOpcode() == ISD::RET) {
2330 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
2331 default: assert(0 && "This action is not supported yet!");
2332 case TargetLowering::Legal: break;
2333 case TargetLowering::Custom:
2334 Tmp1 = TLI.LowerOperation(Result, DAG);
2335 if (Tmp1.getNode()) Result = Tmp1;
2341 StoreSDNode *ST = cast<StoreSDNode>(Node);
2342 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
2343 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
2344 int SVOffset = ST->getSrcValueOffset();
2345 unsigned Alignment = ST->getAlignment();
2346 bool isVolatile = ST->isVolatile();
2348 if (!ST->isTruncatingStore()) {
2349 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
2350 // FIXME: We shouldn't do this for TargetConstantFP's.
2351 // FIXME: move this to the DAG Combiner! Note that we can't regress due
2352 // to phase ordering between legalized code and the dag combiner. This
2353 // probably means that we need to integrate dag combiner and legalizer
2355 // We generally can't do this one for long doubles.
2356 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
2357 if (CFP->getValueType(0) == MVT::f32 &&
2358 getTypeAction(MVT::i32) == Legal) {
2359 Tmp3 = DAG.getConstant(CFP->getValueAPF().
2360 convertToAPInt().zextOrTrunc(32),
2362 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2363 SVOffset, isVolatile, Alignment);
2365 } else if (CFP->getValueType(0) == MVT::f64) {
2366 // If this target supports 64-bit registers, do a single 64-bit store.
2367 if (getTypeAction(MVT::i64) == Legal) {
2368 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt().
2369 zextOrTrunc(64), MVT::i64);
2370 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2371 SVOffset, isVolatile, Alignment);
2373 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
2374 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
2375 // stores. If the target supports neither 32- nor 64-bits, this
2376 // xform is certainly not worth it.
2377 const APInt &IntVal =CFP->getValueAPF().convertToAPInt();
2378 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
2379 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
2380 if (TLI.isBigEndian()) std::swap(Lo, Hi);
2382 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2383 SVOffset, isVolatile, Alignment);
2384 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2385 DAG.getIntPtrConstant(4));
2386 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
2387 isVolatile, MinAlign(Alignment, 4U));
2389 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2395 switch (getTypeAction(ST->getMemoryVT())) {
2397 Tmp3 = LegalizeOp(ST->getValue());
2398 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2401 MVT VT = Tmp3.getValueType();
2402 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2403 default: assert(0 && "This action is not supported yet!");
2404 case TargetLowering::Legal:
2405 // If this is an unaligned store and the target doesn't support it,
2407 if (!TLI.allowsUnalignedMemoryAccesses()) {
2408 unsigned ABIAlignment = TLI.getTargetData()->
2409 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2410 if (ST->getAlignment() < ABIAlignment)
2411 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
2415 case TargetLowering::Custom:
2416 Tmp1 = TLI.LowerOperation(Result, DAG);
2417 if (Tmp1.getNode()) Result = Tmp1;
2419 case TargetLowering::Promote:
2420 assert(VT.isVector() && "Unknown legal promote case!");
2421 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
2422 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2423 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
2424 ST->getSrcValue(), SVOffset, isVolatile,
2431 // Truncate the value and store the result.
2432 Tmp3 = PromoteOp(ST->getValue());
2433 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2434 SVOffset, ST->getMemoryVT(),
2435 isVolatile, Alignment);
2439 unsigned IncrementSize = 0;
2442 // If this is a vector type, then we have to calculate the increment as
2443 // the product of the element size in bytes, and the number of elements
2444 // in the high half of the vector.
2445 if (ST->getValue().getValueType().isVector()) {
2446 SDNode *InVal = ST->getValue().getNode();
2447 int InIx = ST->getValue().getResNo();
2448 MVT InVT = InVal->getValueType(InIx);
2449 unsigned NumElems = InVT.getVectorNumElements();
2450 MVT EVT = InVT.getVectorElementType();
2452 // Figure out if there is a simple type corresponding to this Vector
2453 // type. If so, convert to the vector type.
2454 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2455 if (TLI.isTypeLegal(TVT)) {
2456 // Turn this into a normal store of the vector type.
2457 Tmp3 = LegalizeOp(ST->getValue());
2458 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2459 SVOffset, isVolatile, Alignment);
2460 Result = LegalizeOp(Result);
2462 } else if (NumElems == 1) {
2463 // Turn this into a normal store of the scalar type.
2464 Tmp3 = ScalarizeVectorOp(ST->getValue());
2465 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2466 SVOffset, isVolatile, Alignment);
2467 // The scalarized value type may not be legal, e.g. it might require
2468 // promotion or expansion. Relegalize the scalar store.
2469 Result = LegalizeOp(Result);
2472 SplitVectorOp(ST->getValue(), Lo, Hi);
2473 IncrementSize = Lo.getNode()->getValueType(0).getVectorNumElements() *
2474 EVT.getSizeInBits()/8;
2477 ExpandOp(ST->getValue(), Lo, Hi);
2478 IncrementSize = Hi.getNode() ? Hi.getValueType().getSizeInBits()/8 : 0;
2480 if (Hi.getNode() && TLI.isBigEndian())
2484 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2485 SVOffset, isVolatile, Alignment);
2487 if (Hi.getNode() == NULL) {
2488 // Must be int <-> float one-to-one expansion.
2493 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2494 DAG.getIntPtrConstant(IncrementSize));
2495 assert(isTypeLegal(Tmp2.getValueType()) &&
2496 "Pointers must be legal!");
2497 SVOffset += IncrementSize;
2498 Alignment = MinAlign(Alignment, IncrementSize);
2499 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2500 SVOffset, isVolatile, Alignment);
2501 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2505 switch (getTypeAction(ST->getValue().getValueType())) {
2507 Tmp3 = LegalizeOp(ST->getValue());
2510 // We can promote the value, the truncstore will still take care of it.
2511 Tmp3 = PromoteOp(ST->getValue());
2514 // Just store the low part. This may become a non-trunc store, so make
2515 // sure to use getTruncStore, not UpdateNodeOperands below.
2516 ExpandOp(ST->getValue(), Tmp3, Tmp4);
2517 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2518 SVOffset, MVT::i8, isVolatile, Alignment);
2521 MVT StVT = ST->getMemoryVT();
2522 unsigned StWidth = StVT.getSizeInBits();
2524 if (StWidth != StVT.getStoreSizeInBits()) {
2525 // Promote to a byte-sized store with upper bits zero if not
2526 // storing an integral number of bytes. For example, promote
2527 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
2528 MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits());
2529 Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT);
2530 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2531 SVOffset, NVT, isVolatile, Alignment);
2532 } else if (StWidth & (StWidth - 1)) {
2533 // If not storing a power-of-2 number of bits, expand as two stores.
2534 assert(StVT.isExtended() && !StVT.isVector() &&
2535 "Unsupported truncstore!");
2536 unsigned RoundWidth = 1 << Log2_32(StWidth);
2537 assert(RoundWidth < StWidth);
2538 unsigned ExtraWidth = StWidth - RoundWidth;
2539 assert(ExtraWidth < RoundWidth);
2540 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2541 "Store size not an integral number of bytes!");
2542 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2543 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2545 unsigned IncrementSize;
2547 if (TLI.isLittleEndian()) {
2548 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
2549 // Store the bottom RoundWidth bits.
2550 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2552 isVolatile, Alignment);
2554 // Store the remaining ExtraWidth bits.
2555 IncrementSize = RoundWidth / 8;
2556 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2557 DAG.getIntPtrConstant(IncrementSize));
2558 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2559 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2560 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2561 SVOffset + IncrementSize, ExtraVT, isVolatile,
2562 MinAlign(Alignment, IncrementSize));
2564 // Big endian - avoid unaligned stores.
2565 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
2566 // Store the top RoundWidth bits.
2567 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2568 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2569 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset,
2570 RoundVT, isVolatile, Alignment);
2572 // Store the remaining ExtraWidth bits.
2573 IncrementSize = RoundWidth / 8;
2574 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2575 DAG.getIntPtrConstant(IncrementSize));
2576 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2577 SVOffset + IncrementSize, ExtraVT, isVolatile,
2578 MinAlign(Alignment, IncrementSize));
2581 // The order of the stores doesn't matter.
2582 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2584 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2585 Tmp2 != ST->getBasePtr())
2586 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2589 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
2590 default: assert(0 && "This action is not supported yet!");
2591 case TargetLowering::Legal:
2592 // If this is an unaligned store and the target doesn't support it,
2594 if (!TLI.allowsUnalignedMemoryAccesses()) {
2595 unsigned ABIAlignment = TLI.getTargetData()->
2596 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2597 if (ST->getAlignment() < ABIAlignment)
2598 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
2602 case TargetLowering::Custom:
2603 Result = TLI.LowerOperation(Result, DAG);
2606 // TRUNCSTORE:i16 i32 -> STORE i16
2607 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
2608 Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3);
2609 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset,
2610 isVolatile, Alignment);
2618 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2619 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2621 case ISD::STACKSAVE:
2622 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2623 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2624 Tmp1 = Result.getValue(0);
2625 Tmp2 = Result.getValue(1);
2627 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2628 default: assert(0 && "This action is not supported yet!");
2629 case TargetLowering::Legal: break;
2630 case TargetLowering::Custom:
2631 Tmp3 = TLI.LowerOperation(Result, DAG);
2632 if (Tmp3.getNode()) {
2633 Tmp1 = LegalizeOp(Tmp3);
2634 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2637 case TargetLowering::Expand:
2638 // Expand to CopyFromReg if the target set
2639 // StackPointerRegisterToSaveRestore.
2640 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2641 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
2642 Node->getValueType(0));
2643 Tmp2 = Tmp1.getValue(1);
2645 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
2646 Tmp2 = Node->getOperand(0);
2651 // Since stacksave produce two values, make sure to remember that we
2652 // legalized both of them.
2653 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2654 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2655 return Op.getResNo() ? Tmp2 : Tmp1;
2657 case ISD::STACKRESTORE:
2658 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2659 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2660 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2662 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2663 default: assert(0 && "This action is not supported yet!");
2664 case TargetLowering::Legal: break;
2665 case TargetLowering::Custom:
2666 Tmp1 = TLI.LowerOperation(Result, DAG);
2667 if (Tmp1.getNode()) Result = Tmp1;
2669 case TargetLowering::Expand:
2670 // Expand to CopyToReg if the target set
2671 // StackPointerRegisterToSaveRestore.
2672 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2673 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
2681 case ISD::READCYCLECOUNTER:
2682 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2683 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2684 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2685 Node->getValueType(0))) {
2686 default: assert(0 && "This action is not supported yet!");
2687 case TargetLowering::Legal:
2688 Tmp1 = Result.getValue(0);
2689 Tmp2 = Result.getValue(1);
2691 case TargetLowering::Custom:
2692 Result = TLI.LowerOperation(Result, DAG);
2693 Tmp1 = LegalizeOp(Result.getValue(0));
2694 Tmp2 = LegalizeOp(Result.getValue(1));
2698 // Since rdcc produce two values, make sure to remember that we legalized
2700 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2701 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2705 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2706 case Expand: assert(0 && "It's impossible to expand bools");
2708 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2711 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2712 // Make sure the condition is either zero or one.
2713 unsigned BitWidth = Tmp1.getValueSizeInBits();
2714 if (!DAG.MaskedValueIsZero(Tmp1,
2715 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2716 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2720 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2721 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2723 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2725 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2726 default: assert(0 && "This action is not supported yet!");
2727 case TargetLowering::Legal: break;
2728 case TargetLowering::Custom: {
2729 Tmp1 = TLI.LowerOperation(Result, DAG);
2730 if (Tmp1.getNode()) Result = Tmp1;
2733 case TargetLowering::Expand:
2734 if (Tmp1.getOpcode() == ISD::SETCC) {
2735 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2737 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2739 Result = DAG.getSelectCC(Tmp1,
2740 DAG.getConstant(0, Tmp1.getValueType()),
2741 Tmp2, Tmp3, ISD::SETNE);
2744 case TargetLowering::Promote: {
2746 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2747 unsigned ExtOp, TruncOp;
2748 if (Tmp2.getValueType().isVector()) {
2749 ExtOp = ISD::BIT_CONVERT;
2750 TruncOp = ISD::BIT_CONVERT;
2751 } else if (Tmp2.getValueType().isInteger()) {
2752 ExtOp = ISD::ANY_EXTEND;
2753 TruncOp = ISD::TRUNCATE;
2755 ExtOp = ISD::FP_EXTEND;
2756 TruncOp = ISD::FP_ROUND;
2758 // Promote each of the values to the new type.
2759 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2760 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2761 // Perform the larger operation, then round down.
2762 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2763 if (TruncOp != ISD::FP_ROUND)
2764 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2766 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result,
2767 DAG.getIntPtrConstant(0));
2772 case ISD::SELECT_CC: {
2773 Tmp1 = Node->getOperand(0); // LHS
2774 Tmp2 = Node->getOperand(1); // RHS
2775 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2776 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2777 SDValue CC = Node->getOperand(4);
2779 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
2781 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
2782 // the LHS is a legal SETCC itself. In this case, we need to compare
2783 // the result against zero to select between true and false values.
2784 if (Tmp2.getNode() == 0) {
2785 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2786 CC = DAG.getCondCode(ISD::SETNE);
2788 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
2790 // Everything is legal, see if we should expand this op or something.
2791 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
2792 default: assert(0 && "This action is not supported yet!");
2793 case TargetLowering::Legal: break;
2794 case TargetLowering::Custom:
2795 Tmp1 = TLI.LowerOperation(Result, DAG);
2796 if (Tmp1.getNode()) Result = Tmp1;
2802 Tmp1 = Node->getOperand(0);
2803 Tmp2 = Node->getOperand(1);
2804 Tmp3 = Node->getOperand(2);
2805 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
2807 // If we had to Expand the SetCC operands into a SELECT node, then it may
2808 // not always be possible to return a true LHS & RHS. In this case, just
2809 // return the value we legalized, returned in the LHS
2810 if (Tmp2.getNode() == 0) {
2815 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
2816 default: assert(0 && "Cannot handle this action for SETCC yet!");
2817 case TargetLowering::Custom:
2820 case TargetLowering::Legal:
2821 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2823 Tmp4 = TLI.LowerOperation(Result, DAG);
2824 if (Tmp4.getNode()) Result = Tmp4;
2827 case TargetLowering::Promote: {
2828 // First step, figure out the appropriate operation to use.
2829 // Allow SETCC to not be supported for all legal data types
2830 // Mostly this targets FP
2831 MVT NewInTy = Node->getOperand(0).getValueType();
2832 MVT OldVT = NewInTy; OldVT = OldVT;
2834 // Scan for the appropriate larger type to use.
2836 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
2838 assert(NewInTy.isInteger() == OldVT.isInteger() &&
2839 "Fell off of the edge of the integer world");
2840 assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() &&
2841 "Fell off of the edge of the floating point world");
2843 // If the target supports SETCC of this type, use it.
2844 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2847 if (NewInTy.isInteger())
2848 assert(0 && "Cannot promote Legal Integer SETCC yet");
2850 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2851 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2853 Tmp1 = LegalizeOp(Tmp1);
2854 Tmp2 = LegalizeOp(Tmp2);
2855 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2856 Result = LegalizeOp(Result);
2859 case TargetLowering::Expand:
2860 // Expand a setcc node into a select_cc of the same condition, lhs, and
2861 // rhs that selects between const 1 (true) and const 0 (false).
2862 MVT VT = Node->getValueType(0);
2863 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2864 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2870 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2871 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2872 SDValue CC = Node->getOperand(2);
2874 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, CC);
2876 // Everything is legal, see if we should expand this op or something.
2877 switch (TLI.getOperationAction(ISD::VSETCC, Tmp1.getValueType())) {
2878 default: assert(0 && "This action is not supported yet!");
2879 case TargetLowering::Legal: break;
2880 case TargetLowering::Custom:
2881 Tmp1 = TLI.LowerOperation(Result, DAG);
2882 if (Tmp1.getNode()) Result = Tmp1;
2888 case ISD::SHL_PARTS:
2889 case ISD::SRA_PARTS:
2890 case ISD::SRL_PARTS: {
2891 SmallVector<SDValue, 8> Ops;
2892 bool Changed = false;
2893 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2894 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2895 Changed |= Ops.back() != Node->getOperand(i);
2898 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2900 switch (TLI.getOperationAction(Node->getOpcode(),
2901 Node->getValueType(0))) {
2902 default: assert(0 && "This action is not supported yet!");
2903 case TargetLowering::Legal: break;
2904 case TargetLowering::Custom:
2905 Tmp1 = TLI.LowerOperation(Result, DAG);
2906 if (Tmp1.getNode()) {
2907 SDValue Tmp2, RetVal(0, 0);
2908 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2909 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2910 AddLegalizedOperand(SDValue(Node, i), Tmp2);
2911 if (i == Op.getResNo())
2914 assert(RetVal.getNode() && "Illegal result number");
2920 // Since these produce multiple values, make sure to remember that we
2921 // legalized all of them.
2922 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2923 AddLegalizedOperand(SDValue(Node, i), Result.getValue(i));
2924 return Result.getValue(Op.getResNo());
2946 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2947 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2948 case Expand: assert(0 && "Not possible");
2950 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2953 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2957 if ((Node->getOpcode() == ISD::SHL ||
2958 Node->getOpcode() == ISD::SRL ||
2959 Node->getOpcode() == ISD::SRA) &&
2960 !Node->getValueType(0).isVector()) {
2961 if (TLI.getShiftAmountTy().bitsLT(Tmp2.getValueType()))
2962 Tmp2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Tmp2);
2963 else if (TLI.getShiftAmountTy().bitsGT(Tmp2.getValueType()))
2964 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Tmp2);
2967 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2969 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2970 default: assert(0 && "BinOp legalize operation not supported");
2971 case TargetLowering::Legal: break;
2972 case TargetLowering::Custom:
2973 Tmp1 = TLI.LowerOperation(Result, DAG);
2974 if (Tmp1.getNode()) {
2978 // Fall through if the custom lower can't deal with the operation
2979 case TargetLowering::Expand: {
2980 MVT VT = Op.getValueType();
2982 // See if multiply or divide can be lowered using two-result operations.
2983 SDVTList VTs = DAG.getVTList(VT, VT);
2984 if (Node->getOpcode() == ISD::MUL) {
2985 // We just need the low half of the multiply; try both the signed
2986 // and unsigned forms. If the target supports both SMUL_LOHI and
2987 // UMUL_LOHI, form a preference by checking which forms of plain
2988 // MULH it supports.
2989 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT);
2990 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT);
2991 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT);
2992 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT);
2993 unsigned OpToUse = 0;
2994 if (HasSMUL_LOHI && !HasMULHS) {
2995 OpToUse = ISD::SMUL_LOHI;
2996 } else if (HasUMUL_LOHI && !HasMULHU) {
2997 OpToUse = ISD::UMUL_LOHI;
2998 } else if (HasSMUL_LOHI) {
2999 OpToUse = ISD::SMUL_LOHI;
3000 } else if (HasUMUL_LOHI) {
3001 OpToUse = ISD::UMUL_LOHI;
3004 Result = SDValue(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).getNode(), 0);
3008 if (Node->getOpcode() == ISD::MULHS &&
3009 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) {
3010 Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).getNode(), 1);
3013 if (Node->getOpcode() == ISD::MULHU &&
3014 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) {
3015 Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).getNode(), 1);
3018 if (Node->getOpcode() == ISD::SDIV &&
3019 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3020 Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(), 0);
3023 if (Node->getOpcode() == ISD::UDIV &&
3024 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3025 Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(), 0);
3029 // Check to see if we have a libcall for this operator.
3030 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3031 bool isSigned = false;
3032 switch (Node->getOpcode()) {
3035 if (VT == MVT::i32) {
3036 LC = Node->getOpcode() == ISD::UDIV
3037 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
3038 isSigned = Node->getOpcode() == ISD::SDIV;
3042 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
3043 RTLIB::POW_PPCF128);
3047 if (LC != RTLIB::UNKNOWN_LIBCALL) {
3049 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3053 assert(Node->getValueType(0).isVector() &&
3054 "Cannot expand this binary operator!");
3055 // Expand the operation into a bunch of nasty scalar code.
3056 Result = LegalizeOp(UnrollVectorOp(Op));
3059 case TargetLowering::Promote: {
3060 switch (Node->getOpcode()) {
3061 default: assert(0 && "Do not know how to promote this BinOp!");
3065 MVT OVT = Node->getValueType(0);
3066 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3067 assert(OVT.isVector() && "Cannot promote this BinOp!");
3068 // Bit convert each of the values to the new type.
3069 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
3070 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
3071 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3072 // Bit convert the result back the original type.
3073 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
3081 case ISD::SMUL_LOHI:
3082 case ISD::UMUL_LOHI:
3085 // These nodes will only be produced by target-specific lowering, so
3086 // they shouldn't be here if they aren't legal.
3087 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
3088 "This must be legal!");
3090 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3091 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3092 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3095 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
3096 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3097 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3098 case Expand: assert(0 && "Not possible");
3100 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3103 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3107 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3109 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3110 default: assert(0 && "Operation not supported");
3111 case TargetLowering::Custom:
3112 Tmp1 = TLI.LowerOperation(Result, DAG);
3113 if (Tmp1.getNode()) Result = Tmp1;
3115 case TargetLowering::Legal: break;
3116 case TargetLowering::Expand: {
3117 // If this target supports fabs/fneg natively and select is cheap,
3118 // do this efficiently.
3119 if (!TLI.isSelectExpensive() &&
3120 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
3121 TargetLowering::Legal &&
3122 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
3123 TargetLowering::Legal) {
3124 // Get the sign bit of the RHS.
3126 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
3127 SDValue SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
3128 SignBit = DAG.getSetCC(TLI.getSetCCResultType(SignBit),
3129 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
3130 // Get the absolute value of the result.
3131 SDValue AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
3132 // Select between the nabs and abs value based on the sign bit of
3134 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
3135 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
3138 Result = LegalizeOp(Result);
3142 // Otherwise, do bitwise ops!
3144 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
3145 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
3146 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
3147 Result = LegalizeOp(Result);
3155 Tmp1 = LegalizeOp(Node->getOperand(0));
3156 Tmp2 = LegalizeOp(Node->getOperand(1));
3157 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3158 // Since this produces two values, make sure to remember that we legalized
3160 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
3161 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
3166 Tmp1 = LegalizeOp(Node->getOperand(0));
3167 Tmp2 = LegalizeOp(Node->getOperand(1));
3168 Tmp3 = LegalizeOp(Node->getOperand(2));
3169 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3170 // Since this produces two values, make sure to remember that we legalized
3172 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
3173 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
3176 case ISD::BUILD_PAIR: {
3177 MVT PairTy = Node->getValueType(0);
3178 // TODO: handle the case where the Lo and Hi operands are not of legal type
3179 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
3180 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
3181 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
3182 case TargetLowering::Promote:
3183 case TargetLowering::Custom:
3184 assert(0 && "Cannot promote/custom this yet!");
3185 case TargetLowering::Legal:
3186 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
3187 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
3189 case TargetLowering::Expand:
3190 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
3191 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
3192 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
3193 DAG.getConstant(PairTy.getSizeInBits()/2,
3194 TLI.getShiftAmountTy()));
3195 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
3204 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3205 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3207 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3208 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
3209 case TargetLowering::Custom:
3212 case TargetLowering::Legal:
3213 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3215 Tmp1 = TLI.LowerOperation(Result, DAG);
3216 if (Tmp1.getNode()) Result = Tmp1;
3219 case TargetLowering::Expand: {
3220 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
3221 bool isSigned = DivOpc == ISD::SDIV;
3222 MVT VT = Node->getValueType(0);
3224 // See if remainder can be lowered using two-result operations.
3225 SDVTList VTs = DAG.getVTList(VT, VT);
3226 if (Node->getOpcode() == ISD::SREM &&
3227 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3228 Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(), 1);
3231 if (Node->getOpcode() == ISD::UREM &&
3232 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3233 Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(), 1);
3237 if (VT.isInteger()) {
3238 if (TLI.getOperationAction(DivOpc, VT) ==
3239 TargetLowering::Legal) {
3241 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
3242 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
3243 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
3244 } else if (VT.isVector()) {
3245 Result = LegalizeOp(UnrollVectorOp(Op));
3247 assert(VT == MVT::i32 &&
3248 "Cannot expand this binary operator!");
3249 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
3250 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
3252 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3255 assert(VT.isFloatingPoint() &&
3256 "remainder op must have integer or floating-point type");
3257 if (VT.isVector()) {
3258 Result = LegalizeOp(UnrollVectorOp(Op));
3260 // Floating point mod -> fmod libcall.
3261 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
3262 RTLIB::REM_F80, RTLIB::REM_PPCF128);
3264 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3272 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3273 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3275 MVT VT = Node->getValueType(0);
3276 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
3277 default: assert(0 && "This action is not supported yet!");
3278 case TargetLowering::Custom:
3281 case TargetLowering::Legal:
3282 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3283 Result = Result.getValue(0);
3284 Tmp1 = Result.getValue(1);
3287 Tmp2 = TLI.LowerOperation(Result, DAG);
3288 if (Tmp2.getNode()) {
3289 Result = LegalizeOp(Tmp2);
3290 Tmp1 = LegalizeOp(Tmp2.getValue(1));
3294 case TargetLowering::Expand: {
3295 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3296 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
3297 // Increment the pointer, VAList, to the next vaarg
3298 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3299 DAG.getConstant(VT.getSizeInBits()/8,
3300 TLI.getPointerTy()));
3301 // Store the incremented VAList to the legalized pointer
3302 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
3303 // Load the actual argument out of the pointer VAList
3304 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
3305 Tmp1 = LegalizeOp(Result.getValue(1));
3306 Result = LegalizeOp(Result);
3310 // Since VAARG produces two values, make sure to remember that we
3311 // legalized both of them.
3312 AddLegalizedOperand(SDValue(Node, 0), Result);
3313 AddLegalizedOperand(SDValue(Node, 1), Tmp1);
3314 return Op.getResNo() ? Tmp1 : Result;
3318 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3319 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
3320 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
3322 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
3323 default: assert(0 && "This action is not supported yet!");
3324 case TargetLowering::Custom:
3327 case TargetLowering::Legal:
3328 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
3329 Node->getOperand(3), Node->getOperand(4));
3331 Tmp1 = TLI.LowerOperation(Result, DAG);
3332 if (Tmp1.getNode()) Result = Tmp1;
3335 case TargetLowering::Expand:
3336 // This defaults to loading a pointer from the input and storing it to the
3337 // output, returning the chain.
3338 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3339 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3340 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VS, 0);
3341 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VD, 0);
3347 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3348 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3350 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
3351 default: assert(0 && "This action is not supported yet!");
3352 case TargetLowering::Custom:
3355 case TargetLowering::Legal:
3356 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3358 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
3359 if (Tmp1.getNode()) Result = Tmp1;
3362 case TargetLowering::Expand:
3363 Result = Tmp1; // Default to a no-op, return the chain
3369 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3370 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3372 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3374 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
3375 default: assert(0 && "This action is not supported yet!");
3376 case TargetLowering::Legal: break;
3377 case TargetLowering::Custom:
3378 Tmp1 = TLI.LowerOperation(Result, DAG);
3379 if (Tmp1.getNode()) Result = Tmp1;
3386 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3387 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3388 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3389 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3391 assert(0 && "ROTL/ROTR legalize operation not supported");
3393 case TargetLowering::Legal:
3395 case TargetLowering::Custom:
3396 Tmp1 = TLI.LowerOperation(Result, DAG);
3397 if (Tmp1.getNode()) Result = Tmp1;
3399 case TargetLowering::Promote:
3400 assert(0 && "Do not know how to promote ROTL/ROTR");
3402 case TargetLowering::Expand:
3403 assert(0 && "Do not know how to expand ROTL/ROTR");
3409 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3410 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3411 case TargetLowering::Custom:
3412 assert(0 && "Cannot custom legalize this yet!");
3413 case TargetLowering::Legal:
3414 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3416 case TargetLowering::Promote: {
3417 MVT OVT = Tmp1.getValueType();
3418 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3419 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3421 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3422 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3423 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3424 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3427 case TargetLowering::Expand:
3428 Result = ExpandBSWAP(Tmp1);
3436 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3437 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3438 case TargetLowering::Custom:
3439 case TargetLowering::Legal:
3440 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3441 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3442 TargetLowering::Custom) {
3443 Tmp1 = TLI.LowerOperation(Result, DAG);
3444 if (Tmp1.getNode()) {
3449 case TargetLowering::Promote: {
3450 MVT OVT = Tmp1.getValueType();
3451 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3453 // Zero extend the argument.
3454 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3455 // Perform the larger operation, then subtract if needed.
3456 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
3457 switch (Node->getOpcode()) {
3462 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3463 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
3464 DAG.getConstant(NVT.getSizeInBits(), NVT),
3466 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3467 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3470 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3471 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3472 DAG.getConstant(NVT.getSizeInBits() -
3473 OVT.getSizeInBits(), NVT));
3478 case TargetLowering::Expand:
3479 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
3499 case ISD::FNEARBYINT:
3500 Tmp1 = LegalizeOp(Node->getOperand(0));
3501 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3502 case TargetLowering::Promote:
3503 case TargetLowering::Custom:
3506 case TargetLowering::Legal:
3507 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3509 Tmp1 = TLI.LowerOperation(Result, DAG);
3510 if (Tmp1.getNode()) Result = Tmp1;
3513 case TargetLowering::Expand:
3514 switch (Node->getOpcode()) {
3515 default: assert(0 && "Unreachable!");
3517 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3518 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3519 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
3522 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3523 MVT VT = Node->getValueType(0);
3524 Tmp2 = DAG.getConstantFP(0.0, VT);
3525 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
3527 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
3528 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
3543 case ISD::FNEARBYINT: {
3544 MVT VT = Node->getValueType(0);
3546 // Expand unsupported unary vector operators by unrolling them.
3547 if (VT.isVector()) {
3548 Result = LegalizeOp(UnrollVectorOp(Op));
3552 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3553 switch(Node->getOpcode()) {
3555 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3556 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
3559 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
3560 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
3563 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
3564 RTLIB::COS_F80, RTLIB::COS_PPCF128);
3567 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
3568 RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
3571 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3572 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
3575 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3576 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
3579 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
3580 RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
3583 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3584 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
3587 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3588 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
3591 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3592 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128);
3595 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3596 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128);
3599 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64,
3600 RTLIB::RINT_F80, RTLIB::RINT_PPCF128);
3602 case ISD::FNEARBYINT:
3603 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
3604 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
3607 default: assert(0 && "Unreachable!");
3610 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3618 MVT VT = Node->getValueType(0);
3620 // Expand unsupported unary vector operators by unrolling them.
3621 if (VT.isVector()) {
3622 Result = LegalizeOp(UnrollVectorOp(Op));
3626 // We always lower FPOWI into a libcall. No target support for it yet.
3627 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
3628 RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
3630 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3633 case ISD::BIT_CONVERT:
3634 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3635 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3636 Node->getValueType(0));
3637 } else if (Op.getOperand(0).getValueType().isVector()) {
3638 // The input has to be a vector type, we have to either scalarize it, pack
3639 // it, or convert it based on whether the input vector type is legal.
3640 SDNode *InVal = Node->getOperand(0).getNode();
3641 int InIx = Node->getOperand(0).getResNo();
3642 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
3643 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
3645 // Figure out if there is a simple type corresponding to this Vector
3646 // type. If so, convert to the vector type.
3647 MVT TVT = MVT::getVectorVT(EVT, NumElems);
3648 if (TLI.isTypeLegal(TVT)) {
3649 // Turn this into a bit convert of the vector input.
3650 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3651 LegalizeOp(Node->getOperand(0)));
3653 } else if (NumElems == 1) {
3654 // Turn this into a bit convert of the scalar input.
3655 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3656 ScalarizeVectorOp(Node->getOperand(0)));
3659 // FIXME: UNIMP! Store then reload
3660 assert(0 && "Cast from unsupported vector type not implemented yet!");
3663 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3664 Node->getOperand(0).getValueType())) {
3665 default: assert(0 && "Unknown operation action!");
3666 case TargetLowering::Expand:
3667 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3668 Node->getValueType(0));
3670 case TargetLowering::Legal:
3671 Tmp1 = LegalizeOp(Node->getOperand(0));
3672 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3678 // Conversion operators. The source and destination have different types.
3679 case ISD::SINT_TO_FP:
3680 case ISD::UINT_TO_FP: {
3681 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
3682 Result = LegalizeINT_TO_FP(Result, isSigned,
3683 Node->getValueType(0), Node->getOperand(0));
3687 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3689 Tmp1 = LegalizeOp(Node->getOperand(0));
3690 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3693 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3695 // Since the result is legal, we should just be able to truncate the low
3696 // part of the source.
3697 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
3700 Result = PromoteOp(Node->getOperand(0));
3701 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
3706 case ISD::FP_TO_SINT:
3707 case ISD::FP_TO_UINT:
3708 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3710 Tmp1 = LegalizeOp(Node->getOperand(0));
3712 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
3713 default: assert(0 && "Unknown operation action!");
3714 case TargetLowering::Custom:
3717 case TargetLowering::Legal:
3718 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3720 Tmp1 = TLI.LowerOperation(Result, DAG);
3721 if (Tmp1.getNode()) Result = Tmp1;
3724 case TargetLowering::Promote:
3725 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
3726 Node->getOpcode() == ISD::FP_TO_SINT);
3728 case TargetLowering::Expand:
3729 if (Node->getOpcode() == ISD::FP_TO_UINT) {
3730 SDValue True, False;
3731 MVT VT = Node->getOperand(0).getValueType();
3732 MVT NVT = Node->getValueType(0);
3733 const uint64_t zero[] = {0, 0};
3734 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero));
3735 APInt x = APInt::getSignBit(NVT.getSizeInBits());
3736 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
3737 Tmp2 = DAG.getConstantFP(apf, VT);
3738 Tmp3 = DAG.getSetCC(TLI.getSetCCResultType(Node->getOperand(0)),
3739 Node->getOperand(0), Tmp2, ISD::SETLT);
3740 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
3741 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
3742 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
3744 False = DAG.getNode(ISD::XOR, NVT, False,
3745 DAG.getConstant(x, NVT));
3746 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
3749 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
3755 MVT VT = Op.getValueType();
3756 MVT OVT = Node->getOperand(0).getValueType();
3757 // Convert ppcf128 to i32
3758 if (OVT == MVT::ppcf128 && VT == MVT::i32) {
3759 if (Node->getOpcode() == ISD::FP_TO_SINT) {
3760 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128,
3761 Node->getOperand(0), DAG.getValueType(MVT::f64));
3762 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result,
3763 DAG.getIntPtrConstant(1));
3764 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result);
3766 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
3767 APFloat apf = APFloat(APInt(128, 2, TwoE31));
3768 Tmp2 = DAG.getConstantFP(apf, OVT);
3769 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
3770 // FIXME: generated code sucks.
3771 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2,
3772 DAG.getNode(ISD::ADD, MVT::i32,
3773 DAG.getNode(ISD::FP_TO_SINT, VT,
3774 DAG.getNode(ISD::FSUB, OVT,
3775 Node->getOperand(0), Tmp2)),
3776 DAG.getConstant(0x80000000, MVT::i32)),
3777 DAG.getNode(ISD::FP_TO_SINT, VT,
3778 Node->getOperand(0)),
3779 DAG.getCondCode(ISD::SETGE));
3783 // Convert f32 / f64 to i32 / i64 / i128.
3784 RTLIB::Libcall LC = (Node->getOpcode() == ISD::FP_TO_SINT) ?
3785 RTLIB::getFPTOSINT(OVT, VT) : RTLIB::getFPTOUINT(OVT, VT);
3786 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpectd fp-to-int conversion!");
3788 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3792 Tmp1 = PromoteOp(Node->getOperand(0));
3793 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
3794 Result = LegalizeOp(Result);
3799 case ISD::FP_EXTEND: {
3800 MVT DstVT = Op.getValueType();
3801 MVT SrcVT = Op.getOperand(0).getValueType();
3802 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3803 // The only other way we can lower this is to turn it into a STORE,
3804 // LOAD pair, targetting a temporary location (a stack slot).
3805 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT);
3808 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3809 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3811 Tmp1 = LegalizeOp(Node->getOperand(0));
3812 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3815 Tmp1 = PromoteOp(Node->getOperand(0));
3816 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1);
3821 case ISD::FP_ROUND: {
3822 MVT DstVT = Op.getValueType();
3823 MVT SrcVT = Op.getOperand(0).getValueType();
3824 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3825 if (SrcVT == MVT::ppcf128) {
3827 ExpandOp(Node->getOperand(0), Lo, Result);
3828 // Round it the rest of the way (e.g. to f32) if needed.
3829 if (DstVT!=MVT::f64)
3830 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1));
3833 // The only other way we can lower this is to turn it into a STORE,
3834 // LOAD pair, targetting a temporary location (a stack slot).
3835 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT);
3838 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3839 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3841 Tmp1 = LegalizeOp(Node->getOperand(0));
3842 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3845 Tmp1 = PromoteOp(Node->getOperand(0));
3846 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1,
3847 Node->getOperand(1));
3852 case ISD::ANY_EXTEND:
3853 case ISD::ZERO_EXTEND:
3854 case ISD::SIGN_EXTEND:
3855 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3856 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3858 Tmp1 = LegalizeOp(Node->getOperand(0));
3859 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3860 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3861 TargetLowering::Custom) {
3862 Tmp1 = TLI.LowerOperation(Result, DAG);
3863 if (Tmp1.getNode()) Result = Tmp1;
3867 switch (Node->getOpcode()) {
3868 case ISD::ANY_EXTEND:
3869 Tmp1 = PromoteOp(Node->getOperand(0));
3870 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
3872 case ISD::ZERO_EXTEND:
3873 Result = PromoteOp(Node->getOperand(0));
3874 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3875 Result = DAG.getZeroExtendInReg(Result,
3876 Node->getOperand(0).getValueType());
3878 case ISD::SIGN_EXTEND:
3879 Result = PromoteOp(Node->getOperand(0));
3880 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3881 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3883 DAG.getValueType(Node->getOperand(0).getValueType()));
3888 case ISD::FP_ROUND_INREG:
3889 case ISD::SIGN_EXTEND_INREG: {
3890 Tmp1 = LegalizeOp(Node->getOperand(0));
3891 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3893 // If this operation is not supported, convert it to a shl/shr or load/store
3895 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
3896 default: assert(0 && "This action not supported for this op yet!");
3897 case TargetLowering::Legal:
3898 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3900 case TargetLowering::Expand:
3901 // If this is an integer extend and shifts are supported, do that.
3902 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
3903 // NOTE: we could fall back on load/store here too for targets without
3904 // SAR. However, it is doubtful that any exist.
3905 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() -
3906 ExtraVT.getSizeInBits();
3907 SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
3908 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
3909 Node->getOperand(0), ShiftCst);
3910 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
3912 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
3913 // The only way we can lower this is to turn it into a TRUNCSTORE,
3914 // EXTLOAD pair, targetting a temporary location (a stack slot).
3916 // NOTE: there is a choice here between constantly creating new stack
3917 // slots and always reusing the same one. We currently always create
3918 // new ones, as reuse may inhibit scheduling.
3919 Result = EmitStackConvert(Node->getOperand(0), ExtraVT,
3920 Node->getValueType(0));
3922 assert(0 && "Unknown op");
3928 case ISD::TRAMPOLINE: {
3930 for (unsigned i = 0; i != 6; ++i)
3931 Ops[i] = LegalizeOp(Node->getOperand(i));
3932 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
3933 // The only option for this node is to custom lower it.
3934 Result = TLI.LowerOperation(Result, DAG);
3935 assert(Result.getNode() && "Should always custom lower!");
3937 // Since trampoline produces two values, make sure to remember that we
3938 // legalized both of them.
3939 Tmp1 = LegalizeOp(Result.getValue(1));
3940 Result = LegalizeOp(Result);
3941 AddLegalizedOperand(SDValue(Node, 0), Result);
3942 AddLegalizedOperand(SDValue(Node, 1), Tmp1);
3943 return Op.getResNo() ? Tmp1 : Result;
3945 case ISD::FLT_ROUNDS_: {
3946 MVT VT = Node->getValueType(0);
3947 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
3948 default: assert(0 && "This action not supported for this op yet!");
3949 case TargetLowering::Custom:
3950 Result = TLI.LowerOperation(Op, DAG);
3951 if (Result.getNode()) break;
3953 case TargetLowering::Legal:
3954 // If this operation is not supported, lower it to constant 1
3955 Result = DAG.getConstant(1, VT);
3961 MVT VT = Node->getValueType(0);
3962 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
3963 default: assert(0 && "This action not supported for this op yet!");
3964 case TargetLowering::Legal:
3965 Tmp1 = LegalizeOp(Node->getOperand(0));
3966 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3968 case TargetLowering::Custom:
3969 Result = TLI.LowerOperation(Op, DAG);
3970 if (Result.getNode()) break;
3972 case TargetLowering::Expand:
3973 // If this operation is not supported, lower it to 'abort()' call
3974 Tmp1 = LegalizeOp(Node->getOperand(0));
3975 TargetLowering::ArgListTy Args;
3976 std::pair<SDValue,SDValue> CallResult =
3977 TLI.LowerCallTo(Tmp1, Type::VoidTy,
3978 false, false, false, false, CallingConv::C, false,
3979 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
3981 Result = CallResult.second;
3988 assert(Result.getValueType() == Op.getValueType() &&
3989 "Bad legalization!");
3991 // Make sure that the generated code is itself legal.
3993 Result = LegalizeOp(Result);
3995 // Note that LegalizeOp may be reentered even from single-use nodes, which
3996 // means that we always must cache transformed nodes.
3997 AddLegalizedOperand(Op, Result);
4001 /// PromoteOp - Given an operation that produces a value in an invalid type,
4002 /// promote it to compute the value into a larger type. The produced value will
4003 /// have the correct bits for the low portion of the register, but no guarantee
4004 /// is made about the top bits: it may be zero, sign-extended, or garbage.
4005 SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) {
4006 MVT VT = Op.getValueType();
4007 MVT NVT = TLI.getTypeToTransformTo(VT);
4008 assert(getTypeAction(VT) == Promote &&
4009 "Caller should expand or legalize operands that are not promotable!");
4010 assert(NVT.bitsGT(VT) && NVT.isInteger() == VT.isInteger() &&
4011 "Cannot promote to smaller type!");
4013 SDValue Tmp1, Tmp2, Tmp3;
4015 SDNode *Node = Op.getNode();
4017 DenseMap<SDValue, SDValue>::iterator I = PromotedNodes.find(Op);
4018 if (I != PromotedNodes.end()) return I->second;
4020 switch (Node->getOpcode()) {
4021 case ISD::CopyFromReg:
4022 assert(0 && "CopyFromReg must be legal!");
4025 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
4027 assert(0 && "Do not know how to promote this operator!");
4030 Result = DAG.getNode(ISD::UNDEF, NVT);
4034 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
4036 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
4037 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
4039 case ISD::ConstantFP:
4040 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
4041 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
4045 assert(isTypeLegal(TLI.getSetCCResultType(Node->getOperand(0)))
4046 && "SetCC type is not legal??");
4047 Result = DAG.getNode(ISD::SETCC,
4048 TLI.getSetCCResultType(Node->getOperand(0)),
4049 Node->getOperand(0), Node->getOperand(1),
4050 Node->getOperand(2));
4054 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4056 Result = LegalizeOp(Node->getOperand(0));
4057 assert(Result.getValueType().bitsGE(NVT) &&
4058 "This truncation doesn't make sense!");
4059 if (Result.getValueType().bitsGT(NVT)) // Truncate to NVT instead of VT
4060 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
4063 // The truncation is not required, because we don't guarantee anything
4064 // about high bits anyway.
4065 Result = PromoteOp(Node->getOperand(0));
4068 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4069 // Truncate the low part of the expanded value to the result type
4070 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
4073 case ISD::SIGN_EXTEND:
4074 case ISD::ZERO_EXTEND:
4075 case ISD::ANY_EXTEND:
4076 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4077 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
4079 // Input is legal? Just do extend all the way to the larger type.
4080 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4083 // Promote the reg if it's smaller.
4084 Result = PromoteOp(Node->getOperand(0));
4085 // The high bits are not guaranteed to be anything. Insert an extend.
4086 if (Node->getOpcode() == ISD::SIGN_EXTEND)
4087 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4088 DAG.getValueType(Node->getOperand(0).getValueType()));
4089 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
4090 Result = DAG.getZeroExtendInReg(Result,
4091 Node->getOperand(0).getValueType());
4095 case ISD::BIT_CONVERT:
4096 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
4097 Node->getValueType(0));
4098 Result = PromoteOp(Result);
4101 case ISD::FP_EXTEND:
4102 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
4104 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4105 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
4106 case Promote: assert(0 && "Unreachable with 2 FP types!");
4108 if (Node->getConstantOperandVal(1) == 0) {
4109 // Input is legal? Do an FP_ROUND_INREG.
4110 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
4111 DAG.getValueType(VT));
4113 // Just remove the truncate, it isn't affecting the value.
4114 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0),
4115 Node->getOperand(1));
4120 case ISD::SINT_TO_FP:
4121 case ISD::UINT_TO_FP:
4122 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4124 // No extra round required here.
4125 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4129 Result = PromoteOp(Node->getOperand(0));
4130 if (Node->getOpcode() == ISD::SINT_TO_FP)
4131 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
4133 DAG.getValueType(Node->getOperand(0).getValueType()));
4135 Result = DAG.getZeroExtendInReg(Result,
4136 Node->getOperand(0).getValueType());
4137 // No extra round required here.
4138 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
4141 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
4142 Node->getOperand(0));
4143 // Round if we cannot tolerate excess precision.
4144 if (NoExcessFPPrecision)
4145 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4146 DAG.getValueType(VT));
4151 case ISD::SIGN_EXTEND_INREG:
4152 Result = PromoteOp(Node->getOperand(0));
4153 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4154 Node->getOperand(1));
4156 case ISD::FP_TO_SINT:
4157 case ISD::FP_TO_UINT:
4158 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4161 Tmp1 = Node->getOperand(0);
4164 // The input result is prerounded, so we don't have to do anything
4166 Tmp1 = PromoteOp(Node->getOperand(0));
4169 // If we're promoting a UINT to a larger size, check to see if the new node
4170 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
4171 // we can use that instead. This allows us to generate better code for
4172 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
4173 // legal, such as PowerPC.
4174 if (Node->getOpcode() == ISD::FP_TO_UINT &&
4175 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
4176 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
4177 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
4178 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
4180 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4186 Tmp1 = PromoteOp(Node->getOperand(0));
4187 assert(Tmp1.getValueType() == NVT);
4188 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4189 // NOTE: we do not have to do any extra rounding here for
4190 // NoExcessFPPrecision, because we know the input will have the appropriate
4191 // precision, and these operations don't modify precision at all.
4206 case ISD::FNEARBYINT:
4207 Tmp1 = PromoteOp(Node->getOperand(0));
4208 assert(Tmp1.getValueType() == NVT);
4209 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4210 if (NoExcessFPPrecision)
4211 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4212 DAG.getValueType(VT));
4217 // Promote f32 pow(i) to f64 pow(i). Note that this could insert a libcall
4218 // directly as well, which may be better.
4219 Tmp1 = PromoteOp(Node->getOperand(0));
4220 Tmp2 = Node->getOperand(1);
4221 if (Node->getOpcode() == ISD::FPOW)
4222 Tmp2 = PromoteOp(Tmp2);
4223 assert(Tmp1.getValueType() == NVT);
4224 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4225 if (NoExcessFPPrecision)
4226 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4227 DAG.getValueType(VT));
4231 case ISD::ATOMIC_CMP_SWAP_8:
4232 case ISD::ATOMIC_CMP_SWAP_16:
4233 case ISD::ATOMIC_CMP_SWAP_32:
4234 case ISD::ATOMIC_CMP_SWAP_64: {
4235 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4236 Tmp2 = PromoteOp(Node->getOperand(2));
4237 Tmp3 = PromoteOp(Node->getOperand(3));
4238 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(),
4239 AtomNode->getBasePtr(), Tmp2, Tmp3,
4240 AtomNode->getSrcValue(),
4241 AtomNode->getAlignment());
4242 // Remember that we legalized the chain.
4243 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4246 case ISD::ATOMIC_LOAD_ADD_8:
4247 case ISD::ATOMIC_LOAD_SUB_8:
4248 case ISD::ATOMIC_LOAD_AND_8:
4249 case ISD::ATOMIC_LOAD_OR_8:
4250 case ISD::ATOMIC_LOAD_XOR_8:
4251 case ISD::ATOMIC_LOAD_NAND_8:
4252 case ISD::ATOMIC_LOAD_MIN_8:
4253 case ISD::ATOMIC_LOAD_MAX_8:
4254 case ISD::ATOMIC_LOAD_UMIN_8:
4255 case ISD::ATOMIC_LOAD_UMAX_8:
4256 case ISD::ATOMIC_SWAP_8:
4257 case ISD::ATOMIC_LOAD_ADD_16:
4258 case ISD::ATOMIC_LOAD_SUB_16:
4259 case ISD::ATOMIC_LOAD_AND_16:
4260 case ISD::ATOMIC_LOAD_OR_16:
4261 case ISD::ATOMIC_LOAD_XOR_16:
4262 case ISD::ATOMIC_LOAD_NAND_16:
4263 case ISD::ATOMIC_LOAD_MIN_16:
4264 case ISD::ATOMIC_LOAD_MAX_16:
4265 case ISD::ATOMIC_LOAD_UMIN_16:
4266 case ISD::ATOMIC_LOAD_UMAX_16:
4267 case ISD::ATOMIC_SWAP_16:
4268 case ISD::ATOMIC_LOAD_ADD_32:
4269 case ISD::ATOMIC_LOAD_SUB_32:
4270 case ISD::ATOMIC_LOAD_AND_32:
4271 case ISD::ATOMIC_LOAD_OR_32:
4272 case ISD::ATOMIC_LOAD_XOR_32:
4273 case ISD::ATOMIC_LOAD_NAND_32:
4274 case ISD::ATOMIC_LOAD_MIN_32:
4275 case ISD::ATOMIC_LOAD_MAX_32:
4276 case ISD::ATOMIC_LOAD_UMIN_32:
4277 case ISD::ATOMIC_LOAD_UMAX_32:
4278 case ISD::ATOMIC_SWAP_32:
4279 case ISD::ATOMIC_LOAD_ADD_64:
4280 case ISD::ATOMIC_LOAD_SUB_64:
4281 case ISD::ATOMIC_LOAD_AND_64:
4282 case ISD::ATOMIC_LOAD_OR_64:
4283 case ISD::ATOMIC_LOAD_XOR_64:
4284 case ISD::ATOMIC_LOAD_NAND_64:
4285 case ISD::ATOMIC_LOAD_MIN_64:
4286 case ISD::ATOMIC_LOAD_MAX_64:
4287 case ISD::ATOMIC_LOAD_UMIN_64:
4288 case ISD::ATOMIC_LOAD_UMAX_64:
4289 case ISD::ATOMIC_SWAP_64: {
4290 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4291 Tmp2 = PromoteOp(Node->getOperand(2));
4292 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(),
4293 AtomNode->getBasePtr(), Tmp2,
4294 AtomNode->getSrcValue(),
4295 AtomNode->getAlignment());
4296 // Remember that we legalized the chain.
4297 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4307 // The input may have strange things in the top bits of the registers, but
4308 // these operations don't care. They may have weird bits going out, but
4309 // that too is okay if they are integer operations.
4310 Tmp1 = PromoteOp(Node->getOperand(0));
4311 Tmp2 = PromoteOp(Node->getOperand(1));
4312 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4313 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4318 Tmp1 = PromoteOp(Node->getOperand(0));
4319 Tmp2 = PromoteOp(Node->getOperand(1));
4320 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4321 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4323 // Floating point operations will give excess precision that we may not be
4324 // able to tolerate. If we DO allow excess precision, just leave it,
4325 // otherwise excise it.
4326 // FIXME: Why would we need to round FP ops more than integer ones?
4327 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
4328 if (NoExcessFPPrecision)
4329 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4330 DAG.getValueType(VT));
4335 // These operators require that their input be sign extended.
4336 Tmp1 = PromoteOp(Node->getOperand(0));
4337 Tmp2 = PromoteOp(Node->getOperand(1));
4338 if (NVT.isInteger()) {
4339 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4340 DAG.getValueType(VT));
4341 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4342 DAG.getValueType(VT));
4344 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4346 // Perform FP_ROUND: this is probably overly pessimistic.
4347 if (NVT.isFloatingPoint() && NoExcessFPPrecision)
4348 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4349 DAG.getValueType(VT));
4353 case ISD::FCOPYSIGN:
4354 // These operators require that their input be fp extended.
4355 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4356 case Expand: assert(0 && "not implemented");
4357 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break;
4358 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break;
4360 switch (getTypeAction(Node->getOperand(1).getValueType())) {
4361 case Expand: assert(0 && "not implemented");
4362 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
4363 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
4365 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4367 // Perform FP_ROUND: this is probably overly pessimistic.
4368 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
4369 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4370 DAG.getValueType(VT));
4375 // These operators require that their input be zero extended.
4376 Tmp1 = PromoteOp(Node->getOperand(0));
4377 Tmp2 = PromoteOp(Node->getOperand(1));
4378 assert(NVT.isInteger() && "Operators don't apply to FP!");
4379 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4380 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4381 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4385 Tmp1 = PromoteOp(Node->getOperand(0));
4386 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
4389 // The input value must be properly sign extended.
4390 Tmp1 = PromoteOp(Node->getOperand(0));
4391 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4392 DAG.getValueType(VT));
4393 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
4396 // The input value must be properly zero extended.
4397 Tmp1 = PromoteOp(Node->getOperand(0));
4398 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4399 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
4403 Tmp1 = Node->getOperand(0); // Get the chain.
4404 Tmp2 = Node->getOperand(1); // Get the pointer.
4405 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
4406 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
4407 Result = TLI.LowerOperation(Tmp3, DAG);
4409 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
4410 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
4411 // Increment the pointer, VAList, to the next vaarg
4412 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
4413 DAG.getConstant(VT.getSizeInBits()/8,
4414 TLI.getPointerTy()));
4415 // Store the incremented VAList to the legalized pointer
4416 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
4417 // Load the actual argument out of the pointer VAList
4418 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
4420 // Remember that we legalized the chain.
4421 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4425 LoadSDNode *LD = cast<LoadSDNode>(Node);
4426 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
4427 ? ISD::EXTLOAD : LD->getExtensionType();
4428 Result = DAG.getExtLoad(ExtType, NVT,
4429 LD->getChain(), LD->getBasePtr(),
4430 LD->getSrcValue(), LD->getSrcValueOffset(),
4433 LD->getAlignment());
4434 // Remember that we legalized the chain.
4435 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4439 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
4440 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
4442 MVT VT2 = Tmp2.getValueType();
4443 assert(VT2 == Tmp3.getValueType()
4444 && "PromoteOp SELECT: Operands 2 and 3 ValueTypes don't match");
4445 // Ensure that the resulting node is at least the same size as the operands'
4446 // value types, because we cannot assume that TLI.getSetCCValueType() is
4448 Result = DAG.getNode(ISD::SELECT, VT2, Node->getOperand(0), Tmp2, Tmp3);
4451 case ISD::SELECT_CC:
4452 Tmp2 = PromoteOp(Node->getOperand(2)); // True
4453 Tmp3 = PromoteOp(Node->getOperand(3)); // False
4454 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4455 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
4458 Tmp1 = Node->getOperand(0);
4459 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
4460 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
4461 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
4462 DAG.getConstant(NVT.getSizeInBits() -
4464 TLI.getShiftAmountTy()));
4469 // Zero extend the argument
4470 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4471 // Perform the larger operation, then subtract if needed.
4472 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4473 switch(Node->getOpcode()) {
4478 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
4479 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
4480 DAG.getConstant(NVT.getSizeInBits(), NVT),
4482 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
4483 DAG.getConstant(VT.getSizeInBits(), NVT), Tmp1);
4486 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4487 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
4488 DAG.getConstant(NVT.getSizeInBits() -
4489 VT.getSizeInBits(), NVT));
4493 case ISD::EXTRACT_SUBVECTOR:
4494 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
4496 case ISD::EXTRACT_VECTOR_ELT:
4497 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
4501 assert(Result.getNode() && "Didn't set a result!");
4503 // Make sure the result is itself legal.
4504 Result = LegalizeOp(Result);
4506 // Remember that we promoted this!
4507 AddPromotedOperand(Op, Result);
4511 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
4512 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
4513 /// based on the vector type. The return type of this matches the element type
4514 /// of the vector, which may not be legal for the target.
4515 SDValue SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDValue Op) {
4516 // We know that operand #0 is the Vec vector. If the index is a constant
4517 // or if the invec is a supported hardware type, we can use it. Otherwise,
4518 // lower to a store then an indexed load.
4519 SDValue Vec = Op.getOperand(0);
4520 SDValue Idx = Op.getOperand(1);
4522 MVT TVT = Vec.getValueType();
4523 unsigned NumElems = TVT.getVectorNumElements();
4525 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
4526 default: assert(0 && "This action is not supported yet!");
4527 case TargetLowering::Custom: {
4528 Vec = LegalizeOp(Vec);
4529 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4530 SDValue Tmp3 = TLI.LowerOperation(Op, DAG);
4535 case TargetLowering::Legal:
4536 if (isTypeLegal(TVT)) {
4537 Vec = LegalizeOp(Vec);
4538 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4542 case TargetLowering::Expand:
4546 if (NumElems == 1) {
4547 // This must be an access of the only element. Return it.
4548 Op = ScalarizeVectorOp(Vec);
4549 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
4550 unsigned NumLoElts = 1 << Log2_32(NumElems-1);
4551 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4553 SplitVectorOp(Vec, Lo, Hi);
4554 if (CIdx->getZExtValue() < NumLoElts) {
4558 Idx = DAG.getConstant(CIdx->getZExtValue() - NumLoElts,
4559 Idx.getValueType());
4562 // It's now an extract from the appropriate high or low part. Recurse.
4563 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4564 Op = ExpandEXTRACT_VECTOR_ELT(Op);
4566 // Store the value to a temporary stack slot, then LOAD the scalar
4567 // element back out.
4568 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
4569 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
4571 // Add the offset to the index.
4572 unsigned EltSize = Op.getValueType().getSizeInBits()/8;
4573 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
4574 DAG.getConstant(EltSize, Idx.getValueType()));
4576 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
4577 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx);
4579 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
4581 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
4583 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
4588 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
4589 /// we assume the operation can be split if it is not already legal.
4590 SDValue SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDValue Op) {
4591 // We know that operand #0 is the Vec vector. For now we assume the index
4592 // is a constant and that the extracted result is a supported hardware type.
4593 SDValue Vec = Op.getOperand(0);
4594 SDValue Idx = LegalizeOp(Op.getOperand(1));
4596 unsigned NumElems = Vec.getValueType().getVectorNumElements();
4598 if (NumElems == Op.getValueType().getVectorNumElements()) {
4599 // This must be an access of the desired vector length. Return it.
4603 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4605 SplitVectorOp(Vec, Lo, Hi);
4606 if (CIdx->getZExtValue() < NumElems/2) {
4610 Idx = DAG.getConstant(CIdx->getZExtValue() - NumElems/2,
4611 Idx.getValueType());
4614 // It's now an extract from the appropriate high or low part. Recurse.
4615 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4616 return ExpandEXTRACT_SUBVECTOR(Op);
4619 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
4620 /// with condition CC on the current target. This usually involves legalizing
4621 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
4622 /// there may be no choice but to create a new SetCC node to represent the
4623 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
4624 /// LHS, and the SDValue returned in RHS has a nil SDNode value.
4625 void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS,
4628 SDValue Tmp1, Tmp2, Tmp3, Result;
4630 switch (getTypeAction(LHS.getValueType())) {
4632 Tmp1 = LegalizeOp(LHS); // LHS
4633 Tmp2 = LegalizeOp(RHS); // RHS
4636 Tmp1 = PromoteOp(LHS); // LHS
4637 Tmp2 = PromoteOp(RHS); // RHS
4639 // If this is an FP compare, the operands have already been extended.
4640 if (LHS.getValueType().isInteger()) {
4641 MVT VT = LHS.getValueType();
4642 MVT NVT = TLI.getTypeToTransformTo(VT);
4644 // Otherwise, we have to insert explicit sign or zero extends. Note
4645 // that we could insert sign extends for ALL conditions, but zero extend
4646 // is cheaper on many machines (an AND instead of two shifts), so prefer
4648 switch (cast<CondCodeSDNode>(CC)->get()) {
4649 default: assert(0 && "Unknown integer comparison!");
4656 // ALL of these operations will work if we either sign or zero extend
4657 // the operands (including the unsigned comparisons!). Zero extend is
4658 // usually a simpler/cheaper operation, so prefer it.
4659 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4660 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4666 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4667 DAG.getValueType(VT));
4668 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4669 DAG.getValueType(VT));
4675 MVT VT = LHS.getValueType();
4676 if (VT == MVT::f32 || VT == MVT::f64) {
4677 // Expand into one or more soft-fp libcall(s).
4678 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
4679 switch (cast<CondCodeSDNode>(CC)->get()) {
4682 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4686 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
4690 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4694 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4698 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4702 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4705 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4708 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
4711 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4712 switch (cast<CondCodeSDNode>(CC)->get()) {
4714 // SETONE = SETOLT | SETOGT
4715 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4718 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4721 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4724 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4727 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4730 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4732 default: assert(0 && "Unsupported FP setcc!");
4737 SDValue Ops[2] = { LHS, RHS };
4738 Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2).getNode(),
4739 false /*sign irrelevant*/, Dummy);
4740 Tmp2 = DAG.getConstant(0, MVT::i32);
4741 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
4742 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
4743 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
4745 LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2).getNode(),
4746 false /*sign irrelevant*/, Dummy);
4747 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, Tmp2,
4748 DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
4749 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4752 LHS = LegalizeOp(Tmp1);
4757 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
4758 ExpandOp(LHS, LHSLo, LHSHi);
4759 ExpandOp(RHS, RHSLo, RHSHi);
4760 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
4762 if (VT==MVT::ppcf128) {
4763 // FIXME: This generated code sucks. We want to generate
4764 // FCMPU crN, hi1, hi2
4766 // FCMPU crN, lo1, lo2
4767 // The following can be improved, but not that much.
4768 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4770 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, CCCode);
4771 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4772 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4774 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode);
4775 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4776 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
4785 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
4786 if (RHSCST->isAllOnesValue()) {
4787 // Comparison to -1.
4788 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
4793 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
4794 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
4795 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4796 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
4799 // If this is a comparison of the sign bit, just look at the top part.
4801 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
4802 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
4803 CST->isNullValue()) || // X < 0
4804 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
4805 CST->isAllOnesValue())) { // X > -1
4811 // FIXME: This generated code sucks.
4812 ISD::CondCode LowCC;
4814 default: assert(0 && "Unknown integer setcc!");
4816 case ISD::SETULT: LowCC = ISD::SETULT; break;
4818 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
4820 case ISD::SETULE: LowCC = ISD::SETULE; break;
4822 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
4825 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
4826 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
4827 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
4829 // NOTE: on targets without efficient SELECT of bools, we can always use
4830 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
4831 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
4832 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo,
4833 LowCC, false, DagCombineInfo);
4834 if (!Tmp1.getNode())
4835 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC);
4836 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4837 CCCode, false, DagCombineInfo);
4838 if (!Tmp2.getNode())
4839 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi,
4842 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
4843 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
4844 if ((Tmp1C && Tmp1C->isNullValue()) ||
4845 (Tmp2C && Tmp2C->isNullValue() &&
4846 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
4847 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
4848 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
4849 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
4850 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
4851 // low part is known false, returns high part.
4852 // For LE / GE, if high part is known false, ignore the low part.
4853 // For LT / GT, if high part is known true, ignore the low part.
4857 Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4858 ISD::SETEQ, false, DagCombineInfo);
4859 if (!Result.getNode())
4860 Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4862 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
4863 Result, Tmp1, Tmp2));
4874 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
4875 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
4876 /// a load from the stack slot to DestVT, extending it if needed.
4877 /// The resultant code need not be legal.
4878 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
4881 // Create the stack frame object.
4882 unsigned SrcAlign = TLI.getTargetData()->getPrefTypeAlignment(
4883 SrcOp.getValueType().getTypeForMVT());
4884 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
4886 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
4887 int SPFI = StackPtrFI->getIndex();
4889 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
4890 unsigned SlotSize = SlotVT.getSizeInBits();
4891 unsigned DestSize = DestVT.getSizeInBits();
4892 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(
4893 DestVT.getTypeForMVT());
4895 // Emit a store to the stack slot. Use a truncstore if the input value is
4896 // later than DestVT.
4899 if (SrcSize > SlotSize)
4900 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr,
4901 PseudoSourceValue::getFixedStack(SPFI), 0,
4902 SlotVT, false, SrcAlign);
4904 assert(SrcSize == SlotSize && "Invalid store");
4905 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr,
4906 PseudoSourceValue::getFixedStack(SPFI), 0,
4910 // Result is a load from the stack slot.
4911 if (SlotSize == DestSize)
4912 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0, false, DestAlign);
4914 assert(SlotSize < DestSize && "Unknown extension!");
4915 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT,
4919 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
4920 // Create a vector sized/aligned stack slot, store the value to element #0,
4921 // then load the whole vector back out.
4922 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
4924 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
4925 int SPFI = StackPtrFI->getIndex();
4927 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
4928 PseudoSourceValue::getFixedStack(SPFI), 0);
4929 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,
4930 PseudoSourceValue::getFixedStack(SPFI), 0);
4934 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
4935 /// support the operation, but do support the resultant vector type.
4936 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
4938 // If the only non-undef value is the low element, turn this into a
4939 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
4940 unsigned NumElems = Node->getNumOperands();
4941 bool isOnlyLowElement = true;
4942 SDValue SplatValue = Node->getOperand(0);
4944 // FIXME: it would be far nicer to change this into map<SDValue,uint64_t>
4945 // and use a bitmask instead of a list of elements.
4946 std::map<SDValue, std::vector<unsigned> > Values;
4947 Values[SplatValue].push_back(0);
4948 bool isConstant = true;
4949 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
4950 SplatValue.getOpcode() != ISD::UNDEF)
4953 for (unsigned i = 1; i < NumElems; ++i) {
4954 SDValue V = Node->getOperand(i);
4955 Values[V].push_back(i);
4956 if (V.getOpcode() != ISD::UNDEF)
4957 isOnlyLowElement = false;
4958 if (SplatValue != V)
4959 SplatValue = SDValue(0,0);
4961 // If this isn't a constant element or an undef, we can't use a constant
4963 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
4964 V.getOpcode() != ISD::UNDEF)
4968 if (isOnlyLowElement) {
4969 // If the low element is an undef too, then this whole things is an undef.
4970 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
4971 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
4972 // Otherwise, turn this into a scalar_to_vector node.
4973 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4974 Node->getOperand(0));
4977 // If all elements are constants, create a load from the constant pool.
4979 MVT VT = Node->getValueType(0);
4980 std::vector<Constant*> CV;
4981 for (unsigned i = 0, e = NumElems; i != e; ++i) {
4982 if (ConstantFPSDNode *V =
4983 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
4984 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
4985 } else if (ConstantSDNode *V =
4986 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
4987 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
4989 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
4991 Node->getOperand(0).getValueType().getTypeForMVT();
4992 CV.push_back(UndefValue::get(OpNTy));
4995 Constant *CP = ConstantVector::get(CV);
4996 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
4997 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
4998 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4999 PseudoSourceValue::getConstantPool(), 0,
5003 if (SplatValue.getNode()) { // Splat of one value?
5004 // Build the shuffle constant vector: <0, 0, 0, 0>
5005 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
5006 SDValue Zero = DAG.getConstant(0, MaskVT.getVectorElementType());
5007 std::vector<SDValue> ZeroVec(NumElems, Zero);
5008 SDValue SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
5009 &ZeroVec[0], ZeroVec.size());
5011 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
5012 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
5013 // Get the splatted value into the low element of a vector register.
5015 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
5017 // Return shuffle(LowValVec, undef, <0,0,0,0>)
5018 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
5019 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
5024 // If there are only two unique elements, we may be able to turn this into a
5026 if (Values.size() == 2) {
5027 // Get the two values in deterministic order.
5028 SDValue Val1 = Node->getOperand(1);
5030 std::map<SDValue, std::vector<unsigned> >::iterator MI = Values.begin();
5031 if (MI->first != Val1)
5034 Val2 = (++MI)->first;
5036 // If Val1 is an undef, make sure end ends up as Val2, to ensure that our
5037 // vector shuffle has the undef vector on the RHS.
5038 if (Val1.getOpcode() == ISD::UNDEF)
5039 std::swap(Val1, Val2);
5041 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
5042 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
5043 MVT MaskEltVT = MaskVT.getVectorElementType();
5044 std::vector<SDValue> MaskVec(NumElems);
5046 // Set elements of the shuffle mask for Val1.
5047 std::vector<unsigned> &Val1Elts = Values[Val1];
5048 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i)
5049 MaskVec[Val1Elts[i]] = DAG.getConstant(0, MaskEltVT);
5051 // Set elements of the shuffle mask for Val2.
5052 std::vector<unsigned> &Val2Elts = Values[Val2];
5053 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i)
5054 if (Val2.getOpcode() != ISD::UNDEF)
5055 MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT);
5057 MaskVec[Val2Elts[i]] = DAG.getNode(ISD::UNDEF, MaskEltVT);
5059 SDValue ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
5060 &MaskVec[0], MaskVec.size());
5062 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it.
5063 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
5064 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
5065 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val1);
5066 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val2);
5067 SDValue Ops[] = { Val1, Val2, ShuffleMask };
5069 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
5070 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops, 3);
5074 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
5075 // aligned object on the stack, store each element into it, then load
5076 // the result as a vector.
5077 MVT VT = Node->getValueType(0);
5078 // Create the stack frame object.
5079 SDValue FIPtr = DAG.CreateStackTemporary(VT);
5081 // Emit a store of each element to the stack slot.
5082 SmallVector<SDValue, 8> Stores;
5083 unsigned TypeByteSize = Node->getOperand(0).getValueType().getSizeInBits()/8;
5084 // Store (in the right endianness) the elements to memory.
5085 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5086 // Ignore undef elements.
5087 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
5089 unsigned Offset = TypeByteSize*i;
5091 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
5092 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
5094 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
5099 if (!Stores.empty()) // Not all undef elements?
5100 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
5101 &Stores[0], Stores.size());
5103 StoreChain = DAG.getEntryNode();
5105 // Result is a load from the stack slot.
5106 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
5109 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
5110 SDValue Op, SDValue Amt,
5111 SDValue &Lo, SDValue &Hi) {
5112 // Expand the subcomponents.
5114 ExpandOp(Op, LHSL, LHSH);
5116 SDValue Ops[] = { LHSL, LHSH, Amt };
5117 MVT VT = LHSL.getValueType();
5118 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
5119 Hi = Lo.getValue(1);
5123 /// ExpandShift - Try to find a clever way to expand this shift operation out to
5124 /// smaller elements. If we can't find a way that is more efficient than a
5125 /// libcall on this target, return false. Otherwise, return true with the
5126 /// low-parts expanded into Lo and Hi.
5127 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op,SDValue Amt,
5128 SDValue &Lo, SDValue &Hi) {
5129 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
5130 "This is not a shift!");
5132 MVT NVT = TLI.getTypeToTransformTo(Op.getValueType());
5133 SDValue ShAmt = LegalizeOp(Amt);
5134 MVT ShTy = ShAmt.getValueType();
5135 unsigned ShBits = ShTy.getSizeInBits();
5136 unsigned VTBits = Op.getValueType().getSizeInBits();
5137 unsigned NVTBits = NVT.getSizeInBits();
5139 // Handle the case when Amt is an immediate.
5140 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.getNode())) {
5141 unsigned Cst = CN->getZExtValue();
5142 // Expand the incoming operand to be shifted, so that we have its parts
5144 ExpandOp(Op, InL, InH);
5148 Lo = DAG.getConstant(0, NVT);
5149 Hi = DAG.getConstant(0, NVT);
5150 } else if (Cst > NVTBits) {
5151 Lo = DAG.getConstant(0, NVT);
5152 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
5153 } else if (Cst == NVTBits) {
5154 Lo = DAG.getConstant(0, NVT);
5157 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
5158 Hi = DAG.getNode(ISD::OR, NVT,
5159 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
5160 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
5165 Lo = DAG.getConstant(0, NVT);
5166 Hi = DAG.getConstant(0, NVT);
5167 } else if (Cst > NVTBits) {
5168 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
5169 Hi = DAG.getConstant(0, NVT);
5170 } else if (Cst == NVTBits) {
5172 Hi = DAG.getConstant(0, NVT);
5174 Lo = DAG.getNode(ISD::OR, NVT,
5175 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5176 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5177 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
5182 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
5183 DAG.getConstant(NVTBits-1, ShTy));
5184 } else if (Cst > NVTBits) {
5185 Lo = DAG.getNode(ISD::SRA, NVT, InH,
5186 DAG.getConstant(Cst-NVTBits, ShTy));
5187 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5188 DAG.getConstant(NVTBits-1, ShTy));
5189 } else if (Cst == NVTBits) {
5191 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5192 DAG.getConstant(NVTBits-1, ShTy));
5194 Lo = DAG.getNode(ISD::OR, NVT,
5195 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5196 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5197 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
5203 // Okay, the shift amount isn't constant. However, if we can tell that it is
5204 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
5205 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
5206 APInt KnownZero, KnownOne;
5207 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
5209 // If we know that if any of the high bits of the shift amount are one, then
5210 // we can do this as a couple of simple shifts.
5211 if (KnownOne.intersects(Mask)) {
5212 // Mask out the high bit, which we know is set.
5213 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
5214 DAG.getConstant(~Mask, Amt.getValueType()));
5216 // Expand the incoming operand to be shifted, so that we have its parts
5218 ExpandOp(Op, InL, InH);
5221 Lo = DAG.getConstant(0, NVT); // Low part is zero.
5222 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
5225 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
5226 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
5229 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
5230 DAG.getConstant(NVTBits-1, Amt.getValueType()));
5231 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
5236 // If we know that the high bits of the shift amount are all zero, then we can
5237 // do this as a couple of simple shifts.
5238 if ((KnownZero & Mask) == Mask) {
5240 SDValue Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
5241 DAG.getConstant(NVTBits, Amt.getValueType()),
5244 // Expand the incoming operand to be shifted, so that we have its parts
5246 ExpandOp(Op, InL, InH);
5249 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
5250 Hi = DAG.getNode(ISD::OR, NVT,
5251 DAG.getNode(ISD::SHL, NVT, InH, Amt),
5252 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
5255 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
5256 Lo = DAG.getNode(ISD::OR, NVT,
5257 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5258 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5261 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
5262 Lo = DAG.getNode(ISD::OR, NVT,
5263 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5264 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5273 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
5274 // does not fit into a register, return the lo part and set the hi part to the
5275 // by-reg argument. If it does fit into a single register, return the result
5276 // and leave the Hi part unset.
5277 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
5278 bool isSigned, SDValue &Hi) {
5279 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
5280 // The input chain to this libcall is the entry node of the function.
5281 // Legalizing the call will automatically add the previous call to the
5283 SDValue InChain = DAG.getEntryNode();
5285 TargetLowering::ArgListTy Args;
5286 TargetLowering::ArgListEntry Entry;
5287 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5288 MVT ArgVT = Node->getOperand(i).getValueType();
5289 const Type *ArgTy = ArgVT.getTypeForMVT();
5290 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
5291 Entry.isSExt = isSigned;
5292 Entry.isZExt = !isSigned;
5293 Args.push_back(Entry);
5295 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
5296 TLI.getPointerTy());
5298 // Splice the libcall in wherever FindInputOutputChains tells us to.
5299 const Type *RetTy = Node->getValueType(0).getTypeForMVT();
5300 std::pair<SDValue,SDValue> CallInfo =
5301 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
5302 CallingConv::C, false, Callee, Args, DAG);
5304 // Legalize the call sequence, starting with the chain. This will advance
5305 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
5306 // was added by LowerCallTo (guaranteeing proper serialization of calls).
5307 LegalizeOp(CallInfo.second);
5309 switch (getTypeAction(CallInfo.first.getValueType())) {
5310 default: assert(0 && "Unknown thing");
5312 Result = CallInfo.first;
5315 ExpandOp(CallInfo.first, Result, Hi);
5321 /// LegalizeINT_TO_FP - Legalize a [US]INT_TO_FP operation.
5323 SDValue SelectionDAGLegalize::
5324 LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op) {
5325 bool isCustom = false;
5327 switch (getTypeAction(Op.getValueType())) {
5329 switch (TLI.getOperationAction(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5330 Op.getValueType())) {
5331 default: assert(0 && "Unknown operation action!");
5332 case TargetLowering::Custom:
5335 case TargetLowering::Legal:
5336 Tmp1 = LegalizeOp(Op);
5337 if (Result.getNode())
5338 Result = DAG.UpdateNodeOperands(Result, Tmp1);
5340 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5343 Tmp1 = TLI.LowerOperation(Result, DAG);
5344 if (Tmp1.getNode()) Result = Tmp1;
5347 case TargetLowering::Expand:
5348 Result = ExpandLegalINT_TO_FP(isSigned, LegalizeOp(Op), DestTy);
5350 case TargetLowering::Promote:
5351 Result = PromoteLegalINT_TO_FP(LegalizeOp(Op), DestTy, isSigned);
5356 Result = ExpandIntToFP(isSigned, DestTy, Op);
5359 Tmp1 = PromoteOp(Op);
5361 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
5362 Tmp1, DAG.getValueType(Op.getValueType()));
5364 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
5367 if (Result.getNode())
5368 Result = DAG.UpdateNodeOperands(Result, Tmp1);
5370 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5372 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
5378 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
5380 SDValue SelectionDAGLegalize::
5381 ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source) {
5382 MVT SourceVT = Source.getValueType();
5383 bool ExpandSource = getTypeAction(SourceVT) == Expand;
5385 // Expand unsupported int-to-fp vector casts by unrolling them.
5386 if (DestTy.isVector()) {
5388 return LegalizeOp(UnrollVectorOp(Source));
5389 MVT DestEltTy = DestTy.getVectorElementType();
5390 if (DestTy.getVectorNumElements() == 1) {
5391 SDValue Scalar = ScalarizeVectorOp(Source);
5392 SDValue Result = LegalizeINT_TO_FP(SDValue(), isSigned,
5394 return DAG.getNode(ISD::BUILD_VECTOR, DestTy, Result);
5397 SplitVectorOp(Source, Lo, Hi);
5398 MVT SplitDestTy = MVT::getVectorVT(DestEltTy,
5399 DestTy.getVectorNumElements() / 2);
5400 SDValue LoResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, Lo);
5401 SDValue HiResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, Hi);
5402 return LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, DestTy, LoResult, HiResult));
5405 // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc.
5406 if (!isSigned && SourceVT != MVT::i32) {
5407 // The integer value loaded will be incorrectly if the 'sign bit' of the
5408 // incoming integer is set. To handle this, we dynamically test to see if
5409 // it is set, and, if so, add a fudge factor.
5413 ExpandOp(Source, Lo, Hi);
5414 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi);
5416 // The comparison for the sign bit will use the entire operand.
5420 // If this is unsigned, and not supported, first perform the conversion to
5421 // signed, then adjust the result if the sign bit is set.
5422 SDValue SignedConv = ExpandIntToFP(true, DestTy, Source);
5424 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
5425 DAG.getConstant(0, Hi.getValueType()),
5427 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5428 SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5429 SignSet, Four, Zero);
5430 uint64_t FF = 0x5f800000ULL;
5431 if (TLI.isLittleEndian()) FF <<= 32;
5432 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5434 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5435 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5436 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5437 Alignment = std::min(Alignment, 4u);
5439 if (DestTy == MVT::f32)
5440 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5441 PseudoSourceValue::getConstantPool(), 0,
5443 else if (DestTy.bitsGT(MVT::f32))
5444 // FIXME: Avoid the extend by construction the right constantpool?
5445 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
5447 PseudoSourceValue::getConstantPool(), 0,
5448 MVT::f32, false, Alignment);
5450 assert(0 && "Unexpected conversion");
5452 MVT SCVT = SignedConv.getValueType();
5453 if (SCVT != DestTy) {
5454 // Destination type needs to be expanded as well. The FADD now we are
5455 // constructing will be expanded into a libcall.
5456 if (SCVT.getSizeInBits() != DestTy.getSizeInBits()) {
5457 assert(SCVT.getSizeInBits() * 2 == DestTy.getSizeInBits());
5458 SignedConv = DAG.getNode(ISD::BUILD_PAIR, DestTy,
5459 SignedConv, SignedConv.getValue(1));
5461 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
5463 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
5466 // Check to see if the target has a custom way to lower this. If so, use it.
5467 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) {
5468 default: assert(0 && "This action not implemented for this operation!");
5469 case TargetLowering::Legal:
5470 case TargetLowering::Expand:
5471 break; // This case is handled below.
5472 case TargetLowering::Custom: {
5473 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
5476 return LegalizeOp(NV);
5477 break; // The target decided this was legal after all
5481 // Expand the source, then glue it back together for the call. We must expand
5482 // the source in case it is shared (this pass of legalize must traverse it).
5484 SDValue SrcLo, SrcHi;
5485 ExpandOp(Source, SrcLo, SrcHi);
5486 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, SrcLo, SrcHi);
5489 RTLIB::Libcall LC = isSigned ?
5490 RTLIB::getSINTTOFP(SourceVT, DestTy) :
5491 RTLIB::getUINTTOFP(SourceVT, DestTy);
5492 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unknown int value type");
5494 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
5496 SDValue Result = ExpandLibCall(LC, Source.getNode(), isSigned, HiPart);
5497 if (Result.getValueType() != DestTy && HiPart.getNode())
5498 Result = DAG.getNode(ISD::BUILD_PAIR, DestTy, Result, HiPart);
5502 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
5503 /// INT_TO_FP operation of the specified operand when the target requests that
5504 /// we expand it. At this point, we know that the result and operand types are
5505 /// legal for the target.
5506 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
5509 if (Op0.getValueType() == MVT::i32) {
5510 // simple 32-bit [signed|unsigned] integer to float/double expansion
5512 // Get the stack frame index of a 8 byte buffer.
5513 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
5515 // word offset constant for Hi/Lo address computation
5516 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
5517 // set up Hi and Lo (into buffer) address based on endian
5518 SDValue Hi = StackSlot;
5519 SDValue Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
5520 if (TLI.isLittleEndian())
5523 // if signed map to unsigned space
5526 // constant used to invert sign bit (signed to unsigned mapping)
5527 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
5528 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
5532 // store the lo of the constructed double - based on integer input
5533 SDValue Store1 = DAG.getStore(DAG.getEntryNode(),
5534 Op0Mapped, Lo, NULL, 0);
5535 // initial hi portion of constructed double
5536 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
5537 // store the hi of the constructed double - biased exponent
5538 SDValue Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
5539 // load the constructed double
5540 SDValue Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
5541 // FP constant to bias correct the final result
5542 SDValue Bias = DAG.getConstantFP(isSigned ?
5543 BitsToDouble(0x4330000080000000ULL)
5544 : BitsToDouble(0x4330000000000000ULL),
5546 // subtract the bias
5547 SDValue Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
5550 // handle final rounding
5551 if (DestVT == MVT::f64) {
5554 } else if (DestVT.bitsLT(MVT::f64)) {
5555 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub,
5556 DAG.getIntPtrConstant(0));
5557 } else if (DestVT.bitsGT(MVT::f64)) {
5558 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
5562 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
5563 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
5565 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Op0), Op0,
5566 DAG.getConstant(0, Op0.getValueType()),
5568 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5569 SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5570 SignSet, Four, Zero);
5572 // If the sign bit of the integer is set, the large number will be treated
5573 // as a negative number. To counteract this, the dynamic code adds an
5574 // offset depending on the data type.
5576 switch (Op0.getValueType().getSimpleVT()) {
5577 default: assert(0 && "Unsupported integer type!");
5578 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
5579 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
5580 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
5581 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
5583 if (TLI.isLittleEndian()) FF <<= 32;
5584 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5586 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5587 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5588 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5589 Alignment = std::min(Alignment, 4u);
5591 if (DestVT == MVT::f32)
5592 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5593 PseudoSourceValue::getConstantPool(), 0,
5597 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT,
5598 DAG.getEntryNode(), CPIdx,
5599 PseudoSourceValue::getConstantPool(), 0,
5600 MVT::f32, false, Alignment));
5603 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
5606 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
5607 /// *INT_TO_FP operation of the specified operand when the target requests that
5608 /// we promote it. At this point, we know that the result and operand types are
5609 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
5610 /// operation that takes a larger input.
5611 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
5614 // First step, figure out the appropriate *INT_TO_FP operation to use.
5615 MVT NewInTy = LegalOp.getValueType();
5617 unsigned OpToUse = 0;
5619 // Scan for the appropriate larger type to use.
5621 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
5622 assert(NewInTy.isInteger() && "Ran out of possibilities!");
5624 // If the target supports SINT_TO_FP of this type, use it.
5625 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
5627 case TargetLowering::Legal:
5628 if (!TLI.isTypeLegal(NewInTy))
5629 break; // Can't use this datatype.
5631 case TargetLowering::Custom:
5632 OpToUse = ISD::SINT_TO_FP;
5636 if (isSigned) continue;
5638 // If the target supports UINT_TO_FP of this type, use it.
5639 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
5641 case TargetLowering::Legal:
5642 if (!TLI.isTypeLegal(NewInTy))
5643 break; // Can't use this datatype.
5645 case TargetLowering::Custom:
5646 OpToUse = ISD::UINT_TO_FP;
5651 // Otherwise, try a larger type.
5654 // Okay, we found the operation and type to use. Zero extend our input to the
5655 // desired type then run the operation on it.
5656 return DAG.getNode(OpToUse, DestVT,
5657 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
5661 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
5662 /// FP_TO_*INT operation of the specified operand when the target requests that
5663 /// we promote it. At this point, we know that the result and operand types are
5664 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
5665 /// operation that returns a larger result.
5666 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
5669 // First step, figure out the appropriate FP_TO*INT operation to use.
5670 MVT NewOutTy = DestVT;
5672 unsigned OpToUse = 0;
5674 // Scan for the appropriate larger type to use.
5676 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1);
5677 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
5679 // If the target supports FP_TO_SINT returning this type, use it.
5680 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
5682 case TargetLowering::Legal:
5683 if (!TLI.isTypeLegal(NewOutTy))
5684 break; // Can't use this datatype.
5686 case TargetLowering::Custom:
5687 OpToUse = ISD::FP_TO_SINT;
5692 // If the target supports FP_TO_UINT of this type, use it.
5693 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
5695 case TargetLowering::Legal:
5696 if (!TLI.isTypeLegal(NewOutTy))
5697 break; // Can't use this datatype.
5699 case TargetLowering::Custom:
5700 OpToUse = ISD::FP_TO_UINT;
5705 // Otherwise, try a larger type.
5709 // Okay, we found the operation and type to use.
5710 SDValue Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp);
5712 // If the operation produces an invalid type, it must be custom lowered. Use
5713 // the target lowering hooks to expand it. Just keep the low part of the
5714 // expanded operation, we know that we're truncating anyway.
5715 if (getTypeAction(NewOutTy) == Expand) {
5716 Operation = SDValue(TLI.ReplaceNodeResults(Operation.getNode(), DAG), 0);
5717 assert(Operation.getNode() && "Didn't return anything");
5720 // Truncate the result of the extended FP_TO_*INT operation to the desired
5722 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation);
5725 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
5727 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op) {
5728 MVT VT = Op.getValueType();
5729 MVT SHVT = TLI.getShiftAmountTy();
5730 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
5731 switch (VT.getSimpleVT()) {
5732 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
5734 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5735 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5736 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
5738 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5739 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5740 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5741 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5742 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
5743 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
5744 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5745 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5746 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5748 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
5749 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
5750 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5751 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5752 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5753 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5754 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
5755 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
5756 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
5757 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
5758 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
5759 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
5760 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
5761 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
5762 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
5763 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
5764 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5765 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5766 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
5767 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5768 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
5772 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
5774 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op) {
5776 default: assert(0 && "Cannot expand this yet!");
5778 static const uint64_t mask[6] = {
5779 0x5555555555555555ULL, 0x3333333333333333ULL,
5780 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
5781 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
5783 MVT VT = Op.getValueType();
5784 MVT ShVT = TLI.getShiftAmountTy();
5785 unsigned len = VT.getSizeInBits();
5786 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5787 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
5788 SDValue Tmp2 = DAG.getConstant(mask[i], VT);
5789 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5790 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
5791 DAG.getNode(ISD::AND, VT,
5792 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
5797 // for now, we do this:
5798 // x = x | (x >> 1);
5799 // x = x | (x >> 2);
5801 // x = x | (x >>16);
5802 // x = x | (x >>32); // for 64-bit input
5803 // return popcount(~x);
5805 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
5806 MVT VT = Op.getValueType();
5807 MVT ShVT = TLI.getShiftAmountTy();
5808 unsigned len = VT.getSizeInBits();
5809 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5810 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5811 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
5813 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
5814 return DAG.getNode(ISD::CTPOP, VT, Op);
5817 // for now, we use: { return popcount(~x & (x - 1)); }
5818 // unless the target has ctlz but not ctpop, in which case we use:
5819 // { return 32 - nlz(~x & (x-1)); }
5820 // see also http://www.hackersdelight.org/HDcode/ntz.cc
5821 MVT VT = Op.getValueType();
5822 SDValue Tmp2 = DAG.getConstant(~0ULL, VT);
5823 SDValue Tmp3 = DAG.getNode(ISD::AND, VT,
5824 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
5825 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
5826 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
5827 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
5828 TLI.isOperationLegal(ISD::CTLZ, VT))
5829 return DAG.getNode(ISD::SUB, VT,
5830 DAG.getConstant(VT.getSizeInBits(), VT),
5831 DAG.getNode(ISD::CTLZ, VT, Tmp3));
5832 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
5837 /// ExpandOp - Expand the specified SDValue into its two component pieces
5838 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
5839 /// LegalizedNodes map is filled in for any results that are not expanded, the
5840 /// ExpandedNodes map is filled in for any results that are expanded, and the
5841 /// Lo/Hi values are returned.
5842 void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
5843 MVT VT = Op.getValueType();
5844 MVT NVT = TLI.getTypeToTransformTo(VT);
5845 SDNode *Node = Op.getNode();
5846 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
5847 assert(((NVT.isInteger() && NVT.bitsLT(VT)) || VT.isFloatingPoint() ||
5848 VT.isVector()) && "Cannot expand to FP value or to larger int value!");
5850 // See if we already expanded it.
5851 DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator I
5852 = ExpandedNodes.find(Op);
5853 if (I != ExpandedNodes.end()) {
5854 Lo = I->second.first;
5855 Hi = I->second.second;
5859 switch (Node->getOpcode()) {
5860 case ISD::CopyFromReg:
5861 assert(0 && "CopyFromReg must be legal!");
5862 case ISD::FP_ROUND_INREG:
5863 if (VT == MVT::ppcf128 &&
5864 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
5865 TargetLowering::Custom) {
5866 SDValue SrcLo, SrcHi, Src;
5867 ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
5868 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi);
5869 SDValue Result = TLI.LowerOperation(
5870 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG);
5871 assert(Result.getNode()->getOpcode() == ISD::BUILD_PAIR);
5872 Lo = Result.getNode()->getOperand(0);
5873 Hi = Result.getNode()->getOperand(1);
5879 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
5881 assert(0 && "Do not know how to expand this operator!");
5883 case ISD::EXTRACT_ELEMENT:
5884 ExpandOp(Node->getOperand(0), Lo, Hi);
5885 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
5886 return ExpandOp(Hi, Lo, Hi);
5887 return ExpandOp(Lo, Lo, Hi);
5888 case ISD::EXTRACT_VECTOR_ELT:
5889 assert(VT==MVT::i64 && "Do not know how to expand this operator!");
5890 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types.
5891 Lo = ExpandEXTRACT_VECTOR_ELT(Op);
5892 return ExpandOp(Lo, Lo, Hi);
5894 Lo = DAG.getNode(ISD::UNDEF, NVT);
5895 Hi = DAG.getNode(ISD::UNDEF, NVT);
5897 case ISD::Constant: {
5898 unsigned NVTBits = NVT.getSizeInBits();
5899 const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue();
5900 Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT);
5901 Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT);
5904 case ISD::ConstantFP: {
5905 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
5906 if (CFP->getValueType(0) == MVT::ppcf128) {
5907 APInt api = CFP->getValueAPF().convertToAPInt();
5908 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
5910 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
5914 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
5915 if (getTypeAction(Lo.getValueType()) == Expand)
5916 ExpandOp(Lo, Lo, Hi);
5919 case ISD::BUILD_PAIR:
5920 // Return the operands.
5921 Lo = Node->getOperand(0);
5922 Hi = Node->getOperand(1);
5925 case ISD::MERGE_VALUES:
5926 if (Node->getNumValues() == 1) {
5927 ExpandOp(Op.getOperand(0), Lo, Hi);
5930 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y)
5931 assert(Op.getResNo() == 0 && Node->getNumValues() == 2 &&
5932 Op.getValue(1).getValueType() == MVT::Other &&
5933 "unhandled MERGE_VALUES");
5934 ExpandOp(Op.getOperand(0), Lo, Hi);
5935 // Remember that we legalized the chain.
5936 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1)));
5939 case ISD::SIGN_EXTEND_INREG:
5940 ExpandOp(Node->getOperand(0), Lo, Hi);
5941 // sext_inreg the low part if needed.
5942 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
5944 // The high part gets the sign extension from the lo-part. This handles
5945 // things like sextinreg V:i64 from i8.
5946 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5947 DAG.getConstant(NVT.getSizeInBits()-1,
5948 TLI.getShiftAmountTy()));
5952 ExpandOp(Node->getOperand(0), Lo, Hi);
5953 SDValue TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
5954 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
5960 ExpandOp(Node->getOperand(0), Lo, Hi);
5961 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
5962 DAG.getNode(ISD::CTPOP, NVT, Lo),
5963 DAG.getNode(ISD::CTPOP, NVT, Hi));
5964 Hi = DAG.getConstant(0, NVT);
5968 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
5969 ExpandOp(Node->getOperand(0), Lo, Hi);
5970 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
5971 SDValue HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
5972 SDValue TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(HLZ), HLZ, BitsC,
5974 SDValue LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
5975 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
5977 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
5978 Hi = DAG.getConstant(0, NVT);
5983 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
5984 ExpandOp(Node->getOperand(0), Lo, Hi);
5985 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
5986 SDValue LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
5987 SDValue BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(LTZ), LTZ, BitsC,
5989 SDValue HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
5990 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
5992 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
5993 Hi = DAG.getConstant(0, NVT);
5998 SDValue Ch = Node->getOperand(0); // Legalize the chain.
5999 SDValue Ptr = Node->getOperand(1); // Legalize the pointer.
6000 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
6001 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
6003 // Remember that we legalized the chain.
6004 Hi = LegalizeOp(Hi);
6005 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
6006 if (TLI.isBigEndian())
6012 LoadSDNode *LD = cast<LoadSDNode>(Node);
6013 SDValue Ch = LD->getChain(); // Legalize the chain.
6014 SDValue Ptr = LD->getBasePtr(); // Legalize the pointer.
6015 ISD::LoadExtType ExtType = LD->getExtensionType();
6016 const Value *SV = LD->getSrcValue();
6017 int SVOffset = LD->getSrcValueOffset();
6018 unsigned Alignment = LD->getAlignment();
6019 bool isVolatile = LD->isVolatile();
6021 if (ExtType == ISD::NON_EXTLOAD) {
6022 Lo = DAG.getLoad(NVT, Ch, Ptr, SV, SVOffset,
6023 isVolatile, Alignment);
6024 if (VT == MVT::f32 || VT == MVT::f64) {
6025 // f32->i32 or f64->i64 one to one expansion.
6026 // Remember that we legalized the chain.
6027 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
6028 // Recursively expand the new load.
6029 if (getTypeAction(NVT) == Expand)
6030 ExpandOp(Lo, Lo, Hi);
6034 // Increment the pointer to the other half.
6035 unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8;
6036 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
6037 DAG.getIntPtrConstant(IncrementSize));
6038 SVOffset += IncrementSize;
6039 Alignment = MinAlign(Alignment, IncrementSize);
6040 Hi = DAG.getLoad(NVT, Ch, Ptr, SV, SVOffset,
6041 isVolatile, Alignment);
6043 // Build a factor node to remember that this load is independent of the
6045 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
6048 // Remember that we legalized the chain.
6049 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
6050 if (TLI.isBigEndian())
6053 MVT EVT = LD->getMemoryVT();
6055 if ((VT == MVT::f64 && EVT == MVT::f32) ||
6056 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
6057 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
6058 SDValue Load = DAG.getLoad(EVT, Ch, Ptr, SV,
6059 SVOffset, isVolatile, Alignment);
6060 // Remember that we legalized the chain.
6061 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Load.getValue(1)));
6062 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
6067 Lo = DAG.getLoad(NVT, Ch, Ptr, SV,
6068 SVOffset, isVolatile, Alignment);
6070 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, SV,
6071 SVOffset, EVT, isVolatile,
6074 // Remember that we legalized the chain.
6075 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
6077 if (ExtType == ISD::SEXTLOAD) {
6078 // The high part is obtained by SRA'ing all but one of the bits of the
6080 unsigned LoSize = Lo.getValueType().getSizeInBits();
6081 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6082 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6083 } else if (ExtType == ISD::ZEXTLOAD) {
6084 // The high part is just a zero.
6085 Hi = DAG.getConstant(0, NVT);
6086 } else /* if (ExtType == ISD::EXTLOAD) */ {
6087 // The high part is undefined.
6088 Hi = DAG.getNode(ISD::UNDEF, NVT);
6095 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
6096 SDValue LL, LH, RL, RH;
6097 ExpandOp(Node->getOperand(0), LL, LH);
6098 ExpandOp(Node->getOperand(1), RL, RH);
6099 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
6100 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
6104 SDValue LL, LH, RL, RH;
6105 ExpandOp(Node->getOperand(1), LL, LH);
6106 ExpandOp(Node->getOperand(2), RL, RH);
6107 if (getTypeAction(NVT) == Expand)
6108 NVT = TLI.getTypeToExpandTo(NVT);
6109 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
6111 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
6114 case ISD::SELECT_CC: {
6115 SDValue TL, TH, FL, FH;
6116 ExpandOp(Node->getOperand(2), TL, TH);
6117 ExpandOp(Node->getOperand(3), FL, FH);
6118 if (getTypeAction(NVT) == Expand)
6119 NVT = TLI.getTypeToExpandTo(NVT);
6120 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
6121 Node->getOperand(1), TL, FL, Node->getOperand(4));
6123 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
6124 Node->getOperand(1), TH, FH, Node->getOperand(4));
6127 case ISD::ANY_EXTEND:
6128 // The low part is any extension of the input (which degenerates to a copy).
6129 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
6130 // The high part is undefined.
6131 Hi = DAG.getNode(ISD::UNDEF, NVT);
6133 case ISD::SIGN_EXTEND: {
6134 // The low part is just a sign extension of the input (which degenerates to
6136 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
6138 // The high part is obtained by SRA'ing all but one of the bits of the lo
6140 unsigned LoSize = Lo.getValueType().getSizeInBits();
6141 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6142 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6145 case ISD::ZERO_EXTEND:
6146 // The low part is just a zero extension of the input (which degenerates to
6148 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
6150 // The high part is just a zero.
6151 Hi = DAG.getConstant(0, NVT);
6154 case ISD::TRUNCATE: {
6155 // The input value must be larger than this value. Expand *it*.
6157 ExpandOp(Node->getOperand(0), NewLo, Hi);
6159 // The low part is now either the right size, or it is closer. If not the
6160 // right size, make an illegal truncate so we recursively expand it.
6161 if (NewLo.getValueType() != Node->getValueType(0))
6162 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
6163 ExpandOp(NewLo, Lo, Hi);
6167 case ISD::BIT_CONVERT: {
6169 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
6170 // If the target wants to, allow it to lower this itself.
6171 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6172 case Expand: assert(0 && "cannot expand FP!");
6173 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
6174 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
6176 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
6179 // f32 / f64 must be expanded to i32 / i64.
6180 if (VT == MVT::f32 || VT == MVT::f64) {
6181 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6182 if (getTypeAction(NVT) == Expand)
6183 ExpandOp(Lo, Lo, Hi);
6187 // If source operand will be expanded to the same type as VT, i.e.
6188 // i64 <- f64, i32 <- f32, expand the source operand instead.
6189 MVT VT0 = Node->getOperand(0).getValueType();
6190 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
6191 ExpandOp(Node->getOperand(0), Lo, Hi);
6195 // Turn this into a load/store pair by default.
6196 if (Tmp.getNode() == 0)
6197 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT);
6199 ExpandOp(Tmp, Lo, Hi);
6203 case ISD::READCYCLECOUNTER: {
6204 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
6205 TargetLowering::Custom &&
6206 "Must custom expand ReadCycleCounter");
6207 SDValue Tmp = TLI.LowerOperation(Op, DAG);
6208 assert(Tmp.getNode() && "Node must be custom expanded!");
6209 ExpandOp(Tmp.getValue(0), Lo, Hi);
6210 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6211 LegalizeOp(Tmp.getValue(1)));
6215 // FIXME: should the LOAD_BIN and SWAP atomics get here too? Probably.
6216 case ISD::ATOMIC_CMP_SWAP_8:
6217 case ISD::ATOMIC_CMP_SWAP_16:
6218 case ISD::ATOMIC_CMP_SWAP_32:
6219 case ISD::ATOMIC_CMP_SWAP_64: {
6220 SDValue Tmp = TLI.LowerOperation(Op, DAG);
6221 assert(Tmp.getNode() && "Node must be custom expanded!");
6222 ExpandOp(Tmp.getValue(0), Lo, Hi);
6223 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6224 LegalizeOp(Tmp.getValue(1)));
6230 // These operators cannot be expanded directly, emit them as calls to
6231 // library functions.
6232 case ISD::FP_TO_SINT: {
6233 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
6235 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6236 case Expand: assert(0 && "cannot expand FP!");
6237 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6238 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6241 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
6243 // Now that the custom expander is done, expand the result, which is still
6246 ExpandOp(Op, Lo, Hi);
6251 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Node->getOperand(0).getValueType(),
6253 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected uint-to-fp conversion!");
6254 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6258 case ISD::FP_TO_UINT: {
6259 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
6261 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6262 case Expand: assert(0 && "cannot expand FP!");
6263 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6264 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6267 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
6269 // Now that the custom expander is done, expand the result.
6271 ExpandOp(Op, Lo, Hi);
6276 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Node->getOperand(0).getValueType(),
6278 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
6279 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6284 // If the target wants custom lowering, do so.
6285 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6286 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
6287 SDValue Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
6288 Op = TLI.LowerOperation(Op, DAG);
6290 // Now that the custom expander is done, expand the result, which is
6292 ExpandOp(Op, Lo, Hi);
6297 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
6298 // this X << 1 as X+X.
6299 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
6300 if (ShAmt->getAPIntValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
6301 TLI.isOperationLegal(ISD::ADDE, NVT)) {
6302 SDValue LoOps[2], HiOps[3];
6303 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
6304 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
6305 LoOps[1] = LoOps[0];
6306 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6308 HiOps[1] = HiOps[0];
6309 HiOps[2] = Lo.getValue(1);
6310 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6315 // If we can emit an efficient shift operation, do so now.
6316 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6319 // If this target supports SHL_PARTS, use it.
6320 TargetLowering::LegalizeAction Action =
6321 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
6322 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6323 Action == TargetLowering::Custom) {
6324 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6328 // Otherwise, emit a libcall.
6329 Lo = ExpandLibCall(RTLIB::SHL_I64, Node, false/*left shift=unsigned*/, Hi);
6334 // If the target wants custom lowering, do so.
6335 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6336 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
6337 SDValue Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
6338 Op = TLI.LowerOperation(Op, DAG);
6340 // Now that the custom expander is done, expand the result, which is
6342 ExpandOp(Op, Lo, Hi);
6347 // If we can emit an efficient shift operation, do so now.
6348 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
6351 // If this target supports SRA_PARTS, use it.
6352 TargetLowering::LegalizeAction Action =
6353 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
6354 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6355 Action == TargetLowering::Custom) {
6356 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6360 // Otherwise, emit a libcall.
6361 Lo = ExpandLibCall(RTLIB::SRA_I64, Node, true/*ashr is signed*/, Hi);
6366 // If the target wants custom lowering, do so.
6367 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6368 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
6369 SDValue Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
6370 Op = TLI.LowerOperation(Op, DAG);
6372 // Now that the custom expander is done, expand the result, which is
6374 ExpandOp(Op, Lo, Hi);
6379 // If we can emit an efficient shift operation, do so now.
6380 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6383 // If this target supports SRL_PARTS, use it.
6384 TargetLowering::LegalizeAction Action =
6385 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
6386 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6387 Action == TargetLowering::Custom) {
6388 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6392 // Otherwise, emit a libcall.
6393 Lo = ExpandLibCall(RTLIB::SRL_I64, Node, false/*lshr is unsigned*/, Hi);
6399 // If the target wants to custom expand this, let them.
6400 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
6401 TargetLowering::Custom) {
6402 SDValue Result = TLI.LowerOperation(Op, DAG);
6403 if (Result.getNode()) {
6404 ExpandOp(Result, Lo, Hi);
6409 // Expand the subcomponents.
6410 SDValue LHSL, LHSH, RHSL, RHSH;
6411 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6412 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6413 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6414 SDValue LoOps[2], HiOps[3];
6419 if (Node->getOpcode() == ISD::ADD) {
6420 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6421 HiOps[2] = Lo.getValue(1);
6422 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6424 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6425 HiOps[2] = Lo.getValue(1);
6426 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6433 // Expand the subcomponents.
6434 SDValue LHSL, LHSH, RHSL, RHSH;
6435 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6436 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6437 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6438 SDValue LoOps[2] = { LHSL, RHSL };
6439 SDValue HiOps[3] = { LHSH, RHSH };
6441 if (Node->getOpcode() == ISD::ADDC) {
6442 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6443 HiOps[2] = Lo.getValue(1);
6444 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6446 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6447 HiOps[2] = Lo.getValue(1);
6448 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6450 // Remember that we legalized the flag.
6451 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6456 // Expand the subcomponents.
6457 SDValue LHSL, LHSH, RHSL, RHSH;
6458 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6459 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6460 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6461 SDValue LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
6462 SDValue HiOps[3] = { LHSH, RHSH };
6464 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
6465 HiOps[2] = Lo.getValue(1);
6466 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
6468 // Remember that we legalized the flag.
6469 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6473 // If the target wants to custom expand this, let them.
6474 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
6475 SDValue New = TLI.LowerOperation(Op, DAG);
6476 if (New.getNode()) {
6477 ExpandOp(New, Lo, Hi);
6482 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
6483 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
6484 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
6485 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
6486 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
6487 SDValue LL, LH, RL, RH;
6488 ExpandOp(Node->getOperand(0), LL, LH);
6489 ExpandOp(Node->getOperand(1), RL, RH);
6490 unsigned OuterBitSize = Op.getValueSizeInBits();
6491 unsigned InnerBitSize = RH.getValueSizeInBits();
6492 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
6493 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
6494 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
6495 if (DAG.MaskedValueIsZero(Node->getOperand(0), HighMask) &&
6496 DAG.MaskedValueIsZero(Node->getOperand(1), HighMask)) {
6497 // The inputs are both zero-extended.
6499 // We can emit a umul_lohi.
6500 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6501 Hi = SDValue(Lo.getNode(), 1);
6505 // We can emit a mulhu+mul.
6506 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6507 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6511 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
6512 // The input values are both sign-extended.
6514 // We can emit a smul_lohi.
6515 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6516 Hi = SDValue(Lo.getNode(), 1);
6520 // We can emit a mulhs+mul.
6521 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6522 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
6527 // Lo,Hi = umul LHS, RHS.
6528 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
6529 DAG.getVTList(NVT, NVT), LL, RL);
6531 Hi = UMulLOHI.getValue(1);
6532 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6533 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6534 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6535 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6539 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6540 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6541 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6542 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6543 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6544 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6549 // If nothing else, we can make a libcall.
6550 Lo = ExpandLibCall(RTLIB::MUL_I64, Node, false/*sign irrelevant*/, Hi);
6554 Lo = ExpandLibCall(RTLIB::SDIV_I64, Node, true, Hi);
6557 Lo = ExpandLibCall(RTLIB::UDIV_I64, Node, true, Hi);
6560 Lo = ExpandLibCall(RTLIB::SREM_I64, Node, true, Hi);
6563 Lo = ExpandLibCall(RTLIB::UREM_I64, Node, true, Hi);
6567 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::ADD_F32,
6570 RTLIB::ADD_PPCF128),
6574 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::SUB_F32,
6577 RTLIB::SUB_PPCF128),
6581 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::MUL_F32,
6584 RTLIB::MUL_PPCF128),
6588 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::DIV_F32,
6591 RTLIB::DIV_PPCF128),
6594 case ISD::FP_EXTEND: {
6595 if (VT == MVT::ppcf128) {
6596 assert(Node->getOperand(0).getValueType()==MVT::f32 ||
6597 Node->getOperand(0).getValueType()==MVT::f64);
6598 const uint64_t zero = 0;
6599 if (Node->getOperand(0).getValueType()==MVT::f32)
6600 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0));
6602 Hi = Node->getOperand(0);
6603 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6606 RTLIB::Libcall LC = RTLIB::getFPEXT(Node->getOperand(0).getValueType(), VT);
6607 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!");
6608 Lo = ExpandLibCall(LC, Node, true, Hi);
6611 case ISD::FP_ROUND: {
6612 RTLIB::Libcall LC = RTLIB::getFPROUND(Node->getOperand(0).getValueType(),
6614 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!");
6615 Lo = ExpandLibCall(LC, Node, true, Hi);
6630 case ISD::FNEARBYINT:
6633 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6634 switch(Node->getOpcode()) {
6636 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
6637 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
6640 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
6641 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
6644 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
6645 RTLIB::COS_F80, RTLIB::COS_PPCF128);
6648 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
6649 RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
6652 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
6653 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
6656 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
6657 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
6660 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
6661 RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
6664 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
6665 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
6668 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
6669 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
6672 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
6673 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128);
6676 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
6677 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128);
6680 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64,
6681 RTLIB::RINT_F80, RTLIB::RINT_PPCF128);
6683 case ISD::FNEARBYINT:
6684 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
6685 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
6688 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
6689 RTLIB::POW_PPCF128);
6692 LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64, RTLIB::POWI_F80,
6693 RTLIB::POWI_PPCF128);
6695 default: assert(0 && "Unreachable!");
6697 Lo = ExpandLibCall(LC, Node, false, Hi);
6701 if (VT == MVT::ppcf128) {
6703 ExpandOp(Node->getOperand(0), Lo, Tmp);
6704 Hi = DAG.getNode(ISD::FABS, NVT, Tmp);
6705 // lo = hi==fabs(hi) ? lo : -lo;
6706 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp,
6707 Lo, DAG.getNode(ISD::FNEG, NVT, Lo),
6708 DAG.getCondCode(ISD::SETEQ));
6711 SDValue Mask = (VT == MVT::f64)
6712 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
6713 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
6714 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6715 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6716 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
6717 if (getTypeAction(NVT) == Expand)
6718 ExpandOp(Lo, Lo, Hi);
6722 if (VT == MVT::ppcf128) {
6723 ExpandOp(Node->getOperand(0), Lo, Hi);
6724 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo);
6725 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi);
6728 SDValue Mask = (VT == MVT::f64)
6729 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
6730 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
6731 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6732 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6733 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
6734 if (getTypeAction(NVT) == Expand)
6735 ExpandOp(Lo, Lo, Hi);
6738 case ISD::FCOPYSIGN: {
6739 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
6740 if (getTypeAction(NVT) == Expand)
6741 ExpandOp(Lo, Lo, Hi);
6744 case ISD::SINT_TO_FP:
6745 case ISD::UINT_TO_FP: {
6746 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
6747 MVT SrcVT = Node->getOperand(0).getValueType();
6749 // Promote the operand if needed. Do this before checking for
6750 // ppcf128 so conversions of i16 and i8 work.
6751 if (getTypeAction(SrcVT) == Promote) {
6752 SDValue Tmp = PromoteOp(Node->getOperand(0));
6754 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
6755 DAG.getValueType(SrcVT))
6756 : DAG.getZeroExtendInReg(Tmp, SrcVT);
6757 Node = DAG.UpdateNodeOperands(Op, Tmp).getNode();
6758 SrcVT = Node->getOperand(0).getValueType();
6761 if (VT == MVT::ppcf128 && SrcVT == MVT::i32) {
6762 static const uint64_t zero = 0;
6764 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6765 Node->getOperand(0)));
6766 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6768 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
6769 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6770 Node->getOperand(0)));
6771 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6772 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6773 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
6774 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6775 DAG.getConstant(0, MVT::i32),
6776 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6778 APFloat(APInt(128, 2, TwoE32)),
6781 DAG.getCondCode(ISD::SETLT)),
6786 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) {
6787 // si64->ppcf128 done by libcall, below
6788 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
6789 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)),
6791 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6792 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
6793 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6794 DAG.getConstant(0, MVT::i64),
6795 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6797 APFloat(APInt(128, 2, TwoE64)),
6800 DAG.getCondCode(ISD::SETLT)),
6805 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
6806 Node->getOperand(0));
6807 if (getTypeAction(Lo.getValueType()) == Expand)
6808 // float to i32 etc. can be 'expanded' to a single node.
6809 ExpandOp(Lo, Lo, Hi);
6814 // Make sure the resultant values have been legalized themselves, unless this
6815 // is a type that requires multi-step expansion.
6816 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
6817 Lo = LegalizeOp(Lo);
6819 // Don't legalize the high part if it is expanded to a single node.
6820 Hi = LegalizeOp(Hi);
6823 // Remember in a map if the values will be reused later.
6825 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
6826 assert(isNew && "Value already expanded?!?");
6829 /// SplitVectorOp - Given an operand of vector type, break it down into
6830 /// two smaller values, still of vector type.
6831 void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
6833 assert(Op.getValueType().isVector() && "Cannot split non-vector type!");
6834 SDNode *Node = Op.getNode();
6835 unsigned NumElements = Op.getValueType().getVectorNumElements();
6836 assert(NumElements > 1 && "Cannot split a single element vector!");
6838 MVT NewEltVT = Op.getValueType().getVectorElementType();
6840 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
6841 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
6843 MVT NewVT_Lo = MVT::getVectorVT(NewEltVT, NewNumElts_Lo);
6844 MVT NewVT_Hi = MVT::getVectorVT(NewEltVT, NewNumElts_Hi);
6846 // See if we already split it.
6847 std::map<SDValue, std::pair<SDValue, SDValue> >::iterator I
6848 = SplitNodes.find(Op);
6849 if (I != SplitNodes.end()) {
6850 Lo = I->second.first;
6851 Hi = I->second.second;
6855 switch (Node->getOpcode()) {
6860 assert(0 && "Unhandled operation in SplitVectorOp!");
6862 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo);
6863 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi);
6865 case ISD::BUILD_PAIR:
6866 Lo = Node->getOperand(0);
6867 Hi = Node->getOperand(1);
6869 case ISD::INSERT_VECTOR_ELT: {
6870 if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) {
6871 SplitVectorOp(Node->getOperand(0), Lo, Hi);
6872 unsigned Index = Idx->getZExtValue();
6873 SDValue ScalarOp = Node->getOperand(1);
6874 if (Index < NewNumElts_Lo)
6875 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp,
6876 DAG.getIntPtrConstant(Index));
6878 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp,
6879 DAG.getIntPtrConstant(Index - NewNumElts_Lo));
6882 SDValue Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0),
6883 Node->getOperand(1),
6884 Node->getOperand(2));
6885 SplitVectorOp(Tmp, Lo, Hi);
6888 case ISD::VECTOR_SHUFFLE: {
6889 // Build the low part.
6890 SDValue Mask = Node->getOperand(2);
6891 SmallVector<SDValue, 8> Ops;
6892 MVT PtrVT = TLI.getPointerTy();
6894 // Insert all of the elements from the input that are needed. We use
6895 // buildvector of extractelement here because the input vectors will have
6896 // to be legalized, so this makes the code simpler.
6897 for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
6898 SDValue IdxNode = Mask.getOperand(i);
6899 if (IdxNode.getOpcode() == ISD::UNDEF) {
6900 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
6903 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
6904 SDValue InVec = Node->getOperand(0);
6905 if (Idx >= NumElements) {
6906 InVec = Node->getOperand(1);
6909 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6910 DAG.getConstant(Idx, PtrVT)));
6912 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6915 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
6916 SDValue IdxNode = Mask.getOperand(i);
6917 if (IdxNode.getOpcode() == ISD::UNDEF) {
6918 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
6921 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
6922 SDValue InVec = Node->getOperand(0);
6923 if (Idx >= NumElements) {
6924 InVec = Node->getOperand(1);
6927 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6928 DAG.getConstant(Idx, PtrVT)));
6930 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &Ops[0], Ops.size());
6933 case ISD::BUILD_VECTOR: {
6934 SmallVector<SDValue, 8> LoOps(Node->op_begin(),
6935 Node->op_begin()+NewNumElts_Lo);
6936 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size());
6938 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
6940 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size());
6943 case ISD::CONCAT_VECTORS: {
6944 // FIXME: Handle non-power-of-two vectors?
6945 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
6946 if (NewNumSubvectors == 1) {
6947 Lo = Node->getOperand(0);
6948 Hi = Node->getOperand(1);
6950 SmallVector<SDValue, 8> LoOps(Node->op_begin(),
6951 Node->op_begin()+NewNumSubvectors);
6952 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size());
6954 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumSubvectors,
6956 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size());
6961 SDValue Cond = Node->getOperand(0);
6963 SDValue LL, LH, RL, RH;
6964 SplitVectorOp(Node->getOperand(1), LL, LH);
6965 SplitVectorOp(Node->getOperand(2), RL, RH);
6967 if (Cond.getValueType().isVector()) {
6968 // Handle a vector merge.
6970 SplitVectorOp(Cond, CL, CH);
6971 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL);
6972 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH);
6974 // Handle a simple select with vector operands.
6975 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL);
6976 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH);
6980 case ISD::SELECT_CC: {
6981 SDValue CondLHS = Node->getOperand(0);
6982 SDValue CondRHS = Node->getOperand(1);
6983 SDValue CondCode = Node->getOperand(4);
6985 SDValue LL, LH, RL, RH;
6986 SplitVectorOp(Node->getOperand(2), LL, LH);
6987 SplitVectorOp(Node->getOperand(3), RL, RH);
6989 // Handle a simple select with vector operands.
6990 Lo = DAG.getNode(ISD::SELECT_CC, NewVT_Lo, CondLHS, CondRHS,
6992 Hi = DAG.getNode(ISD::SELECT_CC, NewVT_Hi, CondLHS, CondRHS,
6997 SDValue LL, LH, RL, RH;
6998 SplitVectorOp(Node->getOperand(0), LL, LH);
6999 SplitVectorOp(Node->getOperand(1), RL, RH);
7000 Lo = DAG.getNode(ISD::VSETCC, NewVT_Lo, LL, RL, Node->getOperand(2));
7001 Hi = DAG.getNode(ISD::VSETCC, NewVT_Hi, LH, RH, Node->getOperand(2));
7020 SDValue LL, LH, RL, RH;
7021 SplitVectorOp(Node->getOperand(0), LL, LH);
7022 SplitVectorOp(Node->getOperand(1), RL, RH);
7024 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL);
7025 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH);
7031 SplitVectorOp(Node->getOperand(0), L, H);
7033 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1));
7034 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1));
7050 case ISD::FP_TO_SINT:
7051 case ISD::FP_TO_UINT:
7052 case ISD::SINT_TO_FP:
7053 case ISD::UINT_TO_FP:
7055 case ISD::ANY_EXTEND:
7056 case ISD::SIGN_EXTEND:
7057 case ISD::ZERO_EXTEND:
7058 case ISD::FP_EXTEND: {
7060 SplitVectorOp(Node->getOperand(0), L, H);
7062 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L);
7063 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H);
7067 LoadSDNode *LD = cast<LoadSDNode>(Node);
7068 SDValue Ch = LD->getChain();
7069 SDValue Ptr = LD->getBasePtr();
7070 ISD::LoadExtType ExtType = LD->getExtensionType();
7071 const Value *SV = LD->getSrcValue();
7072 int SVOffset = LD->getSrcValueOffset();
7073 MVT MemoryVT = LD->getMemoryVT();
7074 unsigned Alignment = LD->getAlignment();
7075 bool isVolatile = LD->isVolatile();
7077 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
7078 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType());
7080 MVT MemNewEltVT = MemoryVT.getVectorElementType();
7081 MVT MemNewVT_Lo = MVT::getVectorVT(MemNewEltVT, NewNumElts_Lo);
7082 MVT MemNewVT_Hi = MVT::getVectorVT(MemNewEltVT, NewNumElts_Hi);
7084 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType,
7085 NewVT_Lo, Ch, Ptr, Offset,
7086 SV, SVOffset, MemNewVT_Lo, isVolatile, Alignment);
7087 unsigned IncrementSize = NewNumElts_Lo * MemNewEltVT.getSizeInBits()/8;
7088 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
7089 DAG.getIntPtrConstant(IncrementSize));
7090 SVOffset += IncrementSize;
7091 Alignment = MinAlign(Alignment, IncrementSize);
7092 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType,
7093 NewVT_Hi, Ch, Ptr, Offset,
7094 SV, SVOffset, MemNewVT_Hi, isVolatile, Alignment);
7096 // Build a factor node to remember that this load is independent of the
7098 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
7101 // Remember that we legalized the chain.
7102 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
7105 case ISD::BIT_CONVERT: {
7106 // We know the result is a vector. The input may be either a vector or a
7108 SDValue InOp = Node->getOperand(0);
7109 if (!InOp.getValueType().isVector() ||
7110 InOp.getValueType().getVectorNumElements() == 1) {
7111 // The input is a scalar or single-element vector.
7112 // Lower to a store/load so that it can be split.
7113 // FIXME: this could be improved probably.
7114 unsigned LdAlign = TLI.getTargetData()->getPrefTypeAlignment(
7115 Op.getValueType().getTypeForMVT());
7116 SDValue Ptr = DAG.CreateStackTemporary(InOp.getValueType(), LdAlign);
7117 int FI = cast<FrameIndexSDNode>(Ptr.getNode())->getIndex();
7119 SDValue St = DAG.getStore(DAG.getEntryNode(),
7121 PseudoSourceValue::getFixedStack(FI), 0);
7122 InOp = DAG.getLoad(Op.getValueType(), St, Ptr,
7123 PseudoSourceValue::getFixedStack(FI), 0);
7125 // Split the vector and convert each of the pieces now.
7126 SplitVectorOp(InOp, Lo, Hi);
7127 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo);
7128 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi);
7133 // Remember in a map if the values will be reused later.
7135 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
7136 assert(isNew && "Value already split?!?");
7140 /// ScalarizeVectorOp - Given an operand of single-element vector type
7141 /// (e.g. v1f32), convert it into the equivalent operation that returns a
7142 /// scalar (e.g. f32) value.
7143 SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) {
7144 assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!");
7145 SDNode *Node = Op.getNode();
7146 MVT NewVT = Op.getValueType().getVectorElementType();
7147 assert(Op.getValueType().getVectorNumElements() == 1);
7149 // See if we already scalarized it.
7150 std::map<SDValue, SDValue>::iterator I = ScalarizedNodes.find(Op);
7151 if (I != ScalarizedNodes.end()) return I->second;
7154 switch (Node->getOpcode()) {
7157 Node->dump(&DAG); cerr << "\n";
7159 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
7176 Result = DAG.getNode(Node->getOpcode(),
7178 ScalarizeVectorOp(Node->getOperand(0)),
7179 ScalarizeVectorOp(Node->getOperand(1)));
7191 case ISD::FP_TO_SINT:
7192 case ISD::FP_TO_UINT:
7193 case ISD::SINT_TO_FP:
7194 case ISD::UINT_TO_FP:
7195 case ISD::SIGN_EXTEND:
7196 case ISD::ZERO_EXTEND:
7197 case ISD::ANY_EXTEND:
7199 case ISD::FP_EXTEND:
7200 Result = DAG.getNode(Node->getOpcode(),
7202 ScalarizeVectorOp(Node->getOperand(0)));
7206 Result = DAG.getNode(Node->getOpcode(),
7208 ScalarizeVectorOp(Node->getOperand(0)),
7209 Node->getOperand(1));
7212 LoadSDNode *LD = cast<LoadSDNode>(Node);
7213 SDValue Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
7214 SDValue Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
7215 ISD::LoadExtType ExtType = LD->getExtensionType();
7216 const Value *SV = LD->getSrcValue();
7217 int SVOffset = LD->getSrcValueOffset();
7218 MVT MemoryVT = LD->getMemoryVT();
7219 unsigned Alignment = LD->getAlignment();
7220 bool isVolatile = LD->isVolatile();
7222 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
7223 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType());
7225 Result = DAG.getLoad(ISD::UNINDEXED, ExtType,
7226 NewVT, Ch, Ptr, Offset, SV, SVOffset,
7227 MemoryVT.getVectorElementType(),
7228 isVolatile, Alignment);
7230 // Remember that we legalized the chain.
7231 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
7234 case ISD::BUILD_VECTOR:
7235 Result = Node->getOperand(0);
7237 case ISD::INSERT_VECTOR_ELT:
7238 // Returning the inserted scalar element.
7239 Result = Node->getOperand(1);
7241 case ISD::CONCAT_VECTORS:
7242 assert(Node->getOperand(0).getValueType() == NewVT &&
7243 "Concat of non-legal vectors not yet supported!");
7244 Result = Node->getOperand(0);
7246 case ISD::VECTOR_SHUFFLE: {
7247 // Figure out if the scalar is the LHS or RHS and return it.
7248 SDValue EltNum = Node->getOperand(2).getOperand(0);
7249 if (cast<ConstantSDNode>(EltNum)->getZExtValue())
7250 Result = ScalarizeVectorOp(Node->getOperand(1));
7252 Result = ScalarizeVectorOp(Node->getOperand(0));
7255 case ISD::EXTRACT_SUBVECTOR:
7256 Result = Node->getOperand(0);
7257 assert(Result.getValueType() == NewVT);
7259 case ISD::BIT_CONVERT: {
7260 SDValue Op0 = Op.getOperand(0);
7261 if (Op0.getValueType().getVectorNumElements() == 1)
7262 Op0 = ScalarizeVectorOp(Op0);
7263 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op0);
7267 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
7268 ScalarizeVectorOp(Op.getOperand(1)),
7269 ScalarizeVectorOp(Op.getOperand(2)));
7271 case ISD::SELECT_CC:
7272 Result = DAG.getNode(ISD::SELECT_CC, NewVT, Node->getOperand(0),
7273 Node->getOperand(1),
7274 ScalarizeVectorOp(Op.getOperand(2)),
7275 ScalarizeVectorOp(Op.getOperand(3)),
7276 Node->getOperand(4));
7279 SDValue Op0 = ScalarizeVectorOp(Op.getOperand(0));
7280 SDValue Op1 = ScalarizeVectorOp(Op.getOperand(1));
7281 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Op0), Op0, Op1,
7283 Result = DAG.getNode(ISD::SELECT, NewVT, Result,
7284 DAG.getConstant(-1ULL, NewVT),
7285 DAG.getConstant(0ULL, NewVT));
7290 if (TLI.isTypeLegal(NewVT))
7291 Result = LegalizeOp(Result);
7292 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
7293 assert(isNew && "Value already scalarized?");
7298 // SelectionDAG::Legalize - This is the entry point for the file.
7300 void SelectionDAG::Legalize() {
7301 /// run - This is the main entry point to this class.
7303 SelectionDAGLegalize(*this).LegalizeDAG();