1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/CodeGen/DwarfWriter.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/CodeGen/PseudoSourceValue.h"
22 #include "llvm/Target/TargetFrameInfo.h"
23 #include "llvm/Target/TargetLowering.h"
24 #include "llvm/Target/TargetData.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Target/TargetSubtarget.h"
28 #include "llvm/CallingConv.h"
29 #include "llvm/Constants.h"
30 #include "llvm/DerivedTypes.h"
31 #include "llvm/Function.h"
32 #include "llvm/GlobalVariable.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Compiler.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/ADT/DenseMap.h"
37 #include "llvm/ADT/SmallVector.h"
38 #include "llvm/ADT/SmallPtrSet.h"
42 //===----------------------------------------------------------------------===//
43 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
44 /// hacks on it until the target machine can handle it. This involves
45 /// eliminating value sizes the machine cannot handle (promoting small sizes to
46 /// large sizes or splitting up large values into small values) as well as
47 /// eliminating operations the machine cannot handle.
49 /// This code also does a small amount of optimization and recognition of idioms
50 /// as part of its processing. For example, if a target does not support a
51 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
52 /// will attempt merge setcc and brc instructions into brcc's.
55 class VISIBILITY_HIDDEN SelectionDAGLegalize {
58 bool TypesNeedLegalizing;
60 // Libcall insertion helpers.
62 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
63 /// legalized. We use this to ensure that calls are properly serialized
64 /// against each other, including inserted libcalls.
65 SDValue LastCALLSEQ_END;
67 /// IsLegalizingCall - This member is used *only* for purposes of providing
68 /// helpful assertions that a libcall isn't created while another call is
69 /// being legalized (which could lead to non-serialized call sequences).
70 bool IsLegalizingCall;
72 /// IsLegalizingCallArguments - This member is used only for the purpose
73 /// of providing assert to check for LegalizeTypes because legalizing an
74 /// operation might introduce call nodes that might need type legalization.
75 bool IsLegalizingCallArgs;
78 Legal, // The target natively supports this operation.
79 Promote, // This operation should be executed in a larger type.
80 Expand // Try to expand this to other ops, otherwise use a libcall.
83 /// ValueTypeActions - This is a bitvector that contains two bits for each
84 /// value type, where the two bits correspond to the LegalizeAction enum.
85 /// This can be queried with "getTypeAction(VT)".
86 TargetLowering::ValueTypeActionImpl ValueTypeActions;
88 /// LegalizedNodes - For nodes that are of legal width, and that have more
89 /// than one use, this map indicates what regularized operand to use. This
90 /// allows us to avoid legalizing the same thing more than once.
91 DenseMap<SDValue, SDValue> LegalizedNodes;
93 /// PromotedNodes - For nodes that are below legal width, and that have more
94 /// than one use, this map indicates what promoted value to use. This allows
95 /// us to avoid promoting the same thing more than once.
96 DenseMap<SDValue, SDValue> PromotedNodes;
98 /// ExpandedNodes - For nodes that need to be expanded this map indicates
99 /// which operands are the expanded version of the input. This allows
100 /// us to avoid expanding the same node more than once.
101 DenseMap<SDValue, std::pair<SDValue, SDValue> > ExpandedNodes;
103 /// SplitNodes - For vector nodes that need to be split, this map indicates
104 /// which operands are the split version of the input. This allows us
105 /// to avoid splitting the same node more than once.
106 std::map<SDValue, std::pair<SDValue, SDValue> > SplitNodes;
108 /// ScalarizedNodes - For nodes that need to be converted from vector types to
109 /// scalar types, this contains the mapping of ones we have already
110 /// processed to the result.
111 std::map<SDValue, SDValue> ScalarizedNodes;
113 /// WidenNodes - For nodes that need to be widened from one vector type to
114 /// another, this contains the mapping of those that we have already widen.
115 /// This allows us to avoid widening more than once.
116 std::map<SDValue, SDValue> WidenNodes;
118 void AddLegalizedOperand(SDValue From, SDValue To) {
119 LegalizedNodes.insert(std::make_pair(From, To));
120 // If someone requests legalization of the new node, return itself.
122 LegalizedNodes.insert(std::make_pair(To, To));
124 void AddPromotedOperand(SDValue From, SDValue To) {
125 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
126 assert(isNew && "Got into the map somehow?");
128 // If someone requests legalization of the new node, return itself.
129 LegalizedNodes.insert(std::make_pair(To, To));
131 void AddWidenedOperand(SDValue From, SDValue To) {
132 bool isNew = WidenNodes.insert(std::make_pair(From, To)).second;
133 assert(isNew && "Got into the map somehow?");
135 // If someone requests legalization of the new node, return itself.
136 LegalizedNodes.insert(std::make_pair(To, To));
140 explicit SelectionDAGLegalize(SelectionDAG &DAG, bool TypesNeedLegalizing);
142 /// getTypeAction - Return how we should legalize values of this type, either
143 /// it is already legal or we need to expand it into multiple registers of
144 /// smaller integer type, or we need to promote it to a larger type.
145 LegalizeAction getTypeAction(MVT VT) const {
146 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
149 /// isTypeLegal - Return true if this type is legal on this target.
151 bool isTypeLegal(MVT VT) const {
152 return getTypeAction(VT) == Legal;
158 /// HandleOp - Legalize, Promote, or Expand the specified operand as
159 /// appropriate for its type.
160 void HandleOp(SDValue Op);
162 /// LegalizeOp - We know that the specified value has a legal type.
163 /// Recursively ensure that the operands have legal types, then return the
165 SDValue LegalizeOp(SDValue O);
167 /// UnrollVectorOp - We know that the given vector has a legal type, however
168 /// the operation it performs is not legal and is an operation that we have
169 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
170 /// operating on each element individually.
171 SDValue UnrollVectorOp(SDValue O);
173 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
174 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
175 /// is necessary to spill the vector being inserted into to memory, perform
176 /// the insert there, and then read the result back.
177 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
178 SDValue Idx, DebugLoc dl);
180 /// PromoteOp - Given an operation that produces a value in an invalid type,
181 /// promote it to compute the value into a larger type. The produced value
182 /// will have the correct bits for the low portion of the register, but no
183 /// guarantee is made about the top bits: it may be zero, sign-extended, or
185 SDValue PromoteOp(SDValue O);
187 /// ExpandOp - Expand the specified SDValue into its two component pieces
188 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
189 /// the LegalizedNodes map is filled in for any results that are not expanded,
190 /// the ExpandedNodes map is filled in for any results that are expanded, and
191 /// the Lo/Hi values are returned. This applies to integer types and Vector
193 void ExpandOp(SDValue O, SDValue &Lo, SDValue &Hi);
195 /// WidenVectorOp - Widen a vector operation to a wider type given by WidenVT
196 /// (e.g., v3i32 to v4i32). The produced value will have the correct value
197 /// for the existing elements but no guarantee is made about the new elements
198 /// at the end of the vector: it may be zero, ones, or garbage. This is useful
199 /// when we have an instruction operating on an illegal vector type and we
200 /// want to widen it to do the computation on a legal wider vector type.
201 SDValue WidenVectorOp(SDValue Op, MVT WidenVT);
203 /// SplitVectorOp - Given an operand of vector type, break it down into
204 /// two smaller values.
205 void SplitVectorOp(SDValue O, SDValue &Lo, SDValue &Hi);
207 /// ScalarizeVectorOp - Given an operand of single-element vector type
208 /// (e.g. v1f32), convert it into the equivalent operation that returns a
209 /// scalar (e.g. f32) value.
210 SDValue ScalarizeVectorOp(SDValue O);
212 /// Useful 16 element vector type that is used to pass operands for widening.
213 typedef SmallVector<SDValue, 16> SDValueVector;
215 /// LoadWidenVectorOp - Load a vector for a wider type. Returns true if
216 /// the LdChain contains a single load and false if it contains a token
217 /// factor for multiple loads. It takes
218 /// Result: location to return the result
219 /// LdChain: location to return the load chain
220 /// Op: load operation to widen
221 /// NVT: widen vector result type we want for the load
222 bool LoadWidenVectorOp(SDValue& Result, SDValue& LdChain,
223 SDValue Op, MVT NVT);
225 /// Helper genWidenVectorLoads - Helper function to generate a set of
226 /// loads to load a vector with a resulting wider type. It takes
227 /// LdChain: list of chains for the load we have generated
228 /// Chain: incoming chain for the ld vector
229 /// BasePtr: base pointer to load from
230 /// SV: memory disambiguation source value
231 /// SVOffset: memory disambiugation offset
232 /// Alignment: alignment of the memory
233 /// isVolatile: volatile load
234 /// LdWidth: width of memory that we want to load
235 /// ResType: the wider result result type for the resulting loaded vector
236 SDValue genWidenVectorLoads(SDValueVector& LdChain, SDValue Chain,
237 SDValue BasePtr, const Value *SV,
238 int SVOffset, unsigned Alignment,
239 bool isVolatile, unsigned LdWidth,
240 MVT ResType, DebugLoc dl);
242 /// StoreWidenVectorOp - Stores a widen vector into non widen memory
243 /// location. It takes
244 /// ST: store node that we want to replace
245 /// Chain: incoming store chain
246 /// BasePtr: base address of where we want to store into
247 SDValue StoreWidenVectorOp(StoreSDNode *ST, SDValue Chain,
250 /// Helper genWidenVectorStores - Helper function to generate a set of
251 /// stores to store a widen vector into non widen memory
253 // StChain: list of chains for the stores we have generated
254 // Chain: incoming chain for the ld vector
255 // BasePtr: base pointer to load from
256 // SV: memory disambiguation source value
257 // SVOffset: memory disambiugation offset
258 // Alignment: alignment of the memory
259 // isVolatile: volatile lod
260 // ValOp: value to store
261 // StWidth: width of memory that we want to store
262 void genWidenVectorStores(SDValueVector& StChain, SDValue Chain,
263 SDValue BasePtr, const Value *SV,
264 int SVOffset, unsigned Alignment,
265 bool isVolatile, SDValue ValOp,
266 unsigned StWidth, DebugLoc dl);
268 /// isShuffleLegal - Return non-null if a vector shuffle is legal with the
269 /// specified mask and type. Targets can specify exactly which masks they
270 /// support and the code generator is tasked with not creating illegal masks.
272 /// Note that this will also return true for shuffles that are promoted to a
275 /// If this is a legal shuffle, this method returns the (possibly promoted)
276 /// build_vector Mask. If it's not a legal shuffle, it returns null.
277 SDNode *isShuffleLegal(MVT VT, SDValue Mask) const;
279 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
280 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
282 void LegalizeSetCCOperands(SDValue &LHS, SDValue &RHS, SDValue &CC,
284 void LegalizeSetCCCondCode(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
286 void LegalizeSetCC(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
288 LegalizeSetCCOperands(LHS, RHS, CC, dl);
289 LegalizeSetCCCondCode(VT, LHS, RHS, CC, dl);
292 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned,
294 SDValue ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source, DebugLoc dl);
296 SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT, DebugLoc dl);
297 SDValue ExpandBUILD_VECTOR(SDNode *Node);
298 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
299 SDValue LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy,
300 SDValue Op, DebugLoc dl);
301 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT,
303 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, bool isSigned,
305 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned,
308 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl);
309 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl);
310 bool ExpandShift(unsigned Opc, SDValue Op, SDValue Amt,
311 SDValue &Lo, SDValue &Hi, DebugLoc dl);
312 void ExpandShiftParts(unsigned NodeOp, SDValue Op, SDValue Amt,
313 SDValue &Lo, SDValue &Hi, DebugLoc dl);
315 SDValue ExpandEXTRACT_SUBVECTOR(SDValue Op);
316 SDValue ExpandEXTRACT_VECTOR_ELT(SDValue Op);
320 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
321 /// specified mask and type. Targets can specify exactly which masks they
322 /// support and the code generator is tasked with not creating illegal masks.
324 /// Note that this will also return true for shuffles that are promoted to a
326 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDValue Mask) const {
327 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
329 case TargetLowering::Legal:
330 case TargetLowering::Custom:
332 case TargetLowering::Promote: {
333 // If this is promoted to a different type, convert the shuffle mask and
334 // ask if it is legal in the promoted type!
335 MVT NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
336 MVT EltVT = NVT.getVectorElementType();
338 // If we changed # elements, change the shuffle mask.
339 unsigned NumEltsGrowth =
340 NVT.getVectorNumElements() / VT.getVectorNumElements();
341 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
342 if (NumEltsGrowth > 1) {
343 // Renumber the elements.
344 SmallVector<SDValue, 8> Ops;
345 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
346 SDValue InOp = Mask.getOperand(i);
347 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
348 if (InOp.getOpcode() == ISD::UNDEF)
349 Ops.push_back(DAG.getUNDEF(EltVT));
351 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getZExtValue();
352 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, EltVT));
356 Mask = DAG.getBUILD_VECTOR(NVT, Mask.getDebugLoc(), &Ops[0], Ops.size());
362 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.getNode() : 0;
365 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag, bool types)
366 : TLI(dag.getTargetLoweringInfo()), DAG(dag), TypesNeedLegalizing(types),
367 ValueTypeActions(TLI.getValueTypeActions()) {
368 assert(MVT::LAST_VALUETYPE <= 32 &&
369 "Too many value types for ValueTypeActions to hold!");
372 void SelectionDAGLegalize::LegalizeDAG() {
373 LastCALLSEQ_END = DAG.getEntryNode();
374 IsLegalizingCall = false;
375 IsLegalizingCallArgs = false;
377 // The legalize process is inherently a bottom-up recursive process (users
378 // legalize their uses before themselves). Given infinite stack space, we
379 // could just start legalizing on the root and traverse the whole graph. In
380 // practice however, this causes us to run out of stack space on large basic
381 // blocks. To avoid this problem, compute an ordering of the nodes where each
382 // node is only legalized after all of its operands are legalized.
383 DAG.AssignTopologicalOrder();
384 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
385 E = prior(DAG.allnodes_end()); I != next(E); ++I)
386 HandleOp(SDValue(I, 0));
388 // Finally, it's possible the root changed. Get the new root.
389 SDValue OldRoot = DAG.getRoot();
390 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
391 DAG.setRoot(LegalizedNodes[OldRoot]);
393 ExpandedNodes.clear();
394 LegalizedNodes.clear();
395 PromotedNodes.clear();
397 ScalarizedNodes.clear();
400 // Remove dead nodes now.
401 DAG.RemoveDeadNodes();
405 /// FindCallEndFromCallStart - Given a chained node that is part of a call
406 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
407 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
408 if (Node->getOpcode() == ISD::CALLSEQ_END)
410 if (Node->use_empty())
411 return 0; // No CallSeqEnd
413 // The chain is usually at the end.
414 SDValue TheChain(Node, Node->getNumValues()-1);
415 if (TheChain.getValueType() != MVT::Other) {
416 // Sometimes it's at the beginning.
417 TheChain = SDValue(Node, 0);
418 if (TheChain.getValueType() != MVT::Other) {
419 // Otherwise, hunt for it.
420 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
421 if (Node->getValueType(i) == MVT::Other) {
422 TheChain = SDValue(Node, i);
426 // Otherwise, we walked into a node without a chain.
427 if (TheChain.getValueType() != MVT::Other)
432 for (SDNode::use_iterator UI = Node->use_begin(),
433 E = Node->use_end(); UI != E; ++UI) {
435 // Make sure to only follow users of our token chain.
437 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
438 if (User->getOperand(i) == TheChain)
439 if (SDNode *Result = FindCallEndFromCallStart(User))
445 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
446 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
447 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
448 assert(Node && "Didn't find callseq_start for a call??");
449 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
451 assert(Node->getOperand(0).getValueType() == MVT::Other &&
452 "Node doesn't have a token chain argument!");
453 return FindCallStartFromCallEnd(Node->getOperand(0).getNode());
456 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
457 /// see if any uses can reach Dest. If no dest operands can get to dest,
458 /// legalize them, legalize ourself, and return false, otherwise, return true.
460 /// Keep track of the nodes we fine that actually do lead to Dest in
461 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
463 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
464 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
465 if (N == Dest) return true; // N certainly leads to Dest :)
467 // If we've already processed this node and it does lead to Dest, there is no
468 // need to reprocess it.
469 if (NodesLeadingTo.count(N)) return true;
471 // If the first result of this node has been already legalized, then it cannot
473 switch (getTypeAction(N->getValueType(0))) {
475 if (LegalizedNodes.count(SDValue(N, 0))) return false;
478 if (PromotedNodes.count(SDValue(N, 0))) return false;
481 if (ExpandedNodes.count(SDValue(N, 0))) return false;
485 // Okay, this node has not already been legalized. Check and legalize all
486 // operands. If none lead to Dest, then we can legalize this node.
487 bool OperandsLeadToDest = false;
488 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
489 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
490 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo);
492 if (OperandsLeadToDest) {
493 NodesLeadingTo.insert(N);
497 // Okay, this node looks safe, legalize it and return false.
498 HandleOp(SDValue(N, 0));
502 /// HandleOp - Legalize, Promote, Widen, or Expand the specified operand as
503 /// appropriate for its type.
504 void SelectionDAGLegalize::HandleOp(SDValue Op) {
505 MVT VT = Op.getValueType();
506 // If the type legalizer was run then we should never see any illegal result
507 // types here except for target constants (the type legalizer does not touch
508 // those) or for build vector used as a mask for a vector shuffle.
509 // FIXME: We can removed the BUILD_VECTOR case when we fix PR2957.
510 assert((TypesNeedLegalizing || getTypeAction(VT) == Legal ||
511 IsLegalizingCallArgs || Op.getOpcode() == ISD::TargetConstant ||
512 Op.getOpcode() == ISD::BUILD_VECTOR) &&
513 "Illegal type introduced after type legalization?");
514 switch (getTypeAction(VT)) {
515 default: assert(0 && "Bad type action!");
516 case Legal: (void)LegalizeOp(Op); break;
518 if (!VT.isVector()) {
523 // See if we can widen otherwise use Expand to either scalarize or split
524 MVT WidenVT = TLI.getWidenVectorType(VT);
525 if (WidenVT != MVT::Other) {
526 (void) WidenVectorOp(Op, WidenVT);
529 // else fall thru to expand since we can't widen the vector
532 if (!VT.isVector()) {
533 // If this is an illegal scalar, expand it into its two component
536 if (Op.getOpcode() == ISD::TargetConstant)
537 break; // Allow illegal target nodes.
539 } else if (VT.getVectorNumElements() == 1) {
540 // If this is an illegal single element vector, convert it to a
542 (void)ScalarizeVectorOp(Op);
544 // This is an illegal multiple element vector.
545 // Split it in half and legalize both parts.
547 SplitVectorOp(Op, X, Y);
553 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
554 /// a load from the constant pool.
555 static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
556 SelectionDAG &DAG, const TargetLowering &TLI) {
558 DebugLoc dl = CFP->getDebugLoc();
560 // If a FP immediate is precise when represented as a float and if the
561 // target can do an extending load from float to double, we put it into
562 // the constant pool as a float, even if it's is statically typed as a
563 // double. This shrinks FP constants and canonicalizes them for targets where
564 // an FP extending load is the same cost as a normal load (such as on the x87
565 // fp stack or PPC FP unit).
566 MVT VT = CFP->getValueType(0);
567 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
569 if (VT!=MVT::f64 && VT!=MVT::f32)
570 assert(0 && "Invalid type expansion");
571 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
572 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
577 while (SVT != MVT::f32) {
578 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1);
579 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
580 // Only do this if the target has a native EXTLOAD instruction from
582 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
583 TLI.ShouldShrinkFPConstant(OrigVT)) {
584 const Type *SType = SVT.getTypeForMVT();
585 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
591 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
592 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
594 return DAG.getExtLoad(ISD::EXTLOAD, dl,
595 OrigVT, DAG.getEntryNode(),
596 CPIdx, PseudoSourceValue::getConstantPool(),
597 0, VT, false, Alignment);
598 return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
599 PseudoSourceValue::getConstantPool(), 0, false, Alignment);
603 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
606 SDValue ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT,
608 const TargetLowering &TLI) {
609 DebugLoc dl = Node->getDebugLoc();
610 MVT VT = Node->getValueType(0);
611 MVT SrcVT = Node->getOperand(1).getValueType();
612 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
613 "fcopysign expansion only supported for f32 and f64");
614 MVT SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
616 // First get the sign bit of second operand.
617 SDValue Mask1 = (SrcVT == MVT::f64)
618 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
619 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
620 Mask1 = DAG.getNode(ISD::BIT_CONVERT, dl, SrcNVT, Mask1);
621 SDValue SignBit= DAG.getNode(ISD::BIT_CONVERT, dl, SrcNVT,
622 Node->getOperand(1));
623 SignBit = DAG.getNode(ISD::AND, dl, SrcNVT, SignBit, Mask1);
624 // Shift right or sign-extend it if the two operands have different types.
625 int SizeDiff = SrcNVT.getSizeInBits() - NVT.getSizeInBits();
627 SignBit = DAG.getNode(ISD::SRL, dl, SrcNVT, SignBit,
628 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
629 SignBit = DAG.getNode(ISD::TRUNCATE, dl, NVT, SignBit);
630 } else if (SizeDiff < 0) {
631 SignBit = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, SignBit);
632 SignBit = DAG.getNode(ISD::SHL, dl, NVT, SignBit,
633 DAG.getConstant(-SizeDiff, TLI.getShiftAmountTy()));
636 // Clear the sign bit of first operand.
637 SDValue Mask2 = (VT == MVT::f64)
638 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
639 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
640 Mask2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Mask2);
641 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
642 Result = DAG.getNode(ISD::AND, dl, NVT, Result, Mask2);
644 // Or the value with the sign bit.
645 Result = DAG.getNode(ISD::OR, dl, NVT, Result, SignBit);
649 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
651 SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
652 const TargetLowering &TLI) {
653 SDValue Chain = ST->getChain();
654 SDValue Ptr = ST->getBasePtr();
655 SDValue Val = ST->getValue();
656 MVT VT = Val.getValueType();
657 int Alignment = ST->getAlignment();
658 int SVOffset = ST->getSrcValueOffset();
659 DebugLoc dl = ST->getDebugLoc();
660 if (ST->getMemoryVT().isFloatingPoint() ||
661 ST->getMemoryVT().isVector()) {
662 MVT intVT = MVT::getIntegerVT(VT.getSizeInBits());
663 if (TLI.isTypeLegal(intVT)) {
664 // Expand to a bitconvert of the value to the integer type of the
665 // same size, then a (misaligned) int store.
666 // FIXME: Does not handle truncating floating point stores!
667 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, intVT, Val);
668 return DAG.getStore(Chain, dl, Result, Ptr, ST->getSrcValue(),
669 SVOffset, ST->isVolatile(), Alignment);
671 // Do a (aligned) store to a stack slot, then copy from the stack slot
672 // to the final destination using (unaligned) integer loads and stores.
673 MVT StoredVT = ST->getMemoryVT();
675 TLI.getRegisterType(MVT::getIntegerVT(StoredVT.getSizeInBits()));
676 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
677 unsigned RegBytes = RegVT.getSizeInBits() / 8;
678 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
680 // Make sure the stack slot is also aligned for the register type.
681 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
683 // Perform the original store, only redirected to the stack slot.
684 SDValue Store = DAG.getTruncStore(Chain, dl,
685 Val, StackPtr, NULL, 0,StoredVT);
686 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
687 SmallVector<SDValue, 8> Stores;
690 // Do all but one copies using the full register width.
691 for (unsigned i = 1; i < NumRegs; i++) {
692 // Load one integer register's worth from the stack slot.
693 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, NULL, 0);
694 // Store it to the final location. Remember the store.
695 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
696 ST->getSrcValue(), SVOffset + Offset,
698 MinAlign(ST->getAlignment(), Offset)));
699 // Increment the pointers.
701 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
703 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
706 // The last store may be partial. Do a truncating store. On big-endian
707 // machines this requires an extending load from the stack slot to ensure
708 // that the bits are in the right place.
709 MVT MemVT = MVT::getIntegerVT(8 * (StoredBytes - Offset));
711 // Load from the stack slot.
712 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
715 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
716 ST->getSrcValue(), SVOffset + Offset,
717 MemVT, ST->isVolatile(),
718 MinAlign(ST->getAlignment(), Offset)));
719 // The order of the stores doesn't matter - say it with a TokenFactor.
720 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
724 assert(ST->getMemoryVT().isInteger() &&
725 !ST->getMemoryVT().isVector() &&
726 "Unaligned store of unknown type.");
727 // Get the half-size VT
729 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1);
730 int NumBits = NewStoredVT.getSizeInBits();
731 int IncrementSize = NumBits / 8;
733 // Divide the stored value in two parts.
734 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
736 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
738 // Store the two parts
739 SDValue Store1, Store2;
740 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
741 ST->getSrcValue(), SVOffset, NewStoredVT,
742 ST->isVolatile(), Alignment);
743 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
744 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
745 Alignment = MinAlign(Alignment, IncrementSize);
746 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
747 ST->getSrcValue(), SVOffset + IncrementSize,
748 NewStoredVT, ST->isVolatile(), Alignment);
750 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
753 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
755 SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
756 const TargetLowering &TLI) {
757 int SVOffset = LD->getSrcValueOffset();
758 SDValue Chain = LD->getChain();
759 SDValue Ptr = LD->getBasePtr();
760 MVT VT = LD->getValueType(0);
761 MVT LoadedVT = LD->getMemoryVT();
762 DebugLoc dl = LD->getDebugLoc();
763 if (VT.isFloatingPoint() || VT.isVector()) {
764 MVT intVT = MVT::getIntegerVT(LoadedVT.getSizeInBits());
765 if (TLI.isTypeLegal(intVT)) {
766 // Expand to a (misaligned) integer load of the same size,
767 // then bitconvert to floating point or vector.
768 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getSrcValue(),
769 SVOffset, LD->isVolatile(),
771 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, LoadedVT, newLoad);
772 if (VT.isFloatingPoint() && LoadedVT != VT)
773 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result);
775 SDValue Ops[] = { Result, Chain };
776 return DAG.getMergeValues(Ops, 2, dl);
778 // Copy the value to a (aligned) stack slot using (unaligned) integer
779 // loads and stores, then do a (aligned) load from the stack slot.
780 MVT RegVT = TLI.getRegisterType(intVT);
781 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
782 unsigned RegBytes = RegVT.getSizeInBits() / 8;
783 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
785 // Make sure the stack slot is also aligned for the register type.
786 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
788 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
789 SmallVector<SDValue, 8> Stores;
790 SDValue StackPtr = StackBase;
793 // Do all but one copies using the full register width.
794 for (unsigned i = 1; i < NumRegs; i++) {
795 // Load one integer register's worth from the original location.
796 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, LD->getSrcValue(),
797 SVOffset + Offset, LD->isVolatile(),
798 MinAlign(LD->getAlignment(), Offset));
799 // Follow the load with a store to the stack slot. Remember the store.
800 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
802 // Increment the pointers.
804 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
805 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
809 // The last copy may be partial. Do an extending load.
810 MVT MemVT = MVT::getIntegerVT(8 * (LoadedBytes - Offset));
811 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
812 LD->getSrcValue(), SVOffset + Offset,
813 MemVT, LD->isVolatile(),
814 MinAlign(LD->getAlignment(), Offset));
815 // Follow the load with a store to the stack slot. Remember the store.
816 // On big-endian machines this requires a truncating store to ensure
817 // that the bits end up in the right place.
818 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
821 // The order of the stores doesn't matter - say it with a TokenFactor.
822 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
825 // Finally, perform the original load only redirected to the stack slot.
826 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
829 // Callers expect a MERGE_VALUES node.
830 SDValue Ops[] = { Load, TF };
831 return DAG.getMergeValues(Ops, 2, dl);
834 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
835 "Unaligned load of unsupported type.");
837 // Compute the new VT that is half the size of the old one. This is an
839 unsigned NumBits = LoadedVT.getSizeInBits();
841 NewLoadedVT = MVT::getIntegerVT(NumBits/2);
844 unsigned Alignment = LD->getAlignment();
845 unsigned IncrementSize = NumBits / 8;
846 ISD::LoadExtType HiExtType = LD->getExtensionType();
848 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
849 if (HiExtType == ISD::NON_EXTLOAD)
850 HiExtType = ISD::ZEXTLOAD;
852 // Load the value in two parts
854 if (TLI.isLittleEndian()) {
855 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(),
856 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
857 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
858 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
859 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(),
860 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
861 MinAlign(Alignment, IncrementSize));
863 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(),
864 SVOffset, NewLoadedVT,LD->isVolatile(), Alignment);
865 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
866 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
867 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(),
868 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
869 MinAlign(Alignment, IncrementSize));
872 // aggregate the two parts
873 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
874 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
875 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
877 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
880 SDValue Ops[] = { Result, TF };
881 return DAG.getMergeValues(Ops, 2, dl);
884 /// UnrollVectorOp - We know that the given vector has a legal type, however
885 /// the operation it performs is not legal and is an operation that we have
886 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
887 /// operating on each element individually.
888 SDValue SelectionDAGLegalize::UnrollVectorOp(SDValue Op) {
889 MVT VT = Op.getValueType();
890 assert(isTypeLegal(VT) &&
891 "Caller should expand or promote operands that are not legal!");
892 assert(Op.getNode()->getNumValues() == 1 &&
893 "Can't unroll a vector with multiple results!");
894 unsigned NE = VT.getVectorNumElements();
895 MVT EltVT = VT.getVectorElementType();
896 DebugLoc dl = Op.getDebugLoc();
898 SmallVector<SDValue, 8> Scalars;
899 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
900 for (unsigned i = 0; i != NE; ++i) {
901 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
902 SDValue Operand = Op.getOperand(j);
903 MVT OperandVT = Operand.getValueType();
904 if (OperandVT.isVector()) {
905 // A vector operand; extract a single element.
906 MVT OperandEltVT = OperandVT.getVectorElementType();
907 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
910 DAG.getConstant(i, MVT::i32));
912 // A scalar operand; just use it as is.
913 Operands[j] = Operand;
917 switch (Op.getOpcode()) {
919 Scalars.push_back(DAG.getNode(Op.getOpcode(), dl, EltVT,
920 &Operands[0], Operands.size()));
927 Scalars.push_back(DAG.getNode(Op.getOpcode(), dl, EltVT, Operands[0],
928 DAG.getShiftAmountOperand(Operands[1])));
933 return DAG.getBUILD_VECTOR(VT, dl, &Scalars[0], Scalars.size());
936 /// GetFPLibCall - Return the right libcall for the given floating point type.
937 static RTLIB::Libcall GetFPLibCall(MVT VT,
938 RTLIB::Libcall Call_F32,
939 RTLIB::Libcall Call_F64,
940 RTLIB::Libcall Call_F80,
941 RTLIB::Libcall Call_PPCF128) {
943 VT == MVT::f32 ? Call_F32 :
944 VT == MVT::f64 ? Call_F64 :
945 VT == MVT::f80 ? Call_F80 :
946 VT == MVT::ppcf128 ? Call_PPCF128 :
947 RTLIB::UNKNOWN_LIBCALL;
950 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
951 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
952 /// is necessary to spill the vector being inserted into to memory, perform
953 /// the insert there, and then read the result back.
954 SDValue SelectionDAGLegalize::
955 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
961 // If the target doesn't support this, we have to spill the input vector
962 // to a temporary stack slot, update the element, then reload it. This is
963 // badness. We could also load the value into a vector register (either
964 // with a "move to register" or "extload into register" instruction, then
965 // permute it into place, if the idx is a constant and if the idx is
966 // supported by the target.
967 MVT VT = Tmp1.getValueType();
968 MVT EltVT = VT.getVectorElementType();
969 MVT IdxVT = Tmp3.getValueType();
970 MVT PtrVT = TLI.getPointerTy();
971 SDValue StackPtr = DAG.CreateStackTemporary(VT);
973 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
976 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
977 PseudoSourceValue::getFixedStack(SPFI), 0);
979 // Truncate or zero extend offset to target pointer type.
980 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
981 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
982 // Add the offset to the index.
983 unsigned EltSize = EltVT.getSizeInBits()/8;
984 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
985 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
986 // Store the scalar value.
987 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2,
988 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT);
989 // Load the updated vector.
990 return DAG.getLoad(VT, dl, Ch, StackPtr,
991 PseudoSourceValue::getFixedStack(SPFI), 0);
995 /// LegalizeOp - We know that the specified value has a legal type, and
996 /// that its operands are legal. Now ensure that the operation itself
997 /// is legal, recursively ensuring that the operands' operations remain
999 SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
1000 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
1003 assert(isTypeLegal(Op.getValueType()) &&
1004 "Caller should expand or promote operands that are not legal!");
1005 SDNode *Node = Op.getNode();
1006 DebugLoc dl = Node->getDebugLoc();
1008 // If this operation defines any values that cannot be represented in a
1009 // register on this target, make sure to expand or promote them.
1010 if (Node->getNumValues() > 1) {
1011 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1012 if (getTypeAction(Node->getValueType(i)) != Legal) {
1013 HandleOp(Op.getValue(i));
1014 assert(LegalizedNodes.count(Op) &&
1015 "Handling didn't add legal operands!");
1016 return LegalizedNodes[Op];
1020 // Note that LegalizeOp may be reentered even from single-use nodes, which
1021 // means that we always must cache transformed nodes.
1022 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1023 if (I != LegalizedNodes.end()) return I->second;
1025 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
1026 SDValue Result = Op;
1027 bool isCustom = false;
1029 switch (Node->getOpcode()) {
1030 case ISD::FrameIndex:
1031 case ISD::EntryToken:
1033 case ISD::BasicBlock:
1034 case ISD::TargetFrameIndex:
1035 case ISD::TargetJumpTable:
1036 case ISD::TargetConstant:
1037 case ISD::TargetConstantFP:
1038 case ISD::TargetConstantPool:
1039 case ISD::TargetGlobalAddress:
1040 case ISD::TargetGlobalTLSAddress:
1041 case ISD::TargetExternalSymbol:
1042 case ISD::VALUETYPE:
1044 case ISD::MEMOPERAND:
1046 case ISD::ARG_FLAGS:
1047 // Primitives must all be legal.
1048 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
1049 "This must be legal!");
1052 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1053 // If this is a target node, legalize it by legalizing the operands then
1054 // passing it through.
1055 SmallVector<SDValue, 8> Ops;
1056 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1057 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1059 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
1061 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1062 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
1063 return Result.getValue(Op.getResNo());
1065 // Otherwise this is an unhandled builtin node. splat.
1067 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
1069 assert(0 && "Do not know how to legalize this operator!");
1071 case ISD::GLOBAL_OFFSET_TABLE:
1072 case ISD::GlobalAddress:
1073 case ISD::GlobalTLSAddress:
1074 case ISD::ExternalSymbol:
1075 case ISD::ConstantPool:
1076 case ISD::JumpTable: // Nothing to do.
1077 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1078 default: assert(0 && "This action is not supported yet!");
1079 case TargetLowering::Custom:
1080 Tmp1 = TLI.LowerOperation(Op, DAG);
1081 if (Tmp1.getNode()) Result = Tmp1;
1082 // FALLTHROUGH if the target doesn't want to lower this op after all.
1083 case TargetLowering::Legal:
1087 case ISD::FRAMEADDR:
1088 case ISD::RETURNADDR:
1089 // The only option for these nodes is to custom lower them. If the target
1090 // does not custom lower them, then return zero.
1091 Tmp1 = TLI.LowerOperation(Op, DAG);
1095 Result = DAG.getConstant(0, TLI.getPointerTy());
1097 case ISD::FRAME_TO_ARGS_OFFSET: {
1098 MVT VT = Node->getValueType(0);
1099 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1100 default: assert(0 && "This action is not supported yet!");
1101 case TargetLowering::Custom:
1102 Result = TLI.LowerOperation(Op, DAG);
1103 if (Result.getNode()) break;
1105 case TargetLowering::Legal:
1106 Result = DAG.getConstant(0, VT);
1111 case ISD::EXCEPTIONADDR: {
1112 Tmp1 = LegalizeOp(Node->getOperand(0));
1113 MVT VT = Node->getValueType(0);
1114 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1115 default: assert(0 && "This action is not supported yet!");
1116 case TargetLowering::Expand: {
1117 unsigned Reg = TLI.getExceptionAddressRegister();
1118 Result = DAG.getCopyFromReg(Tmp1, dl, Reg, VT);
1121 case TargetLowering::Custom:
1122 Result = TLI.LowerOperation(Op, DAG);
1123 if (Result.getNode()) break;
1125 case TargetLowering::Legal: {
1126 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp1 };
1127 Result = DAG.getMergeValues(Ops, 2, dl);
1132 if (Result.getNode()->getNumValues() == 1) break;
1134 assert(Result.getNode()->getNumValues() == 2 &&
1135 "Cannot return more than two values!");
1137 // Since we produced two values, make sure to remember that we
1138 // legalized both of them.
1139 Tmp1 = LegalizeOp(Result);
1140 Tmp2 = LegalizeOp(Result.getValue(1));
1141 AddLegalizedOperand(Op.getValue(0), Tmp1);
1142 AddLegalizedOperand(Op.getValue(1), Tmp2);
1143 return Op.getResNo() ? Tmp2 : Tmp1;
1144 case ISD::EHSELECTION: {
1145 Tmp1 = LegalizeOp(Node->getOperand(0));
1146 Tmp2 = LegalizeOp(Node->getOperand(1));
1147 MVT VT = Node->getValueType(0);
1148 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1149 default: assert(0 && "This action is not supported yet!");
1150 case TargetLowering::Expand: {
1151 unsigned Reg = TLI.getExceptionSelectorRegister();
1152 Result = DAG.getCopyFromReg(Tmp2, dl, Reg, VT);
1155 case TargetLowering::Custom:
1156 Result = TLI.LowerOperation(Op, DAG);
1157 if (Result.getNode()) break;
1159 case TargetLowering::Legal: {
1160 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp2 };
1161 Result = DAG.getMergeValues(Ops, 2, dl);
1166 if (Result.getNode()->getNumValues() == 1) break;
1168 assert(Result.getNode()->getNumValues() == 2 &&
1169 "Cannot return more than two values!");
1171 // Since we produced two values, make sure to remember that we
1172 // legalized both of them.
1173 Tmp1 = LegalizeOp(Result);
1174 Tmp2 = LegalizeOp(Result.getValue(1));
1175 AddLegalizedOperand(Op.getValue(0), Tmp1);
1176 AddLegalizedOperand(Op.getValue(1), Tmp2);
1177 return Op.getResNo() ? Tmp2 : Tmp1;
1178 case ISD::EH_RETURN: {
1179 MVT VT = Node->getValueType(0);
1180 // The only "good" option for this node is to custom lower it.
1181 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1182 default: assert(0 && "This action is not supported at all!");
1183 case TargetLowering::Custom:
1184 Result = TLI.LowerOperation(Op, DAG);
1185 if (Result.getNode()) break;
1187 case TargetLowering::Legal:
1188 // Target does not know, how to lower this, lower to noop
1189 Result = LegalizeOp(Node->getOperand(0));
1194 case ISD::AssertSext:
1195 case ISD::AssertZext:
1196 Tmp1 = LegalizeOp(Node->getOperand(0));
1197 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1199 case ISD::MERGE_VALUES:
1200 // Legalize eliminates MERGE_VALUES nodes.
1201 Result = Node->getOperand(Op.getResNo());
1203 case ISD::CopyFromReg:
1204 Tmp1 = LegalizeOp(Node->getOperand(0));
1205 Result = Op.getValue(0);
1206 if (Node->getNumValues() == 2) {
1207 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1209 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
1210 if (Node->getNumOperands() == 3) {
1211 Tmp2 = LegalizeOp(Node->getOperand(2));
1212 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1214 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1216 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
1218 // Since CopyFromReg produces two values, make sure to remember that we
1219 // legalized both of them.
1220 AddLegalizedOperand(Op.getValue(0), Result);
1221 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1222 return Result.getValue(Op.getResNo());
1224 MVT VT = Op.getValueType();
1225 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
1226 default: assert(0 && "This action is not supported yet!");
1227 case TargetLowering::Expand:
1229 Result = DAG.getConstant(0, VT);
1230 else if (VT.isFloatingPoint())
1231 Result = DAG.getConstantFP(APFloat(APInt(VT.getSizeInBits(), 0)),
1234 assert(0 && "Unknown value type!");
1236 case TargetLowering::Legal:
1242 case ISD::INTRINSIC_W_CHAIN:
1243 case ISD::INTRINSIC_WO_CHAIN:
1244 case ISD::INTRINSIC_VOID: {
1245 SmallVector<SDValue, 8> Ops;
1246 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1247 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1248 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1250 // Allow the target to custom lower its intrinsics if it wants to.
1251 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
1252 TargetLowering::Custom) {
1253 Tmp3 = TLI.LowerOperation(Result, DAG);
1254 if (Tmp3.getNode()) Result = Tmp3;
1257 if (Result.getNode()->getNumValues() == 1) break;
1259 // Must have return value and chain result.
1260 assert(Result.getNode()->getNumValues() == 2 &&
1261 "Cannot return more than two values!");
1263 // Since loads produce two values, make sure to remember that we
1264 // legalized both of them.
1265 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1266 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1267 return Result.getValue(Op.getResNo());
1270 case ISD::DBG_STOPPOINT:
1271 assert(Node->getNumOperands() == 1 && "Invalid DBG_STOPPOINT node!");
1272 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
1274 switch (TLI.getOperationAction(ISD::DBG_STOPPOINT, MVT::Other)) {
1275 case TargetLowering::Promote:
1276 default: assert(0 && "This action is not supported yet!");
1277 case TargetLowering::Expand: {
1278 DwarfWriter *DW = DAG.getDwarfWriter();
1279 bool useDEBUG_LOC = TLI.isOperationLegalOrCustom(ISD::DEBUG_LOC,
1281 bool useLABEL = TLI.isOperationLegalOrCustom(ISD::DBG_LABEL, MVT::Other);
1283 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node);
1284 GlobalVariable *CU_GV = cast<GlobalVariable>(DSP->getCompileUnit());
1285 if (DW && (useDEBUG_LOC || useLABEL) && !CU_GV->isDeclaration()) {
1286 DICompileUnit CU(cast<GlobalVariable>(DSP->getCompileUnit()));
1287 unsigned SrcFile = DW->RecordSource(CU.getDirectory(),
1290 unsigned Line = DSP->getLine();
1291 unsigned Col = DSP->getColumn();
1292 const Function *F = DAG.getMachineFunction().getFunction();
1294 if (!F->hasFnAttr(Attribute::OptimizeForSize)) {
1295 // A bit self-referential to have DebugLoc on Debug_Loc nodes, but it
1296 // won't hurt anything.
1298 SDValue Ops[] = { Tmp1, DAG.getConstant(Line, MVT::i32),
1299 DAG.getConstant(Col, MVT::i32),
1300 DAG.getConstant(SrcFile, MVT::i32) };
1301 Result = DAG.getNode(ISD::DEBUG_LOC, dl, MVT::Other, Ops, 4);
1303 unsigned ID = DW->RecordSourceLine(Line, Col, SrcFile);
1304 Result = DAG.getLabel(ISD::DBG_LABEL, dl, Tmp1, ID);
1307 Result = Tmp1; // chain
1310 Result = Tmp1; // chain
1314 case TargetLowering::Legal: {
1315 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1316 if (Action == Legal && Tmp1 == Node->getOperand(0))
1319 SmallVector<SDValue, 8> Ops;
1320 Ops.push_back(Tmp1);
1321 if (Action == Legal) {
1322 Ops.push_back(Node->getOperand(1)); // line # must be legal.
1323 Ops.push_back(Node->getOperand(2)); // col # must be legal.
1325 // Otherwise promote them.
1326 Ops.push_back(PromoteOp(Node->getOperand(1)));
1327 Ops.push_back(PromoteOp(Node->getOperand(2)));
1329 Ops.push_back(Node->getOperand(3)); // filename must be legal.
1330 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
1331 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1338 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!");
1339 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) {
1340 default: assert(0 && "This action is not supported yet!");
1341 case TargetLowering::Legal:
1342 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1343 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1344 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable.
1345 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1347 case TargetLowering::Expand:
1348 Result = LegalizeOp(Node->getOperand(0));
1353 case ISD::DEBUG_LOC:
1354 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
1355 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
1356 default: assert(0 && "This action is not supported yet!");
1357 case TargetLowering::Legal: {
1358 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1359 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1360 if (Action == Legal && Tmp1 == Node->getOperand(0))
1362 if (Action == Legal) {
1363 Tmp2 = Node->getOperand(1);
1364 Tmp3 = Node->getOperand(2);
1365 Tmp4 = Node->getOperand(3);
1367 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1368 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1369 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1371 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1377 case ISD::DBG_LABEL:
1379 assert(Node->getNumOperands() == 1 && "Invalid LABEL node!");
1380 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
1381 default: assert(0 && "This action is not supported yet!");
1382 case TargetLowering::Legal:
1383 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1384 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1386 case TargetLowering::Expand:
1387 Result = LegalizeOp(Node->getOperand(0));
1393 assert(Node->getNumOperands() == 4 && "Invalid Prefetch node!");
1394 switch (TLI.getOperationAction(ISD::PREFETCH, MVT::Other)) {
1395 default: assert(0 && "This action is not supported yet!");
1396 case TargetLowering::Legal:
1397 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1398 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1399 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the rw specifier.
1400 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize locality specifier.
1401 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1403 case TargetLowering::Expand:
1405 Result = LegalizeOp(Node->getOperand(0));
1410 case ISD::MEMBARRIER: {
1411 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!");
1412 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) {
1413 default: assert(0 && "This action is not supported yet!");
1414 case TargetLowering::Legal: {
1416 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1417 for (int x = 1; x < 6; ++x) {
1418 Ops[x] = Node->getOperand(x);
1419 if (!isTypeLegal(Ops[x].getValueType()))
1420 Ops[x] = PromoteOp(Ops[x]);
1422 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6);
1425 case TargetLowering::Expand:
1426 //There is no libgcc call for this op
1427 Result = Node->getOperand(0); // Noop
1433 case ISD::ATOMIC_CMP_SWAP: {
1434 unsigned int num_operands = 4;
1435 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1437 for (unsigned int x = 0; x < num_operands; ++x)
1438 Ops[x] = LegalizeOp(Node->getOperand(x));
1439 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1441 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1442 default: assert(0 && "This action is not supported yet!");
1443 case TargetLowering::Custom:
1444 Result = TLI.LowerOperation(Result, DAG);
1446 case TargetLowering::Legal:
1449 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1450 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1451 return Result.getValue(Op.getResNo());
1453 case ISD::ATOMIC_LOAD_ADD:
1454 case ISD::ATOMIC_LOAD_SUB:
1455 case ISD::ATOMIC_LOAD_AND:
1456 case ISD::ATOMIC_LOAD_OR:
1457 case ISD::ATOMIC_LOAD_XOR:
1458 case ISD::ATOMIC_LOAD_NAND:
1459 case ISD::ATOMIC_LOAD_MIN:
1460 case ISD::ATOMIC_LOAD_MAX:
1461 case ISD::ATOMIC_LOAD_UMIN:
1462 case ISD::ATOMIC_LOAD_UMAX:
1463 case ISD::ATOMIC_SWAP: {
1464 unsigned int num_operands = 3;
1465 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1467 for (unsigned int x = 0; x < num_operands; ++x)
1468 Ops[x] = LegalizeOp(Node->getOperand(x));
1469 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1471 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1472 default: assert(0 && "This action is not supported yet!");
1473 case TargetLowering::Custom:
1474 Result = TLI.LowerOperation(Result, DAG);
1476 case TargetLowering::Legal:
1479 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1480 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1481 return Result.getValue(Op.getResNo());
1483 case ISD::Constant: {
1484 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1486 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1488 // We know we don't need to expand constants here, constants only have one
1489 // value and we check that it is fine above.
1491 if (opAction == TargetLowering::Custom) {
1492 Tmp1 = TLI.LowerOperation(Result, DAG);
1498 case ISD::ConstantFP: {
1499 // Spill FP immediates to the constant pool if the target cannot directly
1500 // codegen them. Targets often have some immediate values that can be
1501 // efficiently generated into an FP register without a load. We explicitly
1502 // leave these constants as ConstantFP nodes for the target to deal with.
1503 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1505 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1506 default: assert(0 && "This action is not supported yet!");
1507 case TargetLowering::Legal:
1509 case TargetLowering::Custom:
1510 Tmp3 = TLI.LowerOperation(Result, DAG);
1511 if (Tmp3.getNode()) {
1516 case TargetLowering::Expand: {
1517 // Check to see if this FP immediate is already legal.
1518 bool isLegal = false;
1519 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1520 E = TLI.legal_fpimm_end(); I != E; ++I) {
1521 if (CFP->isExactlyValue(*I)) {
1526 // If this is a legal constant, turn it into a TargetConstantFP node.
1529 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1534 case ISD::TokenFactor:
1535 if (Node->getNumOperands() == 2) {
1536 Tmp1 = LegalizeOp(Node->getOperand(0));
1537 Tmp2 = LegalizeOp(Node->getOperand(1));
1538 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1539 } else if (Node->getNumOperands() == 3) {
1540 Tmp1 = LegalizeOp(Node->getOperand(0));
1541 Tmp2 = LegalizeOp(Node->getOperand(1));
1542 Tmp3 = LegalizeOp(Node->getOperand(2));
1543 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1545 SmallVector<SDValue, 8> Ops;
1546 // Legalize the operands.
1547 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1548 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1549 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1553 case ISD::FORMAL_ARGUMENTS:
1555 // The only option for this is to custom lower it.
1556 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1557 assert(Tmp3.getNode() && "Target didn't custom lower this node!");
1558 // A call within a calling sequence must be legalized to something
1559 // other than the normal CALLSEQ_END. Violating this gets Legalize
1560 // into an infinite loop.
1561 assert ((!IsLegalizingCall ||
1562 Node->getOpcode() != ISD::CALL ||
1563 Tmp3.getNode()->getOpcode() != ISD::CALLSEQ_END) &&
1564 "Nested CALLSEQ_START..CALLSEQ_END not supported.");
1566 // The number of incoming and outgoing values should match; unless the final
1567 // outgoing value is a flag.
1568 assert((Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() ||
1569 (Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() + 1 &&
1570 Tmp3.getNode()->getValueType(Tmp3.getNode()->getNumValues() - 1) ==
1572 "Lowering call/formal_arguments produced unexpected # results!");
1574 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1575 // remember that we legalized all of them, so it doesn't get relegalized.
1576 for (unsigned i = 0, e = Tmp3.getNode()->getNumValues(); i != e; ++i) {
1577 if (Tmp3.getNode()->getValueType(i) == MVT::Flag)
1579 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1580 if (Op.getResNo() == i)
1582 AddLegalizedOperand(SDValue(Node, i), Tmp1);
1585 case ISD::EXTRACT_SUBREG: {
1586 Tmp1 = LegalizeOp(Node->getOperand(0));
1587 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1588 assert(idx && "Operand must be a constant");
1589 Tmp2 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0));
1590 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1593 case ISD::INSERT_SUBREG: {
1594 Tmp1 = LegalizeOp(Node->getOperand(0));
1595 Tmp2 = LegalizeOp(Node->getOperand(1));
1596 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1597 assert(idx && "Operand must be a constant");
1598 Tmp3 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0));
1599 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1602 case ISD::BUILD_VECTOR:
1603 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1604 default: assert(0 && "This action is not supported yet!");
1605 case TargetLowering::Custom:
1606 Tmp3 = TLI.LowerOperation(Result, DAG);
1607 if (Tmp3.getNode()) {
1612 case TargetLowering::Expand:
1613 Result = ExpandBUILD_VECTOR(Result.getNode());
1617 case ISD::INSERT_VECTOR_ELT:
1618 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1619 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1621 // The type of the value to insert may not be legal, even though the vector
1622 // type is legal. Legalize/Promote accordingly. We do not handle Expand
1624 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1625 default: assert(0 && "Cannot expand insert element operand");
1626 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
1627 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
1629 // FIXME: An alternative would be to check to see if the target is not
1630 // going to custom lower this operation, we could bitcast to half elt
1631 // width and perform two inserts at that width, if that is legal.
1632 Tmp2 = Node->getOperand(1);
1635 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1637 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1638 Node->getValueType(0))) {
1639 default: assert(0 && "This action is not supported yet!");
1640 case TargetLowering::Legal:
1642 case TargetLowering::Custom:
1643 Tmp4 = TLI.LowerOperation(Result, DAG);
1644 if (Tmp4.getNode()) {
1649 case TargetLowering::Promote:
1650 // Fall thru for vector case
1651 case TargetLowering::Expand: {
1652 // If the insert index is a constant, codegen this as a scalar_to_vector,
1653 // then a shuffle that inserts it into the right position in the vector.
1654 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1655 // SCALAR_TO_VECTOR requires that the type of the value being inserted
1656 // match the element type of the vector being created.
1657 if (Tmp2.getValueType() ==
1658 Op.getValueType().getVectorElementType()) {
1659 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
1660 Tmp1.getValueType(), Tmp2);
1662 unsigned NumElts = Tmp1.getValueType().getVectorNumElements();
1664 MVT::getIntVectorWithNumElements(NumElts);
1665 MVT ShufMaskEltVT = ShufMaskVT.getVectorElementType();
1667 // We generate a shuffle of InVec and ScVec, so the shuffle mask
1668 // should be 0,1,2,3,4,5... with the appropriate element replaced with
1669 // elt 0 of the RHS.
1670 SmallVector<SDValue, 8> ShufOps;
1671 for (unsigned i = 0; i != NumElts; ++i) {
1672 if (i != InsertPos->getZExtValue())
1673 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1675 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1677 SDValue ShufMask = DAG.getBUILD_VECTOR(ShufMaskVT, dl,
1678 &ShufOps[0], ShufOps.size());
1680 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, Tmp1.getValueType(),
1681 Tmp1, ScVec, ShufMask);
1682 Result = LegalizeOp(Result);
1686 Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3, dl);
1691 case ISD::SCALAR_TO_VECTOR:
1692 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1693 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1697 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1698 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1699 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1700 Node->getValueType(0))) {
1701 default: assert(0 && "This action is not supported yet!");
1702 case TargetLowering::Legal:
1704 case TargetLowering::Custom:
1705 Tmp3 = TLI.LowerOperation(Result, DAG);
1706 if (Tmp3.getNode()) {
1711 case TargetLowering::Expand:
1712 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1716 case ISD::VECTOR_SHUFFLE:
1717 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1718 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1719 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1721 // Allow targets to custom lower the SHUFFLEs they support.
1722 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1723 default: assert(0 && "Unknown operation action!");
1724 case TargetLowering::Legal:
1725 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1726 "vector shuffle should not be created if not legal!");
1728 case TargetLowering::Custom:
1729 Tmp3 = TLI.LowerOperation(Result, DAG);
1730 if (Tmp3.getNode()) {
1735 case TargetLowering::Expand: {
1736 MVT VT = Node->getValueType(0);
1737 MVT EltVT = VT.getVectorElementType();
1738 MVT PtrVT = TLI.getPointerTy();
1739 SDValue Mask = Node->getOperand(2);
1740 unsigned NumElems = Mask.getNumOperands();
1741 SmallVector<SDValue,8> Ops;
1742 for (unsigned i = 0; i != NumElems; ++i) {
1743 SDValue Arg = Mask.getOperand(i);
1744 if (Arg.getOpcode() == ISD::UNDEF) {
1745 Ops.push_back(DAG.getUNDEF(EltVT));
1747 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1748 unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
1750 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Tmp1,
1751 DAG.getConstant(Idx, PtrVT)));
1753 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Tmp2,
1754 DAG.getConstant(Idx - NumElems, PtrVT)));
1757 Result = DAG.getBUILD_VECTOR(VT, dl, &Ops[0], Ops.size());
1760 case TargetLowering::Promote: {
1761 // Change base type to a different vector type.
1762 MVT OVT = Node->getValueType(0);
1763 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1765 // Cast the two input vectors.
1766 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp1);
1767 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp2);
1769 // Convert the shuffle mask to the right # elements.
1770 Tmp3 = SDValue(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1771 assert(Tmp3.getNode() && "Shuffle not legal?");
1772 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, NVT, Tmp1, Tmp2, Tmp3);
1773 Result = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Result);
1779 case ISD::EXTRACT_VECTOR_ELT:
1780 Tmp1 = Node->getOperand(0);
1781 Tmp2 = LegalizeOp(Node->getOperand(1));
1782 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1783 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1786 case ISD::EXTRACT_SUBVECTOR:
1787 Tmp1 = Node->getOperand(0);
1788 Tmp2 = LegalizeOp(Node->getOperand(1));
1789 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1790 Result = ExpandEXTRACT_SUBVECTOR(Result);
1793 case ISD::CONCAT_VECTORS: {
1794 // Use extract/insert/build vector for now. We might try to be
1795 // more clever later.
1796 MVT PtrVT = TLI.getPointerTy();
1797 SmallVector<SDValue, 8> Ops;
1798 unsigned NumOperands = Node->getNumOperands();
1799 for (unsigned i=0; i < NumOperands; ++i) {
1800 SDValue SubOp = Node->getOperand(i);
1801 MVT VVT = SubOp.getNode()->getValueType(0);
1802 MVT EltVT = VVT.getVectorElementType();
1803 unsigned NumSubElem = VVT.getVectorNumElements();
1804 for (unsigned j=0; j < NumSubElem; ++j) {
1805 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp,
1806 DAG.getConstant(j, PtrVT)));
1809 return LegalizeOp(DAG.getBUILD_VECTOR(Node->getValueType(0), dl,
1810 &Ops[0], Ops.size()));
1813 case ISD::CALLSEQ_START: {
1814 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1816 // Recursively Legalize all of the inputs of the call end that do not lead
1817 // to this call start. This ensures that any libcalls that need be inserted
1818 // are inserted *before* the CALLSEQ_START.
1819 IsLegalizingCallArgs = true;
1820 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1821 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1822 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
1825 IsLegalizingCallArgs = false;
1827 // Now that we legalized all of the inputs (which may have inserted
1828 // libcalls) create the new CALLSEQ_START node.
1829 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1831 // Merge in the last call, to ensure that this call start after the last
1833 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1834 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1835 Tmp1, LastCALLSEQ_END);
1836 Tmp1 = LegalizeOp(Tmp1);
1839 // Do not try to legalize the target-specific arguments (#1+).
1840 if (Tmp1 != Node->getOperand(0)) {
1841 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1843 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1846 // Remember that the CALLSEQ_START is legalized.
1847 AddLegalizedOperand(Op.getValue(0), Result);
1848 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1849 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1851 // Now that the callseq_start and all of the non-call nodes above this call
1852 // sequence have been legalized, legalize the call itself. During this
1853 // process, no libcalls can/will be inserted, guaranteeing that no calls
1855 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1856 // Note that we are selecting this call!
1857 LastCALLSEQ_END = SDValue(CallEnd, 0);
1858 IsLegalizingCall = true;
1860 // Legalize the call, starting from the CALLSEQ_END.
1861 LegalizeOp(LastCALLSEQ_END);
1862 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1865 case ISD::CALLSEQ_END:
1866 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1867 // will cause this node to be legalized as well as handling libcalls right.
1868 if (LastCALLSEQ_END.getNode() != Node) {
1869 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
1870 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1871 assert(I != LegalizedNodes.end() &&
1872 "Legalizing the call start should have legalized this node!");
1876 // Otherwise, the call start has been legalized and everything is going
1877 // according to plan. Just legalize ourselves normally here.
1878 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1879 // Do not try to legalize the target-specific arguments (#1+), except for
1880 // an optional flag input.
1881 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1882 if (Tmp1 != Node->getOperand(0)) {
1883 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1885 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1888 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1889 if (Tmp1 != Node->getOperand(0) ||
1890 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1891 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1894 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1897 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1898 // This finishes up call legalization.
1899 IsLegalizingCall = false;
1901 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1902 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1903 if (Node->getNumValues() == 2)
1904 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1905 return Result.getValue(Op.getResNo());
1906 case ISD::DYNAMIC_STACKALLOC: {
1907 MVT VT = Node->getValueType(0);
1908 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1909 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1910 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1911 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1913 Tmp1 = Result.getValue(0);
1914 Tmp2 = Result.getValue(1);
1915 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1916 default: assert(0 && "This action is not supported yet!");
1917 case TargetLowering::Expand: {
1918 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1919 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1920 " not tell us which reg is the stack pointer!");
1921 SDValue Chain = Tmp1.getOperand(0);
1923 // Chain the dynamic stack allocation so that it doesn't modify the stack
1924 // pointer when other instructions are using the stack.
1925 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1927 SDValue Size = Tmp2.getOperand(1);
1928 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1929 Chain = SP.getValue(1);
1930 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1931 unsigned StackAlign =
1932 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1933 if (Align > StackAlign)
1934 SP = DAG.getNode(ISD::AND, dl, VT, SP,
1935 DAG.getConstant(-(uint64_t)Align, VT));
1936 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1937 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1939 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1940 DAG.getIntPtrConstant(0, true), SDValue());
1942 Tmp1 = LegalizeOp(Tmp1);
1943 Tmp2 = LegalizeOp(Tmp2);
1946 case TargetLowering::Custom:
1947 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1948 if (Tmp3.getNode()) {
1949 Tmp1 = LegalizeOp(Tmp3);
1950 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1953 case TargetLowering::Legal:
1956 // Since this op produce two values, make sure to remember that we
1957 // legalized both of them.
1958 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
1959 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
1960 return Op.getResNo() ? Tmp2 : Tmp1;
1962 case ISD::INLINEASM: {
1963 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1964 bool Changed = false;
1965 // Legalize all of the operands of the inline asm, in case they are nodes
1966 // that need to be expanded or something. Note we skip the asm string and
1967 // all of the TargetConstant flags.
1968 SDValue Op = LegalizeOp(Ops[0]);
1969 Changed = Op != Ops[0];
1972 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1973 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1974 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getZExtValue() >> 3;
1975 for (++i; NumVals; ++i, --NumVals) {
1976 SDValue Op = LegalizeOp(Ops[i]);
1985 Op = LegalizeOp(Ops.back());
1986 Changed |= Op != Ops.back();
1991 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1993 // INLINE asm returns a chain and flag, make sure to add both to the map.
1994 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1995 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1996 return Result.getValue(Op.getResNo());
1999 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2000 // Ensure that libcalls are emitted before a branch.
2001 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
2002 Tmp1 = LegalizeOp(Tmp1);
2003 LastCALLSEQ_END = DAG.getEntryNode();
2005 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2008 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2009 // Ensure that libcalls are emitted before a branch.
2010 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
2011 Tmp1 = LegalizeOp(Tmp1);
2012 LastCALLSEQ_END = DAG.getEntryNode();
2014 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2015 default: assert(0 && "Indirect target must be legal type (pointer)!");
2017 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
2020 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2023 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2024 // Ensure that libcalls are emitted before a branch.
2025 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
2026 Tmp1 = LegalizeOp(Tmp1);
2027 LastCALLSEQ_END = DAG.getEntryNode();
2029 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
2030 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2032 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
2033 default: assert(0 && "This action is not supported yet!");
2034 case TargetLowering::Legal: break;
2035 case TargetLowering::Custom:
2036 Tmp1 = TLI.LowerOperation(Result, DAG);
2037 if (Tmp1.getNode()) Result = Tmp1;
2039 case TargetLowering::Expand: {
2040 SDValue Chain = Result.getOperand(0);
2041 SDValue Table = Result.getOperand(1);
2042 SDValue Index = Result.getOperand(2);
2044 MVT PTy = TLI.getPointerTy();
2045 MachineFunction &MF = DAG.getMachineFunction();
2046 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
2047 Index= DAG.getNode(ISD::MUL, dl, PTy,
2048 Index, DAG.getConstant(EntrySize, PTy));
2049 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2051 MVT MemVT = MVT::getIntegerVT(EntrySize * 8);
2052 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
2053 PseudoSourceValue::getJumpTable(), 0, MemVT);
2055 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2056 // For PIC, the sequence is:
2057 // BRIND(load(Jumptable + index) + RelocBase)
2058 // RelocBase can be JumpTable, GOT or some sort of global base.
2059 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
2060 TLI.getPICJumpTableRelocBase(Table, DAG));
2062 Result = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
2067 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2068 // Ensure that libcalls are emitted before a return.
2069 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
2070 Tmp1 = LegalizeOp(Tmp1);
2071 LastCALLSEQ_END = DAG.getEntryNode();
2073 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2074 case Expand: assert(0 && "It's impossible to expand bools");
2076 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
2079 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
2081 // The top bits of the promoted condition are not necessarily zero, ensure
2082 // that the value is properly zero extended.
2083 unsigned BitWidth = Tmp2.getValueSizeInBits();
2084 if (!DAG.MaskedValueIsZero(Tmp2,
2085 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2086 Tmp2 = DAG.getZeroExtendInReg(Tmp2, dl, MVT::i1);
2091 // Basic block destination (Op#2) is always legal.
2092 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2094 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
2095 default: assert(0 && "This action is not supported yet!");
2096 case TargetLowering::Legal: break;
2097 case TargetLowering::Custom:
2098 Tmp1 = TLI.LowerOperation(Result, DAG);
2099 if (Tmp1.getNode()) Result = Tmp1;
2101 case TargetLowering::Expand:
2102 // Expand brcond's setcc into its constituent parts and create a BR_CC
2104 if (Tmp2.getOpcode() == ISD::SETCC) {
2105 Result = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
2106 Tmp1, Tmp2.getOperand(2),
2107 Tmp2.getOperand(0), Tmp2.getOperand(1),
2108 Node->getOperand(2));
2110 Result = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
2111 DAG.getCondCode(ISD::SETNE), Tmp2,
2112 DAG.getConstant(0, Tmp2.getValueType()),
2113 Node->getOperand(2));
2119 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2120 // Ensure that libcalls are emitted before a branch.
2121 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
2122 Tmp1 = LegalizeOp(Tmp1);
2123 Tmp2 = Node->getOperand(2); // LHS
2124 Tmp3 = Node->getOperand(3); // RHS
2125 Tmp4 = Node->getOperand(1); // CC
2127 LegalizeSetCC(TLI.getSetCCResultType(Tmp2.getValueType()),
2128 Tmp2, Tmp3, Tmp4, dl);
2129 LastCALLSEQ_END = DAG.getEntryNode();
2131 // If we didn't get both a LHS and RHS back from LegalizeSetCC,
2132 // the LHS is a legal SETCC itself. In this case, we need to compare
2133 // the result against zero to select between true and false values.
2134 if (Tmp3.getNode() == 0) {
2135 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
2136 Tmp4 = DAG.getCondCode(ISD::SETNE);
2139 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
2140 Node->getOperand(4));
2142 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
2143 default: assert(0 && "Unexpected action for BR_CC!");
2144 case TargetLowering::Legal: break;
2145 case TargetLowering::Custom:
2146 Tmp4 = TLI.LowerOperation(Result, DAG);
2147 if (Tmp4.getNode()) Result = Tmp4;
2152 LoadSDNode *LD = cast<LoadSDNode>(Node);
2153 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
2154 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
2156 ISD::LoadExtType ExtType = LD->getExtensionType();
2157 if (ExtType == ISD::NON_EXTLOAD) {
2158 MVT VT = Node->getValueType(0);
2159 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2160 Tmp3 = Result.getValue(0);
2161 Tmp4 = Result.getValue(1);
2163 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
2164 default: assert(0 && "This action is not supported yet!");
2165 case TargetLowering::Legal:
2166 // If this is an unaligned load and the target doesn't support it,
2168 if (!TLI.allowsUnalignedMemoryAccesses()) {
2169 unsigned ABIAlignment = TLI.getTargetData()->
2170 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
2171 if (LD->getAlignment() < ABIAlignment){
2172 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
2174 Tmp3 = Result.getOperand(0);
2175 Tmp4 = Result.getOperand(1);
2176 Tmp3 = LegalizeOp(Tmp3);
2177 Tmp4 = LegalizeOp(Tmp4);
2181 case TargetLowering::Custom:
2182 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
2183 if (Tmp1.getNode()) {
2184 Tmp3 = LegalizeOp(Tmp1);
2185 Tmp4 = LegalizeOp(Tmp1.getValue(1));
2188 case TargetLowering::Promote: {
2189 // Only promote a load of vector type to another.
2190 assert(VT.isVector() && "Cannot promote this load!");
2191 // Change base type to a different vector type.
2192 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
2194 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
2195 LD->getSrcValueOffset(),
2196 LD->isVolatile(), LD->getAlignment());
2197 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp1));
2198 Tmp4 = LegalizeOp(Tmp1.getValue(1));
2202 // Since loads produce two values, make sure to remember that we
2203 // legalized both of them.
2204 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
2205 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
2206 return Op.getResNo() ? Tmp4 : Tmp3;
2208 MVT SrcVT = LD->getMemoryVT();
2209 unsigned SrcWidth = SrcVT.getSizeInBits();
2210 int SVOffset = LD->getSrcValueOffset();
2211 unsigned Alignment = LD->getAlignment();
2212 bool isVolatile = LD->isVolatile();
2214 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
2215 // Some targets pretend to have an i1 loading operation, and actually
2216 // load an i8. This trick is correct for ZEXTLOAD because the top 7
2217 // bits are guaranteed to be zero; it helps the optimizers understand
2218 // that these bits are zero. It is also useful for EXTLOAD, since it
2219 // tells the optimizers that those bits are undefined. It would be
2220 // nice to have an effective generic way of getting these benefits...
2221 // Until such a way is found, don't insist on promoting i1 here.
2222 (SrcVT != MVT::i1 ||
2223 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
2224 // Promote to a byte-sized load if not loading an integral number of
2225 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
2226 unsigned NewWidth = SrcVT.getStoreSizeInBits();
2227 MVT NVT = MVT::getIntegerVT(NewWidth);
2230 // The extra bits are guaranteed to be zero, since we stored them that
2231 // way. A zext load from NVT thus automatically gives zext from SrcVT.
2233 ISD::LoadExtType NewExtType =
2234 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
2236 Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
2237 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
2238 NVT, isVolatile, Alignment);
2240 Ch = Result.getValue(1); // The chain.
2242 if (ExtType == ISD::SEXTLOAD)
2243 // Having the top bits zero doesn't help when sign extending.
2244 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
2245 Result.getValueType(),
2246 Result, DAG.getValueType(SrcVT));
2247 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
2248 // All the top bits are guaranteed to be zero - inform the optimizers.
2249 Result = DAG.getNode(ISD::AssertZext, dl,
2250 Result.getValueType(), Result,
2251 DAG.getValueType(SrcVT));
2253 Tmp1 = LegalizeOp(Result);
2254 Tmp2 = LegalizeOp(Ch);
2255 } else if (SrcWidth & (SrcWidth - 1)) {
2256 // If not loading a power-of-2 number of bits, expand as two loads.
2257 assert(SrcVT.isExtended() && !SrcVT.isVector() &&
2258 "Unsupported extload!");
2259 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
2260 assert(RoundWidth < SrcWidth);
2261 unsigned ExtraWidth = SrcWidth - RoundWidth;
2262 assert(ExtraWidth < RoundWidth);
2263 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2264 "Load size not an integral number of bytes!");
2265 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2266 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2268 unsigned IncrementSize;
2270 if (TLI.isLittleEndian()) {
2271 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
2272 // Load the bottom RoundWidth bits.
2273 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl,
2274 Node->getValueType(0), Tmp1, Tmp2,
2275 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2278 // Load the remaining ExtraWidth bits.
2279 IncrementSize = RoundWidth / 8;
2280 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
2281 DAG.getIntPtrConstant(IncrementSize));
2282 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
2283 LD->getSrcValue(), SVOffset + IncrementSize,
2284 ExtraVT, isVolatile,
2285 MinAlign(Alignment, IncrementSize));
2287 // Build a factor node to remember that this load is independent of the
2289 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
2292 // Move the top bits to the right place.
2293 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
2294 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2296 // Join the hi and lo parts.
2297 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
2299 // Big endian - avoid unaligned loads.
2300 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
2301 // Load the top RoundWidth bits.
2302 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
2303 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2306 // Load the remaining ExtraWidth bits.
2307 IncrementSize = RoundWidth / 8;
2308 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
2309 DAG.getIntPtrConstant(IncrementSize));
2310 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl,
2311 Node->getValueType(0), Tmp1, Tmp2,
2312 LD->getSrcValue(), SVOffset + IncrementSize,
2313 ExtraVT, isVolatile,
2314 MinAlign(Alignment, IncrementSize));
2316 // Build a factor node to remember that this load is independent of the
2318 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
2321 // Move the top bits to the right place.
2322 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
2323 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2325 // Join the hi and lo parts.
2326 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
2329 Tmp1 = LegalizeOp(Result);
2330 Tmp2 = LegalizeOp(Ch);
2332 switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
2333 default: assert(0 && "This action is not supported yet!");
2334 case TargetLowering::Custom:
2337 case TargetLowering::Legal:
2338 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2339 Tmp1 = Result.getValue(0);
2340 Tmp2 = Result.getValue(1);
2343 Tmp3 = TLI.LowerOperation(Result, DAG);
2344 if (Tmp3.getNode()) {
2345 Tmp1 = LegalizeOp(Tmp3);
2346 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2349 // If this is an unaligned load and the target doesn't support it,
2351 if (!TLI.allowsUnalignedMemoryAccesses()) {
2352 unsigned ABIAlignment = TLI.getTargetData()->
2353 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
2354 if (LD->getAlignment() < ABIAlignment){
2355 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
2357 Tmp1 = Result.getOperand(0);
2358 Tmp2 = Result.getOperand(1);
2359 Tmp1 = LegalizeOp(Tmp1);
2360 Tmp2 = LegalizeOp(Tmp2);
2365 case TargetLowering::Expand:
2366 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
2367 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
2368 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
2369 LD->getSrcValueOffset(),
2370 LD->isVolatile(), LD->getAlignment());
2371 Result = DAG.getNode(ISD::FP_EXTEND, dl,
2372 Node->getValueType(0), Load);
2373 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
2374 Tmp2 = LegalizeOp(Load.getValue(1));
2377 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
2378 // Turn the unsupported load into an EXTLOAD followed by an explicit
2379 // zero/sign extend inreg.
2380 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
2381 Tmp1, Tmp2, LD->getSrcValue(),
2382 LD->getSrcValueOffset(), SrcVT,
2383 LD->isVolatile(), LD->getAlignment());
2385 if (ExtType == ISD::SEXTLOAD)
2386 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
2387 Result.getValueType(),
2388 Result, DAG.getValueType(SrcVT));
2390 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT);
2391 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
2392 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
2397 // Since loads produce two values, make sure to remember that we legalized
2399 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2400 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2401 return Op.getResNo() ? Tmp2 : Tmp1;
2404 case ISD::EXTRACT_ELEMENT: {
2405 MVT OpTy = Node->getOperand(0).getValueType();
2406 switch (getTypeAction(OpTy)) {
2407 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
2409 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
2411 Result = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
2412 DAG.getConstant(OpTy.getSizeInBits()/2,
2413 TLI.getShiftAmountTy()));
2414 Result = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Result);
2417 Result = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
2418 Node->getOperand(0));
2422 // Get both the low and high parts.
2423 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2424 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
2425 Result = Tmp2; // 1 -> Hi
2427 Result = Tmp1; // 0 -> Lo
2433 case ISD::CopyToReg:
2434 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2436 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
2437 "Register type must be legal!");
2438 // Legalize the incoming value (must be a legal type).
2439 Tmp2 = LegalizeOp(Node->getOperand(2));
2440 if (Node->getNumValues() == 1) {
2441 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
2443 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
2444 if (Node->getNumOperands() == 4) {
2445 Tmp3 = LegalizeOp(Node->getOperand(3));
2446 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
2449 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
2452 // Since this produces two values, make sure to remember that we legalized
2454 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
2455 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
2461 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2463 // Ensure that libcalls are emitted before a return.
2464 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
2465 Tmp1 = LegalizeOp(Tmp1);
2466 LastCALLSEQ_END = DAG.getEntryNode();
2468 switch (Node->getNumOperands()) {
2470 Tmp2 = Node->getOperand(1);
2471 Tmp3 = Node->getOperand(2); // Signness
2472 switch (getTypeAction(Tmp2.getValueType())) {
2474 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
2477 if (!Tmp2.getValueType().isVector()) {
2479 ExpandOp(Tmp2, Lo, Hi);
2481 // Big endian systems want the hi reg first.
2482 if (TLI.isBigEndian())
2486 Result = DAG.getNode(ISD::RET, dl, MVT::Other,
2487 Tmp1, Lo, Tmp3, Hi,Tmp3);
2489 Result = DAG.getNode(ISD::RET, dl, MVT::Other, Tmp1, Lo, Tmp3);
2490 Result = LegalizeOp(Result);
2492 SDNode *InVal = Tmp2.getNode();
2493 int InIx = Tmp2.getResNo();
2494 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
2495 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
2497 // Figure out if there is a simple type corresponding to this Vector
2498 // type. If so, convert to the vector type.
2499 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2500 if (TLI.isTypeLegal(TVT)) {
2501 // Turn this into a return of the vector type.
2502 Tmp2 = LegalizeOp(Tmp2);
2503 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2504 } else if (NumElems == 1) {
2505 // Turn this into a return of the scalar type.
2506 Tmp2 = ScalarizeVectorOp(Tmp2);
2507 Tmp2 = LegalizeOp(Tmp2);
2508 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2510 // FIXME: Returns of gcc generic vectors smaller than a legal type
2511 // should be returned in integer registers!
2513 // The scalarized value type may not be legal, e.g. it might require
2514 // promotion or expansion. Relegalize the return.
2515 Result = LegalizeOp(Result);
2517 // FIXME: Returns of gcc generic vectors larger than a legal vector
2518 // type should be returned by reference!
2520 SplitVectorOp(Tmp2, Lo, Hi);
2521 Result = DAG.getNode(ISD::RET, dl, MVT::Other,
2522 Tmp1, Lo, Tmp3, Hi,Tmp3);
2523 Result = LegalizeOp(Result);
2528 Tmp2 = PromoteOp(Node->getOperand(1));
2529 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2530 Result = LegalizeOp(Result);
2535 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2537 default: { // ret <values>
2538 SmallVector<SDValue, 8> NewValues;
2539 NewValues.push_back(Tmp1);
2540 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
2541 switch (getTypeAction(Node->getOperand(i).getValueType())) {
2543 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
2544 NewValues.push_back(Node->getOperand(i+1));
2548 assert(!Node->getOperand(i).getValueType().isExtended() &&
2549 "FIXME: TODO: implement returning non-legal vector types!");
2550 ExpandOp(Node->getOperand(i), Lo, Hi);
2551 NewValues.push_back(Lo);
2552 NewValues.push_back(Node->getOperand(i+1));
2554 NewValues.push_back(Hi);
2555 NewValues.push_back(Node->getOperand(i+1));
2560 assert(0 && "Can't promote multiple return value yet!");
2563 if (NewValues.size() == Node->getNumOperands())
2564 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
2566 Result = DAG.getNode(ISD::RET, dl, MVT::Other,
2567 &NewValues[0], NewValues.size());
2572 if (Result.getOpcode() == ISD::RET) {
2573 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
2574 default: assert(0 && "This action is not supported yet!");
2575 case TargetLowering::Legal: break;
2576 case TargetLowering::Custom:
2577 Tmp1 = TLI.LowerOperation(Result, DAG);
2578 if (Tmp1.getNode()) Result = Tmp1;
2584 StoreSDNode *ST = cast<StoreSDNode>(Node);
2585 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
2586 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
2587 int SVOffset = ST->getSrcValueOffset();
2588 unsigned Alignment = ST->getAlignment();
2589 bool isVolatile = ST->isVolatile();
2591 if (!ST->isTruncatingStore()) {
2592 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
2593 // FIXME: We shouldn't do this for TargetConstantFP's.
2594 // FIXME: move this to the DAG Combiner! Note that we can't regress due
2595 // to phase ordering between legalized code and the dag combiner. This
2596 // probably means that we need to integrate dag combiner and legalizer
2598 // We generally can't do this one for long doubles.
2599 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
2600 if (CFP->getValueType(0) == MVT::f32 &&
2601 getTypeAction(MVT::i32) == Legal) {
2602 Tmp3 = DAG.getConstant(CFP->getValueAPF().
2603 bitcastToAPInt().zextOrTrunc(32),
2605 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2606 SVOffset, isVolatile, Alignment);
2608 } else if (CFP->getValueType(0) == MVT::f64) {
2609 // If this target supports 64-bit registers, do a single 64-bit store.
2610 if (getTypeAction(MVT::i64) == Legal) {
2611 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
2612 zextOrTrunc(64), MVT::i64);
2613 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2614 SVOffset, isVolatile, Alignment);
2616 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
2617 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
2618 // stores. If the target supports neither 32- nor 64-bits, this
2619 // xform is certainly not worth it.
2620 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
2621 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
2622 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
2623 if (TLI.isBigEndian()) std::swap(Lo, Hi);
2625 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(),
2626 SVOffset, isVolatile, Alignment);
2627 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
2628 DAG.getIntPtrConstant(4));
2629 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
2630 isVolatile, MinAlign(Alignment, 4U));
2632 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2638 switch (getTypeAction(ST->getMemoryVT())) {
2640 Tmp3 = LegalizeOp(ST->getValue());
2641 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2644 MVT VT = Tmp3.getValueType();
2645 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2646 default: assert(0 && "This action is not supported yet!");
2647 case TargetLowering::Legal:
2648 // If this is an unaligned store and the target doesn't support it,
2650 if (!TLI.allowsUnalignedMemoryAccesses()) {
2651 unsigned ABIAlignment = TLI.getTargetData()->
2652 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2653 if (ST->getAlignment() < ABIAlignment)
2654 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
2658 case TargetLowering::Custom:
2659 Tmp1 = TLI.LowerOperation(Result, DAG);
2660 if (Tmp1.getNode()) Result = Tmp1;
2662 case TargetLowering::Promote:
2663 assert(VT.isVector() && "Unknown legal promote case!");
2664 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, dl,
2665 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2666 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2,
2667 ST->getSrcValue(), SVOffset, isVolatile,
2674 if (!ST->getMemoryVT().isVector()) {
2675 // Truncate the value and store the result.
2676 Tmp3 = PromoteOp(ST->getValue());
2677 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2678 SVOffset, ST->getMemoryVT(),
2679 isVolatile, Alignment);
2682 // Fall thru to expand for vector
2684 unsigned IncrementSize = 0;
2687 // If this is a vector type, then we have to calculate the increment as
2688 // the product of the element size in bytes, and the number of elements
2689 // in the high half of the vector.
2690 if (ST->getValue().getValueType().isVector()) {
2691 SDNode *InVal = ST->getValue().getNode();
2692 int InIx = ST->getValue().getResNo();
2693 MVT InVT = InVal->getValueType(InIx);
2694 unsigned NumElems = InVT.getVectorNumElements();
2695 MVT EVT = InVT.getVectorElementType();
2697 // Figure out if there is a simple type corresponding to this Vector
2698 // type. If so, convert to the vector type.
2699 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2700 if (TLI.isTypeLegal(TVT)) {
2701 // Turn this into a normal store of the vector type.
2702 Tmp3 = LegalizeOp(ST->getValue());
2703 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2704 SVOffset, isVolatile, Alignment);
2705 Result = LegalizeOp(Result);
2707 } else if (NumElems == 1) {
2708 // Turn this into a normal store of the scalar type.
2709 Tmp3 = ScalarizeVectorOp(ST->getValue());
2710 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2711 SVOffset, isVolatile, Alignment);
2712 // The scalarized value type may not be legal, e.g. it might require
2713 // promotion or expansion. Relegalize the scalar store.
2714 Result = LegalizeOp(Result);
2717 // Check if we have widen this node with another value
2718 std::map<SDValue, SDValue>::iterator I =
2719 WidenNodes.find(ST->getValue());
2720 if (I != WidenNodes.end()) {
2721 Result = StoreWidenVectorOp(ST, Tmp1, Tmp2);
2725 SplitVectorOp(ST->getValue(), Lo, Hi);
2726 IncrementSize = Lo.getNode()->getValueType(0).getVectorNumElements() *
2727 EVT.getSizeInBits()/8;
2731 ExpandOp(ST->getValue(), Lo, Hi);
2732 IncrementSize = Hi.getNode() ? Hi.getValueType().getSizeInBits()/8 : 0;
2734 if (Hi.getNode() && TLI.isBigEndian())
2738 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(),
2739 SVOffset, isVolatile, Alignment);
2741 if (Hi.getNode() == NULL) {
2742 // Must be int <-> float one-to-one expansion.
2747 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
2748 DAG.getIntPtrConstant(IncrementSize));
2749 assert(isTypeLegal(Tmp2.getValueType()) &&
2750 "Pointers must be legal!");
2751 SVOffset += IncrementSize;
2752 Alignment = MinAlign(Alignment, IncrementSize);
2753 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
2754 SVOffset, isVolatile, Alignment);
2755 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2760 switch (getTypeAction(ST->getValue().getValueType())) {
2762 Tmp3 = LegalizeOp(ST->getValue());
2765 if (!ST->getValue().getValueType().isVector()) {
2766 // We can promote the value, the truncstore will still take care of it.
2767 Tmp3 = PromoteOp(ST->getValue());
2770 // Vector case falls through to expand
2772 // Just store the low part. This may become a non-trunc store, so make
2773 // sure to use getTruncStore, not UpdateNodeOperands below.
2774 ExpandOp(ST->getValue(), Tmp3, Tmp4);
2775 return DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2776 SVOffset, MVT::i8, isVolatile, Alignment);
2779 MVT StVT = ST->getMemoryVT();
2780 unsigned StWidth = StVT.getSizeInBits();
2782 if (StWidth != StVT.getStoreSizeInBits()) {
2783 // Promote to a byte-sized store with upper bits zero if not
2784 // storing an integral number of bytes. For example, promote
2785 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
2786 MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits());
2787 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT);
2788 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2789 SVOffset, NVT, isVolatile, Alignment);
2790 } else if (StWidth & (StWidth - 1)) {
2791 // If not storing a power-of-2 number of bits, expand as two stores.
2792 assert(StVT.isExtended() && !StVT.isVector() &&
2793 "Unsupported truncstore!");
2794 unsigned RoundWidth = 1 << Log2_32(StWidth);
2795 assert(RoundWidth < StWidth);
2796 unsigned ExtraWidth = StWidth - RoundWidth;
2797 assert(ExtraWidth < RoundWidth);
2798 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2799 "Store size not an integral number of bytes!");
2800 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2801 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2803 unsigned IncrementSize;
2805 if (TLI.isLittleEndian()) {
2806 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
2807 // Store the bottom RoundWidth bits.
2808 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2810 isVolatile, Alignment);
2812 // Store the remaining ExtraWidth bits.
2813 IncrementSize = RoundWidth / 8;
2814 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
2815 DAG.getIntPtrConstant(IncrementSize));
2816 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
2817 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2818 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
2819 SVOffset + IncrementSize, ExtraVT, isVolatile,
2820 MinAlign(Alignment, IncrementSize));
2822 // Big endian - avoid unaligned stores.
2823 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
2824 // Store the top RoundWidth bits.
2825 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
2826 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2827 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
2828 SVOffset, RoundVT, isVolatile, Alignment);
2830 // Store the remaining ExtraWidth bits.
2831 IncrementSize = RoundWidth / 8;
2832 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
2833 DAG.getIntPtrConstant(IncrementSize));
2834 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2835 SVOffset + IncrementSize, ExtraVT, isVolatile,
2836 MinAlign(Alignment, IncrementSize));
2839 // The order of the stores doesn't matter.
2840 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2842 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2843 Tmp2 != ST->getBasePtr())
2844 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2847 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
2848 default: assert(0 && "This action is not supported yet!");
2849 case TargetLowering::Legal:
2850 // If this is an unaligned store and the target doesn't support it,
2852 if (!TLI.allowsUnalignedMemoryAccesses()) {
2853 unsigned ABIAlignment = TLI.getTargetData()->
2854 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2855 if (ST->getAlignment() < ABIAlignment)
2856 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
2860 case TargetLowering::Custom:
2861 Result = TLI.LowerOperation(Result, DAG);
2864 // TRUNCSTORE:i16 i32 -> STORE i16
2865 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
2866 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3);
2867 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2868 SVOffset, isVolatile, Alignment);
2876 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2877 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2879 case ISD::STACKSAVE:
2880 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2881 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2882 Tmp1 = Result.getValue(0);
2883 Tmp2 = Result.getValue(1);
2885 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2886 default: assert(0 && "This action is not supported yet!");
2887 case TargetLowering::Legal: break;
2888 case TargetLowering::Custom:
2889 Tmp3 = TLI.LowerOperation(Result, DAG);
2890 if (Tmp3.getNode()) {
2891 Tmp1 = LegalizeOp(Tmp3);
2892 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2895 case TargetLowering::Expand:
2896 // Expand to CopyFromReg if the target set
2897 // StackPointerRegisterToSaveRestore.
2898 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2899 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), dl, SP,
2900 Node->getValueType(0));
2901 Tmp2 = Tmp1.getValue(1);
2903 Tmp1 = DAG.getUNDEF(Node->getValueType(0));
2904 Tmp2 = Node->getOperand(0);
2909 // Since stacksave produce two values, make sure to remember that we
2910 // legalized both of them.
2911 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2912 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2913 return Op.getResNo() ? Tmp2 : Tmp1;
2915 case ISD::STACKRESTORE:
2916 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2917 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2918 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2920 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2921 default: assert(0 && "This action is not supported yet!");
2922 case TargetLowering::Legal: break;
2923 case TargetLowering::Custom:
2924 Tmp1 = TLI.LowerOperation(Result, DAG);
2925 if (Tmp1.getNode()) Result = Tmp1;
2927 case TargetLowering::Expand:
2928 // Expand to CopyToReg if the target set
2929 // StackPointerRegisterToSaveRestore.
2930 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2931 Result = DAG.getCopyToReg(Tmp1, dl, SP, Tmp2);
2939 case ISD::READCYCLECOUNTER:
2940 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2941 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2942 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2943 Node->getValueType(0))) {
2944 default: assert(0 && "This action is not supported yet!");
2945 case TargetLowering::Legal:
2946 Tmp1 = Result.getValue(0);
2947 Tmp2 = Result.getValue(1);
2949 case TargetLowering::Custom:
2950 Result = TLI.LowerOperation(Result, DAG);
2951 Tmp1 = LegalizeOp(Result.getValue(0));
2952 Tmp2 = LegalizeOp(Result.getValue(1));
2956 // Since rdcc produce two values, make sure to remember that we legalized
2958 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2959 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2963 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2964 case Expand: assert(0 && "It's impossible to expand bools");
2966 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2969 assert(!Node->getOperand(0).getValueType().isVector() && "not possible");
2970 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2971 // Make sure the condition is either zero or one.
2972 unsigned BitWidth = Tmp1.getValueSizeInBits();
2973 if (!DAG.MaskedValueIsZero(Tmp1,
2974 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2975 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, MVT::i1);
2979 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2980 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2982 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2984 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2985 default: assert(0 && "This action is not supported yet!");
2986 case TargetLowering::Legal: break;
2987 case TargetLowering::Custom: {
2988 Tmp1 = TLI.LowerOperation(Result, DAG);
2989 if (Tmp1.getNode()) Result = Tmp1;
2992 case TargetLowering::Expand:
2993 if (Tmp1.getOpcode() == ISD::SETCC) {
2994 Result = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
2996 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2998 Result = DAG.getSelectCC(dl, Tmp1,
2999 DAG.getConstant(0, Tmp1.getValueType()),
3000 Tmp2, Tmp3, ISD::SETNE);
3003 case TargetLowering::Promote: {
3005 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
3006 unsigned ExtOp, TruncOp;
3007 if (Tmp2.getValueType().isVector()) {
3008 ExtOp = ISD::BIT_CONVERT;
3009 TruncOp = ISD::BIT_CONVERT;
3010 } else if (Tmp2.getValueType().isInteger()) {
3011 ExtOp = ISD::ANY_EXTEND;
3012 TruncOp = ISD::TRUNCATE;
3014 ExtOp = ISD::FP_EXTEND;
3015 TruncOp = ISD::FP_ROUND;
3017 // Promote each of the values to the new type.
3018 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Tmp2);
3019 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Tmp3);
3020 // Perform the larger operation, then round down.
3021 Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2,Tmp3);
3022 if (TruncOp != ISD::FP_ROUND)
3023 Result = DAG.getNode(TruncOp, dl, Node->getValueType(0), Result);
3025 Result = DAG.getNode(TruncOp, dl, Node->getValueType(0), Result,
3026 DAG.getIntPtrConstant(0));
3031 case ISD::SELECT_CC: {
3032 Tmp1 = Node->getOperand(0); // LHS
3033 Tmp2 = Node->getOperand(1); // RHS
3034 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
3035 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
3036 SDValue CC = Node->getOperand(4);
3038 LegalizeSetCC(TLI.getSetCCResultType(Tmp1.getValueType()),
3039 Tmp1, Tmp2, CC, dl);
3041 // If we didn't get both a LHS and RHS back from LegalizeSetCC,
3042 // the LHS is a legal SETCC itself. In this case, we need to compare
3043 // the result against zero to select between true and false values.
3044 if (Tmp2.getNode() == 0) {
3045 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3046 CC = DAG.getCondCode(ISD::SETNE);
3048 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
3050 // Everything is legal, see if we should expand this op or something.
3051 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
3052 default: assert(0 && "This action is not supported yet!");
3053 case TargetLowering::Legal: break;
3054 case TargetLowering::Custom:
3055 Tmp1 = TLI.LowerOperation(Result, DAG);
3056 if (Tmp1.getNode()) Result = Tmp1;
3062 Tmp1 = Node->getOperand(0);
3063 Tmp2 = Node->getOperand(1);
3064 Tmp3 = Node->getOperand(2);
3065 LegalizeSetCC(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl);
3067 // If we had to Expand the SetCC operands into a SELECT node, then it may
3068 // not always be possible to return a true LHS & RHS. In this case, just
3069 // return the value we legalized, returned in the LHS
3070 if (Tmp2.getNode() == 0) {
3075 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
3076 default: assert(0 && "Cannot handle this action for SETCC yet!");
3077 case TargetLowering::Custom:
3080 case TargetLowering::Legal:
3081 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3083 Tmp4 = TLI.LowerOperation(Result, DAG);
3084 if (Tmp4.getNode()) Result = Tmp4;
3087 case TargetLowering::Promote: {
3088 // First step, figure out the appropriate operation to use.
3089 // Allow SETCC to not be supported for all legal data types
3090 // Mostly this targets FP
3091 MVT NewInTy = Node->getOperand(0).getValueType();
3092 MVT OldVT = NewInTy; OldVT = OldVT;
3094 // Scan for the appropriate larger type to use.
3096 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
3098 assert(NewInTy.isInteger() == OldVT.isInteger() &&
3099 "Fell off of the edge of the integer world");
3100 assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() &&
3101 "Fell off of the edge of the floating point world");
3103 // If the target supports SETCC of this type, use it.
3104 if (TLI.isOperationLegalOrCustom(ISD::SETCC, NewInTy))
3107 if (NewInTy.isInteger())
3108 assert(0 && "Cannot promote Legal Integer SETCC yet");
3110 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NewInTy, Tmp1);
3111 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NewInTy, Tmp2);
3113 Tmp1 = LegalizeOp(Tmp1);
3114 Tmp2 = LegalizeOp(Tmp2);
3115 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3116 Result = LegalizeOp(Result);
3119 case TargetLowering::Expand:
3120 // Expand a setcc node into a select_cc of the same condition, lhs, and
3121 // rhs that selects between const 1 (true) and const 0 (false).
3122 MVT VT = Node->getValueType(0);
3123 Result = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3124 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3130 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3131 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3132 SDValue CC = Node->getOperand(2);
3134 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, CC);
3136 // Everything is legal, see if we should expand this op or something.
3137 switch (TLI.getOperationAction(ISD::VSETCC, Tmp1.getValueType())) {
3138 default: assert(0 && "This action is not supported yet!");
3139 case TargetLowering::Legal: break;
3140 case TargetLowering::Custom:
3141 Tmp1 = TLI.LowerOperation(Result, DAG);
3142 if (Tmp1.getNode()) Result = Tmp1;
3144 case TargetLowering::Expand: {
3145 // Unroll into a nasty set of scalar code for now.
3146 MVT VT = Node->getValueType(0);
3147 unsigned NumElems = VT.getVectorNumElements();
3148 MVT EltVT = VT.getVectorElementType();
3149 MVT TmpEltVT = Tmp1.getValueType().getVectorElementType();
3150 SmallVector<SDValue, 8> Ops(NumElems);
3151 for (unsigned i = 0; i < NumElems; ++i) {
3152 SDValue In1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT,
3153 Tmp1, DAG.getIntPtrConstant(i));
3154 Ops[i] = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(TmpEltVT),
3155 In1, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3157 DAG.getIntPtrConstant(i)),
3159 Ops[i] = DAG.getNode(ISD::SELECT, dl, EltVT, Ops[i], DAG.getConstant(
3160 APInt::getAllOnesValue(EltVT.getSizeInBits()),
3161 EltVT), DAG.getConstant(0, EltVT));
3163 Result = DAG.getBUILD_VECTOR(VT, dl, &Ops[0], NumElems);
3170 case ISD::SHL_PARTS:
3171 case ISD::SRA_PARTS:
3172 case ISD::SRL_PARTS: {
3173 SmallVector<SDValue, 8> Ops;
3174 bool Changed = false;
3175 unsigned N = Node->getNumOperands();
3176 for (unsigned i = 0; i + 1 < N; ++i) {
3177 Ops.push_back(LegalizeOp(Node->getOperand(i)));
3178 Changed |= Ops.back() != Node->getOperand(i);
3180 Ops.push_back(LegalizeOp(DAG.getShiftAmountOperand(Node->getOperand(N-1))));
3181 Changed |= Ops.back() != Node->getOperand(N-1);
3183 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
3185 switch (TLI.getOperationAction(Node->getOpcode(),
3186 Node->getValueType(0))) {
3187 default: assert(0 && "This action is not supported yet!");
3188 case TargetLowering::Legal: break;
3189 case TargetLowering::Custom:
3190 Tmp1 = TLI.LowerOperation(Result, DAG);
3191 if (Tmp1.getNode()) {
3192 SDValue Tmp2, RetVal(0, 0);
3193 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
3194 Tmp2 = LegalizeOp(Tmp1.getValue(i));
3195 AddLegalizedOperand(SDValue(Node, i), Tmp2);
3196 if (i == Op.getResNo())
3199 assert(RetVal.getNode() && "Illegal result number");
3205 // Since these produce multiple values, make sure to remember that we
3206 // legalized all of them.
3207 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
3208 AddLegalizedOperand(SDValue(Node, i), Result.getValue(i));
3209 return Result.getValue(Op.getResNo());
3231 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3232 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3234 if ((Node->getOpcode() == ISD::SHL ||
3235 Node->getOpcode() == ISD::SRL ||
3236 Node->getOpcode() == ISD::SRA) &&
3237 !Node->getValueType(0).isVector())
3238 Tmp2 = DAG.getShiftAmountOperand(Tmp2);
3240 switch (getTypeAction(Tmp2.getValueType())) {
3241 case Expand: assert(0 && "Not possible");
3243 Tmp2 = LegalizeOp(Tmp2); // Legalize the RHS.
3246 Tmp2 = PromoteOp(Tmp2); // Promote the RHS.
3250 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3252 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3253 default: assert(0 && "BinOp legalize operation not supported");
3254 case TargetLowering::Legal: break;
3255 case TargetLowering::Custom:
3256 Tmp1 = TLI.LowerOperation(Result, DAG);
3257 if (Tmp1.getNode()) {
3261 // Fall through if the custom lower can't deal with the operation
3262 case TargetLowering::Expand: {
3263 MVT VT = Op.getValueType();
3265 // See if multiply or divide can be lowered using two-result operations.
3266 SDVTList VTs = DAG.getVTList(VT, VT);
3267 if (Node->getOpcode() == ISD::MUL) {
3268 // We just need the low half of the multiply; try both the signed
3269 // and unsigned forms. If the target supports both SMUL_LOHI and
3270 // UMUL_LOHI, form a preference by checking which forms of plain
3271 // MULH it supports.
3272 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3273 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3274 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3275 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3276 unsigned OpToUse = 0;
3277 if (HasSMUL_LOHI && !HasMULHS) {
3278 OpToUse = ISD::SMUL_LOHI;
3279 } else if (HasUMUL_LOHI && !HasMULHU) {
3280 OpToUse = ISD::UMUL_LOHI;
3281 } else if (HasSMUL_LOHI) {
3282 OpToUse = ISD::SMUL_LOHI;
3283 } else if (HasUMUL_LOHI) {
3284 OpToUse = ISD::UMUL_LOHI;
3287 Result = SDValue(DAG.getNode(OpToUse, dl, VTs, Tmp1, Tmp2).getNode(),
3292 if (Node->getOpcode() == ISD::MULHS &&
3293 TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) {
3294 Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl,
3295 VTs, Tmp1, Tmp2).getNode(),
3299 if (Node->getOpcode() == ISD::MULHU &&
3300 TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) {
3301 Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl,
3302 VTs, Tmp1, Tmp2).getNode(),
3306 if (Node->getOpcode() == ISD::SDIV &&
3307 TLI.isOperationLegalOrCustom(ISD::SDIVREM, VT)) {
3308 Result = SDValue(DAG.getNode(ISD::SDIVREM, dl,
3309 VTs, Tmp1, Tmp2).getNode(),
3313 if (Node->getOpcode() == ISD::UDIV &&
3314 TLI.isOperationLegalOrCustom(ISD::UDIVREM, VT)) {
3315 Result = SDValue(DAG.getNode(ISD::UDIVREM, dl,
3316 VTs, Tmp1, Tmp2).getNode(),
3321 // Check to see if we have a libcall for this operator.
3322 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3323 bool isSigned = false;
3324 switch (Node->getOpcode()) {
3327 if (VT == MVT::i32) {
3328 LC = Node->getOpcode() == ISD::UDIV
3329 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
3330 isSigned = Node->getOpcode() == ISD::SDIV;
3335 LC = RTLIB::MUL_I32;
3336 else if (VT == MVT::i64)
3337 LC = RTLIB::MUL_I64;
3340 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
3341 RTLIB::POW_PPCF128);
3344 LC = GetFPLibCall(VT, RTLIB::DIV_F32, RTLIB::DIV_F64, RTLIB::DIV_F80,
3345 RTLIB::DIV_PPCF128);
3349 if (LC != RTLIB::UNKNOWN_LIBCALL) {
3351 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3355 assert(Node->getValueType(0).isVector() &&
3356 "Cannot expand this binary operator!");
3357 // Expand the operation into a bunch of nasty scalar code.
3358 Result = LegalizeOp(UnrollVectorOp(Op));
3361 case TargetLowering::Promote: {
3362 switch (Node->getOpcode()) {
3363 default: assert(0 && "Do not know how to promote this BinOp!");
3367 MVT OVT = Node->getValueType(0);
3368 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3369 assert(OVT.isVector() && "Cannot promote this BinOp!");
3370 // Bit convert each of the values to the new type.
3371 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp1);
3372 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp2);
3373 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3374 // Bit convert the result back the original type.
3375 Result = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Result);
3383 case ISD::SMUL_LOHI:
3384 case ISD::UMUL_LOHI:
3387 // These nodes will only be produced by target-specific lowering, so
3388 // they shouldn't be here if they aren't legal.
3389 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
3390 "This must be legal!");
3392 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3393 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3394 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3397 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
3398 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3399 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3400 case Expand: assert(0 && "Not possible");
3402 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3405 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3409 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3411 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3412 default: assert(0 && "Operation not supported");
3413 case TargetLowering::Custom:
3414 Tmp1 = TLI.LowerOperation(Result, DAG);
3415 if (Tmp1.getNode()) Result = Tmp1;
3417 case TargetLowering::Legal: break;
3418 case TargetLowering::Expand: {
3419 // If this target supports fabs/fneg natively and select is cheap,
3420 // do this efficiently.
3421 if (!TLI.isSelectExpensive() &&
3422 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
3423 TargetLowering::Legal &&
3424 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
3425 TargetLowering::Legal) {
3426 // Get the sign bit of the RHS.
3428 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
3429 SDValue SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, IVT, Tmp2);
3430 SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(IVT),
3431 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
3432 // Get the absolute value of the result.
3433 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
3434 // Select between the nabs and abs value based on the sign bit of
3436 Result = DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit,
3437 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(),
3440 Result = LegalizeOp(Result);
3444 // Otherwise, do bitwise ops!
3446 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
3447 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
3448 Result = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0), Result);
3449 Result = LegalizeOp(Result);
3457 Tmp1 = LegalizeOp(Node->getOperand(0));
3458 Tmp2 = LegalizeOp(Node->getOperand(1));
3459 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3460 Tmp3 = Result.getValue(0);
3461 Tmp4 = Result.getValue(1);
3463 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3464 default: assert(0 && "This action is not supported yet!");
3465 case TargetLowering::Legal:
3467 case TargetLowering::Custom:
3468 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
3469 if (Tmp1.getNode() != NULL) {
3470 Tmp3 = LegalizeOp(Tmp1);
3471 Tmp4 = LegalizeOp(Tmp1.getValue(1));
3475 // Since this produces two values, make sure to remember that we legalized
3477 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
3478 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
3479 return Op.getResNo() ? Tmp4 : Tmp3;
3483 Tmp1 = LegalizeOp(Node->getOperand(0));
3484 Tmp2 = LegalizeOp(Node->getOperand(1));
3485 Tmp3 = LegalizeOp(Node->getOperand(2));
3486 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3487 Tmp3 = Result.getValue(0);
3488 Tmp4 = Result.getValue(1);
3490 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3491 default: assert(0 && "This action is not supported yet!");
3492 case TargetLowering::Legal:
3494 case TargetLowering::Custom:
3495 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
3496 if (Tmp1.getNode() != NULL) {
3497 Tmp3 = LegalizeOp(Tmp1);
3498 Tmp4 = LegalizeOp(Tmp1.getValue(1));
3502 // Since this produces two values, make sure to remember that we legalized
3504 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
3505 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
3506 return Op.getResNo() ? Tmp4 : Tmp3;
3508 case ISD::BUILD_PAIR: {
3509 MVT PairTy = Node->getValueType(0);
3510 // TODO: handle the case where the Lo and Hi operands are not of legal type
3511 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
3512 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
3513 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
3514 case TargetLowering::Promote:
3515 case TargetLowering::Custom:
3516 assert(0 && "Cannot promote/custom this yet!");
3517 case TargetLowering::Legal:
3518 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
3519 Result = DAG.getNode(ISD::BUILD_PAIR, dl, PairTy, Tmp1, Tmp2);
3521 case TargetLowering::Expand:
3522 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Tmp1);
3523 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Tmp2);
3524 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
3525 DAG.getConstant(PairTy.getSizeInBits()/2,
3526 TLI.getShiftAmountTy()));
3527 Result = DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2);
3536 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3537 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3539 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3540 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
3541 case TargetLowering::Custom:
3544 case TargetLowering::Legal:
3545 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3547 Tmp1 = TLI.LowerOperation(Result, DAG);
3548 if (Tmp1.getNode()) Result = Tmp1;
3551 case TargetLowering::Expand: {
3552 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
3553 bool isSigned = DivOpc == ISD::SDIV;
3554 MVT VT = Node->getValueType(0);
3556 // See if remainder can be lowered using two-result operations.
3557 SDVTList VTs = DAG.getVTList(VT, VT);
3558 if (Node->getOpcode() == ISD::SREM &&
3559 TLI.isOperationLegalOrCustom(ISD::SDIVREM, VT)) {
3560 Result = SDValue(DAG.getNode(ISD::SDIVREM, dl,
3561 VTs, Tmp1, Tmp2).getNode(), 1);
3564 if (Node->getOpcode() == ISD::UREM &&
3565 TLI.isOperationLegalOrCustom(ISD::UDIVREM, VT)) {
3566 Result = SDValue(DAG.getNode(ISD::UDIVREM, dl,
3567 VTs, Tmp1, Tmp2).getNode(), 1);
3571 if (VT.isInteger()) {
3572 if (TLI.getOperationAction(DivOpc, VT) ==
3573 TargetLowering::Legal) {
3575 Result = DAG.getNode(DivOpc, dl, VT, Tmp1, Tmp2);
3576 Result = DAG.getNode(ISD::MUL, dl, VT, Result, Tmp2);
3577 Result = DAG.getNode(ISD::SUB, dl, VT, Tmp1, Result);
3578 } else if (VT.isVector()) {
3579 Result = LegalizeOp(UnrollVectorOp(Op));
3581 assert(VT == MVT::i32 &&
3582 "Cannot expand this binary operator!");
3583 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
3584 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
3586 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3589 assert(VT.isFloatingPoint() &&
3590 "remainder op must have integer or floating-point type");
3591 if (VT.isVector()) {
3592 Result = LegalizeOp(UnrollVectorOp(Op));
3594 // Floating point mod -> fmod libcall.
3595 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
3596 RTLIB::REM_F80, RTLIB::REM_PPCF128);
3598 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3606 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3607 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3609 MVT VT = Node->getValueType(0);
3610 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
3611 default: assert(0 && "This action is not supported yet!");
3612 case TargetLowering::Custom:
3615 case TargetLowering::Legal:
3616 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3617 Result = Result.getValue(0);
3618 Tmp1 = Result.getValue(1);
3621 Tmp2 = TLI.LowerOperation(Result, DAG);
3622 if (Tmp2.getNode()) {
3623 Result = LegalizeOp(Tmp2);
3624 Tmp1 = LegalizeOp(Tmp2.getValue(1));
3628 case TargetLowering::Expand: {
3629 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3630 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0);
3631 // Increment the pointer, VAList, to the next vaarg
3632 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
3633 DAG.getConstant(TLI.getTargetData()->
3634 getTypePaddedSize(VT.getTypeForMVT()),
3635 TLI.getPointerTy()));
3636 // Store the incremented VAList to the legalized pointer
3637 Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0);
3638 // Load the actual argument out of the pointer VAList
3639 Result = DAG.getLoad(VT, dl, Tmp3, VAList, NULL, 0);
3640 Tmp1 = LegalizeOp(Result.getValue(1));
3641 Result = LegalizeOp(Result);
3645 // Since VAARG produces two values, make sure to remember that we
3646 // legalized both of them.
3647 AddLegalizedOperand(SDValue(Node, 0), Result);
3648 AddLegalizedOperand(SDValue(Node, 1), Tmp1);
3649 return Op.getResNo() ? Tmp1 : Result;
3653 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3654 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
3655 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
3657 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
3658 default: assert(0 && "This action is not supported yet!");
3659 case TargetLowering::Custom:
3662 case TargetLowering::Legal:
3663 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
3664 Node->getOperand(3), Node->getOperand(4));
3666 Tmp1 = TLI.LowerOperation(Result, DAG);
3667 if (Tmp1.getNode()) Result = Tmp1;
3670 case TargetLowering::Expand:
3671 // This defaults to loading a pointer from the input and storing it to the
3672 // output, returning the chain.
3673 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3674 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3675 Tmp4 = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp3, VS, 0);
3676 Result = DAG.getStore(Tmp4.getValue(1), dl, Tmp4, Tmp2, VD, 0);
3682 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3683 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3685 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
3686 default: assert(0 && "This action is not supported yet!");
3687 case TargetLowering::Custom:
3690 case TargetLowering::Legal:
3691 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3693 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
3694 if (Tmp1.getNode()) Result = Tmp1;
3697 case TargetLowering::Expand:
3698 Result = Tmp1; // Default to a no-op, return the chain
3704 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3705 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3707 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3709 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
3710 default: assert(0 && "This action is not supported yet!");
3711 case TargetLowering::Legal: break;
3712 case TargetLowering::Custom:
3713 Tmp1 = TLI.LowerOperation(Result, DAG);
3714 if (Tmp1.getNode()) Result = Tmp1;
3721 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3722 Tmp2 = LegalizeOp(DAG.getShiftAmountOperand(Node->getOperand(1))); // RHS
3723 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3724 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3726 assert(0 && "ROTL/ROTR legalize operation not supported");
3728 case TargetLowering::Legal:
3730 case TargetLowering::Custom:
3731 Tmp1 = TLI.LowerOperation(Result, DAG);
3732 if (Tmp1.getNode()) Result = Tmp1;
3734 case TargetLowering::Promote:
3735 assert(0 && "Do not know how to promote ROTL/ROTR");
3737 case TargetLowering::Expand:
3738 assert(0 && "Do not know how to expand ROTL/ROTR");
3744 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3745 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3746 case TargetLowering::Custom:
3747 assert(0 && "Cannot custom legalize this yet!");
3748 case TargetLowering::Legal:
3749 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3751 case TargetLowering::Promote: {
3752 MVT OVT = Tmp1.getValueType();
3753 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3754 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3756 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1);
3757 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
3758 Result = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
3759 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3762 case TargetLowering::Expand:
3763 Result = ExpandBSWAP(Tmp1, dl);
3771 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3772 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3773 case TargetLowering::Custom:
3774 case TargetLowering::Legal:
3775 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3776 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3777 TargetLowering::Custom) {
3778 Tmp1 = TLI.LowerOperation(Result, DAG);
3779 if (Tmp1.getNode()) {
3784 case TargetLowering::Promote: {
3785 MVT OVT = Tmp1.getValueType();
3786 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3788 // Zero extend the argument.
3789 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1);
3790 // Perform the larger operation, then subtract if needed.
3791 Tmp1 = DAG.getNode(Node->getOpcode(), dl, Node->getValueType(0), Tmp1);
3792 switch (Node->getOpcode()) {
3797 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3798 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
3799 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
3801 Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
3802 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3805 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3806 Result = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
3807 DAG.getConstant(NVT.getSizeInBits() -
3808 OVT.getSizeInBits(), NVT));
3813 case TargetLowering::Expand:
3814 Result = ExpandBitCount(Node->getOpcode(), Tmp1, dl);
3834 case ISD::FNEARBYINT:
3835 Tmp1 = LegalizeOp(Node->getOperand(0));
3836 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3837 case TargetLowering::Promote:
3838 case TargetLowering::Custom:
3841 case TargetLowering::Legal:
3842 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3844 Tmp1 = TLI.LowerOperation(Result, DAG);
3845 if (Tmp1.getNode()) Result = Tmp1;
3848 case TargetLowering::Expand:
3849 switch (Node->getOpcode()) {
3850 default: assert(0 && "Unreachable!");
3852 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3853 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3854 Result = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp2, Tmp1);
3857 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3858 MVT VT = Node->getValueType(0);
3859 Tmp2 = DAG.getConstantFP(0.0, VT);
3860 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
3861 Tmp1, Tmp2, ISD::SETUGT);
3862 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
3863 Result = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3);
3878 case ISD::FNEARBYINT: {
3879 MVT VT = Node->getValueType(0);
3881 // Expand unsupported unary vector operators by unrolling them.
3882 if (VT.isVector()) {
3883 Result = LegalizeOp(UnrollVectorOp(Op));
3887 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3888 switch(Node->getOpcode()) {
3890 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3891 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
3894 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
3895 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
3898 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
3899 RTLIB::COS_F80, RTLIB::COS_PPCF128);
3902 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
3903 RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
3906 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3907 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
3910 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3911 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
3914 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
3915 RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
3918 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3919 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
3922 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3923 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
3926 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3927 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128);
3930 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3931 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128);
3934 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64,
3935 RTLIB::RINT_F80, RTLIB::RINT_PPCF128);
3937 case ISD::FNEARBYINT:
3938 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
3939 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
3942 default: assert(0 && "Unreachable!");
3945 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3953 MVT VT = Node->getValueType(0);
3955 // Expand unsupported unary vector operators by unrolling them.
3956 if (VT.isVector()) {
3957 Result = LegalizeOp(UnrollVectorOp(Op));
3961 // We always lower FPOWI into a libcall. No target support for it yet.
3962 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
3963 RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
3965 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3968 case ISD::BIT_CONVERT:
3969 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3970 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3971 Node->getValueType(0), dl);
3972 } else if (Op.getOperand(0).getValueType().isVector()) {
3973 // The input has to be a vector type, we have to either scalarize it, pack
3974 // it, or convert it based on whether the input vector type is legal.
3975 SDNode *InVal = Node->getOperand(0).getNode();
3976 int InIx = Node->getOperand(0).getResNo();
3977 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
3978 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
3980 // Figure out if there is a simple type corresponding to this Vector
3981 // type. If so, convert to the vector type.
3982 MVT TVT = MVT::getVectorVT(EVT, NumElems);
3983 if (TLI.isTypeLegal(TVT)) {
3984 // Turn this into a bit convert of the vector input.
3985 Result = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0),
3986 LegalizeOp(Node->getOperand(0)));
3988 } else if (NumElems == 1) {
3989 // Turn this into a bit convert of the scalar input.
3990 Result = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0),
3991 ScalarizeVectorOp(Node->getOperand(0)));
3994 // FIXME: UNIMP! Store then reload
3995 assert(0 && "Cast from unsupported vector type not implemented yet!");
3998 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3999 Node->getOperand(0).getValueType())) {
4000 default: assert(0 && "Unknown operation action!");
4001 case TargetLowering::Expand:
4002 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
4003 Node->getValueType(0), dl);
4005 case TargetLowering::Legal:
4006 Tmp1 = LegalizeOp(Node->getOperand(0));
4007 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4012 case ISD::CONVERT_RNDSAT: {
4013 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
4015 default: assert(0 && "Unknown cvt code!");
4026 SDValue DTyOp = Node->getOperand(1);
4027 SDValue STyOp = Node->getOperand(2);
4028 SDValue RndOp = Node->getOperand(3);
4029 SDValue SatOp = Node->getOperand(4);
4030 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4031 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4033 Tmp1 = LegalizeOp(Node->getOperand(0));
4034 Result = DAG.UpdateNodeOperands(Result, Tmp1, DTyOp, STyOp,
4036 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
4037 TargetLowering::Custom) {
4038 Tmp1 = TLI.LowerOperation(Result, DAG);
4039 if (Tmp1.getNode()) Result = Tmp1;
4043 Result = PromoteOp(Node->getOperand(0));
4044 // For FP, make Op1 a i32
4046 Result = DAG.getConvertRndSat(Op.getValueType(), dl, Result,
4047 DTyOp, STyOp, RndOp, SatOp, CvtCode);
4052 } // end switch CvtCode
4055 // Conversion operators. The source and destination have different types.
4056 case ISD::SINT_TO_FP:
4057 case ISD::UINT_TO_FP: {
4058 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
4059 Result = LegalizeINT_TO_FP(Result, isSigned,
4060 Node->getValueType(0), Node->getOperand(0), dl);
4064 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4066 Tmp1 = LegalizeOp(Node->getOperand(0));
4067 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
4068 default: assert(0 && "Unknown TRUNCATE legalization operation action!");
4069 case TargetLowering::Custom:
4072 case TargetLowering::Legal:
4073 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4075 Tmp1 = TLI.LowerOperation(Result, DAG);
4076 if (Tmp1.getNode()) Result = Tmp1;
4079 case TargetLowering::Expand:
4080 assert(Result.getValueType().isVector() && "must be vector type");
4081 // Unroll the truncate. We should do better.
4082 Result = LegalizeOp(UnrollVectorOp(Result));
4086 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4088 // Since the result is legal, we should just be able to truncate the low
4089 // part of the source.
4090 Result = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
4093 Result = PromoteOp(Node->getOperand(0));
4094 Result = DAG.getNode(ISD::TRUNCATE, dl, Op.getValueType(), Result);
4099 case ISD::FP_TO_SINT:
4100 case ISD::FP_TO_UINT:
4101 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4103 Tmp1 = LegalizeOp(Node->getOperand(0));
4105 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
4106 default: assert(0 && "Unknown operation action!");
4107 case TargetLowering::Custom:
4110 case TargetLowering::Legal:
4111 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4113 Tmp1 = TLI.LowerOperation(Result, DAG);
4114 if (Tmp1.getNode()) Result = Tmp1;
4117 case TargetLowering::Promote:
4118 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
4119 Node->getOpcode() == ISD::FP_TO_SINT,
4122 case TargetLowering::Expand:
4123 if (Node->getOpcode() == ISD::FP_TO_UINT) {
4124 SDValue True, False;
4125 MVT VT = Node->getOperand(0).getValueType();
4126 MVT NVT = Node->getValueType(0);
4127 const uint64_t zero[] = {0, 0};
4128 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero));
4129 APInt x = APInt::getSignBit(NVT.getSizeInBits());
4130 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
4131 Tmp2 = DAG.getConstantFP(apf, VT);
4132 Tmp3 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
4133 Node->getOperand(0),
4135 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
4136 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
4137 DAG.getNode(ISD::FSUB, dl, VT,
4138 Node->getOperand(0), Tmp2));
4139 False = DAG.getNode(ISD::XOR, dl, NVT, False,
4140 DAG.getConstant(x, NVT));
4141 Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp3, True, False);
4144 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
4150 MVT VT = Op.getValueType();
4151 MVT OVT = Node->getOperand(0).getValueType();
4152 // Convert ppcf128 to i32
4153 if (OVT == MVT::ppcf128 && VT == MVT::i32) {
4154 if (Node->getOpcode() == ISD::FP_TO_SINT) {
4155 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, MVT::ppcf128,
4156 Node->getOperand(0), DAG.getValueType(MVT::f64));
4157 Result = DAG.getNode(ISD::FP_ROUND, dl, MVT::f64, Result,
4158 DAG.getIntPtrConstant(1));
4159 Result = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Result);
4161 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
4162 APFloat apf = APFloat(APInt(128, 2, TwoE31));
4163 Tmp2 = DAG.getConstantFP(apf, OVT);
4164 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
4165 // FIXME: generated code sucks.
4166 Result = DAG.getNode(ISD::SELECT_CC, dl, VT, Node->getOperand(0),
4168 DAG.getNode(ISD::ADD, dl, MVT::i32,
4169 DAG.getNode(ISD::FP_TO_SINT, dl, VT,
4170 DAG.getNode(ISD::FSUB, dl, OVT,
4171 Node->getOperand(0), Tmp2)),
4172 DAG.getConstant(0x80000000, MVT::i32)),
4173 DAG.getNode(ISD::FP_TO_SINT, dl, VT,
4174 Node->getOperand(0)),
4175 DAG.getCondCode(ISD::SETGE));
4179 // Convert f32 / f64 to i32 / i64 / i128.
4180 RTLIB::Libcall LC = (Node->getOpcode() == ISD::FP_TO_SINT) ?
4181 RTLIB::getFPTOSINT(OVT, VT) : RTLIB::getFPTOUINT(OVT, VT);
4182 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpectd fp-to-int conversion!");
4184 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
4188 Tmp1 = PromoteOp(Node->getOperand(0));
4189 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
4190 Result = LegalizeOp(Result);
4195 case ISD::FP_EXTEND: {
4196 MVT DstVT = Op.getValueType();
4197 MVT SrcVT = Op.getOperand(0).getValueType();
4198 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
4199 // The only other way we can lower this is to turn it into a STORE,
4200 // LOAD pair, targetting a temporary location (a stack slot).
4201 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT, dl);
4204 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4205 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4207 Tmp1 = LegalizeOp(Node->getOperand(0));
4208 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4211 Tmp1 = PromoteOp(Node->getOperand(0));
4212 Result = DAG.getNode(ISD::FP_EXTEND, dl, Op.getValueType(), Tmp1);
4217 case ISD::FP_ROUND: {
4218 MVT DstVT = Op.getValueType();
4219 MVT SrcVT = Op.getOperand(0).getValueType();
4220 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
4221 if (SrcVT == MVT::ppcf128) {
4223 ExpandOp(Node->getOperand(0), Lo, Result);
4224 // Round it the rest of the way (e.g. to f32) if needed.
4225 if (DstVT!=MVT::f64)
4226 Result = DAG.getNode(ISD::FP_ROUND, dl,
4227 DstVT, Result, Op.getOperand(1));
4230 // The only other way we can lower this is to turn it into a STORE,
4231 // LOAD pair, targetting a temporary location (a stack slot).
4232 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT, dl);
4235 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4236 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4238 Tmp1 = LegalizeOp(Node->getOperand(0));
4239 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
4242 Tmp1 = PromoteOp(Node->getOperand(0));
4243 Result = DAG.getNode(ISD::FP_ROUND, dl, Op.getValueType(), Tmp1,
4244 Node->getOperand(1));
4249 case ISD::ANY_EXTEND:
4250 case ISD::ZERO_EXTEND:
4251 case ISD::SIGN_EXTEND:
4252 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4253 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4255 Tmp1 = LegalizeOp(Node->getOperand(0));
4256 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4257 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
4258 TargetLowering::Custom) {
4259 Tmp1 = TLI.LowerOperation(Result, DAG);
4260 if (Tmp1.getNode()) Result = Tmp1;
4264 switch (Node->getOpcode()) {
4265 case ISD::ANY_EXTEND:
4266 Tmp1 = PromoteOp(Node->getOperand(0));
4267 Result = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), Tmp1);
4269 case ISD::ZERO_EXTEND:
4270 Result = PromoteOp(Node->getOperand(0));
4271 Result = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), Result);
4272 Result = DAG.getZeroExtendInReg(Result, dl,
4273 Node->getOperand(0).getValueType());
4275 case ISD::SIGN_EXTEND:
4276 Result = PromoteOp(Node->getOperand(0));
4277 Result = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), Result);
4278 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Result.getValueType(),
4280 DAG.getValueType(Node->getOperand(0).getValueType()));
4285 case ISD::FP_ROUND_INREG:
4286 case ISD::SIGN_EXTEND_INREG: {
4287 Tmp1 = LegalizeOp(Node->getOperand(0));
4288 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
4290 // If this operation is not supported, convert it to a shl/shr or load/store
4292 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
4293 default: assert(0 && "This action not supported for this op yet!");
4294 case TargetLowering::Legal:
4295 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
4297 case TargetLowering::Expand:
4298 // If this is an integer extend and shifts are supported, do that.
4299 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
4300 // NOTE: we could fall back on load/store here too for targets without
4301 // SAR. However, it is doubtful that any exist.
4302 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() -
4303 ExtraVT.getSizeInBits();
4304 SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
4305 Result = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
4306 Node->getOperand(0), ShiftCst);
4307 Result = DAG.getNode(ISD::SRA, dl, Node->getValueType(0),
4309 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
4310 // The only way we can lower this is to turn it into a TRUNCSTORE,
4311 // EXTLOAD pair, targetting a temporary location (a stack slot).
4313 // NOTE: there is a choice here between constantly creating new stack
4314 // slots and always reusing the same one. We currently always create
4315 // new ones, as reuse may inhibit scheduling.
4316 Result = EmitStackConvert(Node->getOperand(0), ExtraVT,
4317 Node->getValueType(0), dl);
4319 assert(0 && "Unknown op");
4325 case ISD::TRAMPOLINE: {
4327 for (unsigned i = 0; i != 6; ++i)
4328 Ops[i] = LegalizeOp(Node->getOperand(i));
4329 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
4330 // The only option for this node is to custom lower it.
4331 Result = TLI.LowerOperation(Result, DAG);
4332 assert(Result.getNode() && "Should always custom lower!");
4334 // Since trampoline produces two values, make sure to remember that we
4335 // legalized both of them.
4336 Tmp1 = LegalizeOp(Result.getValue(1));
4337 Result = LegalizeOp(Result);
4338 AddLegalizedOperand(SDValue(Node, 0), Result);
4339 AddLegalizedOperand(SDValue(Node, 1), Tmp1);
4340 return Op.getResNo() ? Tmp1 : Result;
4342 case ISD::FLT_ROUNDS_: {
4343 MVT VT = Node->getValueType(0);
4344 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4345 default: assert(0 && "This action not supported for this op yet!");
4346 case TargetLowering::Custom:
4347 Result = TLI.LowerOperation(Op, DAG);
4348 if (Result.getNode()) break;
4350 case TargetLowering::Legal:
4351 // If this operation is not supported, lower it to constant 1
4352 Result = DAG.getConstant(1, VT);
4358 MVT VT = Node->getValueType(0);
4359 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4360 default: assert(0 && "This action not supported for this op yet!");
4361 case TargetLowering::Legal:
4362 Tmp1 = LegalizeOp(Node->getOperand(0));
4363 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4365 case TargetLowering::Custom:
4366 Result = TLI.LowerOperation(Op, DAG);
4367 if (Result.getNode()) break;
4369 case TargetLowering::Expand:
4370 // If this operation is not supported, lower it to 'abort()' call
4371 Tmp1 = LegalizeOp(Node->getOperand(0));
4372 TargetLowering::ArgListTy Args;
4373 std::pair<SDValue,SDValue> CallResult =
4374 TLI.LowerCallTo(Tmp1, Type::VoidTy,
4375 false, false, false, false, CallingConv::C, false,
4376 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
4378 Result = CallResult.second;
4386 MVT VT = Node->getValueType(0);
4387 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4388 default: assert(0 && "This action not supported for this op yet!");
4389 case TargetLowering::Custom:
4390 Result = TLI.LowerOperation(Op, DAG);
4391 if (Result.getNode()) break;
4393 case TargetLowering::Legal: {
4394 SDValue LHS = LegalizeOp(Node->getOperand(0));
4395 SDValue RHS = LegalizeOp(Node->getOperand(1));
4397 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
4398 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
4400 MVT OType = Node->getValueType(1);
4402 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
4404 // LHSSign -> LHS >= 0
4405 // RHSSign -> RHS >= 0
4406 // SumSign -> Sum >= 0
4409 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
4411 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
4413 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
4414 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
4415 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
4416 Node->getOpcode() == ISD::SADDO ?
4417 ISD::SETEQ : ISD::SETNE);
4419 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
4420 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
4422 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
4424 MVT ValueVTs[] = { LHS.getValueType(), OType };
4425 SDValue Ops[] = { Sum, Cmp };
4427 Result = DAG.getNode(ISD::MERGE_VALUES, dl,
4428 DAG.getVTList(&ValueVTs[0], 2),
4430 SDNode *RNode = Result.getNode();
4431 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), SDValue(RNode, 0));
4432 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), SDValue(RNode, 1));
4441 MVT VT = Node->getValueType(0);
4442 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4443 default: assert(0 && "This action not supported for this op yet!");
4444 case TargetLowering::Custom:
4445 Result = TLI.LowerOperation(Op, DAG);
4446 if (Result.getNode()) break;
4448 case TargetLowering::Legal: {
4449 SDValue LHS = LegalizeOp(Node->getOperand(0));
4450 SDValue RHS = LegalizeOp(Node->getOperand(1));
4452 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
4453 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
4455 MVT OType = Node->getValueType(1);
4456 SDValue Cmp = DAG.getSetCC(dl, OType, Sum, LHS,
4457 Node->getOpcode () == ISD::UADDO ?
4458 ISD::SETULT : ISD::SETUGT);
4460 MVT ValueVTs[] = { LHS.getValueType(), OType };
4461 SDValue Ops[] = { Sum, Cmp };
4463 Result = DAG.getNode(ISD::MERGE_VALUES, dl,
4464 DAG.getVTList(&ValueVTs[0], 2),
4466 SDNode *RNode = Result.getNode();
4467 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), SDValue(RNode, 0));
4468 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), SDValue(RNode, 1));
4477 MVT VT = Node->getValueType(0);
4478 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4479 default: assert(0 && "This action is not supported at all!");
4480 case TargetLowering::Custom:
4481 Result = TLI.LowerOperation(Op, DAG);
4482 if (Result.getNode()) break;
4484 case TargetLowering::Legal:
4485 // FIXME: According to Hacker's Delight, this can be implemented in
4486 // target independent lowering, but it would be inefficient, since it
4487 // requires a division + a branch.
4488 assert(0 && "Target independent lowering is not supported for SMULO/UMULO!");
4496 assert(Result.getValueType() == Op.getValueType() &&
4497 "Bad legalization!");
4499 // Make sure that the generated code is itself legal.
4501 Result = LegalizeOp(Result);
4503 // Note that LegalizeOp may be reentered even from single-use nodes, which
4504 // means that we always must cache transformed nodes.
4505 AddLegalizedOperand(Op, Result);
4509 /// PromoteOp - Given an operation that produces a value in an invalid type,
4510 /// promote it to compute the value into a larger type. The produced value will
4511 /// have the correct bits for the low portion of the register, but no guarantee
4512 /// is made about the top bits: it may be zero, sign-extended, or garbage.
4513 SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) {
4514 MVT VT = Op.getValueType();
4515 MVT NVT = TLI.getTypeToTransformTo(VT);
4516 assert(getTypeAction(VT) == Promote &&
4517 "Caller should expand or legalize operands that are not promotable!");
4518 assert(NVT.bitsGT(VT) && NVT.isInteger() == VT.isInteger() &&
4519 "Cannot promote to smaller type!");
4521 SDValue Tmp1, Tmp2, Tmp3;
4523 SDNode *Node = Op.getNode();
4524 DebugLoc dl = Node->getDebugLoc();
4526 DenseMap<SDValue, SDValue>::iterator I = PromotedNodes.find(Op);
4527 if (I != PromotedNodes.end()) return I->second;
4529 switch (Node->getOpcode()) {
4530 case ISD::CopyFromReg:
4531 assert(0 && "CopyFromReg must be legal!");
4534 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
4536 assert(0 && "Do not know how to promote this operator!");
4539 Result = DAG.getUNDEF(NVT);
4543 Result = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, Op);
4545 Result = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Op);
4546 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
4548 case ISD::ConstantFP:
4549 Result = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Op);
4550 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
4554 MVT VT0 = Node->getOperand(0).getValueType();
4555 assert(isTypeLegal(TLI.getSetCCResultType(VT0))
4556 && "SetCC type is not legal??");
4557 Result = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(VT0),
4558 Node->getOperand(0), Node->getOperand(1),
4559 Node->getOperand(2));
4563 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4565 Result = LegalizeOp(Node->getOperand(0));
4566 assert(Result.getValueType().bitsGE(NVT) &&
4567 "This truncation doesn't make sense!");
4568 if (Result.getValueType().bitsGT(NVT)) // Truncate to NVT instead of VT
4569 Result = DAG.getNode(ISD::TRUNCATE, dl, NVT, Result);
4572 // The truncation is not required, because we don't guarantee anything
4573 // about high bits anyway.
4574 Result = PromoteOp(Node->getOperand(0));
4577 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4578 // Truncate the low part of the expanded value to the result type
4579 Result = DAG.getNode(ISD::TRUNCATE, dl, NVT, Tmp1);
4582 case ISD::SIGN_EXTEND:
4583 case ISD::ZERO_EXTEND:
4584 case ISD::ANY_EXTEND:
4585 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4586 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
4588 // Input is legal? Just do extend all the way to the larger type.
4589 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Node->getOperand(0));
4592 // Promote the reg if it's smaller.
4593 Result = PromoteOp(Node->getOperand(0));
4594 // The high bits are not guaranteed to be anything. Insert an extend.
4595 if (Node->getOpcode() == ISD::SIGN_EXTEND)
4596 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Result,
4597 DAG.getValueType(Node->getOperand(0).getValueType()));
4598 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
4599 Result = DAG.getZeroExtendInReg(Result, dl,
4600 Node->getOperand(0).getValueType());
4604 case ISD::CONVERT_RNDSAT: {
4605 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
4606 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
4607 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
4608 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
4609 "can only promote integers");
4610 Result = DAG.getConvertRndSat(NVT, dl, Node->getOperand(0),
4611 Node->getOperand(1), Node->getOperand(2),
4612 Node->getOperand(3), Node->getOperand(4),
4617 case ISD::BIT_CONVERT:
4618 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
4619 Node->getValueType(0), dl);
4620 Result = PromoteOp(Result);
4623 case ISD::FP_EXTEND:
4624 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
4626 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4627 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
4628 case Promote: assert(0 && "Unreachable with 2 FP types!");
4630 if (Node->getConstantOperandVal(1) == 0) {
4631 // Input is legal? Do an FP_ROUND_INREG.
4632 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Node->getOperand(0),
4633 DAG.getValueType(VT));
4635 // Just remove the truncate, it isn't affecting the value.
4636 Result = DAG.getNode(ISD::FP_ROUND, dl, NVT, Node->getOperand(0),
4637 Node->getOperand(1));
4642 case ISD::SINT_TO_FP:
4643 case ISD::UINT_TO_FP:
4644 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4646 // No extra round required here.
4647 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Node->getOperand(0));
4651 Result = PromoteOp(Node->getOperand(0));
4652 if (Node->getOpcode() == ISD::SINT_TO_FP)
4653 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Result.getValueType(),
4655 DAG.getValueType(Node->getOperand(0).getValueType()));
4657 Result = DAG.getZeroExtendInReg(Result, dl,
4658 Node->getOperand(0).getValueType());
4659 // No extra round required here.
4660 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Result);
4663 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
4664 Node->getOperand(0), dl);
4665 // Round if we cannot tolerate excess precision.
4666 if (NoExcessFPPrecision)
4667 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4668 DAG.getValueType(VT));
4673 case ISD::SIGN_EXTEND_INREG:
4674 Result = PromoteOp(Node->getOperand(0));
4675 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Result,
4676 Node->getOperand(1));
4678 case ISD::FP_TO_SINT:
4679 case ISD::FP_TO_UINT:
4680 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4683 Tmp1 = Node->getOperand(0);
4686 // The input result is prerounded, so we don't have to do anything
4688 Tmp1 = PromoteOp(Node->getOperand(0));
4691 // If we're promoting a UINT to a larger size, check to see if the new node
4692 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
4693 // we can use that instead. This allows us to generate better code for
4694 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
4695 // legal, such as PowerPC.
4696 if (Node->getOpcode() == ISD::FP_TO_UINT &&
4697 !TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NVT) &&
4698 (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT) ||
4699 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
4700 Result = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Tmp1);
4702 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4708 Tmp1 = PromoteOp(Node->getOperand(0));
4709 assert(Tmp1.getValueType() == NVT);
4710 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4711 // NOTE: we do not have to do any extra rounding here for
4712 // NoExcessFPPrecision, because we know the input will have the appropriate
4713 // precision, and these operations don't modify precision at all.
4728 case ISD::FNEARBYINT:
4729 Tmp1 = PromoteOp(Node->getOperand(0));
4730 assert(Tmp1.getValueType() == NVT);
4731 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4732 if (NoExcessFPPrecision)
4733 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4734 DAG.getValueType(VT));
4739 // Promote f32 pow(i) to f64 pow(i). Note that this could insert a libcall
4740 // directly as well, which may be better.
4741 Tmp1 = PromoteOp(Node->getOperand(0));
4742 Tmp2 = Node->getOperand(1);
4743 if (Node->getOpcode() == ISD::FPOW)
4744 Tmp2 = PromoteOp(Tmp2);
4745 assert(Tmp1.getValueType() == NVT);
4746 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4747 if (NoExcessFPPrecision)
4748 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4749 DAG.getValueType(VT));
4753 case ISD::ATOMIC_CMP_SWAP: {
4754 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4755 Tmp2 = PromoteOp(Node->getOperand(2));
4756 Tmp3 = PromoteOp(Node->getOperand(3));
4757 Result = DAG.getAtomic(Node->getOpcode(), dl, AtomNode->getMemoryVT(),
4758 AtomNode->getChain(),
4759 AtomNode->getBasePtr(), Tmp2, Tmp3,
4760 AtomNode->getSrcValue(),
4761 AtomNode->getAlignment());
4762 // Remember that we legalized the chain.
4763 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4766 case ISD::ATOMIC_LOAD_ADD:
4767 case ISD::ATOMIC_LOAD_SUB:
4768 case ISD::ATOMIC_LOAD_AND:
4769 case ISD::ATOMIC_LOAD_OR:
4770 case ISD::ATOMIC_LOAD_XOR:
4771 case ISD::ATOMIC_LOAD_NAND:
4772 case ISD::ATOMIC_LOAD_MIN:
4773 case ISD::ATOMIC_LOAD_MAX:
4774 case ISD::ATOMIC_LOAD_UMIN:
4775 case ISD::ATOMIC_LOAD_UMAX:
4776 case ISD::ATOMIC_SWAP: {
4777 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4778 Tmp2 = PromoteOp(Node->getOperand(2));
4779 Result = DAG.getAtomic(Node->getOpcode(), dl, AtomNode->getMemoryVT(),
4780 AtomNode->getChain(),
4781 AtomNode->getBasePtr(), Tmp2,
4782 AtomNode->getSrcValue(),
4783 AtomNode->getAlignment());
4784 // Remember that we legalized the chain.
4785 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4795 // The input may have strange things in the top bits of the registers, but
4796 // these operations don't care. They may have weird bits going out, but
4797 // that too is okay if they are integer operations.
4798 Tmp1 = PromoteOp(Node->getOperand(0));
4799 Tmp2 = PromoteOp(Node->getOperand(1));
4800 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4801 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4806 Tmp1 = PromoteOp(Node->getOperand(0));
4807 Tmp2 = PromoteOp(Node->getOperand(1));
4808 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4809 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4811 // Floating point operations will give excess precision that we may not be
4812 // able to tolerate. If we DO allow excess precision, just leave it,
4813 // otherwise excise it.
4814 // FIXME: Why would we need to round FP ops more than integer ones?
4815 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
4816 if (NoExcessFPPrecision)
4817 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4818 DAG.getValueType(VT));
4823 // These operators require that their input be sign extended.
4824 Tmp1 = PromoteOp(Node->getOperand(0));
4825 Tmp2 = PromoteOp(Node->getOperand(1));
4826 if (NVT.isInteger()) {
4827 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp1,
4828 DAG.getValueType(VT));
4829 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp2,
4830 DAG.getValueType(VT));
4832 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4834 // Perform FP_ROUND: this is probably overly pessimistic.
4835 if (NVT.isFloatingPoint() && NoExcessFPPrecision)
4836 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4837 DAG.getValueType(VT));
4841 case ISD::FCOPYSIGN:
4842 // These operators require that their input be fp extended.
4843 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4844 case Expand: assert(0 && "not implemented");
4845 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break;
4846 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break;
4848 switch (getTypeAction(Node->getOperand(1).getValueType())) {
4849 case Expand: assert(0 && "not implemented");
4850 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
4851 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
4853 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4855 // Perform FP_ROUND: this is probably overly pessimistic.
4856 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
4857 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4858 DAG.getValueType(VT));
4863 // These operators require that their input be zero extended.
4864 Tmp1 = PromoteOp(Node->getOperand(0));
4865 Tmp2 = PromoteOp(Node->getOperand(1));
4866 assert(NVT.isInteger() && "Operators don't apply to FP!");
4867 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, VT);
4868 Tmp2 = DAG.getZeroExtendInReg(Tmp2, dl, VT);
4869 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4873 Tmp1 = PromoteOp(Node->getOperand(0));
4874 Result = DAG.getNode(ISD::SHL, dl, NVT, Tmp1, Node->getOperand(1));
4877 // The input value must be properly sign extended.
4878 Tmp1 = PromoteOp(Node->getOperand(0));
4879 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp1,
4880 DAG.getValueType(VT));
4881 Result = DAG.getNode(ISD::SRA, dl, NVT, Tmp1, Node->getOperand(1));
4884 // The input value must be properly zero extended.
4885 Tmp1 = PromoteOp(Node->getOperand(0));
4886 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, VT);
4887 Result = DAG.getNode(ISD::SRL, dl, NVT, Tmp1, Node->getOperand(1));
4891 Tmp1 = Node->getOperand(0); // Get the chain.
4892 Tmp2 = Node->getOperand(1); // Get the pointer.
4893 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
4894 Tmp3 = DAG.getVAArg(VT, dl, Tmp1, Tmp2, Node->getOperand(2));
4895 Result = TLI.LowerOperation(Tmp3, DAG);
4897 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
4898 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0);
4899 // Increment the pointer, VAList, to the next vaarg
4900 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
4901 DAG.getConstant(VT.getSizeInBits()/8,
4902 TLI.getPointerTy()));
4903 // Store the incremented VAList to the legalized pointer
4904 Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0);
4905 // Load the actual argument out of the pointer VAList
4906 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, NVT, Tmp3, VAList, NULL, 0, VT);
4908 // Remember that we legalized the chain.
4909 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4913 LoadSDNode *LD = cast<LoadSDNode>(Node);
4914 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
4915 ? ISD::EXTLOAD : LD->getExtensionType();
4916 Result = DAG.getExtLoad(ExtType, dl, NVT,
4917 LD->getChain(), LD->getBasePtr(),
4918 LD->getSrcValue(), LD->getSrcValueOffset(),
4921 LD->getAlignment());
4922 // Remember that we legalized the chain.
4923 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4927 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
4928 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
4930 MVT VT2 = Tmp2.getValueType();
4931 assert(VT2 == Tmp3.getValueType()
4932 && "PromoteOp SELECT: Operands 2 and 3 ValueTypes don't match");
4933 // Ensure that the resulting node is at least the same size as the operands'
4934 // value types, because we cannot assume that TLI.getSetCCValueType() is
4936 Result = DAG.getNode(ISD::SELECT, dl, VT2, Node->getOperand(0), Tmp2, Tmp3);
4939 case ISD::SELECT_CC:
4940 Tmp2 = PromoteOp(Node->getOperand(2)); // True
4941 Tmp3 = PromoteOp(Node->getOperand(3)); // False
4942 Result = DAG.getNode(ISD::SELECT_CC, dl, NVT, Node->getOperand(0),
4943 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
4946 Tmp1 = Node->getOperand(0);
4947 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1);
4948 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
4949 Result = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
4950 DAG.getConstant(NVT.getSizeInBits() -
4952 TLI.getShiftAmountTy()));
4957 // Zero extend the argument
4958 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4959 // Perform the larger operation, then subtract if needed.
4960 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4961 switch(Node->getOpcode()) {
4966 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
4967 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()), Tmp1,
4968 DAG.getConstant(NVT.getSizeInBits(), NVT),
4970 Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
4971 DAG.getConstant(VT.getSizeInBits(), NVT), Tmp1);
4974 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4975 Result = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
4976 DAG.getConstant(NVT.getSizeInBits() -
4977 VT.getSizeInBits(), NVT));
4981 case ISD::EXTRACT_SUBVECTOR:
4982 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
4984 case ISD::EXTRACT_VECTOR_ELT:
4985 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
4989 assert(Result.getNode() && "Didn't set a result!");
4991 // Make sure the result is itself legal.
4992 Result = LegalizeOp(Result);
4994 // Remember that we promoted this!
4995 AddPromotedOperand(Op, Result);
4999 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
5000 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
5001 /// based on the vector type. The return type of this matches the element type
5002 /// of the vector, which may not be legal for the target.
5003 SDValue SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDValue Op) {
5004 // We know that operand #0 is the Vec vector. If the index is a constant
5005 // or if the invec is a supported hardware type, we can use it. Otherwise,
5006 // lower to a store then an indexed load.
5007 SDValue Vec = Op.getOperand(0);
5008 SDValue Idx = Op.getOperand(1);
5009 DebugLoc dl = Op.getDebugLoc();
5011 MVT TVT = Vec.getValueType();
5012 unsigned NumElems = TVT.getVectorNumElements();
5014 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
5015 default: assert(0 && "This action is not supported yet!");
5016 case TargetLowering::Custom: {
5017 Vec = LegalizeOp(Vec);
5018 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
5019 SDValue Tmp3 = TLI.LowerOperation(Op, DAG);
5024 case TargetLowering::Legal:
5025 if (isTypeLegal(TVT)) {
5026 Vec = LegalizeOp(Vec);
5027 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
5031 case TargetLowering::Promote:
5032 assert(TVT.isVector() && "not vector type");
5033 // fall thru to expand since vectors are by default are promote
5034 case TargetLowering::Expand:
5038 if (NumElems == 1) {
5039 // This must be an access of the only element. Return it.
5040 Op = ScalarizeVectorOp(Vec);
5041 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
5042 unsigned NumLoElts = 1 << Log2_32(NumElems-1);
5043 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
5045 SplitVectorOp(Vec, Lo, Hi);
5046 if (CIdx->getZExtValue() < NumLoElts) {
5050 Idx = DAG.getConstant(CIdx->getZExtValue() - NumLoElts,
5051 Idx.getValueType());
5054 // It's now an extract from the appropriate high or low part. Recurse.
5055 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
5056 Op = ExpandEXTRACT_VECTOR_ELT(Op);
5058 // Store the value to a temporary stack slot, then LOAD the scalar
5059 // element back out.
5060 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
5061 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0);
5063 // Add the offset to the index.
5064 unsigned EltSize = Op.getValueType().getSizeInBits()/8;
5065 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
5066 DAG.getConstant(EltSize, Idx.getValueType()));
5068 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
5069 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
5071 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
5073 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
5075 Op = DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, NULL, 0);
5080 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
5081 /// we assume the operation can be split if it is not already legal.
5082 SDValue SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDValue Op) {
5083 // We know that operand #0 is the Vec vector. For now we assume the index
5084 // is a constant and that the extracted result is a supported hardware type.
5085 SDValue Vec = Op.getOperand(0);
5086 SDValue Idx = LegalizeOp(Op.getOperand(1));
5088 unsigned NumElems = Vec.getValueType().getVectorNumElements();
5090 if (NumElems == Op.getValueType().getVectorNumElements()) {
5091 // This must be an access of the desired vector length. Return it.
5095 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
5097 SplitVectorOp(Vec, Lo, Hi);
5098 if (CIdx->getZExtValue() < NumElems/2) {
5102 Idx = DAG.getConstant(CIdx->getZExtValue() - NumElems/2,
5103 Idx.getValueType());
5106 // It's now an extract from the appropriate high or low part. Recurse.
5107 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
5108 return ExpandEXTRACT_SUBVECTOR(Op);
5111 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
5112 /// with condition CC on the current target. This usually involves legalizing
5113 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
5114 /// there may be no choice but to create a new SetCC node to represent the
5115 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
5116 /// LHS, and the SDValue returned in RHS has a nil SDNode value.
5117 void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS,
5121 SDValue Tmp1, Tmp2, Tmp3, Result;
5123 switch (getTypeAction(LHS.getValueType())) {
5125 Tmp1 = LegalizeOp(LHS); // LHS
5126 Tmp2 = LegalizeOp(RHS); // RHS
5129 Tmp1 = PromoteOp(LHS); // LHS
5130 Tmp2 = PromoteOp(RHS); // RHS
5132 // If this is an FP compare, the operands have already been extended.
5133 if (LHS.getValueType().isInteger()) {
5134 MVT VT = LHS.getValueType();
5135 MVT NVT = TLI.getTypeToTransformTo(VT);
5137 // Otherwise, we have to insert explicit sign or zero extends. Note
5138 // that we could insert sign extends for ALL conditions, but zero extend
5139 // is cheaper on many machines (an AND instead of two shifts), so prefer
5141 switch (cast<CondCodeSDNode>(CC)->get()) {
5142 default: assert(0 && "Unknown integer comparison!");
5149 // ALL of these operations will work if we either sign or zero extend
5150 // the operands (including the unsigned comparisons!). Zero extend is
5151 // usually a simpler/cheaper operation, so prefer it.
5152 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, VT);
5153 Tmp2 = DAG.getZeroExtendInReg(Tmp2, dl, VT);
5159 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp1,
5160 DAG.getValueType(VT));
5161 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp2,
5162 DAG.getValueType(VT));
5163 Tmp1 = LegalizeOp(Tmp1); // Relegalize new nodes.
5164 Tmp2 = LegalizeOp(Tmp2); // Relegalize new nodes.
5170 MVT VT = LHS.getValueType();
5171 if (VT == MVT::f32 || VT == MVT::f64) {
5172 // Expand into one or more soft-fp libcall(s).
5173 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
5174 switch (cast<CondCodeSDNode>(CC)->get()) {
5177 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
5181 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
5185 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
5189 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
5193 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
5197 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
5200 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
5203 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
5206 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
5207 switch (cast<CondCodeSDNode>(CC)->get()) {
5209 // SETONE = SETOLT | SETOGT
5210 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
5213 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
5216 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
5219 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
5222 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
5225 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
5227 default: assert(0 && "Unsupported FP setcc!");
5232 SDValue Ops[2] = { LHS, RHS };
5233 Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2, dl).getNode(),
5234 false /*sign irrelevant*/, Dummy);
5235 Tmp2 = DAG.getConstant(0, MVT::i32);
5236 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
5237 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
5238 Tmp1 = DAG.getNode(ISD::SETCC, dl,
5239 TLI.getSetCCResultType(Tmp1.getValueType()),
5241 LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2, dl).getNode(),
5242 false /*sign irrelevant*/, Dummy);
5243 Tmp2 = DAG.getNode(ISD::SETCC, dl,
5244 TLI.getSetCCResultType(LHS.getValueType()), LHS,
5245 Tmp2, DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
5246 Tmp1 = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp2);
5249 LHS = LegalizeOp(Tmp1);
5254 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
5255 ExpandOp(LHS, LHSLo, LHSHi);
5256 ExpandOp(RHS, RHSLo, RHSHi);
5257 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
5259 if (VT==MVT::ppcf128) {
5260 // FIXME: This generated code sucks. We want to generate
5261 // FCMPU crN, hi1, hi2
5263 // FCMPU crN, lo1, lo2
5264 // The following can be improved, but not that much.
5265 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
5266 LHSHi, RHSHi, ISD::SETOEQ);
5267 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()),
5268 LHSLo, RHSLo, CCCode);
5269 Tmp3 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2);
5270 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
5271 LHSHi, RHSHi, ISD::SETUNE);
5272 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
5273 LHSHi, RHSHi, CCCode);
5274 Tmp1 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2);
5275 Tmp1 = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp3);
5284 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
5285 if (RHSCST->isAllOnesValue()) {
5286 // Comparison to -1.
5287 Tmp1 = DAG.getNode(ISD::AND, dl,LHSLo.getValueType(), LHSLo, LHSHi);
5292 Tmp1 = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
5293 Tmp2 = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
5294 Tmp1 = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp2);
5295 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
5298 // If this is a comparison of the sign bit, just look at the top part.
5300 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
5301 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
5302 CST->isNullValue()) || // X < 0
5303 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
5304 CST->isAllOnesValue())) { // X > -1
5310 // FIXME: This generated code sucks.
5311 ISD::CondCode LowCC;
5313 default: assert(0 && "Unknown integer setcc!");
5315 case ISD::SETULT: LowCC = ISD::SETULT; break;
5317 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
5319 case ISD::SETULE: LowCC = ISD::SETULE; break;
5321 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
5324 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
5325 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
5326 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
5328 // NOTE: on targets without efficient SELECT of bools, we can always use
5329 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
5330 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
5331 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
5332 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
5333 if (!Tmp1.getNode())
5334 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()),
5335 LHSLo, RHSLo, LowCC);
5336 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
5337 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
5338 if (!Tmp2.getNode())
5339 Tmp2 = DAG.getNode(ISD::SETCC, dl,
5340 TLI.getSetCCResultType(LHSHi.getValueType()),
5343 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
5344 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
5345 if ((Tmp1C && Tmp1C->isNullValue()) ||
5346 (Tmp2C && Tmp2C->isNullValue() &&
5347 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
5348 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
5349 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
5350 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
5351 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
5352 // low part is known false, returns high part.
5353 // For LE / GE, if high part is known false, ignore the low part.
5354 // For LT / GT, if high part is known true, ignore the low part.
5358 Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
5359 LHSHi, RHSHi, ISD::SETEQ, false,
5360 DagCombineInfo, dl);
5361 if (!Result.getNode())
5362 Result=DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
5363 LHSHi, RHSHi, ISD::SETEQ);
5364 Result = LegalizeOp(DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(),
5365 Result, Tmp1, Tmp2));
5376 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
5377 /// condition code CC on the current target. This routine assumes LHS and rHS
5378 /// have already been legalized by LegalizeSetCCOperands. It expands SETCC with
5379 /// illegal condition code into AND / OR of multiple SETCC values.
5380 void SelectionDAGLegalize::LegalizeSetCCCondCode(MVT VT,
5381 SDValue &LHS, SDValue &RHS,
5384 MVT OpVT = LHS.getValueType();
5385 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
5386 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
5387 default: assert(0 && "Unknown condition code action!");
5388 case TargetLowering::Legal:
5391 case TargetLowering::Expand: {
5392 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
5395 default: assert(0 && "Don't know how to expand this condition!"); abort();
5396 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break;
5397 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break;
5398 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5399 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break;
5400 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5401 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5402 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5403 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5404 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5405 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5406 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5407 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5408 // FIXME: Implement more expansions.
5411 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
5412 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
5413 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
5421 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
5422 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
5423 /// a load from the stack slot to DestVT, extending it if needed.
5424 /// The resultant code need not be legal.
5425 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
5429 // Create the stack frame object.
5430 unsigned SrcAlign = TLI.getTargetData()->getPrefTypeAlignment(
5431 SrcOp.getValueType().getTypeForMVT());
5432 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
5434 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
5435 int SPFI = StackPtrFI->getIndex();
5436 const Value *SV = PseudoSourceValue::getFixedStack(SPFI);
5438 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
5439 unsigned SlotSize = SlotVT.getSizeInBits();
5440 unsigned DestSize = DestVT.getSizeInBits();
5441 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(
5442 DestVT.getTypeForMVT());
5444 // Emit a store to the stack slot. Use a truncstore if the input value is
5445 // later than DestVT.
5448 if (SrcSize > SlotSize)
5449 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
5450 SV, 0, SlotVT, false, SrcAlign);
5452 assert(SrcSize == SlotSize && "Invalid store");
5453 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
5454 SV, 0, false, SrcAlign);
5457 // Result is a load from the stack slot.
5458 if (SlotSize == DestSize)
5459 return DAG.getLoad(DestVT, dl, Store, FIPtr, SV, 0, false, DestAlign);
5461 assert(SlotSize < DestSize && "Unknown extension!");
5462 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, SV, 0, SlotVT,
5466 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
5467 DebugLoc dl = Node->getDebugLoc();
5468 // Create a vector sized/aligned stack slot, store the value to element #0,
5469 // then load the whole vector back out.
5470 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
5472 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
5473 int SPFI = StackPtrFI->getIndex();
5475 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(0),
5477 PseudoSourceValue::getFixedStack(SPFI), 0);
5478 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
5479 PseudoSourceValue::getFixedStack(SPFI), 0);
5483 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
5484 /// support the operation, but do support the resultant vector type.
5485 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
5487 // If the only non-undef value is the low element, turn this into a
5488 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
5489 unsigned NumElems = Node->getNumOperands();
5490 bool isOnlyLowElement = true;
5491 SDValue SplatValue = Node->getOperand(0);
5492 DebugLoc dl = Node->getDebugLoc();
5494 // FIXME: it would be far nicer to change this into map<SDValue,uint64_t>
5495 // and use a bitmask instead of a list of elements.
5496 std::map<SDValue, std::vector<unsigned> > Values;
5497 Values[SplatValue].push_back(0);
5498 bool isConstant = true;
5499 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
5500 SplatValue.getOpcode() != ISD::UNDEF)
5503 for (unsigned i = 1; i < NumElems; ++i) {
5504 SDValue V = Node->getOperand(i);
5505 Values[V].push_back(i);
5506 if (V.getOpcode() != ISD::UNDEF)
5507 isOnlyLowElement = false;
5508 if (SplatValue != V)
5509 SplatValue = SDValue(0,0);
5511 // If this isn't a constant element or an undef, we can't use a constant
5513 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
5514 V.getOpcode() != ISD::UNDEF)
5518 if (isOnlyLowElement) {
5519 // If the low element is an undef too, then this whole things is an undef.
5520 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
5521 return DAG.getUNDEF(Node->getValueType(0));
5522 // Otherwise, turn this into a scalar_to_vector node.
5523 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, Node->getValueType(0),
5524 Node->getOperand(0));
5527 // If all elements are constants, create a load from the constant pool.
5529 MVT VT = Node->getValueType(0);
5530 std::vector<Constant*> CV;
5531 for (unsigned i = 0, e = NumElems; i != e; ++i) {
5532 if (ConstantFPSDNode *V =
5533 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
5534 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
5535 } else if (ConstantSDNode *V =
5536 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
5537 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
5539 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
5541 Node->getOperand(0).getValueType().getTypeForMVT();
5542 CV.push_back(UndefValue::get(OpNTy));
5545 Constant *CP = ConstantVector::get(CV);
5546 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
5547 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5548 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5549 PseudoSourceValue::getConstantPool(), 0,
5553 if (SplatValue.getNode()) { // Splat of one value?
5554 // Build the shuffle constant vector: <0, 0, 0, 0>
5555 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
5556 SDValue Zero = DAG.getConstant(0, MaskVT.getVectorElementType());
5557 std::vector<SDValue> ZeroVec(NumElems, Zero);
5558 SDValue SplatMask = DAG.getBUILD_VECTOR(MaskVT, dl,
5559 &ZeroVec[0], ZeroVec.size());
5561 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
5562 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
5563 // Get the splatted value into the low element of a vector register.
5565 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5566 Node->getValueType(0), SplatValue);
5568 // Return shuffle(LowValVec, undef, <0,0,0,0>)
5569 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl,
5570 Node->getValueType(0), LowValVec,
5571 DAG.getUNDEF(Node->getValueType(0)),
5576 // If there are only two unique elements, we may be able to turn this into a
5578 if (Values.size() == 2) {
5579 // Get the two values in deterministic order.
5580 SDValue Val1 = Node->getOperand(1);
5582 std::map<SDValue, std::vector<unsigned> >::iterator MI = Values.begin();
5583 if (MI->first != Val1)
5586 Val2 = (++MI)->first;
5588 // If Val1 is an undef, make sure end ends up as Val2, to ensure that our
5589 // vector shuffle has the undef vector on the RHS.
5590 if (Val1.getOpcode() == ISD::UNDEF)
5591 std::swap(Val1, Val2);
5593 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
5594 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
5595 MVT MaskEltVT = MaskVT.getVectorElementType();
5596 std::vector<SDValue> MaskVec(NumElems);
5598 // Set elements of the shuffle mask for Val1.
5599 std::vector<unsigned> &Val1Elts = Values[Val1];
5600 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i)
5601 MaskVec[Val1Elts[i]] = DAG.getConstant(0, MaskEltVT);
5603 // Set elements of the shuffle mask for Val2.
5604 std::vector<unsigned> &Val2Elts = Values[Val2];
5605 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i)
5606 if (Val2.getOpcode() != ISD::UNDEF)
5607 MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT);
5609 MaskVec[Val2Elts[i]] = DAG.getUNDEF(MaskEltVT);
5611 SDValue ShuffleMask = DAG.getBUILD_VECTOR(MaskVT, dl,
5612 &MaskVec[0], MaskVec.size());
5614 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it.
5615 if (TLI.isOperationLegalOrCustom(ISD::SCALAR_TO_VECTOR,
5616 Node->getValueType(0)) &&
5617 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
5618 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,Node->getValueType(0), Val1);
5619 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,Node->getValueType(0), Val2);
5620 SDValue Ops[] = { Val1, Val2, ShuffleMask };
5622 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
5623 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl,Node->getValueType(0), Ops, 3);
5627 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
5628 // aligned object on the stack, store each element into it, then load
5629 // the result as a vector.
5630 MVT VT = Node->getValueType(0);
5631 // Create the stack frame object.
5632 SDValue FIPtr = DAG.CreateStackTemporary(VT);
5633 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
5634 const Value *SV = PseudoSourceValue::getFixedStack(FI);
5636 // Emit a store of each element to the stack slot.
5637 SmallVector<SDValue, 8> Stores;
5638 unsigned TypeByteSize = Node->getOperand(0).getValueType().getSizeInBits()/8;
5639 // Store (in the right endianness) the elements to memory.
5640 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5641 // Ignore undef elements.
5642 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
5644 unsigned Offset = TypeByteSize*i;
5646 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
5647 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
5649 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(i),
5654 if (!Stores.empty()) // Not all undef elements?
5655 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
5656 &Stores[0], Stores.size());
5658 StoreChain = DAG.getEntryNode();
5660 // Result is a load from the stack slot.
5661 return DAG.getLoad(VT, dl, StoreChain, FIPtr, SV, 0);
5664 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
5665 SDValue Op, SDValue Amt,
5666 SDValue &Lo, SDValue &Hi,
5668 // Expand the subcomponents.
5670 ExpandOp(Op, LHSL, LHSH);
5672 SDValue Ops[] = { LHSL, LHSH, Amt };
5673 MVT VT = LHSL.getValueType();
5674 Lo = DAG.getNode(NodeOp, dl, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
5675 Hi = Lo.getValue(1);
5679 /// ExpandShift - Try to find a clever way to expand this shift operation out to
5680 /// smaller elements. If we can't find a way that is more efficient than a
5681 /// libcall on this target, return false. Otherwise, return true with the
5682 /// low-parts expanded into Lo and Hi.
5683 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op,SDValue Amt,
5684 SDValue &Lo, SDValue &Hi,
5686 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
5687 "This is not a shift!");
5689 MVT NVT = TLI.getTypeToTransformTo(Op.getValueType());
5690 SDValue ShAmt = LegalizeOp(Amt);
5691 MVT ShTy = ShAmt.getValueType();
5692 unsigned ShBits = ShTy.getSizeInBits();
5693 unsigned VTBits = Op.getValueType().getSizeInBits();
5694 unsigned NVTBits = NVT.getSizeInBits();
5696 // Handle the case when Amt is an immediate.
5697 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.getNode())) {
5698 unsigned Cst = CN->getZExtValue();
5699 // Expand the incoming operand to be shifted, so that we have its parts
5701 ExpandOp(Op, InL, InH);
5705 Lo = DAG.getConstant(0, NVT);
5706 Hi = DAG.getConstant(0, NVT);
5707 } else if (Cst > NVTBits) {
5708 Lo = DAG.getConstant(0, NVT);
5709 Hi = DAG.getNode(ISD::SHL, dl,
5710 NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
5711 } else if (Cst == NVTBits) {
5712 Lo = DAG.getConstant(0, NVT);
5715 Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, DAG.getConstant(Cst, ShTy));
5716 Hi = DAG.getNode(ISD::OR, dl, NVT,
5717 DAG.getNode(ISD::SHL, dl, NVT, InH, DAG.getConstant(Cst, ShTy)),
5718 DAG.getNode(ISD::SRL, dl, NVT, InL,
5719 DAG.getConstant(NVTBits-Cst, ShTy)));
5724 Lo = DAG.getConstant(0, NVT);
5725 Hi = DAG.getConstant(0, NVT);
5726 } else if (Cst > NVTBits) {
5727 Lo = DAG.getNode(ISD::SRL, dl, NVT,
5728 InH, DAG.getConstant(Cst-NVTBits,ShTy));
5729 Hi = DAG.getConstant(0, NVT);
5730 } else if (Cst == NVTBits) {
5732 Hi = DAG.getConstant(0, NVT);
5734 Lo = DAG.getNode(ISD::OR, dl, NVT,
5735 DAG.getNode(ISD::SRL, dl, NVT, InL, DAG.getConstant(Cst, ShTy)),
5736 DAG.getNode(ISD::SHL, dl, NVT, InH,
5737 DAG.getConstant(NVTBits-Cst, ShTy)));
5738 Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, DAG.getConstant(Cst, ShTy));
5743 Hi = Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
5744 DAG.getConstant(NVTBits-1, ShTy));
5745 } else if (Cst > NVTBits) {
5746 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
5747 DAG.getConstant(Cst-NVTBits, ShTy));
5748 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
5749 DAG.getConstant(NVTBits-1, ShTy));
5750 } else if (Cst == NVTBits) {
5752 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
5753 DAG.getConstant(NVTBits-1, ShTy));
5755 Lo = DAG.getNode(ISD::OR, dl, NVT,
5756 DAG.getNode(ISD::SRL, dl, NVT, InL, DAG.getConstant(Cst, ShTy)),
5757 DAG.getNode(ISD::SHL, dl,
5758 NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5759 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(Cst, ShTy));
5765 // Okay, the shift amount isn't constant. However, if we can tell that it is
5766 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
5767 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
5768 APInt KnownZero, KnownOne;
5769 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
5771 // If we know that if any of the high bits of the shift amount are one, then
5772 // we can do this as a couple of simple shifts.
5773 if (KnownOne.intersects(Mask)) {
5774 // Mask out the high bit, which we know is set.
5775 Amt = DAG.getNode(ISD::AND, dl, Amt.getValueType(), Amt,
5776 DAG.getConstant(~Mask, Amt.getValueType()));
5778 // Expand the incoming operand to be shifted, so that we have its parts
5780 ExpandOp(Op, InL, InH);
5783 Lo = DAG.getConstant(0, NVT); // Low part is zero.
5784 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
5787 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
5788 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
5791 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
5792 DAG.getConstant(NVTBits-1, Amt.getValueType()));
5793 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
5798 // If we know that the high bits of the shift amount are all zero, then we can
5799 // do this as a couple of simple shifts.
5800 if ((KnownZero & Mask) == Mask) {
5802 SDValue Amt2 = DAG.getNode(ISD::SUB, dl, Amt.getValueType(),
5803 DAG.getConstant(NVTBits, Amt.getValueType()),
5806 // Expand the incoming operand to be shifted, so that we have its parts
5808 ExpandOp(Op, InL, InH);
5811 Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
5812 Hi = DAG.getNode(ISD::OR, dl, NVT,
5813 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
5814 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt2));
5817 Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
5818 Lo = DAG.getNode(ISD::OR, dl, NVT,
5819 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
5820 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt2));
5823 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
5824 Lo = DAG.getNode(ISD::OR, dl, NVT,
5825 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
5826 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt2));
5835 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
5836 // does not fit into a register, return the lo part and set the hi part to the
5837 // by-reg argument. If it does fit into a single register, return the result
5838 // and leave the Hi part unset.
5839 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
5840 bool isSigned, SDValue &Hi) {
5841 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
5842 // The input chain to this libcall is the entry node of the function.
5843 // Legalizing the call will automatically add the previous call to the
5845 SDValue InChain = DAG.getEntryNode();
5847 TargetLowering::ArgListTy Args;
5848 TargetLowering::ArgListEntry Entry;
5849 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5850 MVT ArgVT = Node->getOperand(i).getValueType();
5851 const Type *ArgTy = ArgVT.getTypeForMVT();
5852 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
5853 Entry.isSExt = isSigned;
5854 Entry.isZExt = !isSigned;
5855 Args.push_back(Entry);
5857 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
5858 TLI.getPointerTy());
5860 // Splice the libcall in wherever FindInputOutputChains tells us to.
5861 const Type *RetTy = Node->getValueType(0).getTypeForMVT();
5862 std::pair<SDValue,SDValue> CallInfo =
5863 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
5864 CallingConv::C, false, Callee, Args, DAG,
5865 Node->getDebugLoc());
5867 // Legalize the call sequence, starting with the chain. This will advance
5868 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
5869 // was added by LowerCallTo (guaranteeing proper serialization of calls).
5870 LegalizeOp(CallInfo.second);
5872 switch (getTypeAction(CallInfo.first.getValueType())) {
5873 default: assert(0 && "Unknown thing");
5875 Result = CallInfo.first;
5878 ExpandOp(CallInfo.first, Result, Hi);
5884 /// LegalizeINT_TO_FP - Legalize a [US]INT_TO_FP operation.
5886 SDValue SelectionDAGLegalize::
5887 LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op,
5889 bool isCustom = false;
5891 switch (getTypeAction(Op.getValueType())) {
5893 switch (TLI.getOperationAction(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5894 Op.getValueType())) {
5895 default: assert(0 && "Unknown operation action!");
5896 case TargetLowering::Custom:
5899 case TargetLowering::Legal:
5900 Tmp1 = LegalizeOp(Op);
5901 if (Result.getNode())
5902 Result = DAG.UpdateNodeOperands(Result, Tmp1);
5904 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, dl,
5907 Tmp1 = TLI.LowerOperation(Result, DAG);
5908 if (Tmp1.getNode()) Result = Tmp1;
5911 case TargetLowering::Expand:
5912 Result = ExpandLegalINT_TO_FP(isSigned, LegalizeOp(Op), DestTy, dl);
5914 case TargetLowering::Promote:
5915 Result = PromoteLegalINT_TO_FP(LegalizeOp(Op), DestTy, isSigned, dl);
5920 Result = ExpandIntToFP(isSigned, DestTy, Op, dl) ;
5923 Tmp1 = PromoteOp(Op);
5925 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Tmp1.getValueType(),
5926 Tmp1, DAG.getValueType(Op.getValueType()));
5928 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl,
5931 if (Result.getNode())
5932 Result = DAG.UpdateNodeOperands(Result, Tmp1);
5934 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, dl,
5936 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
5942 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
5944 SDValue SelectionDAGLegalize::
5945 ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source, DebugLoc dl) {
5946 MVT SourceVT = Source.getValueType();
5947 bool ExpandSource = getTypeAction(SourceVT) == Expand;
5949 // Expand unsupported int-to-fp vector casts by unrolling them.
5950 if (DestTy.isVector()) {
5952 return LegalizeOp(UnrollVectorOp(Source));
5953 MVT DestEltTy = DestTy.getVectorElementType();
5954 if (DestTy.getVectorNumElements() == 1) {
5955 SDValue Scalar = ScalarizeVectorOp(Source);
5956 SDValue Result = LegalizeINT_TO_FP(SDValue(), isSigned,
5957 DestEltTy, Scalar, dl);
5958 return DAG.getBUILD_VECTOR(DestTy, dl, Result);
5961 SplitVectorOp(Source, Lo, Hi);
5962 MVT SplitDestTy = MVT::getVectorVT(DestEltTy,
5963 DestTy.getVectorNumElements() / 2);
5964 SDValue LoResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy,
5966 SDValue HiResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy,
5968 return LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, dl, DestTy, LoResult,
5972 // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc.
5973 if (!isSigned && SourceVT != MVT::i32) {
5974 // The integer value loaded will be incorrectly if the 'sign bit' of the
5975 // incoming integer is set. To handle this, we dynamically test to see if
5976 // it is set, and, if so, add a fudge factor.
5980 ExpandOp(Source, Lo, Hi);
5981 Source = DAG.getNode(ISD::BUILD_PAIR, dl, SourceVT, Lo, Hi);
5983 // The comparison for the sign bit will use the entire operand.
5987 // Check to see if the target has a custom way to lower this. If so, use
5988 // it. (Note we've already expanded the operand in this case.)
5989 switch (TLI.getOperationAction(ISD::UINT_TO_FP, SourceVT)) {
5990 default: assert(0 && "This action not implemented for this operation!");
5991 case TargetLowering::Legal:
5992 case TargetLowering::Expand:
5993 break; // This case is handled below.
5994 case TargetLowering::Custom: {
5995 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::UINT_TO_FP, dl, DestTy,
5998 return LegalizeOp(NV);
5999 break; // The target decided this was legal after all
6003 // If this is unsigned, and not supported, first perform the conversion to
6004 // signed, then adjust the result if the sign bit is set.
6005 SDValue SignedConv = ExpandIntToFP(true, DestTy, Source, dl);
6007 SDValue SignSet = DAG.getSetCC(dl,
6008 TLI.getSetCCResultType(Hi.getValueType()),
6009 Hi, DAG.getConstant(0, Hi.getValueType()),
6011 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
6012 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
6013 SignSet, Four, Zero);
6014 uint64_t FF = 0x5f800000ULL;
6015 if (TLI.isLittleEndian()) FF <<= 32;
6016 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
6018 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
6019 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
6020 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
6021 Alignment = std::min(Alignment, 4u);
6023 if (DestTy == MVT::f32)
6024 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
6025 PseudoSourceValue::getConstantPool(), 0,
6027 else if (DestTy.bitsGT(MVT::f32))
6028 // FIXME: Avoid the extend by construction the right constantpool?
6029 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, dl, DestTy, DAG.getEntryNode(),
6031 PseudoSourceValue::getConstantPool(), 0,
6032 MVT::f32, false, Alignment);
6034 assert(0 && "Unexpected conversion");
6036 MVT SCVT = SignedConv.getValueType();
6037 if (SCVT != DestTy) {
6038 // Destination type needs to be expanded as well. The FADD now we are
6039 // constructing will be expanded into a libcall.
6040 if (SCVT.getSizeInBits() != DestTy.getSizeInBits()) {
6041 assert(SCVT.getSizeInBits() * 2 == DestTy.getSizeInBits());
6042 SignedConv = DAG.getNode(ISD::BUILD_PAIR, dl, DestTy,
6043 SignedConv, SignedConv.getValue(1));
6045 SignedConv = DAG.getNode(ISD::BIT_CONVERT, dl, DestTy, SignedConv);
6047 return DAG.getNode(ISD::FADD, dl, DestTy, SignedConv, FudgeInReg);
6050 // Check to see if the target has a custom way to lower this. If so, use it.
6051 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) {
6052 default: assert(0 && "This action not implemented for this operation!");
6053 case TargetLowering::Legal:
6054 case TargetLowering::Expand:
6055 break; // This case is handled below.
6056 case TargetLowering::Custom: {
6057 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, dl, DestTy,
6060 return LegalizeOp(NV);
6061 break; // The target decided this was legal after all
6065 // Expand the source, then glue it back together for the call. We must expand
6066 // the source in case it is shared (this pass of legalize must traverse it).
6068 SDValue SrcLo, SrcHi;
6069 ExpandOp(Source, SrcLo, SrcHi);
6070 Source = DAG.getNode(ISD::BUILD_PAIR, dl, SourceVT, SrcLo, SrcHi);
6073 RTLIB::Libcall LC = isSigned ?
6074 RTLIB::getSINTTOFP(SourceVT, DestTy) :
6075 RTLIB::getUINTTOFP(SourceVT, DestTy);
6076 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unknown int value type");
6078 Source = DAG.getNode(ISD::SINT_TO_FP, dl, DestTy, Source);
6080 SDValue Result = ExpandLibCall(LC, Source.getNode(), isSigned, HiPart);
6081 if (Result.getValueType() != DestTy && HiPart.getNode())
6082 Result = DAG.getNode(ISD::BUILD_PAIR, dl, DestTy, Result, HiPart);
6086 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
6087 /// INT_TO_FP operation of the specified operand when the target requests that
6088 /// we expand it. At this point, we know that the result and operand types are
6089 /// legal for the target.
6090 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
6094 if (Op0.getValueType() == MVT::i32) {
6095 // simple 32-bit [signed|unsigned] integer to float/double expansion
6097 // Get the stack frame index of a 8 byte buffer.
6098 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
6100 // word offset constant for Hi/Lo address computation
6101 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
6102 // set up Hi and Lo (into buffer) address based on endian
6103 SDValue Hi = StackSlot;
6104 SDValue Lo = DAG.getNode(ISD::ADD, dl,
6105 TLI.getPointerTy(), StackSlot,WordOff);
6106 if (TLI.isLittleEndian())
6109 // if signed map to unsigned space
6112 // constant used to invert sign bit (signed to unsigned mapping)
6113 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
6114 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
6118 // store the lo of the constructed double - based on integer input
6119 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
6120 Op0Mapped, Lo, NULL, 0);
6121 // initial hi portion of constructed double
6122 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
6123 // store the hi of the constructed double - biased exponent
6124 SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0);
6125 // load the constructed double
6126 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0);
6127 // FP constant to bias correct the final result
6128 SDValue Bias = DAG.getConstantFP(isSigned ?
6129 BitsToDouble(0x4330000080000000ULL)
6130 : BitsToDouble(0x4330000000000000ULL),
6132 // subtract the bias
6133 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
6136 // handle final rounding
6137 if (DestVT == MVT::f64) {
6140 } else if (DestVT.bitsLT(MVT::f64)) {
6141 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
6142 DAG.getIntPtrConstant(0));
6143 } else if (DestVT.bitsGT(MVT::f64)) {
6144 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
6148 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
6149 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
6151 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()),
6152 Op0, DAG.getConstant(0, Op0.getValueType()),
6154 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
6155 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
6156 SignSet, Four, Zero);
6158 // If the sign bit of the integer is set, the large number will be treated
6159 // as a negative number. To counteract this, the dynamic code adds an
6160 // offset depending on the data type.
6162 switch (Op0.getValueType().getSimpleVT()) {
6163 default: assert(0 && "Unsupported integer type!");
6164 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
6165 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
6166 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
6167 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
6169 if (TLI.isLittleEndian()) FF <<= 32;
6170 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
6172 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
6173 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
6174 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
6175 Alignment = std::min(Alignment, 4u);
6177 if (DestVT == MVT::f32)
6178 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
6179 PseudoSourceValue::getConstantPool(), 0,
6183 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
6184 DAG.getEntryNode(), CPIdx,
6185 PseudoSourceValue::getConstantPool(), 0,
6186 MVT::f32, false, Alignment));
6189 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
6192 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
6193 /// *INT_TO_FP operation of the specified operand when the target requests that
6194 /// we promote it. At this point, we know that the result and operand types are
6195 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
6196 /// operation that takes a larger input.
6197 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
6201 // First step, figure out the appropriate *INT_TO_FP operation to use.
6202 MVT NewInTy = LegalOp.getValueType();
6204 unsigned OpToUse = 0;
6206 // Scan for the appropriate larger type to use.
6208 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
6209 assert(NewInTy.isInteger() && "Ran out of possibilities!");
6211 // If the target supports SINT_TO_FP of this type, use it.
6212 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
6214 case TargetLowering::Legal:
6215 if (!TLI.isTypeLegal(NewInTy))
6216 break; // Can't use this datatype.
6218 case TargetLowering::Custom:
6219 OpToUse = ISD::SINT_TO_FP;
6223 if (isSigned) continue;
6225 // If the target supports UINT_TO_FP of this type, use it.
6226 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
6228 case TargetLowering::Legal:
6229 if (!TLI.isTypeLegal(NewInTy))
6230 break; // Can't use this datatype.
6232 case TargetLowering::Custom:
6233 OpToUse = ISD::UINT_TO_FP;
6238 // Otherwise, try a larger type.
6241 // Okay, we found the operation and type to use. Zero extend our input to the
6242 // desired type then run the operation on it.
6243 return DAG.getNode(OpToUse, dl, DestVT,
6244 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
6245 dl, NewInTy, LegalOp));
6248 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
6249 /// FP_TO_*INT operation of the specified operand when the target requests that
6250 /// we promote it. At this point, we know that the result and operand types are
6251 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
6252 /// operation that returns a larger result.
6253 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
6257 // First step, figure out the appropriate FP_TO*INT operation to use.
6258 MVT NewOutTy = DestVT;
6260 unsigned OpToUse = 0;
6262 // Scan for the appropriate larger type to use.
6264 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1);
6265 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
6267 // If the target supports FP_TO_SINT returning this type, use it.
6268 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
6270 case TargetLowering::Legal:
6271 if (!TLI.isTypeLegal(NewOutTy))
6272 break; // Can't use this datatype.
6274 case TargetLowering::Custom:
6275 OpToUse = ISD::FP_TO_SINT;
6280 // If the target supports FP_TO_UINT of this type, use it.
6281 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
6283 case TargetLowering::Legal:
6284 if (!TLI.isTypeLegal(NewOutTy))
6285 break; // Can't use this datatype.
6287 case TargetLowering::Custom:
6288 OpToUse = ISD::FP_TO_UINT;
6293 // Otherwise, try a larger type.
6297 // Okay, we found the operation and type to use.
6298 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
6300 // If the operation produces an invalid type, it must be custom lowered. Use
6301 // the target lowering hooks to expand it. Just keep the low part of the
6302 // expanded operation, we know that we're truncating anyway.
6303 if (getTypeAction(NewOutTy) == Expand) {
6304 SmallVector<SDValue, 2> Results;
6305 TLI.ReplaceNodeResults(Operation.getNode(), Results, DAG);
6306 assert(Results.size() == 1 && "Incorrect FP_TO_XINT lowering!");
6307 Operation = Results[0];
6310 // Truncate the result of the extended FP_TO_*INT operation to the desired
6312 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
6315 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
6317 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) {
6318 MVT VT = Op.getValueType();
6319 MVT SHVT = TLI.getShiftAmountTy();
6320 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
6321 switch (VT.getSimpleVT()) {
6322 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
6324 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
6325 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
6326 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
6328 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
6329 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
6330 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
6331 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
6332 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
6333 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
6334 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
6335 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
6336 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
6338 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
6339 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
6340 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
6341 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
6342 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
6343 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
6344 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
6345 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
6346 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
6347 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
6348 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
6349 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
6350 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
6351 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
6352 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
6353 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
6354 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
6355 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
6356 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
6357 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
6358 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
6362 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
6364 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
6367 default: assert(0 && "Cannot expand this yet!");
6369 static const uint64_t mask[6] = {
6370 0x5555555555555555ULL, 0x3333333333333333ULL,
6371 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
6372 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
6374 MVT VT = Op.getValueType();
6375 MVT ShVT = TLI.getShiftAmountTy();
6376 unsigned len = VT.getSizeInBits();
6377 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
6378 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
6379 unsigned EltSize = VT.isVector() ?
6380 VT.getVectorElementType().getSizeInBits() : len;
6381 SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT);
6382 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
6383 Op = DAG.getNode(ISD::ADD, dl, VT,
6384 DAG.getNode(ISD::AND, dl, VT, Op, Tmp2),
6385 DAG.getNode(ISD::AND, dl, VT,
6386 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3),
6392 // for now, we do this:
6393 // x = x | (x >> 1);
6394 // x = x | (x >> 2);
6396 // x = x | (x >>16);
6397 // x = x | (x >>32); // for 64-bit input
6398 // return popcount(~x);
6400 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
6401 MVT VT = Op.getValueType();
6402 MVT ShVT = TLI.getShiftAmountTy();
6403 unsigned len = VT.getSizeInBits();
6404 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
6405 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
6406 Op = DAG.getNode(ISD::OR, dl, VT, Op,
6407 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
6409 Op = DAG.getNOT(dl, Op, VT);
6410 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
6413 // for now, we use: { return popcount(~x & (x - 1)); }
6414 // unless the target has ctlz but not ctpop, in which case we use:
6415 // { return 32 - nlz(~x & (x-1)); }
6416 // see also http://www.hackersdelight.org/HDcode/ntz.cc
6417 MVT VT = Op.getValueType();
6418 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
6419 DAG.getNOT(dl, Op, VT),
6420 DAG.getNode(ISD::SUB, dl, VT, Op,
6421 DAG.getConstant(1, VT)));
6422 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
6423 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
6424 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
6425 return DAG.getNode(ISD::SUB, dl, VT,
6426 DAG.getConstant(VT.getSizeInBits(), VT),
6427 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
6428 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
6433 /// ExpandOp - Expand the specified SDValue into its two component pieces
6434 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
6435 /// LegalizedNodes map is filled in for any results that are not expanded, the
6436 /// ExpandedNodes map is filled in for any results that are expanded, and the
6437 /// Lo/Hi values are returned.
6438 void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
6439 MVT VT = Op.getValueType();
6440 MVT NVT = TLI.getTypeToTransformTo(VT);
6441 SDNode *Node = Op.getNode();
6442 DebugLoc dl = Node->getDebugLoc();
6443 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
6444 assert(((NVT.isInteger() && NVT.bitsLT(VT)) || VT.isFloatingPoint() ||
6445 VT.isVector()) && "Cannot expand to FP value or to larger int value!");
6447 // See if we already expanded it.
6448 DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator I
6449 = ExpandedNodes.find(Op);
6450 if (I != ExpandedNodes.end()) {
6451 Lo = I->second.first;
6452 Hi = I->second.second;
6456 switch (Node->getOpcode()) {
6457 case ISD::CopyFromReg:
6458 assert(0 && "CopyFromReg must be legal!");
6459 case ISD::FP_ROUND_INREG:
6460 if (VT == MVT::ppcf128 &&
6461 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
6462 TargetLowering::Custom) {
6463 SDValue SrcLo, SrcHi, Src;
6464 ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
6465 Src = DAG.getNode(ISD::BUILD_PAIR, dl, VT, SrcLo, SrcHi);
6466 SDValue Result = TLI.LowerOperation(
6467 DAG.getNode(ISD::FP_ROUND_INREG, dl, VT, Src, Op.getOperand(1)), DAG);
6468 assert(Result.getNode()->getOpcode() == ISD::BUILD_PAIR);
6469 Lo = Result.getNode()->getOperand(0);
6470 Hi = Result.getNode()->getOperand(1);
6476 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
6478 assert(0 && "Do not know how to expand this operator!");
6480 case ISD::EXTRACT_ELEMENT:
6481 ExpandOp(Node->getOperand(0), Lo, Hi);
6482 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
6483 return ExpandOp(Hi, Lo, Hi);
6484 return ExpandOp(Lo, Lo, Hi);
6485 case ISD::EXTRACT_VECTOR_ELT:
6486 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types.
6487 Lo = ExpandEXTRACT_VECTOR_ELT(Op);
6488 return ExpandOp(Lo, Lo, Hi);
6490 Lo = DAG.getUNDEF(NVT);
6491 Hi = DAG.getUNDEF(NVT);
6493 case ISD::Constant: {
6494 unsigned NVTBits = NVT.getSizeInBits();
6495 const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue();
6496 Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT);
6497 Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT);
6500 case ISD::ConstantFP: {
6501 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
6502 if (CFP->getValueType(0) == MVT::ppcf128) {
6503 APInt api = CFP->getValueAPF().bitcastToAPInt();
6504 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
6506 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
6510 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
6511 if (getTypeAction(Lo.getValueType()) == Expand)
6512 ExpandOp(Lo, Lo, Hi);
6515 case ISD::BUILD_PAIR:
6516 // Return the operands.
6517 Lo = Node->getOperand(0);
6518 Hi = Node->getOperand(1);
6521 case ISD::MERGE_VALUES:
6522 if (Node->getNumValues() == 1) {
6523 ExpandOp(Op.getOperand(0), Lo, Hi);
6526 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y)
6527 assert(Op.getResNo() == 0 && Node->getNumValues() == 2 &&
6528 Op.getValue(1).getValueType() == MVT::Other &&
6529 "unhandled MERGE_VALUES");
6530 ExpandOp(Op.getOperand(0), Lo, Hi);
6531 // Remember that we legalized the chain.
6532 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1)));
6535 case ISD::SIGN_EXTEND_INREG:
6536 ExpandOp(Node->getOperand(0), Lo, Hi);
6537 // sext_inreg the low part if needed.
6538 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Lo, Node->getOperand(1));
6540 // The high part gets the sign extension from the lo-part. This handles
6541 // things like sextinreg V:i64 from i8.
6542 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
6543 DAG.getConstant(NVT.getSizeInBits()-1,
6544 TLI.getShiftAmountTy()));
6548 ExpandOp(Node->getOperand(0), Lo, Hi);
6549 SDValue TempLo = DAG.getNode(ISD::BSWAP, dl, NVT, Hi);
6550 Hi = DAG.getNode(ISD::BSWAP, dl, NVT, Lo);
6556 ExpandOp(Node->getOperand(0), Lo, Hi);
6557 Lo = DAG.getNode(ISD::ADD, dl, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
6558 DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
6559 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
6560 Hi = DAG.getConstant(0, NVT);
6564 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
6565 ExpandOp(Node->getOperand(0), Lo, Hi);
6566 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
6567 SDValue HLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Hi);
6568 SDValue TopNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), HLZ,
6570 SDValue LowPart = DAG.getNode(ISD::CTLZ, dl, NVT, Lo);
6571 LowPart = DAG.getNode(ISD::ADD, dl, NVT, LowPart, BitsC);
6573 Lo = DAG.getNode(ISD::SELECT, dl, NVT, TopNotZero, HLZ, LowPart);
6574 Hi = DAG.getConstant(0, NVT);
6579 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
6580 ExpandOp(Node->getOperand(0), Lo, Hi);
6581 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
6582 SDValue LTZ = DAG.getNode(ISD::CTTZ, dl, NVT, Lo);
6583 SDValue BotNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), LTZ,
6585 SDValue HiPart = DAG.getNode(ISD::CTTZ, dl, NVT, Hi);
6586 HiPart = DAG.getNode(ISD::ADD, dl, NVT, HiPart, BitsC);
6588 Lo = DAG.getNode(ISD::SELECT, dl, NVT, BotNotZero, LTZ, HiPart);
6589 Hi = DAG.getConstant(0, NVT);
6594 SDValue Ch = Node->getOperand(0); // Legalize the chain.
6595 SDValue Ptr = Node->getOperand(1); // Legalize the pointer.
6596 Lo = DAG.getVAArg(NVT, dl, Ch, Ptr, Node->getOperand(2));
6597 Hi = DAG.getVAArg(NVT, dl, Lo.getValue(1), Ptr, Node->getOperand(2));
6599 // Remember that we legalized the chain.
6600 Hi = LegalizeOp(Hi);
6601 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
6602 if (TLI.isBigEndian())
6608 LoadSDNode *LD = cast<LoadSDNode>(Node);
6609 SDValue Ch = LD->getChain(); // Legalize the chain.
6610 SDValue Ptr = LD->getBasePtr(); // Legalize the pointer.
6611 ISD::LoadExtType ExtType = LD->getExtensionType();
6612 const Value *SV = LD->getSrcValue();
6613 int SVOffset = LD->getSrcValueOffset();
6614 unsigned Alignment = LD->getAlignment();
6615 bool isVolatile = LD->isVolatile();
6617 if (ExtType == ISD::NON_EXTLOAD) {
6618 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, SV, SVOffset,
6619 isVolatile, Alignment);
6620 if (VT == MVT::f32 || VT == MVT::f64) {
6621 // f32->i32 or f64->i64 one to one expansion.
6622 // Remember that we legalized the chain.
6623 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
6624 // Recursively expand the new load.
6625 if (getTypeAction(NVT) == Expand)
6626 ExpandOp(Lo, Lo, Hi);
6630 // Increment the pointer to the other half.
6631 unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8;
6632 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
6633 DAG.getIntPtrConstant(IncrementSize));
6634 SVOffset += IncrementSize;
6635 Alignment = MinAlign(Alignment, IncrementSize);
6636 Hi = DAG.getLoad(NVT, dl, Ch, Ptr, SV, SVOffset,
6637 isVolatile, Alignment);
6639 // Build a factor node to remember that this load is independent of the
6641 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
6644 // Remember that we legalized the chain.
6645 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
6646 if (TLI.isBigEndian())
6649 MVT EVT = LD->getMemoryVT();
6651 if ((VT == MVT::f64 && EVT == MVT::f32) ||
6652 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
6653 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
6654 SDValue Load = DAG.getLoad(EVT, dl, Ch, Ptr, SV,
6655 SVOffset, isVolatile, Alignment);
6656 // Remember that we legalized the chain.
6657 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Load.getValue(1)));
6658 ExpandOp(DAG.getNode(ISD::FP_EXTEND, dl, VT, Load), Lo, Hi);
6663 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, SV,
6664 SVOffset, isVolatile, Alignment);
6666 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, SV,
6667 SVOffset, EVT, isVolatile,
6670 // Remember that we legalized the chain.
6671 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
6673 if (ExtType == ISD::SEXTLOAD) {
6674 // The high part is obtained by SRA'ing all but one of the bits of the
6676 unsigned LoSize = Lo.getValueType().getSizeInBits();
6677 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
6678 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6679 } else if (ExtType == ISD::ZEXTLOAD) {
6680 // The high part is just a zero.
6681 Hi = DAG.getConstant(0, NVT);
6682 } else /* if (ExtType == ISD::EXTLOAD) */ {
6683 // The high part is undefined.
6684 Hi = DAG.getUNDEF(NVT);
6691 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
6692 SDValue LL, LH, RL, RH;
6693 ExpandOp(Node->getOperand(0), LL, LH);
6694 ExpandOp(Node->getOperand(1), RL, RH);
6695 Lo = DAG.getNode(Node->getOpcode(), dl, NVT, LL, RL);
6696 Hi = DAG.getNode(Node->getOpcode(), dl, NVT, LH, RH);
6700 SDValue LL, LH, RL, RH;
6701 ExpandOp(Node->getOperand(1), LL, LH);
6702 ExpandOp(Node->getOperand(2), RL, RH);
6703 if (getTypeAction(NVT) == Expand)
6704 NVT = TLI.getTypeToExpandTo(NVT);
6705 Lo = DAG.getNode(ISD::SELECT, dl, NVT, Node->getOperand(0), LL, RL);
6707 Hi = DAG.getNode(ISD::SELECT, dl, NVT, Node->getOperand(0), LH, RH);
6710 case ISD::SELECT_CC: {
6711 SDValue TL, TH, FL, FH;
6712 ExpandOp(Node->getOperand(2), TL, TH);
6713 ExpandOp(Node->getOperand(3), FL, FH);
6714 if (getTypeAction(NVT) == Expand)
6715 NVT = TLI.getTypeToExpandTo(NVT);
6716 Lo = DAG.getNode(ISD::SELECT_CC, dl, NVT, Node->getOperand(0),
6717 Node->getOperand(1), TL, FL, Node->getOperand(4));
6719 Hi = DAG.getNode(ISD::SELECT_CC, dl, NVT, Node->getOperand(0),
6720 Node->getOperand(1), TH, FH, Node->getOperand(4));
6723 case ISD::ANY_EXTEND:
6724 // The low part is any extension of the input (which degenerates to a copy).
6725 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Node->getOperand(0));
6726 // The high part is undefined.
6727 Hi = DAG.getUNDEF(NVT);
6729 case ISD::SIGN_EXTEND: {
6730 // The low part is just a sign extension of the input (which degenerates to
6732 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, Node->getOperand(0));
6734 // The high part is obtained by SRA'ing all but one of the bits of the lo
6736 unsigned LoSize = Lo.getValueType().getSizeInBits();
6737 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
6738 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6741 case ISD::ZERO_EXTEND:
6742 // The low part is just a zero extension of the input (which degenerates to
6744 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
6746 // The high part is just a zero.
6747 Hi = DAG.getConstant(0, NVT);
6750 case ISD::TRUNCATE: {
6751 // The input value must be larger than this value. Expand *it*.
6753 ExpandOp(Node->getOperand(0), NewLo, Hi);
6755 // The low part is now either the right size, or it is closer. If not the
6756 // right size, make an illegal truncate so we recursively expand it.
6757 if (NewLo.getValueType() != Node->getValueType(0))
6758 NewLo = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), NewLo);
6759 ExpandOp(NewLo, Lo, Hi);
6763 case ISD::BIT_CONVERT: {
6765 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
6766 // If the target wants to, allow it to lower this itself.
6767 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6768 case Expand: assert(0 && "cannot expand FP!");
6769 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
6770 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
6772 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp), DAG);
6775 // f32 / f64 must be expanded to i32 / i64.
6776 if (VT == MVT::f32 || VT == MVT::f64) {
6777 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
6778 if (getTypeAction(NVT) == Expand)
6779 ExpandOp(Lo, Lo, Hi);
6783 // If source operand will be expanded to the same type as VT, i.e.
6784 // i64 <- f64, i32 <- f32, expand the source operand instead.
6785 MVT VT0 = Node->getOperand(0).getValueType();
6786 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
6787 ExpandOp(Node->getOperand(0), Lo, Hi);
6791 // Turn this into a load/store pair by default.
6792 if (Tmp.getNode() == 0)
6793 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT, dl);
6795 ExpandOp(Tmp, Lo, Hi);
6799 case ISD::READCYCLECOUNTER: {
6800 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
6801 TargetLowering::Custom &&
6802 "Must custom expand ReadCycleCounter");
6803 SDValue Tmp = TLI.LowerOperation(Op, DAG);
6804 assert(Tmp.getNode() && "Node must be custom expanded!");
6805 ExpandOp(Tmp.getValue(0), Lo, Hi);
6806 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6807 LegalizeOp(Tmp.getValue(1)));
6811 case ISD::ATOMIC_CMP_SWAP: {
6812 // This operation does not need a loop.
6813 SDValue Tmp = TLI.LowerOperation(Op, DAG);
6814 assert(Tmp.getNode() && "Node must be custom expanded!");
6815 ExpandOp(Tmp.getValue(0), Lo, Hi);
6816 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6817 LegalizeOp(Tmp.getValue(1)));
6821 case ISD::ATOMIC_LOAD_ADD:
6822 case ISD::ATOMIC_LOAD_SUB:
6823 case ISD::ATOMIC_LOAD_AND:
6824 case ISD::ATOMIC_LOAD_OR:
6825 case ISD::ATOMIC_LOAD_XOR:
6826 case ISD::ATOMIC_LOAD_NAND:
6827 case ISD::ATOMIC_SWAP: {
6828 // These operations require a loop to be generated. We can't do that yet,
6829 // so substitute a target-dependent pseudo and expand that later.
6830 SDValue In2Lo, In2Hi, In2;
6831 ExpandOp(Op.getOperand(2), In2Lo, In2Hi);
6832 In2 = DAG.getNode(ISD::BUILD_PAIR, dl, VT, In2Lo, In2Hi);
6833 AtomicSDNode* Anode = cast<AtomicSDNode>(Node);
6835 DAG.getAtomic(Op.getOpcode(), dl, Anode->getMemoryVT(),
6836 Op.getOperand(0), Op.getOperand(1), In2,
6837 Anode->getSrcValue(), Anode->getAlignment());
6838 SDValue Result = TLI.LowerOperation(Replace, DAG);
6839 ExpandOp(Result.getValue(0), Lo, Hi);
6840 // Remember that we legalized the chain.
6841 AddLegalizedOperand(SDValue(Node,1), LegalizeOp(Result.getValue(1)));
6845 // These operators cannot be expanded directly, emit them as calls to
6846 // library functions.
6847 case ISD::FP_TO_SINT: {
6848 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
6850 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6851 case Expand: assert(0 && "cannot expand FP!");
6852 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6853 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6856 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op), DAG);
6858 // Now that the custom expander is done, expand the result, which is still
6861 ExpandOp(Op, Lo, Hi);
6866 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Node->getOperand(0).getValueType(),
6868 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected uint-to-fp conversion!");
6869 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6873 case ISD::FP_TO_UINT: {
6874 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
6876 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6877 case Expand: assert(0 && "cannot expand FP!");
6878 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6879 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6882 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, dl, VT, Op), DAG);
6884 // Now that the custom expander is done, expand the result.
6886 ExpandOp(Op, Lo, Hi);
6891 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Node->getOperand(0).getValueType(),
6893 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
6894 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6899 // If the target wants custom lowering, do so.
6900 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6901 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
6902 SDValue Op = DAG.getNode(ISD::SHL, dl, VT, Node->getOperand(0), ShiftAmt);
6903 Op = TLI.LowerOperation(Op, DAG);
6905 // Now that the custom expander is done, expand the result, which is
6907 ExpandOp(Op, Lo, Hi);
6912 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
6913 // this X << 1 as X+X.
6914 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
6915 if (ShAmt->getAPIntValue() == 1 &&
6916 TLI.isOperationLegalOrCustom(ISD::ADDC, NVT) &&
6917 TLI.isOperationLegalOrCustom(ISD::ADDE, NVT)) {
6918 SDValue LoOps[2], HiOps[3];
6919 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
6920 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
6921 LoOps[1] = LoOps[0];
6922 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
6924 HiOps[1] = HiOps[0];
6925 HiOps[2] = Lo.getValue(1);
6926 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
6931 // If we can emit an efficient shift operation, do so now.
6932 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi, dl))
6935 // If this target supports SHL_PARTS, use it.
6936 TargetLowering::LegalizeAction Action =
6937 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
6938 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6939 Action == TargetLowering::Custom) {
6940 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0),
6941 ShiftAmt, Lo, Hi, dl);
6945 // Otherwise, emit a libcall.
6946 Lo = ExpandLibCall(RTLIB::SHL_I64, Node, false/*left shift=unsigned*/, Hi);
6951 // If the target wants custom lowering, do so.
6952 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6953 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
6954 SDValue Op = DAG.getNode(ISD::SRA, dl, VT, Node->getOperand(0), ShiftAmt);
6955 Op = TLI.LowerOperation(Op, DAG);
6957 // Now that the custom expander is done, expand the result, which is
6959 ExpandOp(Op, Lo, Hi);
6964 // If we can emit an efficient shift operation, do so now.
6965 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi, dl))
6968 // If this target supports SRA_PARTS, use it.
6969 TargetLowering::LegalizeAction Action =
6970 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
6971 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6972 Action == TargetLowering::Custom) {
6973 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0),
6974 ShiftAmt, Lo, Hi, dl);
6978 // Otherwise, emit a libcall.
6979 Lo = ExpandLibCall(RTLIB::SRA_I64, Node, true/*ashr is signed*/, Hi);
6984 // If the target wants custom lowering, do so.
6985 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6986 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
6987 SDValue Op = DAG.getNode(ISD::SRL, dl, VT, Node->getOperand(0), ShiftAmt);
6988 Op = TLI.LowerOperation(Op, DAG);
6990 // Now that the custom expander is done, expand the result, which is
6992 ExpandOp(Op, Lo, Hi);
6997 // If we can emit an efficient shift operation, do so now.
6998 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi, dl))
7001 // If this target supports SRL_PARTS, use it.
7002 TargetLowering::LegalizeAction Action =
7003 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
7004 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
7005 Action == TargetLowering::Custom) {
7006 ExpandShiftParts(ISD::SRL_PARTS,
7007 Node->getOperand(0), ShiftAmt, Lo, Hi, dl);
7011 // Otherwise, emit a libcall.
7012 Lo = ExpandLibCall(RTLIB::SRL_I64, Node, false/*lshr is unsigned*/, Hi);
7018 // If the target wants to custom expand this, let them.
7019 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
7020 TargetLowering::Custom) {
7021 SDValue Result = TLI.LowerOperation(Op, DAG);
7022 if (Result.getNode()) {
7023 ExpandOp(Result, Lo, Hi);
7027 // Expand the subcomponents.
7028 SDValue LHSL, LHSH, RHSL, RHSH;
7029 ExpandOp(Node->getOperand(0), LHSL, LHSH);
7030 ExpandOp(Node->getOperand(1), RHSL, RHSH);
7031 SDValue LoOps[2], HiOps[3];
7037 //cascaded check to see if any smaller size has a a carry flag.
7038 unsigned OpV = Node->getOpcode() == ISD::ADD ? ISD::ADDC : ISD::SUBC;
7039 bool hasCarry = false;
7040 for (unsigned BitSize = NVT.getSizeInBits(); BitSize != 0; BitSize /= 2) {
7041 MVT AVT = MVT::getIntegerVT(BitSize);
7042 if (TLI.isOperationLegalOrCustom(OpV, AVT)) {
7049 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
7050 if (Node->getOpcode() == ISD::ADD) {
7051 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
7052 HiOps[2] = Lo.getValue(1);
7053 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
7055 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
7056 HiOps[2] = Lo.getValue(1);
7057 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
7061 if (Node->getOpcode() == ISD::ADD) {
7062 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2);
7063 Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2);
7064 SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
7065 Lo, LoOps[0], ISD::SETULT);
7066 SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1,
7067 DAG.getConstant(1, NVT),
7068 DAG.getConstant(0, NVT));
7069 SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
7070 Lo, LoOps[1], ISD::SETULT);
7071 SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2,
7072 DAG.getConstant(1, NVT),
7074 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
7076 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2);
7077 Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2);
7078 SDValue Cmp = DAG.getSetCC(dl, NVT, LoOps[0], LoOps[1], ISD::SETULT);
7079 SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp,
7080 DAG.getConstant(1, NVT),
7081 DAG.getConstant(0, NVT));
7082 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
7090 // Expand the subcomponents.
7091 SDValue LHSL, LHSH, RHSL, RHSH;
7092 ExpandOp(Node->getOperand(0), LHSL, LHSH);
7093 ExpandOp(Node->getOperand(1), RHSL, RHSH);
7094 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
7095 SDValue LoOps[2] = { LHSL, RHSL };
7096 SDValue HiOps[3] = { LHSH, RHSH };
7098 if (Node->getOpcode() == ISD::ADDC) {
7099 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
7100 HiOps[2] = Lo.getValue(1);
7101 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
7103 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
7104 HiOps[2] = Lo.getValue(1);
7105 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
7107 // Remember that we legalized the flag.
7108 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
7113 // Expand the subcomponents.
7114 SDValue LHSL, LHSH, RHSL, RHSH;
7115 ExpandOp(Node->getOperand(0), LHSL, LHSH);
7116 ExpandOp(Node->getOperand(1), RHSL, RHSH);
7117 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
7118 SDValue LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
7119 SDValue HiOps[3] = { LHSH, RHSH };
7121 Lo = DAG.getNode(Node->getOpcode(), dl, VTList, LoOps, 3);
7122 HiOps[2] = Lo.getValue(1);
7123 Hi = DAG.getNode(Node->getOpcode(), dl, VTList, HiOps, 3);
7125 // Remember that we legalized the flag.
7126 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
7130 // If the target wants to custom expand this, let them.
7131 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
7132 SDValue New = TLI.LowerOperation(Op, DAG);
7133 if (New.getNode()) {
7134 ExpandOp(New, Lo, Hi);
7139 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT);
7140 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT);
7141 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT);
7142 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT);
7143 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
7144 SDValue LL, LH, RL, RH;
7145 ExpandOp(Node->getOperand(0), LL, LH);
7146 ExpandOp(Node->getOperand(1), RL, RH);
7147 unsigned OuterBitSize = Op.getValueSizeInBits();
7148 unsigned InnerBitSize = RH.getValueSizeInBits();
7149 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
7150 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
7151 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
7152 if (DAG.MaskedValueIsZero(Node->getOperand(0), HighMask) &&
7153 DAG.MaskedValueIsZero(Node->getOperand(1), HighMask)) {
7154 // The inputs are both zero-extended.
7156 // We can emit a umul_lohi.
7157 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
7158 Hi = SDValue(Lo.getNode(), 1);
7162 // We can emit a mulhu+mul.
7163 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
7164 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
7168 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
7169 // The input values are both sign-extended.
7171 // We can emit a smul_lohi.
7172 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
7173 Hi = SDValue(Lo.getNode(), 1);
7177 // We can emit a mulhs+mul.
7178 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
7179 Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL);
7184 // Lo,Hi = umul LHS, RHS.
7185 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
7186 DAG.getVTList(NVT, NVT), LL, RL);
7188 Hi = UMulLOHI.getValue(1);
7189 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
7190 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
7191 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
7192 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
7196 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
7197 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
7198 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
7199 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
7200 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
7201 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
7206 // If nothing else, we can make a libcall.
7207 Lo = ExpandLibCall(RTLIB::MUL_I64, Node, false/*sign irrelevant*/, Hi);
7211 Lo = ExpandLibCall(RTLIB::SDIV_I64, Node, true, Hi);
7214 Lo = ExpandLibCall(RTLIB::UDIV_I64, Node, true, Hi);
7217 Lo = ExpandLibCall(RTLIB::SREM_I64, Node, true, Hi);
7220 Lo = ExpandLibCall(RTLIB::UREM_I64, Node, true, Hi);
7224 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::ADD_F32,
7227 RTLIB::ADD_PPCF128),
7231 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::SUB_F32,
7234 RTLIB::SUB_PPCF128),
7238 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::MUL_F32,
7241 RTLIB::MUL_PPCF128),
7245 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::DIV_F32,
7248 RTLIB::DIV_PPCF128),
7251 case ISD::FP_EXTEND: {
7252 if (VT == MVT::ppcf128) {
7253 assert(Node->getOperand(0).getValueType()==MVT::f32 ||
7254 Node->getOperand(0).getValueType()==MVT::f64);
7255 const uint64_t zero = 0;
7256 if (Node->getOperand(0).getValueType()==MVT::f32)
7257 Hi = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Node->getOperand(0));
7259 Hi = Node->getOperand(0);
7260 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7263 RTLIB::Libcall LC = RTLIB::getFPEXT(Node->getOperand(0).getValueType(), VT);
7264 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!");
7265 Lo = ExpandLibCall(LC, Node, true, Hi);
7268 case ISD::FP_ROUND: {
7269 RTLIB::Libcall LC = RTLIB::getFPROUND(Node->getOperand(0).getValueType(),
7271 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!");
7272 Lo = ExpandLibCall(LC, Node, true, Hi);
7287 case ISD::FNEARBYINT:
7290 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
7291 switch(Node->getOpcode()) {
7293 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
7294 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
7297 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
7298 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
7301 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
7302 RTLIB::COS_F80, RTLIB::COS_PPCF128);
7305 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
7306 RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
7309 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
7310 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
7313 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
7314 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
7317 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
7318 RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
7321 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
7322 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
7325 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
7326 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
7329 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
7330 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128);
7333 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
7334 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128);
7337 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64,
7338 RTLIB::RINT_F80, RTLIB::RINT_PPCF128);
7340 case ISD::FNEARBYINT:
7341 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
7342 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
7345 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
7346 RTLIB::POW_PPCF128);
7349 LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64, RTLIB::POWI_F80,
7350 RTLIB::POWI_PPCF128);
7352 default: assert(0 && "Unreachable!");
7354 Lo = ExpandLibCall(LC, Node, false, Hi);
7358 if (VT == MVT::ppcf128) {
7360 ExpandOp(Node->getOperand(0), Lo, Tmp);
7361 Hi = DAG.getNode(ISD::FABS, dl, NVT, Tmp);
7362 // lo = hi==fabs(hi) ? lo : -lo;
7363 Lo = DAG.getNode(ISD::SELECT_CC, dl, NVT, Hi, Tmp,
7364 Lo, DAG.getNode(ISD::FNEG, dl, NVT, Lo),
7365 DAG.getCondCode(ISD::SETEQ));
7368 SDValue Mask = (VT == MVT::f64)
7369 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
7370 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
7371 Mask = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Mask);
7372 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
7373 Lo = DAG.getNode(ISD::AND, dl, NVT, Lo, Mask);
7374 if (getTypeAction(NVT) == Expand)
7375 ExpandOp(Lo, Lo, Hi);
7379 if (VT == MVT::ppcf128) {
7380 ExpandOp(Node->getOperand(0), Lo, Hi);
7381 Lo = DAG.getNode(ISD::FNEG, dl, MVT::f64, Lo);
7382 Hi = DAG.getNode(ISD::FNEG, dl, MVT::f64, Hi);
7385 SDValue Mask = (VT == MVT::f64)
7386 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
7387 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
7388 Mask = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Mask);
7389 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
7390 Lo = DAG.getNode(ISD::XOR, dl, NVT, Lo, Mask);
7391 if (getTypeAction(NVT) == Expand)
7392 ExpandOp(Lo, Lo, Hi);
7395 case ISD::FCOPYSIGN: {
7396 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
7397 if (getTypeAction(NVT) == Expand)
7398 ExpandOp(Lo, Lo, Hi);
7401 case ISD::SINT_TO_FP:
7402 case ISD::UINT_TO_FP: {
7403 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
7404 MVT SrcVT = Node->getOperand(0).getValueType();
7406 // Promote the operand if needed. Do this before checking for
7407 // ppcf128 so conversions of i16 and i8 work.
7408 if (getTypeAction(SrcVT) == Promote) {
7409 SDValue Tmp = PromoteOp(Node->getOperand(0));
7411 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Tmp.getValueType(), Tmp,
7412 DAG.getValueType(SrcVT))
7413 : DAG.getZeroExtendInReg(Tmp, dl, SrcVT);
7414 Node = DAG.UpdateNodeOperands(Op, Tmp).getNode();
7415 SrcVT = Node->getOperand(0).getValueType();
7418 if (VT == MVT::ppcf128 && SrcVT == MVT::i32) {
7419 static const uint64_t zero = 0;
7421 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f64,
7422 Node->getOperand(0)));
7423 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7425 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
7426 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f64,
7427 Node->getOperand(0)));
7428 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7429 Hi = DAG.getNode(ISD::BUILD_PAIR, dl, VT, Lo, Hi);
7430 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
7431 ExpandOp(DAG.getNode(ISD::SELECT_CC, dl,
7432 MVT::ppcf128, Node->getOperand(0),
7433 DAG.getConstant(0, MVT::i32),
7434 DAG.getNode(ISD::FADD, dl, MVT::ppcf128, Hi,
7436 APFloat(APInt(128, 2, TwoE32)),
7439 DAG.getCondCode(ISD::SETLT)),
7444 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) {
7445 // si64->ppcf128 done by libcall, below
7446 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
7447 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, dl, MVT::ppcf128,
7448 Node->getOperand(0)), Lo, Hi);
7449 Hi = DAG.getNode(ISD::BUILD_PAIR, dl, VT, Lo, Hi);
7450 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
7451 ExpandOp(DAG.getNode(ISD::SELECT_CC, dl, MVT::ppcf128,
7452 Node->getOperand(0),
7453 DAG.getConstant(0, MVT::i64),
7454 DAG.getNode(ISD::FADD, dl, MVT::ppcf128, Hi,
7456 APFloat(APInt(128, 2, TwoE64)),
7459 DAG.getCondCode(ISD::SETLT)),
7464 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
7465 Node->getOperand(0), dl);
7466 if (getTypeAction(Lo.getValueType()) == Expand)
7467 // float to i32 etc. can be 'expanded' to a single node.
7468 ExpandOp(Lo, Lo, Hi);
7473 // Make sure the resultant values have been legalized themselves, unless this
7474 // is a type that requires multi-step expansion.
7475 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
7476 Lo = LegalizeOp(Lo);
7478 // Don't legalize the high part if it is expanded to a single node.
7479 Hi = LegalizeOp(Hi);
7482 // Remember in a map if the values will be reused later.
7484 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
7485 assert(isNew && "Value already expanded?!?");
7489 /// SplitVectorOp - Given an operand of vector type, break it down into
7490 /// two smaller values, still of vector type.
7491 void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
7493 assert(Op.getValueType().isVector() && "Cannot split non-vector type!");
7494 SDNode *Node = Op.getNode();
7495 DebugLoc dl = Node->getDebugLoc();
7496 unsigned NumElements = Op.getValueType().getVectorNumElements();
7497 assert(NumElements > 1 && "Cannot split a single element vector!");
7499 MVT NewEltVT = Op.getValueType().getVectorElementType();
7501 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
7502 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
7504 MVT NewVT_Lo = MVT::getVectorVT(NewEltVT, NewNumElts_Lo);
7505 MVT NewVT_Hi = MVT::getVectorVT(NewEltVT, NewNumElts_Hi);
7507 // See if we already split it.
7508 std::map<SDValue, std::pair<SDValue, SDValue> >::iterator I
7509 = SplitNodes.find(Op);
7510 if (I != SplitNodes.end()) {
7511 Lo = I->second.first;
7512 Hi = I->second.second;
7516 switch (Node->getOpcode()) {
7521 assert(0 && "Unhandled operation in SplitVectorOp!");
7523 Lo = DAG.getUNDEF(NewVT_Lo);
7524 Hi = DAG.getUNDEF(NewVT_Hi);
7526 case ISD::BUILD_PAIR:
7527 Lo = Node->getOperand(0);
7528 Hi = Node->getOperand(1);
7530 case ISD::INSERT_VECTOR_ELT: {
7531 if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) {
7532 SplitVectorOp(Node->getOperand(0), Lo, Hi);
7533 unsigned Index = Idx->getZExtValue();
7534 SDValue ScalarOp = Node->getOperand(1);
7535 if (Index < NewNumElts_Lo)
7536 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVT_Lo, Lo, ScalarOp,
7537 DAG.getIntPtrConstant(Index));
7539 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVT_Hi, Hi, ScalarOp,
7540 DAG.getIntPtrConstant(Index - NewNumElts_Lo));
7543 SDValue Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0),
7544 Node->getOperand(1),
7545 Node->getOperand(2), dl);
7546 SplitVectorOp(Tmp, Lo, Hi);
7549 case ISD::VECTOR_SHUFFLE: {
7550 // Build the low part.
7551 SDValue Mask = Node->getOperand(2);
7552 SmallVector<SDValue, 8> Ops;
7553 MVT PtrVT = TLI.getPointerTy();
7555 // Insert all of the elements from the input that are needed. We use
7556 // buildvector of extractelement here because the input vectors will have
7557 // to be legalized, so this makes the code simpler.
7558 for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
7559 SDValue IdxNode = Mask.getOperand(i);
7560 if (IdxNode.getOpcode() == ISD::UNDEF) {
7561 Ops.push_back(DAG.getUNDEF(NewEltVT));
7564 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
7565 SDValue InVec = Node->getOperand(0);
7566 if (Idx >= NumElements) {
7567 InVec = Node->getOperand(1);
7570 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewEltVT, InVec,
7571 DAG.getConstant(Idx, PtrVT)));
7573 Lo = DAG.getBUILD_VECTOR(NewVT_Lo, dl, &Ops[0], Ops.size());
7576 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
7577 SDValue IdxNode = Mask.getOperand(i);
7578 if (IdxNode.getOpcode() == ISD::UNDEF) {
7579 Ops.push_back(DAG.getUNDEF(NewEltVT));
7582 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
7583 SDValue InVec = Node->getOperand(0);
7584 if (Idx >= NumElements) {
7585 InVec = Node->getOperand(1);
7588 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewEltVT, InVec,
7589 DAG.getConstant(Idx, PtrVT)));
7591 Hi = DAG.getBUILD_VECTOR(NewVT_Hi, dl, &Ops[0], Ops.size());
7594 case ISD::BUILD_VECTOR: {
7595 SmallVector<SDValue, 8> LoOps(Node->op_begin(),
7596 Node->op_begin()+NewNumElts_Lo);
7597 Lo = DAG.getBUILD_VECTOR(NewVT_Lo, dl, &LoOps[0], LoOps.size());
7599 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
7601 Hi = DAG.getBUILD_VECTOR(NewVT_Hi, dl, &HiOps[0], HiOps.size());
7604 case ISD::CONCAT_VECTORS: {
7605 // FIXME: Handle non-power-of-two vectors?
7606 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
7607 if (NewNumSubvectors == 1) {
7608 Lo = Node->getOperand(0);
7609 Hi = Node->getOperand(1);
7611 SmallVector<SDValue, 8> LoOps(Node->op_begin(),
7612 Node->op_begin()+NewNumSubvectors);
7613 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewVT_Lo,
7614 &LoOps[0], LoOps.size());
7616 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumSubvectors,
7618 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewVT_Hi,
7619 &HiOps[0], HiOps.size());
7623 case ISD::EXTRACT_SUBVECTOR: {
7624 SDValue Vec = Op.getOperand(0);
7625 SDValue Idx = Op.getOperand(1);
7626 MVT IdxVT = Idx.getValueType();
7628 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT_Lo, Vec, Idx);
7629 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx);
7631 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT_Hi, Vec,
7632 DAG.getConstant(CIdx->getZExtValue() + NewNumElts_Lo,
7635 Idx = DAG.getNode(ISD::ADD, dl, IdxVT, Idx,
7636 DAG.getConstant(NewNumElts_Lo, IdxVT));
7637 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT_Hi, Vec, Idx);
7642 SDValue Cond = Node->getOperand(0);
7644 SDValue LL, LH, RL, RH;
7645 SplitVectorOp(Node->getOperand(1), LL, LH);
7646 SplitVectorOp(Node->getOperand(2), RL, RH);
7648 if (Cond.getValueType().isVector()) {
7649 // Handle a vector merge.
7651 SplitVectorOp(Cond, CL, CH);
7652 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, CL, LL, RL);
7653 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, CH, LH, RH);
7655 // Handle a simple select with vector operands.
7656 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, Cond, LL, RL);
7657 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, Cond, LH, RH);
7661 case ISD::SELECT_CC: {
7662 SDValue CondLHS = Node->getOperand(0);
7663 SDValue CondRHS = Node->getOperand(1);
7664 SDValue CondCode = Node->getOperand(4);
7666 SDValue LL, LH, RL, RH;
7667 SplitVectorOp(Node->getOperand(2), LL, LH);
7668 SplitVectorOp(Node->getOperand(3), RL, RH);
7670 // Handle a simple select with vector operands.
7671 Lo = DAG.getNode(ISD::SELECT_CC, dl, NewVT_Lo, CondLHS, CondRHS,
7673 Hi = DAG.getNode(ISD::SELECT_CC, dl, NewVT_Hi, CondLHS, CondRHS,
7678 SDValue LL, LH, RL, RH;
7679 SplitVectorOp(Node->getOperand(0), LL, LH);
7680 SplitVectorOp(Node->getOperand(1), RL, RH);
7681 Lo = DAG.getNode(ISD::VSETCC, dl, NewVT_Lo, LL, RL, Node->getOperand(2));
7682 Hi = DAG.getNode(ISD::VSETCC, dl, NewVT_Hi, LH, RH, Node->getOperand(2));
7704 SDValue LL, LH, RL, RH;
7705 SplitVectorOp(Node->getOperand(0), LL, LH);
7706 SplitVectorOp(Node->getOperand(1), RL, RH);
7708 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, LL, RL);
7709 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, LH, RH);
7715 SplitVectorOp(Node->getOperand(0), L, H);
7717 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, L, Node->getOperand(1));
7718 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, H, Node->getOperand(1));
7734 case ISD::FP_TO_SINT:
7735 case ISD::FP_TO_UINT:
7736 case ISD::SINT_TO_FP:
7737 case ISD::UINT_TO_FP:
7739 case ISD::ANY_EXTEND:
7740 case ISD::SIGN_EXTEND:
7741 case ISD::ZERO_EXTEND:
7742 case ISD::FP_EXTEND: {
7744 SplitVectorOp(Node->getOperand(0), L, H);
7746 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, L);
7747 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, H);
7750 case ISD::CONVERT_RNDSAT: {
7751 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
7753 SplitVectorOp(Node->getOperand(0), L, H);
7754 SDValue DTyOpL = DAG.getValueType(NewVT_Lo);
7755 SDValue DTyOpH = DAG.getValueType(NewVT_Hi);
7756 SDValue STyOpL = DAG.getValueType(L.getValueType());
7757 SDValue STyOpH = DAG.getValueType(H.getValueType());
7759 SDValue RndOp = Node->getOperand(3);
7760 SDValue SatOp = Node->getOperand(4);
7762 Lo = DAG.getConvertRndSat(NewVT_Lo, dl, L, DTyOpL, STyOpL,
7763 RndOp, SatOp, CvtCode);
7764 Hi = DAG.getConvertRndSat(NewVT_Hi, dl, H, DTyOpH, STyOpH,
7765 RndOp, SatOp, CvtCode);
7769 LoadSDNode *LD = cast<LoadSDNode>(Node);
7770 SDValue Ch = LD->getChain();
7771 SDValue Ptr = LD->getBasePtr();
7772 ISD::LoadExtType ExtType = LD->getExtensionType();
7773 const Value *SV = LD->getSrcValue();
7774 int SVOffset = LD->getSrcValueOffset();
7775 MVT MemoryVT = LD->getMemoryVT();
7776 unsigned Alignment = LD->getAlignment();
7777 bool isVolatile = LD->isVolatile();
7779 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
7780 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
7782 MVT MemNewEltVT = MemoryVT.getVectorElementType();
7783 MVT MemNewVT_Lo = MVT::getVectorVT(MemNewEltVT, NewNumElts_Lo);
7784 MVT MemNewVT_Hi = MVT::getVectorVT(MemNewEltVT, NewNumElts_Hi);
7786 Lo = DAG.getLoad(ISD::UNINDEXED, dl, ExtType,
7787 NewVT_Lo, Ch, Ptr, Offset,
7788 SV, SVOffset, MemNewVT_Lo, isVolatile, Alignment);
7789 unsigned IncrementSize = NewNumElts_Lo * MemNewEltVT.getSizeInBits()/8;
7790 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
7791 DAG.getIntPtrConstant(IncrementSize));
7792 SVOffset += IncrementSize;
7793 Alignment = MinAlign(Alignment, IncrementSize);
7794 Hi = DAG.getLoad(ISD::UNINDEXED, dl, ExtType,
7795 NewVT_Hi, Ch, Ptr, Offset,
7796 SV, SVOffset, MemNewVT_Hi, isVolatile, Alignment);
7798 // Build a factor node to remember that this load is independent of the
7800 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
7803 // Remember that we legalized the chain.
7804 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
7807 case ISD::BIT_CONVERT: {
7808 // We know the result is a vector. The input may be either a vector or a
7810 SDValue InOp = Node->getOperand(0);
7811 if (!InOp.getValueType().isVector() ||
7812 InOp.getValueType().getVectorNumElements() == 1) {
7813 // The input is a scalar or single-element vector.
7814 // Lower to a store/load so that it can be split.
7815 // FIXME: this could be improved probably.
7816 unsigned LdAlign = TLI.getTargetData()->getPrefTypeAlignment(
7817 Op.getValueType().getTypeForMVT());
7818 SDValue Ptr = DAG.CreateStackTemporary(InOp.getValueType(), LdAlign);
7819 int FI = cast<FrameIndexSDNode>(Ptr.getNode())->getIndex();
7821 SDValue St = DAG.getStore(DAG.getEntryNode(), dl,
7823 PseudoSourceValue::getFixedStack(FI), 0);
7824 InOp = DAG.getLoad(Op.getValueType(), dl, St, Ptr,
7825 PseudoSourceValue::getFixedStack(FI), 0);
7827 // Split the vector and convert each of the pieces now.
7828 SplitVectorOp(InOp, Lo, Hi);
7829 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT_Lo, Lo);
7830 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT_Hi, Hi);
7835 // Remember in a map if the values will be reused later.
7837 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
7838 assert(isNew && "Value already split?!?");
7843 /// ScalarizeVectorOp - Given an operand of single-element vector type
7844 /// (e.g. v1f32), convert it into the equivalent operation that returns a
7845 /// scalar (e.g. f32) value.
7846 SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) {
7847 assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!");
7848 SDNode *Node = Op.getNode();
7849 DebugLoc dl = Node->getDebugLoc();
7850 MVT NewVT = Op.getValueType().getVectorElementType();
7851 assert(Op.getValueType().getVectorNumElements() == 1);
7853 // See if we already scalarized it.
7854 std::map<SDValue, SDValue>::iterator I = ScalarizedNodes.find(Op);
7855 if (I != ScalarizedNodes.end()) return I->second;
7858 switch (Node->getOpcode()) {
7861 Node->dump(&DAG); cerr << "\n";
7863 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
7880 Result = DAG.getNode(Node->getOpcode(), dl,
7882 ScalarizeVectorOp(Node->getOperand(0)),
7883 ScalarizeVectorOp(Node->getOperand(1)));
7895 case ISD::FP_TO_SINT:
7896 case ISD::FP_TO_UINT:
7897 case ISD::SINT_TO_FP:
7898 case ISD::UINT_TO_FP:
7899 case ISD::SIGN_EXTEND:
7900 case ISD::ZERO_EXTEND:
7901 case ISD::ANY_EXTEND:
7903 case ISD::FP_EXTEND:
7904 Result = DAG.getNode(Node->getOpcode(), dl,
7906 ScalarizeVectorOp(Node->getOperand(0)));
7908 case ISD::CONVERT_RNDSAT: {
7909 SDValue Op0 = ScalarizeVectorOp(Node->getOperand(0));
7910 Result = DAG.getConvertRndSat(NewVT, dl, Op0,
7911 DAG.getValueType(NewVT),
7912 DAG.getValueType(Op0.getValueType()),
7913 Node->getOperand(3),
7914 Node->getOperand(4),
7915 cast<CvtRndSatSDNode>(Node)->getCvtCode());
7920 Result = DAG.getNode(Node->getOpcode(), dl,
7922 ScalarizeVectorOp(Node->getOperand(0)),
7923 Node->getOperand(1));
7926 LoadSDNode *LD = cast<LoadSDNode>(Node);
7927 SDValue Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
7928 SDValue Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
7929 ISD::LoadExtType ExtType = LD->getExtensionType();
7930 const Value *SV = LD->getSrcValue();
7931 int SVOffset = LD->getSrcValueOffset();
7932 MVT MemoryVT = LD->getMemoryVT();
7933 unsigned Alignment = LD->getAlignment();
7934 bool isVolatile = LD->isVolatile();
7936 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
7937 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
7939 Result = DAG.getLoad(ISD::UNINDEXED, dl, ExtType,
7940 NewVT, Ch, Ptr, Offset, SV, SVOffset,
7941 MemoryVT.getVectorElementType(),
7942 isVolatile, Alignment);
7944 // Remember that we legalized the chain.
7945 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
7948 case ISD::BUILD_VECTOR:
7949 Result = Node->getOperand(0);
7951 case ISD::INSERT_VECTOR_ELT:
7952 // Returning the inserted scalar element.
7953 Result = Node->getOperand(1);
7955 case ISD::CONCAT_VECTORS:
7956 assert(Node->getOperand(0).getValueType() == NewVT &&
7957 "Concat of non-legal vectors not yet supported!");
7958 Result = Node->getOperand(0);
7960 case ISD::VECTOR_SHUFFLE: {
7961 // Figure out if the scalar is the LHS or RHS and return it.
7962 SDValue EltNum = Node->getOperand(2).getOperand(0);
7963 if (cast<ConstantSDNode>(EltNum)->getZExtValue())
7964 Result = ScalarizeVectorOp(Node->getOperand(1));
7966 Result = ScalarizeVectorOp(Node->getOperand(0));
7969 case ISD::EXTRACT_SUBVECTOR:
7970 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT,
7971 Node->getOperand(0), Node->getOperand(1));
7973 case ISD::BIT_CONVERT: {
7974 SDValue Op0 = Op.getOperand(0);
7975 if (Op0.getValueType().getVectorNumElements() == 1)
7976 Op0 = ScalarizeVectorOp(Op0);
7977 Result = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, Op0);
7981 Result = DAG.getNode(ISD::SELECT, dl, NewVT, Op.getOperand(0),
7982 ScalarizeVectorOp(Op.getOperand(1)),
7983 ScalarizeVectorOp(Op.getOperand(2)));
7985 case ISD::SELECT_CC:
7986 Result = DAG.getNode(ISD::SELECT_CC, dl, NewVT, Node->getOperand(0),
7987 Node->getOperand(1),
7988 ScalarizeVectorOp(Op.getOperand(2)),
7989 ScalarizeVectorOp(Op.getOperand(3)),
7990 Node->getOperand(4));
7993 SDValue Op0 = ScalarizeVectorOp(Op.getOperand(0));
7994 SDValue Op1 = ScalarizeVectorOp(Op.getOperand(1));
7995 Result = DAG.getNode(ISD::SETCC, dl,
7996 TLI.getSetCCResultType(Op0.getValueType()),
7997 Op0, Op1, Op.getOperand(2));
7998 Result = DAG.getNode(ISD::SELECT, dl, NewVT, Result,
7999 DAG.getConstant(-1ULL, NewVT),
8000 DAG.getConstant(0ULL, NewVT));
8005 if (TLI.isTypeLegal(NewVT))
8006 Result = LegalizeOp(Result);
8007 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
8008 assert(isNew && "Value already scalarized?");
8014 SDValue SelectionDAGLegalize::WidenVectorOp(SDValue Op, MVT WidenVT) {
8015 std::map<SDValue, SDValue>::iterator I = WidenNodes.find(Op);
8016 if (I != WidenNodes.end()) return I->second;
8018 MVT VT = Op.getValueType();
8019 assert(VT.isVector() && "Cannot widen non-vector type!");
8022 SDNode *Node = Op.getNode();
8023 DebugLoc dl = Node->getDebugLoc();
8024 MVT EVT = VT.getVectorElementType();
8026 unsigned NumElts = VT.getVectorNumElements();
8027 unsigned NewNumElts = WidenVT.getVectorNumElements();
8028 assert(NewNumElts > NumElts && "Cannot widen to smaller type!");
8029 assert(NewNumElts < 17);
8031 // When widen is called, it is assumed that it is more efficient to use a
8032 // wide type. The default action is to widen to operation to a wider legal
8033 // vector type and then do the operation if it is legal by calling LegalizeOp
8034 // again. If there is no vector equivalent, we will unroll the operation, do
8035 // it, and rebuild the vector. If most of the operations are vectorizible to
8036 // the legal type, the resulting code will be more efficient. If this is not
8037 // the case, the resulting code will preform badly as we end up generating
8038 // code to pack/unpack the results. It is the function that calls widen
8039 // that is responsible for seeing this doesn't happen.
8040 switch (Node->getOpcode()) {
8045 assert(0 && "Unexpected operation in WidenVectorOp!");
8047 case ISD::CopyFromReg:
8048 assert(0 && "CopyFromReg doesn't need widening!");
8050 case ISD::ConstantFP:
8051 // To build a vector of these elements, clients should call BuildVector
8052 // and with each element instead of creating a node with a vector type
8053 assert(0 && "Unexpected operation in WidenVectorOp!");
8055 // Variable Arguments with vector types doesn't make any sense to me
8056 assert(0 && "Unexpected operation in WidenVectorOp!");
8059 Result = DAG.getUNDEF(WidenVT);
8061 case ISD::BUILD_VECTOR: {
8062 // Build a vector with undefined for the new nodes
8063 SDValueVector NewOps(Node->op_begin(), Node->op_end());
8064 for (unsigned i = NumElts; i < NewNumElts; ++i) {
8065 NewOps.push_back(DAG.getUNDEF(EVT));
8067 Result = DAG.getBUILD_VECTOR(WidenVT, dl, &NewOps[0], NewOps.size());
8070 case ISD::INSERT_VECTOR_ELT: {
8071 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8072 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, WidenVT, Tmp1,
8073 Node->getOperand(1), Node->getOperand(2));
8076 case ISD::VECTOR_SHUFFLE: {
8077 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8078 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT);
8079 // VECTOR_SHUFFLE 3rd operand must be a constant build vector that is
8080 // used as permutation array. We build the vector here instead of widening
8081 // because we don't want to legalize and have it turned to something else.
8082 SDValue PermOp = Node->getOperand(2);
8083 SDValueVector NewOps;
8084 MVT PVT = PermOp.getValueType().getVectorElementType();
8085 for (unsigned i = 0; i < NumElts; ++i) {
8086 if (PermOp.getOperand(i).getOpcode() == ISD::UNDEF) {
8087 NewOps.push_back(PermOp.getOperand(i));
8090 cast<ConstantSDNode>(PermOp.getOperand(i))->getZExtValue();
8091 if (Idx < NumElts) {
8092 NewOps.push_back(PermOp.getOperand(i));
8095 NewOps.push_back(DAG.getConstant(Idx + NewNumElts - NumElts,
8096 PermOp.getOperand(i).getValueType()));
8100 for (unsigned i = NumElts; i < NewNumElts; ++i) {
8101 NewOps.push_back(DAG.getUNDEF(PVT));
8104 SDValue Tmp3 = DAG.getBUILD_VECTOR(MVT::getVectorVT(PVT, NewOps.size()), dl,
8105 &NewOps[0], NewOps.size());
8107 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, WidenVT, Tmp1, Tmp2, Tmp3);
8111 // If the load widen returns true, we can use a single load for the
8112 // vector. Otherwise, it is returning a token factor for multiple
8115 if (LoadWidenVectorOp(Result, TFOp, Op, WidenVT))
8116 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TFOp.getValue(1)));
8118 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TFOp.getValue(0)));
8122 case ISD::BIT_CONVERT: {
8123 SDValue Tmp1 = Node->getOperand(0);
8124 // Converts between two different types so we need to determine
8125 // the correct widen type for the input operand.
8126 MVT InVT = Tmp1.getValueType();
8127 unsigned WidenSize = WidenVT.getSizeInBits();
8128 if (InVT.isVector()) {
8129 MVT InEltVT = InVT.getVectorElementType();
8130 unsigned InEltSize = InEltVT.getSizeInBits();
8131 assert(WidenSize % InEltSize == 0 &&
8132 "can not widen bit convert that are not multiple of element type");
8133 MVT NewInWidenVT = MVT::getVectorVT(InEltVT, WidenSize / InEltSize);
8134 Tmp1 = WidenVectorOp(Tmp1, NewInWidenVT);
8135 assert(Tmp1.getValueType().getSizeInBits() == WidenVT.getSizeInBits());
8136 Result = DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, Tmp1);
8138 // If the result size is a multiple of the input size, widen the input
8139 // and then convert.
8140 unsigned InSize = InVT.getSizeInBits();
8141 assert(WidenSize % InSize == 0 &&
8142 "can not widen bit convert that are not multiple of element type");
8143 unsigned NewNumElts = WidenSize / InSize;
8144 SmallVector<SDValue, 16> Ops(NewNumElts);
8145 SDValue UndefVal = DAG.getUNDEF(InVT);
8147 for (unsigned i = 1; i < NewNumElts; ++i)
8150 MVT NewInVT = MVT::getVectorVT(InVT, NewNumElts);
8151 Result = DAG.getBUILD_VECTOR(NewInVT, dl, &Ops[0], NewNumElts);
8152 Result = DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, Result);
8157 case ISD::SINT_TO_FP:
8158 case ISD::UINT_TO_FP:
8159 case ISD::FP_TO_SINT:
8160 case ISD::FP_TO_UINT:
8161 case ISD::FP_ROUND: {
8162 SDValue Tmp1 = Node->getOperand(0);
8163 // Converts between two different types so we need to determine
8164 // the correct widen type for the input operand.
8165 MVT TVT = Tmp1.getValueType();
8166 assert(TVT.isVector() && "can not widen non vector type");
8167 MVT TEVT = TVT.getVectorElementType();
8168 MVT TWidenVT = MVT::getVectorVT(TEVT, NewNumElts);
8169 Tmp1 = WidenVectorOp(Tmp1, TWidenVT);
8170 assert(Tmp1.getValueType().getVectorNumElements() == NewNumElts);
8171 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1);
8175 case ISD::FP_EXTEND:
8176 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
8178 case ISD::SIGN_EXTEND:
8179 case ISD::ZERO_EXTEND:
8180 case ISD::ANY_EXTEND:
8181 case ISD::SIGN_EXTEND_INREG:
8190 // Unary op widening
8192 Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8193 assert(Tmp1.getValueType() == WidenVT);
8194 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1);
8197 case ISD::CONVERT_RNDSAT: {
8198 SDValue RndOp = Node->getOperand(3);
8199 SDValue SatOp = Node->getOperand(4);
8200 SDValue SrcOp = Node->getOperand(0);
8202 // Converts between two different types so we need to determine
8203 // the correct widen type for the input operand.
8204 MVT SVT = SrcOp.getValueType();
8205 assert(SVT.isVector() && "can not widen non vector type");
8206 MVT SEVT = SVT.getVectorElementType();
8207 MVT SWidenVT = MVT::getVectorVT(SEVT, NewNumElts);
8209 SrcOp = WidenVectorOp(SrcOp, SWidenVT);
8210 assert(SrcOp.getValueType() == WidenVT);
8211 SDValue DTyOp = DAG.getValueType(WidenVT);
8212 SDValue STyOp = DAG.getValueType(SrcOp.getValueType());
8213 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
8215 Result = DAG.getConvertRndSat(WidenVT, dl, SrcOp, DTyOp, STyOp,
8216 RndOp, SatOp, CvtCode);
8236 case ISD::FCOPYSIGN:
8240 // Binary op widening
8241 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8242 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT);
8243 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT);
8244 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1, Tmp2);
8251 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8252 assert(Tmp1.getValueType() == WidenVT);
8253 SDValue ShOp = Node->getOperand(1);
8254 MVT ShVT = ShOp.getValueType();
8255 MVT NewShVT = MVT::getVectorVT(ShVT.getVectorElementType(),
8256 WidenVT.getVectorNumElements());
8257 ShOp = WidenVectorOp(ShOp, NewShVT);
8258 assert(ShOp.getValueType() == NewShVT);
8259 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1, ShOp);
8263 case ISD::EXTRACT_VECTOR_ELT: {
8264 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8265 assert(Tmp1.getValueType() == WidenVT);
8266 Result = DAG.getNode(Node->getOpcode(), dl, EVT, Tmp1, Node->getOperand(1));
8269 case ISD::CONCAT_VECTORS: {
8270 // We concurrently support only widen on a multiple of the incoming vector.
8271 // We could widen on a multiple of the incoming operand if necessary.
8272 unsigned NumConcat = NewNumElts / NumElts;
8273 assert(NewNumElts % NumElts == 0 && "Can widen only a multiple of vector");
8274 SDValue UndefVal = DAG.getUNDEF(VT);
8275 SmallVector<SDValue, 8> MOps;
8277 for (unsigned i = 1; i != NumConcat; ++i) {
8278 MOps.push_back(UndefVal);
8280 Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
8281 &MOps[0], MOps.size()));
8284 case ISD::EXTRACT_SUBVECTOR: {
8285 SDValue Tmp1 = Node->getOperand(0);
8286 SDValue Idx = Node->getOperand(1);
8287 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx);
8288 if (CIdx && CIdx->getZExtValue() == 0) {
8289 // Since we are access the start of the vector, the incoming
8290 // vector type might be the proper.
8291 MVT Tmp1VT = Tmp1.getValueType();
8292 if (Tmp1VT == WidenVT)
8295 unsigned Tmp1VTNumElts = Tmp1VT.getVectorNumElements();
8296 if (Tmp1VTNumElts < NewNumElts)
8297 Result = WidenVectorOp(Tmp1, WidenVT);
8299 Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, Tmp1, Idx);
8301 } else if (NewNumElts % NumElts == 0) {
8302 // Widen the extracted subvector.
8303 unsigned NumConcat = NewNumElts / NumElts;
8304 SDValue UndefVal = DAG.getUNDEF(VT);
8305 SmallVector<SDValue, 8> MOps;
8307 for (unsigned i = 1; i != NumConcat; ++i) {
8308 MOps.push_back(UndefVal);
8310 Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
8311 &MOps[0], MOps.size()));
8313 assert(0 && "can not widen extract subvector");
8314 // This could be implemented using insert and build vector but I would
8315 // like to see when this happens.
8321 // Determine new condition widen type and widen
8322 SDValue Cond1 = Node->getOperand(0);
8323 MVT CondVT = Cond1.getValueType();
8324 assert(CondVT.isVector() && "can not widen non vector type");
8325 MVT CondEVT = CondVT.getVectorElementType();
8326 MVT CondWidenVT = MVT::getVectorVT(CondEVT, NewNumElts);
8327 Cond1 = WidenVectorOp(Cond1, CondWidenVT);
8328 assert(Cond1.getValueType() == CondWidenVT && "Condition not widen");
8330 SDValue Tmp1 = WidenVectorOp(Node->getOperand(1), WidenVT);
8331 SDValue Tmp2 = WidenVectorOp(Node->getOperand(2), WidenVT);
8332 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT);
8333 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Cond1, Tmp1, Tmp2);
8337 case ISD::SELECT_CC: {
8338 // Determine new condition widen type and widen
8339 SDValue Cond1 = Node->getOperand(0);
8340 SDValue Cond2 = Node->getOperand(1);
8341 MVT CondVT = Cond1.getValueType();
8342 assert(CondVT.isVector() && "can not widen non vector type");
8343 assert(CondVT == Cond2.getValueType() && "mismatch lhs/rhs");
8344 MVT CondEVT = CondVT.getVectorElementType();
8345 MVT CondWidenVT = MVT::getVectorVT(CondEVT, NewNumElts);
8346 Cond1 = WidenVectorOp(Cond1, CondWidenVT);
8347 Cond2 = WidenVectorOp(Cond2, CondWidenVT);
8348 assert(Cond1.getValueType() == CondWidenVT &&
8349 Cond2.getValueType() == CondWidenVT && "condition not widen");
8351 SDValue Tmp1 = WidenVectorOp(Node->getOperand(2), WidenVT);
8352 SDValue Tmp2 = WidenVectorOp(Node->getOperand(3), WidenVT);
8353 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT &&
8354 "operands not widen");
8355 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Cond1, Cond2, Tmp1,
8356 Tmp2, Node->getOperand(4));
8360 // Determine widen for the operand
8361 SDValue Tmp1 = Node->getOperand(0);
8362 MVT TmpVT = Tmp1.getValueType();
8363 assert(TmpVT.isVector() && "can not widen non vector type");
8364 MVT TmpEVT = TmpVT.getVectorElementType();
8365 MVT TmpWidenVT = MVT::getVectorVT(TmpEVT, NewNumElts);
8366 Tmp1 = WidenVectorOp(Tmp1, TmpWidenVT);
8367 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), TmpWidenVT);
8368 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1, Tmp2,
8369 Node->getOperand(2));
8372 case ISD::ATOMIC_CMP_SWAP:
8373 case ISD::ATOMIC_LOAD_ADD:
8374 case ISD::ATOMIC_LOAD_SUB:
8375 case ISD::ATOMIC_LOAD_AND:
8376 case ISD::ATOMIC_LOAD_OR:
8377 case ISD::ATOMIC_LOAD_XOR:
8378 case ISD::ATOMIC_LOAD_NAND:
8379 case ISD::ATOMIC_LOAD_MIN:
8380 case ISD::ATOMIC_LOAD_MAX:
8381 case ISD::ATOMIC_LOAD_UMIN:
8382 case ISD::ATOMIC_LOAD_UMAX:
8383 case ISD::ATOMIC_SWAP: {
8384 // For now, we assume that using vectors for these operations don't make
8385 // much sense so we just split it. We return an empty result
8387 SplitVectorOp(Op, X, Y);
8392 } // end switch (Node->getOpcode())
8394 assert(Result.getNode() && "Didn't set a result!");
8396 Result = LegalizeOp(Result);
8398 AddWidenedOperand(Op, Result);
8402 // Utility function to find a legal vector type and its associated element
8403 // type from a preferred width and whose vector type must be the same size
8405 // TLI: Target lowering used to determine legal types
8406 // Width: Preferred width of element type
8407 // VVT: Vector value type whose size we must match.
8408 // Returns VecEVT and EVT - the vector type and its associated element type
8409 static void FindWidenVecType(const TargetLowering &TLI, unsigned Width, MVT VVT,
8410 MVT& EVT, MVT& VecEVT) {
8411 // We start with the preferred width, make it a power of 2 and see if
8412 // we can find a vector type of that width. If not, we reduce it by
8413 // another power of 2. If we have widen the type, a vector of bytes should
8415 assert(TLI.isTypeLegal(VVT));
8416 unsigned EWidth = Width + 1;
8419 EWidth = (1 << Log2_32(EWidth-1));
8420 EVT = MVT::getIntegerVT(EWidth);
8421 unsigned NumEVT = VVT.getSizeInBits()/EWidth;
8422 VecEVT = MVT::getVectorVT(EVT, NumEVT);
8423 } while (!TLI.isTypeLegal(VecEVT) ||
8424 VVT.getSizeInBits() != VecEVT.getSizeInBits());
8427 SDValue SelectionDAGLegalize::genWidenVectorLoads(SDValueVector& LdChain,
8437 // We assume that we have good rules to handle loading power of two loads so
8438 // we break down the operations to power of 2 loads. The strategy is to
8439 // load the largest power of 2 that we can easily transform to a legal vector
8440 // and then insert into that vector, and the cast the result into the legal
8441 // vector that we want. This avoids unnecessary stack converts.
8442 // TODO: If the Ldwidth is legal, alignment is the same as the LdWidth, and
8443 // the load is nonvolatile, we an use a wider load for the value.
8444 // Find a vector length we can load a large chunk
8447 FindWidenVecType(TLI, LdWidth, ResType, EVT, VecEVT);
8448 EVTWidth = EVT.getSizeInBits();
8450 SDValue LdOp = DAG.getLoad(EVT, dl, Chain, BasePtr, SV, SVOffset,
8451 isVolatile, Alignment);
8452 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecEVT, LdOp);
8453 LdChain.push_back(LdOp.getValue(1));
8455 // Check if we can load the element with one instruction
8456 if (LdWidth == EVTWidth) {
8457 return DAG.getNode(ISD::BIT_CONVERT, dl, ResType, VecOp);
8460 // The vector element order is endianness dependent.
8462 LdWidth -= EVTWidth;
8463 unsigned Offset = 0;
8465 while (LdWidth > 0) {
8466 unsigned Increment = EVTWidth / 8;
8467 Offset += Increment;
8468 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
8469 DAG.getIntPtrConstant(Increment));
8471 if (LdWidth < EVTWidth) {
8472 // Our current type we are using is too large, use a smaller size by
8473 // using a smaller power of 2
8474 unsigned oEVTWidth = EVTWidth;
8475 FindWidenVecType(TLI, LdWidth, ResType, EVT, VecEVT);
8476 EVTWidth = EVT.getSizeInBits();
8477 // Readjust position and vector position based on new load type
8478 Idx = Idx * (oEVTWidth/EVTWidth);
8479 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, VecEVT, VecOp);
8482 SDValue LdOp = DAG.getLoad(EVT, dl, Chain, BasePtr, SV,
8483 SVOffset+Offset, isVolatile,
8484 MinAlign(Alignment, Offset));
8485 LdChain.push_back(LdOp.getValue(1));
8486 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VecEVT, VecOp, LdOp,
8487 DAG.getIntPtrConstant(Idx++));
8489 LdWidth -= EVTWidth;
8492 return DAG.getNode(ISD::BIT_CONVERT, dl, ResType, VecOp);
8495 bool SelectionDAGLegalize::LoadWidenVectorOp(SDValue& Result,
8499 // TODO: Add support for ConcatVec and the ability to load many vector
8500 // types (e.g., v4i8). This will not work when a vector register
8501 // to memory mapping is strange (e.g., vector elements are not
8502 // stored in some sequential order).
8504 // It must be true that the widen vector type is bigger than where
8505 // we need to load from.
8506 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
8507 MVT LdVT = LD->getMemoryVT();
8508 DebugLoc dl = LD->getDebugLoc();
8509 assert(LdVT.isVector() && NVT.isVector());
8510 assert(LdVT.getVectorElementType() == NVT.getVectorElementType());
8513 SDValue Chain = LD->getChain();
8514 SDValue BasePtr = LD->getBasePtr();
8515 int SVOffset = LD->getSrcValueOffset();
8516 unsigned Alignment = LD->getAlignment();
8517 bool isVolatile = LD->isVolatile();
8518 const Value *SV = LD->getSrcValue();
8519 unsigned int LdWidth = LdVT.getSizeInBits();
8521 // Load value as a large register
8522 SDValueVector LdChain;
8523 Result = genWidenVectorLoads(LdChain, Chain, BasePtr, SV, SVOffset,
8524 Alignment, isVolatile, LdWidth, NVT, dl);
8526 if (LdChain.size() == 1) {
8531 TFOp=DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
8532 &LdChain[0], LdChain.size());
8538 void SelectionDAGLegalize::genWidenVectorStores(SDValueVector& StChain,
8548 // Breaks the stores into a series of power of 2 width stores. For any
8549 // width, we convert the vector to the vector of element size that we
8550 // want to store. This avoids requiring a stack convert.
8552 // Find a width of the element type we can store with
8553 MVT VVT = ValOp.getValueType();
8556 FindWidenVecType(TLI, StWidth, VVT, EVT, VecEVT);
8557 EVTWidth = EVT.getSizeInBits();
8559 SDValue VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, VecEVT, ValOp);
8560 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT, VecOp,
8561 DAG.getIntPtrConstant(0));
8562 SDValue StOp = DAG.getStore(Chain, dl, EOp, BasePtr, SV, SVOffset,
8563 isVolatile, Alignment);
8564 StChain.push_back(StOp);
8566 // Check if we are done
8567 if (StWidth == EVTWidth) {
8572 StWidth -= EVTWidth;
8573 unsigned Offset = 0;
8575 while (StWidth > 0) {
8576 unsigned Increment = EVTWidth / 8;
8577 Offset += Increment;
8578 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
8579 DAG.getIntPtrConstant(Increment));
8581 if (StWidth < EVTWidth) {
8582 // Our current type we are using is too large, use a smaller size by
8583 // using a smaller power of 2
8584 unsigned oEVTWidth = EVTWidth;
8585 FindWidenVecType(TLI, StWidth, VVT, EVT, VecEVT);
8586 EVTWidth = EVT.getSizeInBits();
8587 // Readjust position and vector position based on new load type
8588 Idx = Idx * (oEVTWidth/EVTWidth);
8589 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, VecEVT, VecOp);
8592 EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT, VecOp,
8593 DAG.getIntPtrConstant(Idx++));
8594 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr, SV,
8595 SVOffset + Offset, isVolatile,
8596 MinAlign(Alignment, Offset)));
8597 StWidth -= EVTWidth;
8602 SDValue SelectionDAGLegalize::StoreWidenVectorOp(StoreSDNode *ST,
8605 // TODO: It might be cleaner if we can use SplitVector and have more legal
8606 // vector types that can be stored into memory (e.g., v4xi8 can
8607 // be stored as a word). This will not work when a vector register
8608 // to memory mapping is strange (e.g., vector elements are not
8609 // stored in some sequential order).
8611 MVT StVT = ST->getMemoryVT();
8612 SDValue ValOp = ST->getValue();
8613 DebugLoc dl = ST->getDebugLoc();
8615 // Check if we have widen this node with another value
8616 std::map<SDValue, SDValue>::iterator I = WidenNodes.find(ValOp);
8617 if (I != WidenNodes.end())
8620 MVT VVT = ValOp.getValueType();
8622 // It must be true that we the widen vector type is bigger than where
8623 // we need to store.
8624 assert(StVT.isVector() && VVT.isVector());
8625 assert(StVT.bitsLT(VVT));
8626 assert(StVT.getVectorElementType() == VVT.getVectorElementType());
8629 SDValueVector StChain;
8630 genWidenVectorStores(StChain, Chain, BasePtr, ST->getSrcValue(),
8631 ST->getSrcValueOffset(), ST->getAlignment(),
8632 ST->isVolatile(), ValOp, StVT.getSizeInBits(), dl);
8633 if (StChain.size() == 1)
8636 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
8637 &StChain[0], StChain.size());
8641 // SelectionDAG::Legalize - This is the entry point for the file.
8643 void SelectionDAG::Legalize(bool TypesNeedLegalizing) {
8644 /// run - This is the main entry point to this class.
8646 SelectionDAGLegalize(*this, TypesNeedLegalizing).LegalizeDAG();