1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/CodeGen/PseudoSourceValue.h"
20 #include "llvm/Target/TargetFrameInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/Target/TargetData.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/Target/TargetSubtarget.h"
26 #include "llvm/CallingConv.h"
27 #include "llvm/Constants.h"
28 #include "llvm/DerivedTypes.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Compiler.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/ADT/DenseMap.h"
33 #include "llvm/ADT/SmallVector.h"
34 #include "llvm/ADT/SmallPtrSet.h"
38 //===----------------------------------------------------------------------===//
39 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
40 /// hacks on it until the target machine can handle it. This involves
41 /// eliminating value sizes the machine cannot handle (promoting small sizes to
42 /// large sizes or splitting up large values into small values) as well as
43 /// eliminating operations the machine cannot handle.
45 /// This code also does a small amount of optimization and recognition of idioms
46 /// as part of its processing. For example, if a target does not support a
47 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
48 /// will attempt merge setcc and brc instructions into brcc's.
51 class VISIBILITY_HIDDEN SelectionDAGLegalize {
55 // Libcall insertion helpers.
57 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
58 /// legalized. We use this to ensure that calls are properly serialized
59 /// against each other, including inserted libcalls.
60 SDValue LastCALLSEQ_END;
62 /// IsLegalizingCall - This member is used *only* for purposes of providing
63 /// helpful assertions that a libcall isn't created while another call is
64 /// being legalized (which could lead to non-serialized call sequences).
65 bool IsLegalizingCall;
68 Legal, // The target natively supports this operation.
69 Promote, // This operation should be executed in a larger type.
70 Expand // Try to expand this to other ops, otherwise use a libcall.
73 /// ValueTypeActions - This is a bitvector that contains two bits for each
74 /// value type, where the two bits correspond to the LegalizeAction enum.
75 /// This can be queried with "getTypeAction(VT)".
76 TargetLowering::ValueTypeActionImpl ValueTypeActions;
78 /// LegalizedNodes - For nodes that are of legal width, and that have more
79 /// than one use, this map indicates what regularized operand to use. This
80 /// allows us to avoid legalizing the same thing more than once.
81 DenseMap<SDValue, SDValue> LegalizedNodes;
83 /// PromotedNodes - For nodes that are below legal width, and that have more
84 /// than one use, this map indicates what promoted value to use. This allows
85 /// us to avoid promoting the same thing more than once.
86 DenseMap<SDValue, SDValue> PromotedNodes;
88 /// ExpandedNodes - For nodes that need to be expanded this map indicates
89 /// which which operands are the expanded version of the input. This allows
90 /// us to avoid expanding the same node more than once.
91 DenseMap<SDValue, std::pair<SDValue, SDValue> > ExpandedNodes;
93 /// SplitNodes - For vector nodes that need to be split, this map indicates
94 /// which which operands are the split version of the input. This allows us
95 /// to avoid splitting the same node more than once.
96 std::map<SDValue, std::pair<SDValue, SDValue> > SplitNodes;
98 /// ScalarizedNodes - For nodes that need to be converted from vector types to
99 /// scalar types, this contains the mapping of ones we have already
100 /// processed to the result.
101 std::map<SDValue, SDValue> ScalarizedNodes;
103 void AddLegalizedOperand(SDValue From, SDValue To) {
104 LegalizedNodes.insert(std::make_pair(From, To));
105 // If someone requests legalization of the new node, return itself.
107 LegalizedNodes.insert(std::make_pair(To, To));
109 void AddPromotedOperand(SDValue From, SDValue To) {
110 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
111 assert(isNew && "Got into the map somehow?");
112 // If someone requests legalization of the new node, return itself.
113 LegalizedNodes.insert(std::make_pair(To, To));
117 explicit SelectionDAGLegalize(SelectionDAG &DAG);
119 /// getTypeAction - Return how we should legalize values of this type, either
120 /// it is already legal or we need to expand it into multiple registers of
121 /// smaller integer type, or we need to promote it to a larger type.
122 LegalizeAction getTypeAction(MVT VT) const {
123 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
126 /// isTypeLegal - Return true if this type is legal on this target.
128 bool isTypeLegal(MVT VT) const {
129 return getTypeAction(VT) == Legal;
135 /// HandleOp - Legalize, Promote, or Expand the specified operand as
136 /// appropriate for its type.
137 void HandleOp(SDValue Op);
139 /// LegalizeOp - We know that the specified value has a legal type.
140 /// Recursively ensure that the operands have legal types, then return the
142 SDValue LegalizeOp(SDValue O);
144 /// UnrollVectorOp - We know that the given vector has a legal type, however
145 /// the operation it performs is not legal and is an operation that we have
146 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
147 /// operating on each element individually.
148 SDValue UnrollVectorOp(SDValue O);
150 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
151 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
152 /// is necessary to spill the vector being inserted into to memory, perform
153 /// the insert there, and then read the result back.
154 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
157 /// PromoteOp - Given an operation that produces a value in an invalid type,
158 /// promote it to compute the value into a larger type. The produced value
159 /// will have the correct bits for the low portion of the register, but no
160 /// guarantee is made about the top bits: it may be zero, sign-extended, or
162 SDValue PromoteOp(SDValue O);
164 /// ExpandOp - Expand the specified SDValue into its two component pieces
165 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
166 /// the LegalizeNodes map is filled in for any results that are not expanded,
167 /// the ExpandedNodes map is filled in for any results that are expanded, and
168 /// the Lo/Hi values are returned. This applies to integer types and Vector
170 void ExpandOp(SDValue O, SDValue &Lo, SDValue &Hi);
172 /// SplitVectorOp - Given an operand of vector type, break it down into
173 /// two smaller values.
174 void SplitVectorOp(SDValue O, SDValue &Lo, SDValue &Hi);
176 /// ScalarizeVectorOp - Given an operand of single-element vector type
177 /// (e.g. v1f32), convert it into the equivalent operation that returns a
178 /// scalar (e.g. f32) value.
179 SDValue ScalarizeVectorOp(SDValue O);
181 /// isShuffleLegal - Return non-null if a vector shuffle is legal with the
182 /// specified mask and type. Targets can specify exactly which masks they
183 /// support and the code generator is tasked with not creating illegal masks.
185 /// Note that this will also return true for shuffles that are promoted to a
188 /// If this is a legal shuffle, this method returns the (possibly promoted)
189 /// build_vector Mask. If it's not a legal shuffle, it returns null.
190 SDNode *isShuffleLegal(MVT VT, SDValue Mask) const;
192 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
193 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
195 void LegalizeSetCCOperands(SDValue &LHS, SDValue &RHS, SDValue &CC);
197 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned,
199 SDValue ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source);
201 SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT);
202 SDValue ExpandBUILD_VECTOR(SDNode *Node);
203 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
204 SDValue LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op);
205 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT);
206 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, bool isSigned);
207 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned);
209 SDValue ExpandBSWAP(SDValue Op);
210 SDValue ExpandBitCount(unsigned Opc, SDValue Op);
211 bool ExpandShift(unsigned Opc, SDValue Op, SDValue Amt,
212 SDValue &Lo, SDValue &Hi);
213 void ExpandShiftParts(unsigned NodeOp, SDValue Op, SDValue Amt,
214 SDValue &Lo, SDValue &Hi);
216 SDValue ExpandEXTRACT_SUBVECTOR(SDValue Op);
217 SDValue ExpandEXTRACT_VECTOR_ELT(SDValue Op);
221 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
222 /// specified mask and type. Targets can specify exactly which masks they
223 /// support and the code generator is tasked with not creating illegal masks.
225 /// Note that this will also return true for shuffles that are promoted to a
227 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDValue Mask) const {
228 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
230 case TargetLowering::Legal:
231 case TargetLowering::Custom:
233 case TargetLowering::Promote: {
234 // If this is promoted to a different type, convert the shuffle mask and
235 // ask if it is legal in the promoted type!
236 MVT NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
237 MVT EltVT = NVT.getVectorElementType();
239 // If we changed # elements, change the shuffle mask.
240 unsigned NumEltsGrowth =
241 NVT.getVectorNumElements() / VT.getVectorNumElements();
242 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
243 if (NumEltsGrowth > 1) {
244 // Renumber the elements.
245 SmallVector<SDValue, 8> Ops;
246 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
247 SDValue InOp = Mask.getOperand(i);
248 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
249 if (InOp.getOpcode() == ISD::UNDEF)
250 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
252 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getZExtValue();
253 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, EltVT));
257 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
263 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.getNode() : 0;
266 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
267 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
268 ValueTypeActions(TLI.getValueTypeActions()) {
269 assert(MVT::LAST_VALUETYPE <= 32 &&
270 "Too many value types for ValueTypeActions to hold!");
273 void SelectionDAGLegalize::LegalizeDAG() {
274 LastCALLSEQ_END = DAG.getEntryNode();
275 IsLegalizingCall = false;
277 // The legalize process is inherently a bottom-up recursive process (users
278 // legalize their uses before themselves). Given infinite stack space, we
279 // could just start legalizing on the root and traverse the whole graph. In
280 // practice however, this causes us to run out of stack space on large basic
281 // blocks. To avoid this problem, compute an ordering of the nodes where each
282 // node is only legalized after all of its operands are legalized.
283 std::vector<SDNode *> TopOrder;
284 unsigned N = DAG.AssignTopologicalOrder(TopOrder);
285 for (unsigned i = N; i != 0; --i)
286 HandleOp(SDValue(TopOrder[i-1], 0));
289 // Finally, it's possible the root changed. Get the new root.
290 SDValue OldRoot = DAG.getRoot();
291 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
292 DAG.setRoot(LegalizedNodes[OldRoot]);
294 ExpandedNodes.clear();
295 LegalizedNodes.clear();
296 PromotedNodes.clear();
298 ScalarizedNodes.clear();
300 // Remove dead nodes now.
301 DAG.RemoveDeadNodes();
305 /// FindCallEndFromCallStart - Given a chained node that is part of a call
306 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
307 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
308 if (Node->getOpcode() == ISD::CALLSEQ_END)
310 if (Node->use_empty())
311 return 0; // No CallSeqEnd
313 // The chain is usually at the end.
314 SDValue TheChain(Node, Node->getNumValues()-1);
315 if (TheChain.getValueType() != MVT::Other) {
316 // Sometimes it's at the beginning.
317 TheChain = SDValue(Node, 0);
318 if (TheChain.getValueType() != MVT::Other) {
319 // Otherwise, hunt for it.
320 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
321 if (Node->getValueType(i) == MVT::Other) {
322 TheChain = SDValue(Node, i);
326 // Otherwise, we walked into a node without a chain.
327 if (TheChain.getValueType() != MVT::Other)
332 for (SDNode::use_iterator UI = Node->use_begin(),
333 E = Node->use_end(); UI != E; ++UI) {
335 // Make sure to only follow users of our token chain.
337 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
338 if (User->getOperand(i) == TheChain)
339 if (SDNode *Result = FindCallEndFromCallStart(User))
345 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
346 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
347 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
348 assert(Node && "Didn't find callseq_start for a call??");
349 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
351 assert(Node->getOperand(0).getValueType() == MVT::Other &&
352 "Node doesn't have a token chain argument!");
353 return FindCallStartFromCallEnd(Node->getOperand(0).getNode());
356 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
357 /// see if any uses can reach Dest. If no dest operands can get to dest,
358 /// legalize them, legalize ourself, and return false, otherwise, return true.
360 /// Keep track of the nodes we fine that actually do lead to Dest in
361 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
363 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
364 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
365 if (N == Dest) return true; // N certainly leads to Dest :)
367 // If we've already processed this node and it does lead to Dest, there is no
368 // need to reprocess it.
369 if (NodesLeadingTo.count(N)) return true;
371 // If the first result of this node has been already legalized, then it cannot
373 switch (getTypeAction(N->getValueType(0))) {
375 if (LegalizedNodes.count(SDValue(N, 0))) return false;
378 if (PromotedNodes.count(SDValue(N, 0))) return false;
381 if (ExpandedNodes.count(SDValue(N, 0))) return false;
385 // Okay, this node has not already been legalized. Check and legalize all
386 // operands. If none lead to Dest, then we can legalize this node.
387 bool OperandsLeadToDest = false;
388 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
389 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
390 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo);
392 if (OperandsLeadToDest) {
393 NodesLeadingTo.insert(N);
397 // Okay, this node looks safe, legalize it and return false.
398 HandleOp(SDValue(N, 0));
402 /// HandleOp - Legalize, Promote, or Expand the specified operand as
403 /// appropriate for its type.
404 void SelectionDAGLegalize::HandleOp(SDValue Op) {
405 MVT VT = Op.getValueType();
406 switch (getTypeAction(VT)) {
407 default: assert(0 && "Bad type action!");
408 case Legal: (void)LegalizeOp(Op); break;
409 case Promote: (void)PromoteOp(Op); break;
411 if (!VT.isVector()) {
412 // If this is an illegal scalar, expand it into its two component
415 if (Op.getOpcode() == ISD::TargetConstant)
416 break; // Allow illegal target nodes.
418 } else if (VT.getVectorNumElements() == 1) {
419 // If this is an illegal single element vector, convert it to a
421 (void)ScalarizeVectorOp(Op);
423 // Otherwise, this is an illegal multiple element vector.
424 // Split it in half and legalize both parts.
426 SplitVectorOp(Op, X, Y);
432 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
433 /// a load from the constant pool.
434 static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
435 SelectionDAG &DAG, TargetLowering &TLI) {
438 // If a FP immediate is precise when represented as a float and if the
439 // target can do an extending load from float to double, we put it into
440 // the constant pool as a float, even if it's is statically typed as a
441 // double. This shrinks FP constants and canonicalizes them for targets where
442 // an FP extending load is the same cost as a normal load (such as on the x87
443 // fp stack or PPC FP unit).
444 MVT VT = CFP->getValueType(0);
445 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
447 if (VT!=MVT::f64 && VT!=MVT::f32)
448 assert(0 && "Invalid type expansion");
449 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt(),
450 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
455 while (SVT != MVT::f32) {
456 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1);
457 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
458 // Only do this if the target has a native EXTLOAD instruction from
460 TLI.isLoadXLegal(ISD::EXTLOAD, SVT) &&
461 TLI.ShouldShrinkFPConstant(OrigVT)) {
462 const Type *SType = SVT.getTypeForMVT();
463 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
469 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
470 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
472 return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, DAG.getEntryNode(),
473 CPIdx, PseudoSourceValue::getConstantPool(),
474 0, VT, false, Alignment);
475 return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx,
476 PseudoSourceValue::getConstantPool(), 0, false, Alignment);
480 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
483 SDValue ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT,
484 SelectionDAG &DAG, TargetLowering &TLI) {
485 MVT VT = Node->getValueType(0);
486 MVT SrcVT = Node->getOperand(1).getValueType();
487 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
488 "fcopysign expansion only supported for f32 and f64");
489 MVT SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
491 // First get the sign bit of second operand.
492 SDValue Mask1 = (SrcVT == MVT::f64)
493 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
494 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
495 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
496 SDValue SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
497 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
498 // Shift right or sign-extend it if the two operands have different types.
499 int SizeDiff = SrcNVT.getSizeInBits() - NVT.getSizeInBits();
501 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
502 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
503 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
504 } else if (SizeDiff < 0) {
505 SignBit = DAG.getNode(ISD::ZERO_EXTEND, NVT, SignBit);
506 SignBit = DAG.getNode(ISD::SHL, NVT, SignBit,
507 DAG.getConstant(-SizeDiff, TLI.getShiftAmountTy()));
510 // Clear the sign bit of first operand.
511 SDValue Mask2 = (VT == MVT::f64)
512 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
513 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
514 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
515 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
516 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
518 // Or the value with the sign bit.
519 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
523 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
525 SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
526 TargetLowering &TLI) {
527 SDValue Chain = ST->getChain();
528 SDValue Ptr = ST->getBasePtr();
529 SDValue Val = ST->getValue();
530 MVT VT = Val.getValueType();
531 int Alignment = ST->getAlignment();
532 int SVOffset = ST->getSrcValueOffset();
533 if (ST->getMemoryVT().isFloatingPoint() ||
534 ST->getMemoryVT().isVector()) {
535 // Expand to a bitconvert of the value to the integer type of the
536 // same size, then a (misaligned) int store.
538 if (VT.is128BitVector() || VT == MVT::ppcf128 || VT == MVT::f128)
540 else if (VT.is64BitVector() || VT==MVT::f64)
542 else if (VT==MVT::f32)
545 assert(0 && "Unaligned store of unsupported type");
547 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val);
548 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(),
549 SVOffset, ST->isVolatile(), Alignment);
551 assert(ST->getMemoryVT().isInteger() &&
552 !ST->getMemoryVT().isVector() &&
553 "Unaligned store of unknown type.");
554 // Get the half-size VT
556 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1);
557 int NumBits = NewStoredVT.getSizeInBits();
558 int IncrementSize = NumBits / 8;
560 // Divide the stored value in two parts.
561 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
563 SDValue Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
565 // Store the two parts
566 SDValue Store1, Store2;
567 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr,
568 ST->getSrcValue(), SVOffset, NewStoredVT,
569 ST->isVolatile(), Alignment);
570 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
571 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
572 Alignment = MinAlign(Alignment, IncrementSize);
573 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr,
574 ST->getSrcValue(), SVOffset + IncrementSize,
575 NewStoredVT, ST->isVolatile(), Alignment);
577 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2);
580 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
582 SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
583 TargetLowering &TLI) {
584 int SVOffset = LD->getSrcValueOffset();
585 SDValue Chain = LD->getChain();
586 SDValue Ptr = LD->getBasePtr();
587 MVT VT = LD->getValueType(0);
588 MVT LoadedVT = LD->getMemoryVT();
589 if (VT.isFloatingPoint() || VT.isVector()) {
590 // Expand to a (misaligned) integer load of the same size,
591 // then bitconvert to floating point or vector.
593 if (LoadedVT.is128BitVector() ||
594 LoadedVT == MVT::ppcf128 || LoadedVT == MVT::f128)
596 else if (LoadedVT.is64BitVector() || LoadedVT == MVT::f64)
598 else if (LoadedVT == MVT::f32)
601 assert(0 && "Unaligned load of unsupported type");
603 SDValue newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(),
604 SVOffset, LD->isVolatile(),
606 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad);
607 if (VT.isFloatingPoint() && LoadedVT != VT)
608 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result);
610 SDValue Ops[] = { Result, Chain };
611 return DAG.getMergeValues(Ops, 2);
613 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
614 "Unaligned load of unsupported type.");
616 // Compute the new VT that is half the size of the old one. This is an
618 unsigned NumBits = LoadedVT.getSizeInBits();
620 NewLoadedVT = MVT::getIntegerVT(NumBits/2);
623 unsigned Alignment = LD->getAlignment();
624 unsigned IncrementSize = NumBits / 8;
625 ISD::LoadExtType HiExtType = LD->getExtensionType();
627 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
628 if (HiExtType == ISD::NON_EXTLOAD)
629 HiExtType = ISD::ZEXTLOAD;
631 // Load the value in two parts
633 if (TLI.isLittleEndian()) {
634 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
635 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
636 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
637 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
638 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(),
639 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
640 MinAlign(Alignment, IncrementSize));
642 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset,
643 NewLoadedVT,LD->isVolatile(), Alignment);
644 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
645 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
646 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
647 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
648 MinAlign(Alignment, IncrementSize));
651 // aggregate the two parts
652 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
653 SDValue Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
654 Result = DAG.getNode(ISD::OR, VT, Result, Lo);
656 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
659 SDValue Ops[] = { Result, TF };
660 return DAG.getMergeValues(Ops, 2);
663 /// UnrollVectorOp - We know that the given vector has a legal type, however
664 /// the operation it performs is not legal and is an operation that we have
665 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
666 /// operating on each element individually.
667 SDValue SelectionDAGLegalize::UnrollVectorOp(SDValue Op) {
668 MVT VT = Op.getValueType();
669 assert(isTypeLegal(VT) &&
670 "Caller should expand or promote operands that are not legal!");
671 assert(Op.getNode()->getNumValues() == 1 &&
672 "Can't unroll a vector with multiple results!");
673 unsigned NE = VT.getVectorNumElements();
674 MVT EltVT = VT.getVectorElementType();
676 SmallVector<SDValue, 8> Scalars;
677 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
678 for (unsigned i = 0; i != NE; ++i) {
679 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
680 SDValue Operand = Op.getOperand(j);
681 MVT OperandVT = Operand.getValueType();
682 if (OperandVT.isVector()) {
683 // A vector operand; extract a single element.
684 MVT OperandEltVT = OperandVT.getVectorElementType();
685 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
688 DAG.getConstant(i, MVT::i32));
690 // A scalar operand; just use it as is.
691 Operands[j] = Operand;
694 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT,
695 &Operands[0], Operands.size()));
698 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size());
701 /// GetFPLibCall - Return the right libcall for the given floating point type.
702 static RTLIB::Libcall GetFPLibCall(MVT VT,
703 RTLIB::Libcall Call_F32,
704 RTLIB::Libcall Call_F64,
705 RTLIB::Libcall Call_F80,
706 RTLIB::Libcall Call_PPCF128) {
708 VT == MVT::f32 ? Call_F32 :
709 VT == MVT::f64 ? Call_F64 :
710 VT == MVT::f80 ? Call_F80 :
711 VT == MVT::ppcf128 ? Call_PPCF128 :
712 RTLIB::UNKNOWN_LIBCALL;
715 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
716 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
717 /// is necessary to spill the vector being inserted into to memory, perform
718 /// the insert there, and then read the result back.
719 SDValue SelectionDAGLegalize::
720 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx) {
725 // If the target doesn't support this, we have to spill the input vector
726 // to a temporary stack slot, update the element, then reload it. This is
727 // badness. We could also load the value into a vector register (either
728 // with a "move to register" or "extload into register" instruction, then
729 // permute it into place, if the idx is a constant and if the idx is
730 // supported by the target.
731 MVT VT = Tmp1.getValueType();
732 MVT EltVT = VT.getVectorElementType();
733 MVT IdxVT = Tmp3.getValueType();
734 MVT PtrVT = TLI.getPointerTy();
735 SDValue StackPtr = DAG.CreateStackTemporary(VT);
737 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
740 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr,
741 PseudoSourceValue::getFixedStack(SPFI), 0);
743 // Truncate or zero extend offset to target pointer type.
744 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
745 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
746 // Add the offset to the index.
747 unsigned EltSize = EltVT.getSizeInBits()/8;
748 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
749 SDValue StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
750 // Store the scalar value.
751 Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2,
752 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT);
753 // Load the updated vector.
754 return DAG.getLoad(VT, Ch, StackPtr,
755 PseudoSourceValue::getFixedStack(SPFI), 0);
758 /// LegalizeOp - We know that the specified value has a legal type, and
759 /// that its operands are legal. Now ensure that the operation itself
760 /// is legal, recursively ensuring that the operands' operations remain
762 SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
763 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
766 assert(isTypeLegal(Op.getValueType()) &&
767 "Caller should expand or promote operands that are not legal!");
768 SDNode *Node = Op.getNode();
770 // If this operation defines any values that cannot be represented in a
771 // register on this target, make sure to expand or promote them.
772 if (Node->getNumValues() > 1) {
773 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
774 if (getTypeAction(Node->getValueType(i)) != Legal) {
775 HandleOp(Op.getValue(i));
776 assert(LegalizedNodes.count(Op) &&
777 "Handling didn't add legal operands!");
778 return LegalizedNodes[Op];
782 // Note that LegalizeOp may be reentered even from single-use nodes, which
783 // means that we always must cache transformed nodes.
784 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
785 if (I != LegalizedNodes.end()) return I->second;
787 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
789 bool isCustom = false;
791 switch (Node->getOpcode()) {
792 case ISD::FrameIndex:
793 case ISD::EntryToken:
795 case ISD::BasicBlock:
796 case ISD::TargetFrameIndex:
797 case ISD::TargetJumpTable:
798 case ISD::TargetConstant:
799 case ISD::TargetConstantFP:
800 case ISD::TargetConstantPool:
801 case ISD::TargetGlobalAddress:
802 case ISD::TargetGlobalTLSAddress:
803 case ISD::TargetExternalSymbol:
806 case ISD::MEMOPERAND:
809 // Primitives must all be legal.
810 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
811 "This must be legal!");
814 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
815 // If this is a target node, legalize it by legalizing the operands then
816 // passing it through.
817 SmallVector<SDValue, 8> Ops;
818 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
819 Ops.push_back(LegalizeOp(Node->getOperand(i)));
821 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
823 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
824 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
825 return Result.getValue(Op.getResNo());
827 // Otherwise this is an unhandled builtin node. splat.
829 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
831 assert(0 && "Do not know how to legalize this operator!");
833 case ISD::GLOBAL_OFFSET_TABLE:
834 case ISD::GlobalAddress:
835 case ISD::GlobalTLSAddress:
836 case ISD::ExternalSymbol:
837 case ISD::ConstantPool:
838 case ISD::JumpTable: // Nothing to do.
839 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
840 default: assert(0 && "This action is not supported yet!");
841 case TargetLowering::Custom:
842 Tmp1 = TLI.LowerOperation(Op, DAG);
843 if (Tmp1.getNode()) Result = Tmp1;
844 // FALLTHROUGH if the target doesn't want to lower this op after all.
845 case TargetLowering::Legal:
850 case ISD::RETURNADDR:
851 // The only option for these nodes is to custom lower them. If the target
852 // does not custom lower them, then return zero.
853 Tmp1 = TLI.LowerOperation(Op, DAG);
857 Result = DAG.getConstant(0, TLI.getPointerTy());
859 case ISD::FRAME_TO_ARGS_OFFSET: {
860 MVT VT = Node->getValueType(0);
861 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
862 default: assert(0 && "This action is not supported yet!");
863 case TargetLowering::Custom:
864 Result = TLI.LowerOperation(Op, DAG);
865 if (Result.getNode()) break;
867 case TargetLowering::Legal:
868 Result = DAG.getConstant(0, VT);
873 case ISD::EXCEPTIONADDR: {
874 Tmp1 = LegalizeOp(Node->getOperand(0));
875 MVT VT = Node->getValueType(0);
876 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
877 default: assert(0 && "This action is not supported yet!");
878 case TargetLowering::Expand: {
879 unsigned Reg = TLI.getExceptionAddressRegister();
880 Result = DAG.getCopyFromReg(Tmp1, Reg, VT);
883 case TargetLowering::Custom:
884 Result = TLI.LowerOperation(Op, DAG);
885 if (Result.getNode()) break;
887 case TargetLowering::Legal: {
888 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp1 };
889 Result = DAG.getMergeValues(Ops, 2);
894 if (Result.getNode()->getNumValues() == 1) break;
896 assert(Result.getNode()->getNumValues() == 2 &&
897 "Cannot return more than two values!");
899 // Since we produced two values, make sure to remember that we
900 // legalized both of them.
901 Tmp1 = LegalizeOp(Result);
902 Tmp2 = LegalizeOp(Result.getValue(1));
903 AddLegalizedOperand(Op.getValue(0), Tmp1);
904 AddLegalizedOperand(Op.getValue(1), Tmp2);
905 return Op.getResNo() ? Tmp2 : Tmp1;
906 case ISD::EHSELECTION: {
907 Tmp1 = LegalizeOp(Node->getOperand(0));
908 Tmp2 = LegalizeOp(Node->getOperand(1));
909 MVT VT = Node->getValueType(0);
910 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
911 default: assert(0 && "This action is not supported yet!");
912 case TargetLowering::Expand: {
913 unsigned Reg = TLI.getExceptionSelectorRegister();
914 Result = DAG.getCopyFromReg(Tmp2, Reg, VT);
917 case TargetLowering::Custom:
918 Result = TLI.LowerOperation(Op, DAG);
919 if (Result.getNode()) break;
921 case TargetLowering::Legal: {
922 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp2 };
923 Result = DAG.getMergeValues(Ops, 2);
928 if (Result.getNode()->getNumValues() == 1) break;
930 assert(Result.getNode()->getNumValues() == 2 &&
931 "Cannot return more than two values!");
933 // Since we produced two values, make sure to remember that we
934 // legalized both of them.
935 Tmp1 = LegalizeOp(Result);
936 Tmp2 = LegalizeOp(Result.getValue(1));
937 AddLegalizedOperand(Op.getValue(0), Tmp1);
938 AddLegalizedOperand(Op.getValue(1), Tmp2);
939 return Op.getResNo() ? Tmp2 : Tmp1;
940 case ISD::EH_RETURN: {
941 MVT VT = Node->getValueType(0);
942 // The only "good" option for this node is to custom lower it.
943 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
944 default: assert(0 && "This action is not supported at all!");
945 case TargetLowering::Custom:
946 Result = TLI.LowerOperation(Op, DAG);
947 if (Result.getNode()) break;
949 case TargetLowering::Legal:
950 // Target does not know, how to lower this, lower to noop
951 Result = LegalizeOp(Node->getOperand(0));
956 case ISD::AssertSext:
957 case ISD::AssertZext:
958 Tmp1 = LegalizeOp(Node->getOperand(0));
959 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
961 case ISD::MERGE_VALUES:
962 // Legalize eliminates MERGE_VALUES nodes.
963 Result = Node->getOperand(Op.getResNo());
965 case ISD::CopyFromReg:
966 Tmp1 = LegalizeOp(Node->getOperand(0));
967 Result = Op.getValue(0);
968 if (Node->getNumValues() == 2) {
969 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
971 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
972 if (Node->getNumOperands() == 3) {
973 Tmp2 = LegalizeOp(Node->getOperand(2));
974 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
976 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
978 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
980 // Since CopyFromReg produces two values, make sure to remember that we
981 // legalized both of them.
982 AddLegalizedOperand(Op.getValue(0), Result);
983 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
984 return Result.getValue(Op.getResNo());
986 MVT VT = Op.getValueType();
987 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
988 default: assert(0 && "This action is not supported yet!");
989 case TargetLowering::Expand:
991 Result = DAG.getConstant(0, VT);
992 else if (VT.isFloatingPoint())
993 Result = DAG.getConstantFP(APFloat(APInt(VT.getSizeInBits(), 0)),
996 assert(0 && "Unknown value type!");
998 case TargetLowering::Legal:
1004 case ISD::INTRINSIC_W_CHAIN:
1005 case ISD::INTRINSIC_WO_CHAIN:
1006 case ISD::INTRINSIC_VOID: {
1007 SmallVector<SDValue, 8> Ops;
1008 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1009 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1010 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1012 // Allow the target to custom lower its intrinsics if it wants to.
1013 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
1014 TargetLowering::Custom) {
1015 Tmp3 = TLI.LowerOperation(Result, DAG);
1016 if (Tmp3.getNode()) Result = Tmp3;
1019 if (Result.getNode()->getNumValues() == 1) break;
1021 // Must have return value and chain result.
1022 assert(Result.getNode()->getNumValues() == 2 &&
1023 "Cannot return more than two values!");
1025 // Since loads produce two values, make sure to remember that we
1026 // legalized both of them.
1027 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1028 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1029 return Result.getValue(Op.getResNo());
1032 case ISD::DBG_STOPPOINT:
1033 assert(Node->getNumOperands() == 1 && "Invalid DBG_STOPPOINT node!");
1034 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
1036 switch (TLI.getOperationAction(ISD::DBG_STOPPOINT, MVT::Other)) {
1037 case TargetLowering::Promote:
1038 default: assert(0 && "This action is not supported yet!");
1039 case TargetLowering::Expand: {
1040 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
1041 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
1042 bool useLABEL = TLI.isOperationLegal(ISD::DBG_LABEL, MVT::Other);
1044 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node);
1045 if (MMI && (useDEBUG_LOC || useLABEL)) {
1046 const CompileUnitDesc *CompileUnit = DSP->getCompileUnit();
1047 unsigned SrcFile = MMI->RecordSource(CompileUnit);
1049 unsigned Line = DSP->getLine();
1050 unsigned Col = DSP->getColumn();
1053 SDValue Ops[] = { Tmp1, DAG.getConstant(Line, MVT::i32),
1054 DAG.getConstant(Col, MVT::i32),
1055 DAG.getConstant(SrcFile, MVT::i32) };
1056 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops, 4);
1058 unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile);
1059 Result = DAG.getLabel(ISD::DBG_LABEL, Tmp1, ID);
1062 Result = Tmp1; // chain
1066 case TargetLowering::Legal: {
1067 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1068 if (Action == Legal && Tmp1 == Node->getOperand(0))
1071 SmallVector<SDValue, 8> Ops;
1072 Ops.push_back(Tmp1);
1073 if (Action == Legal) {
1074 Ops.push_back(Node->getOperand(1)); // line # must be legal.
1075 Ops.push_back(Node->getOperand(2)); // col # must be legal.
1077 // Otherwise promote them.
1078 Ops.push_back(PromoteOp(Node->getOperand(1)));
1079 Ops.push_back(PromoteOp(Node->getOperand(2)));
1081 Ops.push_back(Node->getOperand(3)); // filename must be legal.
1082 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
1083 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1090 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!");
1091 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) {
1092 default: assert(0 && "This action is not supported yet!");
1093 case TargetLowering::Legal:
1094 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1095 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1096 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable.
1097 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1099 case TargetLowering::Expand:
1100 Result = LegalizeOp(Node->getOperand(0));
1105 case ISD::DEBUG_LOC:
1106 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
1107 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
1108 default: assert(0 && "This action is not supported yet!");
1109 case TargetLowering::Legal: {
1110 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1111 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1112 if (Action == Legal && Tmp1 == Node->getOperand(0))
1114 if (Action == Legal) {
1115 Tmp2 = Node->getOperand(1);
1116 Tmp3 = Node->getOperand(2);
1117 Tmp4 = Node->getOperand(3);
1119 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1120 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1121 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1123 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1129 case ISD::DBG_LABEL:
1131 assert(Node->getNumOperands() == 1 && "Invalid LABEL node!");
1132 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
1133 default: assert(0 && "This action is not supported yet!");
1134 case TargetLowering::Legal:
1135 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1136 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1138 case TargetLowering::Expand:
1139 Result = LegalizeOp(Node->getOperand(0));
1145 assert(Node->getNumOperands() == 4 && "Invalid Prefetch node!");
1146 switch (TLI.getOperationAction(ISD::PREFETCH, MVT::Other)) {
1147 default: assert(0 && "This action is not supported yet!");
1148 case TargetLowering::Legal:
1149 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1150 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1151 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the rw specifier.
1152 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize locality specifier.
1153 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1155 case TargetLowering::Expand:
1157 Result = LegalizeOp(Node->getOperand(0));
1162 case ISD::MEMBARRIER: {
1163 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!");
1164 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) {
1165 default: assert(0 && "This action is not supported yet!");
1166 case TargetLowering::Legal: {
1168 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1169 for (int x = 1; x < 6; ++x) {
1170 Ops[x] = Node->getOperand(x);
1171 if (!isTypeLegal(Ops[x].getValueType()))
1172 Ops[x] = PromoteOp(Ops[x]);
1174 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6);
1177 case TargetLowering::Expand:
1178 //There is no libgcc call for this op
1179 Result = Node->getOperand(0); // Noop
1185 case ISD::ATOMIC_CMP_SWAP_8:
1186 case ISD::ATOMIC_CMP_SWAP_16:
1187 case ISD::ATOMIC_CMP_SWAP_32:
1188 case ISD::ATOMIC_CMP_SWAP_64: {
1189 unsigned int num_operands = 4;
1190 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1192 for (unsigned int x = 0; x < num_operands; ++x)
1193 Ops[x] = LegalizeOp(Node->getOperand(x));
1194 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1196 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1197 default: assert(0 && "This action is not supported yet!");
1198 case TargetLowering::Custom:
1199 Result = TLI.LowerOperation(Result, DAG);
1201 case TargetLowering::Legal:
1204 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1205 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1206 return Result.getValue(Op.getResNo());
1208 case ISD::ATOMIC_LOAD_ADD_8:
1209 case ISD::ATOMIC_LOAD_SUB_8:
1210 case ISD::ATOMIC_LOAD_AND_8:
1211 case ISD::ATOMIC_LOAD_OR_8:
1212 case ISD::ATOMIC_LOAD_XOR_8:
1213 case ISD::ATOMIC_LOAD_NAND_8:
1214 case ISD::ATOMIC_LOAD_MIN_8:
1215 case ISD::ATOMIC_LOAD_MAX_8:
1216 case ISD::ATOMIC_LOAD_UMIN_8:
1217 case ISD::ATOMIC_LOAD_UMAX_8:
1218 case ISD::ATOMIC_SWAP_8:
1219 case ISD::ATOMIC_LOAD_ADD_16:
1220 case ISD::ATOMIC_LOAD_SUB_16:
1221 case ISD::ATOMIC_LOAD_AND_16:
1222 case ISD::ATOMIC_LOAD_OR_16:
1223 case ISD::ATOMIC_LOAD_XOR_16:
1224 case ISD::ATOMIC_LOAD_NAND_16:
1225 case ISD::ATOMIC_LOAD_MIN_16:
1226 case ISD::ATOMIC_LOAD_MAX_16:
1227 case ISD::ATOMIC_LOAD_UMIN_16:
1228 case ISD::ATOMIC_LOAD_UMAX_16:
1229 case ISD::ATOMIC_SWAP_16:
1230 case ISD::ATOMIC_LOAD_ADD_32:
1231 case ISD::ATOMIC_LOAD_SUB_32:
1232 case ISD::ATOMIC_LOAD_AND_32:
1233 case ISD::ATOMIC_LOAD_OR_32:
1234 case ISD::ATOMIC_LOAD_XOR_32:
1235 case ISD::ATOMIC_LOAD_NAND_32:
1236 case ISD::ATOMIC_LOAD_MIN_32:
1237 case ISD::ATOMIC_LOAD_MAX_32:
1238 case ISD::ATOMIC_LOAD_UMIN_32:
1239 case ISD::ATOMIC_LOAD_UMAX_32:
1240 case ISD::ATOMIC_SWAP_32:
1241 case ISD::ATOMIC_LOAD_ADD_64:
1242 case ISD::ATOMIC_LOAD_SUB_64:
1243 case ISD::ATOMIC_LOAD_AND_64:
1244 case ISD::ATOMIC_LOAD_OR_64:
1245 case ISD::ATOMIC_LOAD_XOR_64:
1246 case ISD::ATOMIC_LOAD_NAND_64:
1247 case ISD::ATOMIC_LOAD_MIN_64:
1248 case ISD::ATOMIC_LOAD_MAX_64:
1249 case ISD::ATOMIC_LOAD_UMIN_64:
1250 case ISD::ATOMIC_LOAD_UMAX_64:
1251 case ISD::ATOMIC_SWAP_64: {
1252 unsigned int num_operands = 3;
1253 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1255 for (unsigned int x = 0; x < num_operands; ++x)
1256 Ops[x] = LegalizeOp(Node->getOperand(x));
1257 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1259 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1260 default: assert(0 && "This action is not supported yet!");
1261 case TargetLowering::Custom:
1262 Result = TLI.LowerOperation(Result, DAG);
1264 case TargetLowering::Expand:
1265 Result = SDValue(TLI.ReplaceNodeResults(Op.getNode(), DAG),0);
1267 case TargetLowering::Legal:
1270 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1271 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1272 return Result.getValue(Op.getResNo());
1274 case ISD::Constant: {
1275 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1277 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1279 // We know we don't need to expand constants here, constants only have one
1280 // value and we check that it is fine above.
1282 if (opAction == TargetLowering::Custom) {
1283 Tmp1 = TLI.LowerOperation(Result, DAG);
1289 case ISD::ConstantFP: {
1290 // Spill FP immediates to the constant pool if the target cannot directly
1291 // codegen them. Targets often have some immediate values that can be
1292 // efficiently generated into an FP register without a load. We explicitly
1293 // leave these constants as ConstantFP nodes for the target to deal with.
1294 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1296 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1297 default: assert(0 && "This action is not supported yet!");
1298 case TargetLowering::Legal:
1300 case TargetLowering::Custom:
1301 Tmp3 = TLI.LowerOperation(Result, DAG);
1302 if (Tmp3.getNode()) {
1307 case TargetLowering::Expand: {
1308 // Check to see if this FP immediate is already legal.
1309 bool isLegal = false;
1310 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1311 E = TLI.legal_fpimm_end(); I != E; ++I) {
1312 if (CFP->isExactlyValue(*I)) {
1317 // If this is a legal constant, turn it into a TargetConstantFP node.
1320 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1325 case ISD::TokenFactor:
1326 if (Node->getNumOperands() == 2) {
1327 Tmp1 = LegalizeOp(Node->getOperand(0));
1328 Tmp2 = LegalizeOp(Node->getOperand(1));
1329 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1330 } else if (Node->getNumOperands() == 3) {
1331 Tmp1 = LegalizeOp(Node->getOperand(0));
1332 Tmp2 = LegalizeOp(Node->getOperand(1));
1333 Tmp3 = LegalizeOp(Node->getOperand(2));
1334 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1336 SmallVector<SDValue, 8> Ops;
1337 // Legalize the operands.
1338 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1339 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1340 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1344 case ISD::FORMAL_ARGUMENTS:
1346 // The only option for this is to custom lower it.
1347 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1348 assert(Tmp3.getNode() && "Target didn't custom lower this node!");
1349 // A call within a calling sequence must be legalized to something
1350 // other than the normal CALLSEQ_END. Violating this gets Legalize
1351 // into an infinite loop.
1352 assert ((!IsLegalizingCall ||
1353 Node->getOpcode() != ISD::CALL ||
1354 Tmp3.getNode()->getOpcode() != ISD::CALLSEQ_END) &&
1355 "Nested CALLSEQ_START..CALLSEQ_END not supported.");
1357 // The number of incoming and outgoing values should match; unless the final
1358 // outgoing value is a flag.
1359 assert((Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() ||
1360 (Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() + 1 &&
1361 Tmp3.getNode()->getValueType(Tmp3.getNode()->getNumValues() - 1) ==
1363 "Lowering call/formal_arguments produced unexpected # results!");
1365 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1366 // remember that we legalized all of them, so it doesn't get relegalized.
1367 for (unsigned i = 0, e = Tmp3.getNode()->getNumValues(); i != e; ++i) {
1368 if (Tmp3.getNode()->getValueType(i) == MVT::Flag)
1370 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1371 if (Op.getResNo() == i)
1373 AddLegalizedOperand(SDValue(Node, i), Tmp1);
1376 case ISD::EXTRACT_SUBREG: {
1377 Tmp1 = LegalizeOp(Node->getOperand(0));
1378 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1379 assert(idx && "Operand must be a constant");
1380 Tmp2 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0));
1381 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1384 case ISD::INSERT_SUBREG: {
1385 Tmp1 = LegalizeOp(Node->getOperand(0));
1386 Tmp2 = LegalizeOp(Node->getOperand(1));
1387 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1388 assert(idx && "Operand must be a constant");
1389 Tmp3 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0));
1390 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1393 case ISD::BUILD_VECTOR:
1394 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1395 default: assert(0 && "This action is not supported yet!");
1396 case TargetLowering::Custom:
1397 Tmp3 = TLI.LowerOperation(Result, DAG);
1398 if (Tmp3.getNode()) {
1403 case TargetLowering::Expand:
1404 Result = ExpandBUILD_VECTOR(Result.getNode());
1408 case ISD::INSERT_VECTOR_ELT:
1409 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1410 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1412 // The type of the value to insert may not be legal, even though the vector
1413 // type is legal. Legalize/Promote accordingly. We do not handle Expand
1415 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1416 default: assert(0 && "Cannot expand insert element operand");
1417 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
1418 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
1420 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1422 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1423 Node->getValueType(0))) {
1424 default: assert(0 && "This action is not supported yet!");
1425 case TargetLowering::Legal:
1427 case TargetLowering::Custom:
1428 Tmp4 = TLI.LowerOperation(Result, DAG);
1429 if (Tmp4.getNode()) {
1434 case TargetLowering::Expand: {
1435 // If the insert index is a constant, codegen this as a scalar_to_vector,
1436 // then a shuffle that inserts it into the right position in the vector.
1437 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1438 // SCALAR_TO_VECTOR requires that the type of the value being inserted
1439 // match the element type of the vector being created.
1440 if (Tmp2.getValueType() ==
1441 Op.getValueType().getVectorElementType()) {
1442 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
1443 Tmp1.getValueType(), Tmp2);
1445 unsigned NumElts = Tmp1.getValueType().getVectorNumElements();
1447 MVT::getIntVectorWithNumElements(NumElts);
1448 MVT ShufMaskEltVT = ShufMaskVT.getVectorElementType();
1450 // We generate a shuffle of InVec and ScVec, so the shuffle mask
1451 // should be 0,1,2,3,4,5... with the appropriate element replaced with
1452 // elt 0 of the RHS.
1453 SmallVector<SDValue, 8> ShufOps;
1454 for (unsigned i = 0; i != NumElts; ++i) {
1455 if (i != InsertPos->getZExtValue())
1456 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1458 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1460 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1461 &ShufOps[0], ShufOps.size());
1463 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1464 Tmp1, ScVec, ShufMask);
1465 Result = LegalizeOp(Result);
1469 Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3);
1474 case ISD::SCALAR_TO_VECTOR:
1475 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1476 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1480 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1481 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1482 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1483 Node->getValueType(0))) {
1484 default: assert(0 && "This action is not supported yet!");
1485 case TargetLowering::Legal:
1487 case TargetLowering::Custom:
1488 Tmp3 = TLI.LowerOperation(Result, DAG);
1489 if (Tmp3.getNode()) {
1494 case TargetLowering::Expand:
1495 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1499 case ISD::VECTOR_SHUFFLE:
1500 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1501 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1502 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1504 // Allow targets to custom lower the SHUFFLEs they support.
1505 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1506 default: assert(0 && "Unknown operation action!");
1507 case TargetLowering::Legal:
1508 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1509 "vector shuffle should not be created if not legal!");
1511 case TargetLowering::Custom:
1512 Tmp3 = TLI.LowerOperation(Result, DAG);
1513 if (Tmp3.getNode()) {
1518 case TargetLowering::Expand: {
1519 MVT VT = Node->getValueType(0);
1520 MVT EltVT = VT.getVectorElementType();
1521 MVT PtrVT = TLI.getPointerTy();
1522 SDValue Mask = Node->getOperand(2);
1523 unsigned NumElems = Mask.getNumOperands();
1524 SmallVector<SDValue,8> Ops;
1525 for (unsigned i = 0; i != NumElems; ++i) {
1526 SDValue Arg = Mask.getOperand(i);
1527 if (Arg.getOpcode() == ISD::UNDEF) {
1528 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1530 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1531 unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
1533 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1534 DAG.getConstant(Idx, PtrVT)));
1536 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1537 DAG.getConstant(Idx - NumElems, PtrVT)));
1540 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1543 case TargetLowering::Promote: {
1544 // Change base type to a different vector type.
1545 MVT OVT = Node->getValueType(0);
1546 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1548 // Cast the two input vectors.
1549 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1550 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1552 // Convert the shuffle mask to the right # elements.
1553 Tmp3 = SDValue(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1554 assert(Tmp3.getNode() && "Shuffle not legal?");
1555 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1556 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1562 case ISD::EXTRACT_VECTOR_ELT:
1563 Tmp1 = Node->getOperand(0);
1564 Tmp2 = LegalizeOp(Node->getOperand(1));
1565 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1566 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1569 case ISD::EXTRACT_SUBVECTOR:
1570 Tmp1 = Node->getOperand(0);
1571 Tmp2 = LegalizeOp(Node->getOperand(1));
1572 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1573 Result = ExpandEXTRACT_SUBVECTOR(Result);
1576 case ISD::CALLSEQ_START: {
1577 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1579 // Recursively Legalize all of the inputs of the call end that do not lead
1580 // to this call start. This ensures that any libcalls that need be inserted
1581 // are inserted *before* the CALLSEQ_START.
1582 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1583 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1584 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
1588 // Now that we legalized all of the inputs (which may have inserted
1589 // libcalls) create the new CALLSEQ_START node.
1590 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1592 // Merge in the last call, to ensure that this call start after the last
1594 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1595 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1596 Tmp1 = LegalizeOp(Tmp1);
1599 // Do not try to legalize the target-specific arguments (#1+).
1600 if (Tmp1 != Node->getOperand(0)) {
1601 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1603 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1606 // Remember that the CALLSEQ_START is legalized.
1607 AddLegalizedOperand(Op.getValue(0), Result);
1608 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1609 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1611 // Now that the callseq_start and all of the non-call nodes above this call
1612 // sequence have been legalized, legalize the call itself. During this
1613 // process, no libcalls can/will be inserted, guaranteeing that no calls
1615 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1616 // Note that we are selecting this call!
1617 LastCALLSEQ_END = SDValue(CallEnd, 0);
1618 IsLegalizingCall = true;
1620 // Legalize the call, starting from the CALLSEQ_END.
1621 LegalizeOp(LastCALLSEQ_END);
1622 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1625 case ISD::CALLSEQ_END:
1626 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1627 // will cause this node to be legalized as well as handling libcalls right.
1628 if (LastCALLSEQ_END.getNode() != Node) {
1629 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
1630 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1631 assert(I != LegalizedNodes.end() &&
1632 "Legalizing the call start should have legalized this node!");
1636 // Otherwise, the call start has been legalized and everything is going
1637 // according to plan. Just legalize ourselves normally here.
1638 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1639 // Do not try to legalize the target-specific arguments (#1+), except for
1640 // an optional flag input.
1641 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1642 if (Tmp1 != Node->getOperand(0)) {
1643 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1645 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1648 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1649 if (Tmp1 != Node->getOperand(0) ||
1650 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1651 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1654 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1657 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1658 // This finishes up call legalization.
1659 IsLegalizingCall = false;
1661 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1662 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1663 if (Node->getNumValues() == 2)
1664 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1665 return Result.getValue(Op.getResNo());
1666 case ISD::DYNAMIC_STACKALLOC: {
1667 MVT VT = Node->getValueType(0);
1668 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1669 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1670 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1671 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1673 Tmp1 = Result.getValue(0);
1674 Tmp2 = Result.getValue(1);
1675 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1676 default: assert(0 && "This action is not supported yet!");
1677 case TargetLowering::Expand: {
1678 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1679 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1680 " not tell us which reg is the stack pointer!");
1681 SDValue Chain = Tmp1.getOperand(0);
1683 // Chain the dynamic stack allocation so that it doesn't modify the stack
1684 // pointer when other instructions are using the stack.
1685 Chain = DAG.getCALLSEQ_START(Chain,
1686 DAG.getConstant(0, TLI.getPointerTy()));
1688 SDValue Size = Tmp2.getOperand(1);
1689 SDValue SP = DAG.getCopyFromReg(Chain, SPReg, VT);
1690 Chain = SP.getValue(1);
1691 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1692 unsigned StackAlign =
1693 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1694 if (Align > StackAlign)
1695 SP = DAG.getNode(ISD::AND, VT, SP,
1696 DAG.getConstant(-(uint64_t)Align, VT));
1697 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value
1698 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
1701 DAG.getCALLSEQ_END(Chain,
1702 DAG.getConstant(0, TLI.getPointerTy()),
1703 DAG.getConstant(0, TLI.getPointerTy()),
1706 Tmp1 = LegalizeOp(Tmp1);
1707 Tmp2 = LegalizeOp(Tmp2);
1710 case TargetLowering::Custom:
1711 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1712 if (Tmp3.getNode()) {
1713 Tmp1 = LegalizeOp(Tmp3);
1714 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1717 case TargetLowering::Legal:
1720 // Since this op produce two values, make sure to remember that we
1721 // legalized both of them.
1722 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
1723 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
1724 return Op.getResNo() ? Tmp2 : Tmp1;
1726 case ISD::INLINEASM: {
1727 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1728 bool Changed = false;
1729 // Legalize all of the operands of the inline asm, in case they are nodes
1730 // that need to be expanded or something. Note we skip the asm string and
1731 // all of the TargetConstant flags.
1732 SDValue Op = LegalizeOp(Ops[0]);
1733 Changed = Op != Ops[0];
1736 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1737 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1738 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getZExtValue() >> 3;
1739 for (++i; NumVals; ++i, --NumVals) {
1740 SDValue Op = LegalizeOp(Ops[i]);
1749 Op = LegalizeOp(Ops.back());
1750 Changed |= Op != Ops.back();
1755 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1757 // INLINE asm returns a chain and flag, make sure to add both to the map.
1758 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1759 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1760 return Result.getValue(Op.getResNo());
1763 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1764 // Ensure that libcalls are emitted before a branch.
1765 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1766 Tmp1 = LegalizeOp(Tmp1);
1767 LastCALLSEQ_END = DAG.getEntryNode();
1769 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1772 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1773 // Ensure that libcalls are emitted before a branch.
1774 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1775 Tmp1 = LegalizeOp(Tmp1);
1776 LastCALLSEQ_END = DAG.getEntryNode();
1778 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1779 default: assert(0 && "Indirect target must be legal type (pointer)!");
1781 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1784 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1787 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1788 // Ensure that libcalls are emitted before a branch.
1789 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1790 Tmp1 = LegalizeOp(Tmp1);
1791 LastCALLSEQ_END = DAG.getEntryNode();
1793 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1794 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1796 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1797 default: assert(0 && "This action is not supported yet!");
1798 case TargetLowering::Legal: break;
1799 case TargetLowering::Custom:
1800 Tmp1 = TLI.LowerOperation(Result, DAG);
1801 if (Tmp1.getNode()) Result = Tmp1;
1803 case TargetLowering::Expand: {
1804 SDValue Chain = Result.getOperand(0);
1805 SDValue Table = Result.getOperand(1);
1806 SDValue Index = Result.getOperand(2);
1808 MVT PTy = TLI.getPointerTy();
1809 MachineFunction &MF = DAG.getMachineFunction();
1810 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
1811 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1812 SDValue Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1815 switch (EntrySize) {
1816 default: assert(0 && "Size of jump table not supported yet."); break;
1817 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr,
1818 PseudoSourceValue::getJumpTable(), 0); break;
1819 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr,
1820 PseudoSourceValue::getJumpTable(), 0); break;
1824 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1825 // For PIC, the sequence is:
1826 // BRIND(load(Jumptable + index) + RelocBase)
1827 // RelocBase can be JumpTable, GOT or some sort of global base.
1828 if (PTy != MVT::i32)
1829 Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr);
1830 Addr = DAG.getNode(ISD::ADD, PTy, Addr,
1831 TLI.getPICJumpTableRelocBase(Table, DAG));
1833 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1838 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1839 // Ensure that libcalls are emitted before a return.
1840 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1841 Tmp1 = LegalizeOp(Tmp1);
1842 LastCALLSEQ_END = DAG.getEntryNode();
1844 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1845 case Expand: assert(0 && "It's impossible to expand bools");
1847 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1850 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1852 // The top bits of the promoted condition are not necessarily zero, ensure
1853 // that the value is properly zero extended.
1854 unsigned BitWidth = Tmp2.getValueSizeInBits();
1855 if (!DAG.MaskedValueIsZero(Tmp2,
1856 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
1857 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1862 // Basic block destination (Op#2) is always legal.
1863 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1865 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1866 default: assert(0 && "This action is not supported yet!");
1867 case TargetLowering::Legal: break;
1868 case TargetLowering::Custom:
1869 Tmp1 = TLI.LowerOperation(Result, DAG);
1870 if (Tmp1.getNode()) Result = Tmp1;
1872 case TargetLowering::Expand:
1873 // Expand brcond's setcc into its constituent parts and create a BR_CC
1875 if (Tmp2.getOpcode() == ISD::SETCC) {
1876 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1877 Tmp2.getOperand(0), Tmp2.getOperand(1),
1878 Node->getOperand(2));
1880 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1881 DAG.getCondCode(ISD::SETNE), Tmp2,
1882 DAG.getConstant(0, Tmp2.getValueType()),
1883 Node->getOperand(2));
1889 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1890 // Ensure that libcalls are emitted before a branch.
1891 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1892 Tmp1 = LegalizeOp(Tmp1);
1893 Tmp2 = Node->getOperand(2); // LHS
1894 Tmp3 = Node->getOperand(3); // RHS
1895 Tmp4 = Node->getOperand(1); // CC
1897 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1898 LastCALLSEQ_END = DAG.getEntryNode();
1900 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1901 // the LHS is a legal SETCC itself. In this case, we need to compare
1902 // the result against zero to select between true and false values.
1903 if (Tmp3.getNode() == 0) {
1904 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1905 Tmp4 = DAG.getCondCode(ISD::SETNE);
1908 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1909 Node->getOperand(4));
1911 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1912 default: assert(0 && "Unexpected action for BR_CC!");
1913 case TargetLowering::Legal: break;
1914 case TargetLowering::Custom:
1915 Tmp4 = TLI.LowerOperation(Result, DAG);
1916 if (Tmp4.getNode()) Result = Tmp4;
1921 LoadSDNode *LD = cast<LoadSDNode>(Node);
1922 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1923 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1925 ISD::LoadExtType ExtType = LD->getExtensionType();
1926 if (ExtType == ISD::NON_EXTLOAD) {
1927 MVT VT = Node->getValueType(0);
1928 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1929 Tmp3 = Result.getValue(0);
1930 Tmp4 = Result.getValue(1);
1932 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1933 default: assert(0 && "This action is not supported yet!");
1934 case TargetLowering::Legal:
1935 // If this is an unaligned load and the target doesn't support it,
1937 if (!TLI.allowsUnalignedMemoryAccesses()) {
1938 unsigned ABIAlignment = TLI.getTargetData()->
1939 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
1940 if (LD->getAlignment() < ABIAlignment){
1941 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
1943 Tmp3 = Result.getOperand(0);
1944 Tmp4 = Result.getOperand(1);
1945 Tmp3 = LegalizeOp(Tmp3);
1946 Tmp4 = LegalizeOp(Tmp4);
1950 case TargetLowering::Custom:
1951 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1952 if (Tmp1.getNode()) {
1953 Tmp3 = LegalizeOp(Tmp1);
1954 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1957 case TargetLowering::Promote: {
1958 // Only promote a load of vector type to another.
1959 assert(VT.isVector() && "Cannot promote this load!");
1960 // Change base type to a different vector type.
1961 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1963 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1964 LD->getSrcValueOffset(),
1965 LD->isVolatile(), LD->getAlignment());
1966 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1967 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1971 // Since loads produce two values, make sure to remember that we
1972 // legalized both of them.
1973 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
1974 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
1975 return Op.getResNo() ? Tmp4 : Tmp3;
1977 MVT SrcVT = LD->getMemoryVT();
1978 unsigned SrcWidth = SrcVT.getSizeInBits();
1979 int SVOffset = LD->getSrcValueOffset();
1980 unsigned Alignment = LD->getAlignment();
1981 bool isVolatile = LD->isVolatile();
1983 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
1984 // Some targets pretend to have an i1 loading operation, and actually
1985 // load an i8. This trick is correct for ZEXTLOAD because the top 7
1986 // bits are guaranteed to be zero; it helps the optimizers understand
1987 // that these bits are zero. It is also useful for EXTLOAD, since it
1988 // tells the optimizers that those bits are undefined. It would be
1989 // nice to have an effective generic way of getting these benefits...
1990 // Until such a way is found, don't insist on promoting i1 here.
1991 (SrcVT != MVT::i1 ||
1992 TLI.getLoadXAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
1993 // Promote to a byte-sized load if not loading an integral number of
1994 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
1995 unsigned NewWidth = SrcVT.getStoreSizeInBits();
1996 MVT NVT = MVT::getIntegerVT(NewWidth);
1999 // The extra bits are guaranteed to be zero, since we stored them that
2000 // way. A zext load from NVT thus automatically gives zext from SrcVT.
2002 ISD::LoadExtType NewExtType =
2003 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
2005 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0),
2006 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
2007 NVT, isVolatile, Alignment);
2009 Ch = Result.getValue(1); // The chain.
2011 if (ExtType == ISD::SEXTLOAD)
2012 // Having the top bits zero doesn't help when sign extending.
2013 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2014 Result, DAG.getValueType(SrcVT));
2015 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
2016 // All the top bits are guaranteed to be zero - inform the optimizers.
2017 Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result,
2018 DAG.getValueType(SrcVT));
2020 Tmp1 = LegalizeOp(Result);
2021 Tmp2 = LegalizeOp(Ch);
2022 } else if (SrcWidth & (SrcWidth - 1)) {
2023 // If not loading a power-of-2 number of bits, expand as two loads.
2024 assert(SrcVT.isExtended() && !SrcVT.isVector() &&
2025 "Unsupported extload!");
2026 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
2027 assert(RoundWidth < SrcWidth);
2028 unsigned ExtraWidth = SrcWidth - RoundWidth;
2029 assert(ExtraWidth < RoundWidth);
2030 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2031 "Load size not an integral number of bytes!");
2032 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2033 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2035 unsigned IncrementSize;
2037 if (TLI.isLittleEndian()) {
2038 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
2039 // Load the bottom RoundWidth bits.
2040 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2041 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2044 // Load the remaining ExtraWidth bits.
2045 IncrementSize = RoundWidth / 8;
2046 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2047 DAG.getIntPtrConstant(IncrementSize));
2048 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2049 LD->getSrcValue(), SVOffset + IncrementSize,
2050 ExtraVT, isVolatile,
2051 MinAlign(Alignment, IncrementSize));
2053 // Build a factor node to remember that this load is independent of the
2055 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2058 // Move the top bits to the right place.
2059 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2060 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2062 // Join the hi and lo parts.
2063 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2065 // Big endian - avoid unaligned loads.
2066 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
2067 // Load the top RoundWidth bits.
2068 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2069 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2072 // Load the remaining ExtraWidth bits.
2073 IncrementSize = RoundWidth / 8;
2074 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2075 DAG.getIntPtrConstant(IncrementSize));
2076 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2077 LD->getSrcValue(), SVOffset + IncrementSize,
2078 ExtraVT, isVolatile,
2079 MinAlign(Alignment, IncrementSize));
2081 // Build a factor node to remember that this load is independent of the
2083 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2086 // Move the top bits to the right place.
2087 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2088 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2090 // Join the hi and lo parts.
2091 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2094 Tmp1 = LegalizeOp(Result);
2095 Tmp2 = LegalizeOp(Ch);
2097 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
2098 default: assert(0 && "This action is not supported yet!");
2099 case TargetLowering::Custom:
2102 case TargetLowering::Legal:
2103 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2104 Tmp1 = Result.getValue(0);
2105 Tmp2 = Result.getValue(1);
2108 Tmp3 = TLI.LowerOperation(Result, DAG);
2109 if (Tmp3.getNode()) {
2110 Tmp1 = LegalizeOp(Tmp3);
2111 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2114 // If this is an unaligned load and the target doesn't support it,
2116 if (!TLI.allowsUnalignedMemoryAccesses()) {
2117 unsigned ABIAlignment = TLI.getTargetData()->
2118 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
2119 if (LD->getAlignment() < ABIAlignment){
2120 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
2122 Tmp1 = Result.getOperand(0);
2123 Tmp2 = Result.getOperand(1);
2124 Tmp1 = LegalizeOp(Tmp1);
2125 Tmp2 = LegalizeOp(Tmp2);
2130 case TargetLowering::Expand:
2131 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
2132 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
2133 SDValue Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
2134 LD->getSrcValueOffset(),
2135 LD->isVolatile(), LD->getAlignment());
2136 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
2137 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
2138 Tmp2 = LegalizeOp(Load.getValue(1));
2141 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
2142 // Turn the unsupported load into an EXTLOAD followed by an explicit
2143 // zero/sign extend inreg.
2144 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2145 Tmp1, Tmp2, LD->getSrcValue(),
2146 LD->getSrcValueOffset(), SrcVT,
2147 LD->isVolatile(), LD->getAlignment());
2149 if (ExtType == ISD::SEXTLOAD)
2150 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2151 Result, DAG.getValueType(SrcVT));
2153 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
2154 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
2155 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
2160 // Since loads produce two values, make sure to remember that we legalized
2162 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2163 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2164 return Op.getResNo() ? Tmp2 : Tmp1;
2167 case ISD::EXTRACT_ELEMENT: {
2168 MVT OpTy = Node->getOperand(0).getValueType();
2169 switch (getTypeAction(OpTy)) {
2170 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
2172 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
2174 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
2175 DAG.getConstant(OpTy.getSizeInBits()/2,
2176 TLI.getShiftAmountTy()));
2177 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
2180 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
2181 Node->getOperand(0));
2185 // Get both the low and high parts.
2186 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2187 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
2188 Result = Tmp2; // 1 -> Hi
2190 Result = Tmp1; // 0 -> Lo
2196 case ISD::CopyToReg:
2197 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2199 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
2200 "Register type must be legal!");
2201 // Legalize the incoming value (must be a legal type).
2202 Tmp2 = LegalizeOp(Node->getOperand(2));
2203 if (Node->getNumValues() == 1) {
2204 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
2206 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
2207 if (Node->getNumOperands() == 4) {
2208 Tmp3 = LegalizeOp(Node->getOperand(3));
2209 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
2212 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
2215 // Since this produces two values, make sure to remember that we legalized
2217 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
2218 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
2224 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2226 // Ensure that libcalls are emitted before a return.
2227 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2228 Tmp1 = LegalizeOp(Tmp1);
2229 LastCALLSEQ_END = DAG.getEntryNode();
2231 switch (Node->getNumOperands()) {
2233 Tmp2 = Node->getOperand(1);
2234 Tmp3 = Node->getOperand(2); // Signness
2235 switch (getTypeAction(Tmp2.getValueType())) {
2237 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
2240 if (!Tmp2.getValueType().isVector()) {
2242 ExpandOp(Tmp2, Lo, Hi);
2244 // Big endian systems want the hi reg first.
2245 if (TLI.isBigEndian())
2249 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2251 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
2252 Result = LegalizeOp(Result);
2254 SDNode *InVal = Tmp2.getNode();
2255 int InIx = Tmp2.getResNo();
2256 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
2257 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
2259 // Figure out if there is a simple type corresponding to this Vector
2260 // type. If so, convert to the vector type.
2261 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2262 if (TLI.isTypeLegal(TVT)) {
2263 // Turn this into a return of the vector type.
2264 Tmp2 = LegalizeOp(Tmp2);
2265 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2266 } else if (NumElems == 1) {
2267 // Turn this into a return of the scalar type.
2268 Tmp2 = ScalarizeVectorOp(Tmp2);
2269 Tmp2 = LegalizeOp(Tmp2);
2270 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2272 // FIXME: Returns of gcc generic vectors smaller than a legal type
2273 // should be returned in integer registers!
2275 // The scalarized value type may not be legal, e.g. it might require
2276 // promotion or expansion. Relegalize the return.
2277 Result = LegalizeOp(Result);
2279 // FIXME: Returns of gcc generic vectors larger than a legal vector
2280 // type should be returned by reference!
2282 SplitVectorOp(Tmp2, Lo, Hi);
2283 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2284 Result = LegalizeOp(Result);
2289 Tmp2 = PromoteOp(Node->getOperand(1));
2290 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2291 Result = LegalizeOp(Result);
2296 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2298 default: { // ret <values>
2299 SmallVector<SDValue, 8> NewValues;
2300 NewValues.push_back(Tmp1);
2301 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
2302 switch (getTypeAction(Node->getOperand(i).getValueType())) {
2304 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
2305 NewValues.push_back(Node->getOperand(i+1));
2309 assert(!Node->getOperand(i).getValueType().isExtended() &&
2310 "FIXME: TODO: implement returning non-legal vector types!");
2311 ExpandOp(Node->getOperand(i), Lo, Hi);
2312 NewValues.push_back(Lo);
2313 NewValues.push_back(Node->getOperand(i+1));
2315 NewValues.push_back(Hi);
2316 NewValues.push_back(Node->getOperand(i+1));
2321 assert(0 && "Can't promote multiple return value yet!");
2324 if (NewValues.size() == Node->getNumOperands())
2325 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
2327 Result = DAG.getNode(ISD::RET, MVT::Other,
2328 &NewValues[0], NewValues.size());
2333 if (Result.getOpcode() == ISD::RET) {
2334 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
2335 default: assert(0 && "This action is not supported yet!");
2336 case TargetLowering::Legal: break;
2337 case TargetLowering::Custom:
2338 Tmp1 = TLI.LowerOperation(Result, DAG);
2339 if (Tmp1.getNode()) Result = Tmp1;
2345 StoreSDNode *ST = cast<StoreSDNode>(Node);
2346 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
2347 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
2348 int SVOffset = ST->getSrcValueOffset();
2349 unsigned Alignment = ST->getAlignment();
2350 bool isVolatile = ST->isVolatile();
2352 if (!ST->isTruncatingStore()) {
2353 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
2354 // FIXME: We shouldn't do this for TargetConstantFP's.
2355 // FIXME: move this to the DAG Combiner! Note that we can't regress due
2356 // to phase ordering between legalized code and the dag combiner. This
2357 // probably means that we need to integrate dag combiner and legalizer
2359 // We generally can't do this one for long doubles.
2360 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
2361 if (CFP->getValueType(0) == MVT::f32 &&
2362 getTypeAction(MVT::i32) == Legal) {
2363 Tmp3 = DAG.getConstant(CFP->getValueAPF().
2364 convertToAPInt().zextOrTrunc(32),
2366 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2367 SVOffset, isVolatile, Alignment);
2369 } else if (CFP->getValueType(0) == MVT::f64) {
2370 // If this target supports 64-bit registers, do a single 64-bit store.
2371 if (getTypeAction(MVT::i64) == Legal) {
2372 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt().
2373 zextOrTrunc(64), MVT::i64);
2374 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2375 SVOffset, isVolatile, Alignment);
2377 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
2378 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
2379 // stores. If the target supports neither 32- nor 64-bits, this
2380 // xform is certainly not worth it.
2381 const APInt &IntVal =CFP->getValueAPF().convertToAPInt();
2382 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
2383 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
2384 if (TLI.isBigEndian()) std::swap(Lo, Hi);
2386 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2387 SVOffset, isVolatile, Alignment);
2388 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2389 DAG.getIntPtrConstant(4));
2390 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
2391 isVolatile, MinAlign(Alignment, 4U));
2393 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2399 switch (getTypeAction(ST->getMemoryVT())) {
2401 Tmp3 = LegalizeOp(ST->getValue());
2402 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2405 MVT VT = Tmp3.getValueType();
2406 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2407 default: assert(0 && "This action is not supported yet!");
2408 case TargetLowering::Legal:
2409 // If this is an unaligned store and the target doesn't support it,
2411 if (!TLI.allowsUnalignedMemoryAccesses()) {
2412 unsigned ABIAlignment = TLI.getTargetData()->
2413 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2414 if (ST->getAlignment() < ABIAlignment)
2415 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
2419 case TargetLowering::Custom:
2420 Tmp1 = TLI.LowerOperation(Result, DAG);
2421 if (Tmp1.getNode()) Result = Tmp1;
2423 case TargetLowering::Promote:
2424 assert(VT.isVector() && "Unknown legal promote case!");
2425 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
2426 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2427 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
2428 ST->getSrcValue(), SVOffset, isVolatile,
2435 // Truncate the value and store the result.
2436 Tmp3 = PromoteOp(ST->getValue());
2437 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2438 SVOffset, ST->getMemoryVT(),
2439 isVolatile, Alignment);
2443 unsigned IncrementSize = 0;
2446 // If this is a vector type, then we have to calculate the increment as
2447 // the product of the element size in bytes, and the number of elements
2448 // in the high half of the vector.
2449 if (ST->getValue().getValueType().isVector()) {
2450 SDNode *InVal = ST->getValue().getNode();
2451 int InIx = ST->getValue().getResNo();
2452 MVT InVT = InVal->getValueType(InIx);
2453 unsigned NumElems = InVT.getVectorNumElements();
2454 MVT EVT = InVT.getVectorElementType();
2456 // Figure out if there is a simple type corresponding to this Vector
2457 // type. If so, convert to the vector type.
2458 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2459 if (TLI.isTypeLegal(TVT)) {
2460 // Turn this into a normal store of the vector type.
2461 Tmp3 = LegalizeOp(ST->getValue());
2462 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2463 SVOffset, isVolatile, Alignment);
2464 Result = LegalizeOp(Result);
2466 } else if (NumElems == 1) {
2467 // Turn this into a normal store of the scalar type.
2468 Tmp3 = ScalarizeVectorOp(ST->getValue());
2469 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2470 SVOffset, isVolatile, Alignment);
2471 // The scalarized value type may not be legal, e.g. it might require
2472 // promotion or expansion. Relegalize the scalar store.
2473 Result = LegalizeOp(Result);
2476 SplitVectorOp(ST->getValue(), Lo, Hi);
2477 IncrementSize = Lo.getNode()->getValueType(0).getVectorNumElements() *
2478 EVT.getSizeInBits()/8;
2481 ExpandOp(ST->getValue(), Lo, Hi);
2482 IncrementSize = Hi.getNode() ? Hi.getValueType().getSizeInBits()/8 : 0;
2484 if (TLI.isBigEndian())
2488 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2489 SVOffset, isVolatile, Alignment);
2491 if (Hi.getNode() == NULL) {
2492 // Must be int <-> float one-to-one expansion.
2497 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2498 DAG.getIntPtrConstant(IncrementSize));
2499 assert(isTypeLegal(Tmp2.getValueType()) &&
2500 "Pointers must be legal!");
2501 SVOffset += IncrementSize;
2502 Alignment = MinAlign(Alignment, IncrementSize);
2503 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2504 SVOffset, isVolatile, Alignment);
2505 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2509 switch (getTypeAction(ST->getValue().getValueType())) {
2511 Tmp3 = LegalizeOp(ST->getValue());
2514 // We can promote the value, the truncstore will still take care of it.
2515 Tmp3 = PromoteOp(ST->getValue());
2518 // Just store the low part. This may become a non-trunc store, so make
2519 // sure to use getTruncStore, not UpdateNodeOperands below.
2520 ExpandOp(ST->getValue(), Tmp3, Tmp4);
2521 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2522 SVOffset, MVT::i8, isVolatile, Alignment);
2525 MVT StVT = ST->getMemoryVT();
2526 unsigned StWidth = StVT.getSizeInBits();
2528 if (StWidth != StVT.getStoreSizeInBits()) {
2529 // Promote to a byte-sized store with upper bits zero if not
2530 // storing an integral number of bytes. For example, promote
2531 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
2532 MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits());
2533 Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT);
2534 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2535 SVOffset, NVT, isVolatile, Alignment);
2536 } else if (StWidth & (StWidth - 1)) {
2537 // If not storing a power-of-2 number of bits, expand as two stores.
2538 assert(StVT.isExtended() && !StVT.isVector() &&
2539 "Unsupported truncstore!");
2540 unsigned RoundWidth = 1 << Log2_32(StWidth);
2541 assert(RoundWidth < StWidth);
2542 unsigned ExtraWidth = StWidth - RoundWidth;
2543 assert(ExtraWidth < RoundWidth);
2544 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2545 "Store size not an integral number of bytes!");
2546 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2547 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2549 unsigned IncrementSize;
2551 if (TLI.isLittleEndian()) {
2552 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
2553 // Store the bottom RoundWidth bits.
2554 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2556 isVolatile, Alignment);
2558 // Store the remaining ExtraWidth bits.
2559 IncrementSize = RoundWidth / 8;
2560 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2561 DAG.getIntPtrConstant(IncrementSize));
2562 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2563 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2564 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2565 SVOffset + IncrementSize, ExtraVT, isVolatile,
2566 MinAlign(Alignment, IncrementSize));
2568 // Big endian - avoid unaligned stores.
2569 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
2570 // Store the top RoundWidth bits.
2571 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2572 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2573 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset,
2574 RoundVT, isVolatile, Alignment);
2576 // Store the remaining ExtraWidth bits.
2577 IncrementSize = RoundWidth / 8;
2578 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2579 DAG.getIntPtrConstant(IncrementSize));
2580 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2581 SVOffset + IncrementSize, ExtraVT, isVolatile,
2582 MinAlign(Alignment, IncrementSize));
2585 // The order of the stores doesn't matter.
2586 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2588 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2589 Tmp2 != ST->getBasePtr())
2590 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2593 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
2594 default: assert(0 && "This action is not supported yet!");
2595 case TargetLowering::Legal:
2596 // If this is an unaligned store and the target doesn't support it,
2598 if (!TLI.allowsUnalignedMemoryAccesses()) {
2599 unsigned ABIAlignment = TLI.getTargetData()->
2600 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2601 if (ST->getAlignment() < ABIAlignment)
2602 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
2606 case TargetLowering::Custom:
2607 Result = TLI.LowerOperation(Result, DAG);
2610 // TRUNCSTORE:i16 i32 -> STORE i16
2611 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
2612 Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3);
2613 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset,
2614 isVolatile, Alignment);
2622 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2623 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2625 case ISD::STACKSAVE:
2626 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2627 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2628 Tmp1 = Result.getValue(0);
2629 Tmp2 = Result.getValue(1);
2631 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2632 default: assert(0 && "This action is not supported yet!");
2633 case TargetLowering::Legal: break;
2634 case TargetLowering::Custom:
2635 Tmp3 = TLI.LowerOperation(Result, DAG);
2636 if (Tmp3.getNode()) {
2637 Tmp1 = LegalizeOp(Tmp3);
2638 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2641 case TargetLowering::Expand:
2642 // Expand to CopyFromReg if the target set
2643 // StackPointerRegisterToSaveRestore.
2644 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2645 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
2646 Node->getValueType(0));
2647 Tmp2 = Tmp1.getValue(1);
2649 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
2650 Tmp2 = Node->getOperand(0);
2655 // Since stacksave produce two values, make sure to remember that we
2656 // legalized both of them.
2657 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2658 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2659 return Op.getResNo() ? Tmp2 : Tmp1;
2661 case ISD::STACKRESTORE:
2662 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2663 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2664 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2666 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2667 default: assert(0 && "This action is not supported yet!");
2668 case TargetLowering::Legal: break;
2669 case TargetLowering::Custom:
2670 Tmp1 = TLI.LowerOperation(Result, DAG);
2671 if (Tmp1.getNode()) Result = Tmp1;
2673 case TargetLowering::Expand:
2674 // Expand to CopyToReg if the target set
2675 // StackPointerRegisterToSaveRestore.
2676 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2677 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
2685 case ISD::READCYCLECOUNTER:
2686 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2687 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2688 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2689 Node->getValueType(0))) {
2690 default: assert(0 && "This action is not supported yet!");
2691 case TargetLowering::Legal:
2692 Tmp1 = Result.getValue(0);
2693 Tmp2 = Result.getValue(1);
2695 case TargetLowering::Custom:
2696 Result = TLI.LowerOperation(Result, DAG);
2697 Tmp1 = LegalizeOp(Result.getValue(0));
2698 Tmp2 = LegalizeOp(Result.getValue(1));
2702 // Since rdcc produce two values, make sure to remember that we legalized
2704 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2705 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2709 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2710 case Expand: assert(0 && "It's impossible to expand bools");
2712 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2715 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2716 // Make sure the condition is either zero or one.
2717 unsigned BitWidth = Tmp1.getValueSizeInBits();
2718 if (!DAG.MaskedValueIsZero(Tmp1,
2719 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2720 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2724 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2725 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2727 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2729 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2730 default: assert(0 && "This action is not supported yet!");
2731 case TargetLowering::Legal: break;
2732 case TargetLowering::Custom: {
2733 Tmp1 = TLI.LowerOperation(Result, DAG);
2734 if (Tmp1.getNode()) Result = Tmp1;
2737 case TargetLowering::Expand:
2738 if (Tmp1.getOpcode() == ISD::SETCC) {
2739 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2741 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2743 Result = DAG.getSelectCC(Tmp1,
2744 DAG.getConstant(0, Tmp1.getValueType()),
2745 Tmp2, Tmp3, ISD::SETNE);
2748 case TargetLowering::Promote: {
2750 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2751 unsigned ExtOp, TruncOp;
2752 if (Tmp2.getValueType().isVector()) {
2753 ExtOp = ISD::BIT_CONVERT;
2754 TruncOp = ISD::BIT_CONVERT;
2755 } else if (Tmp2.getValueType().isInteger()) {
2756 ExtOp = ISD::ANY_EXTEND;
2757 TruncOp = ISD::TRUNCATE;
2759 ExtOp = ISD::FP_EXTEND;
2760 TruncOp = ISD::FP_ROUND;
2762 // Promote each of the values to the new type.
2763 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2764 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2765 // Perform the larger operation, then round down.
2766 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2767 if (TruncOp != ISD::FP_ROUND)
2768 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2770 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result,
2771 DAG.getIntPtrConstant(0));
2776 case ISD::SELECT_CC: {
2777 Tmp1 = Node->getOperand(0); // LHS
2778 Tmp2 = Node->getOperand(1); // RHS
2779 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2780 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2781 SDValue CC = Node->getOperand(4);
2783 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
2785 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
2786 // the LHS is a legal SETCC itself. In this case, we need to compare
2787 // the result against zero to select between true and false values.
2788 if (Tmp2.getNode() == 0) {
2789 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2790 CC = DAG.getCondCode(ISD::SETNE);
2792 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
2794 // Everything is legal, see if we should expand this op or something.
2795 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
2796 default: assert(0 && "This action is not supported yet!");
2797 case TargetLowering::Legal: break;
2798 case TargetLowering::Custom:
2799 Tmp1 = TLI.LowerOperation(Result, DAG);
2800 if (Tmp1.getNode()) Result = Tmp1;
2806 Tmp1 = Node->getOperand(0);
2807 Tmp2 = Node->getOperand(1);
2808 Tmp3 = Node->getOperand(2);
2809 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
2811 // If we had to Expand the SetCC operands into a SELECT node, then it may
2812 // not always be possible to return a true LHS & RHS. In this case, just
2813 // return the value we legalized, returned in the LHS
2814 if (Tmp2.getNode() == 0) {
2819 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
2820 default: assert(0 && "Cannot handle this action for SETCC yet!");
2821 case TargetLowering::Custom:
2824 case TargetLowering::Legal:
2825 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2827 Tmp4 = TLI.LowerOperation(Result, DAG);
2828 if (Tmp4.getNode()) Result = Tmp4;
2831 case TargetLowering::Promote: {
2832 // First step, figure out the appropriate operation to use.
2833 // Allow SETCC to not be supported for all legal data types
2834 // Mostly this targets FP
2835 MVT NewInTy = Node->getOperand(0).getValueType();
2836 MVT OldVT = NewInTy; OldVT = OldVT;
2838 // Scan for the appropriate larger type to use.
2840 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
2842 assert(NewInTy.isInteger() == OldVT.isInteger() &&
2843 "Fell off of the edge of the integer world");
2844 assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() &&
2845 "Fell off of the edge of the floating point world");
2847 // If the target supports SETCC of this type, use it.
2848 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2851 if (NewInTy.isInteger())
2852 assert(0 && "Cannot promote Legal Integer SETCC yet");
2854 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2855 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2857 Tmp1 = LegalizeOp(Tmp1);
2858 Tmp2 = LegalizeOp(Tmp2);
2859 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2860 Result = LegalizeOp(Result);
2863 case TargetLowering::Expand:
2864 // Expand a setcc node into a select_cc of the same condition, lhs, and
2865 // rhs that selects between const 1 (true) and const 0 (false).
2866 MVT VT = Node->getValueType(0);
2867 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2868 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2874 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2875 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2876 SDValue CC = Node->getOperand(2);
2878 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, CC);
2880 // Everything is legal, see if we should expand this op or something.
2881 switch (TLI.getOperationAction(ISD::VSETCC, Tmp1.getValueType())) {
2882 default: assert(0 && "This action is not supported yet!");
2883 case TargetLowering::Legal: break;
2884 case TargetLowering::Custom:
2885 Tmp1 = TLI.LowerOperation(Result, DAG);
2886 if (Tmp1.getNode()) Result = Tmp1;
2892 case ISD::SHL_PARTS:
2893 case ISD::SRA_PARTS:
2894 case ISD::SRL_PARTS: {
2895 SmallVector<SDValue, 8> Ops;
2896 bool Changed = false;
2897 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2898 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2899 Changed |= Ops.back() != Node->getOperand(i);
2902 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2904 switch (TLI.getOperationAction(Node->getOpcode(),
2905 Node->getValueType(0))) {
2906 default: assert(0 && "This action is not supported yet!");
2907 case TargetLowering::Legal: break;
2908 case TargetLowering::Custom:
2909 Tmp1 = TLI.LowerOperation(Result, DAG);
2910 if (Tmp1.getNode()) {
2911 SDValue Tmp2, RetVal(0, 0);
2912 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2913 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2914 AddLegalizedOperand(SDValue(Node, i), Tmp2);
2915 if (i == Op.getResNo())
2918 assert(RetVal.getNode() && "Illegal result number");
2924 // Since these produce multiple values, make sure to remember that we
2925 // legalized all of them.
2926 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2927 AddLegalizedOperand(SDValue(Node, i), Result.getValue(i));
2928 return Result.getValue(Op.getResNo());
2950 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2951 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2952 case Expand: assert(0 && "Not possible");
2954 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2957 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2961 if ((Node->getOpcode() == ISD::SHL ||
2962 Node->getOpcode() == ISD::SRL ||
2963 Node->getOpcode() == ISD::SRA) &&
2964 !Node->getValueType(0).isVector()) {
2965 if (TLI.getShiftAmountTy().bitsLT(Tmp2.getValueType()))
2966 Tmp2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Tmp2);
2967 else if (TLI.getShiftAmountTy().bitsGT(Tmp2.getValueType()))
2968 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Tmp2);
2971 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2973 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2974 default: assert(0 && "BinOp legalize operation not supported");
2975 case TargetLowering::Legal: break;
2976 case TargetLowering::Custom:
2977 Tmp1 = TLI.LowerOperation(Result, DAG);
2978 if (Tmp1.getNode()) {
2982 // Fall through if the custom lower can't deal with the operation
2983 case TargetLowering::Expand: {
2984 MVT VT = Op.getValueType();
2986 // See if multiply or divide can be lowered using two-result operations.
2987 SDVTList VTs = DAG.getVTList(VT, VT);
2988 if (Node->getOpcode() == ISD::MUL) {
2989 // We just need the low half of the multiply; try both the signed
2990 // and unsigned forms. If the target supports both SMUL_LOHI and
2991 // UMUL_LOHI, form a preference by checking which forms of plain
2992 // MULH it supports.
2993 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT);
2994 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT);
2995 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT);
2996 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT);
2997 unsigned OpToUse = 0;
2998 if (HasSMUL_LOHI && !HasMULHS) {
2999 OpToUse = ISD::SMUL_LOHI;
3000 } else if (HasUMUL_LOHI && !HasMULHU) {
3001 OpToUse = ISD::UMUL_LOHI;
3002 } else if (HasSMUL_LOHI) {
3003 OpToUse = ISD::SMUL_LOHI;
3004 } else if (HasUMUL_LOHI) {
3005 OpToUse = ISD::UMUL_LOHI;
3008 Result = SDValue(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).getNode(), 0);
3012 if (Node->getOpcode() == ISD::MULHS &&
3013 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) {
3014 Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).getNode(), 1);
3017 if (Node->getOpcode() == ISD::MULHU &&
3018 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) {
3019 Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).getNode(), 1);
3022 if (Node->getOpcode() == ISD::SDIV &&
3023 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3024 Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(), 0);
3027 if (Node->getOpcode() == ISD::UDIV &&
3028 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3029 Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(), 0);
3033 // Check to see if we have a libcall for this operator.
3034 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3035 bool isSigned = false;
3036 switch (Node->getOpcode()) {
3039 if (VT == MVT::i32) {
3040 LC = Node->getOpcode() == ISD::UDIV
3041 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
3042 isSigned = Node->getOpcode() == ISD::SDIV;
3046 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
3047 RTLIB::POW_PPCF128);
3051 if (LC != RTLIB::UNKNOWN_LIBCALL) {
3053 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3057 assert(Node->getValueType(0).isVector() &&
3058 "Cannot expand this binary operator!");
3059 // Expand the operation into a bunch of nasty scalar code.
3060 Result = LegalizeOp(UnrollVectorOp(Op));
3063 case TargetLowering::Promote: {
3064 switch (Node->getOpcode()) {
3065 default: assert(0 && "Do not know how to promote this BinOp!");
3069 MVT OVT = Node->getValueType(0);
3070 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3071 assert(OVT.isVector() && "Cannot promote this BinOp!");
3072 // Bit convert each of the values to the new type.
3073 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
3074 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
3075 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3076 // Bit convert the result back the original type.
3077 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
3085 case ISD::SMUL_LOHI:
3086 case ISD::UMUL_LOHI:
3089 // These nodes will only be produced by target-specific lowering, so
3090 // they shouldn't be here if they aren't legal.
3091 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
3092 "This must be legal!");
3094 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3095 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3096 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3099 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
3100 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3101 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3102 case Expand: assert(0 && "Not possible");
3104 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3107 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3111 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3113 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3114 default: assert(0 && "Operation not supported");
3115 case TargetLowering::Custom:
3116 Tmp1 = TLI.LowerOperation(Result, DAG);
3117 if (Tmp1.getNode()) Result = Tmp1;
3119 case TargetLowering::Legal: break;
3120 case TargetLowering::Expand: {
3121 // If this target supports fabs/fneg natively and select is cheap,
3122 // do this efficiently.
3123 if (!TLI.isSelectExpensive() &&
3124 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
3125 TargetLowering::Legal &&
3126 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
3127 TargetLowering::Legal) {
3128 // Get the sign bit of the RHS.
3130 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
3131 SDValue SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
3132 SignBit = DAG.getSetCC(TLI.getSetCCResultType(SignBit),
3133 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
3134 // Get the absolute value of the result.
3135 SDValue AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
3136 // Select between the nabs and abs value based on the sign bit of
3138 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
3139 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
3142 Result = LegalizeOp(Result);
3146 // Otherwise, do bitwise ops!
3148 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
3149 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
3150 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
3151 Result = LegalizeOp(Result);
3159 Tmp1 = LegalizeOp(Node->getOperand(0));
3160 Tmp2 = LegalizeOp(Node->getOperand(1));
3161 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3162 // Since this produces two values, make sure to remember that we legalized
3164 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
3165 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
3170 Tmp1 = LegalizeOp(Node->getOperand(0));
3171 Tmp2 = LegalizeOp(Node->getOperand(1));
3172 Tmp3 = LegalizeOp(Node->getOperand(2));
3173 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3174 // Since this produces two values, make sure to remember that we legalized
3176 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
3177 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
3180 case ISD::BUILD_PAIR: {
3181 MVT PairTy = Node->getValueType(0);
3182 // TODO: handle the case where the Lo and Hi operands are not of legal type
3183 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
3184 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
3185 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
3186 case TargetLowering::Promote:
3187 case TargetLowering::Custom:
3188 assert(0 && "Cannot promote/custom this yet!");
3189 case TargetLowering::Legal:
3190 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
3191 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
3193 case TargetLowering::Expand:
3194 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
3195 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
3196 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
3197 DAG.getConstant(PairTy.getSizeInBits()/2,
3198 TLI.getShiftAmountTy()));
3199 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
3208 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3209 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3211 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3212 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
3213 case TargetLowering::Custom:
3216 case TargetLowering::Legal:
3217 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3219 Tmp1 = TLI.LowerOperation(Result, DAG);
3220 if (Tmp1.getNode()) Result = Tmp1;
3223 case TargetLowering::Expand: {
3224 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
3225 bool isSigned = DivOpc == ISD::SDIV;
3226 MVT VT = Node->getValueType(0);
3228 // See if remainder can be lowered using two-result operations.
3229 SDVTList VTs = DAG.getVTList(VT, VT);
3230 if (Node->getOpcode() == ISD::SREM &&
3231 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3232 Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(), 1);
3235 if (Node->getOpcode() == ISD::UREM &&
3236 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3237 Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(), 1);
3241 if (VT.isInteger()) {
3242 if (TLI.getOperationAction(DivOpc, VT) ==
3243 TargetLowering::Legal) {
3245 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
3246 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
3247 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
3248 } else if (VT.isVector()) {
3249 Result = LegalizeOp(UnrollVectorOp(Op));
3251 assert(VT == MVT::i32 &&
3252 "Cannot expand this binary operator!");
3253 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
3254 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
3256 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3259 assert(VT.isFloatingPoint() &&
3260 "remainder op must have integer or floating-point type");
3261 if (VT.isVector()) {
3262 Result = LegalizeOp(UnrollVectorOp(Op));
3264 // Floating point mod -> fmod libcall.
3265 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
3266 RTLIB::REM_F80, RTLIB::REM_PPCF128);
3268 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3276 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3277 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3279 MVT VT = Node->getValueType(0);
3280 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
3281 default: assert(0 && "This action is not supported yet!");
3282 case TargetLowering::Custom:
3285 case TargetLowering::Legal:
3286 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3287 Result = Result.getValue(0);
3288 Tmp1 = Result.getValue(1);
3291 Tmp2 = TLI.LowerOperation(Result, DAG);
3292 if (Tmp2.getNode()) {
3293 Result = LegalizeOp(Tmp2);
3294 Tmp1 = LegalizeOp(Tmp2.getValue(1));
3298 case TargetLowering::Expand: {
3299 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3300 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
3301 // Increment the pointer, VAList, to the next vaarg
3302 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3303 DAG.getConstant(VT.getSizeInBits()/8,
3304 TLI.getPointerTy()));
3305 // Store the incremented VAList to the legalized pointer
3306 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
3307 // Load the actual argument out of the pointer VAList
3308 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
3309 Tmp1 = LegalizeOp(Result.getValue(1));
3310 Result = LegalizeOp(Result);
3314 // Since VAARG produces two values, make sure to remember that we
3315 // legalized both of them.
3316 AddLegalizedOperand(SDValue(Node, 0), Result);
3317 AddLegalizedOperand(SDValue(Node, 1), Tmp1);
3318 return Op.getResNo() ? Tmp1 : Result;
3322 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3323 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
3324 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
3326 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
3327 default: assert(0 && "This action is not supported yet!");
3328 case TargetLowering::Custom:
3331 case TargetLowering::Legal:
3332 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
3333 Node->getOperand(3), Node->getOperand(4));
3335 Tmp1 = TLI.LowerOperation(Result, DAG);
3336 if (Tmp1.getNode()) Result = Tmp1;
3339 case TargetLowering::Expand:
3340 // This defaults to loading a pointer from the input and storing it to the
3341 // output, returning the chain.
3342 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3343 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3344 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VS, 0);
3345 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VD, 0);
3351 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3352 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3354 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
3355 default: assert(0 && "This action is not supported yet!");
3356 case TargetLowering::Custom:
3359 case TargetLowering::Legal:
3360 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3362 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
3363 if (Tmp1.getNode()) Result = Tmp1;
3366 case TargetLowering::Expand:
3367 Result = Tmp1; // Default to a no-op, return the chain
3373 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3374 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3376 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3378 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
3379 default: assert(0 && "This action is not supported yet!");
3380 case TargetLowering::Legal: break;
3381 case TargetLowering::Custom:
3382 Tmp1 = TLI.LowerOperation(Result, DAG);
3383 if (Tmp1.getNode()) Result = Tmp1;
3390 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3391 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3392 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3393 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3395 assert(0 && "ROTL/ROTR legalize operation not supported");
3397 case TargetLowering::Legal:
3399 case TargetLowering::Custom:
3400 Tmp1 = TLI.LowerOperation(Result, DAG);
3401 if (Tmp1.getNode()) Result = Tmp1;
3403 case TargetLowering::Promote:
3404 assert(0 && "Do not know how to promote ROTL/ROTR");
3406 case TargetLowering::Expand:
3407 assert(0 && "Do not know how to expand ROTL/ROTR");
3413 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3414 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3415 case TargetLowering::Custom:
3416 assert(0 && "Cannot custom legalize this yet!");
3417 case TargetLowering::Legal:
3418 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3420 case TargetLowering::Promote: {
3421 MVT OVT = Tmp1.getValueType();
3422 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3423 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3425 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3426 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3427 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3428 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3431 case TargetLowering::Expand:
3432 Result = ExpandBSWAP(Tmp1);
3440 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3441 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3442 case TargetLowering::Custom:
3443 case TargetLowering::Legal:
3444 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3445 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3446 TargetLowering::Custom) {
3447 Tmp1 = TLI.LowerOperation(Result, DAG);
3448 if (Tmp1.getNode()) {
3453 case TargetLowering::Promote: {
3454 MVT OVT = Tmp1.getValueType();
3455 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3457 // Zero extend the argument.
3458 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3459 // Perform the larger operation, then subtract if needed.
3460 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
3461 switch (Node->getOpcode()) {
3466 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3467 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
3468 DAG.getConstant(NVT.getSizeInBits(), NVT),
3470 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3471 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3474 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3475 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3476 DAG.getConstant(NVT.getSizeInBits() -
3477 OVT.getSizeInBits(), NVT));
3482 case TargetLowering::Expand:
3483 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
3503 case ISD::FNEARBYINT:
3504 Tmp1 = LegalizeOp(Node->getOperand(0));
3505 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3506 case TargetLowering::Promote:
3507 case TargetLowering::Custom:
3510 case TargetLowering::Legal:
3511 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3513 Tmp1 = TLI.LowerOperation(Result, DAG);
3514 if (Tmp1.getNode()) Result = Tmp1;
3517 case TargetLowering::Expand:
3518 switch (Node->getOpcode()) {
3519 default: assert(0 && "Unreachable!");
3521 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3522 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3523 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
3526 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3527 MVT VT = Node->getValueType(0);
3528 Tmp2 = DAG.getConstantFP(0.0, VT);
3529 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
3531 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
3532 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
3547 case ISD::FNEARBYINT: {
3548 MVT VT = Node->getValueType(0);
3550 // Expand unsupported unary vector operators by unrolling them.
3551 if (VT.isVector()) {
3552 Result = LegalizeOp(UnrollVectorOp(Op));
3556 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3557 switch(Node->getOpcode()) {
3559 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3560 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
3563 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
3564 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
3567 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
3568 RTLIB::COS_F80, RTLIB::COS_PPCF128);
3571 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
3572 RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
3575 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3576 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
3579 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3580 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
3583 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
3584 RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
3587 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3588 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
3591 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3592 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
3595 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3596 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128);
3599 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3600 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128);
3603 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64,
3604 RTLIB::RINT_F80, RTLIB::RINT_PPCF128);
3606 case ISD::FNEARBYINT:
3607 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
3608 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
3611 default: assert(0 && "Unreachable!");
3614 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3622 MVT VT = Node->getValueType(0);
3624 // Expand unsupported unary vector operators by unrolling them.
3625 if (VT.isVector()) {
3626 Result = LegalizeOp(UnrollVectorOp(Op));
3630 // We always lower FPOWI into a libcall. No target support for it yet.
3631 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
3632 RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
3634 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3637 case ISD::BIT_CONVERT:
3638 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3639 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3640 Node->getValueType(0));
3641 } else if (Op.getOperand(0).getValueType().isVector()) {
3642 // The input has to be a vector type, we have to either scalarize it, pack
3643 // it, or convert it based on whether the input vector type is legal.
3644 SDNode *InVal = Node->getOperand(0).getNode();
3645 int InIx = Node->getOperand(0).getResNo();
3646 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
3647 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
3649 // Figure out if there is a simple type corresponding to this Vector
3650 // type. If so, convert to the vector type.
3651 MVT TVT = MVT::getVectorVT(EVT, NumElems);
3652 if (TLI.isTypeLegal(TVT)) {
3653 // Turn this into a bit convert of the vector input.
3654 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3655 LegalizeOp(Node->getOperand(0)));
3657 } else if (NumElems == 1) {
3658 // Turn this into a bit convert of the scalar input.
3659 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3660 ScalarizeVectorOp(Node->getOperand(0)));
3663 // FIXME: UNIMP! Store then reload
3664 assert(0 && "Cast from unsupported vector type not implemented yet!");
3667 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3668 Node->getOperand(0).getValueType())) {
3669 default: assert(0 && "Unknown operation action!");
3670 case TargetLowering::Expand:
3671 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3672 Node->getValueType(0));
3674 case TargetLowering::Legal:
3675 Tmp1 = LegalizeOp(Node->getOperand(0));
3676 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3682 // Conversion operators. The source and destination have different types.
3683 case ISD::SINT_TO_FP:
3684 case ISD::UINT_TO_FP: {
3685 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
3686 Result = LegalizeINT_TO_FP(Result, isSigned,
3687 Node->getValueType(0), Node->getOperand(0));
3691 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3693 Tmp1 = LegalizeOp(Node->getOperand(0));
3694 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3697 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3699 // Since the result is legal, we should just be able to truncate the low
3700 // part of the source.
3701 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
3704 Result = PromoteOp(Node->getOperand(0));
3705 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
3710 case ISD::FP_TO_SINT:
3711 case ISD::FP_TO_UINT:
3712 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3714 Tmp1 = LegalizeOp(Node->getOperand(0));
3716 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
3717 default: assert(0 && "Unknown operation action!");
3718 case TargetLowering::Custom:
3721 case TargetLowering::Legal:
3722 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3724 Tmp1 = TLI.LowerOperation(Result, DAG);
3725 if (Tmp1.getNode()) Result = Tmp1;
3728 case TargetLowering::Promote:
3729 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
3730 Node->getOpcode() == ISD::FP_TO_SINT);
3732 case TargetLowering::Expand:
3733 if (Node->getOpcode() == ISD::FP_TO_UINT) {
3734 SDValue True, False;
3735 MVT VT = Node->getOperand(0).getValueType();
3736 MVT NVT = Node->getValueType(0);
3737 const uint64_t zero[] = {0, 0};
3738 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero));
3739 APInt x = APInt::getSignBit(NVT.getSizeInBits());
3740 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
3741 Tmp2 = DAG.getConstantFP(apf, VT);
3742 Tmp3 = DAG.getSetCC(TLI.getSetCCResultType(Node->getOperand(0)),
3743 Node->getOperand(0), Tmp2, ISD::SETLT);
3744 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
3745 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
3746 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
3748 False = DAG.getNode(ISD::XOR, NVT, False,
3749 DAG.getConstant(x, NVT));
3750 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
3753 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
3759 MVT VT = Op.getValueType();
3760 MVT OVT = Node->getOperand(0).getValueType();
3761 // Convert ppcf128 to i32
3762 if (OVT == MVT::ppcf128 && VT == MVT::i32) {
3763 if (Node->getOpcode() == ISD::FP_TO_SINT) {
3764 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128,
3765 Node->getOperand(0), DAG.getValueType(MVT::f64));
3766 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result,
3767 DAG.getIntPtrConstant(1));
3768 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result);
3770 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
3771 APFloat apf = APFloat(APInt(128, 2, TwoE31));
3772 Tmp2 = DAG.getConstantFP(apf, OVT);
3773 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
3774 // FIXME: generated code sucks.
3775 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2,
3776 DAG.getNode(ISD::ADD, MVT::i32,
3777 DAG.getNode(ISD::FP_TO_SINT, VT,
3778 DAG.getNode(ISD::FSUB, OVT,
3779 Node->getOperand(0), Tmp2)),
3780 DAG.getConstant(0x80000000, MVT::i32)),
3781 DAG.getNode(ISD::FP_TO_SINT, VT,
3782 Node->getOperand(0)),
3783 DAG.getCondCode(ISD::SETGE));
3787 // Convert f32 / f64 to i32 / i64 / i128.
3788 RTLIB::Libcall LC = (Node->getOpcode() == ISD::FP_TO_SINT) ?
3789 RTLIB::getFPTOSINT(OVT, VT) : RTLIB::getFPTOUINT(OVT, VT);
3790 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpectd fp-to-int conversion!");
3792 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3796 Tmp1 = PromoteOp(Node->getOperand(0));
3797 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
3798 Result = LegalizeOp(Result);
3803 case ISD::FP_EXTEND: {
3804 MVT DstVT = Op.getValueType();
3805 MVT SrcVT = Op.getOperand(0).getValueType();
3806 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3807 // The only other way we can lower this is to turn it into a STORE,
3808 // LOAD pair, targetting a temporary location (a stack slot).
3809 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT);
3812 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3813 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3815 Tmp1 = LegalizeOp(Node->getOperand(0));
3816 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3819 Tmp1 = PromoteOp(Node->getOperand(0));
3820 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1);
3825 case ISD::FP_ROUND: {
3826 MVT DstVT = Op.getValueType();
3827 MVT SrcVT = Op.getOperand(0).getValueType();
3828 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3829 if (SrcVT == MVT::ppcf128) {
3831 ExpandOp(Node->getOperand(0), Lo, Result);
3832 // Round it the rest of the way (e.g. to f32) if needed.
3833 if (DstVT!=MVT::f64)
3834 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1));
3837 // The only other way we can lower this is to turn it into a STORE,
3838 // LOAD pair, targetting a temporary location (a stack slot).
3839 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT);
3842 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3843 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3845 Tmp1 = LegalizeOp(Node->getOperand(0));
3846 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3849 Tmp1 = PromoteOp(Node->getOperand(0));
3850 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1,
3851 Node->getOperand(1));
3856 case ISD::ANY_EXTEND:
3857 case ISD::ZERO_EXTEND:
3858 case ISD::SIGN_EXTEND:
3859 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3860 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3862 Tmp1 = LegalizeOp(Node->getOperand(0));
3863 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3864 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3865 TargetLowering::Custom) {
3866 Tmp1 = TLI.LowerOperation(Result, DAG);
3867 if (Tmp1.getNode()) Result = Tmp1;
3871 switch (Node->getOpcode()) {
3872 case ISD::ANY_EXTEND:
3873 Tmp1 = PromoteOp(Node->getOperand(0));
3874 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
3876 case ISD::ZERO_EXTEND:
3877 Result = PromoteOp(Node->getOperand(0));
3878 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3879 Result = DAG.getZeroExtendInReg(Result,
3880 Node->getOperand(0).getValueType());
3882 case ISD::SIGN_EXTEND:
3883 Result = PromoteOp(Node->getOperand(0));
3884 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3885 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3887 DAG.getValueType(Node->getOperand(0).getValueType()));
3892 case ISD::FP_ROUND_INREG:
3893 case ISD::SIGN_EXTEND_INREG: {
3894 Tmp1 = LegalizeOp(Node->getOperand(0));
3895 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3897 // If this operation is not supported, convert it to a shl/shr or load/store
3899 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
3900 default: assert(0 && "This action not supported for this op yet!");
3901 case TargetLowering::Legal:
3902 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3904 case TargetLowering::Expand:
3905 // If this is an integer extend and shifts are supported, do that.
3906 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
3907 // NOTE: we could fall back on load/store here too for targets without
3908 // SAR. However, it is doubtful that any exist.
3909 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() -
3910 ExtraVT.getSizeInBits();
3911 SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
3912 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
3913 Node->getOperand(0), ShiftCst);
3914 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
3916 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
3917 // The only way we can lower this is to turn it into a TRUNCSTORE,
3918 // EXTLOAD pair, targetting a temporary location (a stack slot).
3920 // NOTE: there is a choice here between constantly creating new stack
3921 // slots and always reusing the same one. We currently always create
3922 // new ones, as reuse may inhibit scheduling.
3923 Result = EmitStackConvert(Node->getOperand(0), ExtraVT,
3924 Node->getValueType(0));
3926 assert(0 && "Unknown op");
3932 case ISD::TRAMPOLINE: {
3934 for (unsigned i = 0; i != 6; ++i)
3935 Ops[i] = LegalizeOp(Node->getOperand(i));
3936 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
3937 // The only option for this node is to custom lower it.
3938 Result = TLI.LowerOperation(Result, DAG);
3939 assert(Result.getNode() && "Should always custom lower!");
3941 // Since trampoline produces two values, make sure to remember that we
3942 // legalized both of them.
3943 Tmp1 = LegalizeOp(Result.getValue(1));
3944 Result = LegalizeOp(Result);
3945 AddLegalizedOperand(SDValue(Node, 0), Result);
3946 AddLegalizedOperand(SDValue(Node, 1), Tmp1);
3947 return Op.getResNo() ? Tmp1 : Result;
3949 case ISD::FLT_ROUNDS_: {
3950 MVT VT = Node->getValueType(0);
3951 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
3952 default: assert(0 && "This action not supported for this op yet!");
3953 case TargetLowering::Custom:
3954 Result = TLI.LowerOperation(Op, DAG);
3955 if (Result.getNode()) break;
3957 case TargetLowering::Legal:
3958 // If this operation is not supported, lower it to constant 1
3959 Result = DAG.getConstant(1, VT);
3965 MVT VT = Node->getValueType(0);
3966 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
3967 default: assert(0 && "This action not supported for this op yet!");
3968 case TargetLowering::Legal:
3969 Tmp1 = LegalizeOp(Node->getOperand(0));
3970 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3972 case TargetLowering::Custom:
3973 Result = TLI.LowerOperation(Op, DAG);
3974 if (Result.getNode()) break;
3976 case TargetLowering::Expand:
3977 // If this operation is not supported, lower it to 'abort()' call
3978 Tmp1 = LegalizeOp(Node->getOperand(0));
3979 TargetLowering::ArgListTy Args;
3980 std::pair<SDValue,SDValue> CallResult =
3981 TLI.LowerCallTo(Tmp1, Type::VoidTy,
3982 false, false, false, CallingConv::C, false,
3983 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
3985 Result = CallResult.second;
3992 assert(Result.getValueType() == Op.getValueType() &&
3993 "Bad legalization!");
3995 // Make sure that the generated code is itself legal.
3997 Result = LegalizeOp(Result);
3999 // Note that LegalizeOp may be reentered even from single-use nodes, which
4000 // means that we always must cache transformed nodes.
4001 AddLegalizedOperand(Op, Result);
4005 /// PromoteOp - Given an operation that produces a value in an invalid type,
4006 /// promote it to compute the value into a larger type. The produced value will
4007 /// have the correct bits for the low portion of the register, but no guarantee
4008 /// is made about the top bits: it may be zero, sign-extended, or garbage.
4009 SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) {
4010 MVT VT = Op.getValueType();
4011 MVT NVT = TLI.getTypeToTransformTo(VT);
4012 assert(getTypeAction(VT) == Promote &&
4013 "Caller should expand or legalize operands that are not promotable!");
4014 assert(NVT.bitsGT(VT) && NVT.isInteger() == VT.isInteger() &&
4015 "Cannot promote to smaller type!");
4017 SDValue Tmp1, Tmp2, Tmp3;
4019 SDNode *Node = Op.getNode();
4021 DenseMap<SDValue, SDValue>::iterator I = PromotedNodes.find(Op);
4022 if (I != PromotedNodes.end()) return I->second;
4024 switch (Node->getOpcode()) {
4025 case ISD::CopyFromReg:
4026 assert(0 && "CopyFromReg must be legal!");
4029 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
4031 assert(0 && "Do not know how to promote this operator!");
4034 Result = DAG.getNode(ISD::UNDEF, NVT);
4038 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
4040 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
4041 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
4043 case ISD::ConstantFP:
4044 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
4045 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
4049 assert(isTypeLegal(TLI.getSetCCResultType(Node->getOperand(0)))
4050 && "SetCC type is not legal??");
4051 Result = DAG.getNode(ISD::SETCC,
4052 TLI.getSetCCResultType(Node->getOperand(0)),
4053 Node->getOperand(0), Node->getOperand(1),
4054 Node->getOperand(2));
4058 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4060 Result = LegalizeOp(Node->getOperand(0));
4061 assert(Result.getValueType().bitsGE(NVT) &&
4062 "This truncation doesn't make sense!");
4063 if (Result.getValueType().bitsGT(NVT)) // Truncate to NVT instead of VT
4064 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
4067 // The truncation is not required, because we don't guarantee anything
4068 // about high bits anyway.
4069 Result = PromoteOp(Node->getOperand(0));
4072 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4073 // Truncate the low part of the expanded value to the result type
4074 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
4077 case ISD::SIGN_EXTEND:
4078 case ISD::ZERO_EXTEND:
4079 case ISD::ANY_EXTEND:
4080 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4081 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
4083 // Input is legal? Just do extend all the way to the larger type.
4084 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4087 // Promote the reg if it's smaller.
4088 Result = PromoteOp(Node->getOperand(0));
4089 // The high bits are not guaranteed to be anything. Insert an extend.
4090 if (Node->getOpcode() == ISD::SIGN_EXTEND)
4091 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4092 DAG.getValueType(Node->getOperand(0).getValueType()));
4093 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
4094 Result = DAG.getZeroExtendInReg(Result,
4095 Node->getOperand(0).getValueType());
4099 case ISD::BIT_CONVERT:
4100 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
4101 Node->getValueType(0));
4102 Result = PromoteOp(Result);
4105 case ISD::FP_EXTEND:
4106 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
4108 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4109 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
4110 case Promote: assert(0 && "Unreachable with 2 FP types!");
4112 if (Node->getConstantOperandVal(1) == 0) {
4113 // Input is legal? Do an FP_ROUND_INREG.
4114 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
4115 DAG.getValueType(VT));
4117 // Just remove the truncate, it isn't affecting the value.
4118 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0),
4119 Node->getOperand(1));
4124 case ISD::SINT_TO_FP:
4125 case ISD::UINT_TO_FP:
4126 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4128 // No extra round required here.
4129 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4133 Result = PromoteOp(Node->getOperand(0));
4134 if (Node->getOpcode() == ISD::SINT_TO_FP)
4135 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
4137 DAG.getValueType(Node->getOperand(0).getValueType()));
4139 Result = DAG.getZeroExtendInReg(Result,
4140 Node->getOperand(0).getValueType());
4141 // No extra round required here.
4142 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
4145 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
4146 Node->getOperand(0));
4147 // Round if we cannot tolerate excess precision.
4148 if (NoExcessFPPrecision)
4149 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4150 DAG.getValueType(VT));
4155 case ISD::SIGN_EXTEND_INREG:
4156 Result = PromoteOp(Node->getOperand(0));
4157 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4158 Node->getOperand(1));
4160 case ISD::FP_TO_SINT:
4161 case ISD::FP_TO_UINT:
4162 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4165 Tmp1 = Node->getOperand(0);
4168 // The input result is prerounded, so we don't have to do anything
4170 Tmp1 = PromoteOp(Node->getOperand(0));
4173 // If we're promoting a UINT to a larger size, check to see if the new node
4174 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
4175 // we can use that instead. This allows us to generate better code for
4176 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
4177 // legal, such as PowerPC.
4178 if (Node->getOpcode() == ISD::FP_TO_UINT &&
4179 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
4180 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
4181 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
4182 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
4184 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4190 Tmp1 = PromoteOp(Node->getOperand(0));
4191 assert(Tmp1.getValueType() == NVT);
4192 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4193 // NOTE: we do not have to do any extra rounding here for
4194 // NoExcessFPPrecision, because we know the input will have the appropriate
4195 // precision, and these operations don't modify precision at all.
4210 case ISD::FNEARBYINT:
4211 Tmp1 = PromoteOp(Node->getOperand(0));
4212 assert(Tmp1.getValueType() == NVT);
4213 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4214 if (NoExcessFPPrecision)
4215 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4216 DAG.getValueType(VT));
4221 // Promote f32 pow(i) to f64 pow(i). Note that this could insert a libcall
4222 // directly as well, which may be better.
4223 Tmp1 = PromoteOp(Node->getOperand(0));
4224 Tmp2 = Node->getOperand(1);
4225 if (Node->getOpcode() == ISD::FPOW)
4226 Tmp2 = PromoteOp(Tmp2);
4227 assert(Tmp1.getValueType() == NVT);
4228 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4229 if (NoExcessFPPrecision)
4230 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4231 DAG.getValueType(VT));
4235 case ISD::ATOMIC_CMP_SWAP_8:
4236 case ISD::ATOMIC_CMP_SWAP_16:
4237 case ISD::ATOMIC_CMP_SWAP_32:
4238 case ISD::ATOMIC_CMP_SWAP_64: {
4239 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4240 Tmp2 = PromoteOp(Node->getOperand(2));
4241 Tmp3 = PromoteOp(Node->getOperand(3));
4242 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(),
4243 AtomNode->getBasePtr(), Tmp2, Tmp3,
4244 AtomNode->getSrcValue(),
4245 AtomNode->getAlignment());
4246 // Remember that we legalized the chain.
4247 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4250 case ISD::ATOMIC_LOAD_ADD_8:
4251 case ISD::ATOMIC_LOAD_SUB_8:
4252 case ISD::ATOMIC_LOAD_AND_8:
4253 case ISD::ATOMIC_LOAD_OR_8:
4254 case ISD::ATOMIC_LOAD_XOR_8:
4255 case ISD::ATOMIC_LOAD_NAND_8:
4256 case ISD::ATOMIC_LOAD_MIN_8:
4257 case ISD::ATOMIC_LOAD_MAX_8:
4258 case ISD::ATOMIC_LOAD_UMIN_8:
4259 case ISD::ATOMIC_LOAD_UMAX_8:
4260 case ISD::ATOMIC_SWAP_8:
4261 case ISD::ATOMIC_LOAD_ADD_16:
4262 case ISD::ATOMIC_LOAD_SUB_16:
4263 case ISD::ATOMIC_LOAD_AND_16:
4264 case ISD::ATOMIC_LOAD_OR_16:
4265 case ISD::ATOMIC_LOAD_XOR_16:
4266 case ISD::ATOMIC_LOAD_NAND_16:
4267 case ISD::ATOMIC_LOAD_MIN_16:
4268 case ISD::ATOMIC_LOAD_MAX_16:
4269 case ISD::ATOMIC_LOAD_UMIN_16:
4270 case ISD::ATOMIC_LOAD_UMAX_16:
4271 case ISD::ATOMIC_SWAP_16:
4272 case ISD::ATOMIC_LOAD_ADD_32:
4273 case ISD::ATOMIC_LOAD_SUB_32:
4274 case ISD::ATOMIC_LOAD_AND_32:
4275 case ISD::ATOMIC_LOAD_OR_32:
4276 case ISD::ATOMIC_LOAD_XOR_32:
4277 case ISD::ATOMIC_LOAD_NAND_32:
4278 case ISD::ATOMIC_LOAD_MIN_32:
4279 case ISD::ATOMIC_LOAD_MAX_32:
4280 case ISD::ATOMIC_LOAD_UMIN_32:
4281 case ISD::ATOMIC_LOAD_UMAX_32:
4282 case ISD::ATOMIC_SWAP_32:
4283 case ISD::ATOMIC_LOAD_ADD_64:
4284 case ISD::ATOMIC_LOAD_SUB_64:
4285 case ISD::ATOMIC_LOAD_AND_64:
4286 case ISD::ATOMIC_LOAD_OR_64:
4287 case ISD::ATOMIC_LOAD_XOR_64:
4288 case ISD::ATOMIC_LOAD_NAND_64:
4289 case ISD::ATOMIC_LOAD_MIN_64:
4290 case ISD::ATOMIC_LOAD_MAX_64:
4291 case ISD::ATOMIC_LOAD_UMIN_64:
4292 case ISD::ATOMIC_LOAD_UMAX_64:
4293 case ISD::ATOMIC_SWAP_64: {
4294 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4295 Tmp2 = PromoteOp(Node->getOperand(2));
4296 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(),
4297 AtomNode->getBasePtr(), Tmp2,
4298 AtomNode->getSrcValue(),
4299 AtomNode->getAlignment());
4300 // Remember that we legalized the chain.
4301 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4311 // The input may have strange things in the top bits of the registers, but
4312 // these operations don't care. They may have weird bits going out, but
4313 // that too is okay if they are integer operations.
4314 Tmp1 = PromoteOp(Node->getOperand(0));
4315 Tmp2 = PromoteOp(Node->getOperand(1));
4316 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4317 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4322 Tmp1 = PromoteOp(Node->getOperand(0));
4323 Tmp2 = PromoteOp(Node->getOperand(1));
4324 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4325 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4327 // Floating point operations will give excess precision that we may not be
4328 // able to tolerate. If we DO allow excess precision, just leave it,
4329 // otherwise excise it.
4330 // FIXME: Why would we need to round FP ops more than integer ones?
4331 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
4332 if (NoExcessFPPrecision)
4333 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4334 DAG.getValueType(VT));
4339 // These operators require that their input be sign extended.
4340 Tmp1 = PromoteOp(Node->getOperand(0));
4341 Tmp2 = PromoteOp(Node->getOperand(1));
4342 if (NVT.isInteger()) {
4343 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4344 DAG.getValueType(VT));
4345 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4346 DAG.getValueType(VT));
4348 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4350 // Perform FP_ROUND: this is probably overly pessimistic.
4351 if (NVT.isFloatingPoint() && NoExcessFPPrecision)
4352 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4353 DAG.getValueType(VT));
4357 case ISD::FCOPYSIGN:
4358 // These operators require that their input be fp extended.
4359 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4360 case Expand: assert(0 && "not implemented");
4361 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break;
4362 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break;
4364 switch (getTypeAction(Node->getOperand(1).getValueType())) {
4365 case Expand: assert(0 && "not implemented");
4366 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
4367 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
4369 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4371 // Perform FP_ROUND: this is probably overly pessimistic.
4372 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
4373 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4374 DAG.getValueType(VT));
4379 // These operators require that their input be zero extended.
4380 Tmp1 = PromoteOp(Node->getOperand(0));
4381 Tmp2 = PromoteOp(Node->getOperand(1));
4382 assert(NVT.isInteger() && "Operators don't apply to FP!");
4383 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4384 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4385 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4389 Tmp1 = PromoteOp(Node->getOperand(0));
4390 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
4393 // The input value must be properly sign extended.
4394 Tmp1 = PromoteOp(Node->getOperand(0));
4395 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4396 DAG.getValueType(VT));
4397 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
4400 // The input value must be properly zero extended.
4401 Tmp1 = PromoteOp(Node->getOperand(0));
4402 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4403 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
4407 Tmp1 = Node->getOperand(0); // Get the chain.
4408 Tmp2 = Node->getOperand(1); // Get the pointer.
4409 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
4410 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
4411 Result = TLI.LowerOperation(Tmp3, DAG);
4413 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
4414 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
4415 // Increment the pointer, VAList, to the next vaarg
4416 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
4417 DAG.getConstant(VT.getSizeInBits()/8,
4418 TLI.getPointerTy()));
4419 // Store the incremented VAList to the legalized pointer
4420 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
4421 // Load the actual argument out of the pointer VAList
4422 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
4424 // Remember that we legalized the chain.
4425 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4429 LoadSDNode *LD = cast<LoadSDNode>(Node);
4430 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
4431 ? ISD::EXTLOAD : LD->getExtensionType();
4432 Result = DAG.getExtLoad(ExtType, NVT,
4433 LD->getChain(), LD->getBasePtr(),
4434 LD->getSrcValue(), LD->getSrcValueOffset(),
4437 LD->getAlignment());
4438 // Remember that we legalized the chain.
4439 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4443 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
4444 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
4446 MVT VT2 = Tmp2.getValueType();
4447 assert(VT2 == Tmp3.getValueType()
4448 && "PromoteOp SELECT: Operands 2 and 3 ValueTypes don't match");
4449 // Ensure that the resulting node is at least the same size as the operands'
4450 // value types, because we cannot assume that TLI.getSetCCValueType() is
4452 Result = DAG.getNode(ISD::SELECT, VT2, Node->getOperand(0), Tmp2, Tmp3);
4455 case ISD::SELECT_CC:
4456 Tmp2 = PromoteOp(Node->getOperand(2)); // True
4457 Tmp3 = PromoteOp(Node->getOperand(3)); // False
4458 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4459 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
4462 Tmp1 = Node->getOperand(0);
4463 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
4464 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
4465 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
4466 DAG.getConstant(NVT.getSizeInBits() -
4468 TLI.getShiftAmountTy()));
4473 // Zero extend the argument
4474 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4475 // Perform the larger operation, then subtract if needed.
4476 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4477 switch(Node->getOpcode()) {
4482 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
4483 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
4484 DAG.getConstant(NVT.getSizeInBits(), NVT),
4486 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
4487 DAG.getConstant(VT.getSizeInBits(), NVT), Tmp1);
4490 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4491 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
4492 DAG.getConstant(NVT.getSizeInBits() -
4493 VT.getSizeInBits(), NVT));
4497 case ISD::EXTRACT_SUBVECTOR:
4498 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
4500 case ISD::EXTRACT_VECTOR_ELT:
4501 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
4505 assert(Result.getNode() && "Didn't set a result!");
4507 // Make sure the result is itself legal.
4508 Result = LegalizeOp(Result);
4510 // Remember that we promoted this!
4511 AddPromotedOperand(Op, Result);
4515 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
4516 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
4517 /// based on the vector type. The return type of this matches the element type
4518 /// of the vector, which may not be legal for the target.
4519 SDValue SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDValue Op) {
4520 // We know that operand #0 is the Vec vector. If the index is a constant
4521 // or if the invec is a supported hardware type, we can use it. Otherwise,
4522 // lower to a store then an indexed load.
4523 SDValue Vec = Op.getOperand(0);
4524 SDValue Idx = Op.getOperand(1);
4526 MVT TVT = Vec.getValueType();
4527 unsigned NumElems = TVT.getVectorNumElements();
4529 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
4530 default: assert(0 && "This action is not supported yet!");
4531 case TargetLowering::Custom: {
4532 Vec = LegalizeOp(Vec);
4533 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4534 SDValue Tmp3 = TLI.LowerOperation(Op, DAG);
4539 case TargetLowering::Legal:
4540 if (isTypeLegal(TVT)) {
4541 Vec = LegalizeOp(Vec);
4542 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4546 case TargetLowering::Expand:
4550 if (NumElems == 1) {
4551 // This must be an access of the only element. Return it.
4552 Op = ScalarizeVectorOp(Vec);
4553 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
4554 unsigned NumLoElts = 1 << Log2_32(NumElems-1);
4555 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4557 SplitVectorOp(Vec, Lo, Hi);
4558 if (CIdx->getZExtValue() < NumLoElts) {
4562 Idx = DAG.getConstant(CIdx->getZExtValue() - NumLoElts,
4563 Idx.getValueType());
4566 // It's now an extract from the appropriate high or low part. Recurse.
4567 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4568 Op = ExpandEXTRACT_VECTOR_ELT(Op);
4570 // Store the value to a temporary stack slot, then LOAD the scalar
4571 // element back out.
4572 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
4573 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
4575 // Add the offset to the index.
4576 unsigned EltSize = Op.getValueType().getSizeInBits()/8;
4577 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
4578 DAG.getConstant(EltSize, Idx.getValueType()));
4580 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
4581 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx);
4583 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
4585 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
4587 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
4592 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
4593 /// we assume the operation can be split if it is not already legal.
4594 SDValue SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDValue Op) {
4595 // We know that operand #0 is the Vec vector. For now we assume the index
4596 // is a constant and that the extracted result is a supported hardware type.
4597 SDValue Vec = Op.getOperand(0);
4598 SDValue Idx = LegalizeOp(Op.getOperand(1));
4600 unsigned NumElems = Vec.getValueType().getVectorNumElements();
4602 if (NumElems == Op.getValueType().getVectorNumElements()) {
4603 // This must be an access of the desired vector length. Return it.
4607 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4609 SplitVectorOp(Vec, Lo, Hi);
4610 if (CIdx->getZExtValue() < NumElems/2) {
4614 Idx = DAG.getConstant(CIdx->getZExtValue() - NumElems/2,
4615 Idx.getValueType());
4618 // It's now an extract from the appropriate high or low part. Recurse.
4619 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4620 return ExpandEXTRACT_SUBVECTOR(Op);
4623 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
4624 /// with condition CC on the current target. This usually involves legalizing
4625 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
4626 /// there may be no choice but to create a new SetCC node to represent the
4627 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
4628 /// LHS, and the SDValue returned in RHS has a nil SDNode value.
4629 void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS,
4632 SDValue Tmp1, Tmp2, Tmp3, Result;
4634 switch (getTypeAction(LHS.getValueType())) {
4636 Tmp1 = LegalizeOp(LHS); // LHS
4637 Tmp2 = LegalizeOp(RHS); // RHS
4640 Tmp1 = PromoteOp(LHS); // LHS
4641 Tmp2 = PromoteOp(RHS); // RHS
4643 // If this is an FP compare, the operands have already been extended.
4644 if (LHS.getValueType().isInteger()) {
4645 MVT VT = LHS.getValueType();
4646 MVT NVT = TLI.getTypeToTransformTo(VT);
4648 // Otherwise, we have to insert explicit sign or zero extends. Note
4649 // that we could insert sign extends for ALL conditions, but zero extend
4650 // is cheaper on many machines (an AND instead of two shifts), so prefer
4652 switch (cast<CondCodeSDNode>(CC)->get()) {
4653 default: assert(0 && "Unknown integer comparison!");
4660 // ALL of these operations will work if we either sign or zero extend
4661 // the operands (including the unsigned comparisons!). Zero extend is
4662 // usually a simpler/cheaper operation, so prefer it.
4663 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4664 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4670 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4671 DAG.getValueType(VT));
4672 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4673 DAG.getValueType(VT));
4679 MVT VT = LHS.getValueType();
4680 if (VT == MVT::f32 || VT == MVT::f64) {
4681 // Expand into one or more soft-fp libcall(s).
4682 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
4683 switch (cast<CondCodeSDNode>(CC)->get()) {
4686 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4690 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
4694 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4698 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4702 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4706 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4709 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4712 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
4715 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4716 switch (cast<CondCodeSDNode>(CC)->get()) {
4718 // SETONE = SETOLT | SETOGT
4719 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4722 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4725 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4728 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4731 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4734 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4736 default: assert(0 && "Unsupported FP setcc!");
4741 SDValue Ops[2] = { LHS, RHS };
4742 Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2).getNode(),
4743 false /*sign irrelevant*/, Dummy);
4744 Tmp2 = DAG.getConstant(0, MVT::i32);
4745 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
4746 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
4747 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
4749 LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2).getNode(),
4750 false /*sign irrelevant*/, Dummy);
4751 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, Tmp2,
4752 DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
4753 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4756 LHS = LegalizeOp(Tmp1);
4761 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
4762 ExpandOp(LHS, LHSLo, LHSHi);
4763 ExpandOp(RHS, RHSLo, RHSHi);
4764 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
4766 if (VT==MVT::ppcf128) {
4767 // FIXME: This generated code sucks. We want to generate
4768 // FCMPU crN, hi1, hi2
4770 // FCMPU crN, lo1, lo2
4771 // The following can be improved, but not that much.
4772 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4774 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, CCCode);
4775 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4776 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4778 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode);
4779 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4780 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
4789 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
4790 if (RHSCST->isAllOnesValue()) {
4791 // Comparison to -1.
4792 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
4797 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
4798 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
4799 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4800 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
4803 // If this is a comparison of the sign bit, just look at the top part.
4805 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
4806 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
4807 CST->isNullValue()) || // X < 0
4808 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
4809 CST->isAllOnesValue())) { // X > -1
4815 // FIXME: This generated code sucks.
4816 ISD::CondCode LowCC;
4818 default: assert(0 && "Unknown integer setcc!");
4820 case ISD::SETULT: LowCC = ISD::SETULT; break;
4822 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
4824 case ISD::SETULE: LowCC = ISD::SETULE; break;
4826 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
4829 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
4830 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
4831 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
4833 // NOTE: on targets without efficient SELECT of bools, we can always use
4834 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
4835 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
4836 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo,
4837 LowCC, false, DagCombineInfo);
4838 if (!Tmp1.getNode())
4839 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC);
4840 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4841 CCCode, false, DagCombineInfo);
4842 if (!Tmp2.getNode())
4843 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi,
4846 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
4847 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
4848 if ((Tmp1C && Tmp1C->isNullValue()) ||
4849 (Tmp2C && Tmp2C->isNullValue() &&
4850 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
4851 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
4852 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
4853 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
4854 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
4855 // low part is known false, returns high part.
4856 // For LE / GE, if high part is known false, ignore the low part.
4857 // For LT / GT, if high part is known true, ignore the low part.
4861 Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4862 ISD::SETEQ, false, DagCombineInfo);
4863 if (!Result.getNode())
4864 Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4866 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
4867 Result, Tmp1, Tmp2));
4878 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
4879 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
4880 /// a load from the stack slot to DestVT, extending it if needed.
4881 /// The resultant code need not be legal.
4882 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
4885 // Create the stack frame object.
4886 unsigned SrcAlign = TLI.getTargetData()->getPrefTypeAlignment(
4887 SrcOp.getValueType().getTypeForMVT());
4888 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
4890 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
4891 int SPFI = StackPtrFI->getIndex();
4893 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
4894 unsigned SlotSize = SlotVT.getSizeInBits();
4895 unsigned DestSize = DestVT.getSizeInBits();
4896 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(
4897 DestVT.getTypeForMVT());
4899 // Emit a store to the stack slot. Use a truncstore if the input value is
4900 // later than DestVT.
4903 if (SrcSize > SlotSize)
4904 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr,
4905 PseudoSourceValue::getFixedStack(SPFI), 0,
4906 SlotVT, false, SrcAlign);
4908 assert(SrcSize == SlotSize && "Invalid store");
4909 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr,
4910 PseudoSourceValue::getFixedStack(SPFI), 0,
4914 // Result is a load from the stack slot.
4915 if (SlotSize == DestSize)
4916 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0, false, DestAlign);
4918 assert(SlotSize < DestSize && "Unknown extension!");
4919 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT,
4923 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
4924 // Create a vector sized/aligned stack slot, store the value to element #0,
4925 // then load the whole vector back out.
4926 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
4928 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
4929 int SPFI = StackPtrFI->getIndex();
4931 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
4932 PseudoSourceValue::getFixedStack(SPFI), 0);
4933 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,
4934 PseudoSourceValue::getFixedStack(SPFI), 0);
4938 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
4939 /// support the operation, but do support the resultant vector type.
4940 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
4942 // If the only non-undef value is the low element, turn this into a
4943 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
4944 unsigned NumElems = Node->getNumOperands();
4945 bool isOnlyLowElement = true;
4946 SDValue SplatValue = Node->getOperand(0);
4948 // FIXME: it would be far nicer to change this into map<SDValue,uint64_t>
4949 // and use a bitmask instead of a list of elements.
4950 std::map<SDValue, std::vector<unsigned> > Values;
4951 Values[SplatValue].push_back(0);
4952 bool isConstant = true;
4953 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
4954 SplatValue.getOpcode() != ISD::UNDEF)
4957 for (unsigned i = 1; i < NumElems; ++i) {
4958 SDValue V = Node->getOperand(i);
4959 Values[V].push_back(i);
4960 if (V.getOpcode() != ISD::UNDEF)
4961 isOnlyLowElement = false;
4962 if (SplatValue != V)
4963 SplatValue = SDValue(0,0);
4965 // If this isn't a constant element or an undef, we can't use a constant
4967 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
4968 V.getOpcode() != ISD::UNDEF)
4972 if (isOnlyLowElement) {
4973 // If the low element is an undef too, then this whole things is an undef.
4974 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
4975 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
4976 // Otherwise, turn this into a scalar_to_vector node.
4977 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4978 Node->getOperand(0));
4981 // If all elements are constants, create a load from the constant pool.
4983 MVT VT = Node->getValueType(0);
4984 std::vector<Constant*> CV;
4985 for (unsigned i = 0, e = NumElems; i != e; ++i) {
4986 if (ConstantFPSDNode *V =
4987 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
4988 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
4989 } else if (ConstantSDNode *V =
4990 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
4991 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
4993 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
4995 Node->getOperand(0).getValueType().getTypeForMVT();
4996 CV.push_back(UndefValue::get(OpNTy));
4999 Constant *CP = ConstantVector::get(CV);
5000 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
5001 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5002 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
5003 PseudoSourceValue::getConstantPool(), 0,
5007 if (SplatValue.getNode()) { // Splat of one value?
5008 // Build the shuffle constant vector: <0, 0, 0, 0>
5009 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
5010 SDValue Zero = DAG.getConstant(0, MaskVT.getVectorElementType());
5011 std::vector<SDValue> ZeroVec(NumElems, Zero);
5012 SDValue SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
5013 &ZeroVec[0], ZeroVec.size());
5015 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
5016 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
5017 // Get the splatted value into the low element of a vector register.
5019 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
5021 // Return shuffle(LowValVec, undef, <0,0,0,0>)
5022 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
5023 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
5028 // If there are only two unique elements, we may be able to turn this into a
5030 if (Values.size() == 2) {
5031 // Get the two values in deterministic order.
5032 SDValue Val1 = Node->getOperand(1);
5034 std::map<SDValue, std::vector<unsigned> >::iterator MI = Values.begin();
5035 if (MI->first != Val1)
5038 Val2 = (++MI)->first;
5040 // If Val1 is an undef, make sure end ends up as Val2, to ensure that our
5041 // vector shuffle has the undef vector on the RHS.
5042 if (Val1.getOpcode() == ISD::UNDEF)
5043 std::swap(Val1, Val2);
5045 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
5046 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
5047 MVT MaskEltVT = MaskVT.getVectorElementType();
5048 std::vector<SDValue> MaskVec(NumElems);
5050 // Set elements of the shuffle mask for Val1.
5051 std::vector<unsigned> &Val1Elts = Values[Val1];
5052 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i)
5053 MaskVec[Val1Elts[i]] = DAG.getConstant(0, MaskEltVT);
5055 // Set elements of the shuffle mask for Val2.
5056 std::vector<unsigned> &Val2Elts = Values[Val2];
5057 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i)
5058 if (Val2.getOpcode() != ISD::UNDEF)
5059 MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT);
5061 MaskVec[Val2Elts[i]] = DAG.getNode(ISD::UNDEF, MaskEltVT);
5063 SDValue ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
5064 &MaskVec[0], MaskVec.size());
5066 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it.
5067 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
5068 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
5069 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val1);
5070 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val2);
5071 SDValue Ops[] = { Val1, Val2, ShuffleMask };
5073 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
5074 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops, 3);
5078 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
5079 // aligned object on the stack, store each element into it, then load
5080 // the result as a vector.
5081 MVT VT = Node->getValueType(0);
5082 // Create the stack frame object.
5083 SDValue FIPtr = DAG.CreateStackTemporary(VT);
5085 // Emit a store of each element to the stack slot.
5086 SmallVector<SDValue, 8> Stores;
5087 unsigned TypeByteSize = Node->getOperand(0).getValueType().getSizeInBits()/8;
5088 // Store (in the right endianness) the elements to memory.
5089 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5090 // Ignore undef elements.
5091 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
5093 unsigned Offset = TypeByteSize*i;
5095 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
5096 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
5098 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
5103 if (!Stores.empty()) // Not all undef elements?
5104 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
5105 &Stores[0], Stores.size());
5107 StoreChain = DAG.getEntryNode();
5109 // Result is a load from the stack slot.
5110 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
5113 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
5114 SDValue Op, SDValue Amt,
5115 SDValue &Lo, SDValue &Hi) {
5116 // Expand the subcomponents.
5118 ExpandOp(Op, LHSL, LHSH);
5120 SDValue Ops[] = { LHSL, LHSH, Amt };
5121 MVT VT = LHSL.getValueType();
5122 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
5123 Hi = Lo.getValue(1);
5127 /// ExpandShift - Try to find a clever way to expand this shift operation out to
5128 /// smaller elements. If we can't find a way that is more efficient than a
5129 /// libcall on this target, return false. Otherwise, return true with the
5130 /// low-parts expanded into Lo and Hi.
5131 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op,SDValue Amt,
5132 SDValue &Lo, SDValue &Hi) {
5133 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
5134 "This is not a shift!");
5136 MVT NVT = TLI.getTypeToTransformTo(Op.getValueType());
5137 SDValue ShAmt = LegalizeOp(Amt);
5138 MVT ShTy = ShAmt.getValueType();
5139 unsigned ShBits = ShTy.getSizeInBits();
5140 unsigned VTBits = Op.getValueType().getSizeInBits();
5141 unsigned NVTBits = NVT.getSizeInBits();
5143 // Handle the case when Amt is an immediate.
5144 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.getNode())) {
5145 unsigned Cst = CN->getZExtValue();
5146 // Expand the incoming operand to be shifted, so that we have its parts
5148 ExpandOp(Op, InL, InH);
5152 Lo = DAG.getConstant(0, NVT);
5153 Hi = DAG.getConstant(0, NVT);
5154 } else if (Cst > NVTBits) {
5155 Lo = DAG.getConstant(0, NVT);
5156 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
5157 } else if (Cst == NVTBits) {
5158 Lo = DAG.getConstant(0, NVT);
5161 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
5162 Hi = DAG.getNode(ISD::OR, NVT,
5163 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
5164 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
5169 Lo = DAG.getConstant(0, NVT);
5170 Hi = DAG.getConstant(0, NVT);
5171 } else if (Cst > NVTBits) {
5172 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
5173 Hi = DAG.getConstant(0, NVT);
5174 } else if (Cst == NVTBits) {
5176 Hi = DAG.getConstant(0, NVT);
5178 Lo = DAG.getNode(ISD::OR, NVT,
5179 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5180 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5181 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
5186 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
5187 DAG.getConstant(NVTBits-1, ShTy));
5188 } else if (Cst > NVTBits) {
5189 Lo = DAG.getNode(ISD::SRA, NVT, InH,
5190 DAG.getConstant(Cst-NVTBits, ShTy));
5191 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5192 DAG.getConstant(NVTBits-1, ShTy));
5193 } else if (Cst == NVTBits) {
5195 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5196 DAG.getConstant(NVTBits-1, ShTy));
5198 Lo = DAG.getNode(ISD::OR, NVT,
5199 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5200 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5201 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
5207 // Okay, the shift amount isn't constant. However, if we can tell that it is
5208 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
5209 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
5210 APInt KnownZero, KnownOne;
5211 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
5213 // If we know that if any of the high bits of the shift amount are one, then
5214 // we can do this as a couple of simple shifts.
5215 if (KnownOne.intersects(Mask)) {
5216 // Mask out the high bit, which we know is set.
5217 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
5218 DAG.getConstant(~Mask, Amt.getValueType()));
5220 // Expand the incoming operand to be shifted, so that we have its parts
5222 ExpandOp(Op, InL, InH);
5225 Lo = DAG.getConstant(0, NVT); // Low part is zero.
5226 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
5229 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
5230 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
5233 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
5234 DAG.getConstant(NVTBits-1, Amt.getValueType()));
5235 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
5240 // If we know that the high bits of the shift amount are all zero, then we can
5241 // do this as a couple of simple shifts.
5242 if ((KnownZero & Mask) == Mask) {
5244 SDValue Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
5245 DAG.getConstant(NVTBits, Amt.getValueType()),
5248 // Expand the incoming operand to be shifted, so that we have its parts
5250 ExpandOp(Op, InL, InH);
5253 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
5254 Hi = DAG.getNode(ISD::OR, NVT,
5255 DAG.getNode(ISD::SHL, NVT, InH, Amt),
5256 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
5259 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
5260 Lo = DAG.getNode(ISD::OR, NVT,
5261 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5262 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5265 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
5266 Lo = DAG.getNode(ISD::OR, NVT,
5267 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5268 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5277 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
5278 // does not fit into a register, return the lo part and set the hi part to the
5279 // by-reg argument. If it does fit into a single register, return the result
5280 // and leave the Hi part unset.
5281 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
5282 bool isSigned, SDValue &Hi) {
5283 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
5284 // The input chain to this libcall is the entry node of the function.
5285 // Legalizing the call will automatically add the previous call to the
5287 SDValue InChain = DAG.getEntryNode();
5289 TargetLowering::ArgListTy Args;
5290 TargetLowering::ArgListEntry Entry;
5291 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5292 MVT ArgVT = Node->getOperand(i).getValueType();
5293 const Type *ArgTy = ArgVT.getTypeForMVT();
5294 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
5295 Entry.isSExt = isSigned;
5296 Entry.isZExt = !isSigned;
5297 Args.push_back(Entry);
5299 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
5300 TLI.getPointerTy());
5302 // Splice the libcall in wherever FindInputOutputChains tells us to.
5303 const Type *RetTy = Node->getValueType(0).getTypeForMVT();
5304 std::pair<SDValue,SDValue> CallInfo =
5305 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, CallingConv::C,
5306 false, Callee, Args, DAG);
5308 // Legalize the call sequence, starting with the chain. This will advance
5309 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
5310 // was added by LowerCallTo (guaranteeing proper serialization of calls).
5311 LegalizeOp(CallInfo.second);
5313 switch (getTypeAction(CallInfo.first.getValueType())) {
5314 default: assert(0 && "Unknown thing");
5316 Result = CallInfo.first;
5319 ExpandOp(CallInfo.first, Result, Hi);
5325 /// LegalizeINT_TO_FP - Legalize a [US]INT_TO_FP operation.
5327 SDValue SelectionDAGLegalize::
5328 LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op) {
5329 bool isCustom = false;
5331 switch (getTypeAction(Op.getValueType())) {
5333 switch (TLI.getOperationAction(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5334 Op.getValueType())) {
5335 default: assert(0 && "Unknown operation action!");
5336 case TargetLowering::Custom:
5339 case TargetLowering::Legal:
5340 Tmp1 = LegalizeOp(Op);
5341 if (Result.getNode())
5342 Result = DAG.UpdateNodeOperands(Result, Tmp1);
5344 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5347 Tmp1 = TLI.LowerOperation(Result, DAG);
5348 if (Tmp1.getNode()) Result = Tmp1;
5351 case TargetLowering::Expand:
5352 Result = ExpandLegalINT_TO_FP(isSigned, LegalizeOp(Op), DestTy);
5354 case TargetLowering::Promote:
5355 Result = PromoteLegalINT_TO_FP(LegalizeOp(Op), DestTy, isSigned);
5360 Result = ExpandIntToFP(isSigned, DestTy, Op);
5363 Tmp1 = PromoteOp(Op);
5365 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
5366 Tmp1, DAG.getValueType(Op.getValueType()));
5368 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
5371 if (Result.getNode())
5372 Result = DAG.UpdateNodeOperands(Result, Tmp1);
5374 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5376 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
5382 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
5384 SDValue SelectionDAGLegalize::
5385 ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source) {
5386 MVT SourceVT = Source.getValueType();
5387 bool ExpandSource = getTypeAction(SourceVT) == Expand;
5389 // Expand unsupported int-to-fp vector casts by unrolling them.
5390 if (DestTy.isVector()) {
5392 return LegalizeOp(UnrollVectorOp(Source));
5393 MVT DestEltTy = DestTy.getVectorElementType();
5394 if (DestTy.getVectorNumElements() == 1) {
5395 SDValue Scalar = ScalarizeVectorOp(Source);
5396 SDValue Result = LegalizeINT_TO_FP(SDValue(), isSigned,
5398 return DAG.getNode(ISD::BUILD_VECTOR, DestTy, Result);
5401 SplitVectorOp(Source, Lo, Hi);
5402 MVT SplitDestTy = MVT::getVectorVT(DestEltTy,
5403 DestTy.getVectorNumElements() / 2);
5404 SDValue LoResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, Lo);
5405 SDValue HiResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, Hi);
5406 return LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, DestTy, LoResult, HiResult));
5409 // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc.
5410 if (!isSigned && SourceVT != MVT::i32) {
5411 // The integer value loaded will be incorrectly if the 'sign bit' of the
5412 // incoming integer is set. To handle this, we dynamically test to see if
5413 // it is set, and, if so, add a fudge factor.
5417 ExpandOp(Source, Lo, Hi);
5418 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi);
5420 // The comparison for the sign bit will use the entire operand.
5424 // If this is unsigned, and not supported, first perform the conversion to
5425 // signed, then adjust the result if the sign bit is set.
5426 SDValue SignedConv = ExpandIntToFP(true, DestTy, Source);
5428 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
5429 DAG.getConstant(0, Hi.getValueType()),
5431 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5432 SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5433 SignSet, Four, Zero);
5434 uint64_t FF = 0x5f800000ULL;
5435 if (TLI.isLittleEndian()) FF <<= 32;
5436 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5438 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5439 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5440 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5442 if (DestTy == MVT::f32)
5443 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5444 PseudoSourceValue::getConstantPool(), 0,
5446 else if (DestTy.bitsGT(MVT::f32))
5447 // FIXME: Avoid the extend by construction the right constantpool?
5448 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
5450 PseudoSourceValue::getConstantPool(), 0,
5451 MVT::f32, false, Alignment);
5453 assert(0 && "Unexpected conversion");
5455 MVT SCVT = SignedConv.getValueType();
5456 if (SCVT != DestTy) {
5457 // Destination type needs to be expanded as well. The FADD now we are
5458 // constructing will be expanded into a libcall.
5459 if (SCVT.getSizeInBits() != DestTy.getSizeInBits()) {
5460 assert(SCVT.getSizeInBits() * 2 == DestTy.getSizeInBits());
5461 SignedConv = DAG.getNode(ISD::BUILD_PAIR, DestTy,
5462 SignedConv, SignedConv.getValue(1));
5464 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
5466 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
5469 // Check to see if the target has a custom way to lower this. If so, use it.
5470 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) {
5471 default: assert(0 && "This action not implemented for this operation!");
5472 case TargetLowering::Legal:
5473 case TargetLowering::Expand:
5474 break; // This case is handled below.
5475 case TargetLowering::Custom: {
5476 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
5479 return LegalizeOp(NV);
5480 break; // The target decided this was legal after all
5484 // Expand the source, then glue it back together for the call. We must expand
5485 // the source in case it is shared (this pass of legalize must traverse it).
5487 SDValue SrcLo, SrcHi;
5488 ExpandOp(Source, SrcLo, SrcHi);
5489 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, SrcLo, SrcHi);
5492 RTLIB::Libcall LC = isSigned ?
5493 RTLIB::getSINTTOFP(SourceVT, DestTy) :
5494 RTLIB::getUINTTOFP(SourceVT, DestTy);
5495 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unknown int value type");
5497 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
5499 SDValue Result = ExpandLibCall(LC, Source.getNode(), isSigned, HiPart);
5500 if (Result.getValueType() != DestTy && HiPart.getNode())
5501 Result = DAG.getNode(ISD::BUILD_PAIR, DestTy, Result, HiPart);
5505 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
5506 /// INT_TO_FP operation of the specified operand when the target requests that
5507 /// we expand it. At this point, we know that the result and operand types are
5508 /// legal for the target.
5509 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
5512 if (Op0.getValueType() == MVT::i32) {
5513 // simple 32-bit [signed|unsigned] integer to float/double expansion
5515 // Get the stack frame index of a 8 byte buffer.
5516 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
5518 // word offset constant for Hi/Lo address computation
5519 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
5520 // set up Hi and Lo (into buffer) address based on endian
5521 SDValue Hi = StackSlot;
5522 SDValue Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
5523 if (TLI.isLittleEndian())
5526 // if signed map to unsigned space
5529 // constant used to invert sign bit (signed to unsigned mapping)
5530 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
5531 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
5535 // store the lo of the constructed double - based on integer input
5536 SDValue Store1 = DAG.getStore(DAG.getEntryNode(),
5537 Op0Mapped, Lo, NULL, 0);
5538 // initial hi portion of constructed double
5539 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
5540 // store the hi of the constructed double - biased exponent
5541 SDValue Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
5542 // load the constructed double
5543 SDValue Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
5544 // FP constant to bias correct the final result
5545 SDValue Bias = DAG.getConstantFP(isSigned ?
5546 BitsToDouble(0x4330000080000000ULL)
5547 : BitsToDouble(0x4330000000000000ULL),
5549 // subtract the bias
5550 SDValue Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
5553 // handle final rounding
5554 if (DestVT == MVT::f64) {
5557 } else if (DestVT.bitsLT(MVT::f64)) {
5558 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub,
5559 DAG.getIntPtrConstant(0));
5560 } else if (DestVT.bitsGT(MVT::f64)) {
5561 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
5565 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
5566 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
5568 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Op0), Op0,
5569 DAG.getConstant(0, Op0.getValueType()),
5571 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5572 SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5573 SignSet, Four, Zero);
5575 // If the sign bit of the integer is set, the large number will be treated
5576 // as a negative number. To counteract this, the dynamic code adds an
5577 // offset depending on the data type.
5579 switch (Op0.getValueType().getSimpleVT()) {
5580 default: assert(0 && "Unsupported integer type!");
5581 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
5582 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
5583 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
5584 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
5586 if (TLI.isLittleEndian()) FF <<= 32;
5587 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5589 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5590 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5591 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5593 if (DestVT == MVT::f32)
5594 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5595 PseudoSourceValue::getConstantPool(), 0,
5599 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT,
5600 DAG.getEntryNode(), CPIdx,
5601 PseudoSourceValue::getConstantPool(), 0,
5602 MVT::f32, false, Alignment));
5605 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
5608 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
5609 /// *INT_TO_FP operation of the specified operand when the target requests that
5610 /// we promote it. At this point, we know that the result and operand types are
5611 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
5612 /// operation that takes a larger input.
5613 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
5616 // First step, figure out the appropriate *INT_TO_FP operation to use.
5617 MVT NewInTy = LegalOp.getValueType();
5619 unsigned OpToUse = 0;
5621 // Scan for the appropriate larger type to use.
5623 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
5624 assert(NewInTy.isInteger() && "Ran out of possibilities!");
5626 // If the target supports SINT_TO_FP of this type, use it.
5627 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
5629 case TargetLowering::Legal:
5630 if (!TLI.isTypeLegal(NewInTy))
5631 break; // Can't use this datatype.
5633 case TargetLowering::Custom:
5634 OpToUse = ISD::SINT_TO_FP;
5638 if (isSigned) continue;
5640 // If the target supports UINT_TO_FP of this type, use it.
5641 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
5643 case TargetLowering::Legal:
5644 if (!TLI.isTypeLegal(NewInTy))
5645 break; // Can't use this datatype.
5647 case TargetLowering::Custom:
5648 OpToUse = ISD::UINT_TO_FP;
5653 // Otherwise, try a larger type.
5656 // Okay, we found the operation and type to use. Zero extend our input to the
5657 // desired type then run the operation on it.
5658 return DAG.getNode(OpToUse, DestVT,
5659 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
5663 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
5664 /// FP_TO_*INT operation of the specified operand when the target requests that
5665 /// we promote it. At this point, we know that the result and operand types are
5666 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
5667 /// operation that returns a larger result.
5668 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
5671 // First step, figure out the appropriate FP_TO*INT operation to use.
5672 MVT NewOutTy = DestVT;
5674 unsigned OpToUse = 0;
5676 // Scan for the appropriate larger type to use.
5678 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1);
5679 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
5681 // If the target supports FP_TO_SINT returning this type, use it.
5682 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
5684 case TargetLowering::Legal:
5685 if (!TLI.isTypeLegal(NewOutTy))
5686 break; // Can't use this datatype.
5688 case TargetLowering::Custom:
5689 OpToUse = ISD::FP_TO_SINT;
5694 // If the target supports FP_TO_UINT of this type, use it.
5695 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
5697 case TargetLowering::Legal:
5698 if (!TLI.isTypeLegal(NewOutTy))
5699 break; // Can't use this datatype.
5701 case TargetLowering::Custom:
5702 OpToUse = ISD::FP_TO_UINT;
5707 // Otherwise, try a larger type.
5711 // Okay, we found the operation and type to use.
5712 SDValue Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp);
5714 // If the operation produces an invalid type, it must be custom lowered. Use
5715 // the target lowering hooks to expand it. Just keep the low part of the
5716 // expanded operation, we know that we're truncating anyway.
5717 if (getTypeAction(NewOutTy) == Expand) {
5718 Operation = SDValue(TLI.ReplaceNodeResults(Operation.getNode(), DAG), 0);
5719 assert(Operation.getNode() && "Didn't return anything");
5722 // Truncate the result of the extended FP_TO_*INT operation to the desired
5724 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation);
5727 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
5729 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op) {
5730 MVT VT = Op.getValueType();
5731 MVT SHVT = TLI.getShiftAmountTy();
5732 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
5733 switch (VT.getSimpleVT()) {
5734 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
5736 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5737 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5738 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
5740 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5741 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5742 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5743 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5744 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
5745 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
5746 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5747 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5748 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5750 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
5751 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
5752 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5753 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5754 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5755 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5756 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
5757 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
5758 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
5759 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
5760 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
5761 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
5762 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
5763 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
5764 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
5765 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
5766 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5767 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5768 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
5769 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5770 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
5774 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
5776 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op) {
5778 default: assert(0 && "Cannot expand this yet!");
5780 static const uint64_t mask[6] = {
5781 0x5555555555555555ULL, 0x3333333333333333ULL,
5782 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
5783 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
5785 MVT VT = Op.getValueType();
5786 MVT ShVT = TLI.getShiftAmountTy();
5787 unsigned len = VT.getSizeInBits();
5788 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5789 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
5790 SDValue Tmp2 = DAG.getConstant(mask[i], VT);
5791 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5792 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
5793 DAG.getNode(ISD::AND, VT,
5794 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
5799 // for now, we do this:
5800 // x = x | (x >> 1);
5801 // x = x | (x >> 2);
5803 // x = x | (x >>16);
5804 // x = x | (x >>32); // for 64-bit input
5805 // return popcount(~x);
5807 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
5808 MVT VT = Op.getValueType();
5809 MVT ShVT = TLI.getShiftAmountTy();
5810 unsigned len = VT.getSizeInBits();
5811 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5812 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5813 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
5815 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
5816 return DAG.getNode(ISD::CTPOP, VT, Op);
5819 // for now, we use: { return popcount(~x & (x - 1)); }
5820 // unless the target has ctlz but not ctpop, in which case we use:
5821 // { return 32 - nlz(~x & (x-1)); }
5822 // see also http://www.hackersdelight.org/HDcode/ntz.cc
5823 MVT VT = Op.getValueType();
5824 SDValue Tmp2 = DAG.getConstant(~0ULL, VT);
5825 SDValue Tmp3 = DAG.getNode(ISD::AND, VT,
5826 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
5827 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
5828 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
5829 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
5830 TLI.isOperationLegal(ISD::CTLZ, VT))
5831 return DAG.getNode(ISD::SUB, VT,
5832 DAG.getConstant(VT.getSizeInBits(), VT),
5833 DAG.getNode(ISD::CTLZ, VT, Tmp3));
5834 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
5839 /// ExpandOp - Expand the specified SDValue into its two component pieces
5840 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
5841 /// LegalizeNodes map is filled in for any results that are not expanded, the
5842 /// ExpandedNodes map is filled in for any results that are expanded, and the
5843 /// Lo/Hi values are returned.
5844 void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
5845 MVT VT = Op.getValueType();
5846 MVT NVT = TLI.getTypeToTransformTo(VT);
5847 SDNode *Node = Op.getNode();
5848 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
5849 assert(((NVT.isInteger() && NVT.bitsLT(VT)) || VT.isFloatingPoint() ||
5850 VT.isVector()) && "Cannot expand to FP value or to larger int value!");
5852 // See if we already expanded it.
5853 DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator I
5854 = ExpandedNodes.find(Op);
5855 if (I != ExpandedNodes.end()) {
5856 Lo = I->second.first;
5857 Hi = I->second.second;
5861 switch (Node->getOpcode()) {
5862 case ISD::CopyFromReg:
5863 assert(0 && "CopyFromReg must be legal!");
5864 case ISD::FP_ROUND_INREG:
5865 if (VT == MVT::ppcf128 &&
5866 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
5867 TargetLowering::Custom) {
5868 SDValue SrcLo, SrcHi, Src;
5869 ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
5870 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi);
5871 SDValue Result = TLI.LowerOperation(
5872 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG);
5873 assert(Result.getNode()->getOpcode() == ISD::BUILD_PAIR);
5874 Lo = Result.getNode()->getOperand(0);
5875 Hi = Result.getNode()->getOperand(1);
5881 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
5883 assert(0 && "Do not know how to expand this operator!");
5885 case ISD::EXTRACT_ELEMENT:
5886 ExpandOp(Node->getOperand(0), Lo, Hi);
5887 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
5888 return ExpandOp(Hi, Lo, Hi);
5889 return ExpandOp(Lo, Lo, Hi);
5890 case ISD::EXTRACT_VECTOR_ELT:
5891 assert(VT==MVT::i64 && "Do not know how to expand this operator!");
5892 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types.
5893 Lo = ExpandEXTRACT_VECTOR_ELT(Op);
5894 return ExpandOp(Lo, Lo, Hi);
5896 Lo = DAG.getNode(ISD::UNDEF, NVT);
5897 Hi = DAG.getNode(ISD::UNDEF, NVT);
5899 case ISD::Constant: {
5900 unsigned NVTBits = NVT.getSizeInBits();
5901 const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue();
5902 Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT);
5903 Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT);
5906 case ISD::ConstantFP: {
5907 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
5908 if (CFP->getValueType(0) == MVT::ppcf128) {
5909 APInt api = CFP->getValueAPF().convertToAPInt();
5910 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
5912 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
5916 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
5917 if (getTypeAction(Lo.getValueType()) == Expand)
5918 ExpandOp(Lo, Lo, Hi);
5921 case ISD::BUILD_PAIR:
5922 // Return the operands.
5923 Lo = Node->getOperand(0);
5924 Hi = Node->getOperand(1);
5927 case ISD::MERGE_VALUES:
5928 if (Node->getNumValues() == 1) {
5929 ExpandOp(Op.getOperand(0), Lo, Hi);
5932 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y)
5933 assert(Op.getResNo() == 0 && Node->getNumValues() == 2 &&
5934 Op.getValue(1).getValueType() == MVT::Other &&
5935 "unhandled MERGE_VALUES");
5936 ExpandOp(Op.getOperand(0), Lo, Hi);
5937 // Remember that we legalized the chain.
5938 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1)));
5941 case ISD::SIGN_EXTEND_INREG:
5942 ExpandOp(Node->getOperand(0), Lo, Hi);
5943 // sext_inreg the low part if needed.
5944 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
5946 // The high part gets the sign extension from the lo-part. This handles
5947 // things like sextinreg V:i64 from i8.
5948 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5949 DAG.getConstant(NVT.getSizeInBits()-1,
5950 TLI.getShiftAmountTy()));
5954 ExpandOp(Node->getOperand(0), Lo, Hi);
5955 SDValue TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
5956 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
5962 ExpandOp(Node->getOperand(0), Lo, Hi);
5963 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
5964 DAG.getNode(ISD::CTPOP, NVT, Lo),
5965 DAG.getNode(ISD::CTPOP, NVT, Hi));
5966 Hi = DAG.getConstant(0, NVT);
5970 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
5971 ExpandOp(Node->getOperand(0), Lo, Hi);
5972 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
5973 SDValue HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
5974 SDValue TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(HLZ), HLZ, BitsC,
5976 SDValue LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
5977 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
5979 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
5980 Hi = DAG.getConstant(0, NVT);
5985 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
5986 ExpandOp(Node->getOperand(0), Lo, Hi);
5987 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
5988 SDValue LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
5989 SDValue BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(LTZ), LTZ, BitsC,
5991 SDValue HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
5992 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
5994 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
5995 Hi = DAG.getConstant(0, NVT);
6000 SDValue Ch = Node->getOperand(0); // Legalize the chain.
6001 SDValue Ptr = Node->getOperand(1); // Legalize the pointer.
6002 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
6003 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
6005 // Remember that we legalized the chain.
6006 Hi = LegalizeOp(Hi);
6007 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
6008 if (TLI.isBigEndian())
6014 LoadSDNode *LD = cast<LoadSDNode>(Node);
6015 SDValue Ch = LD->getChain(); // Legalize the chain.
6016 SDValue Ptr = LD->getBasePtr(); // Legalize the pointer.
6017 ISD::LoadExtType ExtType = LD->getExtensionType();
6018 const Value *SV = LD->getSrcValue();
6019 int SVOffset = LD->getSrcValueOffset();
6020 unsigned Alignment = LD->getAlignment();
6021 bool isVolatile = LD->isVolatile();
6023 if (ExtType == ISD::NON_EXTLOAD) {
6024 Lo = DAG.getLoad(NVT, Ch, Ptr, SV, SVOffset,
6025 isVolatile, Alignment);
6026 if (VT == MVT::f32 || VT == MVT::f64) {
6027 // f32->i32 or f64->i64 one to one expansion.
6028 // Remember that we legalized the chain.
6029 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
6030 // Recursively expand the new load.
6031 if (getTypeAction(NVT) == Expand)
6032 ExpandOp(Lo, Lo, Hi);
6036 // Increment the pointer to the other half.
6037 unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8;
6038 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
6039 DAG.getIntPtrConstant(IncrementSize));
6040 SVOffset += IncrementSize;
6041 Alignment = MinAlign(Alignment, IncrementSize);
6042 Hi = DAG.getLoad(NVT, Ch, Ptr, SV, SVOffset,
6043 isVolatile, Alignment);
6045 // Build a factor node to remember that this load is independent of the
6047 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
6050 // Remember that we legalized the chain.
6051 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
6052 if (TLI.isBigEndian())
6055 MVT EVT = LD->getMemoryVT();
6057 if ((VT == MVT::f64 && EVT == MVT::f32) ||
6058 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
6059 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
6060 SDValue Load = DAG.getLoad(EVT, Ch, Ptr, SV,
6061 SVOffset, isVolatile, Alignment);
6062 // Remember that we legalized the chain.
6063 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Load.getValue(1)));
6064 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
6069 Lo = DAG.getLoad(NVT, Ch, Ptr, SV,
6070 SVOffset, isVolatile, Alignment);
6072 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, SV,
6073 SVOffset, EVT, isVolatile,
6076 // Remember that we legalized the chain.
6077 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
6079 if (ExtType == ISD::SEXTLOAD) {
6080 // The high part is obtained by SRA'ing all but one of the bits of the
6082 unsigned LoSize = Lo.getValueType().getSizeInBits();
6083 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6084 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6085 } else if (ExtType == ISD::ZEXTLOAD) {
6086 // The high part is just a zero.
6087 Hi = DAG.getConstant(0, NVT);
6088 } else /* if (ExtType == ISD::EXTLOAD) */ {
6089 // The high part is undefined.
6090 Hi = DAG.getNode(ISD::UNDEF, NVT);
6097 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
6098 SDValue LL, LH, RL, RH;
6099 ExpandOp(Node->getOperand(0), LL, LH);
6100 ExpandOp(Node->getOperand(1), RL, RH);
6101 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
6102 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
6106 SDValue LL, LH, RL, RH;
6107 ExpandOp(Node->getOperand(1), LL, LH);
6108 ExpandOp(Node->getOperand(2), RL, RH);
6109 if (getTypeAction(NVT) == Expand)
6110 NVT = TLI.getTypeToExpandTo(NVT);
6111 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
6113 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
6116 case ISD::SELECT_CC: {
6117 SDValue TL, TH, FL, FH;
6118 ExpandOp(Node->getOperand(2), TL, TH);
6119 ExpandOp(Node->getOperand(3), FL, FH);
6120 if (getTypeAction(NVT) == Expand)
6121 NVT = TLI.getTypeToExpandTo(NVT);
6122 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
6123 Node->getOperand(1), TL, FL, Node->getOperand(4));
6125 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
6126 Node->getOperand(1), TH, FH, Node->getOperand(4));
6129 case ISD::ANY_EXTEND:
6130 // The low part is any extension of the input (which degenerates to a copy).
6131 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
6132 // The high part is undefined.
6133 Hi = DAG.getNode(ISD::UNDEF, NVT);
6135 case ISD::SIGN_EXTEND: {
6136 // The low part is just a sign extension of the input (which degenerates to
6138 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
6140 // The high part is obtained by SRA'ing all but one of the bits of the lo
6142 unsigned LoSize = Lo.getValueType().getSizeInBits();
6143 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6144 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6147 case ISD::ZERO_EXTEND:
6148 // The low part is just a zero extension of the input (which degenerates to
6150 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
6152 // The high part is just a zero.
6153 Hi = DAG.getConstant(0, NVT);
6156 case ISD::TRUNCATE: {
6157 // The input value must be larger than this value. Expand *it*.
6159 ExpandOp(Node->getOperand(0), NewLo, Hi);
6161 // The low part is now either the right size, or it is closer. If not the
6162 // right size, make an illegal truncate so we recursively expand it.
6163 if (NewLo.getValueType() != Node->getValueType(0))
6164 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
6165 ExpandOp(NewLo, Lo, Hi);
6169 case ISD::BIT_CONVERT: {
6171 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
6172 // If the target wants to, allow it to lower this itself.
6173 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6174 case Expand: assert(0 && "cannot expand FP!");
6175 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
6176 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
6178 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
6181 // f32 / f64 must be expanded to i32 / i64.
6182 if (VT == MVT::f32 || VT == MVT::f64) {
6183 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6184 if (getTypeAction(NVT) == Expand)
6185 ExpandOp(Lo, Lo, Hi);
6189 // If source operand will be expanded to the same type as VT, i.e.
6190 // i64 <- f64, i32 <- f32, expand the source operand instead.
6191 MVT VT0 = Node->getOperand(0).getValueType();
6192 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
6193 ExpandOp(Node->getOperand(0), Lo, Hi);
6197 // Turn this into a load/store pair by default.
6198 if (Tmp.getNode() == 0)
6199 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT);
6201 ExpandOp(Tmp, Lo, Hi);
6205 case ISD::READCYCLECOUNTER: {
6206 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
6207 TargetLowering::Custom &&
6208 "Must custom expand ReadCycleCounter");
6209 SDValue Tmp = TLI.LowerOperation(Op, DAG);
6210 assert(Tmp.getNode() && "Node must be custom expanded!");
6211 ExpandOp(Tmp.getValue(0), Lo, Hi);
6212 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6213 LegalizeOp(Tmp.getValue(1)));
6217 // FIXME: should the LOAD_BIN and SWAP atomics get here too? Probably.
6218 case ISD::ATOMIC_CMP_SWAP_8:
6219 case ISD::ATOMIC_CMP_SWAP_16:
6220 case ISD::ATOMIC_CMP_SWAP_32:
6221 case ISD::ATOMIC_CMP_SWAP_64: {
6222 SDValue Tmp = TLI.LowerOperation(Op, DAG);
6223 assert(Tmp.getNode() && "Node must be custom expanded!");
6224 ExpandOp(Tmp.getValue(0), Lo, Hi);
6225 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6226 LegalizeOp(Tmp.getValue(1)));
6232 // These operators cannot be expanded directly, emit them as calls to
6233 // library functions.
6234 case ISD::FP_TO_SINT: {
6235 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
6237 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6238 case Expand: assert(0 && "cannot expand FP!");
6239 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6240 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6243 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
6245 // Now that the custom expander is done, expand the result, which is still
6248 ExpandOp(Op, Lo, Hi);
6253 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Node->getOperand(0).getValueType(),
6255 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected uint-to-fp conversion!");
6256 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6260 case ISD::FP_TO_UINT: {
6261 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
6263 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6264 case Expand: assert(0 && "cannot expand FP!");
6265 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6266 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6269 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
6271 // Now that the custom expander is done, expand the result.
6273 ExpandOp(Op, Lo, Hi);
6278 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Node->getOperand(0).getValueType(),
6280 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
6281 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6286 // If the target wants custom lowering, do so.
6287 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6288 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
6289 SDValue Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
6290 Op = TLI.LowerOperation(Op, DAG);
6292 // Now that the custom expander is done, expand the result, which is
6294 ExpandOp(Op, Lo, Hi);
6299 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
6300 // this X << 1 as X+X.
6301 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
6302 if (ShAmt->getAPIntValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
6303 TLI.isOperationLegal(ISD::ADDE, NVT)) {
6304 SDValue LoOps[2], HiOps[3];
6305 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
6306 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
6307 LoOps[1] = LoOps[0];
6308 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6310 HiOps[1] = HiOps[0];
6311 HiOps[2] = Lo.getValue(1);
6312 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6317 // If we can emit an efficient shift operation, do so now.
6318 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6321 // If this target supports SHL_PARTS, use it.
6322 TargetLowering::LegalizeAction Action =
6323 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
6324 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6325 Action == TargetLowering::Custom) {
6326 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6330 // Otherwise, emit a libcall.
6331 Lo = ExpandLibCall(RTLIB::SHL_I64, Node, false/*left shift=unsigned*/, Hi);
6336 // If the target wants custom lowering, do so.
6337 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6338 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
6339 SDValue Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
6340 Op = TLI.LowerOperation(Op, DAG);
6342 // Now that the custom expander is done, expand the result, which is
6344 ExpandOp(Op, Lo, Hi);
6349 // If we can emit an efficient shift operation, do so now.
6350 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
6353 // If this target supports SRA_PARTS, use it.
6354 TargetLowering::LegalizeAction Action =
6355 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
6356 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6357 Action == TargetLowering::Custom) {
6358 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6362 // Otherwise, emit a libcall.
6363 Lo = ExpandLibCall(RTLIB::SRA_I64, Node, true/*ashr is signed*/, Hi);
6368 // If the target wants custom lowering, do so.
6369 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6370 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
6371 SDValue Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
6372 Op = TLI.LowerOperation(Op, DAG);
6374 // Now that the custom expander is done, expand the result, which is
6376 ExpandOp(Op, Lo, Hi);
6381 // If we can emit an efficient shift operation, do so now.
6382 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6385 // If this target supports SRL_PARTS, use it.
6386 TargetLowering::LegalizeAction Action =
6387 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
6388 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6389 Action == TargetLowering::Custom) {
6390 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6394 // Otherwise, emit a libcall.
6395 Lo = ExpandLibCall(RTLIB::SRL_I64, Node, false/*lshr is unsigned*/, Hi);
6401 // If the target wants to custom expand this, let them.
6402 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
6403 TargetLowering::Custom) {
6404 SDValue Result = TLI.LowerOperation(Op, DAG);
6405 if (Result.getNode()) {
6406 ExpandOp(Result, Lo, Hi);
6411 // Expand the subcomponents.
6412 SDValue LHSL, LHSH, RHSL, RHSH;
6413 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6414 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6415 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6416 SDValue LoOps[2], HiOps[3];
6421 if (Node->getOpcode() == ISD::ADD) {
6422 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6423 HiOps[2] = Lo.getValue(1);
6424 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6426 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6427 HiOps[2] = Lo.getValue(1);
6428 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6435 // Expand the subcomponents.
6436 SDValue LHSL, LHSH, RHSL, RHSH;
6437 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6438 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6439 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6440 SDValue LoOps[2] = { LHSL, RHSL };
6441 SDValue HiOps[3] = { LHSH, RHSH };
6443 if (Node->getOpcode() == ISD::ADDC) {
6444 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6445 HiOps[2] = Lo.getValue(1);
6446 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6448 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6449 HiOps[2] = Lo.getValue(1);
6450 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6452 // Remember that we legalized the flag.
6453 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6458 // Expand the subcomponents.
6459 SDValue LHSL, LHSH, RHSL, RHSH;
6460 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6461 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6462 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6463 SDValue LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
6464 SDValue HiOps[3] = { LHSH, RHSH };
6466 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
6467 HiOps[2] = Lo.getValue(1);
6468 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
6470 // Remember that we legalized the flag.
6471 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6475 // If the target wants to custom expand this, let them.
6476 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
6477 SDValue New = TLI.LowerOperation(Op, DAG);
6478 if (New.getNode()) {
6479 ExpandOp(New, Lo, Hi);
6484 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
6485 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
6486 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
6487 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
6488 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
6489 SDValue LL, LH, RL, RH;
6490 ExpandOp(Node->getOperand(0), LL, LH);
6491 ExpandOp(Node->getOperand(1), RL, RH);
6492 unsigned OuterBitSize = Op.getValueSizeInBits();
6493 unsigned InnerBitSize = RH.getValueSizeInBits();
6494 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
6495 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
6496 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
6497 if (DAG.MaskedValueIsZero(Node->getOperand(0), HighMask) &&
6498 DAG.MaskedValueIsZero(Node->getOperand(1), HighMask)) {
6499 // The inputs are both zero-extended.
6501 // We can emit a umul_lohi.
6502 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6503 Hi = SDValue(Lo.getNode(), 1);
6507 // We can emit a mulhu+mul.
6508 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6509 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6513 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
6514 // The input values are both sign-extended.
6516 // We can emit a smul_lohi.
6517 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6518 Hi = SDValue(Lo.getNode(), 1);
6522 // We can emit a mulhs+mul.
6523 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6524 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
6529 // Lo,Hi = umul LHS, RHS.
6530 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
6531 DAG.getVTList(NVT, NVT), LL, RL);
6533 Hi = UMulLOHI.getValue(1);
6534 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6535 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6536 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6537 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6541 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6542 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6543 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6544 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6545 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6546 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6551 // If nothing else, we can make a libcall.
6552 Lo = ExpandLibCall(RTLIB::MUL_I64, Node, false/*sign irrelevant*/, Hi);
6556 Lo = ExpandLibCall(RTLIB::SDIV_I64, Node, true, Hi);
6559 Lo = ExpandLibCall(RTLIB::UDIV_I64, Node, true, Hi);
6562 Lo = ExpandLibCall(RTLIB::SREM_I64, Node, true, Hi);
6565 Lo = ExpandLibCall(RTLIB::UREM_I64, Node, true, Hi);
6569 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::ADD_F32,
6572 RTLIB::ADD_PPCF128),
6576 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::SUB_F32,
6579 RTLIB::SUB_PPCF128),
6583 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::MUL_F32,
6586 RTLIB::MUL_PPCF128),
6590 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::DIV_F32,
6593 RTLIB::DIV_PPCF128),
6596 case ISD::FP_EXTEND: {
6597 if (VT == MVT::ppcf128) {
6598 assert(Node->getOperand(0).getValueType()==MVT::f32 ||
6599 Node->getOperand(0).getValueType()==MVT::f64);
6600 const uint64_t zero = 0;
6601 if (Node->getOperand(0).getValueType()==MVT::f32)
6602 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0));
6604 Hi = Node->getOperand(0);
6605 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6608 RTLIB::Libcall LC = RTLIB::getFPEXT(Node->getOperand(0).getValueType(), VT);
6609 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!");
6610 Lo = ExpandLibCall(LC, Node, true, Hi);
6613 case ISD::FP_ROUND: {
6614 RTLIB::Libcall LC = RTLIB::getFPROUND(Node->getOperand(0).getValueType(),
6616 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!");
6617 Lo = ExpandLibCall(LC, Node, true, Hi);
6632 case ISD::FNEARBYINT:
6635 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6636 switch(Node->getOpcode()) {
6638 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
6639 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
6642 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
6643 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
6646 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
6647 RTLIB::COS_F80, RTLIB::COS_PPCF128);
6650 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
6651 RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
6654 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
6655 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
6658 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
6659 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
6662 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
6663 RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
6666 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
6667 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
6670 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
6671 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
6674 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
6675 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128);
6678 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
6679 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128);
6682 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64,
6683 RTLIB::RINT_F80, RTLIB::RINT_PPCF128);
6685 case ISD::FNEARBYINT:
6686 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
6687 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
6690 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
6691 RTLIB::POW_PPCF128);
6694 LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64, RTLIB::POWI_F80,
6695 RTLIB::POWI_PPCF128);
6697 default: assert(0 && "Unreachable!");
6699 Lo = ExpandLibCall(LC, Node, false, Hi);
6703 if (VT == MVT::ppcf128) {
6705 ExpandOp(Node->getOperand(0), Lo, Tmp);
6706 Hi = DAG.getNode(ISD::FABS, NVT, Tmp);
6707 // lo = hi==fabs(hi) ? lo : -lo;
6708 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp,
6709 Lo, DAG.getNode(ISD::FNEG, NVT, Lo),
6710 DAG.getCondCode(ISD::SETEQ));
6713 SDValue Mask = (VT == MVT::f64)
6714 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
6715 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
6716 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6717 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6718 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
6719 if (getTypeAction(NVT) == Expand)
6720 ExpandOp(Lo, Lo, Hi);
6724 if (VT == MVT::ppcf128) {
6725 ExpandOp(Node->getOperand(0), Lo, Hi);
6726 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo);
6727 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi);
6730 SDValue Mask = (VT == MVT::f64)
6731 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
6732 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
6733 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6734 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6735 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
6736 if (getTypeAction(NVT) == Expand)
6737 ExpandOp(Lo, Lo, Hi);
6740 case ISD::FCOPYSIGN: {
6741 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
6742 if (getTypeAction(NVT) == Expand)
6743 ExpandOp(Lo, Lo, Hi);
6746 case ISD::SINT_TO_FP:
6747 case ISD::UINT_TO_FP: {
6748 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
6749 MVT SrcVT = Node->getOperand(0).getValueType();
6751 // Promote the operand if needed. Do this before checking for
6752 // ppcf128 so conversions of i16 and i8 work.
6753 if (getTypeAction(SrcVT) == Promote) {
6754 SDValue Tmp = PromoteOp(Node->getOperand(0));
6756 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
6757 DAG.getValueType(SrcVT))
6758 : DAG.getZeroExtendInReg(Tmp, SrcVT);
6759 Node = DAG.UpdateNodeOperands(Op, Tmp).getNode();
6760 SrcVT = Node->getOperand(0).getValueType();
6763 if (VT == MVT::ppcf128 && SrcVT == MVT::i32) {
6764 static const uint64_t zero = 0;
6766 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6767 Node->getOperand(0)));
6768 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6770 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
6771 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6772 Node->getOperand(0)));
6773 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6774 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6775 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
6776 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6777 DAG.getConstant(0, MVT::i32),
6778 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6780 APFloat(APInt(128, 2, TwoE32)),
6783 DAG.getCondCode(ISD::SETLT)),
6788 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) {
6789 // si64->ppcf128 done by libcall, below
6790 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
6791 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)),
6793 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6794 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
6795 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6796 DAG.getConstant(0, MVT::i64),
6797 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6799 APFloat(APInt(128, 2, TwoE64)),
6802 DAG.getCondCode(ISD::SETLT)),
6807 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
6808 Node->getOperand(0));
6809 if (getTypeAction(Lo.getValueType()) == Expand)
6810 // float to i32 etc. can be 'expanded' to a single node.
6811 ExpandOp(Lo, Lo, Hi);
6816 // Make sure the resultant values have been legalized themselves, unless this
6817 // is a type that requires multi-step expansion.
6818 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
6819 Lo = LegalizeOp(Lo);
6821 // Don't legalize the high part if it is expanded to a single node.
6822 Hi = LegalizeOp(Hi);
6825 // Remember in a map if the values will be reused later.
6827 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
6828 assert(isNew && "Value already expanded?!?");
6831 /// SplitVectorOp - Given an operand of vector type, break it down into
6832 /// two smaller values, still of vector type.
6833 void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
6835 assert(Op.getValueType().isVector() && "Cannot split non-vector type!");
6836 SDNode *Node = Op.getNode();
6837 unsigned NumElements = Op.getValueType().getVectorNumElements();
6838 assert(NumElements > 1 && "Cannot split a single element vector!");
6840 MVT NewEltVT = Op.getValueType().getVectorElementType();
6842 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
6843 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
6845 MVT NewVT_Lo = MVT::getVectorVT(NewEltVT, NewNumElts_Lo);
6846 MVT NewVT_Hi = MVT::getVectorVT(NewEltVT, NewNumElts_Hi);
6848 // See if we already split it.
6849 std::map<SDValue, std::pair<SDValue, SDValue> >::iterator I
6850 = SplitNodes.find(Op);
6851 if (I != SplitNodes.end()) {
6852 Lo = I->second.first;
6853 Hi = I->second.second;
6857 switch (Node->getOpcode()) {
6862 assert(0 && "Unhandled operation in SplitVectorOp!");
6864 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo);
6865 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi);
6867 case ISD::BUILD_PAIR:
6868 Lo = Node->getOperand(0);
6869 Hi = Node->getOperand(1);
6871 case ISD::INSERT_VECTOR_ELT: {
6872 if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) {
6873 SplitVectorOp(Node->getOperand(0), Lo, Hi);
6874 unsigned Index = Idx->getZExtValue();
6875 SDValue ScalarOp = Node->getOperand(1);
6876 if (Index < NewNumElts_Lo)
6877 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp,
6878 DAG.getIntPtrConstant(Index));
6880 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp,
6881 DAG.getIntPtrConstant(Index - NewNumElts_Lo));
6884 SDValue Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0),
6885 Node->getOperand(1),
6886 Node->getOperand(2));
6887 SplitVectorOp(Tmp, Lo, Hi);
6890 case ISD::VECTOR_SHUFFLE: {
6891 // Build the low part.
6892 SDValue Mask = Node->getOperand(2);
6893 SmallVector<SDValue, 8> Ops;
6894 MVT PtrVT = TLI.getPointerTy();
6896 // Insert all of the elements from the input that are needed. We use
6897 // buildvector of extractelement here because the input vectors will have
6898 // to be legalized, so this makes the code simpler.
6899 for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
6900 SDValue IdxNode = Mask.getOperand(i);
6901 if (IdxNode.getOpcode() == ISD::UNDEF) {
6902 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
6905 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
6906 SDValue InVec = Node->getOperand(0);
6907 if (Idx >= NumElements) {
6908 InVec = Node->getOperand(1);
6911 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6912 DAG.getConstant(Idx, PtrVT)));
6914 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6917 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
6918 SDValue IdxNode = Mask.getOperand(i);
6919 if (IdxNode.getOpcode() == ISD::UNDEF) {
6920 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
6923 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
6924 SDValue InVec = Node->getOperand(0);
6925 if (Idx >= NumElements) {
6926 InVec = Node->getOperand(1);
6929 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6930 DAG.getConstant(Idx, PtrVT)));
6932 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &Ops[0], Ops.size());
6935 case ISD::BUILD_VECTOR: {
6936 SmallVector<SDValue, 8> LoOps(Node->op_begin(),
6937 Node->op_begin()+NewNumElts_Lo);
6938 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size());
6940 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
6942 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size());
6945 case ISD::CONCAT_VECTORS: {
6946 // FIXME: Handle non-power-of-two vectors?
6947 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
6948 if (NewNumSubvectors == 1) {
6949 Lo = Node->getOperand(0);
6950 Hi = Node->getOperand(1);
6952 SmallVector<SDValue, 8> LoOps(Node->op_begin(),
6953 Node->op_begin()+NewNumSubvectors);
6954 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size());
6956 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumSubvectors,
6958 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size());
6963 SDValue Cond = Node->getOperand(0);
6965 SDValue LL, LH, RL, RH;
6966 SplitVectorOp(Node->getOperand(1), LL, LH);
6967 SplitVectorOp(Node->getOperand(2), RL, RH);
6969 if (Cond.getValueType().isVector()) {
6970 // Handle a vector merge.
6972 SplitVectorOp(Cond, CL, CH);
6973 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL);
6974 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH);
6976 // Handle a simple select with vector operands.
6977 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL);
6978 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH);
6982 case ISD::SELECT_CC: {
6983 SDValue CondLHS = Node->getOperand(0);
6984 SDValue CondRHS = Node->getOperand(1);
6985 SDValue CondCode = Node->getOperand(4);
6987 SDValue LL, LH, RL, RH;
6988 SplitVectorOp(Node->getOperand(2), LL, LH);
6989 SplitVectorOp(Node->getOperand(3), RL, RH);
6991 // Handle a simple select with vector operands.
6992 Lo = DAG.getNode(ISD::SELECT_CC, NewVT_Lo, CondLHS, CondRHS,
6994 Hi = DAG.getNode(ISD::SELECT_CC, NewVT_Hi, CondLHS, CondRHS,
6999 SDValue LL, LH, RL, RH;
7000 SplitVectorOp(Node->getOperand(0), LL, LH);
7001 SplitVectorOp(Node->getOperand(1), RL, RH);
7002 Lo = DAG.getNode(ISD::VSETCC, NewVT_Lo, LL, RL, Node->getOperand(2));
7003 Hi = DAG.getNode(ISD::VSETCC, NewVT_Hi, LH, RH, Node->getOperand(2));
7022 SDValue LL, LH, RL, RH;
7023 SplitVectorOp(Node->getOperand(0), LL, LH);
7024 SplitVectorOp(Node->getOperand(1), RL, RH);
7026 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL);
7027 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH);
7033 SplitVectorOp(Node->getOperand(0), L, H);
7035 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1));
7036 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1));
7052 case ISD::FP_TO_SINT:
7053 case ISD::FP_TO_UINT:
7054 case ISD::SINT_TO_FP:
7055 case ISD::UINT_TO_FP:
7057 case ISD::ANY_EXTEND:
7058 case ISD::SIGN_EXTEND:
7059 case ISD::ZERO_EXTEND:
7060 case ISD::FP_EXTEND: {
7062 SplitVectorOp(Node->getOperand(0), L, H);
7064 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L);
7065 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H);
7069 LoadSDNode *LD = cast<LoadSDNode>(Node);
7070 SDValue Ch = LD->getChain();
7071 SDValue Ptr = LD->getBasePtr();
7072 ISD::LoadExtType ExtType = LD->getExtensionType();
7073 const Value *SV = LD->getSrcValue();
7074 int SVOffset = LD->getSrcValueOffset();
7075 MVT MemoryVT = LD->getMemoryVT();
7076 unsigned Alignment = LD->getAlignment();
7077 bool isVolatile = LD->isVolatile();
7079 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
7080 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType());
7082 MVT MemNewEltVT = MemoryVT.getVectorElementType();
7083 MVT MemNewVT_Lo = MVT::getVectorVT(MemNewEltVT, NewNumElts_Lo);
7084 MVT MemNewVT_Hi = MVT::getVectorVT(MemNewEltVT, NewNumElts_Hi);
7086 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType,
7087 NewVT_Lo, Ch, Ptr, Offset,
7088 SV, SVOffset, MemNewVT_Lo, isVolatile, Alignment);
7089 unsigned IncrementSize = NewNumElts_Lo * MemNewEltVT.getSizeInBits()/8;
7090 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
7091 DAG.getIntPtrConstant(IncrementSize));
7092 SVOffset += IncrementSize;
7093 Alignment = MinAlign(Alignment, IncrementSize);
7094 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType,
7095 NewVT_Hi, Ch, Ptr, Offset,
7096 SV, SVOffset, MemNewVT_Hi, isVolatile, Alignment);
7098 // Build a factor node to remember that this load is independent of the
7100 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
7103 // Remember that we legalized the chain.
7104 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
7107 case ISD::BIT_CONVERT: {
7108 // We know the result is a vector. The input may be either a vector or a
7110 SDValue InOp = Node->getOperand(0);
7111 if (!InOp.getValueType().isVector() ||
7112 InOp.getValueType().getVectorNumElements() == 1) {
7113 // The input is a scalar or single-element vector.
7114 // Lower to a store/load so that it can be split.
7115 // FIXME: this could be improved probably.
7116 unsigned LdAlign = TLI.getTargetData()->getPrefTypeAlignment(
7117 Op.getValueType().getTypeForMVT());
7118 SDValue Ptr = DAG.CreateStackTemporary(InOp.getValueType(), LdAlign);
7119 int FI = cast<FrameIndexSDNode>(Ptr.getNode())->getIndex();
7121 SDValue St = DAG.getStore(DAG.getEntryNode(),
7123 PseudoSourceValue::getFixedStack(FI), 0);
7124 InOp = DAG.getLoad(Op.getValueType(), St, Ptr,
7125 PseudoSourceValue::getFixedStack(FI), 0);
7127 // Split the vector and convert each of the pieces now.
7128 SplitVectorOp(InOp, Lo, Hi);
7129 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo);
7130 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi);
7135 // Remember in a map if the values will be reused later.
7137 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
7138 assert(isNew && "Value already split?!?");
7142 /// ScalarizeVectorOp - Given an operand of single-element vector type
7143 /// (e.g. v1f32), convert it into the equivalent operation that returns a
7144 /// scalar (e.g. f32) value.
7145 SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) {
7146 assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!");
7147 SDNode *Node = Op.getNode();
7148 MVT NewVT = Op.getValueType().getVectorElementType();
7149 assert(Op.getValueType().getVectorNumElements() == 1);
7151 // See if we already scalarized it.
7152 std::map<SDValue, SDValue>::iterator I = ScalarizedNodes.find(Op);
7153 if (I != ScalarizedNodes.end()) return I->second;
7156 switch (Node->getOpcode()) {
7159 Node->dump(&DAG); cerr << "\n";
7161 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
7178 Result = DAG.getNode(Node->getOpcode(),
7180 ScalarizeVectorOp(Node->getOperand(0)),
7181 ScalarizeVectorOp(Node->getOperand(1)));
7193 case ISD::FP_TO_SINT:
7194 case ISD::FP_TO_UINT:
7195 case ISD::SINT_TO_FP:
7196 case ISD::UINT_TO_FP:
7197 case ISD::SIGN_EXTEND:
7198 case ISD::ZERO_EXTEND:
7199 case ISD::ANY_EXTEND:
7201 case ISD::FP_EXTEND:
7202 Result = DAG.getNode(Node->getOpcode(),
7204 ScalarizeVectorOp(Node->getOperand(0)));
7208 Result = DAG.getNode(Node->getOpcode(),
7210 ScalarizeVectorOp(Node->getOperand(0)),
7211 Node->getOperand(1));
7214 LoadSDNode *LD = cast<LoadSDNode>(Node);
7215 SDValue Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
7216 SDValue Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
7217 ISD::LoadExtType ExtType = LD->getExtensionType();
7218 const Value *SV = LD->getSrcValue();
7219 int SVOffset = LD->getSrcValueOffset();
7220 MVT MemoryVT = LD->getMemoryVT();
7221 unsigned Alignment = LD->getAlignment();
7222 bool isVolatile = LD->isVolatile();
7224 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
7225 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType());
7227 Result = DAG.getLoad(ISD::UNINDEXED, ExtType,
7228 NewVT, Ch, Ptr, Offset, SV, SVOffset,
7229 MemoryVT.getVectorElementType(),
7230 isVolatile, Alignment);
7232 // Remember that we legalized the chain.
7233 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
7236 case ISD::BUILD_VECTOR:
7237 Result = Node->getOperand(0);
7239 case ISD::INSERT_VECTOR_ELT:
7240 // Returning the inserted scalar element.
7241 Result = Node->getOperand(1);
7243 case ISD::CONCAT_VECTORS:
7244 assert(Node->getOperand(0).getValueType() == NewVT &&
7245 "Concat of non-legal vectors not yet supported!");
7246 Result = Node->getOperand(0);
7248 case ISD::VECTOR_SHUFFLE: {
7249 // Figure out if the scalar is the LHS or RHS and return it.
7250 SDValue EltNum = Node->getOperand(2).getOperand(0);
7251 if (cast<ConstantSDNode>(EltNum)->getZExtValue())
7252 Result = ScalarizeVectorOp(Node->getOperand(1));
7254 Result = ScalarizeVectorOp(Node->getOperand(0));
7257 case ISD::EXTRACT_SUBVECTOR:
7258 Result = Node->getOperand(0);
7259 assert(Result.getValueType() == NewVT);
7261 case ISD::BIT_CONVERT: {
7262 SDValue Op0 = Op.getOperand(0);
7263 if (Op0.getValueType().getVectorNumElements() == 1)
7264 Op0 = ScalarizeVectorOp(Op0);
7265 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op0);
7269 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
7270 ScalarizeVectorOp(Op.getOperand(1)),
7271 ScalarizeVectorOp(Op.getOperand(2)));
7273 case ISD::SELECT_CC:
7274 Result = DAG.getNode(ISD::SELECT_CC, NewVT, Node->getOperand(0),
7275 Node->getOperand(1),
7276 ScalarizeVectorOp(Op.getOperand(2)),
7277 ScalarizeVectorOp(Op.getOperand(3)),
7278 Node->getOperand(4));
7281 SDValue Op0 = ScalarizeVectorOp(Op.getOperand(0));
7282 SDValue Op1 = ScalarizeVectorOp(Op.getOperand(1));
7283 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Op0), Op0, Op1,
7285 Result = DAG.getNode(ISD::SELECT, NewVT, Result,
7286 DAG.getConstant(-1ULL, NewVT),
7287 DAG.getConstant(0ULL, NewVT));
7292 if (TLI.isTypeLegal(NewVT))
7293 Result = LegalizeOp(Result);
7294 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
7295 assert(isNew && "Value already scalarized?");
7300 // SelectionDAG::Legalize - This is the entry point for the file.
7302 void SelectionDAG::Legalize() {
7303 /// run - This is the main entry point to this class.
7305 SelectionDAGLegalize(*this).LegalizeDAG();