1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/CodeGen/PseudoSourceValue.h"
20 #include "llvm/Target/TargetFrameInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/Target/TargetData.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/Target/TargetSubtarget.h"
26 #include "llvm/CallingConv.h"
27 #include "llvm/Constants.h"
28 #include "llvm/DerivedTypes.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Compiler.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/ADT/DenseMap.h"
33 #include "llvm/ADT/SmallVector.h"
34 #include "llvm/ADT/SmallPtrSet.h"
38 //===----------------------------------------------------------------------===//
39 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
40 /// hacks on it until the target machine can handle it. This involves
41 /// eliminating value sizes the machine cannot handle (promoting small sizes to
42 /// large sizes or splitting up large values into small values) as well as
43 /// eliminating operations the machine cannot handle.
45 /// This code also does a small amount of optimization and recognition of idioms
46 /// as part of its processing. For example, if a target does not support a
47 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
48 /// will attempt merge setcc and brc instructions into brcc's.
51 class VISIBILITY_HIDDEN SelectionDAGLegalize {
55 // Libcall insertion helpers.
57 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
58 /// legalized. We use this to ensure that calls are properly serialized
59 /// against each other, including inserted libcalls.
60 SDValue LastCALLSEQ_END;
62 /// IsLegalizingCall - This member is used *only* for purposes of providing
63 /// helpful assertions that a libcall isn't created while another call is
64 /// being legalized (which could lead to non-serialized call sequences).
65 bool IsLegalizingCall;
68 Legal, // The target natively supports this operation.
69 Promote, // This operation should be executed in a larger type.
70 Expand // Try to expand this to other ops, otherwise use a libcall.
73 /// ValueTypeActions - This is a bitvector that contains two bits for each
74 /// value type, where the two bits correspond to the LegalizeAction enum.
75 /// This can be queried with "getTypeAction(VT)".
76 TargetLowering::ValueTypeActionImpl ValueTypeActions;
78 /// LegalizedNodes - For nodes that are of legal width, and that have more
79 /// than one use, this map indicates what regularized operand to use. This
80 /// allows us to avoid legalizing the same thing more than once.
81 DenseMap<SDValue, SDValue> LegalizedNodes;
83 /// PromotedNodes - For nodes that are below legal width, and that have more
84 /// than one use, this map indicates what promoted value to use. This allows
85 /// us to avoid promoting the same thing more than once.
86 DenseMap<SDValue, SDValue> PromotedNodes;
88 /// ExpandedNodes - For nodes that need to be expanded this map indicates
89 /// which which operands are the expanded version of the input. This allows
90 /// us to avoid expanding the same node more than once.
91 DenseMap<SDValue, std::pair<SDValue, SDValue> > ExpandedNodes;
93 /// SplitNodes - For vector nodes that need to be split, this map indicates
94 /// which which operands are the split version of the input. This allows us
95 /// to avoid splitting the same node more than once.
96 std::map<SDValue, std::pair<SDValue, SDValue> > SplitNodes;
98 /// ScalarizedNodes - For nodes that need to be converted from vector types to
99 /// scalar types, this contains the mapping of ones we have already
100 /// processed to the result.
101 std::map<SDValue, SDValue> ScalarizedNodes;
103 void AddLegalizedOperand(SDValue From, SDValue To) {
104 LegalizedNodes.insert(std::make_pair(From, To));
105 // If someone requests legalization of the new node, return itself.
107 LegalizedNodes.insert(std::make_pair(To, To));
109 void AddPromotedOperand(SDValue From, SDValue To) {
110 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
111 assert(isNew && "Got into the map somehow?");
112 // If someone requests legalization of the new node, return itself.
113 LegalizedNodes.insert(std::make_pair(To, To));
117 explicit SelectionDAGLegalize(SelectionDAG &DAG);
119 /// getTypeAction - Return how we should legalize values of this type, either
120 /// it is already legal or we need to expand it into multiple registers of
121 /// smaller integer type, or we need to promote it to a larger type.
122 LegalizeAction getTypeAction(MVT VT) const {
123 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
126 /// isTypeLegal - Return true if this type is legal on this target.
128 bool isTypeLegal(MVT VT) const {
129 return getTypeAction(VT) == Legal;
135 /// HandleOp - Legalize, Promote, or Expand the specified operand as
136 /// appropriate for its type.
137 void HandleOp(SDValue Op);
139 /// LegalizeOp - We know that the specified value has a legal type.
140 /// Recursively ensure that the operands have legal types, then return the
142 SDValue LegalizeOp(SDValue O);
144 /// UnrollVectorOp - We know that the given vector has a legal type, however
145 /// the operation it performs is not legal and is an operation that we have
146 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
147 /// operating on each element individually.
148 SDValue UnrollVectorOp(SDValue O);
150 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
151 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
152 /// is necessary to spill the vector being inserted into to memory, perform
153 /// the insert there, and then read the result back.
154 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
157 /// PromoteOp - Given an operation that produces a value in an invalid type,
158 /// promote it to compute the value into a larger type. The produced value
159 /// will have the correct bits for the low portion of the register, but no
160 /// guarantee is made about the top bits: it may be zero, sign-extended, or
162 SDValue PromoteOp(SDValue O);
164 /// ExpandOp - Expand the specified SDValue into its two component pieces
165 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
166 /// the LegalizeNodes map is filled in for any results that are not expanded,
167 /// the ExpandedNodes map is filled in for any results that are expanded, and
168 /// the Lo/Hi values are returned. This applies to integer types and Vector
170 void ExpandOp(SDValue O, SDValue &Lo, SDValue &Hi);
172 /// SplitVectorOp - Given an operand of vector type, break it down into
173 /// two smaller values.
174 void SplitVectorOp(SDValue O, SDValue &Lo, SDValue &Hi);
176 /// ScalarizeVectorOp - Given an operand of single-element vector type
177 /// (e.g. v1f32), convert it into the equivalent operation that returns a
178 /// scalar (e.g. f32) value.
179 SDValue ScalarizeVectorOp(SDValue O);
181 /// isShuffleLegal - Return non-null if a vector shuffle is legal with the
182 /// specified mask and type. Targets can specify exactly which masks they
183 /// support and the code generator is tasked with not creating illegal masks.
185 /// Note that this will also return true for shuffles that are promoted to a
188 /// If this is a legal shuffle, this method returns the (possibly promoted)
189 /// build_vector Mask. If it's not a legal shuffle, it returns null.
190 SDNode *isShuffleLegal(MVT VT, SDValue Mask) const;
192 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
193 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
195 void LegalizeSetCCOperands(SDValue &LHS, SDValue &RHS, SDValue &CC);
197 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned,
199 SDValue ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source);
201 SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT);
202 SDValue ExpandBUILD_VECTOR(SDNode *Node);
203 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
204 SDValue LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op);
205 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT);
206 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, bool isSigned);
207 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned);
209 SDValue ExpandBSWAP(SDValue Op);
210 SDValue ExpandBitCount(unsigned Opc, SDValue Op);
211 bool ExpandShift(unsigned Opc, SDValue Op, SDValue Amt,
212 SDValue &Lo, SDValue &Hi);
213 void ExpandShiftParts(unsigned NodeOp, SDValue Op, SDValue Amt,
214 SDValue &Lo, SDValue &Hi);
216 SDValue ExpandEXTRACT_SUBVECTOR(SDValue Op);
217 SDValue ExpandEXTRACT_VECTOR_ELT(SDValue Op);
221 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
222 /// specified mask and type. Targets can specify exactly which masks they
223 /// support and the code generator is tasked with not creating illegal masks.
225 /// Note that this will also return true for shuffles that are promoted to a
227 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDValue Mask) const {
228 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
230 case TargetLowering::Legal:
231 case TargetLowering::Custom:
233 case TargetLowering::Promote: {
234 // If this is promoted to a different type, convert the shuffle mask and
235 // ask if it is legal in the promoted type!
236 MVT NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
237 MVT EltVT = NVT.getVectorElementType();
239 // If we changed # elements, change the shuffle mask.
240 unsigned NumEltsGrowth =
241 NVT.getVectorNumElements() / VT.getVectorNumElements();
242 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
243 if (NumEltsGrowth > 1) {
244 // Renumber the elements.
245 SmallVector<SDValue, 8> Ops;
246 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
247 SDValue InOp = Mask.getOperand(i);
248 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
249 if (InOp.getOpcode() == ISD::UNDEF)
250 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
252 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
253 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, EltVT));
257 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
263 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.getNode() : 0;
266 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
267 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
268 ValueTypeActions(TLI.getValueTypeActions()) {
269 assert(MVT::LAST_VALUETYPE <= 32 &&
270 "Too many value types for ValueTypeActions to hold!");
273 void SelectionDAGLegalize::LegalizeDAG() {
274 LastCALLSEQ_END = DAG.getEntryNode();
275 IsLegalizingCall = false;
277 // The legalize process is inherently a bottom-up recursive process (users
278 // legalize their uses before themselves). Given infinite stack space, we
279 // could just start legalizing on the root and traverse the whole graph. In
280 // practice however, this causes us to run out of stack space on large basic
281 // blocks. To avoid this problem, compute an ordering of the nodes where each
282 // node is only legalized after all of its operands are legalized.
283 std::vector<SDNode *> TopOrder;
284 unsigned N = DAG.AssignTopologicalOrder(TopOrder);
285 for (unsigned i = N; i != 0; --i)
286 HandleOp(SDValue(TopOrder[i-1], 0));
289 // Finally, it's possible the root changed. Get the new root.
290 SDValue OldRoot = DAG.getRoot();
291 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
292 DAG.setRoot(LegalizedNodes[OldRoot]);
294 ExpandedNodes.clear();
295 LegalizedNodes.clear();
296 PromotedNodes.clear();
298 ScalarizedNodes.clear();
300 // Remove dead nodes now.
301 DAG.RemoveDeadNodes();
305 /// FindCallEndFromCallStart - Given a chained node that is part of a call
306 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
307 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
308 if (Node->getOpcode() == ISD::CALLSEQ_END)
310 if (Node->use_empty())
311 return 0; // No CallSeqEnd
313 // The chain is usually at the end.
314 SDValue TheChain(Node, Node->getNumValues()-1);
315 if (TheChain.getValueType() != MVT::Other) {
316 // Sometimes it's at the beginning.
317 TheChain = SDValue(Node, 0);
318 if (TheChain.getValueType() != MVT::Other) {
319 // Otherwise, hunt for it.
320 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
321 if (Node->getValueType(i) == MVT::Other) {
322 TheChain = SDValue(Node, i);
326 // Otherwise, we walked into a node without a chain.
327 if (TheChain.getValueType() != MVT::Other)
332 for (SDNode::use_iterator UI = Node->use_begin(),
333 E = Node->use_end(); UI != E; ++UI) {
335 // Make sure to only follow users of our token chain.
337 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
338 if (User->getOperand(i) == TheChain)
339 if (SDNode *Result = FindCallEndFromCallStart(User))
345 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
346 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
347 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
348 assert(Node && "Didn't find callseq_start for a call??");
349 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
351 assert(Node->getOperand(0).getValueType() == MVT::Other &&
352 "Node doesn't have a token chain argument!");
353 return FindCallStartFromCallEnd(Node->getOperand(0).getNode());
356 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
357 /// see if any uses can reach Dest. If no dest operands can get to dest,
358 /// legalize them, legalize ourself, and return false, otherwise, return true.
360 /// Keep track of the nodes we fine that actually do lead to Dest in
361 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
363 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
364 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
365 if (N == Dest) return true; // N certainly leads to Dest :)
367 // If we've already processed this node and it does lead to Dest, there is no
368 // need to reprocess it.
369 if (NodesLeadingTo.count(N)) return true;
371 // If the first result of this node has been already legalized, then it cannot
373 switch (getTypeAction(N->getValueType(0))) {
375 if (LegalizedNodes.count(SDValue(N, 0))) return false;
378 if (PromotedNodes.count(SDValue(N, 0))) return false;
381 if (ExpandedNodes.count(SDValue(N, 0))) return false;
385 // Okay, this node has not already been legalized. Check and legalize all
386 // operands. If none lead to Dest, then we can legalize this node.
387 bool OperandsLeadToDest = false;
388 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
389 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
390 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo);
392 if (OperandsLeadToDest) {
393 NodesLeadingTo.insert(N);
397 // Okay, this node looks safe, legalize it and return false.
398 HandleOp(SDValue(N, 0));
402 /// HandleOp - Legalize, Promote, or Expand the specified operand as
403 /// appropriate for its type.
404 void SelectionDAGLegalize::HandleOp(SDValue Op) {
405 MVT VT = Op.getValueType();
406 switch (getTypeAction(VT)) {
407 default: assert(0 && "Bad type action!");
408 case Legal: (void)LegalizeOp(Op); break;
409 case Promote: (void)PromoteOp(Op); break;
411 if (!VT.isVector()) {
412 // If this is an illegal scalar, expand it into its two component
415 if (Op.getOpcode() == ISD::TargetConstant)
416 break; // Allow illegal target nodes.
418 } else if (VT.getVectorNumElements() == 1) {
419 // If this is an illegal single element vector, convert it to a
421 (void)ScalarizeVectorOp(Op);
423 // Otherwise, this is an illegal multiple element vector.
424 // Split it in half and legalize both parts.
426 SplitVectorOp(Op, X, Y);
432 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
433 /// a load from the constant pool.
434 static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
435 SelectionDAG &DAG, TargetLowering &TLI) {
438 // If a FP immediate is precise when represented as a float and if the
439 // target can do an extending load from float to double, we put it into
440 // the constant pool as a float, even if it's is statically typed as a
441 // double. This shrinks FP constants and canonicalizes them for targets where
442 // an FP extending load is the same cost as a normal load (such as on the x87
443 // fp stack or PPC FP unit).
444 MVT VT = CFP->getValueType(0);
445 ConstantFP *LLVMC = ConstantFP::get(CFP->getValueAPF());
447 if (VT!=MVT::f64 && VT!=MVT::f32)
448 assert(0 && "Invalid type expansion");
449 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt(),
450 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
455 while (SVT != MVT::f32) {
456 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1);
457 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
458 // Only do this if the target has a native EXTLOAD instruction from
460 TLI.isLoadXLegal(ISD::EXTLOAD, SVT) &&
461 TLI.ShouldShrinkFPConstant(OrigVT)) {
462 const Type *SType = SVT.getTypeForMVT();
463 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
469 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
471 return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, DAG.getEntryNode(),
472 CPIdx, PseudoSourceValue::getConstantPool(),
474 return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx,
475 PseudoSourceValue::getConstantPool(), 0);
479 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
482 SDValue ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT,
483 SelectionDAG &DAG, TargetLowering &TLI) {
484 MVT VT = Node->getValueType(0);
485 MVT SrcVT = Node->getOperand(1).getValueType();
486 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
487 "fcopysign expansion only supported for f32 and f64");
488 MVT SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
490 // First get the sign bit of second operand.
491 SDValue Mask1 = (SrcVT == MVT::f64)
492 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
493 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
494 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
495 SDValue SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
496 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
497 // Shift right or sign-extend it if the two operands have different types.
498 int SizeDiff = SrcNVT.getSizeInBits() - NVT.getSizeInBits();
500 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
501 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
502 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
503 } else if (SizeDiff < 0) {
504 SignBit = DAG.getNode(ISD::ZERO_EXTEND, NVT, SignBit);
505 SignBit = DAG.getNode(ISD::SHL, NVT, SignBit,
506 DAG.getConstant(-SizeDiff, TLI.getShiftAmountTy()));
509 // Clear the sign bit of first operand.
510 SDValue Mask2 = (VT == MVT::f64)
511 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
512 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
513 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
514 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
515 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
517 // Or the value with the sign bit.
518 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
522 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
524 SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
525 TargetLowering &TLI) {
526 SDValue Chain = ST->getChain();
527 SDValue Ptr = ST->getBasePtr();
528 SDValue Val = ST->getValue();
529 MVT VT = Val.getValueType();
530 int Alignment = ST->getAlignment();
531 int SVOffset = ST->getSrcValueOffset();
532 if (ST->getMemoryVT().isFloatingPoint() ||
533 ST->getMemoryVT().isVector()) {
534 // Expand to a bitconvert of the value to the integer type of the
535 // same size, then a (misaligned) int store.
537 if (VT.is128BitVector() || VT == MVT::ppcf128 || VT == MVT::f128)
539 else if (VT.is64BitVector() || VT==MVT::f64)
541 else if (VT==MVT::f32)
544 assert(0 && "Unaligned store of unsupported type");
546 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val);
547 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(),
548 SVOffset, ST->isVolatile(), Alignment);
550 assert(ST->getMemoryVT().isInteger() &&
551 !ST->getMemoryVT().isVector() &&
552 "Unaligned store of unknown type.");
553 // Get the half-size VT
555 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1);
556 int NumBits = NewStoredVT.getSizeInBits();
557 int IncrementSize = NumBits / 8;
559 // Divide the stored value in two parts.
560 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
562 SDValue Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
564 // Store the two parts
565 SDValue Store1, Store2;
566 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr,
567 ST->getSrcValue(), SVOffset, NewStoredVT,
568 ST->isVolatile(), Alignment);
569 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
570 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
571 Alignment = MinAlign(Alignment, IncrementSize);
572 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr,
573 ST->getSrcValue(), SVOffset + IncrementSize,
574 NewStoredVT, ST->isVolatile(), Alignment);
576 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2);
579 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
581 SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
582 TargetLowering &TLI) {
583 int SVOffset = LD->getSrcValueOffset();
584 SDValue Chain = LD->getChain();
585 SDValue Ptr = LD->getBasePtr();
586 MVT VT = LD->getValueType(0);
587 MVT LoadedVT = LD->getMemoryVT();
588 if (VT.isFloatingPoint() || VT.isVector()) {
589 // Expand to a (misaligned) integer load of the same size,
590 // then bitconvert to floating point or vector.
592 if (LoadedVT.is128BitVector() ||
593 LoadedVT == MVT::ppcf128 || LoadedVT == MVT::f128)
595 else if (LoadedVT.is64BitVector() || LoadedVT == MVT::f64)
597 else if (LoadedVT == MVT::f32)
600 assert(0 && "Unaligned load of unsupported type");
602 SDValue newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(),
603 SVOffset, LD->isVolatile(),
605 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad);
606 if (VT.isFloatingPoint() && LoadedVT != VT)
607 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result);
609 SDValue Ops[] = { Result, Chain };
610 return DAG.getMergeValues(Ops, 2);
612 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
613 "Unaligned load of unsupported type.");
615 // Compute the new VT that is half the size of the old one. This is an
617 unsigned NumBits = LoadedVT.getSizeInBits();
619 NewLoadedVT = MVT::getIntegerVT(NumBits/2);
622 unsigned Alignment = LD->getAlignment();
623 unsigned IncrementSize = NumBits / 8;
624 ISD::LoadExtType HiExtType = LD->getExtensionType();
626 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
627 if (HiExtType == ISD::NON_EXTLOAD)
628 HiExtType = ISD::ZEXTLOAD;
630 // Load the value in two parts
632 if (TLI.isLittleEndian()) {
633 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
634 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
635 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
636 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
637 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(),
638 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
639 MinAlign(Alignment, IncrementSize));
641 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset,
642 NewLoadedVT,LD->isVolatile(), Alignment);
643 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
644 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
645 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
646 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
647 MinAlign(Alignment, IncrementSize));
650 // aggregate the two parts
651 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
652 SDValue Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
653 Result = DAG.getNode(ISD::OR, VT, Result, Lo);
655 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
658 SDValue Ops[] = { Result, TF };
659 return DAG.getMergeValues(Ops, 2);
662 /// UnrollVectorOp - We know that the given vector has a legal type, however
663 /// the operation it performs is not legal and is an operation that we have
664 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
665 /// operating on each element individually.
666 SDValue SelectionDAGLegalize::UnrollVectorOp(SDValue Op) {
667 MVT VT = Op.getValueType();
668 assert(isTypeLegal(VT) &&
669 "Caller should expand or promote operands that are not legal!");
670 assert(Op.getNode()->getNumValues() == 1 &&
671 "Can't unroll a vector with multiple results!");
672 unsigned NE = VT.getVectorNumElements();
673 MVT EltVT = VT.getVectorElementType();
675 SmallVector<SDValue, 8> Scalars;
676 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
677 for (unsigned i = 0; i != NE; ++i) {
678 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
679 SDValue Operand = Op.getOperand(j);
680 MVT OperandVT = Operand.getValueType();
681 if (OperandVT.isVector()) {
682 // A vector operand; extract a single element.
683 MVT OperandEltVT = OperandVT.getVectorElementType();
684 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
687 DAG.getConstant(i, MVT::i32));
689 // A scalar operand; just use it as is.
690 Operands[j] = Operand;
693 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT,
694 &Operands[0], Operands.size()));
697 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size());
700 /// GetFPLibCall - Return the right libcall for the given floating point type.
701 static RTLIB::Libcall GetFPLibCall(MVT VT,
702 RTLIB::Libcall Call_F32,
703 RTLIB::Libcall Call_F64,
704 RTLIB::Libcall Call_F80,
705 RTLIB::Libcall Call_PPCF128) {
707 VT == MVT::f32 ? Call_F32 :
708 VT == MVT::f64 ? Call_F64 :
709 VT == MVT::f80 ? Call_F80 :
710 VT == MVT::ppcf128 ? Call_PPCF128 :
711 RTLIB::UNKNOWN_LIBCALL;
714 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
715 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
716 /// is necessary to spill the vector being inserted into to memory, perform
717 /// the insert there, and then read the result back.
718 SDValue SelectionDAGLegalize::
719 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx) {
724 // If the target doesn't support this, we have to spill the input vector
725 // to a temporary stack slot, update the element, then reload it. This is
726 // badness. We could also load the value into a vector register (either
727 // with a "move to register" or "extload into register" instruction, then
728 // permute it into place, if the idx is a constant and if the idx is
729 // supported by the target.
730 MVT VT = Tmp1.getValueType();
731 MVT EltVT = VT.getVectorElementType();
732 MVT IdxVT = Tmp3.getValueType();
733 MVT PtrVT = TLI.getPointerTy();
734 SDValue StackPtr = DAG.CreateStackTemporary(VT);
736 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
739 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr,
740 PseudoSourceValue::getFixedStack(SPFI), 0);
742 // Truncate or zero extend offset to target pointer type.
743 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
744 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
745 // Add the offset to the index.
746 unsigned EltSize = EltVT.getSizeInBits()/8;
747 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
748 SDValue StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
749 // Store the scalar value.
750 Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2,
751 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT);
752 // Load the updated vector.
753 return DAG.getLoad(VT, Ch, StackPtr,
754 PseudoSourceValue::getFixedStack(SPFI), 0);
757 /// LegalizeOp - We know that the specified value has a legal type, and
758 /// that its operands are legal. Now ensure that the operation itself
759 /// is legal, recursively ensuring that the operands' operations remain
761 SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
762 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
765 assert(isTypeLegal(Op.getValueType()) &&
766 "Caller should expand or promote operands that are not legal!");
767 SDNode *Node = Op.getNode();
769 // If this operation defines any values that cannot be represented in a
770 // register on this target, make sure to expand or promote them.
771 if (Node->getNumValues() > 1) {
772 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
773 if (getTypeAction(Node->getValueType(i)) != Legal) {
774 HandleOp(Op.getValue(i));
775 assert(LegalizedNodes.count(Op) &&
776 "Handling didn't add legal operands!");
777 return LegalizedNodes[Op];
781 // Note that LegalizeOp may be reentered even from single-use nodes, which
782 // means that we always must cache transformed nodes.
783 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
784 if (I != LegalizedNodes.end()) return I->second;
786 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
788 bool isCustom = false;
790 switch (Node->getOpcode()) {
791 case ISD::FrameIndex:
792 case ISD::EntryToken:
794 case ISD::BasicBlock:
795 case ISD::TargetFrameIndex:
796 case ISD::TargetJumpTable:
797 case ISD::TargetConstant:
798 case ISD::TargetConstantFP:
799 case ISD::TargetConstantPool:
800 case ISD::TargetGlobalAddress:
801 case ISD::TargetGlobalTLSAddress:
802 case ISD::TargetExternalSymbol:
805 case ISD::MEMOPERAND:
808 // Primitives must all be legal.
809 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
810 "This must be legal!");
813 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
814 // If this is a target node, legalize it by legalizing the operands then
815 // passing it through.
816 SmallVector<SDValue, 8> Ops;
817 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
818 Ops.push_back(LegalizeOp(Node->getOperand(i)));
820 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
822 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
823 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
824 return Result.getValue(Op.getResNo());
826 // Otherwise this is an unhandled builtin node. splat.
828 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
830 assert(0 && "Do not know how to legalize this operator!");
832 case ISD::GLOBAL_OFFSET_TABLE:
833 case ISD::GlobalAddress:
834 case ISD::GlobalTLSAddress:
835 case ISD::ExternalSymbol:
836 case ISD::ConstantPool:
837 case ISD::JumpTable: // Nothing to do.
838 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
839 default: assert(0 && "This action is not supported yet!");
840 case TargetLowering::Custom:
841 Tmp1 = TLI.LowerOperation(Op, DAG);
842 if (Tmp1.getNode()) Result = Tmp1;
843 // FALLTHROUGH if the target doesn't want to lower this op after all.
844 case TargetLowering::Legal:
849 case ISD::RETURNADDR:
850 // The only option for these nodes is to custom lower them. If the target
851 // does not custom lower them, then return zero.
852 Tmp1 = TLI.LowerOperation(Op, DAG);
856 Result = DAG.getConstant(0, TLI.getPointerTy());
858 case ISD::FRAME_TO_ARGS_OFFSET: {
859 MVT VT = Node->getValueType(0);
860 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
861 default: assert(0 && "This action is not supported yet!");
862 case TargetLowering::Custom:
863 Result = TLI.LowerOperation(Op, DAG);
864 if (Result.getNode()) break;
866 case TargetLowering::Legal:
867 Result = DAG.getConstant(0, VT);
872 case ISD::EXCEPTIONADDR: {
873 Tmp1 = LegalizeOp(Node->getOperand(0));
874 MVT VT = Node->getValueType(0);
875 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
876 default: assert(0 && "This action is not supported yet!");
877 case TargetLowering::Expand: {
878 unsigned Reg = TLI.getExceptionAddressRegister();
879 Result = DAG.getCopyFromReg(Tmp1, Reg, VT);
882 case TargetLowering::Custom:
883 Result = TLI.LowerOperation(Op, DAG);
884 if (Result.getNode()) break;
886 case TargetLowering::Legal: {
887 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp1 };
888 Result = DAG.getMergeValues(Ops, 2);
893 if (Result.getNode()->getNumValues() == 1) break;
895 assert(Result.getNode()->getNumValues() == 2 &&
896 "Cannot return more than two values!");
898 // Since we produced two values, make sure to remember that we
899 // legalized both of them.
900 Tmp1 = LegalizeOp(Result);
901 Tmp2 = LegalizeOp(Result.getValue(1));
902 AddLegalizedOperand(Op.getValue(0), Tmp1);
903 AddLegalizedOperand(Op.getValue(1), Tmp2);
904 return Op.getResNo() ? Tmp2 : Tmp1;
905 case ISD::EHSELECTION: {
906 Tmp1 = LegalizeOp(Node->getOperand(0));
907 Tmp2 = LegalizeOp(Node->getOperand(1));
908 MVT VT = Node->getValueType(0);
909 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
910 default: assert(0 && "This action is not supported yet!");
911 case TargetLowering::Expand: {
912 unsigned Reg = TLI.getExceptionSelectorRegister();
913 Result = DAG.getCopyFromReg(Tmp2, Reg, VT);
916 case TargetLowering::Custom:
917 Result = TLI.LowerOperation(Op, DAG);
918 if (Result.getNode()) break;
920 case TargetLowering::Legal: {
921 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp2 };
922 Result = DAG.getMergeValues(Ops, 2);
927 if (Result.getNode()->getNumValues() == 1) break;
929 assert(Result.getNode()->getNumValues() == 2 &&
930 "Cannot return more than two values!");
932 // Since we produced two values, make sure to remember that we
933 // legalized both of them.
934 Tmp1 = LegalizeOp(Result);
935 Tmp2 = LegalizeOp(Result.getValue(1));
936 AddLegalizedOperand(Op.getValue(0), Tmp1);
937 AddLegalizedOperand(Op.getValue(1), Tmp2);
938 return Op.getResNo() ? Tmp2 : Tmp1;
939 case ISD::EH_RETURN: {
940 MVT VT = Node->getValueType(0);
941 // The only "good" option for this node is to custom lower it.
942 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
943 default: assert(0 && "This action is not supported at all!");
944 case TargetLowering::Custom:
945 Result = TLI.LowerOperation(Op, DAG);
946 if (Result.getNode()) break;
948 case TargetLowering::Legal:
949 // Target does not know, how to lower this, lower to noop
950 Result = LegalizeOp(Node->getOperand(0));
955 case ISD::AssertSext:
956 case ISD::AssertZext:
957 Tmp1 = LegalizeOp(Node->getOperand(0));
958 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
960 case ISD::MERGE_VALUES:
961 // Legalize eliminates MERGE_VALUES nodes.
962 Result = Node->getOperand(Op.getResNo());
964 case ISD::CopyFromReg:
965 Tmp1 = LegalizeOp(Node->getOperand(0));
966 Result = Op.getValue(0);
967 if (Node->getNumValues() == 2) {
968 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
970 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
971 if (Node->getNumOperands() == 3) {
972 Tmp2 = LegalizeOp(Node->getOperand(2));
973 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
975 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
977 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
979 // Since CopyFromReg produces two values, make sure to remember that we
980 // legalized both of them.
981 AddLegalizedOperand(Op.getValue(0), Result);
982 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
983 return Result.getValue(Op.getResNo());
985 MVT VT = Op.getValueType();
986 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
987 default: assert(0 && "This action is not supported yet!");
988 case TargetLowering::Expand:
990 Result = DAG.getConstant(0, VT);
991 else if (VT.isFloatingPoint())
992 Result = DAG.getConstantFP(APFloat(APInt(VT.getSizeInBits(), 0)),
995 assert(0 && "Unknown value type!");
997 case TargetLowering::Legal:
1003 case ISD::INTRINSIC_W_CHAIN:
1004 case ISD::INTRINSIC_WO_CHAIN:
1005 case ISD::INTRINSIC_VOID: {
1006 SmallVector<SDValue, 8> Ops;
1007 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1008 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1009 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1011 // Allow the target to custom lower its intrinsics if it wants to.
1012 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
1013 TargetLowering::Custom) {
1014 Tmp3 = TLI.LowerOperation(Result, DAG);
1015 if (Tmp3.getNode()) Result = Tmp3;
1018 if (Result.getNode()->getNumValues() == 1) break;
1020 // Must have return value and chain result.
1021 assert(Result.getNode()->getNumValues() == 2 &&
1022 "Cannot return more than two values!");
1024 // Since loads produce two values, make sure to remember that we
1025 // legalized both of them.
1026 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1027 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1028 return Result.getValue(Op.getResNo());
1031 case ISD::DBG_STOPPOINT:
1032 assert(Node->getNumOperands() == 1 && "Invalid DBG_STOPPOINT node!");
1033 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
1035 switch (TLI.getOperationAction(ISD::DBG_STOPPOINT, MVT::Other)) {
1036 case TargetLowering::Promote:
1037 default: assert(0 && "This action is not supported yet!");
1038 case TargetLowering::Expand: {
1039 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
1040 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
1041 bool useLABEL = TLI.isOperationLegal(ISD::DBG_LABEL, MVT::Other);
1043 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node);
1044 if (MMI && (useDEBUG_LOC || useLABEL)) {
1045 const CompileUnitDesc *CompileUnit = DSP->getCompileUnit();
1046 unsigned SrcFile = MMI->RecordSource(CompileUnit);
1048 unsigned Line = DSP->getLine();
1049 unsigned Col = DSP->getColumn();
1052 SDValue Ops[] = { Tmp1, DAG.getConstant(Line, MVT::i32),
1053 DAG.getConstant(Col, MVT::i32),
1054 DAG.getConstant(SrcFile, MVT::i32) };
1055 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops, 4);
1057 unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile);
1058 Result = DAG.getLabel(ISD::DBG_LABEL, Tmp1, ID);
1061 Result = Tmp1; // chain
1065 case TargetLowering::Legal: {
1066 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1067 if (Action == Legal && Tmp1 == Node->getOperand(0))
1070 SmallVector<SDValue, 8> Ops;
1071 Ops.push_back(Tmp1);
1072 if (Action == Legal) {
1073 Ops.push_back(Node->getOperand(1)); // line # must be legal.
1074 Ops.push_back(Node->getOperand(2)); // col # must be legal.
1076 // Otherwise promote them.
1077 Ops.push_back(PromoteOp(Node->getOperand(1)));
1078 Ops.push_back(PromoteOp(Node->getOperand(2)));
1080 Ops.push_back(Node->getOperand(3)); // filename must be legal.
1081 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
1082 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1089 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!");
1090 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) {
1091 default: assert(0 && "This action is not supported yet!");
1092 case TargetLowering::Legal:
1093 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1094 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1095 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable.
1096 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1098 case TargetLowering::Expand:
1099 Result = LegalizeOp(Node->getOperand(0));
1104 case ISD::DEBUG_LOC:
1105 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
1106 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
1107 default: assert(0 && "This action is not supported yet!");
1108 case TargetLowering::Legal: {
1109 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1110 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1111 if (Action == Legal && Tmp1 == Node->getOperand(0))
1113 if (Action == Legal) {
1114 Tmp2 = Node->getOperand(1);
1115 Tmp3 = Node->getOperand(2);
1116 Tmp4 = Node->getOperand(3);
1118 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1119 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1120 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1122 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1128 case ISD::DBG_LABEL:
1130 assert(Node->getNumOperands() == 1 && "Invalid LABEL node!");
1131 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
1132 default: assert(0 && "This action is not supported yet!");
1133 case TargetLowering::Legal:
1134 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1135 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1137 case TargetLowering::Expand:
1138 Result = LegalizeOp(Node->getOperand(0));
1144 assert(Node->getNumOperands() == 4 && "Invalid Prefetch node!");
1145 switch (TLI.getOperationAction(ISD::PREFETCH, MVT::Other)) {
1146 default: assert(0 && "This action is not supported yet!");
1147 case TargetLowering::Legal:
1148 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1149 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1150 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the rw specifier.
1151 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize locality specifier.
1152 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1154 case TargetLowering::Expand:
1156 Result = LegalizeOp(Node->getOperand(0));
1161 case ISD::MEMBARRIER: {
1162 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!");
1163 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) {
1164 default: assert(0 && "This action is not supported yet!");
1165 case TargetLowering::Legal: {
1167 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1168 for (int x = 1; x < 6; ++x) {
1169 Ops[x] = Node->getOperand(x);
1170 if (!isTypeLegal(Ops[x].getValueType()))
1171 Ops[x] = PromoteOp(Ops[x]);
1173 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6);
1176 case TargetLowering::Expand:
1177 //There is no libgcc call for this op
1178 Result = Node->getOperand(0); // Noop
1184 case ISD::ATOMIC_CMP_SWAP_8:
1185 case ISD::ATOMIC_CMP_SWAP_16:
1186 case ISD::ATOMIC_CMP_SWAP_32:
1187 case ISD::ATOMIC_CMP_SWAP_64: {
1188 unsigned int num_operands = 4;
1189 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1191 for (unsigned int x = 0; x < num_operands; ++x)
1192 Ops[x] = LegalizeOp(Node->getOperand(x));
1193 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1195 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1196 default: assert(0 && "This action is not supported yet!");
1197 case TargetLowering::Custom:
1198 Result = TLI.LowerOperation(Result, DAG);
1200 case TargetLowering::Legal:
1203 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1204 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1205 return Result.getValue(Op.getResNo());
1207 case ISD::ATOMIC_LOAD_ADD_8:
1208 case ISD::ATOMIC_LOAD_SUB_8:
1209 case ISD::ATOMIC_LOAD_AND_8:
1210 case ISD::ATOMIC_LOAD_OR_8:
1211 case ISD::ATOMIC_LOAD_XOR_8:
1212 case ISD::ATOMIC_LOAD_NAND_8:
1213 case ISD::ATOMIC_LOAD_MIN_8:
1214 case ISD::ATOMIC_LOAD_MAX_8:
1215 case ISD::ATOMIC_LOAD_UMIN_8:
1216 case ISD::ATOMIC_LOAD_UMAX_8:
1217 case ISD::ATOMIC_SWAP_8:
1218 case ISD::ATOMIC_LOAD_ADD_16:
1219 case ISD::ATOMIC_LOAD_SUB_16:
1220 case ISD::ATOMIC_LOAD_AND_16:
1221 case ISD::ATOMIC_LOAD_OR_16:
1222 case ISD::ATOMIC_LOAD_XOR_16:
1223 case ISD::ATOMIC_LOAD_NAND_16:
1224 case ISD::ATOMIC_LOAD_MIN_16:
1225 case ISD::ATOMIC_LOAD_MAX_16:
1226 case ISD::ATOMIC_LOAD_UMIN_16:
1227 case ISD::ATOMIC_LOAD_UMAX_16:
1228 case ISD::ATOMIC_SWAP_16:
1229 case ISD::ATOMIC_LOAD_ADD_32:
1230 case ISD::ATOMIC_LOAD_SUB_32:
1231 case ISD::ATOMIC_LOAD_AND_32:
1232 case ISD::ATOMIC_LOAD_OR_32:
1233 case ISD::ATOMIC_LOAD_XOR_32:
1234 case ISD::ATOMIC_LOAD_NAND_32:
1235 case ISD::ATOMIC_LOAD_MIN_32:
1236 case ISD::ATOMIC_LOAD_MAX_32:
1237 case ISD::ATOMIC_LOAD_UMIN_32:
1238 case ISD::ATOMIC_LOAD_UMAX_32:
1239 case ISD::ATOMIC_SWAP_32:
1240 case ISD::ATOMIC_LOAD_ADD_64:
1241 case ISD::ATOMIC_LOAD_SUB_64:
1242 case ISD::ATOMIC_LOAD_AND_64:
1243 case ISD::ATOMIC_LOAD_OR_64:
1244 case ISD::ATOMIC_LOAD_XOR_64:
1245 case ISD::ATOMIC_LOAD_NAND_64:
1246 case ISD::ATOMIC_LOAD_MIN_64:
1247 case ISD::ATOMIC_LOAD_MAX_64:
1248 case ISD::ATOMIC_LOAD_UMIN_64:
1249 case ISD::ATOMIC_LOAD_UMAX_64:
1250 case ISD::ATOMIC_SWAP_64: {
1251 unsigned int num_operands = 3;
1252 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1254 for (unsigned int x = 0; x < num_operands; ++x)
1255 Ops[x] = LegalizeOp(Node->getOperand(x));
1256 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1258 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1259 default: assert(0 && "This action is not supported yet!");
1260 case TargetLowering::Custom:
1261 Result = TLI.LowerOperation(Result, DAG);
1263 case TargetLowering::Expand:
1264 Result = SDValue(TLI.ReplaceNodeResults(Op.getNode(), DAG),0);
1266 case TargetLowering::Legal:
1269 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1270 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1271 return Result.getValue(Op.getResNo());
1273 case ISD::Constant: {
1274 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1276 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1278 // We know we don't need to expand constants here, constants only have one
1279 // value and we check that it is fine above.
1281 if (opAction == TargetLowering::Custom) {
1282 Tmp1 = TLI.LowerOperation(Result, DAG);
1288 case ISD::ConstantFP: {
1289 // Spill FP immediates to the constant pool if the target cannot directly
1290 // codegen them. Targets often have some immediate values that can be
1291 // efficiently generated into an FP register without a load. We explicitly
1292 // leave these constants as ConstantFP nodes for the target to deal with.
1293 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1295 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1296 default: assert(0 && "This action is not supported yet!");
1297 case TargetLowering::Legal:
1299 case TargetLowering::Custom:
1300 Tmp3 = TLI.LowerOperation(Result, DAG);
1301 if (Tmp3.getNode()) {
1306 case TargetLowering::Expand: {
1307 // Check to see if this FP immediate is already legal.
1308 bool isLegal = false;
1309 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1310 E = TLI.legal_fpimm_end(); I != E; ++I) {
1311 if (CFP->isExactlyValue(*I)) {
1316 // If this is a legal constant, turn it into a TargetConstantFP node.
1319 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1324 case ISD::TokenFactor:
1325 if (Node->getNumOperands() == 2) {
1326 Tmp1 = LegalizeOp(Node->getOperand(0));
1327 Tmp2 = LegalizeOp(Node->getOperand(1));
1328 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1329 } else if (Node->getNumOperands() == 3) {
1330 Tmp1 = LegalizeOp(Node->getOperand(0));
1331 Tmp2 = LegalizeOp(Node->getOperand(1));
1332 Tmp3 = LegalizeOp(Node->getOperand(2));
1333 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1335 SmallVector<SDValue, 8> Ops;
1336 // Legalize the operands.
1337 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1338 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1339 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1343 case ISD::FORMAL_ARGUMENTS:
1345 // The only option for this is to custom lower it.
1346 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1347 assert(Tmp3.getNode() && "Target didn't custom lower this node!");
1348 // A call within a calling sequence must be legalized to something
1349 // other than the normal CALLSEQ_END. Violating this gets Legalize
1350 // into an infinite loop.
1351 assert ((!IsLegalizingCall ||
1352 Node->getOpcode() != ISD::CALL ||
1353 Tmp3.getNode()->getOpcode() != ISD::CALLSEQ_END) &&
1354 "Nested CALLSEQ_START..CALLSEQ_END not supported.");
1356 // The number of incoming and outgoing values should match; unless the final
1357 // outgoing value is a flag.
1358 assert((Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() ||
1359 (Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() + 1 &&
1360 Tmp3.getNode()->getValueType(Tmp3.getNode()->getNumValues() - 1) ==
1362 "Lowering call/formal_arguments produced unexpected # results!");
1364 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1365 // remember that we legalized all of them, so it doesn't get relegalized.
1366 for (unsigned i = 0, e = Tmp3.getNode()->getNumValues(); i != e; ++i) {
1367 if (Tmp3.getNode()->getValueType(i) == MVT::Flag)
1369 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1370 if (Op.getResNo() == i)
1372 AddLegalizedOperand(SDValue(Node, i), Tmp1);
1375 case ISD::EXTRACT_SUBREG: {
1376 Tmp1 = LegalizeOp(Node->getOperand(0));
1377 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1378 assert(idx && "Operand must be a constant");
1379 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1380 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1383 case ISD::INSERT_SUBREG: {
1384 Tmp1 = LegalizeOp(Node->getOperand(0));
1385 Tmp2 = LegalizeOp(Node->getOperand(1));
1386 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1387 assert(idx && "Operand must be a constant");
1388 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1389 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1392 case ISD::BUILD_VECTOR:
1393 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1394 default: assert(0 && "This action is not supported yet!");
1395 case TargetLowering::Custom:
1396 Tmp3 = TLI.LowerOperation(Result, DAG);
1397 if (Tmp3.getNode()) {
1402 case TargetLowering::Expand:
1403 Result = ExpandBUILD_VECTOR(Result.getNode());
1407 case ISD::INSERT_VECTOR_ELT:
1408 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1409 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1411 // The type of the value to insert may not be legal, even though the vector
1412 // type is legal. Legalize/Promote accordingly. We do not handle Expand
1414 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1415 default: assert(0 && "Cannot expand insert element operand");
1416 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
1417 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
1419 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1421 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1422 Node->getValueType(0))) {
1423 default: assert(0 && "This action is not supported yet!");
1424 case TargetLowering::Legal:
1426 case TargetLowering::Custom:
1427 Tmp4 = TLI.LowerOperation(Result, DAG);
1428 if (Tmp4.getNode()) {
1433 case TargetLowering::Expand: {
1434 // If the insert index is a constant, codegen this as a scalar_to_vector,
1435 // then a shuffle that inserts it into the right position in the vector.
1436 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1437 // SCALAR_TO_VECTOR requires that the type of the value being inserted
1438 // match the element type of the vector being created.
1439 if (Tmp2.getValueType() ==
1440 Op.getValueType().getVectorElementType()) {
1441 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
1442 Tmp1.getValueType(), Tmp2);
1444 unsigned NumElts = Tmp1.getValueType().getVectorNumElements();
1446 MVT::getIntVectorWithNumElements(NumElts);
1447 MVT ShufMaskEltVT = ShufMaskVT.getVectorElementType();
1449 // We generate a shuffle of InVec and ScVec, so the shuffle mask
1450 // should be 0,1,2,3,4,5... with the appropriate element replaced with
1451 // elt 0 of the RHS.
1452 SmallVector<SDValue, 8> ShufOps;
1453 for (unsigned i = 0; i != NumElts; ++i) {
1454 if (i != InsertPos->getValue())
1455 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1457 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1459 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1460 &ShufOps[0], ShufOps.size());
1462 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1463 Tmp1, ScVec, ShufMask);
1464 Result = LegalizeOp(Result);
1468 Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3);
1473 case ISD::SCALAR_TO_VECTOR:
1474 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1475 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1479 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1480 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1481 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1482 Node->getValueType(0))) {
1483 default: assert(0 && "This action is not supported yet!");
1484 case TargetLowering::Legal:
1486 case TargetLowering::Custom:
1487 Tmp3 = TLI.LowerOperation(Result, DAG);
1488 if (Tmp3.getNode()) {
1493 case TargetLowering::Expand:
1494 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1498 case ISD::VECTOR_SHUFFLE:
1499 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1500 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1501 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1503 // Allow targets to custom lower the SHUFFLEs they support.
1504 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1505 default: assert(0 && "Unknown operation action!");
1506 case TargetLowering::Legal:
1507 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1508 "vector shuffle should not be created if not legal!");
1510 case TargetLowering::Custom:
1511 Tmp3 = TLI.LowerOperation(Result, DAG);
1512 if (Tmp3.getNode()) {
1517 case TargetLowering::Expand: {
1518 MVT VT = Node->getValueType(0);
1519 MVT EltVT = VT.getVectorElementType();
1520 MVT PtrVT = TLI.getPointerTy();
1521 SDValue Mask = Node->getOperand(2);
1522 unsigned NumElems = Mask.getNumOperands();
1523 SmallVector<SDValue,8> Ops;
1524 for (unsigned i = 0; i != NumElems; ++i) {
1525 SDValue Arg = Mask.getOperand(i);
1526 if (Arg.getOpcode() == ISD::UNDEF) {
1527 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1529 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1530 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
1532 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1533 DAG.getConstant(Idx, PtrVT)));
1535 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1536 DAG.getConstant(Idx - NumElems, PtrVT)));
1539 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1542 case TargetLowering::Promote: {
1543 // Change base type to a different vector type.
1544 MVT OVT = Node->getValueType(0);
1545 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1547 // Cast the two input vectors.
1548 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1549 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1551 // Convert the shuffle mask to the right # elements.
1552 Tmp3 = SDValue(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1553 assert(Tmp3.getNode() && "Shuffle not legal?");
1554 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1555 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1561 case ISD::EXTRACT_VECTOR_ELT:
1562 Tmp1 = Node->getOperand(0);
1563 Tmp2 = LegalizeOp(Node->getOperand(1));
1564 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1565 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1568 case ISD::EXTRACT_SUBVECTOR:
1569 Tmp1 = Node->getOperand(0);
1570 Tmp2 = LegalizeOp(Node->getOperand(1));
1571 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1572 Result = ExpandEXTRACT_SUBVECTOR(Result);
1575 case ISD::CALLSEQ_START: {
1576 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1578 // Recursively Legalize all of the inputs of the call end that do not lead
1579 // to this call start. This ensures that any libcalls that need be inserted
1580 // are inserted *before* the CALLSEQ_START.
1581 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1582 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1583 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
1587 // Now that we legalized all of the inputs (which may have inserted
1588 // libcalls) create the new CALLSEQ_START node.
1589 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1591 // Merge in the last call, to ensure that this call start after the last
1593 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1594 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1595 Tmp1 = LegalizeOp(Tmp1);
1598 // Do not try to legalize the target-specific arguments (#1+).
1599 if (Tmp1 != Node->getOperand(0)) {
1600 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1602 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1605 // Remember that the CALLSEQ_START is legalized.
1606 AddLegalizedOperand(Op.getValue(0), Result);
1607 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1608 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1610 // Now that the callseq_start and all of the non-call nodes above this call
1611 // sequence have been legalized, legalize the call itself. During this
1612 // process, no libcalls can/will be inserted, guaranteeing that no calls
1614 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1615 // Note that we are selecting this call!
1616 LastCALLSEQ_END = SDValue(CallEnd, 0);
1617 IsLegalizingCall = true;
1619 // Legalize the call, starting from the CALLSEQ_END.
1620 LegalizeOp(LastCALLSEQ_END);
1621 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1624 case ISD::CALLSEQ_END:
1625 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1626 // will cause this node to be legalized as well as handling libcalls right.
1627 if (LastCALLSEQ_END.getNode() != Node) {
1628 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
1629 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1630 assert(I != LegalizedNodes.end() &&
1631 "Legalizing the call start should have legalized this node!");
1635 // Otherwise, the call start has been legalized and everything is going
1636 // according to plan. Just legalize ourselves normally here.
1637 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1638 // Do not try to legalize the target-specific arguments (#1+), except for
1639 // an optional flag input.
1640 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1641 if (Tmp1 != Node->getOperand(0)) {
1642 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1644 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1647 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1648 if (Tmp1 != Node->getOperand(0) ||
1649 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1650 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1653 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1656 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1657 // This finishes up call legalization.
1658 IsLegalizingCall = false;
1660 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1661 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1662 if (Node->getNumValues() == 2)
1663 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1664 return Result.getValue(Op.getResNo());
1665 case ISD::DYNAMIC_STACKALLOC: {
1666 MVT VT = Node->getValueType(0);
1667 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1668 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1669 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1670 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1672 Tmp1 = Result.getValue(0);
1673 Tmp2 = Result.getValue(1);
1674 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1675 default: assert(0 && "This action is not supported yet!");
1676 case TargetLowering::Expand: {
1677 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1678 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1679 " not tell us which reg is the stack pointer!");
1680 SDValue Chain = Tmp1.getOperand(0);
1682 // Chain the dynamic stack allocation so that it doesn't modify the stack
1683 // pointer when other instructions are using the stack.
1684 Chain = DAG.getCALLSEQ_START(Chain,
1685 DAG.getConstant(0, TLI.getPointerTy()));
1687 SDValue Size = Tmp2.getOperand(1);
1688 SDValue SP = DAG.getCopyFromReg(Chain, SPReg, VT);
1689 Chain = SP.getValue(1);
1690 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue();
1691 unsigned StackAlign =
1692 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1693 if (Align > StackAlign)
1694 SP = DAG.getNode(ISD::AND, VT, SP,
1695 DAG.getConstant(-(uint64_t)Align, VT));
1696 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value
1697 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
1700 DAG.getCALLSEQ_END(Chain,
1701 DAG.getConstant(0, TLI.getPointerTy()),
1702 DAG.getConstant(0, TLI.getPointerTy()),
1705 Tmp1 = LegalizeOp(Tmp1);
1706 Tmp2 = LegalizeOp(Tmp2);
1709 case TargetLowering::Custom:
1710 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1711 if (Tmp3.getNode()) {
1712 Tmp1 = LegalizeOp(Tmp3);
1713 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1716 case TargetLowering::Legal:
1719 // Since this op produce two values, make sure to remember that we
1720 // legalized both of them.
1721 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
1722 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
1723 return Op.getResNo() ? Tmp2 : Tmp1;
1725 case ISD::INLINEASM: {
1726 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1727 bool Changed = false;
1728 // Legalize all of the operands of the inline asm, in case they are nodes
1729 // that need to be expanded or something. Note we skip the asm string and
1730 // all of the TargetConstant flags.
1731 SDValue Op = LegalizeOp(Ops[0]);
1732 Changed = Op != Ops[0];
1735 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1736 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1737 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1738 for (++i; NumVals; ++i, --NumVals) {
1739 SDValue Op = LegalizeOp(Ops[i]);
1748 Op = LegalizeOp(Ops.back());
1749 Changed |= Op != Ops.back();
1754 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1756 // INLINE asm returns a chain and flag, make sure to add both to the map.
1757 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1758 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1759 return Result.getValue(Op.getResNo());
1762 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1763 // Ensure that libcalls are emitted before a branch.
1764 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1765 Tmp1 = LegalizeOp(Tmp1);
1766 LastCALLSEQ_END = DAG.getEntryNode();
1768 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1771 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1772 // Ensure that libcalls are emitted before a branch.
1773 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1774 Tmp1 = LegalizeOp(Tmp1);
1775 LastCALLSEQ_END = DAG.getEntryNode();
1777 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1778 default: assert(0 && "Indirect target must be legal type (pointer)!");
1780 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1783 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1786 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1787 // Ensure that libcalls are emitted before a branch.
1788 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1789 Tmp1 = LegalizeOp(Tmp1);
1790 LastCALLSEQ_END = DAG.getEntryNode();
1792 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1793 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1795 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1796 default: assert(0 && "This action is not supported yet!");
1797 case TargetLowering::Legal: break;
1798 case TargetLowering::Custom:
1799 Tmp1 = TLI.LowerOperation(Result, DAG);
1800 if (Tmp1.getNode()) Result = Tmp1;
1802 case TargetLowering::Expand: {
1803 SDValue Chain = Result.getOperand(0);
1804 SDValue Table = Result.getOperand(1);
1805 SDValue Index = Result.getOperand(2);
1807 MVT PTy = TLI.getPointerTy();
1808 MachineFunction &MF = DAG.getMachineFunction();
1809 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
1810 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1811 SDValue Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1814 switch (EntrySize) {
1815 default: assert(0 && "Size of jump table not supported yet."); break;
1816 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr,
1817 PseudoSourceValue::getJumpTable(), 0); break;
1818 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr,
1819 PseudoSourceValue::getJumpTable(), 0); break;
1823 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1824 // For PIC, the sequence is:
1825 // BRIND(load(Jumptable + index) + RelocBase)
1826 // RelocBase can be JumpTable, GOT or some sort of global base.
1827 if (PTy != MVT::i32)
1828 Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr);
1829 Addr = DAG.getNode(ISD::ADD, PTy, Addr,
1830 TLI.getPICJumpTableRelocBase(Table, DAG));
1832 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1837 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1838 // Ensure that libcalls are emitted before a return.
1839 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1840 Tmp1 = LegalizeOp(Tmp1);
1841 LastCALLSEQ_END = DAG.getEntryNode();
1843 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1844 case Expand: assert(0 && "It's impossible to expand bools");
1846 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1849 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1851 // The top bits of the promoted condition are not necessarily zero, ensure
1852 // that the value is properly zero extended.
1853 unsigned BitWidth = Tmp2.getValueSizeInBits();
1854 if (!DAG.MaskedValueIsZero(Tmp2,
1855 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
1856 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1861 // Basic block destination (Op#2) is always legal.
1862 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1864 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1865 default: assert(0 && "This action is not supported yet!");
1866 case TargetLowering::Legal: break;
1867 case TargetLowering::Custom:
1868 Tmp1 = TLI.LowerOperation(Result, DAG);
1869 if (Tmp1.getNode()) Result = Tmp1;
1871 case TargetLowering::Expand:
1872 // Expand brcond's setcc into its constituent parts and create a BR_CC
1874 if (Tmp2.getOpcode() == ISD::SETCC) {
1875 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1876 Tmp2.getOperand(0), Tmp2.getOperand(1),
1877 Node->getOperand(2));
1879 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1880 DAG.getCondCode(ISD::SETNE), Tmp2,
1881 DAG.getConstant(0, Tmp2.getValueType()),
1882 Node->getOperand(2));
1888 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1889 // Ensure that libcalls are emitted before a branch.
1890 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1891 Tmp1 = LegalizeOp(Tmp1);
1892 Tmp2 = Node->getOperand(2); // LHS
1893 Tmp3 = Node->getOperand(3); // RHS
1894 Tmp4 = Node->getOperand(1); // CC
1896 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1897 LastCALLSEQ_END = DAG.getEntryNode();
1899 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1900 // the LHS is a legal SETCC itself. In this case, we need to compare
1901 // the result against zero to select between true and false values.
1902 if (Tmp3.getNode() == 0) {
1903 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1904 Tmp4 = DAG.getCondCode(ISD::SETNE);
1907 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1908 Node->getOperand(4));
1910 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1911 default: assert(0 && "Unexpected action for BR_CC!");
1912 case TargetLowering::Legal: break;
1913 case TargetLowering::Custom:
1914 Tmp4 = TLI.LowerOperation(Result, DAG);
1915 if (Tmp4.getNode()) Result = Tmp4;
1920 LoadSDNode *LD = cast<LoadSDNode>(Node);
1921 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1922 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1924 ISD::LoadExtType ExtType = LD->getExtensionType();
1925 if (ExtType == ISD::NON_EXTLOAD) {
1926 MVT VT = Node->getValueType(0);
1927 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1928 Tmp3 = Result.getValue(0);
1929 Tmp4 = Result.getValue(1);
1931 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1932 default: assert(0 && "This action is not supported yet!");
1933 case TargetLowering::Legal:
1934 // If this is an unaligned load and the target doesn't support it,
1936 if (!TLI.allowsUnalignedMemoryAccesses()) {
1937 unsigned ABIAlignment = TLI.getTargetData()->
1938 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
1939 if (LD->getAlignment() < ABIAlignment){
1940 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
1942 Tmp3 = Result.getOperand(0);
1943 Tmp4 = Result.getOperand(1);
1944 Tmp3 = LegalizeOp(Tmp3);
1945 Tmp4 = LegalizeOp(Tmp4);
1949 case TargetLowering::Custom:
1950 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1951 if (Tmp1.getNode()) {
1952 Tmp3 = LegalizeOp(Tmp1);
1953 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1956 case TargetLowering::Promote: {
1957 // Only promote a load of vector type to another.
1958 assert(VT.isVector() && "Cannot promote this load!");
1959 // Change base type to a different vector type.
1960 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1962 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1963 LD->getSrcValueOffset(),
1964 LD->isVolatile(), LD->getAlignment());
1965 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1966 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1970 // Since loads produce two values, make sure to remember that we
1971 // legalized both of them.
1972 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
1973 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
1974 return Op.getResNo() ? Tmp4 : Tmp3;
1976 MVT SrcVT = LD->getMemoryVT();
1977 unsigned SrcWidth = SrcVT.getSizeInBits();
1978 int SVOffset = LD->getSrcValueOffset();
1979 unsigned Alignment = LD->getAlignment();
1980 bool isVolatile = LD->isVolatile();
1982 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
1983 // Some targets pretend to have an i1 loading operation, and actually
1984 // load an i8. This trick is correct for ZEXTLOAD because the top 7
1985 // bits are guaranteed to be zero; it helps the optimizers understand
1986 // that these bits are zero. It is also useful for EXTLOAD, since it
1987 // tells the optimizers that those bits are undefined. It would be
1988 // nice to have an effective generic way of getting these benefits...
1989 // Until such a way is found, don't insist on promoting i1 here.
1990 (SrcVT != MVT::i1 ||
1991 TLI.getLoadXAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
1992 // Promote to a byte-sized load if not loading an integral number of
1993 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
1994 unsigned NewWidth = SrcVT.getStoreSizeInBits();
1995 MVT NVT = MVT::getIntegerVT(NewWidth);
1998 // The extra bits are guaranteed to be zero, since we stored them that
1999 // way. A zext load from NVT thus automatically gives zext from SrcVT.
2001 ISD::LoadExtType NewExtType =
2002 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
2004 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0),
2005 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
2006 NVT, isVolatile, Alignment);
2008 Ch = Result.getValue(1); // The chain.
2010 if (ExtType == ISD::SEXTLOAD)
2011 // Having the top bits zero doesn't help when sign extending.
2012 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2013 Result, DAG.getValueType(SrcVT));
2014 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
2015 // All the top bits are guaranteed to be zero - inform the optimizers.
2016 Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result,
2017 DAG.getValueType(SrcVT));
2019 Tmp1 = LegalizeOp(Result);
2020 Tmp2 = LegalizeOp(Ch);
2021 } else if (SrcWidth & (SrcWidth - 1)) {
2022 // If not loading a power-of-2 number of bits, expand as two loads.
2023 assert(SrcVT.isExtended() && !SrcVT.isVector() &&
2024 "Unsupported extload!");
2025 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
2026 assert(RoundWidth < SrcWidth);
2027 unsigned ExtraWidth = SrcWidth - RoundWidth;
2028 assert(ExtraWidth < RoundWidth);
2029 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2030 "Load size not an integral number of bytes!");
2031 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2032 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2034 unsigned IncrementSize;
2036 if (TLI.isLittleEndian()) {
2037 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
2038 // Load the bottom RoundWidth bits.
2039 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2040 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2043 // Load the remaining ExtraWidth bits.
2044 IncrementSize = RoundWidth / 8;
2045 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2046 DAG.getIntPtrConstant(IncrementSize));
2047 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2048 LD->getSrcValue(), SVOffset + IncrementSize,
2049 ExtraVT, isVolatile,
2050 MinAlign(Alignment, IncrementSize));
2052 // Build a factor node to remember that this load is independent of the
2054 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2057 // Move the top bits to the right place.
2058 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2059 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2061 // Join the hi and lo parts.
2062 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2064 // Big endian - avoid unaligned loads.
2065 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
2066 // Load the top RoundWidth bits.
2067 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2068 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2071 // Load the remaining ExtraWidth bits.
2072 IncrementSize = RoundWidth / 8;
2073 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2074 DAG.getIntPtrConstant(IncrementSize));
2075 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2076 LD->getSrcValue(), SVOffset + IncrementSize,
2077 ExtraVT, isVolatile,
2078 MinAlign(Alignment, IncrementSize));
2080 // Build a factor node to remember that this load is independent of the
2082 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2085 // Move the top bits to the right place.
2086 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2087 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2089 // Join the hi and lo parts.
2090 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2093 Tmp1 = LegalizeOp(Result);
2094 Tmp2 = LegalizeOp(Ch);
2096 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
2097 default: assert(0 && "This action is not supported yet!");
2098 case TargetLowering::Custom:
2101 case TargetLowering::Legal:
2102 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2103 Tmp1 = Result.getValue(0);
2104 Tmp2 = Result.getValue(1);
2107 Tmp3 = TLI.LowerOperation(Result, DAG);
2108 if (Tmp3.getNode()) {
2109 Tmp1 = LegalizeOp(Tmp3);
2110 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2113 // If this is an unaligned load and the target doesn't support it,
2115 if (!TLI.allowsUnalignedMemoryAccesses()) {
2116 unsigned ABIAlignment = TLI.getTargetData()->
2117 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
2118 if (LD->getAlignment() < ABIAlignment){
2119 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
2121 Tmp1 = Result.getOperand(0);
2122 Tmp2 = Result.getOperand(1);
2123 Tmp1 = LegalizeOp(Tmp1);
2124 Tmp2 = LegalizeOp(Tmp2);
2129 case TargetLowering::Expand:
2130 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
2131 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
2132 SDValue Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
2133 LD->getSrcValueOffset(),
2134 LD->isVolatile(), LD->getAlignment());
2135 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
2136 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
2137 Tmp2 = LegalizeOp(Load.getValue(1));
2140 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
2141 // Turn the unsupported load into an EXTLOAD followed by an explicit
2142 // zero/sign extend inreg.
2143 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2144 Tmp1, Tmp2, LD->getSrcValue(),
2145 LD->getSrcValueOffset(), SrcVT,
2146 LD->isVolatile(), LD->getAlignment());
2148 if (ExtType == ISD::SEXTLOAD)
2149 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2150 Result, DAG.getValueType(SrcVT));
2152 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
2153 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
2154 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
2159 // Since loads produce two values, make sure to remember that we legalized
2161 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2162 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2163 return Op.getResNo() ? Tmp2 : Tmp1;
2166 case ISD::EXTRACT_ELEMENT: {
2167 MVT OpTy = Node->getOperand(0).getValueType();
2168 switch (getTypeAction(OpTy)) {
2169 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
2171 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
2173 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
2174 DAG.getConstant(OpTy.getSizeInBits()/2,
2175 TLI.getShiftAmountTy()));
2176 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
2179 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
2180 Node->getOperand(0));
2184 // Get both the low and high parts.
2185 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2186 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
2187 Result = Tmp2; // 1 -> Hi
2189 Result = Tmp1; // 0 -> Lo
2195 case ISD::CopyToReg:
2196 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2198 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
2199 "Register type must be legal!");
2200 // Legalize the incoming value (must be a legal type).
2201 Tmp2 = LegalizeOp(Node->getOperand(2));
2202 if (Node->getNumValues() == 1) {
2203 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
2205 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
2206 if (Node->getNumOperands() == 4) {
2207 Tmp3 = LegalizeOp(Node->getOperand(3));
2208 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
2211 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
2214 // Since this produces two values, make sure to remember that we legalized
2216 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
2217 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
2223 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2225 // Ensure that libcalls are emitted before a return.
2226 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2227 Tmp1 = LegalizeOp(Tmp1);
2228 LastCALLSEQ_END = DAG.getEntryNode();
2230 switch (Node->getNumOperands()) {
2232 Tmp2 = Node->getOperand(1);
2233 Tmp3 = Node->getOperand(2); // Signness
2234 switch (getTypeAction(Tmp2.getValueType())) {
2236 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
2239 if (!Tmp2.getValueType().isVector()) {
2241 ExpandOp(Tmp2, Lo, Hi);
2243 // Big endian systems want the hi reg first.
2244 if (TLI.isBigEndian())
2248 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2250 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
2251 Result = LegalizeOp(Result);
2253 SDNode *InVal = Tmp2.getNode();
2254 int InIx = Tmp2.getResNo();
2255 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
2256 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
2258 // Figure out if there is a simple type corresponding to this Vector
2259 // type. If so, convert to the vector type.
2260 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2261 if (TLI.isTypeLegal(TVT)) {
2262 // Turn this into a return of the vector type.
2263 Tmp2 = LegalizeOp(Tmp2);
2264 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2265 } else if (NumElems == 1) {
2266 // Turn this into a return of the scalar type.
2267 Tmp2 = ScalarizeVectorOp(Tmp2);
2268 Tmp2 = LegalizeOp(Tmp2);
2269 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2271 // FIXME: Returns of gcc generic vectors smaller than a legal type
2272 // should be returned in integer registers!
2274 // The scalarized value type may not be legal, e.g. it might require
2275 // promotion or expansion. Relegalize the return.
2276 Result = LegalizeOp(Result);
2278 // FIXME: Returns of gcc generic vectors larger than a legal vector
2279 // type should be returned by reference!
2281 SplitVectorOp(Tmp2, Lo, Hi);
2282 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2283 Result = LegalizeOp(Result);
2288 Tmp2 = PromoteOp(Node->getOperand(1));
2289 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2290 Result = LegalizeOp(Result);
2295 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2297 default: { // ret <values>
2298 SmallVector<SDValue, 8> NewValues;
2299 NewValues.push_back(Tmp1);
2300 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
2301 switch (getTypeAction(Node->getOperand(i).getValueType())) {
2303 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
2304 NewValues.push_back(Node->getOperand(i+1));
2308 assert(!Node->getOperand(i).getValueType().isExtended() &&
2309 "FIXME: TODO: implement returning non-legal vector types!");
2310 ExpandOp(Node->getOperand(i), Lo, Hi);
2311 NewValues.push_back(Lo);
2312 NewValues.push_back(Node->getOperand(i+1));
2314 NewValues.push_back(Hi);
2315 NewValues.push_back(Node->getOperand(i+1));
2320 assert(0 && "Can't promote multiple return value yet!");
2323 if (NewValues.size() == Node->getNumOperands())
2324 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
2326 Result = DAG.getNode(ISD::RET, MVT::Other,
2327 &NewValues[0], NewValues.size());
2332 if (Result.getOpcode() == ISD::RET) {
2333 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
2334 default: assert(0 && "This action is not supported yet!");
2335 case TargetLowering::Legal: break;
2336 case TargetLowering::Custom:
2337 Tmp1 = TLI.LowerOperation(Result, DAG);
2338 if (Tmp1.getNode()) Result = Tmp1;
2344 StoreSDNode *ST = cast<StoreSDNode>(Node);
2345 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
2346 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
2347 int SVOffset = ST->getSrcValueOffset();
2348 unsigned Alignment = ST->getAlignment();
2349 bool isVolatile = ST->isVolatile();
2351 if (!ST->isTruncatingStore()) {
2352 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
2353 // FIXME: We shouldn't do this for TargetConstantFP's.
2354 // FIXME: move this to the DAG Combiner! Note that we can't regress due
2355 // to phase ordering between legalized code and the dag combiner. This
2356 // probably means that we need to integrate dag combiner and legalizer
2358 // We generally can't do this one for long doubles.
2359 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
2360 if (CFP->getValueType(0) == MVT::f32 &&
2361 getTypeAction(MVT::i32) == Legal) {
2362 Tmp3 = DAG.getConstant(CFP->getValueAPF().
2363 convertToAPInt().zextOrTrunc(32),
2365 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2366 SVOffset, isVolatile, Alignment);
2368 } else if (CFP->getValueType(0) == MVT::f64) {
2369 // If this target supports 64-bit registers, do a single 64-bit store.
2370 if (getTypeAction(MVT::i64) == Legal) {
2371 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt().
2372 zextOrTrunc(64), MVT::i64);
2373 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2374 SVOffset, isVolatile, Alignment);
2376 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
2377 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
2378 // stores. If the target supports neither 32- nor 64-bits, this
2379 // xform is certainly not worth it.
2380 const APInt &IntVal =CFP->getValueAPF().convertToAPInt();
2381 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
2382 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
2383 if (TLI.isBigEndian()) std::swap(Lo, Hi);
2385 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2386 SVOffset, isVolatile, Alignment);
2387 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2388 DAG.getIntPtrConstant(4));
2389 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
2390 isVolatile, MinAlign(Alignment, 4U));
2392 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2398 switch (getTypeAction(ST->getMemoryVT())) {
2400 Tmp3 = LegalizeOp(ST->getValue());
2401 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2404 MVT VT = Tmp3.getValueType();
2405 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2406 default: assert(0 && "This action is not supported yet!");
2407 case TargetLowering::Legal:
2408 // If this is an unaligned store and the target doesn't support it,
2410 if (!TLI.allowsUnalignedMemoryAccesses()) {
2411 unsigned ABIAlignment = TLI.getTargetData()->
2412 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2413 if (ST->getAlignment() < ABIAlignment)
2414 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
2418 case TargetLowering::Custom:
2419 Tmp1 = TLI.LowerOperation(Result, DAG);
2420 if (Tmp1.getNode()) Result = Tmp1;
2422 case TargetLowering::Promote:
2423 assert(VT.isVector() && "Unknown legal promote case!");
2424 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
2425 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2426 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
2427 ST->getSrcValue(), SVOffset, isVolatile,
2434 // Truncate the value and store the result.
2435 Tmp3 = PromoteOp(ST->getValue());
2436 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2437 SVOffset, ST->getMemoryVT(),
2438 isVolatile, Alignment);
2442 unsigned IncrementSize = 0;
2445 // If this is a vector type, then we have to calculate the increment as
2446 // the product of the element size in bytes, and the number of elements
2447 // in the high half of the vector.
2448 if (ST->getValue().getValueType().isVector()) {
2449 SDNode *InVal = ST->getValue().getNode();
2450 int InIx = ST->getValue().getResNo();
2451 MVT InVT = InVal->getValueType(InIx);
2452 unsigned NumElems = InVT.getVectorNumElements();
2453 MVT EVT = InVT.getVectorElementType();
2455 // Figure out if there is a simple type corresponding to this Vector
2456 // type. If so, convert to the vector type.
2457 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2458 if (TLI.isTypeLegal(TVT)) {
2459 // Turn this into a normal store of the vector type.
2460 Tmp3 = LegalizeOp(ST->getValue());
2461 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2462 SVOffset, isVolatile, Alignment);
2463 Result = LegalizeOp(Result);
2465 } else if (NumElems == 1) {
2466 // Turn this into a normal store of the scalar type.
2467 Tmp3 = ScalarizeVectorOp(ST->getValue());
2468 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2469 SVOffset, isVolatile, Alignment);
2470 // The scalarized value type may not be legal, e.g. it might require
2471 // promotion or expansion. Relegalize the scalar store.
2472 Result = LegalizeOp(Result);
2475 SplitVectorOp(ST->getValue(), Lo, Hi);
2476 IncrementSize = Lo.getNode()->getValueType(0).getVectorNumElements() *
2477 EVT.getSizeInBits()/8;
2480 ExpandOp(ST->getValue(), Lo, Hi);
2481 IncrementSize = Hi.getNode() ? Hi.getValueType().getSizeInBits()/8 : 0;
2483 if (TLI.isBigEndian())
2487 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2488 SVOffset, isVolatile, Alignment);
2490 if (Hi.getNode() == NULL) {
2491 // Must be int <-> float one-to-one expansion.
2496 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2497 DAG.getIntPtrConstant(IncrementSize));
2498 assert(isTypeLegal(Tmp2.getValueType()) &&
2499 "Pointers must be legal!");
2500 SVOffset += IncrementSize;
2501 Alignment = MinAlign(Alignment, IncrementSize);
2502 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2503 SVOffset, isVolatile, Alignment);
2504 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2508 switch (getTypeAction(ST->getValue().getValueType())) {
2510 Tmp3 = LegalizeOp(ST->getValue());
2513 // We can promote the value, the truncstore will still take care of it.
2514 Tmp3 = PromoteOp(ST->getValue());
2517 // Just store the low part. This may become a non-trunc store, so make
2518 // sure to use getTruncStore, not UpdateNodeOperands below.
2519 ExpandOp(ST->getValue(), Tmp3, Tmp4);
2520 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2521 SVOffset, MVT::i8, isVolatile, Alignment);
2524 MVT StVT = ST->getMemoryVT();
2525 unsigned StWidth = StVT.getSizeInBits();
2527 if (StWidth != StVT.getStoreSizeInBits()) {
2528 // Promote to a byte-sized store with upper bits zero if not
2529 // storing an integral number of bytes. For example, promote
2530 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
2531 MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits());
2532 Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT);
2533 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2534 SVOffset, NVT, isVolatile, Alignment);
2535 } else if (StWidth & (StWidth - 1)) {
2536 // If not storing a power-of-2 number of bits, expand as two stores.
2537 assert(StVT.isExtended() && !StVT.isVector() &&
2538 "Unsupported truncstore!");
2539 unsigned RoundWidth = 1 << Log2_32(StWidth);
2540 assert(RoundWidth < StWidth);
2541 unsigned ExtraWidth = StWidth - RoundWidth;
2542 assert(ExtraWidth < RoundWidth);
2543 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2544 "Store size not an integral number of bytes!");
2545 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2546 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2548 unsigned IncrementSize;
2550 if (TLI.isLittleEndian()) {
2551 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
2552 // Store the bottom RoundWidth bits.
2553 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2555 isVolatile, Alignment);
2557 // Store the remaining ExtraWidth bits.
2558 IncrementSize = RoundWidth / 8;
2559 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2560 DAG.getIntPtrConstant(IncrementSize));
2561 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2562 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2563 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2564 SVOffset + IncrementSize, ExtraVT, isVolatile,
2565 MinAlign(Alignment, IncrementSize));
2567 // Big endian - avoid unaligned stores.
2568 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
2569 // Store the top RoundWidth bits.
2570 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2571 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2572 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset,
2573 RoundVT, isVolatile, Alignment);
2575 // Store the remaining ExtraWidth bits.
2576 IncrementSize = RoundWidth / 8;
2577 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2578 DAG.getIntPtrConstant(IncrementSize));
2579 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2580 SVOffset + IncrementSize, ExtraVT, isVolatile,
2581 MinAlign(Alignment, IncrementSize));
2584 // The order of the stores doesn't matter.
2585 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2587 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2588 Tmp2 != ST->getBasePtr())
2589 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2592 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
2593 default: assert(0 && "This action is not supported yet!");
2594 case TargetLowering::Legal:
2595 // If this is an unaligned store and the target doesn't support it,
2597 if (!TLI.allowsUnalignedMemoryAccesses()) {
2598 unsigned ABIAlignment = TLI.getTargetData()->
2599 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2600 if (ST->getAlignment() < ABIAlignment)
2601 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
2605 case TargetLowering::Custom:
2606 Result = TLI.LowerOperation(Result, DAG);
2609 // TRUNCSTORE:i16 i32 -> STORE i16
2610 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
2611 Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3);
2612 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset,
2613 isVolatile, Alignment);
2621 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2622 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2624 case ISD::STACKSAVE:
2625 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2626 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2627 Tmp1 = Result.getValue(0);
2628 Tmp2 = Result.getValue(1);
2630 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2631 default: assert(0 && "This action is not supported yet!");
2632 case TargetLowering::Legal: break;
2633 case TargetLowering::Custom:
2634 Tmp3 = TLI.LowerOperation(Result, DAG);
2635 if (Tmp3.getNode()) {
2636 Tmp1 = LegalizeOp(Tmp3);
2637 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2640 case TargetLowering::Expand:
2641 // Expand to CopyFromReg if the target set
2642 // StackPointerRegisterToSaveRestore.
2643 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2644 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
2645 Node->getValueType(0));
2646 Tmp2 = Tmp1.getValue(1);
2648 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
2649 Tmp2 = Node->getOperand(0);
2654 // Since stacksave produce two values, make sure to remember that we
2655 // legalized both of them.
2656 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2657 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2658 return Op.getResNo() ? Tmp2 : Tmp1;
2660 case ISD::STACKRESTORE:
2661 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2662 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2663 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2665 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2666 default: assert(0 && "This action is not supported yet!");
2667 case TargetLowering::Legal: break;
2668 case TargetLowering::Custom:
2669 Tmp1 = TLI.LowerOperation(Result, DAG);
2670 if (Tmp1.getNode()) Result = Tmp1;
2672 case TargetLowering::Expand:
2673 // Expand to CopyToReg if the target set
2674 // StackPointerRegisterToSaveRestore.
2675 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2676 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
2684 case ISD::READCYCLECOUNTER:
2685 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2686 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2687 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2688 Node->getValueType(0))) {
2689 default: assert(0 && "This action is not supported yet!");
2690 case TargetLowering::Legal:
2691 Tmp1 = Result.getValue(0);
2692 Tmp2 = Result.getValue(1);
2694 case TargetLowering::Custom:
2695 Result = TLI.LowerOperation(Result, DAG);
2696 Tmp1 = LegalizeOp(Result.getValue(0));
2697 Tmp2 = LegalizeOp(Result.getValue(1));
2701 // Since rdcc produce two values, make sure to remember that we legalized
2703 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2704 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2708 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2709 case Expand: assert(0 && "It's impossible to expand bools");
2711 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2714 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2715 // Make sure the condition is either zero or one.
2716 unsigned BitWidth = Tmp1.getValueSizeInBits();
2717 if (!DAG.MaskedValueIsZero(Tmp1,
2718 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2719 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2723 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2724 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2726 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2728 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2729 default: assert(0 && "This action is not supported yet!");
2730 case TargetLowering::Legal: break;
2731 case TargetLowering::Custom: {
2732 Tmp1 = TLI.LowerOperation(Result, DAG);
2733 if (Tmp1.getNode()) Result = Tmp1;
2736 case TargetLowering::Expand:
2737 if (Tmp1.getOpcode() == ISD::SETCC) {
2738 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2740 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2742 Result = DAG.getSelectCC(Tmp1,
2743 DAG.getConstant(0, Tmp1.getValueType()),
2744 Tmp2, Tmp3, ISD::SETNE);
2747 case TargetLowering::Promote: {
2749 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2750 unsigned ExtOp, TruncOp;
2751 if (Tmp2.getValueType().isVector()) {
2752 ExtOp = ISD::BIT_CONVERT;
2753 TruncOp = ISD::BIT_CONVERT;
2754 } else if (Tmp2.getValueType().isInteger()) {
2755 ExtOp = ISD::ANY_EXTEND;
2756 TruncOp = ISD::TRUNCATE;
2758 ExtOp = ISD::FP_EXTEND;
2759 TruncOp = ISD::FP_ROUND;
2761 // Promote each of the values to the new type.
2762 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2763 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2764 // Perform the larger operation, then round down.
2765 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2766 if (TruncOp != ISD::FP_ROUND)
2767 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2769 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result,
2770 DAG.getIntPtrConstant(0));
2775 case ISD::SELECT_CC: {
2776 Tmp1 = Node->getOperand(0); // LHS
2777 Tmp2 = Node->getOperand(1); // RHS
2778 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2779 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2780 SDValue CC = Node->getOperand(4);
2782 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
2784 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
2785 // the LHS is a legal SETCC itself. In this case, we need to compare
2786 // the result against zero to select between true and false values.
2787 if (Tmp2.getNode() == 0) {
2788 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2789 CC = DAG.getCondCode(ISD::SETNE);
2791 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
2793 // Everything is legal, see if we should expand this op or something.
2794 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
2795 default: assert(0 && "This action is not supported yet!");
2796 case TargetLowering::Legal: break;
2797 case TargetLowering::Custom:
2798 Tmp1 = TLI.LowerOperation(Result, DAG);
2799 if (Tmp1.getNode()) Result = Tmp1;
2805 Tmp1 = Node->getOperand(0);
2806 Tmp2 = Node->getOperand(1);
2807 Tmp3 = Node->getOperand(2);
2808 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
2810 // If we had to Expand the SetCC operands into a SELECT node, then it may
2811 // not always be possible to return a true LHS & RHS. In this case, just
2812 // return the value we legalized, returned in the LHS
2813 if (Tmp2.getNode() == 0) {
2818 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
2819 default: assert(0 && "Cannot handle this action for SETCC yet!");
2820 case TargetLowering::Custom:
2823 case TargetLowering::Legal:
2824 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2826 Tmp4 = TLI.LowerOperation(Result, DAG);
2827 if (Tmp4.getNode()) Result = Tmp4;
2830 case TargetLowering::Promote: {
2831 // First step, figure out the appropriate operation to use.
2832 // Allow SETCC to not be supported for all legal data types
2833 // Mostly this targets FP
2834 MVT NewInTy = Node->getOperand(0).getValueType();
2835 MVT OldVT = NewInTy; OldVT = OldVT;
2837 // Scan for the appropriate larger type to use.
2839 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
2841 assert(NewInTy.isInteger() == OldVT.isInteger() &&
2842 "Fell off of the edge of the integer world");
2843 assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() &&
2844 "Fell off of the edge of the floating point world");
2846 // If the target supports SETCC of this type, use it.
2847 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2850 if (NewInTy.isInteger())
2851 assert(0 && "Cannot promote Legal Integer SETCC yet");
2853 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2854 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2856 Tmp1 = LegalizeOp(Tmp1);
2857 Tmp2 = LegalizeOp(Tmp2);
2858 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2859 Result = LegalizeOp(Result);
2862 case TargetLowering::Expand:
2863 // Expand a setcc node into a select_cc of the same condition, lhs, and
2864 // rhs that selects between const 1 (true) and const 0 (false).
2865 MVT VT = Node->getValueType(0);
2866 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2867 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2873 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2874 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2875 SDValue CC = Node->getOperand(2);
2877 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, CC);
2879 // Everything is legal, see if we should expand this op or something.
2880 switch (TLI.getOperationAction(ISD::VSETCC, Tmp1.getValueType())) {
2881 default: assert(0 && "This action is not supported yet!");
2882 case TargetLowering::Legal: break;
2883 case TargetLowering::Custom:
2884 Tmp1 = TLI.LowerOperation(Result, DAG);
2885 if (Tmp1.getNode()) Result = Tmp1;
2891 case ISD::SHL_PARTS:
2892 case ISD::SRA_PARTS:
2893 case ISD::SRL_PARTS: {
2894 SmallVector<SDValue, 8> Ops;
2895 bool Changed = false;
2896 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2897 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2898 Changed |= Ops.back() != Node->getOperand(i);
2901 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2903 switch (TLI.getOperationAction(Node->getOpcode(),
2904 Node->getValueType(0))) {
2905 default: assert(0 && "This action is not supported yet!");
2906 case TargetLowering::Legal: break;
2907 case TargetLowering::Custom:
2908 Tmp1 = TLI.LowerOperation(Result, DAG);
2909 if (Tmp1.getNode()) {
2910 SDValue Tmp2, RetVal(0, 0);
2911 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2912 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2913 AddLegalizedOperand(SDValue(Node, i), Tmp2);
2914 if (i == Op.getResNo())
2917 assert(RetVal.getNode() && "Illegal result number");
2923 // Since these produce multiple values, make sure to remember that we
2924 // legalized all of them.
2925 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2926 AddLegalizedOperand(SDValue(Node, i), Result.getValue(i));
2927 return Result.getValue(Op.getResNo());
2949 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2950 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2951 case Expand: assert(0 && "Not possible");
2953 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2956 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2960 if ((Node->getOpcode() == ISD::SHL ||
2961 Node->getOpcode() == ISD::SRL ||
2962 Node->getOpcode() == ISD::SRA) &&
2963 !Node->getValueType(0).isVector()) {
2964 if (TLI.getShiftAmountTy().bitsLT(Tmp2.getValueType()))
2965 Tmp2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Tmp2);
2966 else if (TLI.getShiftAmountTy().bitsGT(Tmp2.getValueType()))
2967 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Tmp2);
2970 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2972 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2973 default: assert(0 && "BinOp legalize operation not supported");
2974 case TargetLowering::Legal: break;
2975 case TargetLowering::Custom:
2976 Tmp1 = TLI.LowerOperation(Result, DAG);
2977 if (Tmp1.getNode()) {
2981 // Fall through if the custom lower can't deal with the operation
2982 case TargetLowering::Expand: {
2983 MVT VT = Op.getValueType();
2985 // See if multiply or divide can be lowered using two-result operations.
2986 SDVTList VTs = DAG.getVTList(VT, VT);
2987 if (Node->getOpcode() == ISD::MUL) {
2988 // We just need the low half of the multiply; try both the signed
2989 // and unsigned forms. If the target supports both SMUL_LOHI and
2990 // UMUL_LOHI, form a preference by checking which forms of plain
2991 // MULH it supports.
2992 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT);
2993 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT);
2994 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT);
2995 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT);
2996 unsigned OpToUse = 0;
2997 if (HasSMUL_LOHI && !HasMULHS) {
2998 OpToUse = ISD::SMUL_LOHI;
2999 } else if (HasUMUL_LOHI && !HasMULHU) {
3000 OpToUse = ISD::UMUL_LOHI;
3001 } else if (HasSMUL_LOHI) {
3002 OpToUse = ISD::SMUL_LOHI;
3003 } else if (HasUMUL_LOHI) {
3004 OpToUse = ISD::UMUL_LOHI;
3007 Result = SDValue(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).getNode(), 0);
3011 if (Node->getOpcode() == ISD::MULHS &&
3012 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) {
3013 Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).getNode(), 1);
3016 if (Node->getOpcode() == ISD::MULHU &&
3017 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) {
3018 Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).getNode(), 1);
3021 if (Node->getOpcode() == ISD::SDIV &&
3022 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3023 Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(), 0);
3026 if (Node->getOpcode() == ISD::UDIV &&
3027 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3028 Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(), 0);
3032 // Check to see if we have a libcall for this operator.
3033 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3034 bool isSigned = false;
3035 switch (Node->getOpcode()) {
3038 if (VT == MVT::i32) {
3039 LC = Node->getOpcode() == ISD::UDIV
3040 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
3041 isSigned = Node->getOpcode() == ISD::SDIV;
3045 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
3046 RTLIB::POW_PPCF128);
3050 if (LC != RTLIB::UNKNOWN_LIBCALL) {
3052 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3056 assert(Node->getValueType(0).isVector() &&
3057 "Cannot expand this binary operator!");
3058 // Expand the operation into a bunch of nasty scalar code.
3059 Result = LegalizeOp(UnrollVectorOp(Op));
3062 case TargetLowering::Promote: {
3063 switch (Node->getOpcode()) {
3064 default: assert(0 && "Do not know how to promote this BinOp!");
3068 MVT OVT = Node->getValueType(0);
3069 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3070 assert(OVT.isVector() && "Cannot promote this BinOp!");
3071 // Bit convert each of the values to the new type.
3072 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
3073 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
3074 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3075 // Bit convert the result back the original type.
3076 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
3084 case ISD::SMUL_LOHI:
3085 case ISD::UMUL_LOHI:
3088 // These nodes will only be produced by target-specific lowering, so
3089 // they shouldn't be here if they aren't legal.
3090 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
3091 "This must be legal!");
3093 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3094 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3095 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3098 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
3099 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3100 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3101 case Expand: assert(0 && "Not possible");
3103 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3106 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3110 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3112 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3113 default: assert(0 && "Operation not supported");
3114 case TargetLowering::Custom:
3115 Tmp1 = TLI.LowerOperation(Result, DAG);
3116 if (Tmp1.getNode()) Result = Tmp1;
3118 case TargetLowering::Legal: break;
3119 case TargetLowering::Expand: {
3120 // If this target supports fabs/fneg natively and select is cheap,
3121 // do this efficiently.
3122 if (!TLI.isSelectExpensive() &&
3123 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
3124 TargetLowering::Legal &&
3125 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
3126 TargetLowering::Legal) {
3127 // Get the sign bit of the RHS.
3129 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
3130 SDValue SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
3131 SignBit = DAG.getSetCC(TLI.getSetCCResultType(SignBit),
3132 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
3133 // Get the absolute value of the result.
3134 SDValue AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
3135 // Select between the nabs and abs value based on the sign bit of
3137 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
3138 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
3141 Result = LegalizeOp(Result);
3145 // Otherwise, do bitwise ops!
3147 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
3148 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
3149 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
3150 Result = LegalizeOp(Result);
3158 Tmp1 = LegalizeOp(Node->getOperand(0));
3159 Tmp2 = LegalizeOp(Node->getOperand(1));
3160 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3161 // Since this produces two values, make sure to remember that we legalized
3163 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
3164 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
3169 Tmp1 = LegalizeOp(Node->getOperand(0));
3170 Tmp2 = LegalizeOp(Node->getOperand(1));
3171 Tmp3 = LegalizeOp(Node->getOperand(2));
3172 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3173 // Since this produces two values, make sure to remember that we legalized
3175 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
3176 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
3179 case ISD::BUILD_PAIR: {
3180 MVT PairTy = Node->getValueType(0);
3181 // TODO: handle the case where the Lo and Hi operands are not of legal type
3182 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
3183 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
3184 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
3185 case TargetLowering::Promote:
3186 case TargetLowering::Custom:
3187 assert(0 && "Cannot promote/custom this yet!");
3188 case TargetLowering::Legal:
3189 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
3190 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
3192 case TargetLowering::Expand:
3193 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
3194 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
3195 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
3196 DAG.getConstant(PairTy.getSizeInBits()/2,
3197 TLI.getShiftAmountTy()));
3198 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
3207 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3208 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3210 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3211 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
3212 case TargetLowering::Custom:
3215 case TargetLowering::Legal:
3216 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3218 Tmp1 = TLI.LowerOperation(Result, DAG);
3219 if (Tmp1.getNode()) Result = Tmp1;
3222 case TargetLowering::Expand: {
3223 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
3224 bool isSigned = DivOpc == ISD::SDIV;
3225 MVT VT = Node->getValueType(0);
3227 // See if remainder can be lowered using two-result operations.
3228 SDVTList VTs = DAG.getVTList(VT, VT);
3229 if (Node->getOpcode() == ISD::SREM &&
3230 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3231 Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(), 1);
3234 if (Node->getOpcode() == ISD::UREM &&
3235 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3236 Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(), 1);
3240 if (VT.isInteger()) {
3241 if (TLI.getOperationAction(DivOpc, VT) ==
3242 TargetLowering::Legal) {
3244 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
3245 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
3246 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
3247 } else if (VT.isVector()) {
3248 Result = LegalizeOp(UnrollVectorOp(Op));
3250 assert(VT == MVT::i32 &&
3251 "Cannot expand this binary operator!");
3252 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
3253 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
3255 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3258 assert(VT.isFloatingPoint() &&
3259 "remainder op must have integer or floating-point type");
3260 if (VT.isVector()) {
3261 Result = LegalizeOp(UnrollVectorOp(Op));
3263 // Floating point mod -> fmod libcall.
3264 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
3265 RTLIB::REM_F80, RTLIB::REM_PPCF128);
3267 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3275 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3276 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3278 MVT VT = Node->getValueType(0);
3279 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
3280 default: assert(0 && "This action is not supported yet!");
3281 case TargetLowering::Custom:
3284 case TargetLowering::Legal:
3285 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3286 Result = Result.getValue(0);
3287 Tmp1 = Result.getValue(1);
3290 Tmp2 = TLI.LowerOperation(Result, DAG);
3291 if (Tmp2.getNode()) {
3292 Result = LegalizeOp(Tmp2);
3293 Tmp1 = LegalizeOp(Tmp2.getValue(1));
3297 case TargetLowering::Expand: {
3298 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3299 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
3300 // Increment the pointer, VAList, to the next vaarg
3301 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3302 DAG.getConstant(VT.getSizeInBits()/8,
3303 TLI.getPointerTy()));
3304 // Store the incremented VAList to the legalized pointer
3305 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
3306 // Load the actual argument out of the pointer VAList
3307 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
3308 Tmp1 = LegalizeOp(Result.getValue(1));
3309 Result = LegalizeOp(Result);
3313 // Since VAARG produces two values, make sure to remember that we
3314 // legalized both of them.
3315 AddLegalizedOperand(SDValue(Node, 0), Result);
3316 AddLegalizedOperand(SDValue(Node, 1), Tmp1);
3317 return Op.getResNo() ? Tmp1 : Result;
3321 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3322 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
3323 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
3325 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
3326 default: assert(0 && "This action is not supported yet!");
3327 case TargetLowering::Custom:
3330 case TargetLowering::Legal:
3331 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
3332 Node->getOperand(3), Node->getOperand(4));
3334 Tmp1 = TLI.LowerOperation(Result, DAG);
3335 if (Tmp1.getNode()) Result = Tmp1;
3338 case TargetLowering::Expand:
3339 // This defaults to loading a pointer from the input and storing it to the
3340 // output, returning the chain.
3341 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3342 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3343 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VS, 0);
3344 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VD, 0);
3350 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3351 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3353 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
3354 default: assert(0 && "This action is not supported yet!");
3355 case TargetLowering::Custom:
3358 case TargetLowering::Legal:
3359 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3361 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
3362 if (Tmp1.getNode()) Result = Tmp1;
3365 case TargetLowering::Expand:
3366 Result = Tmp1; // Default to a no-op, return the chain
3372 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3373 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3375 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3377 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
3378 default: assert(0 && "This action is not supported yet!");
3379 case TargetLowering::Legal: break;
3380 case TargetLowering::Custom:
3381 Tmp1 = TLI.LowerOperation(Result, DAG);
3382 if (Tmp1.getNode()) Result = Tmp1;
3389 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3390 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3391 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3392 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3394 assert(0 && "ROTL/ROTR legalize operation not supported");
3396 case TargetLowering::Legal:
3398 case TargetLowering::Custom:
3399 Tmp1 = TLI.LowerOperation(Result, DAG);
3400 if (Tmp1.getNode()) Result = Tmp1;
3402 case TargetLowering::Promote:
3403 assert(0 && "Do not know how to promote ROTL/ROTR");
3405 case TargetLowering::Expand:
3406 assert(0 && "Do not know how to expand ROTL/ROTR");
3412 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3413 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3414 case TargetLowering::Custom:
3415 assert(0 && "Cannot custom legalize this yet!");
3416 case TargetLowering::Legal:
3417 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3419 case TargetLowering::Promote: {
3420 MVT OVT = Tmp1.getValueType();
3421 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3422 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3424 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3425 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3426 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3427 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3430 case TargetLowering::Expand:
3431 Result = ExpandBSWAP(Tmp1);
3439 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3440 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3441 case TargetLowering::Custom:
3442 case TargetLowering::Legal:
3443 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3444 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3445 TargetLowering::Custom) {
3446 Tmp1 = TLI.LowerOperation(Result, DAG);
3447 if (Tmp1.getNode()) {
3452 case TargetLowering::Promote: {
3453 MVT OVT = Tmp1.getValueType();
3454 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3456 // Zero extend the argument.
3457 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3458 // Perform the larger operation, then subtract if needed.
3459 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
3460 switch (Node->getOpcode()) {
3465 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3466 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
3467 DAG.getConstant(NVT.getSizeInBits(), NVT),
3469 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3470 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3473 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3474 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3475 DAG.getConstant(NVT.getSizeInBits() -
3476 OVT.getSizeInBits(), NVT));
3481 case TargetLowering::Expand:
3482 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
3502 case ISD::FNEARBYINT:
3503 Tmp1 = LegalizeOp(Node->getOperand(0));
3504 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3505 case TargetLowering::Promote:
3506 case TargetLowering::Custom:
3509 case TargetLowering::Legal:
3510 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3512 Tmp1 = TLI.LowerOperation(Result, DAG);
3513 if (Tmp1.getNode()) Result = Tmp1;
3516 case TargetLowering::Expand:
3517 switch (Node->getOpcode()) {
3518 default: assert(0 && "Unreachable!");
3520 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3521 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3522 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
3525 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3526 MVT VT = Node->getValueType(0);
3527 Tmp2 = DAG.getConstantFP(0.0, VT);
3528 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
3530 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
3531 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
3543 case ISD::FNEARBYINT:
3547 MVT VT = Node->getValueType(0);
3549 // Expand unsupported unary vector operators by unrolling them.
3550 if (VT.isVector()) {
3551 Result = LegalizeOp(UnrollVectorOp(Op));
3555 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3556 switch(Node->getOpcode()) {
3558 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3559 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
3562 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
3563 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
3566 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
3567 RTLIB::COS_F80, RTLIB::COS_PPCF128);
3570 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
3571 RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
3574 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3575 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
3578 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3579 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
3582 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
3583 RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
3586 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3587 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
3590 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3591 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
3594 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3595 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128);
3598 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3599 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128);
3602 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64,
3603 RTLIB::RINT_F80, RTLIB::RINT_PPCF128);
3605 case ISD::FNEARBYINT:
3606 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
3607 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
3609 default: assert(0 && "Unreachable!");
3612 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3620 MVT VT = Node->getValueType(0);
3622 // Expand unsupported unary vector operators by unrolling them.
3623 if (VT.isVector()) {
3624 Result = LegalizeOp(UnrollVectorOp(Op));
3628 // We always lower FPOWI into a libcall. No target support for it yet.
3629 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
3630 RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
3632 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3635 case ISD::BIT_CONVERT:
3636 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3637 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3638 Node->getValueType(0));
3639 } else if (Op.getOperand(0).getValueType().isVector()) {
3640 // The input has to be a vector type, we have to either scalarize it, pack
3641 // it, or convert it based on whether the input vector type is legal.
3642 SDNode *InVal = Node->getOperand(0).getNode();
3643 int InIx = Node->getOperand(0).getResNo();
3644 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
3645 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
3647 // Figure out if there is a simple type corresponding to this Vector
3648 // type. If so, convert to the vector type.
3649 MVT TVT = MVT::getVectorVT(EVT, NumElems);
3650 if (TLI.isTypeLegal(TVT)) {
3651 // Turn this into a bit convert of the vector input.
3652 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3653 LegalizeOp(Node->getOperand(0)));
3655 } else if (NumElems == 1) {
3656 // Turn this into a bit convert of the scalar input.
3657 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3658 ScalarizeVectorOp(Node->getOperand(0)));
3661 // FIXME: UNIMP! Store then reload
3662 assert(0 && "Cast from unsupported vector type not implemented yet!");
3665 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3666 Node->getOperand(0).getValueType())) {
3667 default: assert(0 && "Unknown operation action!");
3668 case TargetLowering::Expand:
3669 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3670 Node->getValueType(0));
3672 case TargetLowering::Legal:
3673 Tmp1 = LegalizeOp(Node->getOperand(0));
3674 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3680 // Conversion operators. The source and destination have different types.
3681 case ISD::SINT_TO_FP:
3682 case ISD::UINT_TO_FP: {
3683 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
3684 Result = LegalizeINT_TO_FP(Result, isSigned,
3685 Node->getValueType(0), Node->getOperand(0));
3689 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3691 Tmp1 = LegalizeOp(Node->getOperand(0));
3692 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3695 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3697 // Since the result is legal, we should just be able to truncate the low
3698 // part of the source.
3699 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
3702 Result = PromoteOp(Node->getOperand(0));
3703 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
3708 case ISD::FP_TO_SINT:
3709 case ISD::FP_TO_UINT:
3710 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3712 Tmp1 = LegalizeOp(Node->getOperand(0));
3714 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
3715 default: assert(0 && "Unknown operation action!");
3716 case TargetLowering::Custom:
3719 case TargetLowering::Legal:
3720 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3722 Tmp1 = TLI.LowerOperation(Result, DAG);
3723 if (Tmp1.getNode()) Result = Tmp1;
3726 case TargetLowering::Promote:
3727 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
3728 Node->getOpcode() == ISD::FP_TO_SINT);
3730 case TargetLowering::Expand:
3731 if (Node->getOpcode() == ISD::FP_TO_UINT) {
3732 SDValue True, False;
3733 MVT VT = Node->getOperand(0).getValueType();
3734 MVT NVT = Node->getValueType(0);
3735 const uint64_t zero[] = {0, 0};
3736 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero));
3737 APInt x = APInt::getSignBit(NVT.getSizeInBits());
3738 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
3739 Tmp2 = DAG.getConstantFP(apf, VT);
3740 Tmp3 = DAG.getSetCC(TLI.getSetCCResultType(Node->getOperand(0)),
3741 Node->getOperand(0), Tmp2, ISD::SETLT);
3742 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
3743 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
3744 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
3746 False = DAG.getNode(ISD::XOR, NVT, False,
3747 DAG.getConstant(x, NVT));
3748 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
3751 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
3757 MVT VT = Op.getValueType();
3758 MVT OVT = Node->getOperand(0).getValueType();
3759 // Convert ppcf128 to i32
3760 if (OVT == MVT::ppcf128 && VT == MVT::i32) {
3761 if (Node->getOpcode() == ISD::FP_TO_SINT) {
3762 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128,
3763 Node->getOperand(0), DAG.getValueType(MVT::f64));
3764 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result,
3765 DAG.getIntPtrConstant(1));
3766 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result);
3768 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
3769 APFloat apf = APFloat(APInt(128, 2, TwoE31));
3770 Tmp2 = DAG.getConstantFP(apf, OVT);
3771 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
3772 // FIXME: generated code sucks.
3773 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2,
3774 DAG.getNode(ISD::ADD, MVT::i32,
3775 DAG.getNode(ISD::FP_TO_SINT, VT,
3776 DAG.getNode(ISD::FSUB, OVT,
3777 Node->getOperand(0), Tmp2)),
3778 DAG.getConstant(0x80000000, MVT::i32)),
3779 DAG.getNode(ISD::FP_TO_SINT, VT,
3780 Node->getOperand(0)),
3781 DAG.getCondCode(ISD::SETGE));
3785 // Convert f32 / f64 to i32 / i64 / i128.
3786 RTLIB::Libcall LC = (Node->getOpcode() == ISD::FP_TO_SINT) ?
3787 RTLIB::getFPTOSINT(OVT, VT) : RTLIB::getFPTOUINT(OVT, VT);
3788 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpectd fp-to-int conversion!");
3790 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3794 Tmp1 = PromoteOp(Node->getOperand(0));
3795 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
3796 Result = LegalizeOp(Result);
3801 case ISD::FP_EXTEND: {
3802 MVT DstVT = Op.getValueType();
3803 MVT SrcVT = Op.getOperand(0).getValueType();
3804 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3805 // The only other way we can lower this is to turn it into a STORE,
3806 // LOAD pair, targetting a temporary location (a stack slot).
3807 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT);
3810 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3811 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3813 Tmp1 = LegalizeOp(Node->getOperand(0));
3814 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3817 Tmp1 = PromoteOp(Node->getOperand(0));
3818 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1);
3823 case ISD::FP_ROUND: {
3824 MVT DstVT = Op.getValueType();
3825 MVT SrcVT = Op.getOperand(0).getValueType();
3826 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3827 if (SrcVT == MVT::ppcf128) {
3829 ExpandOp(Node->getOperand(0), Lo, Result);
3830 // Round it the rest of the way (e.g. to f32) if needed.
3831 if (DstVT!=MVT::f64)
3832 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1));
3835 // The only other way we can lower this is to turn it into a STORE,
3836 // LOAD pair, targetting a temporary location (a stack slot).
3837 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT);
3840 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3841 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3843 Tmp1 = LegalizeOp(Node->getOperand(0));
3844 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3847 Tmp1 = PromoteOp(Node->getOperand(0));
3848 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1,
3849 Node->getOperand(1));
3854 case ISD::ANY_EXTEND:
3855 case ISD::ZERO_EXTEND:
3856 case ISD::SIGN_EXTEND:
3857 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3858 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3860 Tmp1 = LegalizeOp(Node->getOperand(0));
3861 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3862 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3863 TargetLowering::Custom) {
3864 Tmp1 = TLI.LowerOperation(Result, DAG);
3865 if (Tmp1.getNode()) Result = Tmp1;
3869 switch (Node->getOpcode()) {
3870 case ISD::ANY_EXTEND:
3871 Tmp1 = PromoteOp(Node->getOperand(0));
3872 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
3874 case ISD::ZERO_EXTEND:
3875 Result = PromoteOp(Node->getOperand(0));
3876 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3877 Result = DAG.getZeroExtendInReg(Result,
3878 Node->getOperand(0).getValueType());
3880 case ISD::SIGN_EXTEND:
3881 Result = PromoteOp(Node->getOperand(0));
3882 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3883 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3885 DAG.getValueType(Node->getOperand(0).getValueType()));
3890 case ISD::FP_ROUND_INREG:
3891 case ISD::SIGN_EXTEND_INREG: {
3892 Tmp1 = LegalizeOp(Node->getOperand(0));
3893 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3895 // If this operation is not supported, convert it to a shl/shr or load/store
3897 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
3898 default: assert(0 && "This action not supported for this op yet!");
3899 case TargetLowering::Legal:
3900 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3902 case TargetLowering::Expand:
3903 // If this is an integer extend and shifts are supported, do that.
3904 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
3905 // NOTE: we could fall back on load/store here too for targets without
3906 // SAR. However, it is doubtful that any exist.
3907 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() -
3908 ExtraVT.getSizeInBits();
3909 SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
3910 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
3911 Node->getOperand(0), ShiftCst);
3912 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
3914 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
3915 // The only way we can lower this is to turn it into a TRUNCSTORE,
3916 // EXTLOAD pair, targetting a temporary location (a stack slot).
3918 // NOTE: there is a choice here between constantly creating new stack
3919 // slots and always reusing the same one. We currently always create
3920 // new ones, as reuse may inhibit scheduling.
3921 Result = EmitStackConvert(Node->getOperand(0), ExtraVT,
3922 Node->getValueType(0));
3924 assert(0 && "Unknown op");
3930 case ISD::TRAMPOLINE: {
3932 for (unsigned i = 0; i != 6; ++i)
3933 Ops[i] = LegalizeOp(Node->getOperand(i));
3934 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
3935 // The only option for this node is to custom lower it.
3936 Result = TLI.LowerOperation(Result, DAG);
3937 assert(Result.getNode() && "Should always custom lower!");
3939 // Since trampoline produces two values, make sure to remember that we
3940 // legalized both of them.
3941 Tmp1 = LegalizeOp(Result.getValue(1));
3942 Result = LegalizeOp(Result);
3943 AddLegalizedOperand(SDValue(Node, 0), Result);
3944 AddLegalizedOperand(SDValue(Node, 1), Tmp1);
3945 return Op.getResNo() ? Tmp1 : Result;
3947 case ISD::FLT_ROUNDS_: {
3948 MVT VT = Node->getValueType(0);
3949 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
3950 default: assert(0 && "This action not supported for this op yet!");
3951 case TargetLowering::Custom:
3952 Result = TLI.LowerOperation(Op, DAG);
3953 if (Result.getNode()) break;
3955 case TargetLowering::Legal:
3956 // If this operation is not supported, lower it to constant 1
3957 Result = DAG.getConstant(1, VT);
3963 MVT VT = Node->getValueType(0);
3964 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
3965 default: assert(0 && "This action not supported for this op yet!");
3966 case TargetLowering::Legal:
3967 Tmp1 = LegalizeOp(Node->getOperand(0));
3968 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3970 case TargetLowering::Custom:
3971 Result = TLI.LowerOperation(Op, DAG);
3972 if (Result.getNode()) break;
3974 case TargetLowering::Expand:
3975 // If this operation is not supported, lower it to 'abort()' call
3976 Tmp1 = LegalizeOp(Node->getOperand(0));
3977 TargetLowering::ArgListTy Args;
3978 std::pair<SDValue,SDValue> CallResult =
3979 TLI.LowerCallTo(Tmp1, Type::VoidTy,
3980 false, false, false, CallingConv::C, false,
3981 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
3983 Result = CallResult.second;
3990 assert(Result.getValueType() == Op.getValueType() &&
3991 "Bad legalization!");
3993 // Make sure that the generated code is itself legal.
3995 Result = LegalizeOp(Result);
3997 // Note that LegalizeOp may be reentered even from single-use nodes, which
3998 // means that we always must cache transformed nodes.
3999 AddLegalizedOperand(Op, Result);
4003 /// PromoteOp - Given an operation that produces a value in an invalid type,
4004 /// promote it to compute the value into a larger type. The produced value will
4005 /// have the correct bits for the low portion of the register, but no guarantee
4006 /// is made about the top bits: it may be zero, sign-extended, or garbage.
4007 SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) {
4008 MVT VT = Op.getValueType();
4009 MVT NVT = TLI.getTypeToTransformTo(VT);
4010 assert(getTypeAction(VT) == Promote &&
4011 "Caller should expand or legalize operands that are not promotable!");
4012 assert(NVT.bitsGT(VT) && NVT.isInteger() == VT.isInteger() &&
4013 "Cannot promote to smaller type!");
4015 SDValue Tmp1, Tmp2, Tmp3;
4017 SDNode *Node = Op.getNode();
4019 DenseMap<SDValue, SDValue>::iterator I = PromotedNodes.find(Op);
4020 if (I != PromotedNodes.end()) return I->second;
4022 switch (Node->getOpcode()) {
4023 case ISD::CopyFromReg:
4024 assert(0 && "CopyFromReg must be legal!");
4027 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
4029 assert(0 && "Do not know how to promote this operator!");
4032 Result = DAG.getNode(ISD::UNDEF, NVT);
4036 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
4038 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
4039 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
4041 case ISD::ConstantFP:
4042 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
4043 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
4047 assert(isTypeLegal(TLI.getSetCCResultType(Node->getOperand(0)))
4048 && "SetCC type is not legal??");
4049 Result = DAG.getNode(ISD::SETCC,
4050 TLI.getSetCCResultType(Node->getOperand(0)),
4051 Node->getOperand(0), Node->getOperand(1),
4052 Node->getOperand(2));
4056 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4058 Result = LegalizeOp(Node->getOperand(0));
4059 assert(Result.getValueType().bitsGE(NVT) &&
4060 "This truncation doesn't make sense!");
4061 if (Result.getValueType().bitsGT(NVT)) // Truncate to NVT instead of VT
4062 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
4065 // The truncation is not required, because we don't guarantee anything
4066 // about high bits anyway.
4067 Result = PromoteOp(Node->getOperand(0));
4070 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4071 // Truncate the low part of the expanded value to the result type
4072 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
4075 case ISD::SIGN_EXTEND:
4076 case ISD::ZERO_EXTEND:
4077 case ISD::ANY_EXTEND:
4078 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4079 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
4081 // Input is legal? Just do extend all the way to the larger type.
4082 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4085 // Promote the reg if it's smaller.
4086 Result = PromoteOp(Node->getOperand(0));
4087 // The high bits are not guaranteed to be anything. Insert an extend.
4088 if (Node->getOpcode() == ISD::SIGN_EXTEND)
4089 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4090 DAG.getValueType(Node->getOperand(0).getValueType()));
4091 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
4092 Result = DAG.getZeroExtendInReg(Result,
4093 Node->getOperand(0).getValueType());
4097 case ISD::BIT_CONVERT:
4098 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
4099 Node->getValueType(0));
4100 Result = PromoteOp(Result);
4103 case ISD::FP_EXTEND:
4104 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
4106 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4107 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
4108 case Promote: assert(0 && "Unreachable with 2 FP types!");
4110 if (Node->getConstantOperandVal(1) == 0) {
4111 // Input is legal? Do an FP_ROUND_INREG.
4112 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
4113 DAG.getValueType(VT));
4115 // Just remove the truncate, it isn't affecting the value.
4116 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0),
4117 Node->getOperand(1));
4122 case ISD::SINT_TO_FP:
4123 case ISD::UINT_TO_FP:
4124 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4126 // No extra round required here.
4127 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4131 Result = PromoteOp(Node->getOperand(0));
4132 if (Node->getOpcode() == ISD::SINT_TO_FP)
4133 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
4135 DAG.getValueType(Node->getOperand(0).getValueType()));
4137 Result = DAG.getZeroExtendInReg(Result,
4138 Node->getOperand(0).getValueType());
4139 // No extra round required here.
4140 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
4143 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
4144 Node->getOperand(0));
4145 // Round if we cannot tolerate excess precision.
4146 if (NoExcessFPPrecision)
4147 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4148 DAG.getValueType(VT));
4153 case ISD::SIGN_EXTEND_INREG:
4154 Result = PromoteOp(Node->getOperand(0));
4155 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4156 Node->getOperand(1));
4158 case ISD::FP_TO_SINT:
4159 case ISD::FP_TO_UINT:
4160 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4163 Tmp1 = Node->getOperand(0);
4166 // The input result is prerounded, so we don't have to do anything
4168 Tmp1 = PromoteOp(Node->getOperand(0));
4171 // If we're promoting a UINT to a larger size, check to see if the new node
4172 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
4173 // we can use that instead. This allows us to generate better code for
4174 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
4175 // legal, such as PowerPC.
4176 if (Node->getOpcode() == ISD::FP_TO_UINT &&
4177 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
4178 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
4179 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
4180 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
4182 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4188 Tmp1 = PromoteOp(Node->getOperand(0));
4189 assert(Tmp1.getValueType() == NVT);
4190 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4191 // NOTE: we do not have to do any extra rounding here for
4192 // NoExcessFPPrecision, because we know the input will have the appropriate
4193 // precision, and these operations don't modify precision at all.
4208 case ISD::FNEARBYINT:
4209 Tmp1 = PromoteOp(Node->getOperand(0));
4210 assert(Tmp1.getValueType() == NVT);
4211 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4212 if (NoExcessFPPrecision)
4213 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4214 DAG.getValueType(VT));
4218 // Promote f32 powi to f64 powi. Note that this could insert a libcall
4219 // directly as well, which may be better.
4220 Tmp1 = PromoteOp(Node->getOperand(0));
4221 assert(Tmp1.getValueType() == NVT);
4222 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1));
4223 if (NoExcessFPPrecision)
4224 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4225 DAG.getValueType(VT));
4229 case ISD::ATOMIC_CMP_SWAP_8:
4230 case ISD::ATOMIC_CMP_SWAP_16:
4231 case ISD::ATOMIC_CMP_SWAP_32:
4232 case ISD::ATOMIC_CMP_SWAP_64: {
4233 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4234 Tmp2 = PromoteOp(Node->getOperand(2));
4235 Tmp3 = PromoteOp(Node->getOperand(3));
4236 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(),
4237 AtomNode->getBasePtr(), Tmp2, Tmp3,
4238 AtomNode->getSrcValue(),
4239 AtomNode->getAlignment());
4240 // Remember that we legalized the chain.
4241 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4244 case ISD::ATOMIC_LOAD_ADD_8:
4245 case ISD::ATOMIC_LOAD_SUB_8:
4246 case ISD::ATOMIC_LOAD_AND_8:
4247 case ISD::ATOMIC_LOAD_OR_8:
4248 case ISD::ATOMIC_LOAD_XOR_8:
4249 case ISD::ATOMIC_LOAD_NAND_8:
4250 case ISD::ATOMIC_LOAD_MIN_8:
4251 case ISD::ATOMIC_LOAD_MAX_8:
4252 case ISD::ATOMIC_LOAD_UMIN_8:
4253 case ISD::ATOMIC_LOAD_UMAX_8:
4254 case ISD::ATOMIC_SWAP_8:
4255 case ISD::ATOMIC_LOAD_ADD_16:
4256 case ISD::ATOMIC_LOAD_SUB_16:
4257 case ISD::ATOMIC_LOAD_AND_16:
4258 case ISD::ATOMIC_LOAD_OR_16:
4259 case ISD::ATOMIC_LOAD_XOR_16:
4260 case ISD::ATOMIC_LOAD_NAND_16:
4261 case ISD::ATOMIC_LOAD_MIN_16:
4262 case ISD::ATOMIC_LOAD_MAX_16:
4263 case ISD::ATOMIC_LOAD_UMIN_16:
4264 case ISD::ATOMIC_LOAD_UMAX_16:
4265 case ISD::ATOMIC_SWAP_16:
4266 case ISD::ATOMIC_LOAD_ADD_32:
4267 case ISD::ATOMIC_LOAD_SUB_32:
4268 case ISD::ATOMIC_LOAD_AND_32:
4269 case ISD::ATOMIC_LOAD_OR_32:
4270 case ISD::ATOMIC_LOAD_XOR_32:
4271 case ISD::ATOMIC_LOAD_NAND_32:
4272 case ISD::ATOMIC_LOAD_MIN_32:
4273 case ISD::ATOMIC_LOAD_MAX_32:
4274 case ISD::ATOMIC_LOAD_UMIN_32:
4275 case ISD::ATOMIC_LOAD_UMAX_32:
4276 case ISD::ATOMIC_SWAP_32:
4277 case ISD::ATOMIC_LOAD_ADD_64:
4278 case ISD::ATOMIC_LOAD_SUB_64:
4279 case ISD::ATOMIC_LOAD_AND_64:
4280 case ISD::ATOMIC_LOAD_OR_64:
4281 case ISD::ATOMIC_LOAD_XOR_64:
4282 case ISD::ATOMIC_LOAD_NAND_64:
4283 case ISD::ATOMIC_LOAD_MIN_64:
4284 case ISD::ATOMIC_LOAD_MAX_64:
4285 case ISD::ATOMIC_LOAD_UMIN_64:
4286 case ISD::ATOMIC_LOAD_UMAX_64:
4287 case ISD::ATOMIC_SWAP_64: {
4288 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4289 Tmp2 = PromoteOp(Node->getOperand(2));
4290 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(),
4291 AtomNode->getBasePtr(), Tmp2,
4292 AtomNode->getSrcValue(),
4293 AtomNode->getAlignment());
4294 // Remember that we legalized the chain.
4295 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4305 // The input may have strange things in the top bits of the registers, but
4306 // these operations don't care. They may have weird bits going out, but
4307 // that too is okay if they are integer operations.
4308 Tmp1 = PromoteOp(Node->getOperand(0));
4309 Tmp2 = PromoteOp(Node->getOperand(1));
4310 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4311 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4316 Tmp1 = PromoteOp(Node->getOperand(0));
4317 Tmp2 = PromoteOp(Node->getOperand(1));
4318 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4319 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4321 // Floating point operations will give excess precision that we may not be
4322 // able to tolerate. If we DO allow excess precision, just leave it,
4323 // otherwise excise it.
4324 // FIXME: Why would we need to round FP ops more than integer ones?
4325 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
4326 if (NoExcessFPPrecision)
4327 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4328 DAG.getValueType(VT));
4333 // These operators require that their input be sign extended.
4334 Tmp1 = PromoteOp(Node->getOperand(0));
4335 Tmp2 = PromoteOp(Node->getOperand(1));
4336 if (NVT.isInteger()) {
4337 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4338 DAG.getValueType(VT));
4339 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4340 DAG.getValueType(VT));
4342 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4344 // Perform FP_ROUND: this is probably overly pessimistic.
4345 if (NVT.isFloatingPoint() && NoExcessFPPrecision)
4346 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4347 DAG.getValueType(VT));
4351 case ISD::FCOPYSIGN:
4352 // These operators require that their input be fp extended.
4353 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4354 case Expand: assert(0 && "not implemented");
4355 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break;
4356 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break;
4358 switch (getTypeAction(Node->getOperand(1).getValueType())) {
4359 case Expand: assert(0 && "not implemented");
4360 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
4361 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
4363 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4365 // Perform FP_ROUND: this is probably overly pessimistic.
4366 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
4367 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4368 DAG.getValueType(VT));
4373 // These operators require that their input be zero extended.
4374 Tmp1 = PromoteOp(Node->getOperand(0));
4375 Tmp2 = PromoteOp(Node->getOperand(1));
4376 assert(NVT.isInteger() && "Operators don't apply to FP!");
4377 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4378 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4379 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4383 Tmp1 = PromoteOp(Node->getOperand(0));
4384 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
4387 // The input value must be properly sign extended.
4388 Tmp1 = PromoteOp(Node->getOperand(0));
4389 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4390 DAG.getValueType(VT));
4391 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
4394 // The input value must be properly zero extended.
4395 Tmp1 = PromoteOp(Node->getOperand(0));
4396 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4397 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
4401 Tmp1 = Node->getOperand(0); // Get the chain.
4402 Tmp2 = Node->getOperand(1); // Get the pointer.
4403 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
4404 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
4405 Result = TLI.LowerOperation(Tmp3, DAG);
4407 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
4408 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
4409 // Increment the pointer, VAList, to the next vaarg
4410 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
4411 DAG.getConstant(VT.getSizeInBits()/8,
4412 TLI.getPointerTy()));
4413 // Store the incremented VAList to the legalized pointer
4414 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
4415 // Load the actual argument out of the pointer VAList
4416 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
4418 // Remember that we legalized the chain.
4419 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4423 LoadSDNode *LD = cast<LoadSDNode>(Node);
4424 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
4425 ? ISD::EXTLOAD : LD->getExtensionType();
4426 Result = DAG.getExtLoad(ExtType, NVT,
4427 LD->getChain(), LD->getBasePtr(),
4428 LD->getSrcValue(), LD->getSrcValueOffset(),
4431 LD->getAlignment());
4432 // Remember that we legalized the chain.
4433 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4437 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
4438 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
4440 MVT VT2 = Tmp2.getValueType();
4441 assert(VT2 == Tmp3.getValueType()
4442 && "PromoteOp SELECT: Operands 2 and 3 ValueTypes don't match");
4443 // Ensure that the resulting node is at least the same size as the operands'
4444 // value types, because we cannot assume that TLI.getSetCCValueType() is
4446 Result = DAG.getNode(ISD::SELECT, VT2, Node->getOperand(0), Tmp2, Tmp3);
4449 case ISD::SELECT_CC:
4450 Tmp2 = PromoteOp(Node->getOperand(2)); // True
4451 Tmp3 = PromoteOp(Node->getOperand(3)); // False
4452 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4453 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
4456 Tmp1 = Node->getOperand(0);
4457 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
4458 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
4459 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
4460 DAG.getConstant(NVT.getSizeInBits() -
4462 TLI.getShiftAmountTy()));
4467 // Zero extend the argument
4468 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4469 // Perform the larger operation, then subtract if needed.
4470 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4471 switch(Node->getOpcode()) {
4476 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
4477 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
4478 DAG.getConstant(NVT.getSizeInBits(), NVT),
4480 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
4481 DAG.getConstant(VT.getSizeInBits(), NVT), Tmp1);
4484 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4485 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
4486 DAG.getConstant(NVT.getSizeInBits() -
4487 VT.getSizeInBits(), NVT));
4491 case ISD::EXTRACT_SUBVECTOR:
4492 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
4494 case ISD::EXTRACT_VECTOR_ELT:
4495 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
4499 assert(Result.getNode() && "Didn't set a result!");
4501 // Make sure the result is itself legal.
4502 Result = LegalizeOp(Result);
4504 // Remember that we promoted this!
4505 AddPromotedOperand(Op, Result);
4509 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
4510 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
4511 /// based on the vector type. The return type of this matches the element type
4512 /// of the vector, which may not be legal for the target.
4513 SDValue SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDValue Op) {
4514 // We know that operand #0 is the Vec vector. If the index is a constant
4515 // or if the invec is a supported hardware type, we can use it. Otherwise,
4516 // lower to a store then an indexed load.
4517 SDValue Vec = Op.getOperand(0);
4518 SDValue Idx = Op.getOperand(1);
4520 MVT TVT = Vec.getValueType();
4521 unsigned NumElems = TVT.getVectorNumElements();
4523 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
4524 default: assert(0 && "This action is not supported yet!");
4525 case TargetLowering::Custom: {
4526 Vec = LegalizeOp(Vec);
4527 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4528 SDValue Tmp3 = TLI.LowerOperation(Op, DAG);
4533 case TargetLowering::Legal:
4534 if (isTypeLegal(TVT)) {
4535 Vec = LegalizeOp(Vec);
4536 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4540 case TargetLowering::Expand:
4544 if (NumElems == 1) {
4545 // This must be an access of the only element. Return it.
4546 Op = ScalarizeVectorOp(Vec);
4547 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
4548 unsigned NumLoElts = 1 << Log2_32(NumElems-1);
4549 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4551 SplitVectorOp(Vec, Lo, Hi);
4552 if (CIdx->getValue() < NumLoElts) {
4556 Idx = DAG.getConstant(CIdx->getValue() - NumLoElts,
4557 Idx.getValueType());
4560 // It's now an extract from the appropriate high or low part. Recurse.
4561 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4562 Op = ExpandEXTRACT_VECTOR_ELT(Op);
4564 // Store the value to a temporary stack slot, then LOAD the scalar
4565 // element back out.
4566 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
4567 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
4569 // Add the offset to the index.
4570 unsigned EltSize = Op.getValueType().getSizeInBits()/8;
4571 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
4572 DAG.getConstant(EltSize, Idx.getValueType()));
4574 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
4575 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx);
4577 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
4579 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
4581 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
4586 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
4587 /// we assume the operation can be split if it is not already legal.
4588 SDValue SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDValue Op) {
4589 // We know that operand #0 is the Vec vector. For now we assume the index
4590 // is a constant and that the extracted result is a supported hardware type.
4591 SDValue Vec = Op.getOperand(0);
4592 SDValue Idx = LegalizeOp(Op.getOperand(1));
4594 unsigned NumElems = Vec.getValueType().getVectorNumElements();
4596 if (NumElems == Op.getValueType().getVectorNumElements()) {
4597 // This must be an access of the desired vector length. Return it.
4601 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4603 SplitVectorOp(Vec, Lo, Hi);
4604 if (CIdx->getValue() < NumElems/2) {
4608 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
4611 // It's now an extract from the appropriate high or low part. Recurse.
4612 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4613 return ExpandEXTRACT_SUBVECTOR(Op);
4616 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
4617 /// with condition CC on the current target. This usually involves legalizing
4618 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
4619 /// there may be no choice but to create a new SetCC node to represent the
4620 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
4621 /// LHS, and the SDValue returned in RHS has a nil SDNode value.
4622 void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS,
4625 SDValue Tmp1, Tmp2, Tmp3, Result;
4627 switch (getTypeAction(LHS.getValueType())) {
4629 Tmp1 = LegalizeOp(LHS); // LHS
4630 Tmp2 = LegalizeOp(RHS); // RHS
4633 Tmp1 = PromoteOp(LHS); // LHS
4634 Tmp2 = PromoteOp(RHS); // RHS
4636 // If this is an FP compare, the operands have already been extended.
4637 if (LHS.getValueType().isInteger()) {
4638 MVT VT = LHS.getValueType();
4639 MVT NVT = TLI.getTypeToTransformTo(VT);
4641 // Otherwise, we have to insert explicit sign or zero extends. Note
4642 // that we could insert sign extends for ALL conditions, but zero extend
4643 // is cheaper on many machines (an AND instead of two shifts), so prefer
4645 switch (cast<CondCodeSDNode>(CC)->get()) {
4646 default: assert(0 && "Unknown integer comparison!");
4653 // ALL of these operations will work if we either sign or zero extend
4654 // the operands (including the unsigned comparisons!). Zero extend is
4655 // usually a simpler/cheaper operation, so prefer it.
4656 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4657 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4663 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4664 DAG.getValueType(VT));
4665 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4666 DAG.getValueType(VT));
4672 MVT VT = LHS.getValueType();
4673 if (VT == MVT::f32 || VT == MVT::f64) {
4674 // Expand into one or more soft-fp libcall(s).
4675 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
4676 switch (cast<CondCodeSDNode>(CC)->get()) {
4679 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4683 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
4687 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4691 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4695 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4699 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4702 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4705 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
4708 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4709 switch (cast<CondCodeSDNode>(CC)->get()) {
4711 // SETONE = SETOLT | SETOGT
4712 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4715 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4718 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4721 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4724 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4727 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4729 default: assert(0 && "Unsupported FP setcc!");
4734 SDValue Ops[2] = { LHS, RHS };
4735 Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2).getNode(),
4736 false /*sign irrelevant*/, Dummy);
4737 Tmp2 = DAG.getConstant(0, MVT::i32);
4738 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
4739 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
4740 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
4742 LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2).getNode(),
4743 false /*sign irrelevant*/, Dummy);
4744 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, Tmp2,
4745 DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
4746 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4749 LHS = LegalizeOp(Tmp1);
4754 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
4755 ExpandOp(LHS, LHSLo, LHSHi);
4756 ExpandOp(RHS, RHSLo, RHSHi);
4757 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
4759 if (VT==MVT::ppcf128) {
4760 // FIXME: This generated code sucks. We want to generate
4761 // FCMP crN, hi1, hi2
4763 // FCMP crN, lo1, lo2
4764 // The following can be improved, but not that much.
4765 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETEQ);
4766 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, CCCode);
4767 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4768 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETNE);
4769 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode);
4770 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4771 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
4780 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
4781 if (RHSCST->isAllOnesValue()) {
4782 // Comparison to -1.
4783 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
4788 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
4789 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
4790 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4791 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
4794 // If this is a comparison of the sign bit, just look at the top part.
4796 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
4797 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
4798 CST->isNullValue()) || // X < 0
4799 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
4800 CST->isAllOnesValue())) { // X > -1
4806 // FIXME: This generated code sucks.
4807 ISD::CondCode LowCC;
4809 default: assert(0 && "Unknown integer setcc!");
4811 case ISD::SETULT: LowCC = ISD::SETULT; break;
4813 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
4815 case ISD::SETULE: LowCC = ISD::SETULE; break;
4817 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
4820 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
4821 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
4822 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
4824 // NOTE: on targets without efficient SELECT of bools, we can always use
4825 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
4826 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
4827 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo,
4828 LowCC, false, DagCombineInfo);
4829 if (!Tmp1.getNode())
4830 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC);
4831 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4832 CCCode, false, DagCombineInfo);
4833 if (!Tmp2.getNode())
4834 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi,
4837 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
4838 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
4839 if ((Tmp1C && Tmp1C->isNullValue()) ||
4840 (Tmp2C && Tmp2C->isNullValue() &&
4841 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
4842 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
4843 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
4844 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
4845 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
4846 // low part is known false, returns high part.
4847 // For LE / GE, if high part is known false, ignore the low part.
4848 // For LT / GT, if high part is known true, ignore the low part.
4852 Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4853 ISD::SETEQ, false, DagCombineInfo);
4854 if (!Result.getNode())
4855 Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4857 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
4858 Result, Tmp1, Tmp2));
4869 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
4870 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
4871 /// a load from the stack slot to DestVT, extending it if needed.
4872 /// The resultant code need not be legal.
4873 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
4876 // Create the stack frame object.
4877 unsigned SrcAlign = TLI.getTargetData()->getPrefTypeAlignment(
4878 SrcOp.getValueType().getTypeForMVT());
4879 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
4881 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
4882 int SPFI = StackPtrFI->getIndex();
4884 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
4885 unsigned SlotSize = SlotVT.getSizeInBits();
4886 unsigned DestSize = DestVT.getSizeInBits();
4887 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(
4888 DestVT.getTypeForMVT());
4890 // Emit a store to the stack slot. Use a truncstore if the input value is
4891 // later than DestVT.
4894 if (SrcSize > SlotSize)
4895 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr,
4896 PseudoSourceValue::getFixedStack(SPFI), 0,
4897 SlotVT, false, SrcAlign);
4899 assert(SrcSize == SlotSize && "Invalid store");
4900 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr,
4901 PseudoSourceValue::getFixedStack(SPFI), 0,
4905 // Result is a load from the stack slot.
4906 if (SlotSize == DestSize)
4907 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0, false, DestAlign);
4909 assert(SlotSize < DestSize && "Unknown extension!");
4910 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT,
4914 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
4915 // Create a vector sized/aligned stack slot, store the value to element #0,
4916 // then load the whole vector back out.
4917 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
4919 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
4920 int SPFI = StackPtrFI->getIndex();
4922 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
4923 PseudoSourceValue::getFixedStack(SPFI), 0);
4924 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,
4925 PseudoSourceValue::getFixedStack(SPFI), 0);
4929 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
4930 /// support the operation, but do support the resultant vector type.
4931 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
4933 // If the only non-undef value is the low element, turn this into a
4934 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
4935 unsigned NumElems = Node->getNumOperands();
4936 bool isOnlyLowElement = true;
4937 SDValue SplatValue = Node->getOperand(0);
4939 // FIXME: it would be far nicer to change this into map<SDValue,uint64_t>
4940 // and use a bitmask instead of a list of elements.
4941 std::map<SDValue, std::vector<unsigned> > Values;
4942 Values[SplatValue].push_back(0);
4943 bool isConstant = true;
4944 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
4945 SplatValue.getOpcode() != ISD::UNDEF)
4948 for (unsigned i = 1; i < NumElems; ++i) {
4949 SDValue V = Node->getOperand(i);
4950 Values[V].push_back(i);
4951 if (V.getOpcode() != ISD::UNDEF)
4952 isOnlyLowElement = false;
4953 if (SplatValue != V)
4954 SplatValue = SDValue(0,0);
4956 // If this isn't a constant element or an undef, we can't use a constant
4958 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
4959 V.getOpcode() != ISD::UNDEF)
4963 if (isOnlyLowElement) {
4964 // If the low element is an undef too, then this whole things is an undef.
4965 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
4966 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
4967 // Otherwise, turn this into a scalar_to_vector node.
4968 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4969 Node->getOperand(0));
4972 // If all elements are constants, create a load from the constant pool.
4974 MVT VT = Node->getValueType(0);
4975 std::vector<Constant*> CV;
4976 for (unsigned i = 0, e = NumElems; i != e; ++i) {
4977 if (ConstantFPSDNode *V =
4978 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
4979 CV.push_back(ConstantFP::get(V->getValueAPF()));
4980 } else if (ConstantSDNode *V =
4981 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
4982 CV.push_back(ConstantInt::get(V->getAPIntValue()));
4984 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
4986 Node->getOperand(0).getValueType().getTypeForMVT();
4987 CV.push_back(UndefValue::get(OpNTy));
4990 Constant *CP = ConstantVector::get(CV);
4991 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
4992 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4993 PseudoSourceValue::getConstantPool(), 0);
4996 if (SplatValue.getNode()) { // Splat of one value?
4997 // Build the shuffle constant vector: <0, 0, 0, 0>
4998 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
4999 SDValue Zero = DAG.getConstant(0, MaskVT.getVectorElementType());
5000 std::vector<SDValue> ZeroVec(NumElems, Zero);
5001 SDValue SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
5002 &ZeroVec[0], ZeroVec.size());
5004 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
5005 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
5006 // Get the splatted value into the low element of a vector register.
5008 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
5010 // Return shuffle(LowValVec, undef, <0,0,0,0>)
5011 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
5012 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
5017 // If there are only two unique elements, we may be able to turn this into a
5019 if (Values.size() == 2) {
5020 // Get the two values in deterministic order.
5021 SDValue Val1 = Node->getOperand(1);
5023 std::map<SDValue, std::vector<unsigned> >::iterator MI = Values.begin();
5024 if (MI->first != Val1)
5027 Val2 = (++MI)->first;
5029 // If Val1 is an undef, make sure end ends up as Val2, to ensure that our
5030 // vector shuffle has the undef vector on the RHS.
5031 if (Val1.getOpcode() == ISD::UNDEF)
5032 std::swap(Val1, Val2);
5034 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
5035 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
5036 MVT MaskEltVT = MaskVT.getVectorElementType();
5037 std::vector<SDValue> MaskVec(NumElems);
5039 // Set elements of the shuffle mask for Val1.
5040 std::vector<unsigned> &Val1Elts = Values[Val1];
5041 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i)
5042 MaskVec[Val1Elts[i]] = DAG.getConstant(0, MaskEltVT);
5044 // Set elements of the shuffle mask for Val2.
5045 std::vector<unsigned> &Val2Elts = Values[Val2];
5046 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i)
5047 if (Val2.getOpcode() != ISD::UNDEF)
5048 MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT);
5050 MaskVec[Val2Elts[i]] = DAG.getNode(ISD::UNDEF, MaskEltVT);
5052 SDValue ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
5053 &MaskVec[0], MaskVec.size());
5055 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it.
5056 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
5057 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
5058 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val1);
5059 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val2);
5060 SDValue Ops[] = { Val1, Val2, ShuffleMask };
5062 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
5063 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops, 3);
5067 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
5068 // aligned object on the stack, store each element into it, then load
5069 // the result as a vector.
5070 MVT VT = Node->getValueType(0);
5071 // Create the stack frame object.
5072 SDValue FIPtr = DAG.CreateStackTemporary(VT);
5074 // Emit a store of each element to the stack slot.
5075 SmallVector<SDValue, 8> Stores;
5076 unsigned TypeByteSize = Node->getOperand(0).getValueType().getSizeInBits()/8;
5077 // Store (in the right endianness) the elements to memory.
5078 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5079 // Ignore undef elements.
5080 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
5082 unsigned Offset = TypeByteSize*i;
5084 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
5085 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
5087 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
5092 if (!Stores.empty()) // Not all undef elements?
5093 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
5094 &Stores[0], Stores.size());
5096 StoreChain = DAG.getEntryNode();
5098 // Result is a load from the stack slot.
5099 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
5102 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
5103 SDValue Op, SDValue Amt,
5104 SDValue &Lo, SDValue &Hi) {
5105 // Expand the subcomponents.
5107 ExpandOp(Op, LHSL, LHSH);
5109 SDValue Ops[] = { LHSL, LHSH, Amt };
5110 MVT VT = LHSL.getValueType();
5111 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
5112 Hi = Lo.getValue(1);
5116 /// ExpandShift - Try to find a clever way to expand this shift operation out to
5117 /// smaller elements. If we can't find a way that is more efficient than a
5118 /// libcall on this target, return false. Otherwise, return true with the
5119 /// low-parts expanded into Lo and Hi.
5120 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op,SDValue Amt,
5121 SDValue &Lo, SDValue &Hi) {
5122 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
5123 "This is not a shift!");
5125 MVT NVT = TLI.getTypeToTransformTo(Op.getValueType());
5126 SDValue ShAmt = LegalizeOp(Amt);
5127 MVT ShTy = ShAmt.getValueType();
5128 unsigned ShBits = ShTy.getSizeInBits();
5129 unsigned VTBits = Op.getValueType().getSizeInBits();
5130 unsigned NVTBits = NVT.getSizeInBits();
5132 // Handle the case when Amt is an immediate.
5133 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.getNode())) {
5134 unsigned Cst = CN->getValue();
5135 // Expand the incoming operand to be shifted, so that we have its parts
5137 ExpandOp(Op, InL, InH);
5141 Lo = DAG.getConstant(0, NVT);
5142 Hi = DAG.getConstant(0, NVT);
5143 } else if (Cst > NVTBits) {
5144 Lo = DAG.getConstant(0, NVT);
5145 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
5146 } else if (Cst == NVTBits) {
5147 Lo = DAG.getConstant(0, NVT);
5150 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
5151 Hi = DAG.getNode(ISD::OR, NVT,
5152 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
5153 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
5158 Lo = DAG.getConstant(0, NVT);
5159 Hi = DAG.getConstant(0, NVT);
5160 } else if (Cst > NVTBits) {
5161 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
5162 Hi = DAG.getConstant(0, NVT);
5163 } else if (Cst == NVTBits) {
5165 Hi = DAG.getConstant(0, NVT);
5167 Lo = DAG.getNode(ISD::OR, NVT,
5168 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5169 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5170 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
5175 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
5176 DAG.getConstant(NVTBits-1, ShTy));
5177 } else if (Cst > NVTBits) {
5178 Lo = DAG.getNode(ISD::SRA, NVT, InH,
5179 DAG.getConstant(Cst-NVTBits, ShTy));
5180 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5181 DAG.getConstant(NVTBits-1, ShTy));
5182 } else if (Cst == NVTBits) {
5184 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5185 DAG.getConstant(NVTBits-1, ShTy));
5187 Lo = DAG.getNode(ISD::OR, NVT,
5188 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5189 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5190 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
5196 // Okay, the shift amount isn't constant. However, if we can tell that it is
5197 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
5198 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
5199 APInt KnownZero, KnownOne;
5200 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
5202 // If we know that if any of the high bits of the shift amount are one, then
5203 // we can do this as a couple of simple shifts.
5204 if (KnownOne.intersects(Mask)) {
5205 // Mask out the high bit, which we know is set.
5206 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
5207 DAG.getConstant(~Mask, Amt.getValueType()));
5209 // Expand the incoming operand to be shifted, so that we have its parts
5211 ExpandOp(Op, InL, InH);
5214 Lo = DAG.getConstant(0, NVT); // Low part is zero.
5215 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
5218 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
5219 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
5222 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
5223 DAG.getConstant(NVTBits-1, Amt.getValueType()));
5224 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
5229 // If we know that the high bits of the shift amount are all zero, then we can
5230 // do this as a couple of simple shifts.
5231 if ((KnownZero & Mask) == Mask) {
5233 SDValue Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
5234 DAG.getConstant(NVTBits, Amt.getValueType()),
5237 // Expand the incoming operand to be shifted, so that we have its parts
5239 ExpandOp(Op, InL, InH);
5242 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
5243 Hi = DAG.getNode(ISD::OR, NVT,
5244 DAG.getNode(ISD::SHL, NVT, InH, Amt),
5245 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
5248 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
5249 Lo = DAG.getNode(ISD::OR, NVT,
5250 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5251 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5254 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
5255 Lo = DAG.getNode(ISD::OR, NVT,
5256 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5257 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5266 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
5267 // does not fit into a register, return the lo part and set the hi part to the
5268 // by-reg argument. If it does fit into a single register, return the result
5269 // and leave the Hi part unset.
5270 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
5271 bool isSigned, SDValue &Hi) {
5272 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
5273 // The input chain to this libcall is the entry node of the function.
5274 // Legalizing the call will automatically add the previous call to the
5276 SDValue InChain = DAG.getEntryNode();
5278 TargetLowering::ArgListTy Args;
5279 TargetLowering::ArgListEntry Entry;
5280 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5281 MVT ArgVT = Node->getOperand(i).getValueType();
5282 const Type *ArgTy = ArgVT.getTypeForMVT();
5283 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
5284 Entry.isSExt = isSigned;
5285 Entry.isZExt = !isSigned;
5286 Args.push_back(Entry);
5288 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
5289 TLI.getPointerTy());
5291 // Splice the libcall in wherever FindInputOutputChains tells us to.
5292 const Type *RetTy = Node->getValueType(0).getTypeForMVT();
5293 std::pair<SDValue,SDValue> CallInfo =
5294 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, CallingConv::C,
5295 false, Callee, Args, DAG);
5297 // Legalize the call sequence, starting with the chain. This will advance
5298 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
5299 // was added by LowerCallTo (guaranteeing proper serialization of calls).
5300 LegalizeOp(CallInfo.second);
5302 switch (getTypeAction(CallInfo.first.getValueType())) {
5303 default: assert(0 && "Unknown thing");
5305 Result = CallInfo.first;
5308 ExpandOp(CallInfo.first, Result, Hi);
5314 /// LegalizeINT_TO_FP - Legalize a [US]INT_TO_FP operation.
5316 SDValue SelectionDAGLegalize::
5317 LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op) {
5318 bool isCustom = false;
5320 switch (getTypeAction(Op.getValueType())) {
5322 switch (TLI.getOperationAction(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5323 Op.getValueType())) {
5324 default: assert(0 && "Unknown operation action!");
5325 case TargetLowering::Custom:
5328 case TargetLowering::Legal:
5329 Tmp1 = LegalizeOp(Op);
5330 if (Result.getNode())
5331 Result = DAG.UpdateNodeOperands(Result, Tmp1);
5333 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5336 Tmp1 = TLI.LowerOperation(Result, DAG);
5337 if (Tmp1.getNode()) Result = Tmp1;
5340 case TargetLowering::Expand:
5341 Result = ExpandLegalINT_TO_FP(isSigned, LegalizeOp(Op), DestTy);
5343 case TargetLowering::Promote:
5344 Result = PromoteLegalINT_TO_FP(LegalizeOp(Op), DestTy, isSigned);
5349 Result = ExpandIntToFP(isSigned, DestTy, Op);
5352 Tmp1 = PromoteOp(Op);
5354 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
5355 Tmp1, DAG.getValueType(Op.getValueType()));
5357 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
5360 if (Result.getNode())
5361 Result = DAG.UpdateNodeOperands(Result, Tmp1);
5363 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5365 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
5371 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
5373 SDValue SelectionDAGLegalize::
5374 ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source) {
5375 MVT SourceVT = Source.getValueType();
5376 bool ExpandSource = getTypeAction(SourceVT) == Expand;
5378 // Expand unsupported int-to-fp vector casts by unrolling them.
5379 if (DestTy.isVector()) {
5381 return LegalizeOp(UnrollVectorOp(Source));
5382 MVT DestEltTy = DestTy.getVectorElementType();
5383 if (DestTy.getVectorNumElements() == 1) {
5384 SDValue Scalar = ScalarizeVectorOp(Source);
5385 SDValue Result = LegalizeINT_TO_FP(SDValue(), isSigned,
5387 return DAG.getNode(ISD::BUILD_VECTOR, DestTy, Result);
5390 SplitVectorOp(Source, Lo, Hi);
5391 MVT SplitDestTy = MVT::getVectorVT(DestEltTy,
5392 DestTy.getVectorNumElements() / 2);
5393 SDValue LoResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, Lo);
5394 SDValue HiResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, Hi);
5395 return LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, DestTy, LoResult, HiResult));
5398 // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc.
5399 if (!isSigned && SourceVT != MVT::i32) {
5400 // The integer value loaded will be incorrectly if the 'sign bit' of the
5401 // incoming integer is set. To handle this, we dynamically test to see if
5402 // it is set, and, if so, add a fudge factor.
5406 ExpandOp(Source, Lo, Hi);
5407 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi);
5409 // The comparison for the sign bit will use the entire operand.
5413 // If this is unsigned, and not supported, first perform the conversion to
5414 // signed, then adjust the result if the sign bit is set.
5415 SDValue SignedConv = ExpandIntToFP(true, DestTy, Source);
5417 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
5418 DAG.getConstant(0, Hi.getValueType()),
5420 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5421 SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5422 SignSet, Four, Zero);
5423 uint64_t FF = 0x5f800000ULL;
5424 if (TLI.isLittleEndian()) FF <<= 32;
5425 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5427 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5428 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5430 if (DestTy == MVT::f32)
5431 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5432 PseudoSourceValue::getConstantPool(), 0);
5433 else if (DestTy.bitsGT(MVT::f32))
5434 // FIXME: Avoid the extend by construction the right constantpool?
5435 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
5437 PseudoSourceValue::getConstantPool(), 0,
5440 assert(0 && "Unexpected conversion");
5442 MVT SCVT = SignedConv.getValueType();
5443 if (SCVT != DestTy) {
5444 // Destination type needs to be expanded as well. The FADD now we are
5445 // constructing will be expanded into a libcall.
5446 if (SCVT.getSizeInBits() != DestTy.getSizeInBits()) {
5447 assert(SCVT.getSizeInBits() * 2 == DestTy.getSizeInBits());
5448 SignedConv = DAG.getNode(ISD::BUILD_PAIR, DestTy,
5449 SignedConv, SignedConv.getValue(1));
5451 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
5453 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
5456 // Check to see if the target has a custom way to lower this. If so, use it.
5457 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) {
5458 default: assert(0 && "This action not implemented for this operation!");
5459 case TargetLowering::Legal:
5460 case TargetLowering::Expand:
5461 break; // This case is handled below.
5462 case TargetLowering::Custom: {
5463 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
5466 return LegalizeOp(NV);
5467 break; // The target decided this was legal after all
5471 // Expand the source, then glue it back together for the call. We must expand
5472 // the source in case it is shared (this pass of legalize must traverse it).
5474 SDValue SrcLo, SrcHi;
5475 ExpandOp(Source, SrcLo, SrcHi);
5476 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, SrcLo, SrcHi);
5479 RTLIB::Libcall LC = isSigned ?
5480 RTLIB::getSINTTOFP(SourceVT, DestTy) :
5481 RTLIB::getUINTTOFP(SourceVT, DestTy);
5482 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unknown int value type");
5484 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
5486 SDValue Result = ExpandLibCall(LC, Source.getNode(), isSigned, HiPart);
5487 if (Result.getValueType() != DestTy && HiPart.getNode())
5488 Result = DAG.getNode(ISD::BUILD_PAIR, DestTy, Result, HiPart);
5492 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
5493 /// INT_TO_FP operation of the specified operand when the target requests that
5494 /// we expand it. At this point, we know that the result and operand types are
5495 /// legal for the target.
5496 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
5499 if (Op0.getValueType() == MVT::i32) {
5500 // simple 32-bit [signed|unsigned] integer to float/double expansion
5502 // Get the stack frame index of a 8 byte buffer.
5503 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
5505 // word offset constant for Hi/Lo address computation
5506 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
5507 // set up Hi and Lo (into buffer) address based on endian
5508 SDValue Hi = StackSlot;
5509 SDValue Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
5510 if (TLI.isLittleEndian())
5513 // if signed map to unsigned space
5516 // constant used to invert sign bit (signed to unsigned mapping)
5517 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
5518 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
5522 // store the lo of the constructed double - based on integer input
5523 SDValue Store1 = DAG.getStore(DAG.getEntryNode(),
5524 Op0Mapped, Lo, NULL, 0);
5525 // initial hi portion of constructed double
5526 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
5527 // store the hi of the constructed double - biased exponent
5528 SDValue Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
5529 // load the constructed double
5530 SDValue Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
5531 // FP constant to bias correct the final result
5532 SDValue Bias = DAG.getConstantFP(isSigned ?
5533 BitsToDouble(0x4330000080000000ULL)
5534 : BitsToDouble(0x4330000000000000ULL),
5536 // subtract the bias
5537 SDValue Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
5540 // handle final rounding
5541 if (DestVT == MVT::f64) {
5544 } else if (DestVT.bitsLT(MVT::f64)) {
5545 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub,
5546 DAG.getIntPtrConstant(0));
5547 } else if (DestVT.bitsGT(MVT::f64)) {
5548 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
5552 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
5553 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
5555 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Op0), Op0,
5556 DAG.getConstant(0, Op0.getValueType()),
5558 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5559 SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5560 SignSet, Four, Zero);
5562 // If the sign bit of the integer is set, the large number will be treated
5563 // as a negative number. To counteract this, the dynamic code adds an
5564 // offset depending on the data type.
5566 switch (Op0.getValueType().getSimpleVT()) {
5567 default: assert(0 && "Unsupported integer type!");
5568 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
5569 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
5570 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
5571 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
5573 if (TLI.isLittleEndian()) FF <<= 32;
5574 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5576 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5577 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5579 if (DestVT == MVT::f32)
5580 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5581 PseudoSourceValue::getConstantPool(), 0);
5584 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT,
5585 DAG.getEntryNode(), CPIdx,
5586 PseudoSourceValue::getConstantPool(), 0,
5590 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
5593 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
5594 /// *INT_TO_FP operation of the specified operand when the target requests that
5595 /// we promote it. At this point, we know that the result and operand types are
5596 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
5597 /// operation that takes a larger input.
5598 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
5601 // First step, figure out the appropriate *INT_TO_FP operation to use.
5602 MVT NewInTy = LegalOp.getValueType();
5604 unsigned OpToUse = 0;
5606 // Scan for the appropriate larger type to use.
5608 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
5609 assert(NewInTy.isInteger() && "Ran out of possibilities!");
5611 // If the target supports SINT_TO_FP of this type, use it.
5612 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
5614 case TargetLowering::Legal:
5615 if (!TLI.isTypeLegal(NewInTy))
5616 break; // Can't use this datatype.
5618 case TargetLowering::Custom:
5619 OpToUse = ISD::SINT_TO_FP;
5623 if (isSigned) continue;
5625 // If the target supports UINT_TO_FP of this type, use it.
5626 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
5628 case TargetLowering::Legal:
5629 if (!TLI.isTypeLegal(NewInTy))
5630 break; // Can't use this datatype.
5632 case TargetLowering::Custom:
5633 OpToUse = ISD::UINT_TO_FP;
5638 // Otherwise, try a larger type.
5641 // Okay, we found the operation and type to use. Zero extend our input to the
5642 // desired type then run the operation on it.
5643 return DAG.getNode(OpToUse, DestVT,
5644 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
5648 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
5649 /// FP_TO_*INT operation of the specified operand when the target requests that
5650 /// we promote it. At this point, we know that the result and operand types are
5651 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
5652 /// operation that returns a larger result.
5653 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
5656 // First step, figure out the appropriate FP_TO*INT operation to use.
5657 MVT NewOutTy = DestVT;
5659 unsigned OpToUse = 0;
5661 // Scan for the appropriate larger type to use.
5663 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1);
5664 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
5666 // If the target supports FP_TO_SINT returning this type, use it.
5667 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
5669 case TargetLowering::Legal:
5670 if (!TLI.isTypeLegal(NewOutTy))
5671 break; // Can't use this datatype.
5673 case TargetLowering::Custom:
5674 OpToUse = ISD::FP_TO_SINT;
5679 // If the target supports FP_TO_UINT of this type, use it.
5680 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
5682 case TargetLowering::Legal:
5683 if (!TLI.isTypeLegal(NewOutTy))
5684 break; // Can't use this datatype.
5686 case TargetLowering::Custom:
5687 OpToUse = ISD::FP_TO_UINT;
5692 // Otherwise, try a larger type.
5696 // Okay, we found the operation and type to use.
5697 SDValue Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp);
5699 // If the operation produces an invalid type, it must be custom lowered. Use
5700 // the target lowering hooks to expand it. Just keep the low part of the
5701 // expanded operation, we know that we're truncating anyway.
5702 if (getTypeAction(NewOutTy) == Expand) {
5703 Operation = SDValue(TLI.ReplaceNodeResults(Operation.getNode(), DAG), 0);
5704 assert(Operation.getNode() && "Didn't return anything");
5707 // Truncate the result of the extended FP_TO_*INT operation to the desired
5709 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation);
5712 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
5714 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op) {
5715 MVT VT = Op.getValueType();
5716 MVT SHVT = TLI.getShiftAmountTy();
5717 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
5718 switch (VT.getSimpleVT()) {
5719 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
5721 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5722 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5723 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
5725 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5726 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5727 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5728 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5729 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
5730 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
5731 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5732 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5733 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5735 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
5736 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
5737 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5738 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5739 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5740 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5741 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
5742 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
5743 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
5744 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
5745 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
5746 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
5747 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
5748 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
5749 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
5750 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
5751 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5752 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5753 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
5754 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5755 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
5759 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
5761 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op) {
5763 default: assert(0 && "Cannot expand this yet!");
5765 static const uint64_t mask[6] = {
5766 0x5555555555555555ULL, 0x3333333333333333ULL,
5767 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
5768 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
5770 MVT VT = Op.getValueType();
5771 MVT ShVT = TLI.getShiftAmountTy();
5772 unsigned len = VT.getSizeInBits();
5773 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5774 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
5775 SDValue Tmp2 = DAG.getConstant(mask[i], VT);
5776 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5777 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
5778 DAG.getNode(ISD::AND, VT,
5779 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
5784 // for now, we do this:
5785 // x = x | (x >> 1);
5786 // x = x | (x >> 2);
5788 // x = x | (x >>16);
5789 // x = x | (x >>32); // for 64-bit input
5790 // return popcount(~x);
5792 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
5793 MVT VT = Op.getValueType();
5794 MVT ShVT = TLI.getShiftAmountTy();
5795 unsigned len = VT.getSizeInBits();
5796 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5797 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5798 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
5800 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
5801 return DAG.getNode(ISD::CTPOP, VT, Op);
5804 // for now, we use: { return popcount(~x & (x - 1)); }
5805 // unless the target has ctlz but not ctpop, in which case we use:
5806 // { return 32 - nlz(~x & (x-1)); }
5807 // see also http://www.hackersdelight.org/HDcode/ntz.cc
5808 MVT VT = Op.getValueType();
5809 SDValue Tmp2 = DAG.getConstant(~0ULL, VT);
5810 SDValue Tmp3 = DAG.getNode(ISD::AND, VT,
5811 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
5812 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
5813 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
5814 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
5815 TLI.isOperationLegal(ISD::CTLZ, VT))
5816 return DAG.getNode(ISD::SUB, VT,
5817 DAG.getConstant(VT.getSizeInBits(), VT),
5818 DAG.getNode(ISD::CTLZ, VT, Tmp3));
5819 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
5824 /// ExpandOp - Expand the specified SDValue into its two component pieces
5825 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
5826 /// LegalizeNodes map is filled in for any results that are not expanded, the
5827 /// ExpandedNodes map is filled in for any results that are expanded, and the
5828 /// Lo/Hi values are returned.
5829 void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
5830 MVT VT = Op.getValueType();
5831 MVT NVT = TLI.getTypeToTransformTo(VT);
5832 SDNode *Node = Op.getNode();
5833 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
5834 assert(((NVT.isInteger() && NVT.bitsLT(VT)) || VT.isFloatingPoint() ||
5835 VT.isVector()) && "Cannot expand to FP value or to larger int value!");
5837 // See if we already expanded it.
5838 DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator I
5839 = ExpandedNodes.find(Op);
5840 if (I != ExpandedNodes.end()) {
5841 Lo = I->second.first;
5842 Hi = I->second.second;
5846 switch (Node->getOpcode()) {
5847 case ISD::CopyFromReg:
5848 assert(0 && "CopyFromReg must be legal!");
5849 case ISD::FP_ROUND_INREG:
5850 if (VT == MVT::ppcf128 &&
5851 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
5852 TargetLowering::Custom) {
5853 SDValue SrcLo, SrcHi, Src;
5854 ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
5855 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi);
5856 SDValue Result = TLI.LowerOperation(
5857 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG);
5858 assert(Result.getNode()->getOpcode() == ISD::BUILD_PAIR);
5859 Lo = Result.getNode()->getOperand(0);
5860 Hi = Result.getNode()->getOperand(1);
5866 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
5868 assert(0 && "Do not know how to expand this operator!");
5870 case ISD::EXTRACT_ELEMENT:
5871 ExpandOp(Node->getOperand(0), Lo, Hi);
5872 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
5873 return ExpandOp(Hi, Lo, Hi);
5874 return ExpandOp(Lo, Lo, Hi);
5875 case ISD::EXTRACT_VECTOR_ELT:
5876 assert(VT==MVT::i64 && "Do not know how to expand this operator!");
5877 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types.
5878 Lo = ExpandEXTRACT_VECTOR_ELT(Op);
5879 return ExpandOp(Lo, Lo, Hi);
5881 Lo = DAG.getNode(ISD::UNDEF, NVT);
5882 Hi = DAG.getNode(ISD::UNDEF, NVT);
5884 case ISD::Constant: {
5885 unsigned NVTBits = NVT.getSizeInBits();
5886 const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue();
5887 Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT);
5888 Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT);
5891 case ISD::ConstantFP: {
5892 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
5893 if (CFP->getValueType(0) == MVT::ppcf128) {
5894 APInt api = CFP->getValueAPF().convertToAPInt();
5895 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
5897 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
5901 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
5902 if (getTypeAction(Lo.getValueType()) == Expand)
5903 ExpandOp(Lo, Lo, Hi);
5906 case ISD::BUILD_PAIR:
5907 // Return the operands.
5908 Lo = Node->getOperand(0);
5909 Hi = Node->getOperand(1);
5912 case ISD::MERGE_VALUES:
5913 if (Node->getNumValues() == 1) {
5914 ExpandOp(Op.getOperand(0), Lo, Hi);
5917 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y)
5918 assert(Op.getResNo() == 0 && Node->getNumValues() == 2 &&
5919 Op.getValue(1).getValueType() == MVT::Other &&
5920 "unhandled MERGE_VALUES");
5921 ExpandOp(Op.getOperand(0), Lo, Hi);
5922 // Remember that we legalized the chain.
5923 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1)));
5926 case ISD::SIGN_EXTEND_INREG:
5927 ExpandOp(Node->getOperand(0), Lo, Hi);
5928 // sext_inreg the low part if needed.
5929 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
5931 // The high part gets the sign extension from the lo-part. This handles
5932 // things like sextinreg V:i64 from i8.
5933 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5934 DAG.getConstant(NVT.getSizeInBits()-1,
5935 TLI.getShiftAmountTy()));
5939 ExpandOp(Node->getOperand(0), Lo, Hi);
5940 SDValue TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
5941 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
5947 ExpandOp(Node->getOperand(0), Lo, Hi);
5948 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
5949 DAG.getNode(ISD::CTPOP, NVT, Lo),
5950 DAG.getNode(ISD::CTPOP, NVT, Hi));
5951 Hi = DAG.getConstant(0, NVT);
5955 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
5956 ExpandOp(Node->getOperand(0), Lo, Hi);
5957 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
5958 SDValue HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
5959 SDValue TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(HLZ), HLZ, BitsC,
5961 SDValue LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
5962 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
5964 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
5965 Hi = DAG.getConstant(0, NVT);
5970 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
5971 ExpandOp(Node->getOperand(0), Lo, Hi);
5972 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
5973 SDValue LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
5974 SDValue BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(LTZ), LTZ, BitsC,
5976 SDValue HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
5977 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
5979 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
5980 Hi = DAG.getConstant(0, NVT);
5985 SDValue Ch = Node->getOperand(0); // Legalize the chain.
5986 SDValue Ptr = Node->getOperand(1); // Legalize the pointer.
5987 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
5988 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
5990 // Remember that we legalized the chain.
5991 Hi = LegalizeOp(Hi);
5992 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
5993 if (TLI.isBigEndian())
5999 LoadSDNode *LD = cast<LoadSDNode>(Node);
6000 SDValue Ch = LD->getChain(); // Legalize the chain.
6001 SDValue Ptr = LD->getBasePtr(); // Legalize the pointer.
6002 ISD::LoadExtType ExtType = LD->getExtensionType();
6003 const Value *SV = LD->getSrcValue();
6004 int SVOffset = LD->getSrcValueOffset();
6005 unsigned Alignment = LD->getAlignment();
6006 bool isVolatile = LD->isVolatile();
6008 if (ExtType == ISD::NON_EXTLOAD) {
6009 Lo = DAG.getLoad(NVT, Ch, Ptr, SV, SVOffset,
6010 isVolatile, Alignment);
6011 if (VT == MVT::f32 || VT == MVT::f64) {
6012 // f32->i32 or f64->i64 one to one expansion.
6013 // Remember that we legalized the chain.
6014 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
6015 // Recursively expand the new load.
6016 if (getTypeAction(NVT) == Expand)
6017 ExpandOp(Lo, Lo, Hi);
6021 // Increment the pointer to the other half.
6022 unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8;
6023 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
6024 DAG.getIntPtrConstant(IncrementSize));
6025 SVOffset += IncrementSize;
6026 Alignment = MinAlign(Alignment, IncrementSize);
6027 Hi = DAG.getLoad(NVT, Ch, Ptr, SV, SVOffset,
6028 isVolatile, Alignment);
6030 // Build a factor node to remember that this load is independent of the
6032 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
6035 // Remember that we legalized the chain.
6036 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
6037 if (TLI.isBigEndian())
6040 MVT EVT = LD->getMemoryVT();
6042 if ((VT == MVT::f64 && EVT == MVT::f32) ||
6043 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
6044 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
6045 SDValue Load = DAG.getLoad(EVT, Ch, Ptr, SV,
6046 SVOffset, isVolatile, Alignment);
6047 // Remember that we legalized the chain.
6048 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Load.getValue(1)));
6049 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
6054 Lo = DAG.getLoad(NVT, Ch, Ptr, SV,
6055 SVOffset, isVolatile, Alignment);
6057 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, SV,
6058 SVOffset, EVT, isVolatile,
6061 // Remember that we legalized the chain.
6062 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
6064 if (ExtType == ISD::SEXTLOAD) {
6065 // The high part is obtained by SRA'ing all but one of the bits of the
6067 unsigned LoSize = Lo.getValueType().getSizeInBits();
6068 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6069 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6070 } else if (ExtType == ISD::ZEXTLOAD) {
6071 // The high part is just a zero.
6072 Hi = DAG.getConstant(0, NVT);
6073 } else /* if (ExtType == ISD::EXTLOAD) */ {
6074 // The high part is undefined.
6075 Hi = DAG.getNode(ISD::UNDEF, NVT);
6082 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
6083 SDValue LL, LH, RL, RH;
6084 ExpandOp(Node->getOperand(0), LL, LH);
6085 ExpandOp(Node->getOperand(1), RL, RH);
6086 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
6087 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
6091 SDValue LL, LH, RL, RH;
6092 ExpandOp(Node->getOperand(1), LL, LH);
6093 ExpandOp(Node->getOperand(2), RL, RH);
6094 if (getTypeAction(NVT) == Expand)
6095 NVT = TLI.getTypeToExpandTo(NVT);
6096 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
6098 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
6101 case ISD::SELECT_CC: {
6102 SDValue TL, TH, FL, FH;
6103 ExpandOp(Node->getOperand(2), TL, TH);
6104 ExpandOp(Node->getOperand(3), FL, FH);
6105 if (getTypeAction(NVT) == Expand)
6106 NVT = TLI.getTypeToExpandTo(NVT);
6107 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
6108 Node->getOperand(1), TL, FL, Node->getOperand(4));
6110 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
6111 Node->getOperand(1), TH, FH, Node->getOperand(4));
6114 case ISD::ANY_EXTEND:
6115 // The low part is any extension of the input (which degenerates to a copy).
6116 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
6117 // The high part is undefined.
6118 Hi = DAG.getNode(ISD::UNDEF, NVT);
6120 case ISD::SIGN_EXTEND: {
6121 // The low part is just a sign extension of the input (which degenerates to
6123 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
6125 // The high part is obtained by SRA'ing all but one of the bits of the lo
6127 unsigned LoSize = Lo.getValueType().getSizeInBits();
6128 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6129 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6132 case ISD::ZERO_EXTEND:
6133 // The low part is just a zero extension of the input (which degenerates to
6135 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
6137 // The high part is just a zero.
6138 Hi = DAG.getConstant(0, NVT);
6141 case ISD::TRUNCATE: {
6142 // The input value must be larger than this value. Expand *it*.
6144 ExpandOp(Node->getOperand(0), NewLo, Hi);
6146 // The low part is now either the right size, or it is closer. If not the
6147 // right size, make an illegal truncate so we recursively expand it.
6148 if (NewLo.getValueType() != Node->getValueType(0))
6149 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
6150 ExpandOp(NewLo, Lo, Hi);
6154 case ISD::BIT_CONVERT: {
6156 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
6157 // If the target wants to, allow it to lower this itself.
6158 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6159 case Expand: assert(0 && "cannot expand FP!");
6160 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
6161 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
6163 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
6166 // f32 / f64 must be expanded to i32 / i64.
6167 if (VT == MVT::f32 || VT == MVT::f64) {
6168 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6169 if (getTypeAction(NVT) == Expand)
6170 ExpandOp(Lo, Lo, Hi);
6174 // If source operand will be expanded to the same type as VT, i.e.
6175 // i64 <- f64, i32 <- f32, expand the source operand instead.
6176 MVT VT0 = Node->getOperand(0).getValueType();
6177 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
6178 ExpandOp(Node->getOperand(0), Lo, Hi);
6182 // Turn this into a load/store pair by default.
6183 if (Tmp.getNode() == 0)
6184 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT);
6186 ExpandOp(Tmp, Lo, Hi);
6190 case ISD::READCYCLECOUNTER: {
6191 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
6192 TargetLowering::Custom &&
6193 "Must custom expand ReadCycleCounter");
6194 SDValue Tmp = TLI.LowerOperation(Op, DAG);
6195 assert(Tmp.getNode() && "Node must be custom expanded!");
6196 ExpandOp(Tmp.getValue(0), Lo, Hi);
6197 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6198 LegalizeOp(Tmp.getValue(1)));
6202 // FIXME: should the LOAD_BIN and SWAP atomics get here too? Probably.
6203 case ISD::ATOMIC_CMP_SWAP_8:
6204 case ISD::ATOMIC_CMP_SWAP_16:
6205 case ISD::ATOMIC_CMP_SWAP_32:
6206 case ISD::ATOMIC_CMP_SWAP_64: {
6207 SDValue Tmp = TLI.LowerOperation(Op, DAG);
6208 assert(Tmp.getNode() && "Node must be custom expanded!");
6209 ExpandOp(Tmp.getValue(0), Lo, Hi);
6210 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6211 LegalizeOp(Tmp.getValue(1)));
6217 // These operators cannot be expanded directly, emit them as calls to
6218 // library functions.
6219 case ISD::FP_TO_SINT: {
6220 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
6222 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6223 case Expand: assert(0 && "cannot expand FP!");
6224 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6225 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6228 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
6230 // Now that the custom expander is done, expand the result, which is still
6233 ExpandOp(Op, Lo, Hi);
6238 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Node->getOperand(0).getValueType(),
6240 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected uint-to-fp conversion!");
6241 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6245 case ISD::FP_TO_UINT: {
6246 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
6248 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6249 case Expand: assert(0 && "cannot expand FP!");
6250 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6251 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6254 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
6256 // Now that the custom expander is done, expand the result.
6258 ExpandOp(Op, Lo, Hi);
6263 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Node->getOperand(0).getValueType(),
6265 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
6266 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6271 // If the target wants custom lowering, do so.
6272 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6273 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
6274 SDValue Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
6275 Op = TLI.LowerOperation(Op, DAG);
6277 // Now that the custom expander is done, expand the result, which is
6279 ExpandOp(Op, Lo, Hi);
6284 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
6285 // this X << 1 as X+X.
6286 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
6287 if (ShAmt->getAPIntValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
6288 TLI.isOperationLegal(ISD::ADDE, NVT)) {
6289 SDValue LoOps[2], HiOps[3];
6290 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
6291 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
6292 LoOps[1] = LoOps[0];
6293 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6295 HiOps[1] = HiOps[0];
6296 HiOps[2] = Lo.getValue(1);
6297 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6302 // If we can emit an efficient shift operation, do so now.
6303 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6306 // If this target supports SHL_PARTS, use it.
6307 TargetLowering::LegalizeAction Action =
6308 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
6309 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6310 Action == TargetLowering::Custom) {
6311 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6315 // Otherwise, emit a libcall.
6316 Lo = ExpandLibCall(RTLIB::SHL_I64, Node, false/*left shift=unsigned*/, Hi);
6321 // If the target wants custom lowering, do so.
6322 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6323 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
6324 SDValue Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
6325 Op = TLI.LowerOperation(Op, DAG);
6327 // Now that the custom expander is done, expand the result, which is
6329 ExpandOp(Op, Lo, Hi);
6334 // If we can emit an efficient shift operation, do so now.
6335 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
6338 // If this target supports SRA_PARTS, use it.
6339 TargetLowering::LegalizeAction Action =
6340 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
6341 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6342 Action == TargetLowering::Custom) {
6343 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6347 // Otherwise, emit a libcall.
6348 Lo = ExpandLibCall(RTLIB::SRA_I64, Node, true/*ashr is signed*/, Hi);
6353 // If the target wants custom lowering, do so.
6354 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6355 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
6356 SDValue Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
6357 Op = TLI.LowerOperation(Op, DAG);
6359 // Now that the custom expander is done, expand the result, which is
6361 ExpandOp(Op, Lo, Hi);
6366 // If we can emit an efficient shift operation, do so now.
6367 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6370 // If this target supports SRL_PARTS, use it.
6371 TargetLowering::LegalizeAction Action =
6372 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
6373 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6374 Action == TargetLowering::Custom) {
6375 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6379 // Otherwise, emit a libcall.
6380 Lo = ExpandLibCall(RTLIB::SRL_I64, Node, false/*lshr is unsigned*/, Hi);
6386 // If the target wants to custom expand this, let them.
6387 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
6388 TargetLowering::Custom) {
6389 SDValue Result = TLI.LowerOperation(Op, DAG);
6390 if (Result.getNode()) {
6391 ExpandOp(Result, Lo, Hi);
6396 // Expand the subcomponents.
6397 SDValue LHSL, LHSH, RHSL, RHSH;
6398 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6399 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6400 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6401 SDValue LoOps[2], HiOps[3];
6406 if (Node->getOpcode() == ISD::ADD) {
6407 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6408 HiOps[2] = Lo.getValue(1);
6409 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6411 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6412 HiOps[2] = Lo.getValue(1);
6413 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6420 // Expand the subcomponents.
6421 SDValue LHSL, LHSH, RHSL, RHSH;
6422 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6423 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6424 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6425 SDValue LoOps[2] = { LHSL, RHSL };
6426 SDValue HiOps[3] = { LHSH, RHSH };
6428 if (Node->getOpcode() == ISD::ADDC) {
6429 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6430 HiOps[2] = Lo.getValue(1);
6431 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6433 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6434 HiOps[2] = Lo.getValue(1);
6435 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6437 // Remember that we legalized the flag.
6438 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6443 // Expand the subcomponents.
6444 SDValue LHSL, LHSH, RHSL, RHSH;
6445 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6446 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6447 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6448 SDValue LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
6449 SDValue HiOps[3] = { LHSH, RHSH };
6451 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
6452 HiOps[2] = Lo.getValue(1);
6453 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
6455 // Remember that we legalized the flag.
6456 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6460 // If the target wants to custom expand this, let them.
6461 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
6462 SDValue New = TLI.LowerOperation(Op, DAG);
6463 if (New.getNode()) {
6464 ExpandOp(New, Lo, Hi);
6469 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
6470 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
6471 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
6472 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
6473 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
6474 SDValue LL, LH, RL, RH;
6475 ExpandOp(Node->getOperand(0), LL, LH);
6476 ExpandOp(Node->getOperand(1), RL, RH);
6477 unsigned OuterBitSize = Op.getValueSizeInBits();
6478 unsigned InnerBitSize = RH.getValueSizeInBits();
6479 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
6480 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
6481 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
6482 if (DAG.MaskedValueIsZero(Node->getOperand(0), HighMask) &&
6483 DAG.MaskedValueIsZero(Node->getOperand(1), HighMask)) {
6484 // The inputs are both zero-extended.
6486 // We can emit a umul_lohi.
6487 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6488 Hi = SDValue(Lo.getNode(), 1);
6492 // We can emit a mulhu+mul.
6493 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6494 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6498 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
6499 // The input values are both sign-extended.
6501 // We can emit a smul_lohi.
6502 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6503 Hi = SDValue(Lo.getNode(), 1);
6507 // We can emit a mulhs+mul.
6508 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6509 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
6514 // Lo,Hi = umul LHS, RHS.
6515 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
6516 DAG.getVTList(NVT, NVT), LL, RL);
6518 Hi = UMulLOHI.getValue(1);
6519 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6520 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6521 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6522 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6526 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6527 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6528 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6529 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6530 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6531 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6536 // If nothing else, we can make a libcall.
6537 Lo = ExpandLibCall(RTLIB::MUL_I64, Node, false/*sign irrelevant*/, Hi);
6541 Lo = ExpandLibCall(RTLIB::SDIV_I64, Node, true, Hi);
6544 Lo = ExpandLibCall(RTLIB::UDIV_I64, Node, true, Hi);
6547 Lo = ExpandLibCall(RTLIB::SREM_I64, Node, true, Hi);
6550 Lo = ExpandLibCall(RTLIB::UREM_I64, Node, true, Hi);
6554 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::ADD_F32,
6557 RTLIB::ADD_PPCF128),
6561 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::SUB_F32,
6564 RTLIB::SUB_PPCF128),
6568 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::MUL_F32,
6571 RTLIB::MUL_PPCF128),
6575 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::DIV_F32,
6578 RTLIB::DIV_PPCF128),
6581 case ISD::FP_EXTEND: {
6582 if (VT == MVT::ppcf128) {
6583 assert(Node->getOperand(0).getValueType()==MVT::f32 ||
6584 Node->getOperand(0).getValueType()==MVT::f64);
6585 const uint64_t zero = 0;
6586 if (Node->getOperand(0).getValueType()==MVT::f32)
6587 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0));
6589 Hi = Node->getOperand(0);
6590 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6593 RTLIB::Libcall LC = RTLIB::getFPEXT(Node->getOperand(0).getValueType(), VT);
6594 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!");
6595 Lo = ExpandLibCall(LC, Node, true, Hi);
6598 case ISD::FP_ROUND: {
6599 RTLIB::Libcall LC = RTLIB::getFPROUND(Node->getOperand(0).getValueType(),
6601 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!");
6602 Lo = ExpandLibCall(LC, Node, true, Hi);
6606 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::POWI_F32,
6609 RTLIB::POWI_PPCF128),
6621 case ISD::FNEARBYINT:
6625 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6626 switch(Node->getOpcode()) {
6628 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
6629 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
6632 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
6633 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
6636 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
6637 RTLIB::COS_F80, RTLIB::COS_PPCF128);
6640 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
6641 RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
6644 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
6645 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
6648 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
6649 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
6652 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
6653 RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
6656 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
6657 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
6660 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
6661 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
6664 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
6665 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128);
6668 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
6669 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128);
6672 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64,
6673 RTLIB::RINT_F80, RTLIB::RINT_PPCF128);
6675 case ISD::FNEARBYINT:
6676 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
6677 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
6679 default: assert(0 && "Unreachable!");
6681 Lo = ExpandLibCall(LC, Node, false, Hi);
6685 if (VT == MVT::ppcf128) {
6687 ExpandOp(Node->getOperand(0), Lo, Tmp);
6688 Hi = DAG.getNode(ISD::FABS, NVT, Tmp);
6689 // lo = hi==fabs(hi) ? lo : -lo;
6690 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp,
6691 Lo, DAG.getNode(ISD::FNEG, NVT, Lo),
6692 DAG.getCondCode(ISD::SETEQ));
6695 SDValue Mask = (VT == MVT::f64)
6696 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
6697 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
6698 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6699 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6700 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
6701 if (getTypeAction(NVT) == Expand)
6702 ExpandOp(Lo, Lo, Hi);
6706 if (VT == MVT::ppcf128) {
6707 ExpandOp(Node->getOperand(0), Lo, Hi);
6708 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo);
6709 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi);
6712 SDValue Mask = (VT == MVT::f64)
6713 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
6714 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
6715 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6716 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6717 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
6718 if (getTypeAction(NVT) == Expand)
6719 ExpandOp(Lo, Lo, Hi);
6722 case ISD::FCOPYSIGN: {
6723 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
6724 if (getTypeAction(NVT) == Expand)
6725 ExpandOp(Lo, Lo, Hi);
6728 case ISD::SINT_TO_FP:
6729 case ISD::UINT_TO_FP: {
6730 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
6731 MVT SrcVT = Node->getOperand(0).getValueType();
6733 // Promote the operand if needed. Do this before checking for
6734 // ppcf128 so conversions of i16 and i8 work.
6735 if (getTypeAction(SrcVT) == Promote) {
6736 SDValue Tmp = PromoteOp(Node->getOperand(0));
6738 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
6739 DAG.getValueType(SrcVT))
6740 : DAG.getZeroExtendInReg(Tmp, SrcVT);
6741 Node = DAG.UpdateNodeOperands(Op, Tmp).getNode();
6742 SrcVT = Node->getOperand(0).getValueType();
6745 if (VT == MVT::ppcf128 && SrcVT == MVT::i32) {
6746 static const uint64_t zero = 0;
6748 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6749 Node->getOperand(0)));
6750 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6752 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
6753 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6754 Node->getOperand(0)));
6755 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6756 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6757 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
6758 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6759 DAG.getConstant(0, MVT::i32),
6760 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6762 APFloat(APInt(128, 2, TwoE32)),
6765 DAG.getCondCode(ISD::SETLT)),
6770 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) {
6771 // si64->ppcf128 done by libcall, below
6772 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
6773 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)),
6775 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6776 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
6777 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6778 DAG.getConstant(0, MVT::i64),
6779 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6781 APFloat(APInt(128, 2, TwoE64)),
6784 DAG.getCondCode(ISD::SETLT)),
6789 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
6790 Node->getOperand(0));
6791 if (getTypeAction(Lo.getValueType()) == Expand)
6792 // float to i32 etc. can be 'expanded' to a single node.
6793 ExpandOp(Lo, Lo, Hi);
6798 // Make sure the resultant values have been legalized themselves, unless this
6799 // is a type that requires multi-step expansion.
6800 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
6801 Lo = LegalizeOp(Lo);
6803 // Don't legalize the high part if it is expanded to a single node.
6804 Hi = LegalizeOp(Hi);
6807 // Remember in a map if the values will be reused later.
6809 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
6810 assert(isNew && "Value already expanded?!?");
6813 /// SplitVectorOp - Given an operand of vector type, break it down into
6814 /// two smaller values, still of vector type.
6815 void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
6817 assert(Op.getValueType().isVector() && "Cannot split non-vector type!");
6818 SDNode *Node = Op.getNode();
6819 unsigned NumElements = Op.getValueType().getVectorNumElements();
6820 assert(NumElements > 1 && "Cannot split a single element vector!");
6822 MVT NewEltVT = Op.getValueType().getVectorElementType();
6824 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
6825 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
6827 MVT NewVT_Lo = MVT::getVectorVT(NewEltVT, NewNumElts_Lo);
6828 MVT NewVT_Hi = MVT::getVectorVT(NewEltVT, NewNumElts_Hi);
6830 // See if we already split it.
6831 std::map<SDValue, std::pair<SDValue, SDValue> >::iterator I
6832 = SplitNodes.find(Op);
6833 if (I != SplitNodes.end()) {
6834 Lo = I->second.first;
6835 Hi = I->second.second;
6839 switch (Node->getOpcode()) {
6844 assert(0 && "Unhandled operation in SplitVectorOp!");
6846 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo);
6847 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi);
6849 case ISD::BUILD_PAIR:
6850 Lo = Node->getOperand(0);
6851 Hi = Node->getOperand(1);
6853 case ISD::INSERT_VECTOR_ELT: {
6854 if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) {
6855 SplitVectorOp(Node->getOperand(0), Lo, Hi);
6856 unsigned Index = Idx->getValue();
6857 SDValue ScalarOp = Node->getOperand(1);
6858 if (Index < NewNumElts_Lo)
6859 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp,
6860 DAG.getIntPtrConstant(Index));
6862 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp,
6863 DAG.getIntPtrConstant(Index - NewNumElts_Lo));
6866 SDValue Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0),
6867 Node->getOperand(1),
6868 Node->getOperand(2));
6869 SplitVectorOp(Tmp, Lo, Hi);
6872 case ISD::VECTOR_SHUFFLE: {
6873 // Build the low part.
6874 SDValue Mask = Node->getOperand(2);
6875 SmallVector<SDValue, 8> Ops;
6876 MVT PtrVT = TLI.getPointerTy();
6878 // Insert all of the elements from the input that are needed. We use
6879 // buildvector of extractelement here because the input vectors will have
6880 // to be legalized, so this makes the code simpler.
6881 for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
6882 SDValue IdxNode = Mask.getOperand(i);
6883 if (IdxNode.getOpcode() == ISD::UNDEF) {
6884 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
6887 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getValue();
6888 SDValue InVec = Node->getOperand(0);
6889 if (Idx >= NumElements) {
6890 InVec = Node->getOperand(1);
6893 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6894 DAG.getConstant(Idx, PtrVT)));
6896 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6899 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
6900 SDValue IdxNode = Mask.getOperand(i);
6901 if (IdxNode.getOpcode() == ISD::UNDEF) {
6902 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
6905 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getValue();
6906 SDValue InVec = Node->getOperand(0);
6907 if (Idx >= NumElements) {
6908 InVec = Node->getOperand(1);
6911 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6912 DAG.getConstant(Idx, PtrVT)));
6914 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &Ops[0], Ops.size());
6917 case ISD::BUILD_VECTOR: {
6918 SmallVector<SDValue, 8> LoOps(Node->op_begin(),
6919 Node->op_begin()+NewNumElts_Lo);
6920 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size());
6922 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
6924 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size());
6927 case ISD::CONCAT_VECTORS: {
6928 // FIXME: Handle non-power-of-two vectors?
6929 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
6930 if (NewNumSubvectors == 1) {
6931 Lo = Node->getOperand(0);
6932 Hi = Node->getOperand(1);
6934 SmallVector<SDValue, 8> LoOps(Node->op_begin(),
6935 Node->op_begin()+NewNumSubvectors);
6936 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size());
6938 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumSubvectors,
6940 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size());
6945 SDValue Cond = Node->getOperand(0);
6947 SDValue LL, LH, RL, RH;
6948 SplitVectorOp(Node->getOperand(1), LL, LH);
6949 SplitVectorOp(Node->getOperand(2), RL, RH);
6951 if (Cond.getValueType().isVector()) {
6952 // Handle a vector merge.
6954 SplitVectorOp(Cond, CL, CH);
6955 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL);
6956 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH);
6958 // Handle a simple select with vector operands.
6959 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL);
6960 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH);
6964 case ISD::SELECT_CC: {
6965 SDValue CondLHS = Node->getOperand(0);
6966 SDValue CondRHS = Node->getOperand(1);
6967 SDValue CondCode = Node->getOperand(4);
6969 SDValue LL, LH, RL, RH;
6970 SplitVectorOp(Node->getOperand(2), LL, LH);
6971 SplitVectorOp(Node->getOperand(3), RL, RH);
6973 // Handle a simple select with vector operands.
6974 Lo = DAG.getNode(ISD::SELECT_CC, NewVT_Lo, CondLHS, CondRHS,
6976 Hi = DAG.getNode(ISD::SELECT_CC, NewVT_Hi, CondLHS, CondRHS,
6981 SDValue LL, LH, RL, RH;
6982 SplitVectorOp(Node->getOperand(0), LL, LH);
6983 SplitVectorOp(Node->getOperand(1), RL, RH);
6984 Lo = DAG.getNode(ISD::VSETCC, NewVT_Lo, LL, RL, Node->getOperand(2));
6985 Hi = DAG.getNode(ISD::VSETCC, NewVT_Hi, LH, RH, Node->getOperand(2));
7004 SDValue LL, LH, RL, RH;
7005 SplitVectorOp(Node->getOperand(0), LL, LH);
7006 SplitVectorOp(Node->getOperand(1), RL, RH);
7008 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL);
7009 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH);
7015 SplitVectorOp(Node->getOperand(0), L, H);
7017 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1));
7018 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1));
7034 case ISD::FP_TO_SINT:
7035 case ISD::FP_TO_UINT:
7036 case ISD::SINT_TO_FP:
7037 case ISD::UINT_TO_FP:
7039 case ISD::ANY_EXTEND:
7040 case ISD::SIGN_EXTEND:
7041 case ISD::ZERO_EXTEND:
7042 case ISD::FP_EXTEND: {
7044 SplitVectorOp(Node->getOperand(0), L, H);
7046 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L);
7047 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H);
7051 LoadSDNode *LD = cast<LoadSDNode>(Node);
7052 SDValue Ch = LD->getChain();
7053 SDValue Ptr = LD->getBasePtr();
7054 ISD::LoadExtType ExtType = LD->getExtensionType();
7055 const Value *SV = LD->getSrcValue();
7056 int SVOffset = LD->getSrcValueOffset();
7057 MVT MemoryVT = LD->getMemoryVT();
7058 unsigned Alignment = LD->getAlignment();
7059 bool isVolatile = LD->isVolatile();
7061 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
7062 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType());
7064 MVT MemNewEltVT = MemoryVT.getVectorElementType();
7065 MVT MemNewVT_Lo = MVT::getVectorVT(MemNewEltVT, NewNumElts_Lo);
7066 MVT MemNewVT_Hi = MVT::getVectorVT(MemNewEltVT, NewNumElts_Hi);
7068 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType,
7069 NewVT_Lo, Ch, Ptr, Offset,
7070 SV, SVOffset, MemNewVT_Lo, isVolatile, Alignment);
7071 unsigned IncrementSize = NewNumElts_Lo * MemNewEltVT.getSizeInBits()/8;
7072 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
7073 DAG.getIntPtrConstant(IncrementSize));
7074 SVOffset += IncrementSize;
7075 Alignment = MinAlign(Alignment, IncrementSize);
7076 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType,
7077 NewVT_Hi, Ch, Ptr, Offset,
7078 SV, SVOffset, MemNewVT_Hi, isVolatile, Alignment);
7080 // Build a factor node to remember that this load is independent of the
7082 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
7085 // Remember that we legalized the chain.
7086 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
7089 case ISD::BIT_CONVERT: {
7090 // We know the result is a vector. The input may be either a vector or a
7092 SDValue InOp = Node->getOperand(0);
7093 if (!InOp.getValueType().isVector() ||
7094 InOp.getValueType().getVectorNumElements() == 1) {
7095 // The input is a scalar or single-element vector.
7096 // Lower to a store/load so that it can be split.
7097 // FIXME: this could be improved probably.
7098 unsigned LdAlign = TLI.getTargetData()->getPrefTypeAlignment(
7099 Op.getValueType().getTypeForMVT());
7100 SDValue Ptr = DAG.CreateStackTemporary(InOp.getValueType(), LdAlign);
7101 int FI = cast<FrameIndexSDNode>(Ptr.getNode())->getIndex();
7103 SDValue St = DAG.getStore(DAG.getEntryNode(),
7105 PseudoSourceValue::getFixedStack(FI), 0);
7106 InOp = DAG.getLoad(Op.getValueType(), St, Ptr,
7107 PseudoSourceValue::getFixedStack(FI), 0);
7109 // Split the vector and convert each of the pieces now.
7110 SplitVectorOp(InOp, Lo, Hi);
7111 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo);
7112 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi);
7117 // Remember in a map if the values will be reused later.
7119 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
7120 assert(isNew && "Value already split?!?");
7124 /// ScalarizeVectorOp - Given an operand of single-element vector type
7125 /// (e.g. v1f32), convert it into the equivalent operation that returns a
7126 /// scalar (e.g. f32) value.
7127 SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) {
7128 assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!");
7129 SDNode *Node = Op.getNode();
7130 MVT NewVT = Op.getValueType().getVectorElementType();
7131 assert(Op.getValueType().getVectorNumElements() == 1);
7133 // See if we already scalarized it.
7134 std::map<SDValue, SDValue>::iterator I = ScalarizedNodes.find(Op);
7135 if (I != ScalarizedNodes.end()) return I->second;
7138 switch (Node->getOpcode()) {
7141 Node->dump(&DAG); cerr << "\n";
7143 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
7160 Result = DAG.getNode(Node->getOpcode(),
7162 ScalarizeVectorOp(Node->getOperand(0)),
7163 ScalarizeVectorOp(Node->getOperand(1)));
7175 case ISD::FP_TO_SINT:
7176 case ISD::FP_TO_UINT:
7177 case ISD::SINT_TO_FP:
7178 case ISD::UINT_TO_FP:
7179 case ISD::SIGN_EXTEND:
7180 case ISD::ZERO_EXTEND:
7181 case ISD::ANY_EXTEND:
7183 case ISD::FP_EXTEND:
7184 Result = DAG.getNode(Node->getOpcode(),
7186 ScalarizeVectorOp(Node->getOperand(0)));
7190 Result = DAG.getNode(Node->getOpcode(),
7192 ScalarizeVectorOp(Node->getOperand(0)),
7193 Node->getOperand(1));
7196 LoadSDNode *LD = cast<LoadSDNode>(Node);
7197 SDValue Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
7198 SDValue Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
7199 ISD::LoadExtType ExtType = LD->getExtensionType();
7200 const Value *SV = LD->getSrcValue();
7201 int SVOffset = LD->getSrcValueOffset();
7202 MVT MemoryVT = LD->getMemoryVT();
7203 unsigned Alignment = LD->getAlignment();
7204 bool isVolatile = LD->isVolatile();
7206 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
7207 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType());
7209 Result = DAG.getLoad(ISD::UNINDEXED, ExtType,
7210 NewVT, Ch, Ptr, Offset, SV, SVOffset,
7211 MemoryVT.getVectorElementType(),
7212 isVolatile, Alignment);
7214 // Remember that we legalized the chain.
7215 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
7218 case ISD::BUILD_VECTOR:
7219 Result = Node->getOperand(0);
7221 case ISD::INSERT_VECTOR_ELT:
7222 // Returning the inserted scalar element.
7223 Result = Node->getOperand(1);
7225 case ISD::CONCAT_VECTORS:
7226 assert(Node->getOperand(0).getValueType() == NewVT &&
7227 "Concat of non-legal vectors not yet supported!");
7228 Result = Node->getOperand(0);
7230 case ISD::VECTOR_SHUFFLE: {
7231 // Figure out if the scalar is the LHS or RHS and return it.
7232 SDValue EltNum = Node->getOperand(2).getOperand(0);
7233 if (cast<ConstantSDNode>(EltNum)->getValue())
7234 Result = ScalarizeVectorOp(Node->getOperand(1));
7236 Result = ScalarizeVectorOp(Node->getOperand(0));
7239 case ISD::EXTRACT_SUBVECTOR:
7240 Result = Node->getOperand(0);
7241 assert(Result.getValueType() == NewVT);
7243 case ISD::BIT_CONVERT: {
7244 SDValue Op0 = Op.getOperand(0);
7245 if (Op0.getValueType().getVectorNumElements() == 1)
7246 Op0 = ScalarizeVectorOp(Op0);
7247 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op0);
7251 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
7252 ScalarizeVectorOp(Op.getOperand(1)),
7253 ScalarizeVectorOp(Op.getOperand(2)));
7255 case ISD::SELECT_CC:
7256 Result = DAG.getNode(ISD::SELECT_CC, NewVT, Node->getOperand(0),
7257 Node->getOperand(1),
7258 ScalarizeVectorOp(Op.getOperand(2)),
7259 ScalarizeVectorOp(Op.getOperand(3)),
7260 Node->getOperand(4));
7263 SDValue Op0 = ScalarizeVectorOp(Op.getOperand(0));
7264 SDValue Op1 = ScalarizeVectorOp(Op.getOperand(1));
7265 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Op0), Op0, Op1,
7267 Result = DAG.getNode(ISD::SELECT, NewVT, Result,
7268 DAG.getConstant(-1ULL, NewVT),
7269 DAG.getConstant(0ULL, NewVT));
7274 if (TLI.isTypeLegal(NewVT))
7275 Result = LegalizeOp(Result);
7276 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
7277 assert(isNew && "Value already scalarized?");
7282 // SelectionDAG::Legalize - This is the entry point for the file.
7284 void SelectionDAG::Legalize() {
7285 /// run - This is the main entry point to this class.
7287 SelectionDAGLegalize(*this).LegalizeDAG();