1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/Support/MathExtras.h"
18 #include "llvm/Target/TargetLowering.h"
19 #include "llvm/Target/TargetData.h"
20 #include "llvm/Target/TargetOptions.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/Constants.h"
27 //===----------------------------------------------------------------------===//
28 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
29 /// hacks on it until the target machine can handle it. This involves
30 /// eliminating value sizes the machine cannot handle (promoting small sizes to
31 /// large sizes or splitting up large values into small values) as well as
32 /// eliminating operations the machine cannot handle.
34 /// This code also does a small amount of optimization and recognition of idioms
35 /// as part of its processing. For example, if a target does not support a
36 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
37 /// will attempt merge setcc and brc instructions into brcc's.
40 class SelectionDAGLegalize {
44 /// LegalizeAction - This enum indicates what action we should take for each
45 /// value type the can occur in the program.
47 Legal, // The target natively supports this value type.
48 Promote, // This should be promoted to the next larger type.
49 Expand, // This integer type should be broken into smaller pieces.
52 /// ValueTypeActions - This is a bitvector that contains two bits for each
53 /// value type, where the two bits correspond to the LegalizeAction enum.
54 /// This can be queried with "getTypeAction(VT)".
55 unsigned ValueTypeActions;
57 /// NeedsAnotherIteration - This is set when we expand a large integer
58 /// operation into smaller integer operations, but the smaller operations are
59 /// not set. This occurs only rarely in practice, for targets that don't have
60 /// 32-bit or larger integer registers.
61 bool NeedsAnotherIteration;
63 /// LegalizedNodes - For nodes that are of legal width, and that have more
64 /// than one use, this map indicates what regularized operand to use. This
65 /// allows us to avoid legalizing the same thing more than once.
66 std::map<SDOperand, SDOperand> LegalizedNodes;
68 /// PromotedNodes - For nodes that are below legal width, and that have more
69 /// than one use, this map indicates what promoted value to use. This allows
70 /// us to avoid promoting the same thing more than once.
71 std::map<SDOperand, SDOperand> PromotedNodes;
73 /// ExpandedNodes - For nodes that need to be expanded, and which have more
74 /// than one use, this map indicates which which operands are the expanded
75 /// version of the input. This allows us to avoid expanding the same node
77 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
79 void AddLegalizedOperand(SDOperand From, SDOperand To) {
80 bool isNew = LegalizedNodes.insert(std::make_pair(From, To)).second;
81 assert(isNew && "Got into the map somehow?");
83 void AddPromotedOperand(SDOperand From, SDOperand To) {
84 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
85 assert(isNew && "Got into the map somehow?");
90 SelectionDAGLegalize(SelectionDAG &DAG);
92 /// Run - While there is still lowering to do, perform a pass over the DAG.
93 /// Most regularization can be done in a single pass, but targets that require
94 /// large values to be split into registers multiple times (e.g. i64 -> 4x
95 /// i16) require iteration for these values (the first iteration will demote
96 /// to i32, the second will demote to i16).
99 NeedsAnotherIteration = false;
101 } while (NeedsAnotherIteration);
104 /// getTypeAction - Return how we should legalize values of this type, either
105 /// it is already legal or we need to expand it into multiple registers of
106 /// smaller integer type, or we need to promote it to a larger type.
107 LegalizeAction getTypeAction(MVT::ValueType VT) const {
108 return (LegalizeAction)((ValueTypeActions >> (2*VT)) & 3);
111 /// isTypeLegal - Return true if this type is legal on this target.
113 bool isTypeLegal(MVT::ValueType VT) const {
114 return getTypeAction(VT) == Legal;
120 SDOperand LegalizeOp(SDOperand O);
121 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
122 SDOperand PromoteOp(SDOperand O);
124 SDOperand ExpandLibCall(const char *Name, SDNode *Node,
126 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
129 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
131 MVT::ValueType DestVT);
132 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
134 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
137 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
138 SDOperand &Lo, SDOperand &Hi);
139 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
140 SDOperand &Lo, SDOperand &Hi);
141 void ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS,
142 SDOperand &Lo, SDOperand &Hi);
144 void SpliceCallInto(const SDOperand &CallResult, SDNode *OutChain);
146 SDOperand getIntPtrConstant(uint64_t Val) {
147 return DAG.getConstant(Val, TLI.getPointerTy());
153 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
154 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
155 ValueTypeActions(TLI.getValueTypeActions()) {
156 assert(MVT::LAST_VALUETYPE <= 16 &&
157 "Too many value types for ValueTypeActions to hold!");
160 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
161 /// INT_TO_FP operation of the specified operand when the target requests that
162 /// we expand it. At this point, we know that the result and operand types are
163 /// legal for the target.
164 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
166 MVT::ValueType DestVT) {
167 if (Op0.getValueType() == MVT::i32) {
168 // simple 32-bit [signed|unsigned] integer to float/double expansion
170 // get the stack frame index of a 8 byte buffer
171 MachineFunction &MF = DAG.getMachineFunction();
172 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
173 // get address of 8 byte buffer
174 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
175 // word offset constant for Hi/Lo address computation
176 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
177 // set up Hi and Lo (into buffer) address based on endian
179 if (TLI.isLittleEndian()) {
180 Hi = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff);
184 Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff);
186 // if signed map to unsigned space
189 // constant used to invert sign bit (signed to unsigned mapping)
190 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
191 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
195 // store the lo of the constructed double - based on integer input
196 SDOperand Store1 = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
197 Op0Mapped, Lo, DAG.getSrcValue(NULL));
198 // initial hi portion of constructed double
199 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
200 // store the hi of the constructed double - biased exponent
201 SDOperand Store2 = DAG.getNode(ISD::STORE, MVT::Other, Store1,
202 InitialHi, Hi, DAG.getSrcValue(NULL));
203 // load the constructed double
204 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot,
205 DAG.getSrcValue(NULL));
206 // FP constant to bias correct the final result
207 SDOperand Bias = DAG.getConstantFP(isSigned ?
208 BitsToDouble(0x4330000080000000ULL)
209 : BitsToDouble(0x4330000000000000ULL),
212 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
215 // handle final rounding
216 if (DestVT == MVT::f64) {
220 // if f32 then cast to f32
221 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub);
223 NeedsAnotherIteration = true;
226 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
227 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
229 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
230 DAG.getConstant(0, Op0.getValueType()),
232 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
233 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
234 SignSet, Four, Zero);
236 // If the sign bit of the integer is set, the large number will be treated
237 // as a negative number. To counteract this, the dynamic code adds an
238 // offset depending on the data type.
240 switch (Op0.getValueType()) {
241 default: assert(0 && "Unsupported integer type!");
242 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
243 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
244 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
245 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
247 if (TLI.isLittleEndian()) FF <<= 32;
248 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
250 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
251 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
252 SDOperand FudgeInReg;
253 if (DestVT == MVT::f32)
254 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
255 DAG.getSrcValue(NULL));
257 assert(DestVT == MVT::f64 && "Unexpected conversion");
258 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64,
259 DAG.getEntryNode(), CPIdx,
260 DAG.getSrcValue(NULL), MVT::f32));
263 NeedsAnotherIteration = true;
264 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
267 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
268 /// *INT_TO_FP operation of the specified operand when the target requests that
269 /// we promote it. At this point, we know that the result and operand types are
270 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
271 /// operation that takes a larger input.
272 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
273 MVT::ValueType DestVT,
275 // First step, figure out the appropriate *INT_TO_FP operation to use.
276 MVT::ValueType NewInTy = LegalOp.getValueType();
278 unsigned OpToUse = 0;
280 // Scan for the appropriate larger type to use.
282 NewInTy = (MVT::ValueType)(NewInTy+1);
283 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
285 // If the target supports SINT_TO_FP of this type, use it.
286 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
288 case TargetLowering::Legal:
289 if (!TLI.isTypeLegal(NewInTy))
290 break; // Can't use this datatype.
292 case TargetLowering::Custom:
293 OpToUse = ISD::SINT_TO_FP;
297 if (isSigned) continue;
299 // If the target supports UINT_TO_FP of this type, use it.
300 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
302 case TargetLowering::Legal:
303 if (!TLI.isTypeLegal(NewInTy))
304 break; // Can't use this datatype.
306 case TargetLowering::Custom:
307 OpToUse = ISD::UINT_TO_FP;
312 // Otherwise, try a larger type.
315 // Make sure to legalize any nodes we create here in the next pass.
316 NeedsAnotherIteration = true;
318 // Okay, we found the operation and type to use. Zero extend our input to the
319 // desired type then run the operation on it.
320 return DAG.getNode(OpToUse, DestVT,
321 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
325 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
326 /// FP_TO_*INT operation of the specified operand when the target requests that
327 /// we promote it. At this point, we know that the result and operand types are
328 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
329 /// operation that returns a larger result.
330 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
331 MVT::ValueType DestVT,
333 // First step, figure out the appropriate FP_TO*INT operation to use.
334 MVT::ValueType NewOutTy = DestVT;
336 unsigned OpToUse = 0;
338 // Scan for the appropriate larger type to use.
340 NewOutTy = (MVT::ValueType)(NewOutTy+1);
341 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
343 // If the target supports FP_TO_SINT returning this type, use it.
344 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
346 case TargetLowering::Legal:
347 if (!TLI.isTypeLegal(NewOutTy))
348 break; // Can't use this datatype.
350 case TargetLowering::Custom:
351 OpToUse = ISD::FP_TO_SINT;
356 // If the target supports FP_TO_UINT of this type, use it.
357 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
359 case TargetLowering::Legal:
360 if (!TLI.isTypeLegal(NewOutTy))
361 break; // Can't use this datatype.
363 case TargetLowering::Custom:
364 OpToUse = ISD::FP_TO_UINT;
369 // Otherwise, try a larger type.
372 // Make sure to legalize any nodes we create here in the next pass.
373 NeedsAnotherIteration = true;
375 // Okay, we found the operation and type to use. Truncate the result of the
376 // extended FP_TO_*INT operation to the desired size.
377 return DAG.getNode(ISD::TRUNCATE, DestVT,
378 DAG.getNode(OpToUse, NewOutTy, LegalOp));
382 void SelectionDAGLegalize::LegalizeDAG() {
383 SDOperand OldRoot = DAG.getRoot();
384 SDOperand NewRoot = LegalizeOp(OldRoot);
385 DAG.setRoot(NewRoot);
387 ExpandedNodes.clear();
388 LegalizedNodes.clear();
389 PromotedNodes.clear();
391 // Remove dead nodes now.
392 DAG.RemoveDeadNodes(OldRoot.Val);
395 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
396 assert(isTypeLegal(Op.getValueType()) &&
397 "Caller should expand or promote operands that are not legal!");
398 SDNode *Node = Op.Val;
400 // If this operation defines any values that cannot be represented in a
401 // register on this target, make sure to expand or promote them.
402 if (Node->getNumValues() > 1) {
403 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
404 switch (getTypeAction(Node->getValueType(i))) {
405 case Legal: break; // Nothing to do.
408 ExpandOp(Op.getValue(i), T1, T2);
409 assert(LegalizedNodes.count(Op) &&
410 "Expansion didn't add legal operands!");
411 return LegalizedNodes[Op];
414 PromoteOp(Op.getValue(i));
415 assert(LegalizedNodes.count(Op) &&
416 "Expansion didn't add legal operands!");
417 return LegalizedNodes[Op];
421 // Note that LegalizeOp may be reentered even from single-use nodes, which
422 // means that we always must cache transformed nodes.
423 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
424 if (I != LegalizedNodes.end()) return I->second;
426 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
428 SDOperand Result = Op;
430 switch (Node->getOpcode()) {
432 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
433 // If this is a target node, legalize it by legalizing the operands then
434 // passing it through.
435 std::vector<SDOperand> Ops;
436 bool Changed = false;
437 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
438 Ops.push_back(LegalizeOp(Node->getOperand(i)));
439 Changed = Changed || Node->getOperand(i) != Ops.back();
442 if (Node->getNumValues() == 1)
443 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Ops);
445 std::vector<MVT::ValueType> VTs(Node->value_begin(),
447 Result = DAG.getNode(Node->getOpcode(), VTs, Ops);
450 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
451 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
452 return Result.getValue(Op.ResNo);
454 // Otherwise this is an unhandled builtin node. splat.
455 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
456 assert(0 && "Do not know how to legalize this operator!");
458 case ISD::EntryToken:
459 case ISD::FrameIndex:
460 case ISD::GlobalAddress:
461 case ISD::ExternalSymbol:
462 case ISD::ConstantPool: // Nothing to do.
463 assert(isTypeLegal(Node->getValueType(0)) && "This must be legal!");
465 case ISD::AssertSext:
466 case ISD::AssertZext:
467 Tmp1 = LegalizeOp(Node->getOperand(0));
468 if (Tmp1 != Node->getOperand(0))
469 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,
470 Node->getOperand(1));
472 case ISD::CopyFromReg:
473 Tmp1 = LegalizeOp(Node->getOperand(0));
474 if (Tmp1 != Node->getOperand(0))
475 Result = DAG.getCopyFromReg(Tmp1,
476 cast<RegisterSDNode>(Node->getOperand(1))->getReg(),
477 Node->getValueType(0));
479 Result = Op.getValue(0);
481 // Since CopyFromReg produces two values, make sure to remember that we
482 // legalized both of them.
483 AddLegalizedOperand(Op.getValue(0), Result);
484 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
485 return Result.getValue(Op.ResNo);
486 case ISD::ImplicitDef:
487 Tmp1 = LegalizeOp(Node->getOperand(0));
488 if (Tmp1 != Node->getOperand(0))
489 Result = DAG.getNode(ISD::ImplicitDef, MVT::Other,
490 Tmp1, Node->getOperand(1));
493 MVT::ValueType VT = Op.getValueType();
494 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
495 default: assert(0 && "This action is not supported yet!");
496 case TargetLowering::Expand:
497 case TargetLowering::Promote:
498 if (MVT::isInteger(VT))
499 Result = DAG.getConstant(0, VT);
500 else if (MVT::isFloatingPoint(VT))
501 Result = DAG.getConstantFP(0, VT);
503 assert(0 && "Unknown value type!");
505 case TargetLowering::Legal:
511 // We know we don't need to expand constants here, constants only have one
512 // value and we check that it is fine above.
514 // FIXME: Maybe we should handle things like targets that don't support full
515 // 32-bit immediates?
517 case ISD::ConstantFP: {
518 // Spill FP immediates to the constant pool if the target cannot directly
519 // codegen them. Targets often have some immediate values that can be
520 // efficiently generated into an FP register without a load. We explicitly
521 // leave these constants as ConstantFP nodes for the target to deal with.
523 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
525 // Check to see if this FP immediate is already legal.
526 bool isLegal = false;
527 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
528 E = TLI.legal_fpimm_end(); I != E; ++I)
529 if (CFP->isExactlyValue(*I)) {
535 // Otherwise we need to spill the constant to memory.
538 // If a FP immediate is precise when represented as a float, we put it
539 // into the constant pool as a float, even if it's is statically typed
541 MVT::ValueType VT = CFP->getValueType(0);
542 bool isDouble = VT == MVT::f64;
543 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy :
544 Type::FloatTy, CFP->getValue());
545 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) &&
546 // Only do this if the target has a native EXTLOAD instruction from
548 TLI.isOperationLegal(ISD::EXTLOAD, MVT::f32)) {
549 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy));
554 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
556 Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
557 CPIdx, DAG.getSrcValue(NULL), MVT::f32);
559 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
560 DAG.getSrcValue(NULL));
565 case ISD::TokenFactor: {
566 std::vector<SDOperand> Ops;
567 bool Changed = false;
568 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
569 SDOperand Op = Node->getOperand(i);
570 // Fold single-use TokenFactor nodes into this token factor as we go.
571 // FIXME: This is something that the DAGCombiner should do!!
572 if (Op.getOpcode() == ISD::TokenFactor && Op.hasOneUse()) {
574 for (unsigned j = 0, e = Op.getNumOperands(); j != e; ++j)
575 Ops.push_back(LegalizeOp(Op.getOperand(j)));
577 Ops.push_back(LegalizeOp(Op)); // Legalize the operands
578 Changed |= Ops[i] != Op;
582 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Ops);
586 case ISD::CALLSEQ_START:
587 case ISD::CALLSEQ_END:
588 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
589 // Do not try to legalize the target-specific arguments (#1+)
590 Tmp2 = Node->getOperand(0);
592 Node->setAdjCallChain(Tmp1);
594 // If moving the operand from pointing to Tmp2 dropped its use count to 1,
595 // this will cause the maps used to memoize results to get confused.
596 // Create and add a dummy use, just to increase its use count. This will
597 // be removed at the end of legalize when dead nodes are removed.
598 if (Tmp2.Val->hasOneUse())
599 DAG.getNode(ISD::PCMARKER, MVT::Other, Tmp2,
600 DAG.getConstant(0, MVT::i32));
602 // Note that we do not create new CALLSEQ_DOWN/UP nodes here. These
603 // nodes are treated specially and are mutated in place. This makes the dag
604 // legalization process more efficient and also makes libcall insertion
607 case ISD::DYNAMIC_STACKALLOC:
608 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
609 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
610 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
611 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
612 Tmp3 != Node->getOperand(2)) {
613 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end());
614 std::vector<SDOperand> Ops;
615 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3);
616 Result = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, Ops);
618 Result = Op.getValue(0);
620 // Since this op produces two values, make sure to remember that we
621 // legalized both of them.
622 AddLegalizedOperand(SDOperand(Node, 0), Result);
623 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
624 return Result.getValue(Op.ResNo);
628 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
629 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee.
631 bool Changed = false;
632 std::vector<SDOperand> Ops;
633 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) {
634 Ops.push_back(LegalizeOp(Node->getOperand(i)));
635 Changed |= Ops.back() != Node->getOperand(i);
638 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || Changed) {
639 std::vector<MVT::ValueType> RetTyVTs;
640 RetTyVTs.reserve(Node->getNumValues());
641 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
642 RetTyVTs.push_back(Node->getValueType(i));
643 Result = SDOperand(DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops,
644 Node->getOpcode() == ISD::TAILCALL), 0);
646 Result = Result.getValue(0);
648 // Since calls produce multiple values, make sure to remember that we
649 // legalized all of them.
650 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
651 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
652 return Result.getValue(Op.ResNo);
655 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
656 if (Tmp1 != Node->getOperand(0))
657 Result = DAG.getNode(ISD::BR, MVT::Other, Tmp1, Node->getOperand(1));
661 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
663 switch (getTypeAction(Node->getOperand(1).getValueType())) {
664 case Expand: assert(0 && "It's impossible to expand bools");
666 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
669 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
673 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
674 default: assert(0 && "This action is not supported yet!");
675 case TargetLowering::Expand:
676 // Expand brcond's setcc into its constituent parts and create a BR_CC
678 if (Tmp2.getOpcode() == ISD::SETCC) {
679 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
680 Tmp2.getOperand(0), Tmp2.getOperand(1),
681 Node->getOperand(2));
683 // Make sure the condition is either zero or one. It may have been
684 // promoted from something else.
685 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
687 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
688 DAG.getCondCode(ISD::SETNE), Tmp2,
689 DAG.getConstant(0, Tmp2.getValueType()),
690 Node->getOperand(2));
693 case TargetLowering::Legal:
694 // Basic block destination (Op#2) is always legal.
695 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
696 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2,
697 Node->getOperand(2));
702 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
704 if (isTypeLegal(Node->getOperand(2).getValueType())) {
705 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS
706 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS
707 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) ||
708 Tmp3 != Node->getOperand(3)) {
709 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Node->getOperand(1),
710 Tmp2, Tmp3, Node->getOperand(4));
714 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),
715 Node->getOperand(2), // LHS
716 Node->getOperand(3), // RHS
717 Node->getOperand(1)));
718 // If we get a SETCC back from legalizing the SETCC node we just
719 // created, then use its LHS, RHS, and CC directly in creating a new
720 // node. Otherwise, select between the true and false value based on
721 // comparing the result of the legalized with zero.
722 if (Tmp2.getOpcode() == ISD::SETCC) {
723 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
724 Tmp2.getOperand(0), Tmp2.getOperand(1),
725 Node->getOperand(4));
727 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
728 DAG.getCondCode(ISD::SETNE),
729 Tmp2, DAG.getConstant(0, Tmp2.getValueType()),
730 Node->getOperand(4));
734 case ISD::BRCONDTWOWAY:
735 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
736 switch (getTypeAction(Node->getOperand(1).getValueType())) {
737 case Expand: assert(0 && "It's impossible to expand bools");
739 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
742 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
745 // If this target does not support BRCONDTWOWAY, lower it to a BRCOND/BR
747 switch (TLI.getOperationAction(ISD::BRCONDTWOWAY, MVT::Other)) {
748 case TargetLowering::Promote:
749 default: assert(0 && "This action is not supported yet!");
750 case TargetLowering::Legal:
751 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) {
752 std::vector<SDOperand> Ops;
755 Ops.push_back(Node->getOperand(2));
756 Ops.push_back(Node->getOperand(3));
757 Result = DAG.getNode(ISD::BRCONDTWOWAY, MVT::Other, Ops);
760 case TargetLowering::Expand:
761 // If BRTWOWAY_CC is legal for this target, then simply expand this node
762 // to that. Otherwise, skip BRTWOWAY_CC and expand directly to a
764 if (TLI.isOperationLegal(ISD::BRTWOWAY_CC, MVT::Other)) {
765 if (Tmp2.getOpcode() == ISD::SETCC) {
766 Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2),
767 Tmp2.getOperand(0), Tmp2.getOperand(1),
768 Node->getOperand(2), Node->getOperand(3));
770 Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2,
771 DAG.getConstant(0, Tmp2.getValueType()),
772 Node->getOperand(2), Node->getOperand(3));
775 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2,
776 Node->getOperand(2));
777 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(3));
782 case ISD::BRTWOWAY_CC:
783 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
784 if (isTypeLegal(Node->getOperand(2).getValueType())) {
785 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS
786 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS
787 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) ||
788 Tmp3 != Node->getOperand(3)) {
789 Result = DAG.getBR2Way_CC(Tmp1, Node->getOperand(1), Tmp2, Tmp3,
790 Node->getOperand(4), Node->getOperand(5));
794 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),
795 Node->getOperand(2), // LHS
796 Node->getOperand(3), // RHS
797 Node->getOperand(1)));
798 // If this target does not support BRTWOWAY_CC, lower it to a BRCOND/BR
800 switch (TLI.getOperationAction(ISD::BRTWOWAY_CC, MVT::Other)) {
801 default: assert(0 && "This action is not supported yet!");
802 case TargetLowering::Legal:
803 // If we get a SETCC back from legalizing the SETCC node we just
804 // created, then use its LHS, RHS, and CC directly in creating a new
805 // node. Otherwise, select between the true and false value based on
806 // comparing the result of the legalized with zero.
807 if (Tmp2.getOpcode() == ISD::SETCC) {
808 Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2),
809 Tmp2.getOperand(0), Tmp2.getOperand(1),
810 Node->getOperand(4), Node->getOperand(5));
812 Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2,
813 DAG.getConstant(0, Tmp2.getValueType()),
814 Node->getOperand(4), Node->getOperand(5));
817 case TargetLowering::Expand:
818 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2,
819 Node->getOperand(4));
820 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(5));
826 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
827 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
829 if (Tmp1 != Node->getOperand(0) ||
830 Tmp2 != Node->getOperand(1))
831 Result = DAG.getLoad(Node->getValueType(0), Tmp1, Tmp2,
832 Node->getOperand(2));
834 Result = SDOperand(Node, 0);
836 // Since loads produce two values, make sure to remember that we legalized
838 AddLegalizedOperand(SDOperand(Node, 0), Result);
839 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
840 return Result.getValue(Op.ResNo);
844 case ISD::ZEXTLOAD: {
845 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
846 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
848 MVT::ValueType SrcVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
849 switch (TLI.getOperationAction(Node->getOpcode(), SrcVT)) {
850 default: assert(0 && "This action is not supported yet!");
851 case TargetLowering::Promote:
852 assert(SrcVT == MVT::i1 && "Can only promote EXTLOAD from i1 -> i8!");
853 Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0),
854 Tmp1, Tmp2, Node->getOperand(2), MVT::i8);
855 // Since loads produce two values, make sure to remember that we legalized
857 AddLegalizedOperand(SDOperand(Node, 0), Result);
858 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
859 return Result.getValue(Op.ResNo);
861 case TargetLowering::Legal:
862 if (Tmp1 != Node->getOperand(0) ||
863 Tmp2 != Node->getOperand(1))
864 Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0),
865 Tmp1, Tmp2, Node->getOperand(2), SrcVT);
867 Result = SDOperand(Node, 0);
869 // Since loads produce two values, make sure to remember that we legalized
871 AddLegalizedOperand(SDOperand(Node, 0), Result);
872 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
873 return Result.getValue(Op.ResNo);
874 case TargetLowering::Expand:
875 //f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
876 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
877 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, Node->getOperand(2));
878 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
880 return Load.getValue(1);
883 assert(Node->getOpcode() != ISD::EXTLOAD &&
884 "EXTLOAD should always be supported!");
885 // Turn the unsupported load into an EXTLOAD followed by an explicit
886 // zero/sign extend inreg.
887 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
888 Tmp1, Tmp2, Node->getOperand(2), SrcVT);
890 if (Node->getOpcode() == ISD::SEXTLOAD)
891 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
892 Result, DAG.getValueType(SrcVT));
894 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
895 AddLegalizedOperand(SDOperand(Node, 0), ValRes);
896 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
898 return Result.getValue(1);
901 assert(0 && "Unreachable");
903 case ISD::EXTRACT_ELEMENT:
904 // Get both the low and high parts.
905 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
906 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
907 Result = Tmp2; // 1 -> Hi
909 Result = Tmp1; // 0 -> Lo
913 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
915 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
916 "Register type must be legal!");
917 // Legalize the incoming value (must be legal).
918 Tmp2 = LegalizeOp(Node->getOperand(2));
919 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2))
920 Result = DAG.getNode(ISD::CopyToReg, MVT::Other, Tmp1,
921 Node->getOperand(1), Tmp2);
925 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
926 switch (Node->getNumOperands()) {
928 switch (getTypeAction(Node->getOperand(1).getValueType())) {
930 Tmp2 = LegalizeOp(Node->getOperand(1));
931 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
932 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2);
936 ExpandOp(Node->getOperand(1), Lo, Hi);
937 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi);
941 Tmp2 = PromoteOp(Node->getOperand(1));
942 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2);
947 if (Tmp1 != Node->getOperand(0))
948 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1);
950 default: { // ret <values>
951 std::vector<SDOperand> NewValues;
952 NewValues.push_back(Tmp1);
953 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i)
954 switch (getTypeAction(Node->getOperand(i).getValueType())) {
956 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
960 ExpandOp(Node->getOperand(i), Lo, Hi);
961 NewValues.push_back(Lo);
962 NewValues.push_back(Hi);
966 assert(0 && "Can't promote multiple return value yet!");
968 Result = DAG.getNode(ISD::RET, MVT::Other, NewValues);
974 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
975 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
977 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
978 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){
979 if (CFP->getValueType(0) == MVT::f32) {
980 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1,
981 DAG.getConstant(FloatToBits(CFP->getValue()),
984 Node->getOperand(3));
986 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
987 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1,
988 DAG.getConstant(DoubleToBits(CFP->getValue()),
991 Node->getOperand(3));
996 switch (getTypeAction(Node->getOperand(1).getValueType())) {
998 SDOperand Val = LegalizeOp(Node->getOperand(1));
999 if (Val != Node->getOperand(1) || Tmp1 != Node->getOperand(0) ||
1000 Tmp2 != Node->getOperand(2))
1001 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Val, Tmp2,
1002 Node->getOperand(3));
1006 // Truncate the value and store the result.
1007 Tmp3 = PromoteOp(Node->getOperand(1));
1008 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2,
1009 Node->getOperand(3),
1010 DAG.getValueType(Node->getOperand(1).getValueType()));
1015 ExpandOp(Node->getOperand(1), Lo, Hi);
1017 if (!TLI.isLittleEndian())
1020 Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2,
1021 Node->getOperand(3));
1022 unsigned IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8;
1023 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1024 getIntPtrConstant(IncrementSize));
1025 assert(isTypeLegal(Tmp2.getValueType()) &&
1026 "Pointers must be legal!");
1027 //Again, claiming both parts of the store came form the same Instr
1028 Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2,
1029 Node->getOperand(3));
1030 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
1035 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1036 if (Tmp1 != Node->getOperand(0))
1037 Result = DAG.getNode(ISD::PCMARKER, MVT::Other, Tmp1,Node->getOperand(1));
1039 case ISD::TRUNCSTORE:
1040 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1041 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
1043 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1045 Tmp2 = LegalizeOp(Node->getOperand(1));
1047 // The only promote case we handle is TRUNCSTORE:i1 X into
1048 // -> TRUNCSTORE:i8 (and X, 1)
1049 if (cast<VTSDNode>(Node->getOperand(4))->getVT() == MVT::i1 &&
1050 TLI.getOperationAction(ISD::TRUNCSTORE, MVT::i1) ==
1051 TargetLowering::Promote) {
1052 // Promote the bool to a mask then store.
1053 Tmp2 = DAG.getNode(ISD::AND, Tmp2.getValueType(), Tmp2,
1054 DAG.getConstant(1, Tmp2.getValueType()));
1055 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3,
1056 Node->getOperand(3), DAG.getValueType(MVT::i8));
1058 } else if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1059 Tmp3 != Node->getOperand(2)) {
1060 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3,
1061 Node->getOperand(3), Node->getOperand(4));
1066 assert(0 && "Cannot handle illegal TRUNCSTORE yet!");
1070 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1071 case Expand: assert(0 && "It's impossible to expand bools");
1073 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
1076 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
1079 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
1080 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
1082 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
1083 default: assert(0 && "This action is not supported yet!");
1084 case TargetLowering::Expand:
1085 if (Tmp1.getOpcode() == ISD::SETCC) {
1086 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
1088 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
1090 // Make sure the condition is either zero or one. It may have been
1091 // promoted from something else.
1092 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
1093 Result = DAG.getSelectCC(Tmp1,
1094 DAG.getConstant(0, Tmp1.getValueType()),
1095 Tmp2, Tmp3, ISD::SETNE);
1098 case TargetLowering::Legal:
1099 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1100 Tmp3 != Node->getOperand(2))
1101 Result = DAG.getNode(ISD::SELECT, Node->getValueType(0),
1104 case TargetLowering::Promote: {
1105 MVT::ValueType NVT =
1106 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
1107 unsigned ExtOp, TruncOp;
1108 if (MVT::isInteger(Tmp2.getValueType())) {
1109 ExtOp = ISD::ANY_EXTEND;
1110 TruncOp = ISD::TRUNCATE;
1112 ExtOp = ISD::FP_EXTEND;
1113 TruncOp = ISD::FP_ROUND;
1115 // Promote each of the values to the new type.
1116 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
1117 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
1118 // Perform the larger operation, then round down.
1119 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
1120 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
1125 case ISD::SELECT_CC:
1126 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
1127 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
1129 if (isTypeLegal(Node->getOperand(0).getValueType())) {
1130 // Everything is legal, see if we should expand this op or something.
1131 switch (TLI.getOperationAction(ISD::SELECT_CC,
1132 Node->getOperand(0).getValueType())) {
1133 default: assert(0 && "This action is not supported yet!");
1134 case TargetLowering::Custom: {
1136 TLI.LowerOperation(DAG.getNode(ISD::SELECT_CC, Node->getValueType(0),
1137 Node->getOperand(0),
1138 Node->getOperand(1), Tmp3, Tmp4,
1139 Node->getOperand(4)), DAG);
1141 Result = LegalizeOp(Tmp);
1144 } // FALLTHROUGH if the target can't lower this operation after all.
1145 case TargetLowering::Legal:
1146 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
1147 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
1148 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1149 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3)) {
1150 Result = DAG.getNode(ISD::SELECT_CC, Node->getValueType(0), Tmp1, Tmp2,
1151 Tmp3, Tmp4, Node->getOperand(4));
1157 Tmp1 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),
1158 Node->getOperand(0), // LHS
1159 Node->getOperand(1), // RHS
1160 Node->getOperand(4)));
1161 // If we get a SETCC back from legalizing the SETCC node we just
1162 // created, then use its LHS, RHS, and CC directly in creating a new
1163 // node. Otherwise, select between the true and false value based on
1164 // comparing the result of the legalized with zero.
1165 if (Tmp1.getOpcode() == ISD::SETCC) {
1166 Result = DAG.getNode(ISD::SELECT_CC, Tmp3.getValueType(),
1167 Tmp1.getOperand(0), Tmp1.getOperand(1),
1168 Tmp3, Tmp4, Tmp1.getOperand(2));
1170 Result = DAG.getSelectCC(Tmp1,
1171 DAG.getConstant(0, Tmp1.getValueType()),
1172 Tmp3, Tmp4, ISD::SETNE);
1177 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1179 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
1180 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
1183 Tmp1 = PromoteOp(Node->getOperand(0)); // LHS
1184 Tmp2 = PromoteOp(Node->getOperand(1)); // RHS
1186 // If this is an FP compare, the operands have already been extended.
1187 if (MVT::isInteger(Node->getOperand(0).getValueType())) {
1188 MVT::ValueType VT = Node->getOperand(0).getValueType();
1189 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
1191 // Otherwise, we have to insert explicit sign or zero extends. Note
1192 // that we could insert sign extends for ALL conditions, but zero extend
1193 // is cheaper on many machines (an AND instead of two shifts), so prefer
1195 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) {
1196 default: assert(0 && "Unknown integer comparison!");
1203 // ALL of these operations will work if we either sign or zero extend
1204 // the operands (including the unsigned comparisons!). Zero extend is
1205 // usually a simpler/cheaper operation, so prefer it.
1206 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
1207 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
1213 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
1214 DAG.getValueType(VT));
1215 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
1216 DAG.getValueType(VT));
1222 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
1223 ExpandOp(Node->getOperand(0), LHSLo, LHSHi);
1224 ExpandOp(Node->getOperand(1), RHSLo, RHSHi);
1225 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) {
1229 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
1230 if (RHSCST->isAllOnesValue()) {
1231 // Comparison to -1.
1232 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
1237 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
1238 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
1239 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
1240 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
1243 // If this is a comparison of the sign bit, just look at the top part.
1245 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Node->getOperand(1)))
1246 if ((cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETLT &&
1247 CST->getValue() == 0) || // X < 0
1248 (cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETGT &&
1249 (CST->isAllOnesValue()))) { // X > -1
1255 // FIXME: This generated code sucks.
1256 ISD::CondCode LowCC;
1257 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) {
1258 default: assert(0 && "Unknown integer setcc!");
1260 case ISD::SETULT: LowCC = ISD::SETULT; break;
1262 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
1264 case ISD::SETULE: LowCC = ISD::SETULE; break;
1266 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
1269 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
1270 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
1271 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
1273 // NOTE: on targets without efficient SELECT of bools, we can always use
1274 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
1275 Tmp1 = DAG.getSetCC(Node->getValueType(0), LHSLo, RHSLo, LowCC);
1276 Tmp2 = DAG.getNode(ISD::SETCC, Node->getValueType(0), LHSHi, RHSHi,
1277 Node->getOperand(2));
1278 Result = DAG.getSetCC(Node->getValueType(0), LHSHi, RHSHi, ISD::SETEQ);
1279 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
1280 Result, Tmp1, Tmp2));
1285 switch(TLI.getOperationAction(ISD::SETCC, Node->getOperand(0).getValueType())) {
1287 assert(0 && "Cannot handle this action for SETCC yet!");
1289 case TargetLowering::Promote:
1290 Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2,
1291 Node->getOperand(2));
1293 case TargetLowering::Legal:
1294 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
1295 Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2,
1296 Node->getOperand(2));
1298 case TargetLowering::Expand:
1299 // Expand a setcc node into a select_cc of the same condition, lhs, and
1300 // rhs that selects between const 1 (true) and const 0 (false).
1301 MVT::ValueType VT = Node->getValueType(0);
1302 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
1303 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
1304 Node->getOperand(2));
1305 Result = LegalizeOp(Result);
1312 case ISD::MEMMOVE: {
1313 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
1314 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
1316 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
1317 switch (getTypeAction(Node->getOperand(2).getValueType())) {
1318 case Expand: assert(0 && "Cannot expand a byte!");
1320 Tmp3 = LegalizeOp(Node->getOperand(2));
1323 Tmp3 = PromoteOp(Node->getOperand(2));
1327 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
1331 switch (getTypeAction(Node->getOperand(3).getValueType())) {
1333 // Length is too big, just take the lo-part of the length.
1335 ExpandOp(Node->getOperand(3), HiPart, Tmp4);
1339 Tmp4 = LegalizeOp(Node->getOperand(3));
1342 Tmp4 = PromoteOp(Node->getOperand(3));
1347 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
1348 case Expand: assert(0 && "Cannot expand this yet!");
1350 Tmp5 = LegalizeOp(Node->getOperand(4));
1353 Tmp5 = PromoteOp(Node->getOperand(4));
1357 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
1358 default: assert(0 && "This action not implemented for this operation!");
1359 case TargetLowering::Custom: {
1361 TLI.LowerOperation(DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1,
1362 Tmp2, Tmp3, Tmp4, Tmp5), DAG);
1364 Result = LegalizeOp(Tmp);
1367 // FALLTHROUGH if the target thinks it is legal.
1369 case TargetLowering::Legal:
1370 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1371 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3) ||
1372 Tmp5 != Node->getOperand(4)) {
1373 std::vector<SDOperand> Ops;
1374 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3);
1375 Ops.push_back(Tmp4); Ops.push_back(Tmp5);
1376 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Ops);
1379 case TargetLowering::Expand: {
1380 // Otherwise, the target does not support this operation. Lower the
1381 // operation to an explicit libcall as appropriate.
1382 MVT::ValueType IntPtr = TLI.getPointerTy();
1383 const Type *IntPtrTy = TLI.getTargetData().getIntPtrType();
1384 std::vector<std::pair<SDOperand, const Type*> > Args;
1386 const char *FnName = 0;
1387 if (Node->getOpcode() == ISD::MEMSET) {
1388 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
1389 // Extend the ubyte argument to be an int value for the call.
1390 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
1391 Args.push_back(std::make_pair(Tmp3, Type::IntTy));
1392 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
1395 } else if (Node->getOpcode() == ISD::MEMCPY ||
1396 Node->getOpcode() == ISD::MEMMOVE) {
1397 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
1398 Args.push_back(std::make_pair(Tmp3, IntPtrTy));
1399 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
1400 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
1402 assert(0 && "Unknown op!");
1405 std::pair<SDOperand,SDOperand> CallResult =
1406 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, CallingConv::C, false,
1407 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
1408 Result = CallResult.second;
1409 NeedsAnotherIteration = true;
1417 Tmp1 = LegalizeOp(Node->getOperand(0));
1418 Tmp2 = LegalizeOp(Node->getOperand(1));
1420 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) {
1421 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end());
1422 std::vector<SDOperand> Ops;
1423 Ops.push_back(Tmp1);
1424 Ops.push_back(Tmp2);
1425 Result = DAG.getNode(ISD::READPORT, VTs, Ops);
1427 Result = SDOperand(Node, 0);
1428 // Since these produce two values, make sure to remember that we legalized
1430 AddLegalizedOperand(SDOperand(Node, 0), Result);
1431 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1432 return Result.getValue(Op.ResNo);
1433 case ISD::WRITEPORT:
1434 Tmp1 = LegalizeOp(Node->getOperand(0));
1435 Tmp2 = LegalizeOp(Node->getOperand(1));
1436 Tmp3 = LegalizeOp(Node->getOperand(2));
1437 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1438 Tmp3 != Node->getOperand(2))
1439 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3);
1443 Tmp1 = LegalizeOp(Node->getOperand(0));
1444 Tmp2 = LegalizeOp(Node->getOperand(1));
1446 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1447 case TargetLowering::Custom:
1448 default: assert(0 && "This action not implemented for this operation!");
1449 case TargetLowering::Legal:
1450 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) {
1451 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end());
1452 std::vector<SDOperand> Ops;
1453 Ops.push_back(Tmp1);
1454 Ops.push_back(Tmp2);
1455 Result = DAG.getNode(ISD::READPORT, VTs, Ops);
1457 Result = SDOperand(Node, 0);
1459 case TargetLowering::Expand:
1460 // Replace this with a load from memory.
1461 Result = DAG.getLoad(Node->getValueType(0), Node->getOperand(0),
1462 Node->getOperand(1), DAG.getSrcValue(NULL));
1463 Result = LegalizeOp(Result);
1467 // Since these produce two values, make sure to remember that we legalized
1469 AddLegalizedOperand(SDOperand(Node, 0), Result);
1470 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1471 return Result.getValue(Op.ResNo);
1474 Tmp1 = LegalizeOp(Node->getOperand(0));
1475 Tmp2 = LegalizeOp(Node->getOperand(1));
1476 Tmp3 = LegalizeOp(Node->getOperand(2));
1478 switch (TLI.getOperationAction(Node->getOpcode(),
1479 Node->getOperand(1).getValueType())) {
1480 case TargetLowering::Custom:
1481 default: assert(0 && "This action not implemented for this operation!");
1482 case TargetLowering::Legal:
1483 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1484 Tmp3 != Node->getOperand(2))
1485 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3);
1487 case TargetLowering::Expand:
1488 // Replace this with a store to memory.
1489 Result = DAG.getNode(ISD::STORE, MVT::Other, Node->getOperand(0),
1490 Node->getOperand(1), Node->getOperand(2),
1491 DAG.getSrcValue(NULL));
1492 Result = LegalizeOp(Result);
1497 case ISD::ADD_PARTS:
1498 case ISD::SUB_PARTS:
1499 case ISD::SHL_PARTS:
1500 case ISD::SRA_PARTS:
1501 case ISD::SRL_PARTS: {
1502 std::vector<SDOperand> Ops;
1503 bool Changed = false;
1504 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1505 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1506 Changed |= Ops.back() != Node->getOperand(i);
1509 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end());
1510 Result = DAG.getNode(Node->getOpcode(), VTs, Ops);
1513 // Since these produce multiple values, make sure to remember that we
1514 // legalized all of them.
1515 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1516 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
1517 return Result.getValue(Op.ResNo);
1538 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
1539 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1540 case Expand: assert(0 && "Not possible");
1542 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
1545 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
1548 if (Tmp1 != Node->getOperand(0) ||
1549 Tmp2 != Node->getOperand(1))
1550 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,Tmp2);
1556 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
1557 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
1558 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1559 case TargetLowering::Legal:
1560 if (Tmp1 != Node->getOperand(0) ||
1561 Tmp2 != Node->getOperand(1))
1562 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,
1565 case TargetLowering::Promote:
1566 case TargetLowering::Custom:
1567 assert(0 && "Cannot promote/custom handle this yet!");
1568 case TargetLowering::Expand:
1569 if (MVT::isInteger(Node->getValueType(0))) {
1570 MVT::ValueType VT = Node->getValueType(0);
1571 unsigned Opc = (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
1572 Result = DAG.getNode(Opc, VT, Tmp1, Tmp2);
1573 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
1574 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
1576 // Floating point mod -> fmod libcall.
1577 const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod";
1579 Result = ExpandLibCall(FnName, Node, Dummy);
1588 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
1589 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1590 case TargetLowering::Legal:
1591 if (Tmp1 != Node->getOperand(0))
1592 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
1594 case TargetLowering::Promote: {
1595 MVT::ValueType OVT = Tmp1.getValueType();
1596 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1598 // Zero extend the argument.
1599 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
1600 // Perform the larger operation, then subtract if needed.
1601 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
1602 switch(Node->getOpcode())
1608 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
1609 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
1610 DAG.getConstant(getSizeInBits(NVT), NVT),
1612 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
1613 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1);
1616 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
1617 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
1618 DAG.getConstant(getSizeInBits(NVT) -
1619 getSizeInBits(OVT), NVT));
1624 case TargetLowering::Custom:
1625 assert(0 && "Cannot custom handle this yet!");
1626 case TargetLowering::Expand:
1627 switch(Node->getOpcode())
1630 static const uint64_t mask[6] = {
1631 0x5555555555555555ULL, 0x3333333333333333ULL,
1632 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
1633 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
1635 MVT::ValueType VT = Tmp1.getValueType();
1636 MVT::ValueType ShVT = TLI.getShiftAmountTy();
1637 unsigned len = getSizeInBits(VT);
1638 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
1639 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
1640 Tmp2 = DAG.getConstant(mask[i], VT);
1641 Tmp3 = DAG.getConstant(1ULL << i, ShVT);
1642 Tmp1 = DAG.getNode(ISD::ADD, VT,
1643 DAG.getNode(ISD::AND, VT, Tmp1, Tmp2),
1644 DAG.getNode(ISD::AND, VT,
1645 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3),
1652 /* for now, we do this:
1657 x = x | (x >>32); // for 64-bit input
1658 return popcount(~x);
1660 but see also: http://www.hackersdelight.org/HDcode/nlz.cc */
1661 MVT::ValueType VT = Tmp1.getValueType();
1662 MVT::ValueType ShVT = TLI.getShiftAmountTy();
1663 unsigned len = getSizeInBits(VT);
1664 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
1665 Tmp3 = DAG.getConstant(1ULL << i, ShVT);
1666 Tmp1 = DAG.getNode(ISD::OR, VT, Tmp1,
1667 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3));
1669 Tmp3 = DAG.getNode(ISD::XOR, VT, Tmp1, DAG.getConstant(~0ULL, VT));
1670 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3));
1674 // for now, we use: { return popcount(~x & (x - 1)); }
1675 // unless the target has ctlz but not ctpop, in which case we use:
1676 // { return 32 - nlz(~x & (x-1)); }
1677 // see also http://www.hackersdelight.org/HDcode/ntz.cc
1678 MVT::ValueType VT = Tmp1.getValueType();
1679 Tmp2 = DAG.getConstant(~0ULL, VT);
1680 Tmp3 = DAG.getNode(ISD::AND, VT,
1681 DAG.getNode(ISD::XOR, VT, Tmp1, Tmp2),
1682 DAG.getNode(ISD::SUB, VT, Tmp1,
1683 DAG.getConstant(1, VT)));
1684 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead
1685 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
1686 TLI.isOperationLegal(ISD::CTLZ, VT)) {
1687 Result = LegalizeOp(DAG.getNode(ISD::SUB, VT,
1688 DAG.getConstant(getSizeInBits(VT), VT),
1689 DAG.getNode(ISD::CTLZ, VT, Tmp3)));
1691 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3));
1696 assert(0 && "Cannot expand this yet!");
1709 Tmp1 = LegalizeOp(Node->getOperand(0));
1710 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1711 case TargetLowering::Legal:
1712 if (Tmp1 != Node->getOperand(0))
1713 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
1715 case TargetLowering::Promote:
1716 case TargetLowering::Custom:
1717 assert(0 && "Cannot promote/custom handle this yet!");
1718 case TargetLowering::Expand:
1719 switch(Node->getOpcode()) {
1721 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
1722 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
1723 Result = LegalizeOp(DAG.getNode(ISD::FSUB, Node->getValueType(0),
1728 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
1729 MVT::ValueType VT = Node->getValueType(0);
1730 Tmp2 = DAG.getConstantFP(0.0, VT);
1731 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
1732 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
1733 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
1734 Result = LegalizeOp(Result);
1740 MVT::ValueType VT = Node->getValueType(0);
1741 const char *FnName = 0;
1742 switch(Node->getOpcode()) {
1743 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break;
1744 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break;
1745 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break;
1746 default: assert(0 && "Unreachable!");
1749 Result = ExpandLibCall(FnName, Node, Dummy);
1753 assert(0 && "Unreachable!");
1759 // Conversion operators. The source and destination have different types.
1760 case ISD::SINT_TO_FP:
1761 case ISD::UINT_TO_FP: {
1762 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
1763 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1765 switch (TLI.getOperationAction(Node->getOpcode(),
1766 Node->getOperand(0).getValueType())) {
1767 default: assert(0 && "Unknown operation action!");
1768 case TargetLowering::Expand:
1769 Result = ExpandLegalINT_TO_FP(isSigned,
1770 LegalizeOp(Node->getOperand(0)),
1771 Node->getValueType(0));
1772 AddLegalizedOperand(Op, Result);
1774 case TargetLowering::Promote:
1775 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
1776 Node->getValueType(0),
1778 AddLegalizedOperand(Op, Result);
1780 case TargetLowering::Legal:
1784 Tmp1 = LegalizeOp(Node->getOperand(0));
1785 if (Tmp1 != Node->getOperand(0))
1786 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
1789 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
1790 Node->getValueType(0), Node->getOperand(0));
1794 Result = PromoteOp(Node->getOperand(0));
1795 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1796 Result, DAG.getValueType(Node->getOperand(0).getValueType()));
1797 Result = DAG.getNode(ISD::SINT_TO_FP, Op.getValueType(), Result);
1799 Result = PromoteOp(Node->getOperand(0));
1800 Result = DAG.getZeroExtendInReg(Result,
1801 Node->getOperand(0).getValueType());
1802 Result = DAG.getNode(ISD::UINT_TO_FP, Op.getValueType(), Result);
1809 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1811 Tmp1 = LegalizeOp(Node->getOperand(0));
1812 if (Tmp1 != Node->getOperand(0))
1813 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
1816 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1818 // Since the result is legal, we should just be able to truncate the low
1819 // part of the source.
1820 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
1823 Result = PromoteOp(Node->getOperand(0));
1824 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
1829 case ISD::FP_TO_SINT:
1830 case ISD::FP_TO_UINT:
1831 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1833 Tmp1 = LegalizeOp(Node->getOperand(0));
1835 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
1836 default: assert(0 && "Unknown operation action!");
1837 case TargetLowering::Expand:
1838 if (Node->getOpcode() == ISD::FP_TO_UINT) {
1839 SDOperand True, False;
1840 MVT::ValueType VT = Node->getOperand(0).getValueType();
1841 MVT::ValueType NVT = Node->getValueType(0);
1842 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1;
1843 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT);
1844 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
1845 Node->getOperand(0), Tmp2, ISD::SETLT);
1846 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
1847 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
1848 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
1850 False = DAG.getNode(ISD::XOR, NVT, False,
1851 DAG.getConstant(1ULL << ShiftAmt, NVT));
1852 Result = LegalizeOp(DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False));
1855 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
1858 case TargetLowering::Promote:
1859 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
1860 Node->getOpcode() == ISD::FP_TO_SINT);
1861 AddLegalizedOperand(Op, Result);
1863 case TargetLowering::Custom: {
1865 DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
1866 Tmp = TLI.LowerOperation(Tmp, DAG);
1868 AddLegalizedOperand(Op, Tmp);
1869 NeedsAnotherIteration = true;
1872 // The target thinks this is legal afterall.
1876 case TargetLowering::Legal:
1880 if (Tmp1 != Node->getOperand(0))
1881 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
1884 assert(0 && "Shouldn't need to expand other operators here!");
1886 Result = PromoteOp(Node->getOperand(0));
1887 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
1892 case ISD::ANY_EXTEND:
1893 case ISD::ZERO_EXTEND:
1894 case ISD::SIGN_EXTEND:
1895 case ISD::FP_EXTEND:
1897 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1899 Tmp1 = LegalizeOp(Node->getOperand(0));
1900 if (Tmp1 != Node->getOperand(0))
1901 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
1904 assert(0 && "Shouldn't need to expand other operators here!");
1907 switch (Node->getOpcode()) {
1908 case ISD::ANY_EXTEND:
1909 Result = PromoteOp(Node->getOperand(0));
1910 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
1912 case ISD::ZERO_EXTEND:
1913 Result = PromoteOp(Node->getOperand(0));
1914 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
1915 Result = DAG.getZeroExtendInReg(Result,
1916 Node->getOperand(0).getValueType());
1918 case ISD::SIGN_EXTEND:
1919 Result = PromoteOp(Node->getOperand(0));
1920 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
1921 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1923 DAG.getValueType(Node->getOperand(0).getValueType()));
1925 case ISD::FP_EXTEND:
1926 Result = PromoteOp(Node->getOperand(0));
1927 if (Result.getValueType() != Op.getValueType())
1928 // Dynamically dead while we have only 2 FP types.
1929 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result);
1932 Result = PromoteOp(Node->getOperand(0));
1933 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
1938 case ISD::FP_ROUND_INREG:
1939 case ISD::SIGN_EXTEND_INREG: {
1940 Tmp1 = LegalizeOp(Node->getOperand(0));
1941 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
1943 // If this operation is not supported, convert it to a shl/shr or load/store
1945 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
1946 default: assert(0 && "This action not supported for this op yet!");
1947 case TargetLowering::Legal:
1948 if (Tmp1 != Node->getOperand(0))
1949 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,
1950 DAG.getValueType(ExtraVT));
1952 case TargetLowering::Expand:
1953 // If this is an integer extend and shifts are supported, do that.
1954 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
1955 // NOTE: we could fall back on load/store here too for targets without
1956 // SAR. However, it is doubtful that any exist.
1957 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
1958 MVT::getSizeInBits(ExtraVT);
1959 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
1960 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
1961 Node->getOperand(0), ShiftCst);
1962 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
1964 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
1965 // The only way we can lower this is to turn it into a STORETRUNC,
1966 // EXTLOAD pair, targetting a temporary location (a stack slot).
1968 // NOTE: there is a choice here between constantly creating new stack
1969 // slots and always reusing the same one. We currently always create
1970 // new ones, as reuse may inhibit scheduling.
1971 const Type *Ty = MVT::getTypeForValueType(ExtraVT);
1972 unsigned TySize = (unsigned)TLI.getTargetData().getTypeSize(Ty);
1973 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty);
1974 MachineFunction &MF = DAG.getMachineFunction();
1976 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
1977 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
1978 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(),
1979 Node->getOperand(0), StackSlot,
1980 DAG.getSrcValue(NULL), DAG.getValueType(ExtraVT));
1981 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
1982 Result, StackSlot, DAG.getSrcValue(NULL),
1985 assert(0 && "Unknown op");
1987 Result = LegalizeOp(Result);
1994 // Note that LegalizeOp may be reentered even from single-use nodes, which
1995 // means that we always must cache transformed nodes.
1996 AddLegalizedOperand(Op, Result);
2000 /// PromoteOp - Given an operation that produces a value in an invalid type,
2001 /// promote it to compute the value into a larger type. The produced value will
2002 /// have the correct bits for the low portion of the register, but no guarantee
2003 /// is made about the top bits: it may be zero, sign-extended, or garbage.
2004 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
2005 MVT::ValueType VT = Op.getValueType();
2006 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
2007 assert(getTypeAction(VT) == Promote &&
2008 "Caller should expand or legalize operands that are not promotable!");
2009 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
2010 "Cannot promote to smaller type!");
2012 SDOperand Tmp1, Tmp2, Tmp3;
2015 SDNode *Node = Op.Val;
2017 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
2018 if (I != PromotedNodes.end()) return I->second;
2020 // Promotion needs an optimization step to clean up after it, and is not
2021 // careful to avoid operations the target does not support. Make sure that
2022 // all generated operations are legalized in the next iteration.
2023 NeedsAnotherIteration = true;
2025 switch (Node->getOpcode()) {
2026 case ISD::CopyFromReg:
2027 assert(0 && "CopyFromReg must be legal!");
2029 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
2030 assert(0 && "Do not know how to promote this operator!");
2033 Result = DAG.getNode(ISD::UNDEF, NVT);
2037 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
2039 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
2040 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
2042 case ISD::ConstantFP:
2043 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
2044 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
2048 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
2049 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
2050 Node->getOperand(1), Node->getOperand(2));
2051 Result = LegalizeOp(Result);
2055 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2057 Result = LegalizeOp(Node->getOperand(0));
2058 assert(Result.getValueType() >= NVT &&
2059 "This truncation doesn't make sense!");
2060 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
2061 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
2064 // The truncation is not required, because we don't guarantee anything
2065 // about high bits anyway.
2066 Result = PromoteOp(Node->getOperand(0));
2069 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2070 // Truncate the low part of the expanded value to the result type
2071 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
2074 case ISD::SIGN_EXTEND:
2075 case ISD::ZERO_EXTEND:
2076 case ISD::ANY_EXTEND:
2077 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2078 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
2080 // Input is legal? Just do extend all the way to the larger type.
2081 Result = LegalizeOp(Node->getOperand(0));
2082 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
2085 // Promote the reg if it's smaller.
2086 Result = PromoteOp(Node->getOperand(0));
2087 // The high bits are not guaranteed to be anything. Insert an extend.
2088 if (Node->getOpcode() == ISD::SIGN_EXTEND)
2089 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
2090 DAG.getValueType(Node->getOperand(0).getValueType()));
2091 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
2092 Result = DAG.getZeroExtendInReg(Result,
2093 Node->getOperand(0).getValueType());
2098 case ISD::FP_EXTEND:
2099 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
2101 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2102 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
2103 case Promote: assert(0 && "Unreachable with 2 FP types!");
2105 // Input is legal? Do an FP_ROUND_INREG.
2106 Result = LegalizeOp(Node->getOperand(0));
2107 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2108 DAG.getValueType(VT));
2113 case ISD::SINT_TO_FP:
2114 case ISD::UINT_TO_FP:
2115 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2117 Result = LegalizeOp(Node->getOperand(0));
2118 // No extra round required here.
2119 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
2123 Result = PromoteOp(Node->getOperand(0));
2124 if (Node->getOpcode() == ISD::SINT_TO_FP)
2125 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2127 DAG.getValueType(Node->getOperand(0).getValueType()));
2129 Result = DAG.getZeroExtendInReg(Result,
2130 Node->getOperand(0).getValueType());
2131 // No extra round required here.
2132 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
2135 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
2136 Node->getOperand(0));
2137 // Round if we cannot tolerate excess precision.
2138 if (NoExcessFPPrecision)
2139 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2140 DAG.getValueType(VT));
2145 case ISD::FP_TO_SINT:
2146 case ISD::FP_TO_UINT:
2147 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2149 Tmp1 = LegalizeOp(Node->getOperand(0));
2152 // The input result is prerounded, so we don't have to do anything
2154 Tmp1 = PromoteOp(Node->getOperand(0));
2157 assert(0 && "not implemented");
2159 // If we're promoting a UINT to a larger size, check to see if the new node
2160 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
2161 // we can use that instead. This allows us to generate better code for
2162 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
2163 // legal, such as PowerPC.
2164 if (Node->getOpcode() == ISD::FP_TO_UINT &&
2165 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
2166 TLI.isOperationLegal(ISD::FP_TO_SINT, NVT)) {
2167 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
2169 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2175 Tmp1 = PromoteOp(Node->getOperand(0));
2176 assert(Tmp1.getValueType() == NVT);
2177 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2178 // NOTE: we do not have to do any extra rounding here for
2179 // NoExcessFPPrecision, because we know the input will have the appropriate
2180 // precision, and these operations don't modify precision at all.
2186 Tmp1 = PromoteOp(Node->getOperand(0));
2187 assert(Tmp1.getValueType() == NVT);
2188 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2189 if(NoExcessFPPrecision)
2190 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2191 DAG.getValueType(VT));
2200 // The input may have strange things in the top bits of the registers, but
2201 // these operations don't care. They may have weird bits going out, but
2202 // that too is okay if they are integer operations.
2203 Tmp1 = PromoteOp(Node->getOperand(0));
2204 Tmp2 = PromoteOp(Node->getOperand(1));
2205 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
2206 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2211 // The input may have strange things in the top bits of the registers, but
2212 // these operations don't care.
2213 Tmp1 = PromoteOp(Node->getOperand(0));
2214 Tmp2 = PromoteOp(Node->getOperand(1));
2215 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
2216 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2218 // Floating point operations will give excess precision that we may not be
2219 // able to tolerate. If we DO allow excess precision, just leave it,
2220 // otherwise excise it.
2221 // FIXME: Why would we need to round FP ops more than integer ones?
2222 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
2223 if (NoExcessFPPrecision)
2224 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2225 DAG.getValueType(VT));
2230 // These operators require that their input be sign extended.
2231 Tmp1 = PromoteOp(Node->getOperand(0));
2232 Tmp2 = PromoteOp(Node->getOperand(1));
2233 if (MVT::isInteger(NVT)) {
2234 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
2235 DAG.getValueType(VT));
2236 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
2237 DAG.getValueType(VT));
2239 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2241 // Perform FP_ROUND: this is probably overly pessimistic.
2242 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
2243 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2244 DAG.getValueType(VT));
2248 // These operators require that their input be fp extended.
2249 Tmp1 = PromoteOp(Node->getOperand(0));
2250 Tmp2 = PromoteOp(Node->getOperand(1));
2251 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2253 // Perform FP_ROUND: this is probably overly pessimistic.
2254 if (NoExcessFPPrecision)
2255 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2256 DAG.getValueType(VT));
2261 // These operators require that their input be zero extended.
2262 Tmp1 = PromoteOp(Node->getOperand(0));
2263 Tmp2 = PromoteOp(Node->getOperand(1));
2264 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
2265 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
2266 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
2267 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2271 Tmp1 = PromoteOp(Node->getOperand(0));
2272 Tmp2 = LegalizeOp(Node->getOperand(1));
2273 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Tmp2);
2276 // The input value must be properly sign extended.
2277 Tmp1 = PromoteOp(Node->getOperand(0));
2278 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
2279 DAG.getValueType(VT));
2280 Tmp2 = LegalizeOp(Node->getOperand(1));
2281 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Tmp2);
2284 // The input value must be properly zero extended.
2285 Tmp1 = PromoteOp(Node->getOperand(0));
2286 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
2287 Tmp2 = LegalizeOp(Node->getOperand(1));
2288 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Tmp2);
2291 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2292 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2293 // FIXME: When the DAG combiner exists, change this to use EXTLOAD!
2294 if (MVT::isInteger(NVT))
2295 Result = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Tmp1, Tmp2,
2296 Node->getOperand(2), VT);
2298 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp1, Tmp2,
2299 Node->getOperand(2), VT);
2301 // Remember that we legalized the chain.
2302 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
2305 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2306 case Expand: assert(0 && "It's impossible to expand bools");
2308 Tmp1 = LegalizeOp(Node->getOperand(0));// Legalize the condition.
2311 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2314 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
2315 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
2316 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2, Tmp3);
2318 case ISD::SELECT_CC:
2319 Tmp2 = PromoteOp(Node->getOperand(2)); // True
2320 Tmp3 = PromoteOp(Node->getOperand(3)); // False
2321 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
2322 Node->getOperand(1), Tmp2, Tmp3,
2323 Node->getOperand(4));
2327 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2328 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee.
2330 std::vector<SDOperand> Ops;
2331 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i)
2332 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2334 assert(Node->getNumValues() == 2 && Op.ResNo == 0 &&
2335 "Can only promote single result calls");
2336 std::vector<MVT::ValueType> RetTyVTs;
2337 RetTyVTs.reserve(2);
2338 RetTyVTs.push_back(NVT);
2339 RetTyVTs.push_back(MVT::Other);
2340 SDNode *NC = DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops,
2341 Node->getOpcode() == ISD::TAILCALL);
2342 Result = SDOperand(NC, 0);
2344 // Insert the new chain mapping.
2345 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
2351 Tmp1 = Node->getOperand(0);
2352 //Zero extend the argument
2353 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2354 // Perform the larger operation, then subtract if needed.
2355 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2356 switch(Node->getOpcode())
2362 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2363 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
2364 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ);
2365 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
2366 DAG.getConstant(getSizeInBits(VT),NVT), Tmp1);
2369 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2370 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
2371 DAG.getConstant(getSizeInBits(NVT) -
2372 getSizeInBits(VT), NVT));
2378 assert(Result.Val && "Didn't set a result!");
2379 AddPromotedOperand(Op, Result);
2383 /// ExpandAddSub - Find a clever way to expand this add operation into
2385 void SelectionDAGLegalize::
2386 ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS,
2387 SDOperand &Lo, SDOperand &Hi) {
2388 // Expand the subcomponents.
2389 SDOperand LHSL, LHSH, RHSL, RHSH;
2390 ExpandOp(LHS, LHSL, LHSH);
2391 ExpandOp(RHS, RHSL, RHSH);
2393 // FIXME: this should be moved to the dag combiner someday.
2394 assert(NodeOp == ISD::ADD_PARTS || NodeOp == ISD::SUB_PARTS);
2395 if (LHSL.getValueType() == MVT::i32) {
2397 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHSL))
2398 if (C->getValue() == 0)
2400 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHSL))
2401 if (C->getValue() == 0)
2404 // Turn this into an add/sub of the high part only.
2406 DAG.getNode(NodeOp == ISD::ADD_PARTS ? ISD::ADD : ISD::SUB,
2407 LowEl.getValueType(), LHSH, RHSH);
2414 std::vector<SDOperand> Ops;
2415 Ops.push_back(LHSL);
2416 Ops.push_back(LHSH);
2417 Ops.push_back(RHSL);
2418 Ops.push_back(RHSH);
2420 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType());
2421 Lo = DAG.getNode(NodeOp, VTs, Ops);
2422 Hi = Lo.getValue(1);
2425 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
2426 SDOperand Op, SDOperand Amt,
2427 SDOperand &Lo, SDOperand &Hi) {
2428 // Expand the subcomponents.
2429 SDOperand LHSL, LHSH;
2430 ExpandOp(Op, LHSL, LHSH);
2432 std::vector<SDOperand> Ops;
2433 Ops.push_back(LHSL);
2434 Ops.push_back(LHSH);
2436 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType());
2437 Lo = DAG.getNode(NodeOp, VTs, Ops);
2438 Hi = Lo.getValue(1);
2442 /// ExpandShift - Try to find a clever way to expand this shift operation out to
2443 /// smaller elements. If we can't find a way that is more efficient than a
2444 /// libcall on this target, return false. Otherwise, return true with the
2445 /// low-parts expanded into Lo and Hi.
2446 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
2447 SDOperand &Lo, SDOperand &Hi) {
2448 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
2449 "This is not a shift!");
2451 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
2452 SDOperand ShAmt = LegalizeOp(Amt);
2453 MVT::ValueType ShTy = ShAmt.getValueType();
2454 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
2455 unsigned NVTBits = MVT::getSizeInBits(NVT);
2457 // Handle the case when Amt is an immediate. Other cases are currently broken
2458 // and are disabled.
2459 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
2460 unsigned Cst = CN->getValue();
2461 // Expand the incoming operand to be shifted, so that we have its parts
2463 ExpandOp(Op, InL, InH);
2467 Lo = DAG.getConstant(0, NVT);
2468 Hi = DAG.getConstant(0, NVT);
2469 } else if (Cst > NVTBits) {
2470 Lo = DAG.getConstant(0, NVT);
2471 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
2472 } else if (Cst == NVTBits) {
2473 Lo = DAG.getConstant(0, NVT);
2476 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
2477 Hi = DAG.getNode(ISD::OR, NVT,
2478 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
2479 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
2484 Lo = DAG.getConstant(0, NVT);
2485 Hi = DAG.getConstant(0, NVT);
2486 } else if (Cst > NVTBits) {
2487 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
2488 Hi = DAG.getConstant(0, NVT);
2489 } else if (Cst == NVTBits) {
2491 Hi = DAG.getConstant(0, NVT);
2493 Lo = DAG.getNode(ISD::OR, NVT,
2494 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
2495 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
2496 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
2501 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
2502 DAG.getConstant(NVTBits-1, ShTy));
2503 } else if (Cst > NVTBits) {
2504 Lo = DAG.getNode(ISD::SRA, NVT, InH,
2505 DAG.getConstant(Cst-NVTBits, ShTy));
2506 Hi = DAG.getNode(ISD::SRA, NVT, InH,
2507 DAG.getConstant(NVTBits-1, ShTy));
2508 } else if (Cst == NVTBits) {
2510 Hi = DAG.getNode(ISD::SRA, NVT, InH,
2511 DAG.getConstant(NVTBits-1, ShTy));
2513 Lo = DAG.getNode(ISD::OR, NVT,
2514 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
2515 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
2516 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
2521 // FIXME: The following code for expanding shifts using ISD::SELECT is buggy,
2522 // so disable it for now. Currently targets are handling this via SHL_PARTS
2526 // If we have an efficient select operation (or if the selects will all fold
2527 // away), lower to some complex code, otherwise just emit the libcall.
2528 if (!TLI.isOperationLegal(ISD::SELECT, NVT) && !isa<ConstantSDNode>(Amt))
2532 ExpandOp(Op, InL, InH);
2533 SDOperand NAmt = DAG.getNode(ISD::SUB, ShTy, // NAmt = 32-ShAmt
2534 DAG.getConstant(NVTBits, ShTy), ShAmt);
2536 // Compare the unmasked shift amount against 32.
2537 SDOperand Cond = DAG.getSetCC(TLI.getSetCCResultTy(), ShAmt,
2538 DAG.getConstant(NVTBits, ShTy), ISD::SETGE);
2540 if (TLI.getShiftAmountFlavor() != TargetLowering::Mask) {
2541 ShAmt = DAG.getNode(ISD::AND, ShTy, ShAmt, // ShAmt &= 31
2542 DAG.getConstant(NVTBits-1, ShTy));
2543 NAmt = DAG.getNode(ISD::AND, ShTy, NAmt, // NAmt &= 31
2544 DAG.getConstant(NVTBits-1, ShTy));
2547 if (Opc == ISD::SHL) {
2548 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << Amt) | (Lo >> NAmt)
2549 DAG.getNode(ISD::SHL, NVT, InH, ShAmt),
2550 DAG.getNode(ISD::SRL, NVT, InL, NAmt));
2551 SDOperand T2 = DAG.getNode(ISD::SHL, NVT, InL, ShAmt); // T2 = Lo << Amt&31
2553 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1);
2554 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, DAG.getConstant(0, NVT), T2);
2556 SDOperand HiLoPart = DAG.getNode(ISD::SELECT, NVT,
2557 DAG.getSetCC(TLI.getSetCCResultTy(), NAmt,
2558 DAG.getConstant(32, ShTy),
2560 DAG.getConstant(0, NVT),
2561 DAG.getNode(ISD::SHL, NVT, InH, NAmt));
2562 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << NAmt) | (Lo >> Amt)
2564 DAG.getNode(ISD::SRL, NVT, InL, ShAmt));
2565 SDOperand T2 = DAG.getNode(Opc, NVT, InH, ShAmt); // T2 = InH >> ShAmt&31
2568 if (Opc == ISD::SRA)
2569 HiPart = DAG.getNode(ISD::SRA, NVT, InH,
2570 DAG.getConstant(NVTBits-1, ShTy));
2572 HiPart = DAG.getConstant(0, NVT);
2573 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1);
2574 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, HiPart, T2);
2579 /// FindLatestCallSeqStart - Scan up the dag to find the latest (highest
2580 /// NodeDepth) node that is an CallSeqStart operation and occurs later than
2582 static void FindLatestCallSeqStart(SDNode *Node, SDNode *&Found) {
2583 if (Node->getNodeDepth() <= Found->getNodeDepth()) return;
2585 // If we found an CALLSEQ_START, we already know this node occurs later
2586 // than the Found node. Just remember this node and return.
2587 if (Node->getOpcode() == ISD::CALLSEQ_START) {
2592 // Otherwise, scan the operands of Node to see if any of them is a call.
2593 assert(Node->getNumOperands() != 0 &&
2594 "All leaves should have depth equal to the entry node!");
2595 for (unsigned i = 0, e = Node->getNumOperands()-1; i != e; ++i)
2596 FindLatestCallSeqStart(Node->getOperand(i).Val, Found);
2598 // Tail recurse for the last iteration.
2599 FindLatestCallSeqStart(Node->getOperand(Node->getNumOperands()-1).Val,
2604 /// FindEarliestCallSeqEnd - Scan down the dag to find the earliest (lowest
2605 /// NodeDepth) node that is an CallSeqEnd operation and occurs more recent
2607 static void FindEarliestCallSeqEnd(SDNode *Node, SDNode *&Found,
2608 std::set<SDNode*> &Visited) {
2609 if ((Found && Node->getNodeDepth() >= Found->getNodeDepth()) ||
2610 !Visited.insert(Node).second) return;
2612 // If we found an CALLSEQ_END, we already know this node occurs earlier
2613 // than the Found node. Just remember this node and return.
2614 if (Node->getOpcode() == ISD::CALLSEQ_END) {
2619 // Otherwise, scan the operands of Node to see if any of them is a call.
2620 SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
2621 if (UI == E) return;
2622 for (--E; UI != E; ++UI)
2623 FindEarliestCallSeqEnd(*UI, Found, Visited);
2625 // Tail recurse for the last iteration.
2626 FindEarliestCallSeqEnd(*UI, Found, Visited);
2629 /// FindCallSeqEnd - Given a chained node that is part of a call sequence,
2630 /// find the CALLSEQ_END node that terminates the call sequence.
2631 static SDNode *FindCallSeqEnd(SDNode *Node) {
2632 if (Node->getOpcode() == ISD::CALLSEQ_END)
2634 if (Node->use_empty())
2635 return 0; // No CallSeqEnd
2637 if (Node->hasOneUse()) // Simple case, only has one user to check.
2638 return FindCallSeqEnd(*Node->use_begin());
2640 SDOperand TheChain(Node, Node->getNumValues()-1);
2641 if (TheChain.getValueType() != MVT::Other)
2642 TheChain = SDOperand(Node, 0);
2643 assert(TheChain.getValueType() == MVT::Other && "Is not a token chain!");
2645 for (SDNode::use_iterator UI = Node->use_begin(),
2646 E = Node->use_end(); UI != E; ++UI) {
2648 // Make sure to only follow users of our token chain.
2650 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
2651 if (User->getOperand(i) == TheChain)
2652 if (SDNode *Result = FindCallSeqEnd(User))
2658 /// FindCallSeqStart - Given a chained node that is part of a call sequence,
2659 /// find the CALLSEQ_START node that initiates the call sequence.
2660 static SDNode *FindCallSeqStart(SDNode *Node) {
2661 assert(Node && "Didn't find callseq_start for a call??");
2662 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
2664 assert(Node->getOperand(0).getValueType() == MVT::Other &&
2665 "Node doesn't have a token chain argument!");
2666 return FindCallSeqStart(Node->getOperand(0).Val);
2670 /// FindInputOutputChains - If we are replacing an operation with a call we need
2671 /// to find the call that occurs before and the call that occurs after it to
2672 /// properly serialize the calls in the block. The returned operand is the
2673 /// input chain value for the new call (e.g. the entry node or the previous
2674 /// call), and OutChain is set to be the chain node to update to point to the
2675 /// end of the call chain.
2676 static SDOperand FindInputOutputChains(SDNode *OpNode, SDNode *&OutChain,
2678 SDNode *LatestCallSeqStart = Entry.Val;
2679 SDNode *LatestCallSeqEnd = 0;
2680 FindLatestCallSeqStart(OpNode, LatestCallSeqStart);
2681 //std::cerr<<"Found node: "; LatestCallSeqStart->dump(); std::cerr <<"\n";
2683 // It is possible that no ISD::CALLSEQ_START was found because there is no
2684 // previous call in the function. LatestCallStackDown may in that case be
2685 // the entry node itself. Do not attempt to find a matching CALLSEQ_END
2686 // unless LatestCallStackDown is an CALLSEQ_START.
2687 if (LatestCallSeqStart->getOpcode() == ISD::CALLSEQ_START)
2688 LatestCallSeqEnd = FindCallSeqEnd(LatestCallSeqStart);
2690 LatestCallSeqEnd = Entry.Val;
2691 assert(LatestCallSeqEnd && "NULL return from FindCallSeqEnd");
2693 // Finally, find the first call that this must come before, first we find the
2694 // CallSeqEnd that ends the call.
2696 std::set<SDNode*> Visited;
2697 FindEarliestCallSeqEnd(OpNode, OutChain, Visited);
2699 // If we found one, translate from the adj up to the callseq_start.
2701 OutChain = FindCallSeqStart(OutChain);
2703 return SDOperand(LatestCallSeqEnd, 0);
2706 /// SpliceCallInto - Given the result chain of a libcall (CallResult), and a
2707 void SelectionDAGLegalize::SpliceCallInto(const SDOperand &CallResult,
2709 // Nothing to splice it into?
2710 if (OutChain == 0) return;
2712 assert(OutChain->getOperand(0).getValueType() == MVT::Other);
2715 // Form a token factor node merging the old inval and the new inval.
2716 SDOperand InToken = DAG.getNode(ISD::TokenFactor, MVT::Other, CallResult,
2717 OutChain->getOperand(0));
2718 // Change the node to refer to the new token.
2719 OutChain->setAdjCallChain(InToken);
2723 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
2724 // does not fit into a register, return the lo part and set the hi part to the
2725 // by-reg argument. If it does fit into a single register, return the result
2726 // and leave the Hi part unset.
2727 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
2730 SDOperand InChain = FindInputOutputChains(Node, OutChain,
2731 DAG.getEntryNode());
2732 if (InChain.Val == 0)
2733 InChain = DAG.getEntryNode();
2735 TargetLowering::ArgListTy Args;
2736 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2737 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
2738 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
2739 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy));
2741 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
2743 // Splice the libcall in wherever FindInputOutputChains tells us to.
2744 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
2745 std::pair<SDOperand,SDOperand> CallInfo =
2746 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, false,
2750 switch (getTypeAction(CallInfo.first.getValueType())) {
2751 default: assert(0 && "Unknown thing");
2753 Result = CallInfo.first;
2756 assert(0 && "Cannot promote this yet!");
2758 ExpandOp(CallInfo.first, Result, Hi);
2759 CallInfo.second = LegalizeOp(CallInfo.second);
2763 SpliceCallInto(CallInfo.second, OutChain);
2764 NeedsAnotherIteration = true;
2769 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the
2770 /// destination type is legal.
2771 SDOperand SelectionDAGLegalize::
2772 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
2773 assert(isTypeLegal(DestTy) && "Destination type is not legal!");
2774 assert(getTypeAction(Source.getValueType()) == Expand &&
2775 "This is not an expansion!");
2776 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
2779 assert(Source.getValueType() == MVT::i64 &&
2780 "This only works for 64-bit -> FP");
2781 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
2782 // incoming integer is set. To handle this, we dynamically test to see if
2783 // it is set, and, if so, add a fudge factor.
2785 ExpandOp(Source, Lo, Hi);
2787 // If this is unsigned, and not supported, first perform the conversion to
2788 // signed, then adjust the result if the sign bit is set.
2789 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
2790 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
2792 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
2793 DAG.getConstant(0, Hi.getValueType()),
2795 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
2796 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
2797 SignSet, Four, Zero);
2798 uint64_t FF = 0x5f800000ULL;
2799 if (TLI.isLittleEndian()) FF <<= 32;
2800 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
2802 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
2803 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
2804 SDOperand FudgeInReg;
2805 if (DestTy == MVT::f32)
2806 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
2807 DAG.getSrcValue(NULL));
2809 assert(DestTy == MVT::f64 && "Unexpected conversion");
2810 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
2811 CPIdx, DAG.getSrcValue(NULL), MVT::f32);
2813 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
2816 // Check to see if the target has a custom way to lower this. If so, use it.
2817 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
2818 default: assert(0 && "This action not implemented for this operation!");
2819 case TargetLowering::Legal:
2820 case TargetLowering::Expand:
2821 break; // This case is handled below.
2822 case TargetLowering::Custom: {
2823 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
2826 return LegalizeOp(NV);
2827 break; // The target decided this was legal after all
2831 // Expand the source, then glue it back together for the call. We must expand
2832 // the source in case it is shared (this pass of legalize must traverse it).
2833 SDOperand SrcLo, SrcHi;
2834 ExpandOp(Source, SrcLo, SrcHi);
2835 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
2837 SDNode *OutChain = 0;
2838 SDOperand InChain = FindInputOutputChains(Source.Val, OutChain,
2839 DAG.getEntryNode());
2840 const char *FnName = 0;
2841 if (DestTy == MVT::f32)
2842 FnName = "__floatdisf";
2844 assert(DestTy == MVT::f64 && "Unknown fp value type!");
2845 FnName = "__floatdidf";
2848 SDOperand Callee = DAG.getExternalSymbol(FnName, TLI.getPointerTy());
2850 TargetLowering::ArgListTy Args;
2851 const Type *ArgTy = MVT::getTypeForValueType(Source.getValueType());
2853 Args.push_back(std::make_pair(Source, ArgTy));
2855 // We don't care about token chains for libcalls. We just use the entry
2856 // node as our input and ignore the output chain. This allows us to place
2857 // calls wherever we need them to satisfy data dependences.
2858 const Type *RetTy = MVT::getTypeForValueType(DestTy);
2860 std::pair<SDOperand,SDOperand> CallResult =
2861 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, true,
2864 SpliceCallInto(CallResult.second, OutChain);
2865 return CallResult.first;
2870 /// ExpandOp - Expand the specified SDOperand into its two component pieces
2871 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
2872 /// LegalizeNodes map is filled in for any results that are not expanded, the
2873 /// ExpandedNodes map is filled in for any results that are expanded, and the
2874 /// Lo/Hi values are returned.
2875 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
2876 MVT::ValueType VT = Op.getValueType();
2877 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
2878 SDNode *Node = Op.Val;
2879 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
2880 assert(MVT::isInteger(VT) && "Cannot expand FP values!");
2881 assert(MVT::isInteger(NVT) && NVT < VT &&
2882 "Cannot expand to FP value or to larger int value!");
2884 // See if we already expanded it.
2885 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
2886 = ExpandedNodes.find(Op);
2887 if (I != ExpandedNodes.end()) {
2888 Lo = I->second.first;
2889 Hi = I->second.second;
2893 // Expanding to multiple registers needs to perform an optimization step, and
2894 // is not careful to avoid operations the target does not support. Make sure
2895 // that all generated operations are legalized in the next iteration.
2896 NeedsAnotherIteration = true;
2898 switch (Node->getOpcode()) {
2899 case ISD::CopyFromReg:
2900 assert(0 && "CopyFromReg must be legal!");
2902 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
2903 assert(0 && "Do not know how to expand this operator!");
2906 Lo = DAG.getNode(ISD::UNDEF, NVT);
2907 Hi = DAG.getNode(ISD::UNDEF, NVT);
2909 case ISD::Constant: {
2910 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
2911 Lo = DAG.getConstant(Cst, NVT);
2912 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
2916 case ISD::BUILD_PAIR:
2917 // Legalize both operands. FIXME: in the future we should handle the case
2918 // where the two elements are not legal.
2919 assert(isTypeLegal(NVT) && "Cannot expand this multiple times yet!");
2920 Lo = LegalizeOp(Node->getOperand(0));
2921 Hi = LegalizeOp(Node->getOperand(1));
2925 ExpandOp(Node->getOperand(0), Lo, Hi);
2926 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
2927 DAG.getNode(ISD::CTPOP, NVT, Lo),
2928 DAG.getNode(ISD::CTPOP, NVT, Hi));
2929 Hi = DAG.getConstant(0, NVT);
2933 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
2934 ExpandOp(Node->getOperand(0), Lo, Hi);
2935 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
2936 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
2937 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
2939 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
2940 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
2942 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
2943 Hi = DAG.getConstant(0, NVT);
2948 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
2949 ExpandOp(Node->getOperand(0), Lo, Hi);
2950 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
2951 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
2952 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
2954 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
2955 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
2957 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
2958 Hi = DAG.getConstant(0, NVT);
2963 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2964 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2965 Lo = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
2967 // Increment the pointer to the other half.
2968 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
2969 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
2970 getIntPtrConstant(IncrementSize));
2971 //Is this safe? declaring that the two parts of the split load
2972 //are from the same instruction?
2973 Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
2975 // Build a factor node to remember that this load is independent of the
2977 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2980 // Remember that we legalized the chain.
2981 AddLegalizedOperand(Op.getValue(1), TF);
2982 if (!TLI.isLittleEndian())
2988 SDOperand Chain = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2989 SDOperand Callee = LegalizeOp(Node->getOperand(1)); // Legalize the callee.
2991 bool Changed = false;
2992 std::vector<SDOperand> Ops;
2993 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) {
2994 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2995 Changed |= Ops.back() != Node->getOperand(i);
2998 assert(Node->getNumValues() == 2 && Op.ResNo == 0 &&
2999 "Can only expand a call once so far, not i64 -> i16!");
3001 std::vector<MVT::ValueType> RetTyVTs;
3002 RetTyVTs.reserve(3);
3003 RetTyVTs.push_back(NVT);
3004 RetTyVTs.push_back(NVT);
3005 RetTyVTs.push_back(MVT::Other);
3006 SDNode *NC = DAG.getCall(RetTyVTs, Chain, Callee, Ops,
3007 Node->getOpcode() == ISD::TAILCALL);
3008 Lo = SDOperand(NC, 0);
3009 Hi = SDOperand(NC, 1);
3011 // Insert the new chain mapping.
3012 AddLegalizedOperand(Op.getValue(1), Hi.getValue(2));
3017 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
3018 SDOperand LL, LH, RL, RH;
3019 ExpandOp(Node->getOperand(0), LL, LH);
3020 ExpandOp(Node->getOperand(1), RL, RH);
3021 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
3022 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
3026 SDOperand C, LL, LH, RL, RH;
3028 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3029 case Expand: assert(0 && "It's impossible to expand bools");
3031 C = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
3034 C = PromoteOp(Node->getOperand(0)); // Promote the condition.
3037 ExpandOp(Node->getOperand(1), LL, LH);
3038 ExpandOp(Node->getOperand(2), RL, RH);
3039 Lo = DAG.getNode(ISD::SELECT, NVT, C, LL, RL);
3040 Hi = DAG.getNode(ISD::SELECT, NVT, C, LH, RH);
3043 case ISD::SELECT_CC: {
3044 SDOperand TL, TH, FL, FH;
3045 ExpandOp(Node->getOperand(2), TL, TH);
3046 ExpandOp(Node->getOperand(3), FL, FH);
3047 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3048 Node->getOperand(1), TL, FL, Node->getOperand(4));
3049 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3050 Node->getOperand(1), TH, FH, Node->getOperand(4));
3051 Lo = LegalizeOp(Lo);
3052 Hi = LegalizeOp(Hi);
3055 case ISD::ANY_EXTEND: {
3057 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3058 case Expand: assert(0 && "expand-expand not implemented yet!");
3059 case Legal: In = LegalizeOp(Node->getOperand(0)); break;
3061 In = PromoteOp(Node->getOperand(0));
3065 // The low part is any extension of the input (which degenerates to a copy).
3066 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, In);
3067 // The high part is undefined.
3068 Hi = DAG.getNode(ISD::UNDEF, NVT);
3071 case ISD::SIGN_EXTEND: {
3073 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3074 case Expand: assert(0 && "expand-expand not implemented yet!");
3075 case Legal: In = LegalizeOp(Node->getOperand(0)); break;
3077 In = PromoteOp(Node->getOperand(0));
3078 // Emit the appropriate sign_extend_inreg to get the value we want.
3079 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(), In,
3080 DAG.getValueType(Node->getOperand(0).getValueType()));
3084 // The low part is just a sign extension of the input (which degenerates to
3086 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, In);
3088 // The high part is obtained by SRA'ing all but one of the bits of the lo
3090 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
3091 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1,
3092 TLI.getShiftAmountTy()));
3095 case ISD::ZERO_EXTEND: {
3097 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3098 case Expand: assert(0 && "expand-expand not implemented yet!");
3099 case Legal: In = LegalizeOp(Node->getOperand(0)); break;
3101 In = PromoteOp(Node->getOperand(0));
3102 // Emit the appropriate zero_extend_inreg to get the value we want.
3103 In = DAG.getZeroExtendInReg(In, Node->getOperand(0).getValueType());
3107 // The low part is just a zero extension of the input (which degenerates to
3109 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, In);
3111 // The high part is just a zero.
3112 Hi = DAG.getConstant(0, NVT);
3115 // These operators cannot be expanded directly, emit them as calls to
3116 // library functions.
3117 case ISD::FP_TO_SINT:
3118 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
3120 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3121 case Expand: assert(0 && "cannot expand FP!");
3122 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
3123 case Promote: Op = PromoteOp(Node->getOperand(0)); break;
3126 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
3128 // Now that the custom expander is done, expand the result, which is still
3131 ExpandOp(Op, Lo, Hi);
3136 if (Node->getOperand(0).getValueType() == MVT::f32)
3137 Lo = ExpandLibCall("__fixsfdi", Node, Hi);
3139 Lo = ExpandLibCall("__fixdfdi", Node, Hi);
3142 case ISD::FP_TO_UINT:
3143 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
3144 SDOperand Op = DAG.getNode(ISD::FP_TO_UINT, VT,
3145 LegalizeOp(Node->getOperand(0)));
3146 // Now that the custom expander is done, expand the result, which is still
3148 Op = TLI.LowerOperation(Op, DAG);
3150 ExpandOp(Op, Lo, Hi);
3155 if (Node->getOperand(0).getValueType() == MVT::f32)
3156 Lo = ExpandLibCall("__fixunssfdi", Node, Hi);
3158 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi);
3162 // If the target wants custom lowering, do so.
3163 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
3164 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0),
3165 LegalizeOp(Node->getOperand(1)));
3166 Op = TLI.LowerOperation(Op, DAG);
3168 // Now that the custom expander is done, expand the result, which is
3170 ExpandOp(Op, Lo, Hi);
3175 // If we can emit an efficient shift operation, do so now.
3176 if (ExpandShift(ISD::SHL, Node->getOperand(0), Node->getOperand(1), Lo, Hi))
3179 // If this target supports SHL_PARTS, use it.
3180 if (TLI.isOperationLegal(ISD::SHL_PARTS, NVT)) {
3181 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), Node->getOperand(1),
3186 // Otherwise, emit a libcall.
3187 Lo = ExpandLibCall("__ashldi3", Node, Hi);
3191 // If the target wants custom lowering, do so.
3192 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
3193 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0),
3194 LegalizeOp(Node->getOperand(1)));
3195 Op = TLI.LowerOperation(Op, DAG);
3197 // Now that the custom expander is done, expand the result, which is
3199 ExpandOp(Op, Lo, Hi);
3204 // If we can emit an efficient shift operation, do so now.
3205 if (ExpandShift(ISD::SRA, Node->getOperand(0), Node->getOperand(1), Lo, Hi))
3208 // If this target supports SRA_PARTS, use it.
3209 if (TLI.isOperationLegal(ISD::SRA_PARTS, NVT)) {
3210 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), Node->getOperand(1),
3215 // Otherwise, emit a libcall.
3216 Lo = ExpandLibCall("__ashrdi3", Node, Hi);
3219 // If the target wants custom lowering, do so.
3220 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
3221 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0),
3222 LegalizeOp(Node->getOperand(1)));
3223 Op = TLI.LowerOperation(Op, DAG);
3225 // Now that the custom expander is done, expand the result, which is
3227 ExpandOp(Op, Lo, Hi);
3232 // If we can emit an efficient shift operation, do so now.
3233 if (ExpandShift(ISD::SRL, Node->getOperand(0), Node->getOperand(1), Lo, Hi))
3236 // If this target supports SRL_PARTS, use it.
3237 if (TLI.isOperationLegal(ISD::SRL_PARTS, NVT)) {
3238 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), Node->getOperand(1),
3243 // Otherwise, emit a libcall.
3244 Lo = ExpandLibCall("__lshrdi3", Node, Hi);
3248 ExpandByParts(ISD::ADD_PARTS, Node->getOperand(0), Node->getOperand(1),
3252 ExpandByParts(ISD::SUB_PARTS, Node->getOperand(0), Node->getOperand(1),
3256 if (TLI.isOperationLegal(ISD::MULHU, NVT)) {
3257 SDOperand LL, LH, RL, RH;
3258 ExpandOp(Node->getOperand(0), LL, LH);
3259 ExpandOp(Node->getOperand(1), RL, RH);
3260 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1;
3261 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp
3262 // extended the sign bit of the low half through the upper half, and if so
3263 // emit a MULHS instead of the alternate sequence that is valid for any
3264 // i64 x i64 multiply.
3265 if (TLI.isOperationLegal(ISD::MULHS, NVT) &&
3266 // is RH an extension of the sign bit of RL?
3267 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL &&
3268 RH.getOperand(1).getOpcode() == ISD::Constant &&
3269 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH &&
3270 // is LH an extension of the sign bit of LL?
3271 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL &&
3272 LH.getOperand(1).getOpcode() == ISD::Constant &&
3273 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) {
3274 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
3276 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
3277 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
3278 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
3279 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
3280 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
3282 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
3284 Lo = ExpandLibCall("__muldi3" , Node, Hi); break;
3288 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break;
3289 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break;
3290 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break;
3291 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break;
3294 // Remember in a map if the values will be reused later.
3295 bool isNew = ExpandedNodes.insert(std::make_pair(Op,
3296 std::make_pair(Lo, Hi))).second;
3297 assert(isNew && "Value already expanded?!?");
3301 // SelectionDAG::Legalize - This is the entry point for the file.
3303 void SelectionDAG::Legalize() {
3304 /// run - This is the main entry point to this class.
3306 SelectionDAGLegalize(*this).Run();