1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Analysis/DebugInfo.h"
15 #include "llvm/CodeGen/Analysis.h"
16 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/SelectionDAG.h"
19 #include "llvm/Target/TargetFrameLowering.h"
20 #include "llvm/Target/TargetLowering.h"
21 #include "llvm/Target/TargetData.h"
22 #include "llvm/Target/TargetMachine.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/Constants.h"
25 #include "llvm/DerivedTypes.h"
26 #include "llvm/LLVMContext.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/MathExtras.h"
30 #include "llvm/Support/raw_ostream.h"
31 #include "llvm/ADT/DenseMap.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/SmallPtrSet.h"
36 //===----------------------------------------------------------------------===//
37 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
38 /// hacks on it until the target machine can handle it. This involves
39 /// eliminating value sizes the machine cannot handle (promoting small sizes to
40 /// large sizes or splitting up large values into small values) as well as
41 /// eliminating operations the machine cannot handle.
43 /// This code also does a small amount of optimization and recognition of idioms
44 /// as part of its processing. For example, if a target does not support a
45 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
46 /// will attempt merge setcc and brc instructions into brcc's.
49 class SelectionDAGLegalize {
50 const TargetMachine &TM;
51 const TargetLowering &TLI;
54 // Libcall insertion helpers.
56 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
57 /// legalized. We use this to ensure that calls are properly serialized
58 /// against each other, including inserted libcalls.
59 SDValue LastCALLSEQ_END;
61 /// IsLegalizingCall - This member is used *only* for purposes of providing
62 /// helpful assertions that a libcall isn't created while another call is
63 /// being legalized (which could lead to non-serialized call sequences).
64 bool IsLegalizingCall;
66 /// LegalizedNodes - For nodes that are of legal width, and that have more
67 /// than one use, this map indicates what regularized operand to use. This
68 /// allows us to avoid legalizing the same thing more than once.
69 DenseMap<SDValue, SDValue> LegalizedNodes;
71 void AddLegalizedOperand(SDValue From, SDValue To) {
72 LegalizedNodes.insert(std::make_pair(From, To));
73 // If someone requests legalization of the new node, return itself.
75 LegalizedNodes.insert(std::make_pair(To, To));
77 // Transfer SDDbgValues.
78 DAG.TransferDbgValues(From, To);
82 explicit SelectionDAGLegalize(SelectionDAG &DAG);
87 /// LegalizeOp - Return a legal replacement for the given operation, with
88 /// all legal operands.
89 SDValue LegalizeOp(SDValue O);
91 SDValue OptimizeFloatStore(StoreSDNode *ST);
93 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
94 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
95 /// is necessary to spill the vector being inserted into to memory, perform
96 /// the insert there, and then read the result back.
97 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
98 SDValue Idx, DebugLoc dl);
99 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
100 SDValue Idx, DebugLoc dl);
102 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
103 /// performs the same shuffe in terms of order or result bytes, but on a type
104 /// whose vector element type is narrower than the original shuffle type.
105 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
106 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
107 SDValue N1, SDValue N2,
108 SmallVectorImpl<int> &Mask) const;
110 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
111 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
113 void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
116 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
117 SDValue ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops,
118 unsigned NumOps, bool isSigned, DebugLoc dl);
120 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
121 SDNode *Node, bool isSigned);
122 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
123 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
124 RTLIB::Libcall Call_PPCF128);
125 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
126 RTLIB::Libcall Call_I8,
127 RTLIB::Libcall Call_I16,
128 RTLIB::Libcall Call_I32,
129 RTLIB::Libcall Call_I64,
130 RTLIB::Libcall Call_I128);
131 void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
133 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl);
134 SDValue ExpandBUILD_VECTOR(SDNode *Node);
135 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
136 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
137 SmallVectorImpl<SDValue> &Results);
138 SDValue ExpandFCOPYSIGN(SDNode *Node);
139 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
141 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
143 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
146 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl);
147 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl);
149 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
150 SDValue ExpandInsertToVectorThroughStack(SDValue Op);
151 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
153 std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node);
155 void ExpandNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
156 void PromoteNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
160 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
161 /// performs the same shuffe in terms of order or result bytes, but on a type
162 /// whose vector element type is narrower than the original shuffle type.
163 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
165 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
166 SDValue N1, SDValue N2,
167 SmallVectorImpl<int> &Mask) const {
168 unsigned NumMaskElts = VT.getVectorNumElements();
169 unsigned NumDestElts = NVT.getVectorNumElements();
170 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
172 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
174 if (NumEltsGrowth == 1)
175 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
177 SmallVector<int, 8> NewMask;
178 for (unsigned i = 0; i != NumMaskElts; ++i) {
180 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
182 NewMask.push_back(-1);
184 NewMask.push_back(Idx * NumEltsGrowth + j);
187 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
188 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
189 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
192 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
193 : TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()),
197 void SelectionDAGLegalize::LegalizeDAG() {
198 LastCALLSEQ_END = DAG.getEntryNode();
199 IsLegalizingCall = false;
201 // The legalize process is inherently a bottom-up recursive process (users
202 // legalize their uses before themselves). Given infinite stack space, we
203 // could just start legalizing on the root and traverse the whole graph. In
204 // practice however, this causes us to run out of stack space on large basic
205 // blocks. To avoid this problem, compute an ordering of the nodes where each
206 // node is only legalized after all of its operands are legalized.
207 DAG.AssignTopologicalOrder();
208 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
209 E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I)
210 LegalizeOp(SDValue(I, 0));
212 // Finally, it's possible the root changed. Get the new root.
213 SDValue OldRoot = DAG.getRoot();
214 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
215 DAG.setRoot(LegalizedNodes[OldRoot]);
217 LegalizedNodes.clear();
219 // Remove dead nodes now.
220 DAG.RemoveDeadNodes();
224 /// FindCallEndFromCallStart - Given a chained node that is part of a call
225 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
226 static SDNode *FindCallEndFromCallStart(SDNode *Node, int depth = 0) {
227 // Nested CALLSEQ_START/END constructs aren't yet legal,
228 // but we can DTRT and handle them correctly here.
229 if (Node->getOpcode() == ISD::CALLSEQ_START)
231 else if (Node->getOpcode() == ISD::CALLSEQ_END) {
236 if (Node->use_empty())
237 return 0; // No CallSeqEnd
239 // The chain is usually at the end.
240 SDValue TheChain(Node, Node->getNumValues()-1);
241 if (TheChain.getValueType() != MVT::Other) {
242 // Sometimes it's at the beginning.
243 TheChain = SDValue(Node, 0);
244 if (TheChain.getValueType() != MVT::Other) {
245 // Otherwise, hunt for it.
246 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
247 if (Node->getValueType(i) == MVT::Other) {
248 TheChain = SDValue(Node, i);
252 // Otherwise, we walked into a node without a chain.
253 if (TheChain.getValueType() != MVT::Other)
258 for (SDNode::use_iterator UI = Node->use_begin(),
259 E = Node->use_end(); UI != E; ++UI) {
261 // Make sure to only follow users of our token chain.
263 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
264 if (User->getOperand(i) == TheChain)
265 if (SDNode *Result = FindCallEndFromCallStart(User, depth))
271 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
272 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
273 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
275 assert(Node && "Didn't find callseq_start for a call??");
276 while (Node->getOpcode() != ISD::CALLSEQ_START || nested) {
277 Node = Node->getOperand(0).getNode();
278 assert(Node->getOperand(0).getValueType() == MVT::Other &&
279 "Node doesn't have a token chain argument!");
280 switch (Node->getOpcode()) {
283 case ISD::CALLSEQ_START:
288 case ISD::CALLSEQ_END:
296 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
297 /// see if any uses can reach Dest. If no dest operands can get to dest,
298 /// legalize them, legalize ourself, and return false, otherwise, return true.
300 /// Keep track of the nodes we fine that actually do lead to Dest in
301 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
303 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
304 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
305 if (N == Dest) return true; // N certainly leads to Dest :)
307 // If we've already processed this node and it does lead to Dest, there is no
308 // need to reprocess it.
309 if (NodesLeadingTo.count(N)) return true;
311 // If the first result of this node has been already legalized, then it cannot
313 if (LegalizedNodes.count(SDValue(N, 0))) return false;
315 // Okay, this node has not already been legalized. Check and legalize all
316 // operands. If none lead to Dest, then we can legalize this node.
317 bool OperandsLeadToDest = false;
318 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
319 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
320 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest,
323 if (OperandsLeadToDest) {
324 NodesLeadingTo.insert(N);
328 // Okay, this node looks safe, legalize it and return false.
329 LegalizeOp(SDValue(N, 0));
333 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
334 /// a load from the constant pool.
335 static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
336 SelectionDAG &DAG, const TargetLowering &TLI) {
338 DebugLoc dl = CFP->getDebugLoc();
340 // If a FP immediate is precise when represented as a float and if the
341 // target can do an extending load from float to double, we put it into
342 // the constant pool as a float, even if it's is statically typed as a
343 // double. This shrinks FP constants and canonicalizes them for targets where
344 // an FP extending load is the same cost as a normal load (such as on the x87
345 // fp stack or PPC FP unit).
346 EVT VT = CFP->getValueType(0);
347 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
349 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
350 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
351 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
356 while (SVT != MVT::f32) {
357 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
358 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) &&
359 // Only do this if the target has a native EXTLOAD instruction from
361 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
362 TLI.ShouldShrinkFPConstant(OrigVT)) {
363 Type *SType = SVT.getTypeForEVT(*DAG.getContext());
364 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
370 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
371 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
373 return DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT,
375 CPIdx, MachinePointerInfo::getConstantPool(),
376 VT, false, false, Alignment);
377 return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
378 MachinePointerInfo::getConstantPool(), false, false,
382 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
384 SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
385 const TargetLowering &TLI) {
386 SDValue Chain = ST->getChain();
387 SDValue Ptr = ST->getBasePtr();
388 SDValue Val = ST->getValue();
389 EVT VT = Val.getValueType();
390 int Alignment = ST->getAlignment();
391 DebugLoc dl = ST->getDebugLoc();
392 if (ST->getMemoryVT().isFloatingPoint() ||
393 ST->getMemoryVT().isVector()) {
394 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
395 if (TLI.isTypeLegal(intVT)) {
396 // Expand to a bitconvert of the value to the integer type of the
397 // same size, then a (misaligned) int store.
398 // FIXME: Does not handle truncating floating point stores!
399 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
400 return DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
401 ST->isVolatile(), ST->isNonTemporal(), Alignment);
403 // Do a (aligned) store to a stack slot, then copy from the stack slot
404 // to the final destination using (unaligned) integer loads and stores.
405 EVT StoredVT = ST->getMemoryVT();
407 TLI.getRegisterType(*DAG.getContext(),
408 EVT::getIntegerVT(*DAG.getContext(),
409 StoredVT.getSizeInBits()));
410 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
411 unsigned RegBytes = RegVT.getSizeInBits() / 8;
412 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
414 // Make sure the stack slot is also aligned for the register type.
415 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
417 // Perform the original store, only redirected to the stack slot.
418 SDValue Store = DAG.getTruncStore(Chain, dl,
419 Val, StackPtr, MachinePointerInfo(),
420 StoredVT, false, false, 0);
421 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
422 SmallVector<SDValue, 8> Stores;
425 // Do all but one copies using the full register width.
426 for (unsigned i = 1; i < NumRegs; i++) {
427 // Load one integer register's worth from the stack slot.
428 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr,
429 MachinePointerInfo(),
431 // Store it to the final location. Remember the store.
432 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
433 ST->getPointerInfo().getWithOffset(Offset),
434 ST->isVolatile(), ST->isNonTemporal(),
435 MinAlign(ST->getAlignment(), Offset)));
436 // Increment the pointers.
438 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
440 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
443 // The last store may be partial. Do a truncating store. On big-endian
444 // machines this requires an extending load from the stack slot to ensure
445 // that the bits are in the right place.
446 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
447 8 * (StoredBytes - Offset));
449 // Load from the stack slot.
450 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
451 MachinePointerInfo(),
452 MemVT, false, false, 0);
454 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
456 .getWithOffset(Offset),
457 MemVT, ST->isVolatile(),
459 MinAlign(ST->getAlignment(), Offset)));
460 // The order of the stores doesn't matter - say it with a TokenFactor.
461 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
464 assert(ST->getMemoryVT().isInteger() &&
465 !ST->getMemoryVT().isVector() &&
466 "Unaligned store of unknown type.");
467 // Get the half-size VT
468 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext());
469 int NumBits = NewStoredVT.getSizeInBits();
470 int IncrementSize = NumBits / 8;
472 // Divide the stored value in two parts.
473 SDValue ShiftAmount = DAG.getConstant(NumBits,
474 TLI.getShiftAmountTy(Val.getValueType()));
476 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
478 // Store the two parts
479 SDValue Store1, Store2;
480 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
481 ST->getPointerInfo(), NewStoredVT,
482 ST->isVolatile(), ST->isNonTemporal(), Alignment);
483 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
484 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
485 Alignment = MinAlign(Alignment, IncrementSize);
486 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
487 ST->getPointerInfo().getWithOffset(IncrementSize),
488 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(),
491 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
494 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
496 SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
497 const TargetLowering &TLI) {
498 SDValue Chain = LD->getChain();
499 SDValue Ptr = LD->getBasePtr();
500 EVT VT = LD->getValueType(0);
501 EVT LoadedVT = LD->getMemoryVT();
502 DebugLoc dl = LD->getDebugLoc();
503 if (VT.isFloatingPoint() || VT.isVector()) {
504 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
505 if (TLI.isTypeLegal(intVT)) {
506 // Expand to a (misaligned) integer load of the same size,
507 // then bitconvert to floating point or vector.
508 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getPointerInfo(),
510 LD->isNonTemporal(), LD->getAlignment());
511 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad);
512 if (VT.isFloatingPoint() && LoadedVT != VT)
513 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result);
515 SDValue Ops[] = { Result, Chain };
516 return DAG.getMergeValues(Ops, 2, dl);
519 // Copy the value to a (aligned) stack slot using (unaligned) integer
520 // loads and stores, then do a (aligned) load from the stack slot.
521 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
522 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
523 unsigned RegBytes = RegVT.getSizeInBits() / 8;
524 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
526 // Make sure the stack slot is also aligned for the register type.
527 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
529 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
530 SmallVector<SDValue, 8> Stores;
531 SDValue StackPtr = StackBase;
534 // Do all but one copies using the full register width.
535 for (unsigned i = 1; i < NumRegs; i++) {
536 // Load one integer register's worth from the original location.
537 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr,
538 LD->getPointerInfo().getWithOffset(Offset),
539 LD->isVolatile(), LD->isNonTemporal(),
540 MinAlign(LD->getAlignment(), Offset));
541 // Follow the load with a store to the stack slot. Remember the store.
542 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
543 MachinePointerInfo(), false, false, 0));
544 // Increment the pointers.
546 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
547 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
551 // The last copy may be partial. Do an extending load.
552 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
553 8 * (LoadedBytes - Offset));
554 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
555 LD->getPointerInfo().getWithOffset(Offset),
556 MemVT, LD->isVolatile(),
558 MinAlign(LD->getAlignment(), Offset));
559 // Follow the load with a store to the stack slot. Remember the store.
560 // On big-endian machines this requires a truncating store to ensure
561 // that the bits end up in the right place.
562 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
563 MachinePointerInfo(), MemVT,
566 // The order of the stores doesn't matter - say it with a TokenFactor.
567 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
570 // Finally, perform the original load only redirected to the stack slot.
571 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
572 MachinePointerInfo(), LoadedVT, false, false, 0);
574 // Callers expect a MERGE_VALUES node.
575 SDValue Ops[] = { Load, TF };
576 return DAG.getMergeValues(Ops, 2, dl);
578 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
579 "Unaligned load of unsupported type.");
581 // Compute the new VT that is half the size of the old one. This is an
583 unsigned NumBits = LoadedVT.getSizeInBits();
585 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
588 unsigned Alignment = LD->getAlignment();
589 unsigned IncrementSize = NumBits / 8;
590 ISD::LoadExtType HiExtType = LD->getExtensionType();
592 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
593 if (HiExtType == ISD::NON_EXTLOAD)
594 HiExtType = ISD::ZEXTLOAD;
596 // Load the value in two parts
598 if (TLI.isLittleEndian()) {
599 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
600 NewLoadedVT, LD->isVolatile(),
601 LD->isNonTemporal(), Alignment);
602 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
603 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
604 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr,
605 LD->getPointerInfo().getWithOffset(IncrementSize),
606 NewLoadedVT, LD->isVolatile(),
607 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
609 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(),
610 NewLoadedVT, LD->isVolatile(),
611 LD->isNonTemporal(), Alignment);
612 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
613 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
614 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
615 LD->getPointerInfo().getWithOffset(IncrementSize),
616 NewLoadedVT, LD->isVolatile(),
617 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
620 // aggregate the two parts
621 SDValue ShiftAmount = DAG.getConstant(NumBits,
622 TLI.getShiftAmountTy(Hi.getValueType()));
623 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
624 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
626 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
629 SDValue Ops[] = { Result, TF };
630 return DAG.getMergeValues(Ops, 2, dl);
633 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
634 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
635 /// is necessary to spill the vector being inserted into to memory, perform
636 /// the insert there, and then read the result back.
637 SDValue SelectionDAGLegalize::
638 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
644 // If the target doesn't support this, we have to spill the input vector
645 // to a temporary stack slot, update the element, then reload it. This is
646 // badness. We could also load the value into a vector register (either
647 // with a "move to register" or "extload into register" instruction, then
648 // permute it into place, if the idx is a constant and if the idx is
649 // supported by the target.
650 EVT VT = Tmp1.getValueType();
651 EVT EltVT = VT.getVectorElementType();
652 EVT IdxVT = Tmp3.getValueType();
653 EVT PtrVT = TLI.getPointerTy();
654 SDValue StackPtr = DAG.CreateStackTemporary(VT);
656 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
659 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
660 MachinePointerInfo::getFixedStack(SPFI),
663 // Truncate or zero extend offset to target pointer type.
664 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
665 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
666 // Add the offset to the index.
667 unsigned EltSize = EltVT.getSizeInBits()/8;
668 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
669 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
670 // Store the scalar value.
671 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT,
673 // Load the updated vector.
674 return DAG.getLoad(VT, dl, Ch, StackPtr,
675 MachinePointerInfo::getFixedStack(SPFI), false, false, 0);
679 SDValue SelectionDAGLegalize::
680 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) {
681 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
682 // SCALAR_TO_VECTOR requires that the type of the value being inserted
683 // match the element type of the vector being created, except for
684 // integers in which case the inserted value can be over width.
685 EVT EltVT = Vec.getValueType().getVectorElementType();
686 if (Val.getValueType() == EltVT ||
687 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
688 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
689 Vec.getValueType(), Val);
691 unsigned NumElts = Vec.getValueType().getVectorNumElements();
692 // We generate a shuffle of InVec and ScVec, so the shuffle mask
693 // should be 0,1,2,3,4,5... with the appropriate element replaced with
695 SmallVector<int, 8> ShufOps;
696 for (unsigned i = 0; i != NumElts; ++i)
697 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
699 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
703 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
706 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
707 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
708 // FIXME: We shouldn't do this for TargetConstantFP's.
709 // FIXME: move this to the DAG Combiner! Note that we can't regress due
710 // to phase ordering between legalized code and the dag combiner. This
711 // probably means that we need to integrate dag combiner and legalizer
713 // We generally can't do this one for long doubles.
714 SDValue Tmp1 = ST->getChain();
715 SDValue Tmp2 = ST->getBasePtr();
717 unsigned Alignment = ST->getAlignment();
718 bool isVolatile = ST->isVolatile();
719 bool isNonTemporal = ST->isNonTemporal();
720 DebugLoc dl = ST->getDebugLoc();
721 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
722 if (CFP->getValueType(0) == MVT::f32 &&
723 TLI.isTypeLegal(MVT::i32)) {
724 Tmp3 = DAG.getConstant(CFP->getValueAPF().
725 bitcastToAPInt().zextOrTrunc(32),
727 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
728 isVolatile, isNonTemporal, Alignment);
731 if (CFP->getValueType(0) == MVT::f64) {
732 // If this target supports 64-bit registers, do a single 64-bit store.
733 if (TLI.isTypeLegal(MVT::i64)) {
734 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
735 zextOrTrunc(64), MVT::i64);
736 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
737 isVolatile, isNonTemporal, Alignment);
740 if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) {
741 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
742 // stores. If the target supports neither 32- nor 64-bits, this
743 // xform is certainly not worth it.
744 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
745 SDValue Lo = DAG.getConstant(IntVal.trunc(32), MVT::i32);
746 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
747 if (TLI.isBigEndian()) std::swap(Lo, Hi);
749 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getPointerInfo(), isVolatile,
750 isNonTemporal, Alignment);
751 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
752 DAG.getIntPtrConstant(4));
753 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2,
754 ST->getPointerInfo().getWithOffset(4),
755 isVolatile, isNonTemporal, MinAlign(Alignment, 4U));
757 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
761 return SDValue(0, 0);
764 /// LegalizeOp - Return a legal replacement for the given operation, with
765 /// all legal operands.
766 SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
767 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
770 SDNode *Node = Op.getNode();
771 DebugLoc dl = Node->getDebugLoc();
773 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
774 assert(TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) ==
775 TargetLowering::TypeLegal &&
776 "Unexpected illegal type!");
778 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
779 assert((TLI.getTypeAction(*DAG.getContext(),
780 Node->getOperand(i).getValueType()) ==
781 TargetLowering::TypeLegal ||
782 Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
783 "Unexpected illegal type!");
785 // Note that LegalizeOp may be reentered even from single-use nodes, which
786 // means that we always must cache transformed nodes.
787 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
788 if (I != LegalizedNodes.end()) return I->second;
790 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
792 bool isCustom = false;
794 // Figure out the correct action; the way to query this varies by opcode
795 TargetLowering::LegalizeAction Action = TargetLowering::Legal;
796 bool SimpleFinishLegalizing = true;
797 switch (Node->getOpcode()) {
798 case ISD::INTRINSIC_W_CHAIN:
799 case ISD::INTRINSIC_WO_CHAIN:
800 case ISD::INTRINSIC_VOID:
803 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
805 case ISD::SINT_TO_FP:
806 case ISD::UINT_TO_FP:
807 case ISD::EXTRACT_VECTOR_ELT:
808 Action = TLI.getOperationAction(Node->getOpcode(),
809 Node->getOperand(0).getValueType());
811 case ISD::FP_ROUND_INREG:
812 case ISD::SIGN_EXTEND_INREG: {
813 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
814 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
817 case ISD::ATOMIC_STORE: {
818 Action = TLI.getOperationAction(Node->getOpcode(),
819 Node->getOperand(2).getValueType());
825 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
826 Node->getOpcode() == ISD::SETCC ? 2 : 1;
827 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
828 EVT OpVT = Node->getOperand(CompareOperand).getValueType();
829 ISD::CondCode CCCode =
830 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
831 Action = TLI.getCondCodeAction(CCCode, OpVT);
832 if (Action == TargetLowering::Legal) {
833 if (Node->getOpcode() == ISD::SELECT_CC)
834 Action = TLI.getOperationAction(Node->getOpcode(),
835 Node->getValueType(0));
837 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
843 // FIXME: Model these properly. LOAD and STORE are complicated, and
844 // STORE expects the unlegalized operand in some cases.
845 SimpleFinishLegalizing = false;
847 case ISD::CALLSEQ_START:
848 case ISD::CALLSEQ_END:
849 // FIXME: This shouldn't be necessary. These nodes have special properties
850 // dealing with the recursive nature of legalization. Removing this
851 // special case should be done as part of making LegalizeDAG non-recursive.
852 SimpleFinishLegalizing = false;
854 case ISD::EXTRACT_ELEMENT:
855 case ISD::FLT_ROUNDS_:
863 case ISD::MERGE_VALUES:
865 case ISD::FRAME_TO_ARGS_OFFSET:
866 case ISD::EH_SJLJ_SETJMP:
867 case ISD::EH_SJLJ_LONGJMP:
868 case ISD::EH_SJLJ_DISPATCHSETUP:
869 // These operations lie about being legal: when they claim to be legal,
870 // they should actually be expanded.
871 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
872 if (Action == TargetLowering::Legal)
873 Action = TargetLowering::Expand;
875 case ISD::INIT_TRAMPOLINE:
876 case ISD::ADJUST_TRAMPOLINE:
878 case ISD::RETURNADDR:
879 // These operations lie about being legal: when they claim to be legal,
880 // they should actually be custom-lowered.
881 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
882 if (Action == TargetLowering::Legal)
883 Action = TargetLowering::Custom;
885 case ISD::BUILD_VECTOR:
886 // A weird case: legalization for BUILD_VECTOR never legalizes the
888 // FIXME: This really sucks... changing it isn't semantically incorrect,
889 // but it massively pessimizes the code for floating-point BUILD_VECTORs
890 // because ConstantFP operands get legalized into constant pool loads
891 // before the BUILD_VECTOR code can see them. It doesn't usually bite,
892 // though, because BUILD_VECTORS usually get lowered into other nodes
893 // which get legalized properly.
894 SimpleFinishLegalizing = false;
897 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
898 Action = TargetLowering::Legal;
900 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
905 if (SimpleFinishLegalizing) {
906 SmallVector<SDValue, 8> Ops, ResultVals;
907 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
908 Ops.push_back(LegalizeOp(Node->getOperand(i)));
909 switch (Node->getOpcode()) {
916 // Branches tweak the chain to include LastCALLSEQ_END
917 Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0],
919 Ops[0] = LegalizeOp(Ops[0]);
920 LastCALLSEQ_END = DAG.getEntryNode();
927 // Legalizing shifts/rotates requires adjusting the shift amount
928 // to the appropriate width.
929 if (!Ops[1].getValueType().isVector())
930 Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[0].getValueType(),
936 // Legalizing shifts/rotates requires adjusting the shift amount
937 // to the appropriate width.
938 if (!Ops[2].getValueType().isVector())
939 Ops[2] = LegalizeOp(DAG.getShiftAmountOperand(Ops[0].getValueType(),
944 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), Ops.data(),
947 case TargetLowering::Legal:
948 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
949 ResultVals.push_back(Result.getValue(i));
951 case TargetLowering::Custom:
952 // FIXME: The handling for custom lowering with multiple results is
954 Tmp1 = TLI.LowerOperation(Result, DAG);
955 if (Tmp1.getNode()) {
956 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
958 ResultVals.push_back(Tmp1);
960 ResultVals.push_back(Tmp1.getValue(i));
966 case TargetLowering::Expand:
967 ExpandNode(Result.getNode(), ResultVals);
969 case TargetLowering::Promote:
970 PromoteNode(Result.getNode(), ResultVals);
973 if (!ResultVals.empty()) {
974 for (unsigned i = 0, e = ResultVals.size(); i != e; ++i) {
975 if (ResultVals[i] != SDValue(Node, i))
976 ResultVals[i] = LegalizeOp(ResultVals[i]);
977 AddLegalizedOperand(SDValue(Node, i), ResultVals[i]);
979 return ResultVals[Op.getResNo()];
983 switch (Node->getOpcode()) {
990 assert(0 && "Do not know how to legalize this operator!");
992 case ISD::BUILD_VECTOR:
993 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
994 default: assert(0 && "This action is not supported yet!");
995 case TargetLowering::Custom:
996 Tmp3 = TLI.LowerOperation(Result, DAG);
997 if (Tmp3.getNode()) {
1002 case TargetLowering::Expand:
1003 Result = ExpandBUILD_VECTOR(Result.getNode());
1007 case ISD::CALLSEQ_START: {
1008 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1010 // Recursively Legalize all of the inputs of the call end that do not lead
1011 // to this call start. This ensures that any libcalls that need be inserted
1012 // are inserted *before* the CALLSEQ_START.
1013 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1014 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1015 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
1019 // Now that we have legalized all of the inputs (which may have inserted
1020 // libcalls), create the new CALLSEQ_START node.
1021 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1023 // Merge in the last call to ensure that this call starts after the last
1025 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1026 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1027 Tmp1, LastCALLSEQ_END);
1028 Tmp1 = LegalizeOp(Tmp1);
1031 // Do not try to legalize the target-specific arguments (#1+).
1032 if (Tmp1 != Node->getOperand(0)) {
1033 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1035 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), &Ops[0],
1036 Ops.size()), Result.getResNo());
1039 // Remember that the CALLSEQ_START is legalized.
1040 AddLegalizedOperand(Op.getValue(0), Result);
1041 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1042 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1044 // Now that the callseq_start and all of the non-call nodes above this call
1045 // sequence have been legalized, legalize the call itself. During this
1046 // process, no libcalls can/will be inserted, guaranteeing that no calls
1048 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1049 // Note that we are selecting this call!
1050 LastCALLSEQ_END = SDValue(CallEnd, 0);
1051 IsLegalizingCall = true;
1053 // Legalize the call, starting from the CALLSEQ_END.
1054 LegalizeOp(LastCALLSEQ_END);
1055 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1058 case ISD::CALLSEQ_END:
1059 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1060 // will cause this node to be legalized as well as handling libcalls right.
1061 if (LastCALLSEQ_END.getNode() != Node) {
1062 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
1063 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1064 assert(I != LegalizedNodes.end() &&
1065 "Legalizing the call start should have legalized this node!");
1069 // Otherwise, the call start has been legalized and everything is going
1070 // according to plan. Just legalize ourselves normally here.
1071 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1072 // Do not try to legalize the target-specific arguments (#1+), except for
1073 // an optional flag input.
1074 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Glue){
1075 if (Tmp1 != Node->getOperand(0)) {
1076 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1078 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1079 &Ops[0], Ops.size()),
1083 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1084 if (Tmp1 != Node->getOperand(0) ||
1085 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1086 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1089 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1090 &Ops[0], Ops.size()),
1094 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1095 // This finishes up call legalization.
1096 IsLegalizingCall = false;
1098 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1099 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1100 if (Node->getNumValues() == 2)
1101 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1102 return Result.getValue(Op.getResNo());
1104 LoadSDNode *LD = cast<LoadSDNode>(Node);
1105 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1106 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1108 ISD::LoadExtType ExtType = LD->getExtensionType();
1109 if (ExtType == ISD::NON_EXTLOAD) {
1110 EVT VT = Node->getValueType(0);
1111 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1112 Tmp1, Tmp2, LD->getOffset()),
1114 Tmp3 = Result.getValue(0);
1115 Tmp4 = Result.getValue(1);
1117 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1118 default: assert(0 && "This action is not supported yet!");
1119 case TargetLowering::Legal:
1120 // If this is an unaligned load and the target doesn't support it,
1122 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
1123 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1124 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
1125 if (LD->getAlignment() < ABIAlignment){
1126 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
1128 Tmp3 = Result.getOperand(0);
1129 Tmp4 = Result.getOperand(1);
1130 Tmp3 = LegalizeOp(Tmp3);
1131 Tmp4 = LegalizeOp(Tmp4);
1135 case TargetLowering::Custom:
1136 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1137 if (Tmp1.getNode()) {
1138 Tmp3 = LegalizeOp(Tmp1);
1139 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1142 case TargetLowering::Promote: {
1143 // Only promote a load of vector type to another.
1144 assert(VT.isVector() && "Cannot promote this load!");
1145 // Change base type to a different vector type.
1146 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1148 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getPointerInfo(),
1149 LD->isVolatile(), LD->isNonTemporal(),
1150 LD->getAlignment());
1151 Tmp3 = LegalizeOp(DAG.getNode(ISD::BITCAST, dl, VT, Tmp1));
1152 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1156 // Since loads produce two values, make sure to remember that we
1157 // legalized both of them.
1158 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
1159 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
1160 return Op.getResNo() ? Tmp4 : Tmp3;
1163 EVT SrcVT = LD->getMemoryVT();
1164 unsigned SrcWidth = SrcVT.getSizeInBits();
1165 unsigned Alignment = LD->getAlignment();
1166 bool isVolatile = LD->isVolatile();
1167 bool isNonTemporal = LD->isNonTemporal();
1169 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
1170 // Some targets pretend to have an i1 loading operation, and actually
1171 // load an i8. This trick is correct for ZEXTLOAD because the top 7
1172 // bits are guaranteed to be zero; it helps the optimizers understand
1173 // that these bits are zero. It is also useful for EXTLOAD, since it
1174 // tells the optimizers that those bits are undefined. It would be
1175 // nice to have an effective generic way of getting these benefits...
1176 // Until such a way is found, don't insist on promoting i1 here.
1177 (SrcVT != MVT::i1 ||
1178 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
1179 // Promote to a byte-sized load if not loading an integral number of
1180 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
1181 unsigned NewWidth = SrcVT.getStoreSizeInBits();
1182 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
1185 // The extra bits are guaranteed to be zero, since we stored them that
1186 // way. A zext load from NVT thus automatically gives zext from SrcVT.
1188 ISD::LoadExtType NewExtType =
1189 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
1191 Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
1192 Tmp1, Tmp2, LD->getPointerInfo(),
1193 NVT, isVolatile, isNonTemporal, Alignment);
1195 Ch = Result.getValue(1); // The chain.
1197 if (ExtType == ISD::SEXTLOAD)
1198 // Having the top bits zero doesn't help when sign extending.
1199 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1200 Result.getValueType(),
1201 Result, DAG.getValueType(SrcVT));
1202 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
1203 // All the top bits are guaranteed to be zero - inform the optimizers.
1204 Result = DAG.getNode(ISD::AssertZext, dl,
1205 Result.getValueType(), Result,
1206 DAG.getValueType(SrcVT));
1208 Tmp1 = LegalizeOp(Result);
1209 Tmp2 = LegalizeOp(Ch);
1210 } else if (SrcWidth & (SrcWidth - 1)) {
1211 // If not loading a power-of-2 number of bits, expand as two loads.
1212 assert(!SrcVT.isVector() && "Unsupported extload!");
1213 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
1214 assert(RoundWidth < SrcWidth);
1215 unsigned ExtraWidth = SrcWidth - RoundWidth;
1216 assert(ExtraWidth < RoundWidth);
1217 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1218 "Load size not an integral number of bytes!");
1219 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
1220 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
1222 unsigned IncrementSize;
1224 if (TLI.isLittleEndian()) {
1225 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1226 // Load the bottom RoundWidth bits.
1227 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0),
1229 LD->getPointerInfo(), RoundVT, isVolatile,
1230 isNonTemporal, Alignment);
1232 // Load the remaining ExtraWidth bits.
1233 IncrementSize = RoundWidth / 8;
1234 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1235 DAG.getIntPtrConstant(IncrementSize));
1236 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
1237 LD->getPointerInfo().getWithOffset(IncrementSize),
1238 ExtraVT, isVolatile, isNonTemporal,
1239 MinAlign(Alignment, IncrementSize));
1241 // Build a factor node to remember that this load is independent of
1243 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1246 // Move the top bits to the right place.
1247 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1248 DAG.getConstant(RoundWidth,
1249 TLI.getShiftAmountTy(Hi.getValueType())));
1251 // Join the hi and lo parts.
1252 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1254 // Big endian - avoid unaligned loads.
1255 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1256 // Load the top RoundWidth bits.
1257 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
1258 LD->getPointerInfo(), RoundVT, isVolatile,
1259 isNonTemporal, Alignment);
1261 // Load the remaining ExtraWidth bits.
1262 IncrementSize = RoundWidth / 8;
1263 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1264 DAG.getIntPtrConstant(IncrementSize));
1265 Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
1266 dl, Node->getValueType(0), Tmp1, Tmp2,
1267 LD->getPointerInfo().getWithOffset(IncrementSize),
1268 ExtraVT, isVolatile, isNonTemporal,
1269 MinAlign(Alignment, IncrementSize));
1271 // Build a factor node to remember that this load is independent of
1273 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1276 // Move the top bits to the right place.
1277 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1278 DAG.getConstant(ExtraWidth,
1279 TLI.getShiftAmountTy(Hi.getValueType())));
1281 // Join the hi and lo parts.
1282 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1285 Tmp1 = LegalizeOp(Result);
1286 Tmp2 = LegalizeOp(Ch);
1288 switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
1289 default: assert(0 && "This action is not supported yet!");
1290 case TargetLowering::Custom:
1293 case TargetLowering::Legal:
1294 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1295 Tmp1, Tmp2, LD->getOffset()),
1297 Tmp1 = Result.getValue(0);
1298 Tmp2 = Result.getValue(1);
1301 Tmp3 = TLI.LowerOperation(Result, DAG);
1302 if (Tmp3.getNode()) {
1303 Tmp1 = LegalizeOp(Tmp3);
1304 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1307 // If this is an unaligned load and the target doesn't support it,
1309 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
1311 LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1312 unsigned ABIAlignment =
1313 TLI.getTargetData()->getABITypeAlignment(Ty);
1314 if (LD->getAlignment() < ABIAlignment){
1315 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
1317 Tmp1 = Result.getOperand(0);
1318 Tmp2 = Result.getOperand(1);
1319 Tmp1 = LegalizeOp(Tmp1);
1320 Tmp2 = LegalizeOp(Tmp2);
1325 case TargetLowering::Expand:
1326 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) && TLI.isTypeLegal(SrcVT)) {
1327 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2,
1328 LD->getPointerInfo(),
1329 LD->isVolatile(), LD->isNonTemporal(),
1330 LD->getAlignment());
1334 ExtendOp = (SrcVT.isFloatingPoint() ?
1335 ISD::FP_EXTEND : ISD::ANY_EXTEND);
1337 case ISD::SEXTLOAD: ExtendOp = ISD::SIGN_EXTEND; break;
1338 case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break;
1339 default: llvm_unreachable("Unexpected extend load type!");
1341 Result = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
1342 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1343 Tmp2 = LegalizeOp(Load.getValue(1));
1347 // If this is a promoted vector load, and the vector element types are
1348 // legal, then scalarize it.
1349 if (ExtType == ISD::EXTLOAD && SrcVT.isVector() &&
1350 TLI.isTypeLegal(Node->getValueType(0).getScalarType())) {
1351 SmallVector<SDValue, 8> LoadVals;
1352 SmallVector<SDValue, 8> LoadChains;
1353 unsigned NumElem = SrcVT.getVectorNumElements();
1354 unsigned Stride = SrcVT.getScalarType().getSizeInBits()/8;
1356 for (unsigned Idx=0; Idx<NumElem; Idx++) {
1357 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1358 DAG.getIntPtrConstant(Stride));
1359 SDValue ScalarLoad = DAG.getExtLoad(ISD::EXTLOAD, dl,
1360 Node->getValueType(0).getScalarType(),
1361 Tmp1, Tmp2, LD->getPointerInfo().getWithOffset(Idx * Stride),
1362 SrcVT.getScalarType(),
1363 LD->isVolatile(), LD->isNonTemporal(),
1364 LD->getAlignment());
1366 LoadVals.push_back(ScalarLoad.getValue(0));
1367 LoadChains.push_back(ScalarLoad.getValue(1));
1369 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1370 &LoadChains[0], LoadChains.size());
1371 SDValue ValRes = DAG.getNode(ISD::BUILD_VECTOR, dl,
1372 Node->getValueType(0), &LoadVals[0], LoadVals.size());
1374 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1375 Tmp2 = LegalizeOp(Result.getValue(0)); // Relegalize new nodes.
1379 // If this is a promoted vector load, and the vector element types are
1380 // illegal, create the promoted vector from bitcasted segments.
1381 if (ExtType == ISD::EXTLOAD && SrcVT.isVector()) {
1382 EVT MemElemTy = Node->getValueType(0).getScalarType();
1383 EVT SrcSclrTy = SrcVT.getScalarType();
1384 unsigned SizeRatio =
1385 (MemElemTy.getSizeInBits() / SrcSclrTy.getSizeInBits());
1387 SmallVector<SDValue, 8> LoadVals;
1388 SmallVector<SDValue, 8> LoadChains;
1389 unsigned NumElem = SrcVT.getVectorNumElements();
1390 unsigned Stride = SrcVT.getScalarType().getSizeInBits()/8;
1392 for (unsigned Idx=0; Idx<NumElem; Idx++) {
1393 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1394 DAG.getIntPtrConstant(Stride));
1395 SDValue ScalarLoad = DAG.getExtLoad(ISD::EXTLOAD, dl,
1396 SrcVT.getScalarType(),
1397 Tmp1, Tmp2, LD->getPointerInfo().getWithOffset(Idx * Stride),
1398 SrcVT.getScalarType(),
1399 LD->isVolatile(), LD->isNonTemporal(),
1400 LD->getAlignment());
1401 if (TLI.isBigEndian()) {
1402 // MSB (which is garbage, comes first)
1403 LoadVals.push_back(ScalarLoad.getValue(0));
1404 for (unsigned i = 0; i<SizeRatio-1; ++i)
1405 LoadVals.push_back(DAG.getUNDEF(SrcVT.getScalarType()));
1407 // LSB (which is data, comes first)
1408 for (unsigned i = 0; i<SizeRatio-1; ++i)
1409 LoadVals.push_back(DAG.getUNDEF(SrcVT.getScalarType()));
1410 LoadVals.push_back(ScalarLoad.getValue(0));
1412 LoadChains.push_back(ScalarLoad.getValue(1));
1415 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1416 &LoadChains[0], LoadChains.size());
1417 EVT TempWideVector = EVT::getVectorVT(*DAG.getContext(),
1418 SrcVT.getScalarType(), NumElem*SizeRatio);
1419 SDValue ValRes = DAG.getNode(ISD::BUILD_VECTOR, dl,
1420 TempWideVector, &LoadVals[0], LoadVals.size());
1422 // Cast to the correct type
1423 ValRes = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), ValRes);
1425 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1426 Tmp2 = LegalizeOp(Result.getValue(0)); // Relegalize new nodes.
1431 // FIXME: This does not work for vectors on most targets. Sign- and
1432 // zero-extend operations are currently folded into extending loads,
1433 // whether they are legal or not, and then we end up here without any
1434 // support for legalizing them.
1435 assert(ExtType != ISD::EXTLOAD &&
1436 "EXTLOAD should always be supported!");
1437 // Turn the unsupported load into an EXTLOAD followed by an explicit
1438 // zero/sign extend inreg.
1439 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
1440 Tmp1, Tmp2, LD->getPointerInfo(), SrcVT,
1441 LD->isVolatile(), LD->isNonTemporal(),
1442 LD->getAlignment());
1444 if (ExtType == ISD::SEXTLOAD)
1445 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1446 Result.getValueType(),
1447 Result, DAG.getValueType(SrcVT));
1449 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType());
1450 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1451 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1456 // Since loads produce two values, make sure to remember that we legalized
1458 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
1459 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
1460 return Op.getResNo() ? Tmp2 : Tmp1;
1463 StoreSDNode *ST = cast<StoreSDNode>(Node);
1464 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
1465 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
1466 unsigned Alignment = ST->getAlignment();
1467 bool isVolatile = ST->isVolatile();
1468 bool isNonTemporal = ST->isNonTemporal();
1470 if (!ST->isTruncatingStore()) {
1471 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
1472 Result = SDValue(OptStore, 0);
1477 Tmp3 = LegalizeOp(ST->getValue());
1478 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1483 EVT VT = Tmp3.getValueType();
1484 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1485 default: assert(0 && "This action is not supported yet!");
1486 case TargetLowering::Legal:
1487 // If this is an unaligned store and the target doesn't support it,
1489 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
1490 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
1491 unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty);
1492 if (ST->getAlignment() < ABIAlignment)
1493 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()),
1497 case TargetLowering::Custom:
1498 Tmp1 = TLI.LowerOperation(Result, DAG);
1499 if (Tmp1.getNode()) Result = Tmp1;
1501 case TargetLowering::Promote:
1502 assert(VT.isVector() && "Unknown legal promote case!");
1503 Tmp3 = DAG.getNode(ISD::BITCAST, dl,
1504 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
1505 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2,
1506 ST->getPointerInfo(), isVolatile,
1507 isNonTemporal, Alignment);
1513 Tmp3 = LegalizeOp(ST->getValue());
1515 EVT StVT = ST->getMemoryVT();
1516 unsigned StWidth = StVT.getSizeInBits();
1518 if (StWidth != StVT.getStoreSizeInBits()) {
1519 // Promote to a byte-sized store with upper bits zero if not
1520 // storing an integral number of bytes. For example, promote
1521 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
1522 EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
1523 StVT.getStoreSizeInBits());
1524 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT);
1525 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
1526 NVT, isVolatile, isNonTemporal, Alignment);
1527 } else if (StWidth & (StWidth - 1)) {
1528 // If not storing a power-of-2 number of bits, expand as two stores.
1529 assert(!StVT.isVector() && "Unsupported truncstore!");
1530 unsigned RoundWidth = 1 << Log2_32(StWidth);
1531 assert(RoundWidth < StWidth);
1532 unsigned ExtraWidth = StWidth - RoundWidth;
1533 assert(ExtraWidth < RoundWidth);
1534 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1535 "Store size not an integral number of bytes!");
1536 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
1537 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
1539 unsigned IncrementSize;
1541 if (TLI.isLittleEndian()) {
1542 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
1543 // Store the bottom RoundWidth bits.
1544 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
1546 isVolatile, isNonTemporal, Alignment);
1548 // Store the remaining ExtraWidth bits.
1549 IncrementSize = RoundWidth / 8;
1550 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1551 DAG.getIntPtrConstant(IncrementSize));
1552 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
1553 DAG.getConstant(RoundWidth,
1554 TLI.getShiftAmountTy(Tmp3.getValueType())));
1555 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2,
1556 ST->getPointerInfo().getWithOffset(IncrementSize),
1557 ExtraVT, isVolatile, isNonTemporal,
1558 MinAlign(Alignment, IncrementSize));
1560 // Big endian - avoid unaligned stores.
1561 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
1562 // Store the top RoundWidth bits.
1563 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
1564 DAG.getConstant(ExtraWidth,
1565 TLI.getShiftAmountTy(Tmp3.getValueType())));
1566 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getPointerInfo(),
1567 RoundVT, isVolatile, isNonTemporal, Alignment);
1569 // Store the remaining ExtraWidth bits.
1570 IncrementSize = RoundWidth / 8;
1571 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1572 DAG.getIntPtrConstant(IncrementSize));
1573 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2,
1574 ST->getPointerInfo().getWithOffset(IncrementSize),
1575 ExtraVT, isVolatile, isNonTemporal,
1576 MinAlign(Alignment, IncrementSize));
1579 // The order of the stores doesn't matter.
1580 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
1582 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
1583 Tmp2 != ST->getBasePtr())
1584 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1589 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
1590 default: assert(0 && "This action is not supported yet!");
1591 case TargetLowering::Legal:
1592 // If this is an unaligned store and the target doesn't support it,
1594 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
1595 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
1596 unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty);
1597 if (ST->getAlignment() < ABIAlignment)
1598 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()),
1602 case TargetLowering::Custom:
1603 Result = TLI.LowerOperation(Result, DAG);
1605 case TargetLowering::Expand:
1607 EVT WideScalarVT = Tmp3.getValueType().getScalarType();
1608 EVT NarrowScalarVT = StVT.getScalarType();
1610 // The Store type is illegal, must scalarize the vector store.
1611 SmallVector<SDValue, 8> Stores;
1612 bool ScalarLegal = TLI.isTypeLegal(WideScalarVT);
1613 if (!TLI.isTypeLegal(StVT) && StVT.isVector() && ScalarLegal) {
1614 unsigned NumElem = StVT.getVectorNumElements();
1616 unsigned ScalarSize = StVT.getScalarType().getSizeInBits();
1617 // Round odd types to the next pow of two.
1618 if (!isPowerOf2_32(ScalarSize))
1619 ScalarSize = NextPowerOf2(ScalarSize);
1620 // Types smaller than 8 bits are promoted to 8 bits.
1621 ScalarSize = std::max<unsigned>(ScalarSize, 8);
1623 unsigned Stride = ScalarSize/8;
1624 assert(isPowerOf2_32(Stride) && "Stride must be a power of two");
1626 for (unsigned Idx=0; Idx<NumElem; Idx++) {
1627 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
1628 WideScalarVT, Tmp3, DAG.getIntPtrConstant(Idx));
1631 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), ScalarSize);
1633 Ex = DAG.getNode(ISD::TRUNCATE, dl, NVT, Ex);
1634 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1635 DAG.getIntPtrConstant(Stride));
1636 SDValue Store = DAG.getStore(Tmp1, dl, Ex, Tmp2,
1637 ST->getPointerInfo().getWithOffset(Idx*Stride),
1638 isVolatile, isNonTemporal, Alignment);
1639 Stores.push_back(Store);
1641 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1642 &Stores[0], Stores.size());
1646 // The Store type is illegal, must scalarize the vector store.
1647 // However, the scalar type is illegal. Must bitcast the result
1648 // and store it in smaller parts.
1649 if (!TLI.isTypeLegal(StVT) && StVT.isVector()) {
1650 unsigned WideNumElem = StVT.getVectorNumElements();
1651 unsigned Stride = NarrowScalarVT.getSizeInBits()/8;
1653 unsigned SizeRatio =
1654 (WideScalarVT.getSizeInBits() / NarrowScalarVT.getSizeInBits());
1656 EVT CastValueVT = EVT::getVectorVT(*DAG.getContext(), NarrowScalarVT,
1657 SizeRatio*WideNumElem);
1659 // Cast the wide elem vector to wider vec with smaller elem type.
1660 // Example <2 x i64> -> <4 x i32>
1661 Tmp3 = DAG.getNode(ISD::BITCAST, dl, CastValueVT, Tmp3);
1663 for (unsigned Idx=0; Idx<WideNumElem*SizeRatio; Idx++) {
1665 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
1666 NarrowScalarVT, Tmp3, DAG.getIntPtrConstant(Idx));
1668 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1669 DAG.getIntPtrConstant(Stride));
1671 // Store if, this element is:
1672 // - First element on big endian, or
1673 // - Last element on little endian
1674 if (( TLI.isBigEndian() && (Idx%SizeRatio == 0)) ||
1675 ((!TLI.isBigEndian() && (Idx%SizeRatio == SizeRatio-1)))) {
1676 SDValue Store = DAG.getStore(Tmp1, dl, Ex, Tmp2,
1677 ST->getPointerInfo().getWithOffset(Idx*Stride),
1678 isVolatile, isNonTemporal, Alignment);
1679 Stores.push_back(Store);
1682 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1683 &Stores[0], Stores.size());
1688 // TRUNCSTORE:i16 i32 -> STORE i16
1689 assert(TLI.isTypeLegal(StVT) && "Do not know how to expand this store!");
1690 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3);
1691 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
1692 isVolatile, isNonTemporal, Alignment);
1700 assert(Result.getValueType() == Op.getValueType() &&
1701 "Bad legalization!");
1703 // Make sure that the generated code is itself legal.
1705 Result = LegalizeOp(Result);
1707 // Note that LegalizeOp may be reentered even from single-use nodes, which
1708 // means that we always must cache transformed nodes.
1709 AddLegalizedOperand(Op, Result);
1713 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1714 SDValue Vec = Op.getOperand(0);
1715 SDValue Idx = Op.getOperand(1);
1716 DebugLoc dl = Op.getDebugLoc();
1717 // Store the value to a temporary stack slot, then LOAD the returned part.
1718 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1719 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1720 MachinePointerInfo(), false, false, 0);
1722 // Add the offset to the index.
1724 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1725 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1726 DAG.getConstant(EltSize, Idx.getValueType()));
1728 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1729 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1731 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1733 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1735 if (Op.getValueType().isVector())
1736 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,MachinePointerInfo(),
1738 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
1739 MachinePointerInfo(),
1740 Vec.getValueType().getVectorElementType(),
1744 SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
1745 assert(Op.getValueType().isVector() && "Non-vector insert subvector!");
1747 SDValue Vec = Op.getOperand(0);
1748 SDValue Part = Op.getOperand(1);
1749 SDValue Idx = Op.getOperand(2);
1750 DebugLoc dl = Op.getDebugLoc();
1752 // Store the value to a temporary stack slot, then LOAD the returned part.
1754 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1755 int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1756 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1758 // First store the whole vector.
1759 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo,
1762 // Then store the inserted part.
1764 // Add the offset to the index.
1766 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1768 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1769 DAG.getConstant(EltSize, Idx.getValueType()));
1771 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1772 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1774 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1776 SDValue SubStackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
1779 // Store the subvector.
1780 Ch = DAG.getStore(DAG.getEntryNode(), dl, Part, SubStackPtr,
1781 MachinePointerInfo(), false, false, 0);
1783 // Finally, load the updated vector.
1784 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo,
1788 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1789 // We can't handle this case efficiently. Allocate a sufficiently
1790 // aligned object on the stack, store each element into it, then load
1791 // the result as a vector.
1792 // Create the stack frame object.
1793 EVT VT = Node->getValueType(0);
1794 EVT EltVT = VT.getVectorElementType();
1795 DebugLoc dl = Node->getDebugLoc();
1796 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1797 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1798 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1800 // Emit a store of each element to the stack slot.
1801 SmallVector<SDValue, 8> Stores;
1802 unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1803 // Store (in the right endianness) the elements to memory.
1804 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1805 // Ignore undef elements.
1806 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1808 unsigned Offset = TypeByteSize*i;
1810 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
1811 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1813 // If the destination vector element type is narrower than the source
1814 // element type, only store the bits necessary.
1815 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1816 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1817 Node->getOperand(i), Idx,
1818 PtrInfo.getWithOffset(Offset),
1819 EltVT, false, false, 0));
1821 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
1822 Node->getOperand(i), Idx,
1823 PtrInfo.getWithOffset(Offset),
1828 if (!Stores.empty()) // Not all undef elements?
1829 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1830 &Stores[0], Stores.size());
1832 StoreChain = DAG.getEntryNode();
1834 // Result is a load from the stack slot.
1835 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo, false, false, 0);
1838 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
1839 DebugLoc dl = Node->getDebugLoc();
1840 SDValue Tmp1 = Node->getOperand(0);
1841 SDValue Tmp2 = Node->getOperand(1);
1843 // Get the sign bit of the RHS. First obtain a value that has the same
1844 // sign as the sign bit, i.e. negative if and only if the sign bit is 1.
1846 EVT FloatVT = Tmp2.getValueType();
1847 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits());
1848 if (TLI.isTypeLegal(IVT)) {
1849 // Convert to an integer with the same sign bit.
1850 SignBit = DAG.getNode(ISD::BITCAST, dl, IVT, Tmp2);
1852 // Store the float to memory, then load the sign part out as an integer.
1853 MVT LoadTy = TLI.getPointerTy();
1854 // First create a temporary that is aligned for both the load and store.
1855 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1856 // Then store the float to it.
1858 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, MachinePointerInfo(),
1860 if (TLI.isBigEndian()) {
1861 assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1862 // Load out a legal integer with the same sign bit as the float.
1863 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, MachinePointerInfo(),
1865 } else { // Little endian
1866 SDValue LoadPtr = StackPtr;
1867 // The float may be wider than the integer we are going to load. Advance
1868 // the pointer so that the loaded integer will contain the sign bit.
1869 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits();
1870 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8;
1871 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(),
1872 LoadPtr, DAG.getIntPtrConstant(ByteOffset));
1873 // Load a legal integer containing the sign bit.
1874 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(),
1876 // Move the sign bit to the top bit of the loaded integer.
1877 unsigned BitShift = LoadTy.getSizeInBits() -
1878 (FloatVT.getSizeInBits() - 8 * ByteOffset);
1879 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?");
1881 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit,
1882 DAG.getConstant(BitShift,
1883 TLI.getShiftAmountTy(SignBit.getValueType())));
1886 // Now get the sign bit proper, by seeing whether the value is negative.
1887 SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()),
1888 SignBit, DAG.getConstant(0, SignBit.getValueType()),
1890 // Get the absolute value of the result.
1891 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1892 // Select between the nabs and abs value based on the sign bit of
1894 return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit,
1895 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1899 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1900 SmallVectorImpl<SDValue> &Results) {
1901 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1902 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1903 " not tell us which reg is the stack pointer!");
1904 DebugLoc dl = Node->getDebugLoc();
1905 EVT VT = Node->getValueType(0);
1906 SDValue Tmp1 = SDValue(Node, 0);
1907 SDValue Tmp2 = SDValue(Node, 1);
1908 SDValue Tmp3 = Node->getOperand(2);
1909 SDValue Chain = Tmp1.getOperand(0);
1911 // Chain the dynamic stack allocation so that it doesn't modify the stack
1912 // pointer when other instructions are using the stack.
1913 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1915 SDValue Size = Tmp2.getOperand(1);
1916 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1917 Chain = SP.getValue(1);
1918 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1919 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
1920 if (Align > StackAlign)
1921 SP = DAG.getNode(ISD::AND, dl, VT, SP,
1922 DAG.getConstant(-(uint64_t)Align, VT));
1923 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1924 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1926 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1927 DAG.getIntPtrConstant(0, true), SDValue());
1929 Results.push_back(Tmp1);
1930 Results.push_back(Tmp2);
1933 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
1934 /// condition code CC on the current target. This routine expands SETCC with
1935 /// illegal condition code into AND / OR of multiple SETCC values.
1936 void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1937 SDValue &LHS, SDValue &RHS,
1940 EVT OpVT = LHS.getValueType();
1941 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1942 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1943 default: assert(0 && "Unknown condition code action!");
1944 case TargetLowering::Legal:
1947 case TargetLowering::Expand: {
1948 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1951 default: assert(0 && "Don't know how to expand this condition!");
1952 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break;
1953 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1954 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1955 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1956 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1957 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1958 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1959 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1960 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1961 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1962 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1963 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1964 // FIXME: Implement more expansions.
1967 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1968 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1969 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1977 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
1978 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1979 /// a load from the stack slot to DestVT, extending it if needed.
1980 /// The resultant code need not be legal.
1981 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
1985 // Create the stack frame object.
1987 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType().
1988 getTypeForEVT(*DAG.getContext()));
1989 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1991 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1992 int SPFI = StackPtrFI->getIndex();
1993 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(SPFI);
1995 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
1996 unsigned SlotSize = SlotVT.getSizeInBits();
1997 unsigned DestSize = DestVT.getSizeInBits();
1998 Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
1999 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(DestType);
2001 // Emit a store to the stack slot. Use a truncstore if the input value is
2002 // later than DestVT.
2005 if (SrcSize > SlotSize)
2006 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
2007 PtrInfo, SlotVT, false, false, SrcAlign);
2009 assert(SrcSize == SlotSize && "Invalid store");
2010 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
2011 PtrInfo, false, false, SrcAlign);
2014 // Result is a load from the stack slot.
2015 if (SlotSize == DestSize)
2016 return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo,
2017 false, false, DestAlign);
2019 assert(SlotSize < DestSize && "Unknown extension!");
2020 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr,
2021 PtrInfo, SlotVT, false, false, DestAlign);
2024 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
2025 DebugLoc dl = Node->getDebugLoc();
2026 // Create a vector sized/aligned stack slot, store the value to element #0,
2027 // then load the whole vector back out.
2028 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
2030 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
2031 int SPFI = StackPtrFI->getIndex();
2033 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0),
2035 MachinePointerInfo::getFixedStack(SPFI),
2036 Node->getValueType(0).getVectorElementType(),
2038 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
2039 MachinePointerInfo::getFixedStack(SPFI),
2044 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
2045 /// support the operation, but do support the resultant vector type.
2046 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
2047 unsigned NumElems = Node->getNumOperands();
2048 SDValue Value1, Value2;
2049 DebugLoc dl = Node->getDebugLoc();
2050 EVT VT = Node->getValueType(0);
2051 EVT OpVT = Node->getOperand(0).getValueType();
2052 EVT EltVT = VT.getVectorElementType();
2054 // If the only non-undef value is the low element, turn this into a
2055 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
2056 bool isOnlyLowElement = true;
2057 bool MoreThanTwoValues = false;
2058 bool isConstant = true;
2059 for (unsigned i = 0; i < NumElems; ++i) {
2060 SDValue V = Node->getOperand(i);
2061 if (V.getOpcode() == ISD::UNDEF)
2064 isOnlyLowElement = false;
2065 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
2068 if (!Value1.getNode()) {
2070 } else if (!Value2.getNode()) {
2073 } else if (V != Value1 && V != Value2) {
2074 MoreThanTwoValues = true;
2078 if (!Value1.getNode())
2079 return DAG.getUNDEF(VT);
2081 if (isOnlyLowElement)
2082 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
2084 // If all elements are constants, create a load from the constant pool.
2086 std::vector<Constant*> CV;
2087 for (unsigned i = 0, e = NumElems; i != e; ++i) {
2088 if (ConstantFPSDNode *V =
2089 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
2090 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
2091 } else if (ConstantSDNode *V =
2092 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
2094 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
2096 // If OpVT and EltVT don't match, EltVT is not legal and the
2097 // element values have been promoted/truncated earlier. Undo this;
2098 // we don't want a v16i8 to become a v16i32 for example.
2099 const ConstantInt *CI = V->getConstantIntValue();
2100 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
2101 CI->getZExtValue()));
2104 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
2105 Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
2106 CV.push_back(UndefValue::get(OpNTy));
2109 Constant *CP = ConstantVector::get(CV);
2110 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
2111 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2112 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
2113 MachinePointerInfo::getConstantPool(),
2114 false, false, Alignment);
2117 if (!MoreThanTwoValues) {
2118 SmallVector<int, 8> ShuffleVec(NumElems, -1);
2119 for (unsigned i = 0; i < NumElems; ++i) {
2120 SDValue V = Node->getOperand(i);
2121 if (V.getOpcode() == ISD::UNDEF)
2123 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
2125 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
2126 // Get the splatted value into the low element of a vector register.
2127 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
2129 if (Value2.getNode())
2130 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
2132 Vec2 = DAG.getUNDEF(VT);
2134 // Return shuffle(LowValVec, undef, <0,0,0,0>)
2135 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
2139 // Otherwise, we can't handle this case efficiently.
2140 return ExpandVectorBuildThroughStack(Node);
2143 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
2144 // does not fit into a register, return the lo part and set the hi part to the
2145 // by-reg argument. If it does fit into a single register, return the result
2146 // and leave the Hi part unset.
2147 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
2149 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
2150 // The input chain to this libcall is the entry node of the function.
2151 // Legalizing the call will automatically add the previous call to the
2153 SDValue InChain = DAG.getEntryNode();
2155 TargetLowering::ArgListTy Args;
2156 TargetLowering::ArgListEntry Entry;
2157 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2158 EVT ArgVT = Node->getOperand(i).getValueType();
2159 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2160 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
2161 Entry.isSExt = isSigned;
2162 Entry.isZExt = !isSigned;
2163 Args.push_back(Entry);
2165 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2166 TLI.getPointerTy());
2168 // Splice the libcall in wherever FindInputOutputChains tells us to.
2169 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2171 // isTailCall may be true since the callee does not reference caller stack
2172 // frame. Check if it's in the right position.
2173 bool isTailCall = isInTailCallPosition(DAG, Node, TLI);
2174 std::pair<SDValue, SDValue> CallInfo =
2175 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
2176 0, TLI.getLibcallCallingConv(LC), isTailCall,
2177 /*isReturnValueUsed=*/true,
2178 Callee, Args, DAG, Node->getDebugLoc());
2180 if (!CallInfo.second.getNode())
2181 // It's a tailcall, return the chain (which is the DAG root).
2182 return DAG.getRoot();
2184 // Legalize the call sequence, starting with the chain. This will advance
2185 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
2186 // was added by LowerCallTo (guaranteeing proper serialization of calls).
2187 LegalizeOp(CallInfo.second);
2188 return CallInfo.first;
2191 /// ExpandLibCall - Generate a libcall taking the given operands as arguments
2192 /// and returning a result of type RetVT.
2193 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, EVT RetVT,
2194 const SDValue *Ops, unsigned NumOps,
2195 bool isSigned, DebugLoc dl) {
2196 TargetLowering::ArgListTy Args;
2197 Args.reserve(NumOps);
2199 TargetLowering::ArgListEntry Entry;
2200 for (unsigned i = 0; i != NumOps; ++i) {
2201 Entry.Node = Ops[i];
2202 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
2203 Entry.isSExt = isSigned;
2204 Entry.isZExt = !isSigned;
2205 Args.push_back(Entry);
2207 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2208 TLI.getPointerTy());
2210 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2211 std::pair<SDValue,SDValue> CallInfo =
2212 TLI.LowerCallTo(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
2213 false, 0, TLI.getLibcallCallingConv(LC), false,
2214 /*isReturnValueUsed=*/true,
2215 Callee, Args, DAG, dl);
2217 // Legalize the call sequence, starting with the chain. This will advance
2218 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
2219 // was added by LowerCallTo (guaranteeing proper serialization of calls).
2220 LegalizeOp(CallInfo.second);
2222 return CallInfo.first;
2225 // ExpandChainLibCall - Expand a node into a call to a libcall. Similar to
2226 // ExpandLibCall except that the first operand is the in-chain.
2227 std::pair<SDValue, SDValue>
2228 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
2231 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
2232 SDValue InChain = Node->getOperand(0);
2234 TargetLowering::ArgListTy Args;
2235 TargetLowering::ArgListEntry Entry;
2236 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) {
2237 EVT ArgVT = Node->getOperand(i).getValueType();
2238 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2239 Entry.Node = Node->getOperand(i);
2241 Entry.isSExt = isSigned;
2242 Entry.isZExt = !isSigned;
2243 Args.push_back(Entry);
2245 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2246 TLI.getPointerTy());
2248 // Splice the libcall in wherever FindInputOutputChains tells us to.
2249 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2250 std::pair<SDValue, SDValue> CallInfo =
2251 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
2252 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
2253 /*isReturnValueUsed=*/true,
2254 Callee, Args, DAG, Node->getDebugLoc());
2256 // Legalize the call sequence, starting with the chain. This will advance
2257 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
2258 // was added by LowerCallTo (guaranteeing proper serialization of calls).
2259 LegalizeOp(CallInfo.second);
2263 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
2264 RTLIB::Libcall Call_F32,
2265 RTLIB::Libcall Call_F64,
2266 RTLIB::Libcall Call_F80,
2267 RTLIB::Libcall Call_PPCF128) {
2269 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
2270 default: assert(0 && "Unexpected request for libcall!");
2271 case MVT::f32: LC = Call_F32; break;
2272 case MVT::f64: LC = Call_F64; break;
2273 case MVT::f80: LC = Call_F80; break;
2274 case MVT::ppcf128: LC = Call_PPCF128; break;
2276 return ExpandLibCall(LC, Node, false);
2279 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
2280 RTLIB::Libcall Call_I8,
2281 RTLIB::Libcall Call_I16,
2282 RTLIB::Libcall Call_I32,
2283 RTLIB::Libcall Call_I64,
2284 RTLIB::Libcall Call_I128) {
2286 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
2287 default: assert(0 && "Unexpected request for libcall!");
2288 case MVT::i8: LC = Call_I8; break;
2289 case MVT::i16: LC = Call_I16; break;
2290 case MVT::i32: LC = Call_I32; break;
2291 case MVT::i64: LC = Call_I64; break;
2292 case MVT::i128: LC = Call_I128; break;
2294 return ExpandLibCall(LC, Node, isSigned);
2297 /// isDivRemLibcallAvailable - Return true if divmod libcall is available.
2298 static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
2299 const TargetLowering &TLI) {
2301 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
2302 default: assert(0 && "Unexpected request for libcall!");
2303 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2304 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2305 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2306 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2307 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2310 return TLI.getLibcallName(LC) != 0;
2313 /// UseDivRem - Only issue divrem libcall if both quotient and remainder are
2315 static bool UseDivRem(SDNode *Node, bool isSigned, bool isDIV) {
2316 unsigned OtherOpcode = 0;
2318 OtherOpcode = isDIV ? ISD::SREM : ISD::SDIV;
2320 OtherOpcode = isDIV ? ISD::UREM : ISD::UDIV;
2322 SDValue Op0 = Node->getOperand(0);
2323 SDValue Op1 = Node->getOperand(1);
2324 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2325 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2329 if (User->getOpcode() == OtherOpcode &&
2330 User->getOperand(0) == Op0 &&
2331 User->getOperand(1) == Op1)
2337 /// ExpandDivRemLibCall - Issue libcalls to __{u}divmod to compute div / rem
2340 SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
2341 SmallVectorImpl<SDValue> &Results) {
2342 unsigned Opcode = Node->getOpcode();
2343 bool isSigned = Opcode == ISD::SDIVREM;
2346 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
2347 default: assert(0 && "Unexpected request for libcall!");
2348 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2349 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2350 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2351 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2352 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2355 // The input chain to this libcall is the entry node of the function.
2356 // Legalizing the call will automatically add the previous call to the
2358 SDValue InChain = DAG.getEntryNode();
2360 EVT RetVT = Node->getValueType(0);
2361 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2363 TargetLowering::ArgListTy Args;
2364 TargetLowering::ArgListEntry Entry;
2365 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2366 EVT ArgVT = Node->getOperand(i).getValueType();
2367 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2368 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
2369 Entry.isSExt = isSigned;
2370 Entry.isZExt = !isSigned;
2371 Args.push_back(Entry);
2374 // Also pass the return address of the remainder.
2375 SDValue FIPtr = DAG.CreateStackTemporary(RetVT);
2377 Entry.Ty = RetTy->getPointerTo();
2378 Entry.isSExt = isSigned;
2379 Entry.isZExt = !isSigned;
2380 Args.push_back(Entry);
2382 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2383 TLI.getPointerTy());
2385 // Splice the libcall in wherever FindInputOutputChains tells us to.
2386 DebugLoc dl = Node->getDebugLoc();
2387 std::pair<SDValue, SDValue> CallInfo =
2388 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
2389 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
2390 /*isReturnValueUsed=*/true, Callee, Args, DAG, dl);
2392 // Legalize the call sequence, starting with the chain. This will advance
2393 // the LastCALLSEQ to the legalized version of the CALLSEQ_END node that
2394 // was added by LowerCallTo (guaranteeing proper serialization of calls).
2395 LegalizeOp(CallInfo.second);
2397 // Remainder is loaded back from the stack frame.
2398 SDValue Rem = DAG.getLoad(RetVT, dl, LastCALLSEQ_END, FIPtr,
2399 MachinePointerInfo(), false, false, 0);
2400 Results.push_back(CallInfo.first);
2401 Results.push_back(Rem);
2404 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
2405 /// INT_TO_FP operation of the specified operand when the target requests that
2406 /// we expand it. At this point, we know that the result and operand types are
2407 /// legal for the target.
2408 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
2412 if (Op0.getValueType() == MVT::i32) {
2413 // simple 32-bit [signed|unsigned] integer to float/double expansion
2415 // Get the stack frame index of a 8 byte buffer.
2416 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2418 // word offset constant for Hi/Lo address computation
2419 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
2420 // set up Hi and Lo (into buffer) address based on endian
2421 SDValue Hi = StackSlot;
2422 SDValue Lo = DAG.getNode(ISD::ADD, dl,
2423 TLI.getPointerTy(), StackSlot, WordOff);
2424 if (TLI.isLittleEndian())
2427 // if signed map to unsigned space
2430 // constant used to invert sign bit (signed to unsigned mapping)
2431 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
2432 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2436 // store the lo of the constructed double - based on integer input
2437 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
2438 Op0Mapped, Lo, MachinePointerInfo(),
2440 // initial hi portion of constructed double
2441 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
2442 // store the hi of the constructed double - biased exponent
2443 SDValue Store2 = DAG.getStore(Store1, dl, InitialHi, Hi,
2444 MachinePointerInfo(),
2446 // load the constructed double
2447 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot,
2448 MachinePointerInfo(), false, false, 0);
2449 // FP constant to bias correct the final result
2450 SDValue Bias = DAG.getConstantFP(isSigned ?
2451 BitsToDouble(0x4330000080000000ULL) :
2452 BitsToDouble(0x4330000000000000ULL),
2454 // subtract the bias
2455 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2458 // handle final rounding
2459 if (DestVT == MVT::f64) {
2462 } else if (DestVT.bitsLT(MVT::f64)) {
2463 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2464 DAG.getIntPtrConstant(0));
2465 } else if (DestVT.bitsGT(MVT::f64)) {
2466 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2470 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2471 // Code below here assumes !isSigned without checking again.
2473 // Implementation of unsigned i64 to f64 following the algorithm in
2474 // __floatundidf in compiler_rt. This implementation has the advantage
2475 // of performing rounding correctly, both in the default rounding mode
2476 // and in all alternate rounding modes.
2477 // TODO: Generalize this for use with other types.
2478 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
2480 DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64);
2481 SDValue TwoP84PlusTwoP52 =
2482 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64);
2484 DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64);
2486 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32);
2487 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2488 DAG.getConstant(32, MVT::i64));
2489 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2490 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2491 SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr);
2492 SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr);
2493 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
2495 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
2498 // Implementation of unsigned i64 to f32.
2499 // TODO: Generalize this for use with other types.
2500 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) {
2501 // For unsigned conversions, convert them to signed conversions using the
2502 // algorithm from the x86_64 __floatundidf in compiler_rt.
2504 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0);
2506 SDValue ShiftConst =
2507 DAG.getConstant(1, TLI.getShiftAmountTy(Op0.getValueType()));
2508 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
2509 SDValue AndConst = DAG.getConstant(1, MVT::i64);
2510 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst);
2511 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr);
2513 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or);
2514 SDValue Slow = DAG.getNode(ISD::FADD, dl, MVT::f32, SignCvt, SignCvt);
2516 // TODO: This really should be implemented using a branch rather than a
2517 // select. We happen to get lucky and machinesink does the right
2518 // thing most of the time. This would be a good candidate for a
2519 //pseudo-op, or, even better, for whole-function isel.
2520 SDValue SignBitTest = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2521 Op0, DAG.getConstant(0, MVT::i64), ISD::SETLT);
2522 return DAG.getNode(ISD::SELECT, dl, MVT::f32, SignBitTest, Slow, Fast);
2525 // Otherwise, implement the fully general conversion.
2527 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2528 DAG.getConstant(UINT64_C(0xfffffffffffff800), MVT::i64));
2529 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
2530 DAG.getConstant(UINT64_C(0x800), MVT::i64));
2531 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2532 DAG.getConstant(UINT64_C(0x7ff), MVT::i64));
2533 SDValue Ne = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2534 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE);
2535 SDValue Sel = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ne, Or, Op0);
2536 SDValue Ge = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2537 Op0, DAG.getConstant(UINT64_C(0x0020000000000000), MVT::i64),
2539 SDValue Sel2 = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ge, Sel, Op0);
2540 EVT SHVT = TLI.getShiftAmountTy(Sel2.getValueType());
2542 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2543 DAG.getConstant(32, SHVT));
2544 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh);
2545 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc);
2547 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), MVT::f64);
2548 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt);
2549 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2);
2550 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo);
2551 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2);
2552 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd,
2553 DAG.getIntPtrConstant(0));
2556 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2558 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()),
2559 Op0, DAG.getConstant(0, Op0.getValueType()),
2561 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
2562 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
2563 SignSet, Four, Zero);
2565 // If the sign bit of the integer is set, the large number will be treated
2566 // as a negative number. To counteract this, the dynamic code adds an
2567 // offset depending on the data type.
2569 switch (Op0.getValueType().getSimpleVT().SimpleTy) {
2570 default: assert(0 && "Unsupported integer type!");
2571 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2572 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2573 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2574 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2576 if (TLI.isLittleEndian()) FF <<= 32;
2577 Constant *FudgeFactor = ConstantInt::get(
2578 Type::getInt64Ty(*DAG.getContext()), FF);
2580 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
2581 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2582 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
2583 Alignment = std::min(Alignment, 4u);
2585 if (DestVT == MVT::f32)
2586 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2587 MachinePointerInfo::getConstantPool(),
2588 false, false, Alignment);
2591 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
2592 DAG.getEntryNode(), CPIdx,
2593 MachinePointerInfo::getConstantPool(),
2594 MVT::f32, false, false, Alignment));
2597 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2600 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
2601 /// *INT_TO_FP operation of the specified operand when the target requests that
2602 /// we promote it. At this point, we know that the result and operand types are
2603 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2604 /// operation that takes a larger input.
2605 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2609 // First step, figure out the appropriate *INT_TO_FP operation to use.
2610 EVT NewInTy = LegalOp.getValueType();
2612 unsigned OpToUse = 0;
2614 // Scan for the appropriate larger type to use.
2616 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2617 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2619 // If the target supports SINT_TO_FP of this type, use it.
2620 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2621 OpToUse = ISD::SINT_TO_FP;
2624 if (isSigned) continue;
2626 // If the target supports UINT_TO_FP of this type, use it.
2627 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2628 OpToUse = ISD::UINT_TO_FP;
2632 // Otherwise, try a larger type.
2635 // Okay, we found the operation and type to use. Zero extend our input to the
2636 // desired type then run the operation on it.
2637 return DAG.getNode(OpToUse, dl, DestVT,
2638 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2639 dl, NewInTy, LegalOp));
2642 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
2643 /// FP_TO_*INT operation of the specified operand when the target requests that
2644 /// we promote it. At this point, we know that the result and operand types are
2645 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2646 /// operation that returns a larger result.
2647 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2651 // First step, figure out the appropriate FP_TO*INT operation to use.
2652 EVT NewOutTy = DestVT;
2654 unsigned OpToUse = 0;
2656 // Scan for the appropriate larger type to use.
2658 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2659 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2661 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2662 OpToUse = ISD::FP_TO_SINT;
2666 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2667 OpToUse = ISD::FP_TO_UINT;
2671 // Otherwise, try a larger type.
2675 // Okay, we found the operation and type to use.
2676 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2678 // Truncate the result of the extended FP_TO_*INT operation to the desired
2680 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2683 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
2685 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) {
2686 EVT VT = Op.getValueType();
2687 EVT SHVT = TLI.getShiftAmountTy(VT);
2688 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2689 switch (VT.getSimpleVT().SimpleTy) {
2690 default: assert(0 && "Unhandled Expand type in BSWAP!");
2692 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2693 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2694 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2696 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2697 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2698 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2699 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2700 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
2701 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
2702 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2703 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2704 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2706 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
2707 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
2708 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2709 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2710 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2711 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2712 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
2713 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
2714 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
2715 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
2716 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
2717 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
2718 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
2719 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
2720 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2721 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2722 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2723 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2724 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2725 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2726 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2730 /// SplatByte - Distribute ByteVal over NumBits bits.
2731 // FIXME: Move this helper to a common place.
2732 static APInt SplatByte(unsigned NumBits, uint8_t ByteVal) {
2733 APInt Val = APInt(NumBits, ByteVal);
2735 for (unsigned i = NumBits; i > 8; i >>= 1) {
2736 Val = (Val << Shift) | Val;
2742 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
2744 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2747 default: assert(0 && "Cannot expand this yet!");
2749 EVT VT = Op.getValueType();
2750 EVT ShVT = TLI.getShiftAmountTy(VT);
2751 unsigned Len = VT.getSizeInBits();
2753 assert(VT.isInteger() && Len <= 128 && Len % 8 == 0 &&
2754 "CTPOP not implemented for this type.");
2756 // This is the "best" algorithm from
2757 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
2759 SDValue Mask55 = DAG.getConstant(SplatByte(Len, 0x55), VT);
2760 SDValue Mask33 = DAG.getConstant(SplatByte(Len, 0x33), VT);
2761 SDValue Mask0F = DAG.getConstant(SplatByte(Len, 0x0F), VT);
2762 SDValue Mask01 = DAG.getConstant(SplatByte(Len, 0x01), VT);
2764 // v = v - ((v >> 1) & 0x55555555...)
2765 Op = DAG.getNode(ISD::SUB, dl, VT, Op,
2766 DAG.getNode(ISD::AND, dl, VT,
2767 DAG.getNode(ISD::SRL, dl, VT, Op,
2768 DAG.getConstant(1, ShVT)),
2770 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
2771 Op = DAG.getNode(ISD::ADD, dl, VT,
2772 DAG.getNode(ISD::AND, dl, VT, Op, Mask33),
2773 DAG.getNode(ISD::AND, dl, VT,
2774 DAG.getNode(ISD::SRL, dl, VT, Op,
2775 DAG.getConstant(2, ShVT)),
2777 // v = (v + (v >> 4)) & 0x0F0F0F0F...
2778 Op = DAG.getNode(ISD::AND, dl, VT,
2779 DAG.getNode(ISD::ADD, dl, VT, Op,
2780 DAG.getNode(ISD::SRL, dl, VT, Op,
2781 DAG.getConstant(4, ShVT))),
2783 // v = (v * 0x01010101...) >> (Len - 8)
2784 Op = DAG.getNode(ISD::SRL, dl, VT,
2785 DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
2786 DAG.getConstant(Len - 8, ShVT));
2791 // for now, we do this:
2792 // x = x | (x >> 1);
2793 // x = x | (x >> 2);
2795 // x = x | (x >>16);
2796 // x = x | (x >>32); // for 64-bit input
2797 // return popcount(~x);
2799 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
2800 EVT VT = Op.getValueType();
2801 EVT ShVT = TLI.getShiftAmountTy(VT);
2802 unsigned len = VT.getSizeInBits();
2803 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2804 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2805 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2806 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2808 Op = DAG.getNOT(dl, Op, VT);
2809 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2812 // for now, we use: { return popcount(~x & (x - 1)); }
2813 // unless the target has ctlz but not ctpop, in which case we use:
2814 // { return 32 - nlz(~x & (x-1)); }
2815 // see also http://www.hackersdelight.org/HDcode/ntz.cc
2816 EVT VT = Op.getValueType();
2817 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2818 DAG.getNOT(dl, Op, VT),
2819 DAG.getNode(ISD::SUB, dl, VT, Op,
2820 DAG.getConstant(1, VT)));
2821 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2822 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2823 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2824 return DAG.getNode(ISD::SUB, dl, VT,
2825 DAG.getConstant(VT.getSizeInBits(), VT),
2826 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2827 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2832 std::pair <SDValue, SDValue> SelectionDAGLegalize::ExpandAtomic(SDNode *Node) {
2833 unsigned Opc = Node->getOpcode();
2834 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
2839 llvm_unreachable("Unhandled atomic intrinsic Expand!");
2841 case ISD::ATOMIC_SWAP:
2842 switch (VT.SimpleTy) {
2843 default: llvm_unreachable("Unexpected value type for atomic!");
2844 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break;
2845 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
2846 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
2847 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
2850 case ISD::ATOMIC_CMP_SWAP:
2851 switch (VT.SimpleTy) {
2852 default: llvm_unreachable("Unexpected value type for atomic!");
2853 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break;
2854 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;
2855 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;
2856 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
2859 case ISD::ATOMIC_LOAD_ADD:
2860 switch (VT.SimpleTy) {
2861 default: llvm_unreachable("Unexpected value type for atomic!");
2862 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break;
2863 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;
2864 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;
2865 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
2868 case ISD::ATOMIC_LOAD_SUB:
2869 switch (VT.SimpleTy) {
2870 default: llvm_unreachable("Unexpected value type for atomic!");
2871 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break;
2872 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;
2873 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;
2874 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
2877 case ISD::ATOMIC_LOAD_AND:
2878 switch (VT.SimpleTy) {
2879 default: llvm_unreachable("Unexpected value type for atomic!");
2880 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break;
2881 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;
2882 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;
2883 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
2886 case ISD::ATOMIC_LOAD_OR:
2887 switch (VT.SimpleTy) {
2888 default: llvm_unreachable("Unexpected value type for atomic!");
2889 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break;
2890 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;
2891 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;
2892 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
2895 case ISD::ATOMIC_LOAD_XOR:
2896 switch (VT.SimpleTy) {
2897 default: llvm_unreachable("Unexpected value type for atomic!");
2898 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break;
2899 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;
2900 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;
2901 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
2904 case ISD::ATOMIC_LOAD_NAND:
2905 switch (VT.SimpleTy) {
2906 default: llvm_unreachable("Unexpected value type for atomic!");
2907 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break;
2908 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;
2909 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;
2910 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
2915 return ExpandChainLibCall(LC, Node, false);
2918 void SelectionDAGLegalize::ExpandNode(SDNode *Node,
2919 SmallVectorImpl<SDValue> &Results) {
2920 DebugLoc dl = Node->getDebugLoc();
2921 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2922 switch (Node->getOpcode()) {
2926 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
2927 Results.push_back(Tmp1);
2930 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2932 case ISD::FRAMEADDR:
2933 case ISD::RETURNADDR:
2934 case ISD::FRAME_TO_ARGS_OFFSET:
2935 Results.push_back(DAG.getConstant(0, Node->getValueType(0)));
2937 case ISD::FLT_ROUNDS_:
2938 Results.push_back(DAG.getConstant(1, Node->getValueType(0)));
2940 case ISD::EH_RETURN:
2944 case ISD::EH_SJLJ_LONGJMP:
2945 case ISD::EH_SJLJ_DISPATCHSETUP:
2946 // If the target didn't expand these, there's nothing to do, so just
2947 // preserve the chain and be done.
2948 Results.push_back(Node->getOperand(0));
2950 case ISD::EH_SJLJ_SETJMP:
2951 // If the target didn't expand this, just return 'zero' and preserve the
2953 Results.push_back(DAG.getConstant(0, MVT::i32));
2954 Results.push_back(Node->getOperand(0));
2956 case ISD::ATOMIC_FENCE:
2957 case ISD::MEMBARRIER: {
2958 // If the target didn't lower this, lower it to '__sync_synchronize()' call
2959 // FIXME: handle "fence singlethread" more efficiently.
2960 TargetLowering::ArgListTy Args;
2961 std::pair<SDValue, SDValue> CallResult =
2962 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()),
2963 false, false, false, false, 0, CallingConv::C,
2964 /*isTailCall=*/false,
2965 /*isReturnValueUsed=*/true,
2966 DAG.getExternalSymbol("__sync_synchronize",
2967 TLI.getPointerTy()),
2969 Results.push_back(CallResult.second);
2972 case ISD::ATOMIC_LOAD: {
2973 // There is no libcall for atomic load; fake it with ATOMIC_CMP_SWAP.
2974 SDValue Zero = DAG.getConstant(0, Node->getValueType(0));
2975 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl,
2976 cast<AtomicSDNode>(Node)->getMemoryVT(),
2977 Node->getOperand(0),
2978 Node->getOperand(1), Zero, Zero,
2979 cast<AtomicSDNode>(Node)->getMemOperand(),
2980 cast<AtomicSDNode>(Node)->getOrdering(),
2981 cast<AtomicSDNode>(Node)->getSynchScope());
2982 Results.push_back(Swap.getValue(0));
2983 Results.push_back(Swap.getValue(1));
2986 case ISD::ATOMIC_STORE: {
2987 // There is no libcall for atomic store; fake it with ATOMIC_SWAP.
2988 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
2989 cast<AtomicSDNode>(Node)->getMemoryVT(),
2990 Node->getOperand(0),
2991 Node->getOperand(1), Node->getOperand(2),
2992 cast<AtomicSDNode>(Node)->getMemOperand(),
2993 cast<AtomicSDNode>(Node)->getOrdering(),
2994 cast<AtomicSDNode>(Node)->getSynchScope());
2995 Results.push_back(Swap.getValue(1));
2998 // By default, atomic intrinsics are marked Legal and lowered. Targets
2999 // which don't support them directly, however, may want libcalls, in which
3000 // case they mark them Expand, and we get here.
3001 case ISD::ATOMIC_SWAP:
3002 case ISD::ATOMIC_LOAD_ADD:
3003 case ISD::ATOMIC_LOAD_SUB:
3004 case ISD::ATOMIC_LOAD_AND:
3005 case ISD::ATOMIC_LOAD_OR:
3006 case ISD::ATOMIC_LOAD_XOR:
3007 case ISD::ATOMIC_LOAD_NAND:
3008 case ISD::ATOMIC_LOAD_MIN:
3009 case ISD::ATOMIC_LOAD_MAX:
3010 case ISD::ATOMIC_LOAD_UMIN:
3011 case ISD::ATOMIC_LOAD_UMAX:
3012 case ISD::ATOMIC_CMP_SWAP: {
3013 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node);
3014 Results.push_back(Tmp.first);
3015 Results.push_back(Tmp.second);
3018 case ISD::DYNAMIC_STACKALLOC:
3019 ExpandDYNAMIC_STACKALLOC(Node, Results);
3021 case ISD::MERGE_VALUES:
3022 for (unsigned i = 0; i < Node->getNumValues(); i++)
3023 Results.push_back(Node->getOperand(i));
3026 EVT VT = Node->getValueType(0);
3028 Results.push_back(DAG.getConstant(0, VT));
3030 assert(VT.isFloatingPoint() && "Unknown value type!");
3031 Results.push_back(DAG.getConstantFP(0, VT));
3036 // If this operation is not supported, lower it to 'abort()' call
3037 TargetLowering::ArgListTy Args;
3038 std::pair<SDValue, SDValue> CallResult =
3039 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()),
3040 false, false, false, false, 0, CallingConv::C,
3041 /*isTailCall=*/false,
3042 /*isReturnValueUsed=*/true,
3043 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
3045 Results.push_back(CallResult.second);
3050 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3051 Node->getValueType(0), dl);
3052 Results.push_back(Tmp1);
3054 case ISD::FP_EXTEND:
3055 Tmp1 = EmitStackConvert(Node->getOperand(0),
3056 Node->getOperand(0).getValueType(),
3057 Node->getValueType(0), dl);
3058 Results.push_back(Tmp1);
3060 case ISD::SIGN_EXTEND_INREG: {
3061 // NOTE: we could fall back on load/store here too for targets without
3062 // SAR. However, it is doubtful that any exist.
3063 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3064 EVT VT = Node->getValueType(0);
3065 EVT ShiftAmountTy = TLI.getShiftAmountTy(VT);
3068 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
3069 ExtraVT.getScalarType().getSizeInBits();
3070 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy);
3071 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
3072 Node->getOperand(0), ShiftCst);
3073 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
3074 Results.push_back(Tmp1);
3077 case ISD::FP_ROUND_INREG: {
3078 // The only way we can lower this is to turn it into a TRUNCSTORE,
3079 // EXTLOAD pair, targeting a temporary location (a stack slot).
3081 // NOTE: there is a choice here between constantly creating new stack
3082 // slots and always reusing the same one. We currently always create
3083 // new ones, as reuse may inhibit scheduling.
3084 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3085 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
3086 Node->getValueType(0), dl);
3087 Results.push_back(Tmp1);
3090 case ISD::SINT_TO_FP:
3091 case ISD::UINT_TO_FP:
3092 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
3093 Node->getOperand(0), Node->getValueType(0), dl);
3094 Results.push_back(Tmp1);
3096 case ISD::FP_TO_UINT: {
3097 SDValue True, False;
3098 EVT VT = Node->getOperand(0).getValueType();
3099 EVT NVT = Node->getValueType(0);
3100 APFloat apf(APInt::getNullValue(VT.getSizeInBits()));
3101 APInt x = APInt::getSignBit(NVT.getSizeInBits());
3102 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
3103 Tmp1 = DAG.getConstantFP(apf, VT);
3104 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
3105 Node->getOperand(0),
3107 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
3108 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
3109 DAG.getNode(ISD::FSUB, dl, VT,
3110 Node->getOperand(0), Tmp1));
3111 False = DAG.getNode(ISD::XOR, dl, NVT, False,
3112 DAG.getConstant(x, NVT));
3113 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False);
3114 Results.push_back(Tmp1);
3118 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3119 EVT VT = Node->getValueType(0);
3120 Tmp1 = Node->getOperand(0);
3121 Tmp2 = Node->getOperand(1);
3122 unsigned Align = Node->getConstantOperandVal(3);
3124 SDValue VAListLoad = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2,
3125 MachinePointerInfo(V), false, false, 0);
3126 SDValue VAList = VAListLoad;
3128 if (Align > TLI.getMinStackArgumentAlignment()) {
3129 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
3131 VAList = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
3132 DAG.getConstant(Align - 1,
3133 TLI.getPointerTy()));
3135 VAList = DAG.getNode(ISD::AND, dl, TLI.getPointerTy(), VAList,
3136 DAG.getConstant(-(int64_t)Align,
3137 TLI.getPointerTy()));
3140 // Increment the pointer, VAList, to the next vaarg
3141 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
3142 DAG.getConstant(TLI.getTargetData()->
3143 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())),
3144 TLI.getPointerTy()));
3145 // Store the incremented VAList to the legalized pointer
3146 Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2,
3147 MachinePointerInfo(V), false, false, 0);
3148 // Load the actual argument out of the pointer VAList
3149 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(),
3151 Results.push_back(Results[0].getValue(1));
3155 // This defaults to loading a pointer from the input and storing it to the
3156 // output, returning the chain.
3157 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3158 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3159 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0),
3160 Node->getOperand(2), MachinePointerInfo(VS),
3162 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1),
3163 MachinePointerInfo(VD), false, false, 0);
3164 Results.push_back(Tmp1);
3167 case ISD::EXTRACT_VECTOR_ELT:
3168 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
3169 // This must be an access of the only element. Return it.
3170 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
3171 Node->getOperand(0));
3173 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
3174 Results.push_back(Tmp1);
3176 case ISD::EXTRACT_SUBVECTOR:
3177 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
3179 case ISD::INSERT_SUBVECTOR:
3180 Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0)));
3182 case ISD::CONCAT_VECTORS: {
3183 Results.push_back(ExpandVectorBuildThroughStack(Node));
3186 case ISD::SCALAR_TO_VECTOR:
3187 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
3189 case ISD::INSERT_VECTOR_ELT:
3190 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
3191 Node->getOperand(1),
3192 Node->getOperand(2), dl));
3194 case ISD::VECTOR_SHUFFLE: {
3195 SmallVector<int, 8> Mask;
3196 cast<ShuffleVectorSDNode>(Node)->getMask(Mask);
3198 EVT VT = Node->getValueType(0);
3199 EVT EltVT = VT.getVectorElementType();
3200 if (!TLI.isTypeLegal(EltVT))
3201 EltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
3202 unsigned NumElems = VT.getVectorNumElements();
3203 SmallVector<SDValue, 8> Ops;
3204 for (unsigned i = 0; i != NumElems; ++i) {
3206 Ops.push_back(DAG.getUNDEF(EltVT));
3209 unsigned Idx = Mask[i];
3211 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3212 Node->getOperand(0),
3213 DAG.getIntPtrConstant(Idx)));
3215 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3216 Node->getOperand(1),
3217 DAG.getIntPtrConstant(Idx - NumElems)));
3219 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
3220 Results.push_back(Tmp1);
3223 case ISD::EXTRACT_ELEMENT: {
3224 EVT OpTy = Node->getOperand(0).getValueType();
3225 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
3227 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
3228 DAG.getConstant(OpTy.getSizeInBits()/2,
3229 TLI.getShiftAmountTy(Node->getOperand(0).getValueType())));
3230 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
3233 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
3234 Node->getOperand(0));
3236 Results.push_back(Tmp1);
3239 case ISD::STACKSAVE:
3240 // Expand to CopyFromReg if the target set
3241 // StackPointerRegisterToSaveRestore.
3242 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3243 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
3244 Node->getValueType(0)));
3245 Results.push_back(Results[0].getValue(1));
3247 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
3248 Results.push_back(Node->getOperand(0));
3251 case ISD::STACKRESTORE:
3252 // Expand to CopyToReg if the target set
3253 // StackPointerRegisterToSaveRestore.
3254 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3255 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
3256 Node->getOperand(1)));
3258 Results.push_back(Node->getOperand(0));
3261 case ISD::FCOPYSIGN:
3262 Results.push_back(ExpandFCOPYSIGN(Node));
3265 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3266 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3267 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
3268 Node->getOperand(0));
3269 Results.push_back(Tmp1);
3272 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3273 EVT VT = Node->getValueType(0);
3274 Tmp1 = Node->getOperand(0);
3275 Tmp2 = DAG.getConstantFP(0.0, VT);
3276 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
3277 Tmp1, Tmp2, ISD::SETUGT);
3278 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
3279 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3);
3280 Results.push_back(Tmp1);
3284 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3285 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128));
3288 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
3289 RTLIB::SIN_F80, RTLIB::SIN_PPCF128));
3292 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
3293 RTLIB::COS_F80, RTLIB::COS_PPCF128));
3296 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
3297 RTLIB::LOG_F80, RTLIB::LOG_PPCF128));
3300 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3301 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128));
3304 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3305 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128));
3308 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
3309 RTLIB::EXP_F80, RTLIB::EXP_PPCF128));
3312 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3313 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128));
3316 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3317 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128));
3320 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3321 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128));
3324 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3325 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128));
3328 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
3329 RTLIB::RINT_F80, RTLIB::RINT_PPCF128));
3331 case ISD::FNEARBYINT:
3332 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
3333 RTLIB::NEARBYINT_F64,
3334 RTLIB::NEARBYINT_F80,
3335 RTLIB::NEARBYINT_PPCF128));
3338 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
3339 RTLIB::POWI_F80, RTLIB::POWI_PPCF128));
3342 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
3343 RTLIB::POW_F80, RTLIB::POW_PPCF128));
3346 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
3347 RTLIB::DIV_F80, RTLIB::DIV_PPCF128));
3350 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
3351 RTLIB::REM_F80, RTLIB::REM_PPCF128));
3354 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMA_F32, RTLIB::FMA_F64,
3355 RTLIB::FMA_F80, RTLIB::FMA_PPCF128));
3357 case ISD::FP16_TO_FP32:
3358 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
3360 case ISD::FP32_TO_FP16:
3361 Results.push_back(ExpandLibCall(RTLIB::FPROUND_F32_F16, Node, false));
3363 case ISD::ConstantFP: {
3364 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
3365 // Check to see if this FP immediate is already legal.
3366 // If this is a legal constant, turn it into a TargetConstantFP node.
3367 if (TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
3368 Results.push_back(SDValue(Node, 0));
3370 Results.push_back(ExpandConstantFP(CFP, true, DAG, TLI));
3373 case ISD::EHSELECTION: {
3374 unsigned Reg = TLI.getExceptionSelectorRegister();
3375 assert(Reg && "Can't expand to unknown register!");
3376 Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg,
3377 Node->getValueType(0)));
3378 Results.push_back(Results[0].getValue(1));
3381 case ISD::EXCEPTIONADDR: {
3382 unsigned Reg = TLI.getExceptionAddressRegister();
3383 assert(Reg && "Can't expand to unknown register!");
3384 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg,
3385 Node->getValueType(0)));
3386 Results.push_back(Results[0].getValue(1));
3390 EVT VT = Node->getValueType(0);
3391 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3392 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3393 "Don't know how to expand this subtraction!");
3394 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3395 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
3396 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT));
3397 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3402 EVT VT = Node->getValueType(0);
3403 SDVTList VTs = DAG.getVTList(VT, VT);
3404 bool isSigned = Node->getOpcode() == ISD::SREM;
3405 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3406 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3407 Tmp2 = Node->getOperand(0);
3408 Tmp3 = Node->getOperand(1);
3409 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3410 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3411 UseDivRem(Node, isSigned, false))) {
3412 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
3413 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
3415 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
3416 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3417 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3418 } else if (isSigned)
3419 Tmp1 = ExpandIntLibCall(Node, true,
3421 RTLIB::SREM_I16, RTLIB::SREM_I32,
3422 RTLIB::SREM_I64, RTLIB::SREM_I128);
3424 Tmp1 = ExpandIntLibCall(Node, false,
3426 RTLIB::UREM_I16, RTLIB::UREM_I32,
3427 RTLIB::UREM_I64, RTLIB::UREM_I128);
3428 Results.push_back(Tmp1);
3433 bool isSigned = Node->getOpcode() == ISD::SDIV;
3434 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3435 EVT VT = Node->getValueType(0);
3436 SDVTList VTs = DAG.getVTList(VT, VT);
3437 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3438 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3439 UseDivRem(Node, isSigned, true)))
3440 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
3441 Node->getOperand(1));
3443 Tmp1 = ExpandIntLibCall(Node, true,
3445 RTLIB::SDIV_I16, RTLIB::SDIV_I32,
3446 RTLIB::SDIV_I64, RTLIB::SDIV_I128);
3448 Tmp1 = ExpandIntLibCall(Node, false,
3450 RTLIB::UDIV_I16, RTLIB::UDIV_I32,
3451 RTLIB::UDIV_I64, RTLIB::UDIV_I128);
3452 Results.push_back(Tmp1);
3457 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
3459 EVT VT = Node->getValueType(0);
3460 SDVTList VTs = DAG.getVTList(VT, VT);
3461 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
3462 "If this wasn't legal, it shouldn't have been created!");
3463 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
3464 Node->getOperand(1));
3465 Results.push_back(Tmp1.getValue(1));
3470 // Expand into divrem libcall
3471 ExpandDivRemLibCall(Node, Results);
3474 EVT VT = Node->getValueType(0);
3475 SDVTList VTs = DAG.getVTList(VT, VT);
3476 // See if multiply or divide can be lowered using two-result operations.
3477 // We just need the low half of the multiply; try both the signed
3478 // and unsigned forms. If the target supports both SMUL_LOHI and
3479 // UMUL_LOHI, form a preference by checking which forms of plain
3480 // MULH it supports.
3481 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3482 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3483 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3484 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3485 unsigned OpToUse = 0;
3486 if (HasSMUL_LOHI && !HasMULHS) {
3487 OpToUse = ISD::SMUL_LOHI;
3488 } else if (HasUMUL_LOHI && !HasMULHU) {
3489 OpToUse = ISD::UMUL_LOHI;
3490 } else if (HasSMUL_LOHI) {
3491 OpToUse = ISD::SMUL_LOHI;
3492 } else if (HasUMUL_LOHI) {
3493 OpToUse = ISD::UMUL_LOHI;
3496 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
3497 Node->getOperand(1)));
3500 Tmp1 = ExpandIntLibCall(Node, false,
3502 RTLIB::MUL_I16, RTLIB::MUL_I32,
3503 RTLIB::MUL_I64, RTLIB::MUL_I128);
3504 Results.push_back(Tmp1);
3509 SDValue LHS = Node->getOperand(0);
3510 SDValue RHS = Node->getOperand(1);
3511 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3512 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3514 Results.push_back(Sum);
3515 EVT OType = Node->getValueType(1);
3517 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
3519 // LHSSign -> LHS >= 0
3520 // RHSSign -> RHS >= 0
3521 // SumSign -> Sum >= 0
3524 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3526 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3528 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3529 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3530 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
3531 Node->getOpcode() == ISD::SADDO ?
3532 ISD::SETEQ : ISD::SETNE);
3534 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3535 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3537 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3538 Results.push_back(Cmp);
3543 SDValue LHS = Node->getOperand(0);
3544 SDValue RHS = Node->getOperand(1);
3545 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
3546 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3548 Results.push_back(Sum);
3549 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS,
3550 Node->getOpcode () == ISD::UADDO ?
3551 ISD::SETULT : ISD::SETUGT));
3556 EVT VT = Node->getValueType(0);
3557 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
3558 SDValue LHS = Node->getOperand(0);
3559 SDValue RHS = Node->getOperand(1);
3562 static const unsigned Ops[2][3] =
3563 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
3564 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
3565 bool isSigned = Node->getOpcode() == ISD::SMULO;
3566 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3567 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3568 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3569 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3570 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3572 TopHalf = BottomHalf.getValue(1);
3573 } else if (TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(),
3574 VT.getSizeInBits() * 2))) {
3575 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
3576 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
3577 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
3578 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3579 DAG.getIntPtrConstant(0));
3580 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3581 DAG.getIntPtrConstant(1));
3583 // We can fall back to a libcall with an illegal type for the MUL if we
3584 // have a libcall big enough.
3585 // Also, we can fall back to a division in some cases, but that's a big
3586 // performance hit in the general case.
3587 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3588 if (WideVT == MVT::i16)
3589 LC = RTLIB::MUL_I16;
3590 else if (WideVT == MVT::i32)
3591 LC = RTLIB::MUL_I32;
3592 else if (WideVT == MVT::i64)
3593 LC = RTLIB::MUL_I64;
3594 else if (WideVT == MVT::i128)
3595 LC = RTLIB::MUL_I128;
3596 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!");
3598 // The high part is obtained by SRA'ing all but one of the bits of low
3600 unsigned LoSize = VT.getSizeInBits();
3601 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, RHS,
3602 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
3603 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, VT, LHS,
3604 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
3606 // Here we're passing the 2 arguments explicitly as 4 arguments that are
3607 // pre-lowered to the correct types. This all depends upon WideVT not
3608 // being a legal type for the architecture and thus has to be split to
3610 SDValue Args[] = { LHS, HiLHS, RHS, HiRHS };
3611 SDValue Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl);
3612 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3613 DAG.getIntPtrConstant(0));
3614 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3615 DAG.getIntPtrConstant(1));
3619 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1,
3620 TLI.getShiftAmountTy(BottomHalf.getValueType()));
3621 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3622 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1,
3625 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf,
3626 DAG.getConstant(0, VT), ISD::SETNE);
3628 Results.push_back(BottomHalf);
3629 Results.push_back(TopHalf);
3632 case ISD::BUILD_PAIR: {
3633 EVT PairTy = Node->getValueType(0);
3634 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3635 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3636 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
3637 DAG.getConstant(PairTy.getSizeInBits()/2,
3638 TLI.getShiftAmountTy(PairTy)));
3639 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3643 Tmp1 = Node->getOperand(0);
3644 Tmp2 = Node->getOperand(1);
3645 Tmp3 = Node->getOperand(2);
3646 if (Tmp1.getOpcode() == ISD::SETCC) {
3647 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3649 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3651 Tmp1 = DAG.getSelectCC(dl, Tmp1,
3652 DAG.getConstant(0, Tmp1.getValueType()),
3653 Tmp2, Tmp3, ISD::SETNE);
3655 Results.push_back(Tmp1);
3658 SDValue Chain = Node->getOperand(0);
3659 SDValue Table = Node->getOperand(1);
3660 SDValue Index = Node->getOperand(2);
3662 EVT PTy = TLI.getPointerTy();
3664 const TargetData &TD = *TLI.getTargetData();
3665 unsigned EntrySize =
3666 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
3668 Index = DAG.getNode(ISD::MUL, dl, PTy,
3669 Index, DAG.getConstant(EntrySize, PTy));
3670 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
3672 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
3673 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
3674 MachinePointerInfo::getJumpTable(), MemVT,
3677 if (TM.getRelocationModel() == Reloc::PIC_) {
3678 // For PIC, the sequence is:
3679 // BRIND(load(Jumptable + index) + RelocBase)
3680 // RelocBase can be JumpTable, GOT or some sort of global base.
3681 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3682 TLI.getPICJumpTableRelocBase(Table, DAG));
3684 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
3685 Results.push_back(Tmp1);
3689 // Expand brcond's setcc into its constituent parts and create a BR_CC
3691 Tmp1 = Node->getOperand(0);
3692 Tmp2 = Node->getOperand(1);
3693 if (Tmp2.getOpcode() == ISD::SETCC) {
3694 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3695 Tmp1, Tmp2.getOperand(2),
3696 Tmp2.getOperand(0), Tmp2.getOperand(1),
3697 Node->getOperand(2));
3699 // We test only the i1 bit. Skip the AND if UNDEF.
3700 Tmp3 = (Tmp2.getOpcode() == ISD::UNDEF) ? Tmp2 :
3701 DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2,
3702 DAG.getConstant(1, Tmp2.getValueType()));
3703 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3704 DAG.getCondCode(ISD::SETNE), Tmp3,
3705 DAG.getConstant(0, Tmp3.getValueType()),
3706 Node->getOperand(2));
3708 Results.push_back(Tmp1);
3711 Tmp1 = Node->getOperand(0);
3712 Tmp2 = Node->getOperand(1);
3713 Tmp3 = Node->getOperand(2);
3714 LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl);
3716 // If we expanded the SETCC into an AND/OR, return the new node
3717 if (Tmp2.getNode() == 0) {
3718 Results.push_back(Tmp1);
3722 // Otherwise, SETCC for the given comparison type must be completely
3723 // illegal; expand it into a SELECT_CC.
3724 EVT VT = Node->getValueType(0);
3725 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3726 DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3);
3727 Results.push_back(Tmp1);
3730 case ISD::SELECT_CC: {
3731 Tmp1 = Node->getOperand(0); // LHS
3732 Tmp2 = Node->getOperand(1); // RHS
3733 Tmp3 = Node->getOperand(2); // True
3734 Tmp4 = Node->getOperand(3); // False
3735 SDValue CC = Node->getOperand(4);
3737 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()),
3738 Tmp1, Tmp2, CC, dl);
3740 assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!");
3741 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3742 CC = DAG.getCondCode(ISD::SETNE);
3743 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2,
3745 Results.push_back(Tmp1);
3749 Tmp1 = Node->getOperand(0); // Chain
3750 Tmp2 = Node->getOperand(2); // LHS
3751 Tmp3 = Node->getOperand(3); // RHS
3752 Tmp4 = Node->getOperand(1); // CC
3754 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()),
3755 Tmp2, Tmp3, Tmp4, dl);
3756 LastCALLSEQ_END = DAG.getEntryNode();
3758 assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!");
3759 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
3760 Tmp4 = DAG.getCondCode(ISD::SETNE);
3761 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2,
3762 Tmp3, Node->getOperand(4));
3763 Results.push_back(Tmp1);
3766 case ISD::GLOBAL_OFFSET_TABLE:
3767 case ISD::GlobalAddress:
3768 case ISD::GlobalTLSAddress:
3769 case ISD::ExternalSymbol:
3770 case ISD::ConstantPool:
3771 case ISD::JumpTable:
3772 case ISD::INTRINSIC_W_CHAIN:
3773 case ISD::INTRINSIC_WO_CHAIN:
3774 case ISD::INTRINSIC_VOID:
3775 // FIXME: Custom lowering for these operations shouldn't return null!
3776 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
3777 Results.push_back(SDValue(Node, i));
3781 void SelectionDAGLegalize::PromoteNode(SDNode *Node,
3782 SmallVectorImpl<SDValue> &Results) {
3783 EVT OVT = Node->getValueType(0);
3784 if (Node->getOpcode() == ISD::UINT_TO_FP ||
3785 Node->getOpcode() == ISD::SINT_TO_FP ||
3786 Node->getOpcode() == ISD::SETCC) {
3787 OVT = Node->getOperand(0).getValueType();
3789 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3790 DebugLoc dl = Node->getDebugLoc();
3791 SDValue Tmp1, Tmp2, Tmp3;
3792 switch (Node->getOpcode()) {
3796 // Zero extend the argument.
3797 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3798 // Perform the larger operation.
3799 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
3800 if (Node->getOpcode() == ISD::CTTZ) {
3801 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3802 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
3803 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
3805 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
3806 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3807 } else if (Node->getOpcode() == ISD::CTLZ) {
3808 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3809 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
3810 DAG.getConstant(NVT.getSizeInBits() -
3811 OVT.getSizeInBits(), NVT));
3813 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
3816 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3817 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3818 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
3819 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
3820 DAG.getConstant(DiffBits, TLI.getShiftAmountTy(NVT)));
3821 Results.push_back(Tmp1);
3824 case ISD::FP_TO_UINT:
3825 case ISD::FP_TO_SINT:
3826 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
3827 Node->getOpcode() == ISD::FP_TO_SINT, dl);
3828 Results.push_back(Tmp1);
3830 case ISD::UINT_TO_FP:
3831 case ISD::SINT_TO_FP:
3832 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
3833 Node->getOpcode() == ISD::SINT_TO_FP, dl);
3834 Results.push_back(Tmp1);
3839 unsigned ExtOp, TruncOp;
3840 if (OVT.isVector()) {
3841 ExtOp = ISD::BITCAST;
3842 TruncOp = ISD::BITCAST;
3844 assert(OVT.isInteger() && "Cannot promote logic operation");
3845 ExtOp = ISD::ANY_EXTEND;
3846 TruncOp = ISD::TRUNCATE;
3848 // Promote each of the values to the new type.
3849 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3850 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3851 // Perform the larger operation, then convert back
3852 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3853 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
3857 unsigned ExtOp, TruncOp;
3858 if (Node->getValueType(0).isVector()) {
3859 ExtOp = ISD::BITCAST;
3860 TruncOp = ISD::BITCAST;
3861 } else if (Node->getValueType(0).isInteger()) {
3862 ExtOp = ISD::ANY_EXTEND;
3863 TruncOp = ISD::TRUNCATE;
3865 ExtOp = ISD::FP_EXTEND;
3866 TruncOp = ISD::FP_ROUND;
3868 Tmp1 = Node->getOperand(0);
3869 // Promote each of the values to the new type.
3870 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3871 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
3872 // Perform the larger operation, then round down.
3873 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3);
3874 if (TruncOp != ISD::FP_ROUND)
3875 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
3877 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
3878 DAG.getIntPtrConstant(0));
3879 Results.push_back(Tmp1);
3882 case ISD::VECTOR_SHUFFLE: {
3883 SmallVector<int, 8> Mask;
3884 cast<ShuffleVectorSDNode>(Node)->getMask(Mask);
3886 // Cast the two input vectors.
3887 Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
3888 Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
3890 // Convert the shuffle mask to the right # elements.
3891 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
3892 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
3893 Results.push_back(Tmp1);
3897 unsigned ExtOp = ISD::FP_EXTEND;
3898 if (NVT.isInteger()) {
3899 ISD::CondCode CCCode =
3900 cast<CondCodeSDNode>(Node->getOperand(2))->get();
3901 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3903 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3904 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3905 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3906 Tmp1, Tmp2, Node->getOperand(2)));
3912 // SelectionDAG::Legalize - This is the entry point for the file.
3914 void SelectionDAG::Legalize() {
3915 /// run - This is the main entry point to this class.
3917 SelectionDAGLegalize(*this).LegalizeDAG();