1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Analysis/DebugInfo.h"
15 #include "llvm/CodeGen/Analysis.h"
16 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/SelectionDAG.h"
19 #include "llvm/Target/TargetFrameLowering.h"
20 #include "llvm/Target/TargetLowering.h"
21 #include "llvm/Target/TargetData.h"
22 #include "llvm/Target/TargetMachine.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/Constants.h"
25 #include "llvm/DerivedTypes.h"
26 #include "llvm/LLVMContext.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/MathExtras.h"
30 #include "llvm/Support/raw_ostream.h"
31 #include "llvm/ADT/DenseMap.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/SmallPtrSet.h"
36 //===----------------------------------------------------------------------===//
37 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
38 /// hacks on it until the target machine can handle it. This involves
39 /// eliminating value sizes the machine cannot handle (promoting small sizes to
40 /// large sizes or splitting up large values into small values) as well as
41 /// eliminating operations the machine cannot handle.
43 /// This code also does a small amount of optimization and recognition of idioms
44 /// as part of its processing. For example, if a target does not support a
45 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
46 /// will attempt merge setcc and brc instructions into brcc's.
49 class SelectionDAGLegalize : public SelectionDAG::DAGUpdateListener {
50 const TargetMachine &TM;
51 const TargetLowering &TLI;
54 /// LegalizePosition - The iterator for walking through the node list.
55 SelectionDAG::allnodes_iterator LegalizePosition;
57 /// LegalizedNodes - The set of nodes which have already been legalized.
58 SmallPtrSet<SDNode *, 16> LegalizedNodes;
60 // Libcall insertion helpers.
63 explicit SelectionDAGLegalize(SelectionDAG &DAG);
68 /// LegalizeOp - Legalizes the given operation.
69 void LegalizeOp(SDNode *Node);
71 SDValue OptimizeFloatStore(StoreSDNode *ST);
73 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
74 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
75 /// is necessary to spill the vector being inserted into to memory, perform
76 /// the insert there, and then read the result back.
77 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
78 SDValue Idx, DebugLoc dl);
79 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
80 SDValue Idx, DebugLoc dl);
82 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
83 /// performs the same shuffe in terms of order or result bytes, but on a type
84 /// whose vector element type is narrower than the original shuffle type.
85 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
86 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
87 SDValue N1, SDValue N2,
88 ArrayRef<int> Mask) const;
90 void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
93 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
94 SDValue ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops,
95 unsigned NumOps, bool isSigned, DebugLoc dl);
97 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
98 SDNode *Node, bool isSigned);
99 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
100 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
101 RTLIB::Libcall Call_PPCF128);
102 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
103 RTLIB::Libcall Call_I8,
104 RTLIB::Libcall Call_I16,
105 RTLIB::Libcall Call_I32,
106 RTLIB::Libcall Call_I64,
107 RTLIB::Libcall Call_I128);
108 void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
110 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl);
111 SDValue ExpandBUILD_VECTOR(SDNode *Node);
112 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
113 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
114 SmallVectorImpl<SDValue> &Results);
115 SDValue ExpandFCOPYSIGN(SDNode *Node);
116 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
118 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
120 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
123 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl);
124 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl);
126 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
127 SDValue ExpandInsertToVectorThroughStack(SDValue Op);
128 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
130 SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP);
132 std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node);
134 void ExpandNode(SDNode *Node);
135 void PromoteNode(SDNode *Node);
137 void ForgetNode(SDNode *N) {
138 LegalizedNodes.erase(N);
139 if (LegalizePosition == SelectionDAG::allnodes_iterator(N))
144 // DAGUpdateListener implementation.
145 virtual void NodeDeleted(SDNode *N, SDNode *E) {
148 virtual void NodeUpdated(SDNode *N) {}
150 // Node replacement helpers
151 void ReplacedNode(SDNode *N) {
152 if (N->use_empty()) {
153 DAG.RemoveDeadNode(N);
158 void ReplaceNode(SDNode *Old, SDNode *New) {
159 DAG.ReplaceAllUsesWith(Old, New);
162 void ReplaceNode(SDValue Old, SDValue New) {
163 DAG.ReplaceAllUsesWith(Old, New);
164 ReplacedNode(Old.getNode());
166 void ReplaceNode(SDNode *Old, const SDValue *New) {
167 DAG.ReplaceAllUsesWith(Old, New);
173 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
174 /// performs the same shuffe in terms of order or result bytes, but on a type
175 /// whose vector element type is narrower than the original shuffle type.
176 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
178 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
179 SDValue N1, SDValue N2,
180 ArrayRef<int> Mask) const {
181 unsigned NumMaskElts = VT.getVectorNumElements();
182 unsigned NumDestElts = NVT.getVectorNumElements();
183 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
185 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
187 if (NumEltsGrowth == 1)
188 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
190 SmallVector<int, 8> NewMask;
191 for (unsigned i = 0; i != NumMaskElts; ++i) {
193 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
195 NewMask.push_back(-1);
197 NewMask.push_back(Idx * NumEltsGrowth + j);
200 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
201 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
202 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
205 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
206 : SelectionDAG::DAGUpdateListener(dag),
207 TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()),
211 void SelectionDAGLegalize::LegalizeDAG() {
212 DAG.AssignTopologicalOrder();
214 // Visit all the nodes. We start in topological order, so that we see
215 // nodes with their original operands intact. Legalization can produce
216 // new nodes which may themselves need to be legalized. Iterate until all
217 // nodes have been legalized.
219 bool AnyLegalized = false;
220 for (LegalizePosition = DAG.allnodes_end();
221 LegalizePosition != DAG.allnodes_begin(); ) {
224 SDNode *N = LegalizePosition;
225 if (LegalizedNodes.insert(N)) {
235 // Remove dead nodes now.
236 DAG.RemoveDeadNodes();
239 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
240 /// a load from the constant pool.
242 SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) {
244 DebugLoc dl = CFP->getDebugLoc();
246 // If a FP immediate is precise when represented as a float and if the
247 // target can do an extending load from float to double, we put it into
248 // the constant pool as a float, even if it's is statically typed as a
249 // double. This shrinks FP constants and canonicalizes them for targets where
250 // an FP extending load is the same cost as a normal load (such as on the x87
251 // fp stack or PPC FP unit).
252 EVT VT = CFP->getValueType(0);
253 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
255 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
256 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
257 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
262 while (SVT != MVT::f32) {
263 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
264 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) &&
265 // Only do this if the target has a native EXTLOAD instruction from
267 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
268 TLI.ShouldShrinkFPConstant(OrigVT)) {
269 Type *SType = SVT.getTypeForEVT(*DAG.getContext());
270 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
276 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
277 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
280 DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT,
282 CPIdx, MachinePointerInfo::getConstantPool(),
283 VT, false, false, Alignment);
287 DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
288 MachinePointerInfo::getConstantPool(), false, false, false,
293 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
294 static void ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
295 const TargetLowering &TLI,
296 SelectionDAGLegalize *DAGLegalize) {
297 assert(ST->getAddressingMode() == ISD::UNINDEXED &&
298 "unaligned indexed stores not implemented!");
299 SDValue Chain = ST->getChain();
300 SDValue Ptr = ST->getBasePtr();
301 SDValue Val = ST->getValue();
302 EVT VT = Val.getValueType();
303 int Alignment = ST->getAlignment();
304 DebugLoc dl = ST->getDebugLoc();
305 if (ST->getMemoryVT().isFloatingPoint() ||
306 ST->getMemoryVT().isVector()) {
307 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
308 if (TLI.isTypeLegal(intVT)) {
309 // Expand to a bitconvert of the value to the integer type of the
310 // same size, then a (misaligned) int store.
311 // FIXME: Does not handle truncating floating point stores!
312 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
313 Result = DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
314 ST->isVolatile(), ST->isNonTemporal(), Alignment);
315 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
318 // Do a (aligned) store to a stack slot, then copy from the stack slot
319 // to the final destination using (unaligned) integer loads and stores.
320 EVT StoredVT = ST->getMemoryVT();
322 TLI.getRegisterType(*DAG.getContext(),
323 EVT::getIntegerVT(*DAG.getContext(),
324 StoredVT.getSizeInBits()));
325 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
326 unsigned RegBytes = RegVT.getSizeInBits() / 8;
327 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
329 // Make sure the stack slot is also aligned for the register type.
330 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
332 // Perform the original store, only redirected to the stack slot.
333 SDValue Store = DAG.getTruncStore(Chain, dl,
334 Val, StackPtr, MachinePointerInfo(),
335 StoredVT, false, false, 0);
336 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
337 SmallVector<SDValue, 8> Stores;
340 // Do all but one copies using the full register width.
341 for (unsigned i = 1; i < NumRegs; i++) {
342 // Load one integer register's worth from the stack slot.
343 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr,
344 MachinePointerInfo(),
345 false, false, false, 0);
346 // Store it to the final location. Remember the store.
347 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
348 ST->getPointerInfo().getWithOffset(Offset),
349 ST->isVolatile(), ST->isNonTemporal(),
350 MinAlign(ST->getAlignment(), Offset)));
351 // Increment the pointers.
353 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
355 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
358 // The last store may be partial. Do a truncating store. On big-endian
359 // machines this requires an extending load from the stack slot to ensure
360 // that the bits are in the right place.
361 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
362 8 * (StoredBytes - Offset));
364 // Load from the stack slot.
365 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
366 MachinePointerInfo(),
367 MemVT, false, false, 0);
369 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
371 .getWithOffset(Offset),
372 MemVT, ST->isVolatile(),
374 MinAlign(ST->getAlignment(), Offset)));
375 // The order of the stores doesn't matter - say it with a TokenFactor.
377 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
379 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
382 assert(ST->getMemoryVT().isInteger() &&
383 !ST->getMemoryVT().isVector() &&
384 "Unaligned store of unknown type.");
385 // Get the half-size VT
386 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext());
387 int NumBits = NewStoredVT.getSizeInBits();
388 int IncrementSize = NumBits / 8;
390 // Divide the stored value in two parts.
391 SDValue ShiftAmount = DAG.getConstant(NumBits,
392 TLI.getShiftAmountTy(Val.getValueType()));
394 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
396 // Store the two parts
397 SDValue Store1, Store2;
398 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
399 ST->getPointerInfo(), NewStoredVT,
400 ST->isVolatile(), ST->isNonTemporal(), Alignment);
401 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
402 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
403 Alignment = MinAlign(Alignment, IncrementSize);
404 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
405 ST->getPointerInfo().getWithOffset(IncrementSize),
406 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(),
410 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
411 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
414 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
416 ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
417 const TargetLowering &TLI,
418 SDValue &ValResult, SDValue &ChainResult) {
419 assert(LD->getAddressingMode() == ISD::UNINDEXED &&
420 "unaligned indexed loads not implemented!");
421 SDValue Chain = LD->getChain();
422 SDValue Ptr = LD->getBasePtr();
423 EVT VT = LD->getValueType(0);
424 EVT LoadedVT = LD->getMemoryVT();
425 DebugLoc dl = LD->getDebugLoc();
426 if (VT.isFloatingPoint() || VT.isVector()) {
427 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
428 if (TLI.isTypeLegal(intVT)) {
429 // Expand to a (misaligned) integer load of the same size,
430 // then bitconvert to floating point or vector.
431 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getPointerInfo(),
434 LD->isInvariant(), LD->getAlignment());
435 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad);
436 if (VT.isFloatingPoint() && LoadedVT != VT)
437 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result);
444 // Copy the value to a (aligned) stack slot using (unaligned) integer
445 // loads and stores, then do a (aligned) load from the stack slot.
446 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
447 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
448 unsigned RegBytes = RegVT.getSizeInBits() / 8;
449 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
451 // Make sure the stack slot is also aligned for the register type.
452 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
454 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
455 SmallVector<SDValue, 8> Stores;
456 SDValue StackPtr = StackBase;
459 // Do all but one copies using the full register width.
460 for (unsigned i = 1; i < NumRegs; i++) {
461 // Load one integer register's worth from the original location.
462 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr,
463 LD->getPointerInfo().getWithOffset(Offset),
464 LD->isVolatile(), LD->isNonTemporal(),
466 MinAlign(LD->getAlignment(), Offset));
467 // Follow the load with a store to the stack slot. Remember the store.
468 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
469 MachinePointerInfo(), false, false, 0));
470 // Increment the pointers.
472 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
473 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
477 // The last copy may be partial. Do an extending load.
478 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
479 8 * (LoadedBytes - Offset));
480 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
481 LD->getPointerInfo().getWithOffset(Offset),
482 MemVT, LD->isVolatile(),
484 MinAlign(LD->getAlignment(), Offset));
485 // Follow the load with a store to the stack slot. Remember the store.
486 // On big-endian machines this requires a truncating store to ensure
487 // that the bits end up in the right place.
488 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
489 MachinePointerInfo(), MemVT,
492 // The order of the stores doesn't matter - say it with a TokenFactor.
493 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
496 // Finally, perform the original load only redirected to the stack slot.
497 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
498 MachinePointerInfo(), LoadedVT, false, false, 0);
500 // Callers expect a MERGE_VALUES node.
505 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
506 "Unaligned load of unsupported type.");
508 // Compute the new VT that is half the size of the old one. This is an
510 unsigned NumBits = LoadedVT.getSizeInBits();
512 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
515 unsigned Alignment = LD->getAlignment();
516 unsigned IncrementSize = NumBits / 8;
517 ISD::LoadExtType HiExtType = LD->getExtensionType();
519 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
520 if (HiExtType == ISD::NON_EXTLOAD)
521 HiExtType = ISD::ZEXTLOAD;
523 // Load the value in two parts
525 if (TLI.isLittleEndian()) {
526 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
527 NewLoadedVT, LD->isVolatile(),
528 LD->isNonTemporal(), Alignment);
529 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
530 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
531 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr,
532 LD->getPointerInfo().getWithOffset(IncrementSize),
533 NewLoadedVT, LD->isVolatile(),
534 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
536 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(),
537 NewLoadedVT, LD->isVolatile(),
538 LD->isNonTemporal(), Alignment);
539 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
540 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
541 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
542 LD->getPointerInfo().getWithOffset(IncrementSize),
543 NewLoadedVT, LD->isVolatile(),
544 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
547 // aggregate the two parts
548 SDValue ShiftAmount = DAG.getConstant(NumBits,
549 TLI.getShiftAmountTy(Hi.getValueType()));
550 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
551 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
553 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
560 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
561 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
562 /// is necessary to spill the vector being inserted into to memory, perform
563 /// the insert there, and then read the result back.
564 SDValue SelectionDAGLegalize::
565 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
571 // If the target doesn't support this, we have to spill the input vector
572 // to a temporary stack slot, update the element, then reload it. This is
573 // badness. We could also load the value into a vector register (either
574 // with a "move to register" or "extload into register" instruction, then
575 // permute it into place, if the idx is a constant and if the idx is
576 // supported by the target.
577 EVT VT = Tmp1.getValueType();
578 EVT EltVT = VT.getVectorElementType();
579 EVT IdxVT = Tmp3.getValueType();
580 EVT PtrVT = TLI.getPointerTy();
581 SDValue StackPtr = DAG.CreateStackTemporary(VT);
583 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
586 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
587 MachinePointerInfo::getFixedStack(SPFI),
590 // Truncate or zero extend offset to target pointer type.
591 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
592 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
593 // Add the offset to the index.
594 unsigned EltSize = EltVT.getSizeInBits()/8;
595 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
596 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
597 // Store the scalar value.
598 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT,
600 // Load the updated vector.
601 return DAG.getLoad(VT, dl, Ch, StackPtr,
602 MachinePointerInfo::getFixedStack(SPFI), false, false,
607 SDValue SelectionDAGLegalize::
608 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) {
609 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
610 // SCALAR_TO_VECTOR requires that the type of the value being inserted
611 // match the element type of the vector being created, except for
612 // integers in which case the inserted value can be over width.
613 EVT EltVT = Vec.getValueType().getVectorElementType();
614 if (Val.getValueType() == EltVT ||
615 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
616 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
617 Vec.getValueType(), Val);
619 unsigned NumElts = Vec.getValueType().getVectorNumElements();
620 // We generate a shuffle of InVec and ScVec, so the shuffle mask
621 // should be 0,1,2,3,4,5... with the appropriate element replaced with
623 SmallVector<int, 8> ShufOps;
624 for (unsigned i = 0; i != NumElts; ++i)
625 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
627 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
631 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
634 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
635 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
636 // FIXME: We shouldn't do this for TargetConstantFP's.
637 // FIXME: move this to the DAG Combiner! Note that we can't regress due
638 // to phase ordering between legalized code and the dag combiner. This
639 // probably means that we need to integrate dag combiner and legalizer
641 // We generally can't do this one for long doubles.
642 SDValue Tmp1 = ST->getChain();
643 SDValue Tmp2 = ST->getBasePtr();
645 unsigned Alignment = ST->getAlignment();
646 bool isVolatile = ST->isVolatile();
647 bool isNonTemporal = ST->isNonTemporal();
648 DebugLoc dl = ST->getDebugLoc();
649 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
650 if (CFP->getValueType(0) == MVT::f32 &&
651 TLI.isTypeLegal(MVT::i32)) {
652 Tmp3 = DAG.getConstant(CFP->getValueAPF().
653 bitcastToAPInt().zextOrTrunc(32),
655 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
656 isVolatile, isNonTemporal, Alignment);
659 if (CFP->getValueType(0) == MVT::f64) {
660 // If this target supports 64-bit registers, do a single 64-bit store.
661 if (TLI.isTypeLegal(MVT::i64)) {
662 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
663 zextOrTrunc(64), MVT::i64);
664 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
665 isVolatile, isNonTemporal, Alignment);
668 if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) {
669 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
670 // stores. If the target supports neither 32- nor 64-bits, this
671 // xform is certainly not worth it.
672 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
673 SDValue Lo = DAG.getConstant(IntVal.trunc(32), MVT::i32);
674 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
675 if (TLI.isBigEndian()) std::swap(Lo, Hi);
677 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getPointerInfo(), isVolatile,
678 isNonTemporal, Alignment);
679 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
680 DAG.getIntPtrConstant(4));
681 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2,
682 ST->getPointerInfo().getWithOffset(4),
683 isVolatile, isNonTemporal, MinAlign(Alignment, 4U));
685 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
689 return SDValue(0, 0);
692 /// LegalizeOp - Return a legal replacement for the given operation, with
693 /// all legal operands.
694 void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
695 if (Node->getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
698 DebugLoc dl = Node->getDebugLoc();
700 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
701 assert(TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) ==
702 TargetLowering::TypeLegal &&
703 "Unexpected illegal type!");
705 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
706 assert((TLI.getTypeAction(*DAG.getContext(),
707 Node->getOperand(i).getValueType()) ==
708 TargetLowering::TypeLegal ||
709 Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
710 "Unexpected illegal type!");
712 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
713 bool isCustom = false;
715 // Figure out the correct action; the way to query this varies by opcode
716 TargetLowering::LegalizeAction Action = TargetLowering::Legal;
717 bool SimpleFinishLegalizing = true;
718 switch (Node->getOpcode()) {
719 case ISD::INTRINSIC_W_CHAIN:
720 case ISD::INTRINSIC_WO_CHAIN:
721 case ISD::INTRINSIC_VOID:
723 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
726 Action = TLI.getOperationAction(Node->getOpcode(),
727 Node->getValueType(0));
728 if (Action != TargetLowering::Promote)
729 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
731 case ISD::SINT_TO_FP:
732 case ISD::UINT_TO_FP:
733 case ISD::EXTRACT_VECTOR_ELT:
734 Action = TLI.getOperationAction(Node->getOpcode(),
735 Node->getOperand(0).getValueType());
737 case ISD::FP_ROUND_INREG:
738 case ISD::SIGN_EXTEND_INREG: {
739 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
740 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
743 case ISD::ATOMIC_STORE: {
744 Action = TLI.getOperationAction(Node->getOpcode(),
745 Node->getOperand(2).getValueType());
751 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
752 Node->getOpcode() == ISD::SETCC ? 2 : 1;
753 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
754 EVT OpVT = Node->getOperand(CompareOperand).getValueType();
755 ISD::CondCode CCCode =
756 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
757 Action = TLI.getCondCodeAction(CCCode, OpVT);
758 if (Action == TargetLowering::Legal) {
759 if (Node->getOpcode() == ISD::SELECT_CC)
760 Action = TLI.getOperationAction(Node->getOpcode(),
761 Node->getValueType(0));
763 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
769 // FIXME: Model these properly. LOAD and STORE are complicated, and
770 // STORE expects the unlegalized operand in some cases.
771 SimpleFinishLegalizing = false;
773 case ISD::CALLSEQ_START:
774 case ISD::CALLSEQ_END:
775 // FIXME: This shouldn't be necessary. These nodes have special properties
776 // dealing with the recursive nature of legalization. Removing this
777 // special case should be done as part of making LegalizeDAG non-recursive.
778 SimpleFinishLegalizing = false;
780 case ISD::EXTRACT_ELEMENT:
781 case ISD::FLT_ROUNDS_:
789 case ISD::MERGE_VALUES:
791 case ISD::FRAME_TO_ARGS_OFFSET:
792 case ISD::EH_SJLJ_SETJMP:
793 case ISD::EH_SJLJ_LONGJMP:
794 // These operations lie about being legal: when they claim to be legal,
795 // they should actually be expanded.
796 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
797 if (Action == TargetLowering::Legal)
798 Action = TargetLowering::Expand;
800 case ISD::INIT_TRAMPOLINE:
801 case ISD::ADJUST_TRAMPOLINE:
803 case ISD::RETURNADDR:
804 // These operations lie about being legal: when they claim to be legal,
805 // they should actually be custom-lowered.
806 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
807 if (Action == TargetLowering::Legal)
808 Action = TargetLowering::Custom;
811 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
812 Action = TargetLowering::Legal;
814 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
819 if (SimpleFinishLegalizing) {
820 SDNode *NewNode = Node;
821 switch (Node->getOpcode()) {
828 // Legalizing shifts/rotates requires adjusting the shift amount
829 // to the appropriate width.
830 if (!Node->getOperand(1).getValueType().isVector()) {
832 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
833 Node->getOperand(1));
834 HandleSDNode Handle(SAO);
835 LegalizeOp(SAO.getNode());
836 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
843 // Legalizing shifts/rotates requires adjusting the shift amount
844 // to the appropriate width.
845 if (!Node->getOperand(2).getValueType().isVector()) {
847 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
848 Node->getOperand(2));
849 HandleSDNode Handle(SAO);
850 LegalizeOp(SAO.getNode());
851 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
858 if (NewNode != Node) {
859 DAG.ReplaceAllUsesWith(Node, NewNode);
860 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
861 DAG.TransferDbgValues(SDValue(Node, i), SDValue(NewNode, i));
866 case TargetLowering::Legal:
868 case TargetLowering::Custom:
869 // FIXME: The handling for custom lowering with multiple results is
871 Tmp1 = TLI.LowerOperation(SDValue(Node, 0), DAG);
872 if (Tmp1.getNode()) {
873 SmallVector<SDValue, 8> ResultVals;
874 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
876 ResultVals.push_back(Tmp1);
878 ResultVals.push_back(Tmp1.getValue(i));
880 if (Tmp1.getNode() != Node || Tmp1.getResNo() != 0) {
881 DAG.ReplaceAllUsesWith(Node, ResultVals.data());
882 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
883 DAG.TransferDbgValues(SDValue(Node, i), ResultVals[i]);
890 case TargetLowering::Expand:
893 case TargetLowering::Promote:
899 switch (Node->getOpcode()) {
906 llvm_unreachable("Do not know how to legalize this operator!");
908 case ISD::CALLSEQ_START:
909 case ISD::CALLSEQ_END:
912 LoadSDNode *LD = cast<LoadSDNode>(Node);
913 Tmp1 = LD->getChain(); // Legalize the chain.
914 Tmp2 = LD->getBasePtr(); // Legalize the base pointer.
916 ISD::LoadExtType ExtType = LD->getExtensionType();
917 if (ExtType == ISD::NON_EXTLOAD) {
918 EVT VT = Node->getValueType(0);
919 Tmp3 = SDValue(Node, 0);
920 Tmp4 = SDValue(Node, 1);
922 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
923 default: llvm_unreachable("This action is not supported yet!");
924 case TargetLowering::Legal:
925 // If this is an unaligned load and the target doesn't support it,
927 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
928 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
929 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
930 if (LD->getAlignment() < ABIAlignment){
931 ExpandUnalignedLoad(cast<LoadSDNode>(Node),
932 DAG, TLI, Tmp3, Tmp4);
936 case TargetLowering::Custom:
937 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
938 if (Tmp1.getNode()) {
940 Tmp4 = Tmp1.getValue(1);
943 case TargetLowering::Promote: {
944 // Only promote a load of vector type to another.
945 assert(VT.isVector() && "Cannot promote this load!");
946 // Change base type to a different vector type.
947 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
949 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getPointerInfo(),
950 LD->isVolatile(), LD->isNonTemporal(),
951 LD->isInvariant(), LD->getAlignment());
952 Tmp3 = DAG.getNode(ISD::BITCAST, dl, VT, Tmp1);
953 Tmp4 = Tmp1.getValue(1);
957 if (Tmp4.getNode() != Node) {
958 assert(Tmp3.getNode() != Node && "Load must be completely replaced");
959 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp3);
960 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Tmp4);
966 EVT SrcVT = LD->getMemoryVT();
967 unsigned SrcWidth = SrcVT.getSizeInBits();
968 unsigned Alignment = LD->getAlignment();
969 bool isVolatile = LD->isVolatile();
970 bool isNonTemporal = LD->isNonTemporal();
972 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
973 // Some targets pretend to have an i1 loading operation, and actually
974 // load an i8. This trick is correct for ZEXTLOAD because the top 7
975 // bits are guaranteed to be zero; it helps the optimizers understand
976 // that these bits are zero. It is also useful for EXTLOAD, since it
977 // tells the optimizers that those bits are undefined. It would be
978 // nice to have an effective generic way of getting these benefits...
979 // Until such a way is found, don't insist on promoting i1 here.
981 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
982 // Promote to a byte-sized load if not loading an integral number of
983 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
984 unsigned NewWidth = SrcVT.getStoreSizeInBits();
985 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
988 // The extra bits are guaranteed to be zero, since we stored them that
989 // way. A zext load from NVT thus automatically gives zext from SrcVT.
991 ISD::LoadExtType NewExtType =
992 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
995 DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
996 Tmp1, Tmp2, LD->getPointerInfo(),
997 NVT, isVolatile, isNonTemporal, Alignment);
999 Ch = Result.getValue(1); // The chain.
1001 if (ExtType == ISD::SEXTLOAD)
1002 // Having the top bits zero doesn't help when sign extending.
1003 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1004 Result.getValueType(),
1005 Result, DAG.getValueType(SrcVT));
1006 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
1007 // All the top bits are guaranteed to be zero - inform the optimizers.
1008 Result = DAG.getNode(ISD::AssertZext, dl,
1009 Result.getValueType(), Result,
1010 DAG.getValueType(SrcVT));
1014 } else if (SrcWidth & (SrcWidth - 1)) {
1015 // If not loading a power-of-2 number of bits, expand as two loads.
1016 assert(!SrcVT.isVector() && "Unsupported extload!");
1017 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
1018 assert(RoundWidth < SrcWidth);
1019 unsigned ExtraWidth = SrcWidth - RoundWidth;
1020 assert(ExtraWidth < RoundWidth);
1021 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1022 "Load size not an integral number of bytes!");
1023 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
1024 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
1026 unsigned IncrementSize;
1028 if (TLI.isLittleEndian()) {
1029 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1030 // Load the bottom RoundWidth bits.
1031 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0),
1033 LD->getPointerInfo(), RoundVT, isVolatile,
1034 isNonTemporal, Alignment);
1036 // Load the remaining ExtraWidth bits.
1037 IncrementSize = RoundWidth / 8;
1038 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1039 DAG.getIntPtrConstant(IncrementSize));
1040 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
1041 LD->getPointerInfo().getWithOffset(IncrementSize),
1042 ExtraVT, isVolatile, isNonTemporal,
1043 MinAlign(Alignment, IncrementSize));
1045 // Build a factor node to remember that this load is independent of
1047 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1050 // Move the top bits to the right place.
1051 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1052 DAG.getConstant(RoundWidth,
1053 TLI.getShiftAmountTy(Hi.getValueType())));
1055 // Join the hi and lo parts.
1056 Tmp1 = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1058 // Big endian - avoid unaligned loads.
1059 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1060 // Load the top RoundWidth bits.
1061 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
1062 LD->getPointerInfo(), RoundVT, isVolatile,
1063 isNonTemporal, Alignment);
1065 // Load the remaining ExtraWidth bits.
1066 IncrementSize = RoundWidth / 8;
1067 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1068 DAG.getIntPtrConstant(IncrementSize));
1069 Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
1070 dl, Node->getValueType(0), Tmp1, Tmp2,
1071 LD->getPointerInfo().getWithOffset(IncrementSize),
1072 ExtraVT, isVolatile, isNonTemporal,
1073 MinAlign(Alignment, IncrementSize));
1075 // Build a factor node to remember that this load is independent of
1077 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1080 // Move the top bits to the right place.
1081 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1082 DAG.getConstant(ExtraWidth,
1083 TLI.getShiftAmountTy(Hi.getValueType())));
1085 // Join the hi and lo parts.
1086 Tmp1 = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1091 switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
1092 default: llvm_unreachable("This action is not supported yet!");
1093 case TargetLowering::Custom:
1096 case TargetLowering::Legal:
1097 Tmp1 = SDValue(Node, 0);
1098 Tmp2 = SDValue(Node, 1);
1101 Tmp3 = TLI.LowerOperation(SDValue(Node, 0), DAG);
1102 if (Tmp3.getNode()) {
1104 Tmp2 = Tmp3.getValue(1);
1107 // If this is an unaligned load and the target doesn't support it,
1109 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
1111 LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1112 unsigned ABIAlignment =
1113 TLI.getTargetData()->getABITypeAlignment(Ty);
1114 if (LD->getAlignment() < ABIAlignment){
1115 ExpandUnalignedLoad(cast<LoadSDNode>(Node),
1116 DAG, TLI, Tmp1, Tmp2);
1121 case TargetLowering::Expand:
1122 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) && TLI.isTypeLegal(SrcVT)) {
1123 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2,
1124 LD->getPointerInfo(),
1125 LD->isVolatile(), LD->isNonTemporal(),
1126 LD->isInvariant(), LD->getAlignment());
1130 ExtendOp = (SrcVT.isFloatingPoint() ?
1131 ISD::FP_EXTEND : ISD::ANY_EXTEND);
1133 case ISD::SEXTLOAD: ExtendOp = ISD::SIGN_EXTEND; break;
1134 case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break;
1135 default: llvm_unreachable("Unexpected extend load type!");
1137 Tmp1 = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
1138 Tmp2 = Load.getValue(1);
1142 assert(!SrcVT.isVector() &&
1143 "Vector Loads are handled in LegalizeVectorOps");
1145 // FIXME: This does not work for vectors on most targets. Sign- and
1146 // zero-extend operations are currently folded into extending loads,
1147 // whether they are legal or not, and then we end up here without any
1148 // support for legalizing them.
1149 assert(ExtType != ISD::EXTLOAD &&
1150 "EXTLOAD should always be supported!");
1151 // Turn the unsupported load into an EXTLOAD followed by an explicit
1152 // zero/sign extend inreg.
1153 SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
1154 Tmp1, Tmp2, LD->getPointerInfo(), SrcVT,
1155 LD->isVolatile(), LD->isNonTemporal(),
1156 LD->getAlignment());
1158 if (ExtType == ISD::SEXTLOAD)
1159 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1160 Result.getValueType(),
1161 Result, DAG.getValueType(SrcVT));
1163 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType());
1165 Tmp2 = Result.getValue(1);
1170 // Since loads produce two values, make sure to remember that we legalized
1172 if (Tmp2.getNode() != Node) {
1173 assert(Tmp1.getNode() != Node && "Load must be completely replaced");
1174 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp1);
1175 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Tmp2);
1181 StoreSDNode *ST = cast<StoreSDNode>(Node);
1182 Tmp1 = ST->getChain();
1183 Tmp2 = ST->getBasePtr();
1184 unsigned Alignment = ST->getAlignment();
1185 bool isVolatile = ST->isVolatile();
1186 bool isNonTemporal = ST->isNonTemporal();
1188 if (!ST->isTruncatingStore()) {
1189 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
1190 ReplaceNode(ST, OptStore);
1195 Tmp3 = ST->getValue();
1196 EVT VT = Tmp3.getValueType();
1197 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1198 default: llvm_unreachable("This action is not supported yet!");
1199 case TargetLowering::Legal:
1200 // If this is an unaligned store and the target doesn't support it,
1202 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
1203 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
1204 unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty);
1205 if (ST->getAlignment() < ABIAlignment)
1206 ExpandUnalignedStore(cast<StoreSDNode>(Node),
1210 case TargetLowering::Custom:
1211 Tmp1 = TLI.LowerOperation(SDValue(Node, 0), DAG);
1213 ReplaceNode(SDValue(Node, 0), Tmp1);
1215 case TargetLowering::Promote: {
1216 assert(VT.isVector() && "Unknown legal promote case!");
1217 Tmp3 = DAG.getNode(ISD::BITCAST, dl,
1218 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
1220 DAG.getStore(Tmp1, dl, Tmp3, Tmp2,
1221 ST->getPointerInfo(), isVolatile,
1222 isNonTemporal, Alignment);
1223 ReplaceNode(SDValue(Node, 0), Result);
1230 Tmp3 = ST->getValue();
1232 EVT StVT = ST->getMemoryVT();
1233 unsigned StWidth = StVT.getSizeInBits();
1235 if (StWidth != StVT.getStoreSizeInBits()) {
1236 // Promote to a byte-sized store with upper bits zero if not
1237 // storing an integral number of bytes. For example, promote
1238 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
1239 EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
1240 StVT.getStoreSizeInBits());
1241 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT);
1243 DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
1244 NVT, isVolatile, isNonTemporal, Alignment);
1245 ReplaceNode(SDValue(Node, 0), Result);
1246 } else if (StWidth & (StWidth - 1)) {
1247 // If not storing a power-of-2 number of bits, expand as two stores.
1248 assert(!StVT.isVector() && "Unsupported truncstore!");
1249 unsigned RoundWidth = 1 << Log2_32(StWidth);
1250 assert(RoundWidth < StWidth);
1251 unsigned ExtraWidth = StWidth - RoundWidth;
1252 assert(ExtraWidth < RoundWidth);
1253 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1254 "Store size not an integral number of bytes!");
1255 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
1256 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
1258 unsigned IncrementSize;
1260 if (TLI.isLittleEndian()) {
1261 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
1262 // Store the bottom RoundWidth bits.
1263 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
1265 isVolatile, isNonTemporal, Alignment);
1267 // Store the remaining ExtraWidth bits.
1268 IncrementSize = RoundWidth / 8;
1269 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1270 DAG.getIntPtrConstant(IncrementSize));
1271 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
1272 DAG.getConstant(RoundWidth,
1273 TLI.getShiftAmountTy(Tmp3.getValueType())));
1274 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2,
1275 ST->getPointerInfo().getWithOffset(IncrementSize),
1276 ExtraVT, isVolatile, isNonTemporal,
1277 MinAlign(Alignment, IncrementSize));
1279 // Big endian - avoid unaligned stores.
1280 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
1281 // Store the top RoundWidth bits.
1282 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
1283 DAG.getConstant(ExtraWidth,
1284 TLI.getShiftAmountTy(Tmp3.getValueType())));
1285 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getPointerInfo(),
1286 RoundVT, isVolatile, isNonTemporal, Alignment);
1288 // Store the remaining ExtraWidth bits.
1289 IncrementSize = RoundWidth / 8;
1290 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1291 DAG.getIntPtrConstant(IncrementSize));
1292 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2,
1293 ST->getPointerInfo().getWithOffset(IncrementSize),
1294 ExtraVT, isVolatile, isNonTemporal,
1295 MinAlign(Alignment, IncrementSize));
1298 // The order of the stores doesn't matter.
1299 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
1300 ReplaceNode(SDValue(Node, 0), Result);
1302 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
1303 default: llvm_unreachable("This action is not supported yet!");
1304 case TargetLowering::Legal:
1305 // If this is an unaligned store and the target doesn't support it,
1307 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
1308 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
1309 unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty);
1310 if (ST->getAlignment() < ABIAlignment)
1311 ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this);
1314 case TargetLowering::Custom:
1315 Tmp1 = TLI.LowerOperation(SDValue(Node, 0), DAG);
1317 ReplaceNode(SDValue(Node, 0), Tmp1);
1319 case TargetLowering::Expand:
1320 assert(!StVT.isVector() &&
1321 "Vector Stores are handled in LegalizeVectorOps");
1323 // TRUNCSTORE:i16 i32 -> STORE i16
1324 assert(TLI.isTypeLegal(StVT) && "Do not know how to expand this store!");
1325 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3);
1327 DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
1328 isVolatile, isNonTemporal, Alignment);
1329 ReplaceNode(SDValue(Node, 0), Result);
1339 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1340 SDValue Vec = Op.getOperand(0);
1341 SDValue Idx = Op.getOperand(1);
1342 DebugLoc dl = Op.getDebugLoc();
1343 // Store the value to a temporary stack slot, then LOAD the returned part.
1344 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1345 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1346 MachinePointerInfo(), false, false, 0);
1348 // Add the offset to the index.
1350 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1351 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1352 DAG.getConstant(EltSize, Idx.getValueType()));
1354 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1355 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1357 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1359 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1361 if (Op.getValueType().isVector())
1362 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,MachinePointerInfo(),
1363 false, false, false, 0);
1364 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
1365 MachinePointerInfo(),
1366 Vec.getValueType().getVectorElementType(),
1370 SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
1371 assert(Op.getValueType().isVector() && "Non-vector insert subvector!");
1373 SDValue Vec = Op.getOperand(0);
1374 SDValue Part = Op.getOperand(1);
1375 SDValue Idx = Op.getOperand(2);
1376 DebugLoc dl = Op.getDebugLoc();
1378 // Store the value to a temporary stack slot, then LOAD the returned part.
1380 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1381 int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1382 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1384 // First store the whole vector.
1385 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo,
1388 // Then store the inserted part.
1390 // Add the offset to the index.
1392 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1394 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1395 DAG.getConstant(EltSize, Idx.getValueType()));
1397 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1398 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1400 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1402 SDValue SubStackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
1405 // Store the subvector.
1406 Ch = DAG.getStore(DAG.getEntryNode(), dl, Part, SubStackPtr,
1407 MachinePointerInfo(), false, false, 0);
1409 // Finally, load the updated vector.
1410 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo,
1411 false, false, false, 0);
1414 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1415 // We can't handle this case efficiently. Allocate a sufficiently
1416 // aligned object on the stack, store each element into it, then load
1417 // the result as a vector.
1418 // Create the stack frame object.
1419 EVT VT = Node->getValueType(0);
1420 EVT EltVT = VT.getVectorElementType();
1421 DebugLoc dl = Node->getDebugLoc();
1422 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1423 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1424 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1426 // Emit a store of each element to the stack slot.
1427 SmallVector<SDValue, 8> Stores;
1428 unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1429 // Store (in the right endianness) the elements to memory.
1430 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1431 // Ignore undef elements.
1432 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1434 unsigned Offset = TypeByteSize*i;
1436 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
1437 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1439 // If the destination vector element type is narrower than the source
1440 // element type, only store the bits necessary.
1441 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1442 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1443 Node->getOperand(i), Idx,
1444 PtrInfo.getWithOffset(Offset),
1445 EltVT, false, false, 0));
1447 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
1448 Node->getOperand(i), Idx,
1449 PtrInfo.getWithOffset(Offset),
1454 if (!Stores.empty()) // Not all undef elements?
1455 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1456 &Stores[0], Stores.size());
1458 StoreChain = DAG.getEntryNode();
1460 // Result is a load from the stack slot.
1461 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo,
1462 false, false, false, 0);
1465 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
1466 DebugLoc dl = Node->getDebugLoc();
1467 SDValue Tmp1 = Node->getOperand(0);
1468 SDValue Tmp2 = Node->getOperand(1);
1470 // Get the sign bit of the RHS. First obtain a value that has the same
1471 // sign as the sign bit, i.e. negative if and only if the sign bit is 1.
1473 EVT FloatVT = Tmp2.getValueType();
1474 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits());
1475 if (TLI.isTypeLegal(IVT)) {
1476 // Convert to an integer with the same sign bit.
1477 SignBit = DAG.getNode(ISD::BITCAST, dl, IVT, Tmp2);
1479 // Store the float to memory, then load the sign part out as an integer.
1480 MVT LoadTy = TLI.getPointerTy();
1481 // First create a temporary that is aligned for both the load and store.
1482 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1483 // Then store the float to it.
1485 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, MachinePointerInfo(),
1487 if (TLI.isBigEndian()) {
1488 assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1489 // Load out a legal integer with the same sign bit as the float.
1490 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, MachinePointerInfo(),
1491 false, false, false, 0);
1492 } else { // Little endian
1493 SDValue LoadPtr = StackPtr;
1494 // The float may be wider than the integer we are going to load. Advance
1495 // the pointer so that the loaded integer will contain the sign bit.
1496 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits();
1497 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8;
1498 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(),
1499 LoadPtr, DAG.getIntPtrConstant(ByteOffset));
1500 // Load a legal integer containing the sign bit.
1501 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(),
1502 false, false, false, 0);
1503 // Move the sign bit to the top bit of the loaded integer.
1504 unsigned BitShift = LoadTy.getSizeInBits() -
1505 (FloatVT.getSizeInBits() - 8 * ByteOffset);
1506 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?");
1508 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit,
1509 DAG.getConstant(BitShift,
1510 TLI.getShiftAmountTy(SignBit.getValueType())));
1513 // Now get the sign bit proper, by seeing whether the value is negative.
1514 SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()),
1515 SignBit, DAG.getConstant(0, SignBit.getValueType()),
1517 // Get the absolute value of the result.
1518 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1519 // Select between the nabs and abs value based on the sign bit of
1521 return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit,
1522 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1526 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1527 SmallVectorImpl<SDValue> &Results) {
1528 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1529 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1530 " not tell us which reg is the stack pointer!");
1531 DebugLoc dl = Node->getDebugLoc();
1532 EVT VT = Node->getValueType(0);
1533 SDValue Tmp1 = SDValue(Node, 0);
1534 SDValue Tmp2 = SDValue(Node, 1);
1535 SDValue Tmp3 = Node->getOperand(2);
1536 SDValue Chain = Tmp1.getOperand(0);
1538 // Chain the dynamic stack allocation so that it doesn't modify the stack
1539 // pointer when other instructions are using the stack.
1540 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1542 SDValue Size = Tmp2.getOperand(1);
1543 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1544 Chain = SP.getValue(1);
1545 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1546 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
1547 if (Align > StackAlign)
1548 SP = DAG.getNode(ISD::AND, dl, VT, SP,
1549 DAG.getConstant(-(uint64_t)Align, VT));
1550 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1551 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1553 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1554 DAG.getIntPtrConstant(0, true), SDValue());
1556 Results.push_back(Tmp1);
1557 Results.push_back(Tmp2);
1560 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
1561 /// condition code CC on the current target. This routine expands SETCC with
1562 /// illegal condition code into AND / OR of multiple SETCC values.
1563 void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1564 SDValue &LHS, SDValue &RHS,
1567 EVT OpVT = LHS.getValueType();
1568 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1569 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1570 default: llvm_unreachable("Unknown condition code action!");
1571 case TargetLowering::Legal:
1574 case TargetLowering::Expand: {
1575 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1578 default: llvm_unreachable("Don't know how to expand this condition!");
1579 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break;
1580 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1581 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1582 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1583 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1584 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1585 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1586 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1587 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1588 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1589 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1590 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1591 // FIXME: Implement more expansions.
1594 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1595 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1596 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1604 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
1605 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1606 /// a load from the stack slot to DestVT, extending it if needed.
1607 /// The resultant code need not be legal.
1608 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
1612 // Create the stack frame object.
1614 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType().
1615 getTypeForEVT(*DAG.getContext()));
1616 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1618 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1619 int SPFI = StackPtrFI->getIndex();
1620 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(SPFI);
1622 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
1623 unsigned SlotSize = SlotVT.getSizeInBits();
1624 unsigned DestSize = DestVT.getSizeInBits();
1625 Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
1626 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(DestType);
1628 // Emit a store to the stack slot. Use a truncstore if the input value is
1629 // later than DestVT.
1632 if (SrcSize > SlotSize)
1633 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1634 PtrInfo, SlotVT, false, false, SrcAlign);
1636 assert(SrcSize == SlotSize && "Invalid store");
1637 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1638 PtrInfo, false, false, SrcAlign);
1641 // Result is a load from the stack slot.
1642 if (SlotSize == DestSize)
1643 return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo,
1644 false, false, false, DestAlign);
1646 assert(SlotSize < DestSize && "Unknown extension!");
1647 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr,
1648 PtrInfo, SlotVT, false, false, DestAlign);
1651 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1652 DebugLoc dl = Node->getDebugLoc();
1653 // Create a vector sized/aligned stack slot, store the value to element #0,
1654 // then load the whole vector back out.
1655 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1657 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1658 int SPFI = StackPtrFI->getIndex();
1660 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0),
1662 MachinePointerInfo::getFixedStack(SPFI),
1663 Node->getValueType(0).getVectorElementType(),
1665 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
1666 MachinePointerInfo::getFixedStack(SPFI),
1667 false, false, false, 0);
1671 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
1672 /// support the operation, but do support the resultant vector type.
1673 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1674 unsigned NumElems = Node->getNumOperands();
1675 SDValue Value1, Value2;
1676 DebugLoc dl = Node->getDebugLoc();
1677 EVT VT = Node->getValueType(0);
1678 EVT OpVT = Node->getOperand(0).getValueType();
1679 EVT EltVT = VT.getVectorElementType();
1681 // If the only non-undef value is the low element, turn this into a
1682 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1683 bool isOnlyLowElement = true;
1684 bool MoreThanTwoValues = false;
1685 bool isConstant = true;
1686 for (unsigned i = 0; i < NumElems; ++i) {
1687 SDValue V = Node->getOperand(i);
1688 if (V.getOpcode() == ISD::UNDEF)
1691 isOnlyLowElement = false;
1692 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1695 if (!Value1.getNode()) {
1697 } else if (!Value2.getNode()) {
1700 } else if (V != Value1 && V != Value2) {
1701 MoreThanTwoValues = true;
1705 if (!Value1.getNode())
1706 return DAG.getUNDEF(VT);
1708 if (isOnlyLowElement)
1709 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1711 // If all elements are constants, create a load from the constant pool.
1713 SmallVector<Constant*, 16> CV;
1714 for (unsigned i = 0, e = NumElems; i != e; ++i) {
1715 if (ConstantFPSDNode *V =
1716 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1717 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1718 } else if (ConstantSDNode *V =
1719 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1721 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1723 // If OpVT and EltVT don't match, EltVT is not legal and the
1724 // element values have been promoted/truncated earlier. Undo this;
1725 // we don't want a v16i8 to become a v16i32 for example.
1726 const ConstantInt *CI = V->getConstantIntValue();
1727 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
1728 CI->getZExtValue()));
1731 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
1732 Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
1733 CV.push_back(UndefValue::get(OpNTy));
1736 Constant *CP = ConstantVector::get(CV);
1737 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
1738 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
1739 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
1740 MachinePointerInfo::getConstantPool(),
1741 false, false, false, Alignment);
1744 if (!MoreThanTwoValues) {
1745 SmallVector<int, 8> ShuffleVec(NumElems, -1);
1746 for (unsigned i = 0; i < NumElems; ++i) {
1747 SDValue V = Node->getOperand(i);
1748 if (V.getOpcode() == ISD::UNDEF)
1750 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
1752 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
1753 // Get the splatted value into the low element of a vector register.
1754 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
1756 if (Value2.getNode())
1757 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
1759 Vec2 = DAG.getUNDEF(VT);
1761 // Return shuffle(LowValVec, undef, <0,0,0,0>)
1762 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
1766 // Otherwise, we can't handle this case efficiently.
1767 return ExpandVectorBuildThroughStack(Node);
1770 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
1771 // does not fit into a register, return the lo part and set the hi part to the
1772 // by-reg argument. If it does fit into a single register, return the result
1773 // and leave the Hi part unset.
1774 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
1776 TargetLowering::ArgListTy Args;
1777 TargetLowering::ArgListEntry Entry;
1778 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1779 EVT ArgVT = Node->getOperand(i).getValueType();
1780 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1781 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
1782 Entry.isSExt = isSigned;
1783 Entry.isZExt = !isSigned;
1784 Args.push_back(Entry);
1786 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1787 TLI.getPointerTy());
1789 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
1791 // By default, the input chain to this libcall is the entry node of the
1792 // function. If the libcall is going to be emitted as a tail call then
1793 // TLI.isUsedByReturnOnly will change it to the right chain if the return
1794 // node which is being folded has a non-entry input chain.
1795 SDValue InChain = DAG.getEntryNode();
1797 // isTailCall may be true since the callee does not reference caller stack
1798 // frame. Check if it's in the right position.
1799 SDValue TCChain = InChain;
1800 bool isTailCall = isInTailCallPosition(DAG, Node, TCChain, TLI);
1805 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
1806 0, TLI.getLibcallCallingConv(LC), isTailCall,
1807 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
1808 Callee, Args, DAG, Node->getDebugLoc());
1809 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
1812 if (!CallInfo.second.getNode())
1813 // It's a tailcall, return the chain (which is the DAG root).
1814 return DAG.getRoot();
1816 return CallInfo.first;
1819 /// ExpandLibCall - Generate a libcall taking the given operands as arguments
1820 /// and returning a result of type RetVT.
1821 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, EVT RetVT,
1822 const SDValue *Ops, unsigned NumOps,
1823 bool isSigned, DebugLoc dl) {
1824 TargetLowering::ArgListTy Args;
1825 Args.reserve(NumOps);
1827 TargetLowering::ArgListEntry Entry;
1828 for (unsigned i = 0; i != NumOps; ++i) {
1829 Entry.Node = Ops[i];
1830 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
1831 Entry.isSExt = isSigned;
1832 Entry.isZExt = !isSigned;
1833 Args.push_back(Entry);
1835 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1836 TLI.getPointerTy());
1838 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
1840 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
1841 false, 0, TLI.getLibcallCallingConv(LC),
1842 /*isTailCall=*/false,
1843 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
1844 Callee, Args, DAG, dl);
1845 std::pair<SDValue,SDValue> CallInfo = TLI.LowerCallTo(CLI);
1847 return CallInfo.first;
1850 // ExpandChainLibCall - Expand a node into a call to a libcall. Similar to
1851 // ExpandLibCall except that the first operand is the in-chain.
1852 std::pair<SDValue, SDValue>
1853 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
1856 SDValue InChain = Node->getOperand(0);
1858 TargetLowering::ArgListTy Args;
1859 TargetLowering::ArgListEntry Entry;
1860 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) {
1861 EVT ArgVT = Node->getOperand(i).getValueType();
1862 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1863 Entry.Node = Node->getOperand(i);
1865 Entry.isSExt = isSigned;
1866 Entry.isZExt = !isSigned;
1867 Args.push_back(Entry);
1869 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1870 TLI.getPointerTy());
1872 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
1874 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
1875 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
1876 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
1877 Callee, Args, DAG, Node->getDebugLoc());
1878 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
1883 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
1884 RTLIB::Libcall Call_F32,
1885 RTLIB::Libcall Call_F64,
1886 RTLIB::Libcall Call_F80,
1887 RTLIB::Libcall Call_PPCF128) {
1889 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
1890 default: llvm_unreachable("Unexpected request for libcall!");
1891 case MVT::f32: LC = Call_F32; break;
1892 case MVT::f64: LC = Call_F64; break;
1893 case MVT::f80: LC = Call_F80; break;
1894 case MVT::ppcf128: LC = Call_PPCF128; break;
1896 return ExpandLibCall(LC, Node, false);
1899 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
1900 RTLIB::Libcall Call_I8,
1901 RTLIB::Libcall Call_I16,
1902 RTLIB::Libcall Call_I32,
1903 RTLIB::Libcall Call_I64,
1904 RTLIB::Libcall Call_I128) {
1906 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
1907 default: llvm_unreachable("Unexpected request for libcall!");
1908 case MVT::i8: LC = Call_I8; break;
1909 case MVT::i16: LC = Call_I16; break;
1910 case MVT::i32: LC = Call_I32; break;
1911 case MVT::i64: LC = Call_I64; break;
1912 case MVT::i128: LC = Call_I128; break;
1914 return ExpandLibCall(LC, Node, isSigned);
1917 /// isDivRemLibcallAvailable - Return true if divmod libcall is available.
1918 static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
1919 const TargetLowering &TLI) {
1921 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
1922 default: llvm_unreachable("Unexpected request for libcall!");
1923 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
1924 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
1925 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
1926 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
1927 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
1930 return TLI.getLibcallName(LC) != 0;
1933 /// useDivRem - Only issue divrem libcall if both quotient and remainder are
1935 static bool useDivRem(SDNode *Node, bool isSigned, bool isDIV) {
1936 // The other use might have been replaced with a divrem already.
1937 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
1938 unsigned OtherOpcode = 0;
1940 OtherOpcode = isDIV ? ISD::SREM : ISD::SDIV;
1942 OtherOpcode = isDIV ? ISD::UREM : ISD::UDIV;
1944 SDValue Op0 = Node->getOperand(0);
1945 SDValue Op1 = Node->getOperand(1);
1946 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
1947 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
1951 if ((User->getOpcode() == OtherOpcode || User->getOpcode() == DivRemOpc) &&
1952 User->getOperand(0) == Op0 &&
1953 User->getOperand(1) == Op1)
1959 /// ExpandDivRemLibCall - Issue libcalls to __{u}divmod to compute div / rem
1962 SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
1963 SmallVectorImpl<SDValue> &Results) {
1964 unsigned Opcode = Node->getOpcode();
1965 bool isSigned = Opcode == ISD::SDIVREM;
1968 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
1969 default: llvm_unreachable("Unexpected request for libcall!");
1970 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
1971 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
1972 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
1973 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
1974 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
1977 // The input chain to this libcall is the entry node of the function.
1978 // Legalizing the call will automatically add the previous call to the
1980 SDValue InChain = DAG.getEntryNode();
1982 EVT RetVT = Node->getValueType(0);
1983 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
1985 TargetLowering::ArgListTy Args;
1986 TargetLowering::ArgListEntry Entry;
1987 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1988 EVT ArgVT = Node->getOperand(i).getValueType();
1989 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1990 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
1991 Entry.isSExt = isSigned;
1992 Entry.isZExt = !isSigned;
1993 Args.push_back(Entry);
1996 // Also pass the return address of the remainder.
1997 SDValue FIPtr = DAG.CreateStackTemporary(RetVT);
1999 Entry.Ty = RetTy->getPointerTo();
2000 Entry.isSExt = isSigned;
2001 Entry.isZExt = !isSigned;
2002 Args.push_back(Entry);
2004 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2005 TLI.getPointerTy());
2007 DebugLoc dl = Node->getDebugLoc();
2009 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
2010 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
2011 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2012 Callee, Args, DAG, dl);
2013 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2015 // Remainder is loaded back from the stack frame.
2016 SDValue Rem = DAG.getLoad(RetVT, dl, CallInfo.second, FIPtr,
2017 MachinePointerInfo(), false, false, false, 0);
2018 Results.push_back(CallInfo.first);
2019 Results.push_back(Rem);
2022 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
2023 /// INT_TO_FP operation of the specified operand when the target requests that
2024 /// we expand it. At this point, we know that the result and operand types are
2025 /// legal for the target.
2026 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
2030 if (Op0.getValueType() == MVT::i32) {
2031 // simple 32-bit [signed|unsigned] integer to float/double expansion
2033 // Get the stack frame index of a 8 byte buffer.
2034 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2036 // word offset constant for Hi/Lo address computation
2037 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
2038 // set up Hi and Lo (into buffer) address based on endian
2039 SDValue Hi = StackSlot;
2040 SDValue Lo = DAG.getNode(ISD::ADD, dl,
2041 TLI.getPointerTy(), StackSlot, WordOff);
2042 if (TLI.isLittleEndian())
2045 // if signed map to unsigned space
2048 // constant used to invert sign bit (signed to unsigned mapping)
2049 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
2050 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2054 // store the lo of the constructed double - based on integer input
2055 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
2056 Op0Mapped, Lo, MachinePointerInfo(),
2058 // initial hi portion of constructed double
2059 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
2060 // store the hi of the constructed double - biased exponent
2061 SDValue Store2 = DAG.getStore(Store1, dl, InitialHi, Hi,
2062 MachinePointerInfo(),
2064 // load the constructed double
2065 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot,
2066 MachinePointerInfo(), false, false, false, 0);
2067 // FP constant to bias correct the final result
2068 SDValue Bias = DAG.getConstantFP(isSigned ?
2069 BitsToDouble(0x4330000080000000ULL) :
2070 BitsToDouble(0x4330000000000000ULL),
2072 // subtract the bias
2073 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2076 // handle final rounding
2077 if (DestVT == MVT::f64) {
2080 } else if (DestVT.bitsLT(MVT::f64)) {
2081 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2082 DAG.getIntPtrConstant(0));
2083 } else if (DestVT.bitsGT(MVT::f64)) {
2084 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2088 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2089 // Code below here assumes !isSigned without checking again.
2091 // Implementation of unsigned i64 to f64 following the algorithm in
2092 // __floatundidf in compiler_rt. This implementation has the advantage
2093 // of performing rounding correctly, both in the default rounding mode
2094 // and in all alternate rounding modes.
2095 // TODO: Generalize this for use with other types.
2096 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
2098 DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64);
2099 SDValue TwoP84PlusTwoP52 =
2100 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64);
2102 DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64);
2104 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32);
2105 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2106 DAG.getConstant(32, MVT::i64));
2107 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2108 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2109 SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr);
2110 SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr);
2111 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
2113 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
2116 // Implementation of unsigned i64 to f32.
2117 // TODO: Generalize this for use with other types.
2118 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) {
2119 // For unsigned conversions, convert them to signed conversions using the
2120 // algorithm from the x86_64 __floatundidf in compiler_rt.
2122 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0);
2124 SDValue ShiftConst =
2125 DAG.getConstant(1, TLI.getShiftAmountTy(Op0.getValueType()));
2126 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
2127 SDValue AndConst = DAG.getConstant(1, MVT::i64);
2128 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst);
2129 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr);
2131 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or);
2132 SDValue Slow = DAG.getNode(ISD::FADD, dl, MVT::f32, SignCvt, SignCvt);
2134 // TODO: This really should be implemented using a branch rather than a
2135 // select. We happen to get lucky and machinesink does the right
2136 // thing most of the time. This would be a good candidate for a
2137 //pseudo-op, or, even better, for whole-function isel.
2138 SDValue SignBitTest = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2139 Op0, DAG.getConstant(0, MVT::i64), ISD::SETLT);
2140 return DAG.getNode(ISD::SELECT, dl, MVT::f32, SignBitTest, Slow, Fast);
2143 // Otherwise, implement the fully general conversion.
2145 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2146 DAG.getConstant(UINT64_C(0xfffffffffffff800), MVT::i64));
2147 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
2148 DAG.getConstant(UINT64_C(0x800), MVT::i64));
2149 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2150 DAG.getConstant(UINT64_C(0x7ff), MVT::i64));
2151 SDValue Ne = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2152 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE);
2153 SDValue Sel = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ne, Or, Op0);
2154 SDValue Ge = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2155 Op0, DAG.getConstant(UINT64_C(0x0020000000000000), MVT::i64),
2157 SDValue Sel2 = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ge, Sel, Op0);
2158 EVT SHVT = TLI.getShiftAmountTy(Sel2.getValueType());
2160 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2161 DAG.getConstant(32, SHVT));
2162 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh);
2163 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc);
2165 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), MVT::f64);
2166 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt);
2167 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2);
2168 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo);
2169 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2);
2170 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd,
2171 DAG.getIntPtrConstant(0));
2174 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2176 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()),
2177 Op0, DAG.getConstant(0, Op0.getValueType()),
2179 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
2180 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
2181 SignSet, Four, Zero);
2183 // If the sign bit of the integer is set, the large number will be treated
2184 // as a negative number. To counteract this, the dynamic code adds an
2185 // offset depending on the data type.
2187 switch (Op0.getValueType().getSimpleVT().SimpleTy) {
2188 default: llvm_unreachable("Unsupported integer type!");
2189 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2190 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2191 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2192 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2194 if (TLI.isLittleEndian()) FF <<= 32;
2195 Constant *FudgeFactor = ConstantInt::get(
2196 Type::getInt64Ty(*DAG.getContext()), FF);
2198 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
2199 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2200 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
2201 Alignment = std::min(Alignment, 4u);
2203 if (DestVT == MVT::f32)
2204 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2205 MachinePointerInfo::getConstantPool(),
2206 false, false, false, Alignment);
2208 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
2209 DAG.getEntryNode(), CPIdx,
2210 MachinePointerInfo::getConstantPool(),
2211 MVT::f32, false, false, Alignment);
2212 HandleSDNode Handle(Load);
2213 LegalizeOp(Load.getNode());
2214 FudgeInReg = Handle.getValue();
2217 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2220 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
2221 /// *INT_TO_FP operation of the specified operand when the target requests that
2222 /// we promote it. At this point, we know that the result and operand types are
2223 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2224 /// operation that takes a larger input.
2225 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2229 // First step, figure out the appropriate *INT_TO_FP operation to use.
2230 EVT NewInTy = LegalOp.getValueType();
2232 unsigned OpToUse = 0;
2234 // Scan for the appropriate larger type to use.
2236 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2237 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2239 // If the target supports SINT_TO_FP of this type, use it.
2240 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2241 OpToUse = ISD::SINT_TO_FP;
2244 if (isSigned) continue;
2246 // If the target supports UINT_TO_FP of this type, use it.
2247 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2248 OpToUse = ISD::UINT_TO_FP;
2252 // Otherwise, try a larger type.
2255 // Okay, we found the operation and type to use. Zero extend our input to the
2256 // desired type then run the operation on it.
2257 return DAG.getNode(OpToUse, dl, DestVT,
2258 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2259 dl, NewInTy, LegalOp));
2262 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
2263 /// FP_TO_*INT operation of the specified operand when the target requests that
2264 /// we promote it. At this point, we know that the result and operand types are
2265 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2266 /// operation that returns a larger result.
2267 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2271 // First step, figure out the appropriate FP_TO*INT operation to use.
2272 EVT NewOutTy = DestVT;
2274 unsigned OpToUse = 0;
2276 // Scan for the appropriate larger type to use.
2278 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2279 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2281 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2282 OpToUse = ISD::FP_TO_SINT;
2286 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2287 OpToUse = ISD::FP_TO_UINT;
2291 // Otherwise, try a larger type.
2295 // Okay, we found the operation and type to use.
2296 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2298 // Truncate the result of the extended FP_TO_*INT operation to the desired
2300 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2303 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
2305 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) {
2306 EVT VT = Op.getValueType();
2307 EVT SHVT = TLI.getShiftAmountTy(VT);
2308 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2309 switch (VT.getSimpleVT().SimpleTy) {
2310 default: llvm_unreachable("Unhandled Expand type in BSWAP!");
2312 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2313 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2314 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2316 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2317 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2318 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2319 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2320 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
2321 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
2322 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2323 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2324 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2326 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
2327 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
2328 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2329 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2330 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2331 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2332 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
2333 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
2334 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
2335 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
2336 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
2337 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
2338 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
2339 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
2340 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2341 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2342 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2343 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2344 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2345 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2346 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2350 /// SplatByte - Distribute ByteVal over NumBits bits.
2351 // FIXME: Move this helper to a common place.
2352 static APInt SplatByte(unsigned NumBits, uint8_t ByteVal) {
2353 APInt Val = APInt(NumBits, ByteVal);
2355 for (unsigned i = NumBits; i > 8; i >>= 1) {
2356 Val = (Val << Shift) | Val;
2362 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
2364 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2367 default: llvm_unreachable("Cannot expand this yet!");
2369 EVT VT = Op.getValueType();
2370 EVT ShVT = TLI.getShiftAmountTy(VT);
2371 unsigned Len = VT.getSizeInBits();
2373 assert(VT.isInteger() && Len <= 128 && Len % 8 == 0 &&
2374 "CTPOP not implemented for this type.");
2376 // This is the "best" algorithm from
2377 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
2379 SDValue Mask55 = DAG.getConstant(SplatByte(Len, 0x55), VT);
2380 SDValue Mask33 = DAG.getConstant(SplatByte(Len, 0x33), VT);
2381 SDValue Mask0F = DAG.getConstant(SplatByte(Len, 0x0F), VT);
2382 SDValue Mask01 = DAG.getConstant(SplatByte(Len, 0x01), VT);
2384 // v = v - ((v >> 1) & 0x55555555...)
2385 Op = DAG.getNode(ISD::SUB, dl, VT, Op,
2386 DAG.getNode(ISD::AND, dl, VT,
2387 DAG.getNode(ISD::SRL, dl, VT, Op,
2388 DAG.getConstant(1, ShVT)),
2390 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
2391 Op = DAG.getNode(ISD::ADD, dl, VT,
2392 DAG.getNode(ISD::AND, dl, VT, Op, Mask33),
2393 DAG.getNode(ISD::AND, dl, VT,
2394 DAG.getNode(ISD::SRL, dl, VT, Op,
2395 DAG.getConstant(2, ShVT)),
2397 // v = (v + (v >> 4)) & 0x0F0F0F0F...
2398 Op = DAG.getNode(ISD::AND, dl, VT,
2399 DAG.getNode(ISD::ADD, dl, VT, Op,
2400 DAG.getNode(ISD::SRL, dl, VT, Op,
2401 DAG.getConstant(4, ShVT))),
2403 // v = (v * 0x01010101...) >> (Len - 8)
2404 Op = DAG.getNode(ISD::SRL, dl, VT,
2405 DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
2406 DAG.getConstant(Len - 8, ShVT));
2410 case ISD::CTLZ_ZERO_UNDEF:
2411 // This trivially expands to CTLZ.
2412 return DAG.getNode(ISD::CTLZ, dl, Op.getValueType(), Op);
2414 // for now, we do this:
2415 // x = x | (x >> 1);
2416 // x = x | (x >> 2);
2418 // x = x | (x >>16);
2419 // x = x | (x >>32); // for 64-bit input
2420 // return popcount(~x);
2422 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
2423 EVT VT = Op.getValueType();
2424 EVT ShVT = TLI.getShiftAmountTy(VT);
2425 unsigned len = VT.getSizeInBits();
2426 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2427 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2428 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2429 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2431 Op = DAG.getNOT(dl, Op, VT);
2432 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2434 case ISD::CTTZ_ZERO_UNDEF:
2435 // This trivially expands to CTTZ.
2436 return DAG.getNode(ISD::CTTZ, dl, Op.getValueType(), Op);
2438 // for now, we use: { return popcount(~x & (x - 1)); }
2439 // unless the target has ctlz but not ctpop, in which case we use:
2440 // { return 32 - nlz(~x & (x-1)); }
2441 // see also http://www.hackersdelight.org/HDcode/ntz.cc
2442 EVT VT = Op.getValueType();
2443 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2444 DAG.getNOT(dl, Op, VT),
2445 DAG.getNode(ISD::SUB, dl, VT, Op,
2446 DAG.getConstant(1, VT)));
2447 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2448 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2449 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2450 return DAG.getNode(ISD::SUB, dl, VT,
2451 DAG.getConstant(VT.getSizeInBits(), VT),
2452 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2453 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2458 std::pair <SDValue, SDValue> SelectionDAGLegalize::ExpandAtomic(SDNode *Node) {
2459 unsigned Opc = Node->getOpcode();
2460 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
2465 llvm_unreachable("Unhandled atomic intrinsic Expand!");
2466 case ISD::ATOMIC_SWAP:
2467 switch (VT.SimpleTy) {
2468 default: llvm_unreachable("Unexpected value type for atomic!");
2469 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break;
2470 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
2471 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
2472 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
2475 case ISD::ATOMIC_CMP_SWAP:
2476 switch (VT.SimpleTy) {
2477 default: llvm_unreachable("Unexpected value type for atomic!");
2478 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break;
2479 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;
2480 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;
2481 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
2484 case ISD::ATOMIC_LOAD_ADD:
2485 switch (VT.SimpleTy) {
2486 default: llvm_unreachable("Unexpected value type for atomic!");
2487 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break;
2488 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;
2489 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;
2490 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
2493 case ISD::ATOMIC_LOAD_SUB:
2494 switch (VT.SimpleTy) {
2495 default: llvm_unreachable("Unexpected value type for atomic!");
2496 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break;
2497 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;
2498 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;
2499 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
2502 case ISD::ATOMIC_LOAD_AND:
2503 switch (VT.SimpleTy) {
2504 default: llvm_unreachable("Unexpected value type for atomic!");
2505 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break;
2506 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;
2507 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;
2508 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
2511 case ISD::ATOMIC_LOAD_OR:
2512 switch (VT.SimpleTy) {
2513 default: llvm_unreachable("Unexpected value type for atomic!");
2514 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break;
2515 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;
2516 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;
2517 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
2520 case ISD::ATOMIC_LOAD_XOR:
2521 switch (VT.SimpleTy) {
2522 default: llvm_unreachable("Unexpected value type for atomic!");
2523 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break;
2524 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;
2525 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;
2526 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
2529 case ISD::ATOMIC_LOAD_NAND:
2530 switch (VT.SimpleTy) {
2531 default: llvm_unreachable("Unexpected value type for atomic!");
2532 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break;
2533 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;
2534 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;
2535 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
2540 return ExpandChainLibCall(LC, Node, false);
2543 void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
2544 SmallVector<SDValue, 8> Results;
2545 DebugLoc dl = Node->getDebugLoc();
2546 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2547 switch (Node->getOpcode()) {
2550 case ISD::CTLZ_ZERO_UNDEF:
2552 case ISD::CTTZ_ZERO_UNDEF:
2553 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
2554 Results.push_back(Tmp1);
2557 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2559 case ISD::FRAMEADDR:
2560 case ISD::RETURNADDR:
2561 case ISD::FRAME_TO_ARGS_OFFSET:
2562 Results.push_back(DAG.getConstant(0, Node->getValueType(0)));
2564 case ISD::FLT_ROUNDS_:
2565 Results.push_back(DAG.getConstant(1, Node->getValueType(0)));
2567 case ISD::EH_RETURN:
2571 case ISD::EH_SJLJ_LONGJMP:
2572 // If the target didn't expand these, there's nothing to do, so just
2573 // preserve the chain and be done.
2574 Results.push_back(Node->getOperand(0));
2576 case ISD::EH_SJLJ_SETJMP:
2577 // If the target didn't expand this, just return 'zero' and preserve the
2579 Results.push_back(DAG.getConstant(0, MVT::i32));
2580 Results.push_back(Node->getOperand(0));
2582 case ISD::ATOMIC_FENCE:
2583 case ISD::MEMBARRIER: {
2584 // If the target didn't lower this, lower it to '__sync_synchronize()' call
2585 // FIXME: handle "fence singlethread" more efficiently.
2586 TargetLowering::ArgListTy Args;
2588 CallLoweringInfo CLI(Node->getOperand(0),
2589 Type::getVoidTy(*DAG.getContext()),
2590 false, false, false, false, 0, CallingConv::C,
2591 /*isTailCall=*/false,
2592 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2593 DAG.getExternalSymbol("__sync_synchronize",
2594 TLI.getPointerTy()),
2596 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
2598 Results.push_back(CallResult.second);
2601 case ISD::ATOMIC_LOAD: {
2602 // There is no libcall for atomic load; fake it with ATOMIC_CMP_SWAP.
2603 SDValue Zero = DAG.getConstant(0, Node->getValueType(0));
2604 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl,
2605 cast<AtomicSDNode>(Node)->getMemoryVT(),
2606 Node->getOperand(0),
2607 Node->getOperand(1), Zero, Zero,
2608 cast<AtomicSDNode>(Node)->getMemOperand(),
2609 cast<AtomicSDNode>(Node)->getOrdering(),
2610 cast<AtomicSDNode>(Node)->getSynchScope());
2611 Results.push_back(Swap.getValue(0));
2612 Results.push_back(Swap.getValue(1));
2615 case ISD::ATOMIC_STORE: {
2616 // There is no libcall for atomic store; fake it with ATOMIC_SWAP.
2617 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
2618 cast<AtomicSDNode>(Node)->getMemoryVT(),
2619 Node->getOperand(0),
2620 Node->getOperand(1), Node->getOperand(2),
2621 cast<AtomicSDNode>(Node)->getMemOperand(),
2622 cast<AtomicSDNode>(Node)->getOrdering(),
2623 cast<AtomicSDNode>(Node)->getSynchScope());
2624 Results.push_back(Swap.getValue(1));
2627 // By default, atomic intrinsics are marked Legal and lowered. Targets
2628 // which don't support them directly, however, may want libcalls, in which
2629 // case they mark them Expand, and we get here.
2630 case ISD::ATOMIC_SWAP:
2631 case ISD::ATOMIC_LOAD_ADD:
2632 case ISD::ATOMIC_LOAD_SUB:
2633 case ISD::ATOMIC_LOAD_AND:
2634 case ISD::ATOMIC_LOAD_OR:
2635 case ISD::ATOMIC_LOAD_XOR:
2636 case ISD::ATOMIC_LOAD_NAND:
2637 case ISD::ATOMIC_LOAD_MIN:
2638 case ISD::ATOMIC_LOAD_MAX:
2639 case ISD::ATOMIC_LOAD_UMIN:
2640 case ISD::ATOMIC_LOAD_UMAX:
2641 case ISD::ATOMIC_CMP_SWAP: {
2642 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node);
2643 Results.push_back(Tmp.first);
2644 Results.push_back(Tmp.second);
2647 case ISD::DYNAMIC_STACKALLOC:
2648 ExpandDYNAMIC_STACKALLOC(Node, Results);
2650 case ISD::MERGE_VALUES:
2651 for (unsigned i = 0; i < Node->getNumValues(); i++)
2652 Results.push_back(Node->getOperand(i));
2655 EVT VT = Node->getValueType(0);
2657 Results.push_back(DAG.getConstant(0, VT));
2659 assert(VT.isFloatingPoint() && "Unknown value type!");
2660 Results.push_back(DAG.getConstantFP(0, VT));
2665 // If this operation is not supported, lower it to 'abort()' call
2666 TargetLowering::ArgListTy Args;
2668 CallLoweringInfo CLI(Node->getOperand(0),
2669 Type::getVoidTy(*DAG.getContext()),
2670 false, false, false, false, 0, CallingConv::C,
2671 /*isTailCall=*/false,
2672 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2673 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
2675 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
2677 Results.push_back(CallResult.second);
2682 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
2683 Node->getValueType(0), dl);
2684 Results.push_back(Tmp1);
2686 case ISD::FP_EXTEND:
2687 Tmp1 = EmitStackConvert(Node->getOperand(0),
2688 Node->getOperand(0).getValueType(),
2689 Node->getValueType(0), dl);
2690 Results.push_back(Tmp1);
2692 case ISD::SIGN_EXTEND_INREG: {
2693 // NOTE: we could fall back on load/store here too for targets without
2694 // SAR. However, it is doubtful that any exist.
2695 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2696 EVT VT = Node->getValueType(0);
2697 EVT ShiftAmountTy = TLI.getShiftAmountTy(VT);
2700 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
2701 ExtraVT.getScalarType().getSizeInBits();
2702 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy);
2703 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
2704 Node->getOperand(0), ShiftCst);
2705 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
2706 Results.push_back(Tmp1);
2709 case ISD::FP_ROUND_INREG: {
2710 // The only way we can lower this is to turn it into a TRUNCSTORE,
2711 // EXTLOAD pair, targeting a temporary location (a stack slot).
2713 // NOTE: there is a choice here between constantly creating new stack
2714 // slots and always reusing the same one. We currently always create
2715 // new ones, as reuse may inhibit scheduling.
2716 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2717 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
2718 Node->getValueType(0), dl);
2719 Results.push_back(Tmp1);
2722 case ISD::SINT_TO_FP:
2723 case ISD::UINT_TO_FP:
2724 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
2725 Node->getOperand(0), Node->getValueType(0), dl);
2726 Results.push_back(Tmp1);
2728 case ISD::FP_TO_UINT: {
2729 SDValue True, False;
2730 EVT VT = Node->getOperand(0).getValueType();
2731 EVT NVT = Node->getValueType(0);
2732 APFloat apf(APInt::getNullValue(VT.getSizeInBits()));
2733 APInt x = APInt::getSignBit(NVT.getSizeInBits());
2734 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
2735 Tmp1 = DAG.getConstantFP(apf, VT);
2736 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
2737 Node->getOperand(0),
2739 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
2740 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
2741 DAG.getNode(ISD::FSUB, dl, VT,
2742 Node->getOperand(0), Tmp1));
2743 False = DAG.getNode(ISD::XOR, dl, NVT, False,
2744 DAG.getConstant(x, NVT));
2745 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False);
2746 Results.push_back(Tmp1);
2750 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2751 EVT VT = Node->getValueType(0);
2752 Tmp1 = Node->getOperand(0);
2753 Tmp2 = Node->getOperand(1);
2754 unsigned Align = Node->getConstantOperandVal(3);
2756 SDValue VAListLoad = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2,
2757 MachinePointerInfo(V),
2758 false, false, false, 0);
2759 SDValue VAList = VAListLoad;
2761 if (Align > TLI.getMinStackArgumentAlignment()) {
2762 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
2764 VAList = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
2765 DAG.getConstant(Align - 1,
2766 TLI.getPointerTy()));
2768 VAList = DAG.getNode(ISD::AND, dl, TLI.getPointerTy(), VAList,
2769 DAG.getConstant(-(int64_t)Align,
2770 TLI.getPointerTy()));
2773 // Increment the pointer, VAList, to the next vaarg
2774 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
2775 DAG.getConstant(TLI.getTargetData()->
2776 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())),
2777 TLI.getPointerTy()));
2778 // Store the incremented VAList to the legalized pointer
2779 Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2,
2780 MachinePointerInfo(V), false, false, 0);
2781 // Load the actual argument out of the pointer VAList
2782 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(),
2783 false, false, false, 0));
2784 Results.push_back(Results[0].getValue(1));
2788 // This defaults to loading a pointer from the input and storing it to the
2789 // output, returning the chain.
2790 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
2791 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
2792 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0),
2793 Node->getOperand(2), MachinePointerInfo(VS),
2794 false, false, false, 0);
2795 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1),
2796 MachinePointerInfo(VD), false, false, 0);
2797 Results.push_back(Tmp1);
2800 case ISD::EXTRACT_VECTOR_ELT:
2801 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
2802 // This must be an access of the only element. Return it.
2803 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
2804 Node->getOperand(0));
2806 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
2807 Results.push_back(Tmp1);
2809 case ISD::EXTRACT_SUBVECTOR:
2810 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
2812 case ISD::INSERT_SUBVECTOR:
2813 Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0)));
2815 case ISD::CONCAT_VECTORS: {
2816 Results.push_back(ExpandVectorBuildThroughStack(Node));
2819 case ISD::SCALAR_TO_VECTOR:
2820 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
2822 case ISD::INSERT_VECTOR_ELT:
2823 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
2824 Node->getOperand(1),
2825 Node->getOperand(2), dl));
2827 case ISD::VECTOR_SHUFFLE: {
2828 SmallVector<int, 32> NewMask;
2829 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
2831 EVT VT = Node->getValueType(0);
2832 EVT EltVT = VT.getVectorElementType();
2833 SDValue Op0 = Node->getOperand(0);
2834 SDValue Op1 = Node->getOperand(1);
2835 if (!TLI.isTypeLegal(EltVT)) {
2837 EVT NewEltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
2839 // BUILD_VECTOR operands are allowed to be wider than the element type.
2840 // But if NewEltVT is smaller that EltVT the BUILD_VECTOR does not accept it
2841 if (NewEltVT.bitsLT(EltVT)) {
2843 // Convert shuffle node.
2844 // If original node was v4i64 and the new EltVT is i32,
2845 // cast operands to v8i32 and re-build the mask.
2847 // Calculate new VT, the size of the new VT should be equal to original.
2848 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), NewEltVT,
2849 VT.getSizeInBits()/NewEltVT.getSizeInBits());
2850 assert(NewVT.bitsEq(VT));
2852 // cast operands to new VT
2853 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0);
2854 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1);
2856 // Convert the shuffle mask
2857 unsigned int factor = NewVT.getVectorNumElements()/VT.getVectorNumElements();
2859 // EltVT gets smaller
2862 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
2864 for (unsigned fi = 0; fi < factor; ++fi)
2865 NewMask.push_back(Mask[i]);
2868 for (unsigned fi = 0; fi < factor; ++fi)
2869 NewMask.push_back(Mask[i]*factor+fi);
2877 unsigned NumElems = VT.getVectorNumElements();
2878 SmallVector<SDValue, 16> Ops;
2879 for (unsigned i = 0; i != NumElems; ++i) {
2881 Ops.push_back(DAG.getUNDEF(EltVT));
2884 unsigned Idx = Mask[i];
2886 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
2888 DAG.getIntPtrConstant(Idx)));
2890 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
2892 DAG.getIntPtrConstant(Idx - NumElems)));
2895 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
2896 // We may have changed the BUILD_VECTOR type. Cast it back to the Node type.
2897 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), Tmp1);
2898 Results.push_back(Tmp1);
2901 case ISD::EXTRACT_ELEMENT: {
2902 EVT OpTy = Node->getOperand(0).getValueType();
2903 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
2905 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
2906 DAG.getConstant(OpTy.getSizeInBits()/2,
2907 TLI.getShiftAmountTy(Node->getOperand(0).getValueType())));
2908 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
2911 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
2912 Node->getOperand(0));
2914 Results.push_back(Tmp1);
2917 case ISD::STACKSAVE:
2918 // Expand to CopyFromReg if the target set
2919 // StackPointerRegisterToSaveRestore.
2920 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2921 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
2922 Node->getValueType(0)));
2923 Results.push_back(Results[0].getValue(1));
2925 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
2926 Results.push_back(Node->getOperand(0));
2929 case ISD::STACKRESTORE:
2930 // Expand to CopyToReg if the target set
2931 // StackPointerRegisterToSaveRestore.
2932 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2933 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
2934 Node->getOperand(1)));
2936 Results.push_back(Node->getOperand(0));
2939 case ISD::FCOPYSIGN:
2940 Results.push_back(ExpandFCOPYSIGN(Node));
2943 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2944 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2945 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
2946 Node->getOperand(0));
2947 Results.push_back(Tmp1);
2950 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2951 EVT VT = Node->getValueType(0);
2952 Tmp1 = Node->getOperand(0);
2953 Tmp2 = DAG.getConstantFP(0.0, VT);
2954 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
2955 Tmp1, Tmp2, ISD::SETUGT);
2956 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
2957 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3);
2958 Results.push_back(Tmp1);
2962 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
2963 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128));
2966 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
2967 RTLIB::SIN_F80, RTLIB::SIN_PPCF128));
2970 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
2971 RTLIB::COS_F80, RTLIB::COS_PPCF128));
2974 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
2975 RTLIB::LOG_F80, RTLIB::LOG_PPCF128));
2978 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
2979 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128));
2982 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
2983 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128));
2986 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
2987 RTLIB::EXP_F80, RTLIB::EXP_PPCF128));
2990 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
2991 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128));
2994 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
2995 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128));
2998 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
2999 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128));
3002 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3003 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128));
3006 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
3007 RTLIB::RINT_F80, RTLIB::RINT_PPCF128));
3009 case ISD::FNEARBYINT:
3010 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
3011 RTLIB::NEARBYINT_F64,
3012 RTLIB::NEARBYINT_F80,
3013 RTLIB::NEARBYINT_PPCF128));
3016 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
3017 RTLIB::POWI_F80, RTLIB::POWI_PPCF128));
3020 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
3021 RTLIB::POW_F80, RTLIB::POW_PPCF128));
3024 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
3025 RTLIB::DIV_F80, RTLIB::DIV_PPCF128));
3028 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
3029 RTLIB::REM_F80, RTLIB::REM_PPCF128));
3032 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMA_F32, RTLIB::FMA_F64,
3033 RTLIB::FMA_F80, RTLIB::FMA_PPCF128));
3035 case ISD::FP16_TO_FP32:
3036 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
3038 case ISD::FP32_TO_FP16:
3039 Results.push_back(ExpandLibCall(RTLIB::FPROUND_F32_F16, Node, false));
3041 case ISD::ConstantFP: {
3042 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
3043 // Check to see if this FP immediate is already legal.
3044 // If this is a legal constant, turn it into a TargetConstantFP node.
3045 if (!TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
3046 Results.push_back(ExpandConstantFP(CFP, true));
3049 case ISD::EHSELECTION: {
3050 unsigned Reg = TLI.getExceptionSelectorRegister();
3051 assert(Reg && "Can't expand to unknown register!");
3052 Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg,
3053 Node->getValueType(0)));
3054 Results.push_back(Results[0].getValue(1));
3057 case ISD::EXCEPTIONADDR: {
3058 unsigned Reg = TLI.getExceptionPointerRegister();
3059 assert(Reg && "Can't expand to unknown register!");
3060 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg,
3061 Node->getValueType(0)));
3062 Results.push_back(Results[0].getValue(1));
3066 EVT VT = Node->getValueType(0);
3067 assert(TLI.isOperationLegalOrCustom(ISD::FADD, VT) &&
3068 TLI.isOperationLegalOrCustom(ISD::FNEG, VT) &&
3069 "Don't know how to expand this FP subtraction!");
3070 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1));
3071 Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1);
3072 Results.push_back(Tmp1);
3076 EVT VT = Node->getValueType(0);
3077 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3078 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3079 "Don't know how to expand this subtraction!");
3080 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3081 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
3082 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, VT));
3083 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3088 EVT VT = Node->getValueType(0);
3089 SDVTList VTs = DAG.getVTList(VT, VT);
3090 bool isSigned = Node->getOpcode() == ISD::SREM;
3091 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3092 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3093 Tmp2 = Node->getOperand(0);
3094 Tmp3 = Node->getOperand(1);
3095 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3096 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3097 useDivRem(Node, isSigned, false))) {
3098 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
3099 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
3101 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
3102 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3103 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3104 } else if (isSigned)
3105 Tmp1 = ExpandIntLibCall(Node, true,
3107 RTLIB::SREM_I16, RTLIB::SREM_I32,
3108 RTLIB::SREM_I64, RTLIB::SREM_I128);
3110 Tmp1 = ExpandIntLibCall(Node, false,
3112 RTLIB::UREM_I16, RTLIB::UREM_I32,
3113 RTLIB::UREM_I64, RTLIB::UREM_I128);
3114 Results.push_back(Tmp1);
3119 bool isSigned = Node->getOpcode() == ISD::SDIV;
3120 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3121 EVT VT = Node->getValueType(0);
3122 SDVTList VTs = DAG.getVTList(VT, VT);
3123 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3124 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3125 useDivRem(Node, isSigned, true)))
3126 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
3127 Node->getOperand(1));
3129 Tmp1 = ExpandIntLibCall(Node, true,
3131 RTLIB::SDIV_I16, RTLIB::SDIV_I32,
3132 RTLIB::SDIV_I64, RTLIB::SDIV_I128);
3134 Tmp1 = ExpandIntLibCall(Node, false,
3136 RTLIB::UDIV_I16, RTLIB::UDIV_I32,
3137 RTLIB::UDIV_I64, RTLIB::UDIV_I128);
3138 Results.push_back(Tmp1);
3143 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
3145 EVT VT = Node->getValueType(0);
3146 SDVTList VTs = DAG.getVTList(VT, VT);
3147 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
3148 "If this wasn't legal, it shouldn't have been created!");
3149 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
3150 Node->getOperand(1));
3151 Results.push_back(Tmp1.getValue(1));
3156 // Expand into divrem libcall
3157 ExpandDivRemLibCall(Node, Results);
3160 EVT VT = Node->getValueType(0);
3161 SDVTList VTs = DAG.getVTList(VT, VT);
3162 // See if multiply or divide can be lowered using two-result operations.
3163 // We just need the low half of the multiply; try both the signed
3164 // and unsigned forms. If the target supports both SMUL_LOHI and
3165 // UMUL_LOHI, form a preference by checking which forms of plain
3166 // MULH it supports.
3167 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3168 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3169 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3170 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3171 unsigned OpToUse = 0;
3172 if (HasSMUL_LOHI && !HasMULHS) {
3173 OpToUse = ISD::SMUL_LOHI;
3174 } else if (HasUMUL_LOHI && !HasMULHU) {
3175 OpToUse = ISD::UMUL_LOHI;
3176 } else if (HasSMUL_LOHI) {
3177 OpToUse = ISD::SMUL_LOHI;
3178 } else if (HasUMUL_LOHI) {
3179 OpToUse = ISD::UMUL_LOHI;
3182 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
3183 Node->getOperand(1)));
3186 Tmp1 = ExpandIntLibCall(Node, false,
3188 RTLIB::MUL_I16, RTLIB::MUL_I32,
3189 RTLIB::MUL_I64, RTLIB::MUL_I128);
3190 Results.push_back(Tmp1);
3195 SDValue LHS = Node->getOperand(0);
3196 SDValue RHS = Node->getOperand(1);
3197 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3198 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3200 Results.push_back(Sum);
3201 EVT OType = Node->getValueType(1);
3203 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
3205 // LHSSign -> LHS >= 0
3206 // RHSSign -> RHS >= 0
3207 // SumSign -> Sum >= 0
3210 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3212 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3214 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3215 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3216 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
3217 Node->getOpcode() == ISD::SADDO ?
3218 ISD::SETEQ : ISD::SETNE);
3220 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3221 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3223 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3224 Results.push_back(Cmp);
3229 SDValue LHS = Node->getOperand(0);
3230 SDValue RHS = Node->getOperand(1);
3231 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
3232 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3234 Results.push_back(Sum);
3235 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS,
3236 Node->getOpcode () == ISD::UADDO ?
3237 ISD::SETULT : ISD::SETUGT));
3242 EVT VT = Node->getValueType(0);
3243 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
3244 SDValue LHS = Node->getOperand(0);
3245 SDValue RHS = Node->getOperand(1);
3248 static const unsigned Ops[2][3] =
3249 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
3250 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
3251 bool isSigned = Node->getOpcode() == ISD::SMULO;
3252 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3253 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3254 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3255 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3256 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3258 TopHalf = BottomHalf.getValue(1);
3259 } else if (TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(),
3260 VT.getSizeInBits() * 2))) {
3261 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
3262 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
3263 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
3264 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3265 DAG.getIntPtrConstant(0));
3266 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3267 DAG.getIntPtrConstant(1));
3269 // We can fall back to a libcall with an illegal type for the MUL if we
3270 // have a libcall big enough.
3271 // Also, we can fall back to a division in some cases, but that's a big
3272 // performance hit in the general case.
3273 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3274 if (WideVT == MVT::i16)
3275 LC = RTLIB::MUL_I16;
3276 else if (WideVT == MVT::i32)
3277 LC = RTLIB::MUL_I32;
3278 else if (WideVT == MVT::i64)
3279 LC = RTLIB::MUL_I64;
3280 else if (WideVT == MVT::i128)
3281 LC = RTLIB::MUL_I128;
3282 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!");
3284 // The high part is obtained by SRA'ing all but one of the bits of low
3286 unsigned LoSize = VT.getSizeInBits();
3287 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, RHS,
3288 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
3289 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, VT, LHS,
3290 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
3292 // Here we're passing the 2 arguments explicitly as 4 arguments that are
3293 // pre-lowered to the correct types. This all depends upon WideVT not
3294 // being a legal type for the architecture and thus has to be split to
3296 SDValue Args[] = { LHS, HiLHS, RHS, HiRHS };
3297 SDValue Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl);
3298 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3299 DAG.getIntPtrConstant(0));
3300 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3301 DAG.getIntPtrConstant(1));
3302 // Ret is a node with an illegal type. Because such things are not
3303 // generally permitted during this phase of legalization, delete the
3304 // node. The above EXTRACT_ELEMENT nodes should have been folded.
3305 DAG.DeleteNode(Ret.getNode());
3309 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1,
3310 TLI.getShiftAmountTy(BottomHalf.getValueType()));
3311 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3312 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1,
3315 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf,
3316 DAG.getConstant(0, VT), ISD::SETNE);
3318 Results.push_back(BottomHalf);
3319 Results.push_back(TopHalf);
3322 case ISD::BUILD_PAIR: {
3323 EVT PairTy = Node->getValueType(0);
3324 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3325 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3326 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
3327 DAG.getConstant(PairTy.getSizeInBits()/2,
3328 TLI.getShiftAmountTy(PairTy)));
3329 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3333 Tmp1 = Node->getOperand(0);
3334 Tmp2 = Node->getOperand(1);
3335 Tmp3 = Node->getOperand(2);
3336 if (Tmp1.getOpcode() == ISD::SETCC) {
3337 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3339 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3341 Tmp1 = DAG.getSelectCC(dl, Tmp1,
3342 DAG.getConstant(0, Tmp1.getValueType()),
3343 Tmp2, Tmp3, ISD::SETNE);
3345 Results.push_back(Tmp1);
3348 SDValue Chain = Node->getOperand(0);
3349 SDValue Table = Node->getOperand(1);
3350 SDValue Index = Node->getOperand(2);
3352 EVT PTy = TLI.getPointerTy();
3354 const TargetData &TD = *TLI.getTargetData();
3355 unsigned EntrySize =
3356 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
3358 Index = DAG.getNode(ISD::MUL, dl, PTy,
3359 Index, DAG.getConstant(EntrySize, PTy));
3360 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
3362 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
3363 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
3364 MachinePointerInfo::getJumpTable(), MemVT,
3367 if (TM.getRelocationModel() == Reloc::PIC_) {
3368 // For PIC, the sequence is:
3369 // BRIND(load(Jumptable + index) + RelocBase)
3370 // RelocBase can be JumpTable, GOT or some sort of global base.
3371 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3372 TLI.getPICJumpTableRelocBase(Table, DAG));
3374 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
3375 Results.push_back(Tmp1);
3379 // Expand brcond's setcc into its constituent parts and create a BR_CC
3381 Tmp1 = Node->getOperand(0);
3382 Tmp2 = Node->getOperand(1);
3383 if (Tmp2.getOpcode() == ISD::SETCC) {
3384 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3385 Tmp1, Tmp2.getOperand(2),
3386 Tmp2.getOperand(0), Tmp2.getOperand(1),
3387 Node->getOperand(2));
3389 // We test only the i1 bit. Skip the AND if UNDEF.
3390 Tmp3 = (Tmp2.getOpcode() == ISD::UNDEF) ? Tmp2 :
3391 DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2,
3392 DAG.getConstant(1, Tmp2.getValueType()));
3393 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3394 DAG.getCondCode(ISD::SETNE), Tmp3,
3395 DAG.getConstant(0, Tmp3.getValueType()),
3396 Node->getOperand(2));
3398 Results.push_back(Tmp1);
3401 Tmp1 = Node->getOperand(0);
3402 Tmp2 = Node->getOperand(1);
3403 Tmp3 = Node->getOperand(2);
3404 LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl);
3406 // If we expanded the SETCC into an AND/OR, return the new node
3407 if (Tmp2.getNode() == 0) {
3408 Results.push_back(Tmp1);
3412 // Otherwise, SETCC for the given comparison type must be completely
3413 // illegal; expand it into a SELECT_CC.
3414 EVT VT = Node->getValueType(0);
3415 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3416 DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3);
3417 Results.push_back(Tmp1);
3420 case ISD::SELECT_CC: {
3421 Tmp1 = Node->getOperand(0); // LHS
3422 Tmp2 = Node->getOperand(1); // RHS
3423 Tmp3 = Node->getOperand(2); // True
3424 Tmp4 = Node->getOperand(3); // False
3425 SDValue CC = Node->getOperand(4);
3427 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()),
3428 Tmp1, Tmp2, CC, dl);
3430 assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!");
3431 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3432 CC = DAG.getCondCode(ISD::SETNE);
3433 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2,
3435 Results.push_back(Tmp1);
3439 Tmp1 = Node->getOperand(0); // Chain
3440 Tmp2 = Node->getOperand(2); // LHS
3441 Tmp3 = Node->getOperand(3); // RHS
3442 Tmp4 = Node->getOperand(1); // CC
3444 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()),
3445 Tmp2, Tmp3, Tmp4, dl);
3447 assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!");
3448 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
3449 Tmp4 = DAG.getCondCode(ISD::SETNE);
3450 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2,
3451 Tmp3, Node->getOperand(4));
3452 Results.push_back(Tmp1);
3455 case ISD::BUILD_VECTOR:
3456 Results.push_back(ExpandBUILD_VECTOR(Node));
3461 // Scalarize vector SRA/SRL/SHL.
3462 EVT VT = Node->getValueType(0);
3463 assert(VT.isVector() && "Unable to legalize non-vector shift");
3464 assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
3465 unsigned NumElem = VT.getVectorNumElements();
3467 SmallVector<SDValue, 8> Scalars;
3468 for (unsigned Idx = 0; Idx < NumElem; Idx++) {
3469 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3471 Node->getOperand(0), DAG.getIntPtrConstant(Idx));
3472 SDValue Sh = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3474 Node->getOperand(1), DAG.getIntPtrConstant(Idx));
3475 Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
3476 VT.getScalarType(), Ex, Sh));
3479 DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0),
3480 &Scalars[0], Scalars.size());
3481 ReplaceNode(SDValue(Node, 0), Result);
3484 case ISD::GLOBAL_OFFSET_TABLE:
3485 case ISD::GlobalAddress:
3486 case ISD::GlobalTLSAddress:
3487 case ISD::ExternalSymbol:
3488 case ISD::ConstantPool:
3489 case ISD::JumpTable:
3490 case ISD::INTRINSIC_W_CHAIN:
3491 case ISD::INTRINSIC_WO_CHAIN:
3492 case ISD::INTRINSIC_VOID:
3493 // FIXME: Custom lowering for these operations shouldn't return null!
3497 // Replace the original node with the legalized result.
3498 if (!Results.empty())
3499 ReplaceNode(Node, Results.data());
3502 void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
3503 SmallVector<SDValue, 8> Results;
3504 EVT OVT = Node->getValueType(0);
3505 if (Node->getOpcode() == ISD::UINT_TO_FP ||
3506 Node->getOpcode() == ISD::SINT_TO_FP ||
3507 Node->getOpcode() == ISD::SETCC) {
3508 OVT = Node->getOperand(0).getValueType();
3510 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3511 DebugLoc dl = Node->getDebugLoc();
3512 SDValue Tmp1, Tmp2, Tmp3;
3513 switch (Node->getOpcode()) {
3515 case ISD::CTTZ_ZERO_UNDEF:
3517 case ISD::CTLZ_ZERO_UNDEF:
3519 // Zero extend the argument.
3520 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3521 // Perform the larger operation. For CTPOP and CTTZ_ZERO_UNDEF, this is
3522 // already the correct result.
3523 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
3524 if (Node->getOpcode() == ISD::CTTZ) {
3525 // FIXME: This should set a bit in the zero extended value instead.
3526 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
3527 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
3529 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
3530 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3531 } else if (Node->getOpcode() == ISD::CTLZ ||
3532 Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) {
3533 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3534 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
3535 DAG.getConstant(NVT.getSizeInBits() -
3536 OVT.getSizeInBits(), NVT));
3538 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
3541 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3542 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3543 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
3544 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
3545 DAG.getConstant(DiffBits, TLI.getShiftAmountTy(NVT)));
3546 Results.push_back(Tmp1);
3549 case ISD::FP_TO_UINT:
3550 case ISD::FP_TO_SINT:
3551 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
3552 Node->getOpcode() == ISD::FP_TO_SINT, dl);
3553 Results.push_back(Tmp1);
3555 case ISD::UINT_TO_FP:
3556 case ISD::SINT_TO_FP:
3557 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
3558 Node->getOpcode() == ISD::SINT_TO_FP, dl);
3559 Results.push_back(Tmp1);
3562 SDValue Chain = Node->getOperand(0); // Get the chain.
3563 SDValue Ptr = Node->getOperand(1); // Get the pointer.
3566 if (OVT.isVector()) {
3567 TruncOp = ISD::BITCAST;
3569 assert(OVT.isInteger()
3570 && "VAARG promotion is supported only for vectors or integer types");
3571 TruncOp = ISD::TRUNCATE;
3574 // Perform the larger operation, then convert back
3575 Tmp1 = DAG.getVAArg(NVT, dl, Chain, Ptr, Node->getOperand(2),
3576 Node->getConstantOperandVal(3));
3577 Chain = Tmp1.getValue(1);
3579 Tmp2 = DAG.getNode(TruncOp, dl, OVT, Tmp1);
3581 // Modified the chain result - switch anything that used the old chain to
3583 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp2);
3584 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
3591 unsigned ExtOp, TruncOp;
3592 if (OVT.isVector()) {
3593 ExtOp = ISD::BITCAST;
3594 TruncOp = ISD::BITCAST;
3596 assert(OVT.isInteger() && "Cannot promote logic operation");
3597 ExtOp = ISD::ANY_EXTEND;
3598 TruncOp = ISD::TRUNCATE;
3600 // Promote each of the values to the new type.
3601 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3602 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3603 // Perform the larger operation, then convert back
3604 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3605 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
3609 unsigned ExtOp, TruncOp;
3610 if (Node->getValueType(0).isVector()) {
3611 ExtOp = ISD::BITCAST;
3612 TruncOp = ISD::BITCAST;
3613 } else if (Node->getValueType(0).isInteger()) {
3614 ExtOp = ISD::ANY_EXTEND;
3615 TruncOp = ISD::TRUNCATE;
3617 ExtOp = ISD::FP_EXTEND;
3618 TruncOp = ISD::FP_ROUND;
3620 Tmp1 = Node->getOperand(0);
3621 // Promote each of the values to the new type.
3622 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3623 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
3624 // Perform the larger operation, then round down.
3625 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3);
3626 if (TruncOp != ISD::FP_ROUND)
3627 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
3629 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
3630 DAG.getIntPtrConstant(0));
3631 Results.push_back(Tmp1);
3634 case ISD::VECTOR_SHUFFLE: {
3635 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
3637 // Cast the two input vectors.
3638 Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
3639 Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
3641 // Convert the shuffle mask to the right # elements.
3642 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
3643 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
3644 Results.push_back(Tmp1);
3648 unsigned ExtOp = ISD::FP_EXTEND;
3649 if (NVT.isInteger()) {
3650 ISD::CondCode CCCode =
3651 cast<CondCodeSDNode>(Node->getOperand(2))->get();
3652 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3654 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3655 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3656 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3657 Tmp1, Tmp2, Node->getOperand(2)));
3663 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
3664 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
3665 Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3666 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
3667 Tmp3, DAG.getIntPtrConstant(0)));
3674 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
3675 Tmp2 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
3676 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
3677 Tmp2, DAG.getIntPtrConstant(0)));
3682 // Replace the original node with the legalized result.
3683 if (!Results.empty())
3684 ReplaceNode(Node, Results.data());
3687 // SelectionDAG::Legalize - This is the entry point for the file.
3689 void SelectionDAG::Legalize() {
3690 /// run - This is the main entry point to this class.
3692 SelectionDAGLegalize(*this).LegalizeDAG();