1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/ADT/SmallPtrSet.h"
16 #include "llvm/ADT/SmallSet.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/CodeGen/Analysis.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineJumpTableInfo.h"
22 #include "llvm/IR/CallingConv.h"
23 #include "llvm/IR/Constants.h"
24 #include "llvm/IR/DataLayout.h"
25 #include "llvm/IR/DebugInfo.h"
26 #include "llvm/IR/DerivedTypes.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/LLVMContext.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/Target/TargetFrameLowering.h"
34 #include "llvm/Target/TargetLowering.h"
35 #include "llvm/Target/TargetMachine.h"
38 //===----------------------------------------------------------------------===//
39 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
40 /// hacks on it until the target machine can handle it. This involves
41 /// eliminating value sizes the machine cannot handle (promoting small sizes to
42 /// large sizes or splitting up large values into small values) as well as
43 /// eliminating operations the machine cannot handle.
45 /// This code also does a small amount of optimization and recognition of idioms
46 /// as part of its processing. For example, if a target does not support a
47 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
48 /// will attempt merge setcc and brc instructions into brcc's.
51 class SelectionDAGLegalize : public SelectionDAG::DAGUpdateListener {
52 const TargetMachine &TM;
53 const TargetLowering &TLI;
56 /// LegalizePosition - The iterator for walking through the node list.
57 SelectionDAG::allnodes_iterator LegalizePosition;
59 /// LegalizedNodes - The set of nodes which have already been legalized.
60 SmallPtrSet<SDNode *, 16> LegalizedNodes;
62 EVT getSetCCResultType(EVT VT) const {
63 return TLI.getSetCCResultType(*DAG.getContext(), VT);
66 // Libcall insertion helpers.
69 explicit SelectionDAGLegalize(SelectionDAG &DAG);
74 /// LegalizeOp - Legalizes the given operation.
75 void LegalizeOp(SDNode *Node);
77 SDValue OptimizeFloatStore(StoreSDNode *ST);
79 void LegalizeLoadOps(SDNode *Node);
80 void LegalizeStoreOps(SDNode *Node);
82 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
83 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
84 /// is necessary to spill the vector being inserted into to memory, perform
85 /// the insert there, and then read the result back.
86 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
87 SDValue Idx, SDLoc dl);
88 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
89 SDValue Idx, SDLoc dl);
91 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
92 /// performs the same shuffe in terms of order or result bytes, but on a type
93 /// whose vector element type is narrower than the original shuffle type.
94 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
95 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl,
96 SDValue N1, SDValue N2,
97 ArrayRef<int> Mask) const;
99 bool LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
100 bool &NeedInvert, SDLoc dl);
102 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
103 SDValue ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops,
104 unsigned NumOps, bool isSigned, SDLoc dl);
106 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
107 SDNode *Node, bool isSigned);
108 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
109 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
110 RTLIB::Libcall Call_F128,
111 RTLIB::Libcall Call_PPCF128);
112 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
113 RTLIB::Libcall Call_I8,
114 RTLIB::Libcall Call_I16,
115 RTLIB::Libcall Call_I32,
116 RTLIB::Libcall Call_I64,
117 RTLIB::Libcall Call_I128);
118 void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
119 void ExpandSinCosLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
121 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, SDLoc dl);
122 SDValue ExpandBUILD_VECTOR(SDNode *Node);
123 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
124 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
125 SmallVectorImpl<SDValue> &Results);
126 SDValue ExpandFCOPYSIGN(SDNode *Node);
127 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
129 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
131 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
134 SDValue ExpandBSWAP(SDValue Op, SDLoc dl);
135 SDValue ExpandBitCount(unsigned Opc, SDValue Op, SDLoc dl);
137 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
138 SDValue ExpandInsertToVectorThroughStack(SDValue Op);
139 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
141 SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP);
143 std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node);
145 void ExpandNode(SDNode *Node);
146 void PromoteNode(SDNode *Node);
148 void ForgetNode(SDNode *N) {
149 LegalizedNodes.erase(N);
150 if (LegalizePosition == SelectionDAG::allnodes_iterator(N))
155 // DAGUpdateListener implementation.
156 void NodeDeleted(SDNode *N, SDNode *E) override {
159 void NodeUpdated(SDNode *N) override {}
161 // Node replacement helpers
162 void ReplacedNode(SDNode *N) {
163 if (N->use_empty()) {
164 DAG.RemoveDeadNode(N);
169 void ReplaceNode(SDNode *Old, SDNode *New) {
170 DAG.ReplaceAllUsesWith(Old, New);
173 void ReplaceNode(SDValue Old, SDValue New) {
174 DAG.ReplaceAllUsesWith(Old, New);
175 ReplacedNode(Old.getNode());
177 void ReplaceNode(SDNode *Old, const SDValue *New) {
178 DAG.ReplaceAllUsesWith(Old, New);
184 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
185 /// performs the same shuffe in terms of order or result bytes, but on a type
186 /// whose vector element type is narrower than the original shuffle type.
187 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
189 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl,
190 SDValue N1, SDValue N2,
191 ArrayRef<int> Mask) const {
192 unsigned NumMaskElts = VT.getVectorNumElements();
193 unsigned NumDestElts = NVT.getVectorNumElements();
194 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
196 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
198 if (NumEltsGrowth == 1)
199 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
201 SmallVector<int, 8> NewMask;
202 for (unsigned i = 0; i != NumMaskElts; ++i) {
204 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
206 NewMask.push_back(-1);
208 NewMask.push_back(Idx * NumEltsGrowth + j);
211 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
212 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
213 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
216 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
217 : SelectionDAG::DAGUpdateListener(dag),
218 TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()),
222 void SelectionDAGLegalize::LegalizeDAG() {
223 DAG.AssignTopologicalOrder();
225 // Visit all the nodes. We start in topological order, so that we see
226 // nodes with their original operands intact. Legalization can produce
227 // new nodes which may themselves need to be legalized. Iterate until all
228 // nodes have been legalized.
230 bool AnyLegalized = false;
231 for (LegalizePosition = DAG.allnodes_end();
232 LegalizePosition != DAG.allnodes_begin(); ) {
235 SDNode *N = LegalizePosition;
236 if (LegalizedNodes.insert(N)) {
246 // Remove dead nodes now.
247 DAG.RemoveDeadNodes();
250 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
251 /// a load from the constant pool.
253 SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) {
257 // If a FP immediate is precise when represented as a float and if the
258 // target can do an extending load from float to double, we put it into
259 // the constant pool as a float, even if it's is statically typed as a
260 // double. This shrinks FP constants and canonicalizes them for targets where
261 // an FP extending load is the same cost as a normal load (such as on the x87
262 // fp stack or PPC FP unit).
263 EVT VT = CFP->getValueType(0);
264 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
266 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
267 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
268 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
273 while (SVT != MVT::f32) {
274 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
275 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) &&
276 // Only do this if the target has a native EXTLOAD instruction from
278 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
279 TLI.ShouldShrinkFPConstant(OrigVT)) {
280 Type *SType = SVT.getTypeForEVT(*DAG.getContext());
281 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
287 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
288 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
291 DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT,
293 CPIdx, MachinePointerInfo::getConstantPool(),
294 VT, false, false, Alignment);
298 DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
299 MachinePointerInfo::getConstantPool(), false, false, false,
304 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
305 static void ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
306 const TargetLowering &TLI,
307 SelectionDAGLegalize *DAGLegalize) {
308 assert(ST->getAddressingMode() == ISD::UNINDEXED &&
309 "unaligned indexed stores not implemented!");
310 SDValue Chain = ST->getChain();
311 SDValue Ptr = ST->getBasePtr();
312 SDValue Val = ST->getValue();
313 EVT VT = Val.getValueType();
314 int Alignment = ST->getAlignment();
315 unsigned AS = ST->getAddressSpace();
318 if (ST->getMemoryVT().isFloatingPoint() ||
319 ST->getMemoryVT().isVector()) {
320 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
321 if (TLI.isTypeLegal(intVT)) {
322 // Expand to a bitconvert of the value to the integer type of the
323 // same size, then a (misaligned) int store.
324 // FIXME: Does not handle truncating floating point stores!
325 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
326 Result = DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
327 ST->isVolatile(), ST->isNonTemporal(), Alignment);
328 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
331 // Do a (aligned) store to a stack slot, then copy from the stack slot
332 // to the final destination using (unaligned) integer loads and stores.
333 EVT StoredVT = ST->getMemoryVT();
335 TLI.getRegisterType(*DAG.getContext(),
336 EVT::getIntegerVT(*DAG.getContext(),
337 StoredVT.getSizeInBits()));
338 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
339 unsigned RegBytes = RegVT.getSizeInBits() / 8;
340 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
342 // Make sure the stack slot is also aligned for the register type.
343 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
345 // Perform the original store, only redirected to the stack slot.
346 SDValue Store = DAG.getTruncStore(Chain, dl,
347 Val, StackPtr, MachinePointerInfo(),
348 StoredVT, false, false, 0);
349 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy(AS));
350 SmallVector<SDValue, 8> Stores;
353 // Do all but one copies using the full register width.
354 for (unsigned i = 1; i < NumRegs; i++) {
355 // Load one integer register's worth from the stack slot.
356 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr,
357 MachinePointerInfo(),
358 false, false, false, 0);
359 // Store it to the final location. Remember the store.
360 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
361 ST->getPointerInfo().getWithOffset(Offset),
362 ST->isVolatile(), ST->isNonTemporal(),
363 MinAlign(ST->getAlignment(), Offset)));
364 // Increment the pointers.
366 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
368 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
371 // The last store may be partial. Do a truncating store. On big-endian
372 // machines this requires an extending load from the stack slot to ensure
373 // that the bits are in the right place.
374 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
375 8 * (StoredBytes - Offset));
377 // Load from the stack slot.
378 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
379 MachinePointerInfo(),
380 MemVT, false, false, 0);
382 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
384 .getWithOffset(Offset),
385 MemVT, ST->isVolatile(),
387 MinAlign(ST->getAlignment(), Offset),
389 // The order of the stores doesn't matter - say it with a TokenFactor.
391 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
393 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
396 assert(ST->getMemoryVT().isInteger() &&
397 !ST->getMemoryVT().isVector() &&
398 "Unaligned store of unknown type.");
399 // Get the half-size VT
400 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext());
401 int NumBits = NewStoredVT.getSizeInBits();
402 int IncrementSize = NumBits / 8;
404 // Divide the stored value in two parts.
405 SDValue ShiftAmount = DAG.getConstant(NumBits,
406 TLI.getShiftAmountTy(Val.getValueType()));
408 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
410 // Store the two parts
411 SDValue Store1, Store2;
412 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
413 ST->getPointerInfo(), NewStoredVT,
414 ST->isVolatile(), ST->isNonTemporal(), Alignment);
416 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
417 DAG.getConstant(IncrementSize, TLI.getPointerTy(AS)));
418 Alignment = MinAlign(Alignment, IncrementSize);
419 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
420 ST->getPointerInfo().getWithOffset(IncrementSize),
421 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(),
422 Alignment, ST->getTBAAInfo());
425 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
426 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
429 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
431 ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
432 const TargetLowering &TLI,
433 SDValue &ValResult, SDValue &ChainResult) {
434 assert(LD->getAddressingMode() == ISD::UNINDEXED &&
435 "unaligned indexed loads not implemented!");
436 SDValue Chain = LD->getChain();
437 SDValue Ptr = LD->getBasePtr();
438 EVT VT = LD->getValueType(0);
439 EVT LoadedVT = LD->getMemoryVT();
441 if (VT.isFloatingPoint() || VT.isVector()) {
442 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
443 if (TLI.isTypeLegal(intVT) && TLI.isTypeLegal(LoadedVT)) {
444 // Expand to a (misaligned) integer load of the same size,
445 // then bitconvert to floating point or vector.
446 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr,
447 LD->getMemOperand());
448 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad);
450 Result = DAG.getNode(VT.isFloatingPoint() ? ISD::FP_EXTEND :
451 ISD::ANY_EXTEND, dl, VT, Result);
458 // Copy the value to a (aligned) stack slot using (unaligned) integer
459 // loads and stores, then do a (aligned) load from the stack slot.
460 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
461 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
462 unsigned RegBytes = RegVT.getSizeInBits() / 8;
463 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
465 // Make sure the stack slot is also aligned for the register type.
466 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
468 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
469 SmallVector<SDValue, 8> Stores;
470 SDValue StackPtr = StackBase;
473 // Do all but one copies using the full register width.
474 for (unsigned i = 1; i < NumRegs; i++) {
475 // Load one integer register's worth from the original location.
476 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr,
477 LD->getPointerInfo().getWithOffset(Offset),
478 LD->isVolatile(), LD->isNonTemporal(),
480 MinAlign(LD->getAlignment(), Offset),
482 // Follow the load with a store to the stack slot. Remember the store.
483 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
484 MachinePointerInfo(), false, false, 0));
485 // Increment the pointers.
487 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
488 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
492 // The last copy may be partial. Do an extending load.
493 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
494 8 * (LoadedBytes - Offset));
495 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
496 LD->getPointerInfo().getWithOffset(Offset),
497 MemVT, LD->isVolatile(),
499 MinAlign(LD->getAlignment(), Offset),
501 // Follow the load with a store to the stack slot. Remember the store.
502 // On big-endian machines this requires a truncating store to ensure
503 // that the bits end up in the right place.
504 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
505 MachinePointerInfo(), MemVT,
508 // The order of the stores doesn't matter - say it with a TokenFactor.
509 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
512 // Finally, perform the original load only redirected to the stack slot.
513 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
514 MachinePointerInfo(), LoadedVT, false, false, 0);
516 // Callers expect a MERGE_VALUES node.
521 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
522 "Unaligned load of unsupported type.");
524 // Compute the new VT that is half the size of the old one. This is an
526 unsigned NumBits = LoadedVT.getSizeInBits();
528 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
531 unsigned Alignment = LD->getAlignment();
532 unsigned IncrementSize = NumBits / 8;
533 ISD::LoadExtType HiExtType = LD->getExtensionType();
535 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
536 if (HiExtType == ISD::NON_EXTLOAD)
537 HiExtType = ISD::ZEXTLOAD;
539 // Load the value in two parts
541 if (TLI.isLittleEndian()) {
542 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
543 NewLoadedVT, LD->isVolatile(),
544 LD->isNonTemporal(), Alignment, LD->getTBAAInfo());
545 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
546 DAG.getConstant(IncrementSize, Ptr.getValueType()));
547 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr,
548 LD->getPointerInfo().getWithOffset(IncrementSize),
549 NewLoadedVT, LD->isVolatile(),
550 LD->isNonTemporal(), MinAlign(Alignment, IncrementSize),
553 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(),
554 NewLoadedVT, LD->isVolatile(),
555 LD->isNonTemporal(), Alignment, LD->getTBAAInfo());
556 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
557 DAG.getConstant(IncrementSize, Ptr.getValueType()));
558 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
559 LD->getPointerInfo().getWithOffset(IncrementSize),
560 NewLoadedVT, LD->isVolatile(),
561 LD->isNonTemporal(), MinAlign(Alignment, IncrementSize),
565 // aggregate the two parts
566 SDValue ShiftAmount = DAG.getConstant(NumBits,
567 TLI.getShiftAmountTy(Hi.getValueType()));
568 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
569 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
571 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
578 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
579 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
580 /// is necessary to spill the vector being inserted into to memory, perform
581 /// the insert there, and then read the result back.
582 SDValue SelectionDAGLegalize::
583 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
589 // If the target doesn't support this, we have to spill the input vector
590 // to a temporary stack slot, update the element, then reload it. This is
591 // badness. We could also load the value into a vector register (either
592 // with a "move to register" or "extload into register" instruction, then
593 // permute it into place, if the idx is a constant and if the idx is
594 // supported by the target.
595 EVT VT = Tmp1.getValueType();
596 EVT EltVT = VT.getVectorElementType();
597 EVT IdxVT = Tmp3.getValueType();
598 EVT PtrVT = TLI.getPointerTy();
599 SDValue StackPtr = DAG.CreateStackTemporary(VT);
601 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
604 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
605 MachinePointerInfo::getFixedStack(SPFI),
608 // Truncate or zero extend offset to target pointer type.
609 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
610 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
611 // Add the offset to the index.
612 unsigned EltSize = EltVT.getSizeInBits()/8;
613 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
614 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
615 // Store the scalar value.
616 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT,
618 // Load the updated vector.
619 return DAG.getLoad(VT, dl, Ch, StackPtr,
620 MachinePointerInfo::getFixedStack(SPFI), false, false,
625 SDValue SelectionDAGLegalize::
626 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, SDLoc dl) {
627 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
628 // SCALAR_TO_VECTOR requires that the type of the value being inserted
629 // match the element type of the vector being created, except for
630 // integers in which case the inserted value can be over width.
631 EVT EltVT = Vec.getValueType().getVectorElementType();
632 if (Val.getValueType() == EltVT ||
633 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
634 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
635 Vec.getValueType(), Val);
637 unsigned NumElts = Vec.getValueType().getVectorNumElements();
638 // We generate a shuffle of InVec and ScVec, so the shuffle mask
639 // should be 0,1,2,3,4,5... with the appropriate element replaced with
641 SmallVector<int, 8> ShufOps;
642 for (unsigned i = 0; i != NumElts; ++i)
643 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
645 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
649 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
652 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
653 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
654 // FIXME: We shouldn't do this for TargetConstantFP's.
655 // FIXME: move this to the DAG Combiner! Note that we can't regress due
656 // to phase ordering between legalized code and the dag combiner. This
657 // probably means that we need to integrate dag combiner and legalizer
659 // We generally can't do this one for long doubles.
660 SDValue Chain = ST->getChain();
661 SDValue Ptr = ST->getBasePtr();
662 unsigned Alignment = ST->getAlignment();
663 bool isVolatile = ST->isVolatile();
664 bool isNonTemporal = ST->isNonTemporal();
665 const MDNode *TBAAInfo = ST->getTBAAInfo();
667 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
668 if (CFP->getValueType(0) == MVT::f32 &&
669 TLI.isTypeLegal(MVT::i32)) {
670 SDValue Con = DAG.getConstant(CFP->getValueAPF().
671 bitcastToAPInt().zextOrTrunc(32),
673 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
674 isVolatile, isNonTemporal, Alignment, TBAAInfo);
677 if (CFP->getValueType(0) == MVT::f64) {
678 // If this target supports 64-bit registers, do a single 64-bit store.
679 if (TLI.isTypeLegal(MVT::i64)) {
680 SDValue Con = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
681 zextOrTrunc(64), MVT::i64);
682 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
683 isVolatile, isNonTemporal, Alignment, TBAAInfo);
686 if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) {
687 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
688 // stores. If the target supports neither 32- nor 64-bits, this
689 // xform is certainly not worth it.
690 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
691 SDValue Lo = DAG.getConstant(IntVal.trunc(32), MVT::i32);
692 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
693 if (TLI.isBigEndian()) std::swap(Lo, Hi);
695 Lo = DAG.getStore(Chain, dl, Lo, Ptr, ST->getPointerInfo(), isVolatile,
696 isNonTemporal, Alignment, TBAAInfo);
697 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
698 DAG.getConstant(4, Ptr.getValueType()));
699 Hi = DAG.getStore(Chain, dl, Hi, Ptr,
700 ST->getPointerInfo().getWithOffset(4),
701 isVolatile, isNonTemporal, MinAlign(Alignment, 4U),
704 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
708 return SDValue(0, 0);
711 void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
712 StoreSDNode *ST = cast<StoreSDNode>(Node);
713 SDValue Chain = ST->getChain();
714 SDValue Ptr = ST->getBasePtr();
717 unsigned Alignment = ST->getAlignment();
718 bool isVolatile = ST->isVolatile();
719 bool isNonTemporal = ST->isNonTemporal();
720 const MDNode *TBAAInfo = ST->getTBAAInfo();
722 if (!ST->isTruncatingStore()) {
723 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
724 ReplaceNode(ST, OptStore);
729 SDValue Value = ST->getValue();
730 MVT VT = Value.getSimpleValueType();
731 switch (TLI.getOperationAction(ISD::STORE, VT)) {
732 default: llvm_unreachable("This action is not supported yet!");
733 case TargetLowering::Legal: {
734 // If this is an unaligned store and the target doesn't support it,
736 unsigned AS = ST->getAddressSpace();
737 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT(), AS)) {
738 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
739 unsigned ABIAlignment= TLI.getDataLayout()->getABITypeAlignment(Ty);
740 if (ST->getAlignment() < ABIAlignment)
741 ExpandUnalignedStore(cast<StoreSDNode>(Node),
746 case TargetLowering::Custom: {
747 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
749 ReplaceNode(SDValue(Node, 0), Res);
752 case TargetLowering::Promote: {
753 MVT NVT = TLI.getTypeToPromoteTo(ISD::STORE, VT);
754 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
755 "Can only promote stores to same size type");
756 Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value);
758 DAG.getStore(Chain, dl, Value, Ptr,
759 ST->getPointerInfo(), isVolatile,
760 isNonTemporal, Alignment, TBAAInfo);
761 ReplaceNode(SDValue(Node, 0), Result);
768 SDValue Value = ST->getValue();
770 EVT StVT = ST->getMemoryVT();
771 unsigned StWidth = StVT.getSizeInBits();
773 if (StWidth != StVT.getStoreSizeInBits()) {
774 // Promote to a byte-sized store with upper bits zero if not
775 // storing an integral number of bytes. For example, promote
776 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
777 EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
778 StVT.getStoreSizeInBits());
779 Value = DAG.getZeroExtendInReg(Value, dl, StVT);
781 DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
782 NVT, isVolatile, isNonTemporal, Alignment,
784 ReplaceNode(SDValue(Node, 0), Result);
785 } else if (StWidth & (StWidth - 1)) {
786 // If not storing a power-of-2 number of bits, expand as two stores.
787 assert(!StVT.isVector() && "Unsupported truncstore!");
788 unsigned RoundWidth = 1 << Log2_32(StWidth);
789 assert(RoundWidth < StWidth);
790 unsigned ExtraWidth = StWidth - RoundWidth;
791 assert(ExtraWidth < RoundWidth);
792 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
793 "Store size not an integral number of bytes!");
794 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
795 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
797 unsigned IncrementSize;
799 if (TLI.isLittleEndian()) {
800 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
801 // Store the bottom RoundWidth bits.
802 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
804 isVolatile, isNonTemporal, Alignment,
807 // Store the remaining ExtraWidth bits.
808 IncrementSize = RoundWidth / 8;
809 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
810 DAG.getConstant(IncrementSize, Ptr.getValueType()));
811 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
812 DAG.getConstant(RoundWidth,
813 TLI.getShiftAmountTy(Value.getValueType())));
814 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr,
815 ST->getPointerInfo().getWithOffset(IncrementSize),
816 ExtraVT, isVolatile, isNonTemporal,
817 MinAlign(Alignment, IncrementSize), TBAAInfo);
819 // Big endian - avoid unaligned stores.
820 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
821 // Store the top RoundWidth bits.
822 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
823 DAG.getConstant(ExtraWidth,
824 TLI.getShiftAmountTy(Value.getValueType())));
825 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, ST->getPointerInfo(),
826 RoundVT, isVolatile, isNonTemporal, Alignment,
829 // Store the remaining ExtraWidth bits.
830 IncrementSize = RoundWidth / 8;
831 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
832 DAG.getConstant(IncrementSize, Ptr.getValueType()));
833 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr,
834 ST->getPointerInfo().getWithOffset(IncrementSize),
835 ExtraVT, isVolatile, isNonTemporal,
836 MinAlign(Alignment, IncrementSize), TBAAInfo);
839 // The order of the stores doesn't matter.
840 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
841 ReplaceNode(SDValue(Node, 0), Result);
843 switch (TLI.getTruncStoreAction(ST->getValue().getSimpleValueType(),
844 StVT.getSimpleVT())) {
845 default: llvm_unreachable("This action is not supported yet!");
846 case TargetLowering::Legal: {
847 unsigned AS = ST->getAddressSpace();
848 // If this is an unaligned store and the target doesn't support it,
850 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT(), AS)) {
851 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
852 unsigned ABIAlignment= TLI.getDataLayout()->getABITypeAlignment(Ty);
853 if (ST->getAlignment() < ABIAlignment)
854 ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this);
858 case TargetLowering::Custom: {
859 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
861 ReplaceNode(SDValue(Node, 0), Res);
864 case TargetLowering::Expand:
865 assert(!StVT.isVector() &&
866 "Vector Stores are handled in LegalizeVectorOps");
868 // TRUNCSTORE:i16 i32 -> STORE i16
869 assert(TLI.isTypeLegal(StVT) &&
870 "Do not know how to expand this store!");
871 Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value);
873 DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
874 isVolatile, isNonTemporal, Alignment, TBAAInfo);
875 ReplaceNode(SDValue(Node, 0), Result);
882 void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
883 LoadSDNode *LD = cast<LoadSDNode>(Node);
884 SDValue Chain = LD->getChain(); // The chain.
885 SDValue Ptr = LD->getBasePtr(); // The base pointer.
886 SDValue Value; // The value returned by the load op.
889 ISD::LoadExtType ExtType = LD->getExtensionType();
890 if (ExtType == ISD::NON_EXTLOAD) {
891 MVT VT = Node->getSimpleValueType(0);
892 SDValue RVal = SDValue(Node, 0);
893 SDValue RChain = SDValue(Node, 1);
895 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
896 default: llvm_unreachable("This action is not supported yet!");
897 case TargetLowering::Legal: {
898 unsigned AS = LD->getAddressSpace();
899 // If this is an unaligned load and the target doesn't support it,
901 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT(), AS)) {
902 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
903 unsigned ABIAlignment =
904 TLI.getDataLayout()->getABITypeAlignment(Ty);
905 if (LD->getAlignment() < ABIAlignment){
906 ExpandUnalignedLoad(cast<LoadSDNode>(Node), DAG, TLI, RVal, RChain);
911 case TargetLowering::Custom: {
912 SDValue Res = TLI.LowerOperation(RVal, DAG);
915 RChain = Res.getValue(1);
919 case TargetLowering::Promote: {
920 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
921 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
922 "Can only promote loads to same size type");
924 SDValue Res = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getMemOperand());
925 RVal = DAG.getNode(ISD::BITCAST, dl, VT, Res);
926 RChain = Res.getValue(1);
930 if (RChain.getNode() != Node) {
931 assert(RVal.getNode() != Node && "Load must be completely replaced");
932 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), RVal);
933 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), RChain);
939 EVT SrcVT = LD->getMemoryVT();
940 unsigned SrcWidth = SrcVT.getSizeInBits();
941 unsigned Alignment = LD->getAlignment();
942 bool isVolatile = LD->isVolatile();
943 bool isNonTemporal = LD->isNonTemporal();
944 const MDNode *TBAAInfo = LD->getTBAAInfo();
946 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
947 // Some targets pretend to have an i1 loading operation, and actually
948 // load an i8. This trick is correct for ZEXTLOAD because the top 7
949 // bits are guaranteed to be zero; it helps the optimizers understand
950 // that these bits are zero. It is also useful for EXTLOAD, since it
951 // tells the optimizers that those bits are undefined. It would be
952 // nice to have an effective generic way of getting these benefits...
953 // Until such a way is found, don't insist on promoting i1 here.
955 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
956 // Promote to a byte-sized load if not loading an integral number of
957 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
958 unsigned NewWidth = SrcVT.getStoreSizeInBits();
959 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
962 // The extra bits are guaranteed to be zero, since we stored them that
963 // way. A zext load from NVT thus automatically gives zext from SrcVT.
965 ISD::LoadExtType NewExtType =
966 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
969 DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
970 Chain, Ptr, LD->getPointerInfo(),
971 NVT, isVolatile, isNonTemporal, Alignment, TBAAInfo);
973 Ch = Result.getValue(1); // The chain.
975 if (ExtType == ISD::SEXTLOAD)
976 // Having the top bits zero doesn't help when sign extending.
977 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
978 Result.getValueType(),
979 Result, DAG.getValueType(SrcVT));
980 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
981 // All the top bits are guaranteed to be zero - inform the optimizers.
982 Result = DAG.getNode(ISD::AssertZext, dl,
983 Result.getValueType(), Result,
984 DAG.getValueType(SrcVT));
988 } else if (SrcWidth & (SrcWidth - 1)) {
989 // If not loading a power-of-2 number of bits, expand as two loads.
990 assert(!SrcVT.isVector() && "Unsupported extload!");
991 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
992 assert(RoundWidth < SrcWidth);
993 unsigned ExtraWidth = SrcWidth - RoundWidth;
994 assert(ExtraWidth < RoundWidth);
995 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
996 "Load size not an integral number of bytes!");
997 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
998 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
1000 unsigned IncrementSize;
1002 if (TLI.isLittleEndian()) {
1003 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1004 // Load the bottom RoundWidth bits.
1005 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0),
1007 LD->getPointerInfo(), RoundVT, isVolatile,
1008 isNonTemporal, Alignment, TBAAInfo);
1010 // Load the remaining ExtraWidth bits.
1011 IncrementSize = RoundWidth / 8;
1012 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1013 DAG.getConstant(IncrementSize, Ptr.getValueType()));
1014 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
1015 LD->getPointerInfo().getWithOffset(IncrementSize),
1016 ExtraVT, isVolatile, isNonTemporal,
1017 MinAlign(Alignment, IncrementSize), TBAAInfo);
1019 // Build a factor node to remember that this load is independent of
1021 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1024 // Move the top bits to the right place.
1025 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1026 DAG.getConstant(RoundWidth,
1027 TLI.getShiftAmountTy(Hi.getValueType())));
1029 // Join the hi and lo parts.
1030 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1032 // Big endian - avoid unaligned loads.
1033 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1034 // Load the top RoundWidth bits.
1035 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
1036 LD->getPointerInfo(), RoundVT, isVolatile,
1037 isNonTemporal, Alignment, TBAAInfo);
1039 // Load the remaining ExtraWidth bits.
1040 IncrementSize = RoundWidth / 8;
1041 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1042 DAG.getConstant(IncrementSize, Ptr.getValueType()));
1043 Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
1044 dl, Node->getValueType(0), Chain, Ptr,
1045 LD->getPointerInfo().getWithOffset(IncrementSize),
1046 ExtraVT, isVolatile, isNonTemporal,
1047 MinAlign(Alignment, IncrementSize), TBAAInfo);
1049 // Build a factor node to remember that this load is independent of
1051 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1054 // Move the top bits to the right place.
1055 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1056 DAG.getConstant(ExtraWidth,
1057 TLI.getShiftAmountTy(Hi.getValueType())));
1059 // Join the hi and lo parts.
1060 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1065 bool isCustom = false;
1066 switch (TLI.getLoadExtAction(ExtType, SrcVT.getSimpleVT())) {
1067 default: llvm_unreachable("This action is not supported yet!");
1068 case TargetLowering::Custom:
1071 case TargetLowering::Legal: {
1072 Value = SDValue(Node, 0);
1073 Chain = SDValue(Node, 1);
1076 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1077 if (Res.getNode()) {
1079 Chain = Res.getValue(1);
1082 // If this is an unaligned load and the target doesn't support
1084 EVT MemVT = LD->getMemoryVT();
1085 unsigned AS = LD->getAddressSpace();
1086 if (!TLI.allowsUnalignedMemoryAccesses(MemVT, AS)) {
1088 LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1089 unsigned ABIAlignment =
1090 TLI.getDataLayout()->getABITypeAlignment(Ty);
1091 if (LD->getAlignment() < ABIAlignment){
1092 ExpandUnalignedLoad(cast<LoadSDNode>(Node),
1093 DAG, TLI, Value, Chain);
1099 case TargetLowering::Expand:
1100 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) &&
1101 TLI.isTypeLegal(SrcVT)) {
1102 SDValue Load = DAG.getLoad(SrcVT, dl, Chain, Ptr,
1103 LD->getMemOperand());
1107 ExtendOp = (SrcVT.isFloatingPoint() ?
1108 ISD::FP_EXTEND : ISD::ANY_EXTEND);
1110 case ISD::SEXTLOAD: ExtendOp = ISD::SIGN_EXTEND; break;
1111 case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break;
1112 default: llvm_unreachable("Unexpected extend load type!");
1114 Value = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
1115 Chain = Load.getValue(1);
1119 assert(!SrcVT.isVector() &&
1120 "Vector Loads are handled in LegalizeVectorOps");
1122 // FIXME: This does not work for vectors on most targets. Sign-
1123 // and zero-extend operations are currently folded into extending
1124 // loads, whether they are legal or not, and then we end up here
1125 // without any support for legalizing them.
1126 assert(ExtType != ISD::EXTLOAD &&
1127 "EXTLOAD should always be supported!");
1128 // Turn the unsupported load into an EXTLOAD followed by an
1129 // explicit zero/sign extend inreg.
1130 SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl,
1131 Node->getValueType(0),
1133 LD->getMemOperand());
1135 if (ExtType == ISD::SEXTLOAD)
1136 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1137 Result.getValueType(),
1138 Result, DAG.getValueType(SrcVT));
1140 ValRes = DAG.getZeroExtendInReg(Result, dl,
1141 SrcVT.getScalarType());
1143 Chain = Result.getValue(1);
1148 // Since loads produce two values, make sure to remember that we legalized
1150 if (Chain.getNode() != Node) {
1151 assert(Value.getNode() != Node && "Load must be completely replaced");
1152 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Value);
1153 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
1158 /// LegalizeOp - Return a legal replacement for the given operation, with
1159 /// all legal operands.
1160 void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
1161 if (Node->getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
1164 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1165 assert(TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) ==
1166 TargetLowering::TypeLegal &&
1167 "Unexpected illegal type!");
1169 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1170 assert((TLI.getTypeAction(*DAG.getContext(),
1171 Node->getOperand(i).getValueType()) ==
1172 TargetLowering::TypeLegal ||
1173 Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
1174 "Unexpected illegal type!");
1176 // Figure out the correct action; the way to query this varies by opcode
1177 TargetLowering::LegalizeAction Action = TargetLowering::Legal;
1178 bool SimpleFinishLegalizing = true;
1179 switch (Node->getOpcode()) {
1180 case ISD::INTRINSIC_W_CHAIN:
1181 case ISD::INTRINSIC_WO_CHAIN:
1182 case ISD::INTRINSIC_VOID:
1183 case ISD::STACKSAVE:
1184 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1187 Action = TLI.getOperationAction(Node->getOpcode(),
1188 Node->getValueType(0));
1189 if (Action != TargetLowering::Promote)
1190 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1192 case ISD::SINT_TO_FP:
1193 case ISD::UINT_TO_FP:
1194 case ISD::EXTRACT_VECTOR_ELT:
1195 Action = TLI.getOperationAction(Node->getOpcode(),
1196 Node->getOperand(0).getValueType());
1198 case ISD::FP_ROUND_INREG:
1199 case ISD::SIGN_EXTEND_INREG: {
1200 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
1201 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
1204 case ISD::ATOMIC_STORE: {
1205 Action = TLI.getOperationAction(Node->getOpcode(),
1206 Node->getOperand(2).getValueType());
1209 case ISD::SELECT_CC:
1212 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
1213 Node->getOpcode() == ISD::SETCC ? 2 : 1;
1214 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
1215 MVT OpVT = Node->getOperand(CompareOperand).getSimpleValueType();
1216 ISD::CondCode CCCode =
1217 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
1218 Action = TLI.getCondCodeAction(CCCode, OpVT);
1219 if (Action == TargetLowering::Legal) {
1220 if (Node->getOpcode() == ISD::SELECT_CC)
1221 Action = TLI.getOperationAction(Node->getOpcode(),
1222 Node->getValueType(0));
1224 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
1230 // FIXME: Model these properly. LOAD and STORE are complicated, and
1231 // STORE expects the unlegalized operand in some cases.
1232 SimpleFinishLegalizing = false;
1234 case ISD::CALLSEQ_START:
1235 case ISD::CALLSEQ_END:
1236 // FIXME: This shouldn't be necessary. These nodes have special properties
1237 // dealing with the recursive nature of legalization. Removing this
1238 // special case should be done as part of making LegalizeDAG non-recursive.
1239 SimpleFinishLegalizing = false;
1241 case ISD::EXTRACT_ELEMENT:
1242 case ISD::FLT_ROUNDS_:
1250 case ISD::MERGE_VALUES:
1251 case ISD::EH_RETURN:
1252 case ISD::FRAME_TO_ARGS_OFFSET:
1253 case ISD::EH_SJLJ_SETJMP:
1254 case ISD::EH_SJLJ_LONGJMP:
1255 // These operations lie about being legal: when they claim to be legal,
1256 // they should actually be expanded.
1257 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1258 if (Action == TargetLowering::Legal)
1259 Action = TargetLowering::Expand;
1261 case ISD::INIT_TRAMPOLINE:
1262 case ISD::ADJUST_TRAMPOLINE:
1263 case ISD::FRAMEADDR:
1264 case ISD::RETURNADDR:
1265 // These operations lie about being legal: when they claim to be legal,
1266 // they should actually be custom-lowered.
1267 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1268 if (Action == TargetLowering::Legal)
1269 Action = TargetLowering::Custom;
1271 case ISD::DEBUGTRAP:
1272 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1273 if (Action == TargetLowering::Expand) {
1274 // replace ISD::DEBUGTRAP with ISD::TRAP
1276 NewVal = DAG.getNode(ISD::TRAP, SDLoc(Node), Node->getVTList(),
1277 Node->getOperand(0));
1278 ReplaceNode(Node, NewVal.getNode());
1279 LegalizeOp(NewVal.getNode());
1285 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1286 Action = TargetLowering::Legal;
1288 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1293 if (SimpleFinishLegalizing) {
1294 SDNode *NewNode = Node;
1295 switch (Node->getOpcode()) {
1302 // Legalizing shifts/rotates requires adjusting the shift amount
1303 // to the appropriate width.
1304 if (!Node->getOperand(1).getValueType().isVector()) {
1306 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1307 Node->getOperand(1));
1308 HandleSDNode Handle(SAO);
1309 LegalizeOp(SAO.getNode());
1310 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1314 case ISD::SRL_PARTS:
1315 case ISD::SRA_PARTS:
1316 case ISD::SHL_PARTS:
1317 // Legalizing shifts/rotates requires adjusting the shift amount
1318 // to the appropriate width.
1319 if (!Node->getOperand(2).getValueType().isVector()) {
1321 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1322 Node->getOperand(2));
1323 HandleSDNode Handle(SAO);
1324 LegalizeOp(SAO.getNode());
1325 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1326 Node->getOperand(1),
1332 if (NewNode != Node) {
1333 DAG.ReplaceAllUsesWith(Node, NewNode);
1334 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1335 DAG.TransferDbgValues(SDValue(Node, i), SDValue(NewNode, i));
1340 case TargetLowering::Legal:
1342 case TargetLowering::Custom: {
1343 // FIXME: The handling for custom lowering with multiple results is
1345 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1346 if (Res.getNode()) {
1347 SmallVector<SDValue, 8> ResultVals;
1348 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
1350 ResultVals.push_back(Res);
1352 ResultVals.push_back(Res.getValue(i));
1354 if (Res.getNode() != Node || Res.getResNo() != 0) {
1355 DAG.ReplaceAllUsesWith(Node, ResultVals.data());
1356 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1357 DAG.TransferDbgValues(SDValue(Node, i), ResultVals[i]);
1364 case TargetLowering::Expand:
1367 case TargetLowering::Promote:
1373 switch (Node->getOpcode()) {
1380 llvm_unreachable("Do not know how to legalize this operator!");
1382 case ISD::CALLSEQ_START:
1383 case ISD::CALLSEQ_END:
1386 return LegalizeLoadOps(Node);
1389 return LegalizeStoreOps(Node);
1394 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1395 SDValue Vec = Op.getOperand(0);
1396 SDValue Idx = Op.getOperand(1);
1399 // Before we generate a new store to a temporary stack slot, see if there is
1400 // already one that we can use. There often is because when we scalarize
1401 // vector operations (using SelectionDAG::UnrollVectorOp for example) a whole
1402 // series of EXTRACT_VECTOR_ELT nodes are generated, one for each element in
1403 // the vector. If all are expanded here, we don't want one store per vector
1405 SDValue StackPtr, Ch;
1406 for (SDNode::use_iterator UI = Vec.getNode()->use_begin(),
1407 UE = Vec.getNode()->use_end(); UI != UE; ++UI) {
1409 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(User)) {
1410 if (ST->isIndexed() || ST->isTruncatingStore() ||
1411 ST->getValue() != Vec)
1414 // Make sure that nothing else could have stored into the destination of
1416 if (!ST->getChain().reachesChainWithoutSideEffects(DAG.getEntryNode()))
1419 StackPtr = ST->getBasePtr();
1420 Ch = SDValue(ST, 0);
1425 if (!Ch.getNode()) {
1426 // Store the value to a temporary stack slot, then LOAD the returned part.
1427 StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1428 Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1429 MachinePointerInfo(), false, false, 0);
1432 // Add the offset to the index.
1434 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1435 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1436 DAG.getConstant(EltSize, Idx.getValueType()));
1438 Idx = DAG.getZExtOrTrunc(Idx, dl, TLI.getPointerTy());
1439 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1441 if (Op.getValueType().isVector())
1442 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,MachinePointerInfo(),
1443 false, false, false, 0);
1444 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
1445 MachinePointerInfo(),
1446 Vec.getValueType().getVectorElementType(),
1450 SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
1451 assert(Op.getValueType().isVector() && "Non-vector insert subvector!");
1453 SDValue Vec = Op.getOperand(0);
1454 SDValue Part = Op.getOperand(1);
1455 SDValue Idx = Op.getOperand(2);
1458 // Store the value to a temporary stack slot, then LOAD the returned part.
1460 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1461 int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1462 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1464 // First store the whole vector.
1465 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo,
1468 // Then store the inserted part.
1470 // Add the offset to the index.
1472 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1474 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1475 DAG.getConstant(EltSize, Idx.getValueType()));
1476 Idx = DAG.getZExtOrTrunc(Idx, dl, TLI.getPointerTy());
1478 SDValue SubStackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
1481 // Store the subvector.
1482 Ch = DAG.getStore(DAG.getEntryNode(), dl, Part, SubStackPtr,
1483 MachinePointerInfo(), false, false, 0);
1485 // Finally, load the updated vector.
1486 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo,
1487 false, false, false, 0);
1490 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1491 // We can't handle this case efficiently. Allocate a sufficiently
1492 // aligned object on the stack, store each element into it, then load
1493 // the result as a vector.
1494 // Create the stack frame object.
1495 EVT VT = Node->getValueType(0);
1496 EVT EltVT = VT.getVectorElementType();
1498 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1499 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1500 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1502 // Emit a store of each element to the stack slot.
1503 SmallVector<SDValue, 8> Stores;
1504 unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1505 // Store (in the right endianness) the elements to memory.
1506 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1507 // Ignore undef elements.
1508 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1510 unsigned Offset = TypeByteSize*i;
1512 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
1513 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1515 // If the destination vector element type is narrower than the source
1516 // element type, only store the bits necessary.
1517 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1518 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1519 Node->getOperand(i), Idx,
1520 PtrInfo.getWithOffset(Offset),
1521 EltVT, false, false, 0));
1523 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
1524 Node->getOperand(i), Idx,
1525 PtrInfo.getWithOffset(Offset),
1530 if (!Stores.empty()) // Not all undef elements?
1531 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1532 &Stores[0], Stores.size());
1534 StoreChain = DAG.getEntryNode();
1536 // Result is a load from the stack slot.
1537 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo,
1538 false, false, false, 0);
1541 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
1543 SDValue Tmp1 = Node->getOperand(0);
1544 SDValue Tmp2 = Node->getOperand(1);
1546 // Get the sign bit of the RHS. First obtain a value that has the same
1547 // sign as the sign bit, i.e. negative if and only if the sign bit is 1.
1549 EVT FloatVT = Tmp2.getValueType();
1550 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits());
1551 if (TLI.isTypeLegal(IVT)) {
1552 // Convert to an integer with the same sign bit.
1553 SignBit = DAG.getNode(ISD::BITCAST, dl, IVT, Tmp2);
1555 // Store the float to memory, then load the sign part out as an integer.
1556 MVT LoadTy = TLI.getPointerTy();
1557 // First create a temporary that is aligned for both the load and store.
1558 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1559 // Then store the float to it.
1561 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, MachinePointerInfo(),
1563 if (TLI.isBigEndian()) {
1564 assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1565 // Load out a legal integer with the same sign bit as the float.
1566 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, MachinePointerInfo(),
1567 false, false, false, 0);
1568 } else { // Little endian
1569 SDValue LoadPtr = StackPtr;
1570 // The float may be wider than the integer we are going to load. Advance
1571 // the pointer so that the loaded integer will contain the sign bit.
1572 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits();
1573 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8;
1574 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(), LoadPtr,
1575 DAG.getConstant(ByteOffset, LoadPtr.getValueType()));
1576 // Load a legal integer containing the sign bit.
1577 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(),
1578 false, false, false, 0);
1579 // Move the sign bit to the top bit of the loaded integer.
1580 unsigned BitShift = LoadTy.getSizeInBits() -
1581 (FloatVT.getSizeInBits() - 8 * ByteOffset);
1582 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?");
1584 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit,
1585 DAG.getConstant(BitShift,
1586 TLI.getShiftAmountTy(SignBit.getValueType())));
1589 // Now get the sign bit proper, by seeing whether the value is negative.
1590 SignBit = DAG.getSetCC(dl, getSetCCResultType(SignBit.getValueType()),
1591 SignBit, DAG.getConstant(0, SignBit.getValueType()),
1593 // Get the absolute value of the result.
1594 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1595 // Select between the nabs and abs value based on the sign bit of
1597 return DAG.getSelect(dl, AbsVal.getValueType(), SignBit,
1598 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1602 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1603 SmallVectorImpl<SDValue> &Results) {
1604 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1605 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1606 " not tell us which reg is the stack pointer!");
1608 EVT VT = Node->getValueType(0);
1609 SDValue Tmp1 = SDValue(Node, 0);
1610 SDValue Tmp2 = SDValue(Node, 1);
1611 SDValue Tmp3 = Node->getOperand(2);
1612 SDValue Chain = Tmp1.getOperand(0);
1614 // Chain the dynamic stack allocation so that it doesn't modify the stack
1615 // pointer when other instructions are using the stack.
1616 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
1619 SDValue Size = Tmp2.getOperand(1);
1620 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1621 Chain = SP.getValue(1);
1622 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1623 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
1624 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1625 if (Align > StackAlign)
1626 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
1627 DAG.getConstant(-(uint64_t)Align, VT));
1628 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1630 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1631 DAG.getIntPtrConstant(0, true), SDValue(),
1634 Results.push_back(Tmp1);
1635 Results.push_back(Tmp2);
1638 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
1639 /// condition code CC on the current target.
1641 /// If the SETCC has been legalized using AND / OR, then the legalized node
1642 /// will be stored in LHS. RHS and CC will be set to SDValue(). NeedInvert
1643 /// will be set to false.
1645 /// If the SETCC has been legalized by using getSetCCSwappedOperands(),
1646 /// then the values of LHS and RHS will be swapped, CC will be set to the
1647 /// new condition, and NeedInvert will be set to false.
1649 /// If the SETCC has been legalized using the inverse condcode, then LHS and
1650 /// RHS will be unchanged, CC will set to the inverted condcode, and NeedInvert
1651 /// will be set to true. The caller must invert the result of the SETCC with
1652 /// SelectionDAG::getNOT() or take equivalent action to swap the effect of a
1653 /// true/false result.
1655 /// \returns true if the SetCC has been legalized, false if it hasn't.
1656 bool SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1657 SDValue &LHS, SDValue &RHS,
1661 MVT OpVT = LHS.getSimpleValueType();
1662 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1664 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1665 default: llvm_unreachable("Unknown condition code action!");
1666 case TargetLowering::Legal:
1669 case TargetLowering::Expand: {
1670 ISD::CondCode InvCC = ISD::getSetCCSwappedOperands(CCCode);
1671 if (TLI.isCondCodeLegal(InvCC, OpVT)) {
1672 std::swap(LHS, RHS);
1673 CC = DAG.getCondCode(InvCC);
1676 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1679 default: llvm_unreachable("Don't know how to expand this condition!");
1681 assert(TLI.getCondCodeAction(ISD::SETOEQ, OpVT)
1682 == TargetLowering::Legal
1683 && "If SETO is expanded, SETOEQ must be legal!");
1684 CC1 = ISD::SETOEQ; CC2 = ISD::SETOEQ; Opc = ISD::AND; break;
1686 assert(TLI.getCondCodeAction(ISD::SETUNE, OpVT)
1687 == TargetLowering::Legal
1688 && "If SETUO is expanded, SETUNE must be legal!");
1689 CC1 = ISD::SETUNE; CC2 = ISD::SETUNE; Opc = ISD::OR; break;
1702 // If we are floating point, assign and break, otherwise fall through.
1703 if (!OpVT.isInteger()) {
1704 // We can use the 4th bit to tell if we are the unordered
1705 // or ordered version of the opcode.
1706 CC2 = ((unsigned)CCCode & 0x8U) ? ISD::SETUO : ISD::SETO;
1707 Opc = ((unsigned)CCCode & 0x8U) ? ISD::OR : ISD::AND;
1708 CC1 = (ISD::CondCode)(((int)CCCode & 0x7) | 0x10);
1711 // Fallthrough if we are unsigned integer.
1716 // We only support using the inverted operation, which is computed above
1717 // and not a different manner of supporting expanding these cases.
1718 llvm_unreachable("Don't know how to expand this condition!");
1721 // Try inverting the result of the inverse condition.
1722 InvCC = CCCode == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ;
1723 if (TLI.isCondCodeLegal(InvCC, OpVT)) {
1724 CC = DAG.getCondCode(InvCC);
1728 // If inverting the condition didn't work then we have no means to expand
1730 llvm_unreachable("Don't know how to expand this condition!");
1733 SDValue SetCC1, SetCC2;
1734 if (CCCode != ISD::SETO && CCCode != ISD::SETUO) {
1735 // If we aren't the ordered or unorder operation,
1736 // then the pattern is (LHS CC1 RHS) Opc (LHS CC2 RHS).
1737 SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1738 SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1740 // Otherwise, the pattern is (LHS CC1 LHS) Opc (RHS CC2 RHS)
1741 SetCC1 = DAG.getSetCC(dl, VT, LHS, LHS, CC1);
1742 SetCC2 = DAG.getSetCC(dl, VT, RHS, RHS, CC2);
1744 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1753 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
1754 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1755 /// a load from the stack slot to DestVT, extending it if needed.
1756 /// The resultant code need not be legal.
1757 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
1761 // Create the stack frame object.
1763 TLI.getDataLayout()->getPrefTypeAlignment(SrcOp.getValueType().
1764 getTypeForEVT(*DAG.getContext()));
1765 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1767 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1768 int SPFI = StackPtrFI->getIndex();
1769 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(SPFI);
1771 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
1772 unsigned SlotSize = SlotVT.getSizeInBits();
1773 unsigned DestSize = DestVT.getSizeInBits();
1774 Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
1775 unsigned DestAlign = TLI.getDataLayout()->getPrefTypeAlignment(DestType);
1777 // Emit a store to the stack slot. Use a truncstore if the input value is
1778 // later than DestVT.
1781 if (SrcSize > SlotSize)
1782 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1783 PtrInfo, SlotVT, false, false, SrcAlign);
1785 assert(SrcSize == SlotSize && "Invalid store");
1786 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1787 PtrInfo, false, false, SrcAlign);
1790 // Result is a load from the stack slot.
1791 if (SlotSize == DestSize)
1792 return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo,
1793 false, false, false, DestAlign);
1795 assert(SlotSize < DestSize && "Unknown extension!");
1796 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr,
1797 PtrInfo, SlotVT, false, false, DestAlign);
1800 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1802 // Create a vector sized/aligned stack slot, store the value to element #0,
1803 // then load the whole vector back out.
1804 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1806 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1807 int SPFI = StackPtrFI->getIndex();
1809 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0),
1811 MachinePointerInfo::getFixedStack(SPFI),
1812 Node->getValueType(0).getVectorElementType(),
1814 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
1815 MachinePointerInfo::getFixedStack(SPFI),
1816 false, false, false, 0);
1820 ExpandBVWithShuffles(SDNode *Node, SelectionDAG &DAG,
1821 const TargetLowering &TLI, SDValue &Res) {
1822 unsigned NumElems = Node->getNumOperands();
1824 EVT VT = Node->getValueType(0);
1826 // Try to group the scalars into pairs, shuffle the pairs together, then
1827 // shuffle the pairs of pairs together, etc. until the vector has
1828 // been built. This will work only if all of the necessary shuffle masks
1831 // We do this in two phases; first to check the legality of the shuffles,
1832 // and next, assuming that all shuffles are legal, to create the new nodes.
1833 for (int Phase = 0; Phase < 2; ++Phase) {
1834 SmallVector<std::pair<SDValue, SmallVector<int, 16> >, 16> IntermedVals,
1836 for (unsigned i = 0; i < NumElems; ++i) {
1837 SDValue V = Node->getOperand(i);
1838 if (V.getOpcode() == ISD::UNDEF)
1843 Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, V);
1844 IntermedVals.push_back(std::make_pair(Vec, SmallVector<int, 16>(1, i)));
1847 while (IntermedVals.size() > 2) {
1848 NewIntermedVals.clear();
1849 for (unsigned i = 0, e = (IntermedVals.size() & ~1u); i < e; i += 2) {
1850 // This vector and the next vector are shuffled together (simply to
1851 // append the one to the other).
1852 SmallVector<int, 16> ShuffleVec(NumElems, -1);
1854 SmallVector<int, 16> FinalIndices;
1855 FinalIndices.reserve(IntermedVals[i].second.size() +
1856 IntermedVals[i+1].second.size());
1859 for (unsigned j = 0, f = IntermedVals[i].second.size(); j != f;
1862 FinalIndices.push_back(IntermedVals[i].second[j]);
1864 for (unsigned j = 0, f = IntermedVals[i+1].second.size(); j != f;
1866 ShuffleVec[k] = NumElems + j;
1867 FinalIndices.push_back(IntermedVals[i+1].second[j]);
1872 Shuffle = DAG.getVectorShuffle(VT, dl, IntermedVals[i].first,
1873 IntermedVals[i+1].first,
1875 else if (!TLI.isShuffleMaskLegal(ShuffleVec, VT))
1877 NewIntermedVals.push_back(std::make_pair(Shuffle, FinalIndices));
1880 // If we had an odd number of defined values, then append the last
1881 // element to the array of new vectors.
1882 if ((IntermedVals.size() & 1) != 0)
1883 NewIntermedVals.push_back(IntermedVals.back());
1885 IntermedVals.swap(NewIntermedVals);
1888 assert(IntermedVals.size() <= 2 && IntermedVals.size() > 0 &&
1889 "Invalid number of intermediate vectors");
1890 SDValue Vec1 = IntermedVals[0].first;
1892 if (IntermedVals.size() > 1)
1893 Vec2 = IntermedVals[1].first;
1895 Vec2 = DAG.getUNDEF(VT);
1897 SmallVector<int, 16> ShuffleVec(NumElems, -1);
1898 for (unsigned i = 0, e = IntermedVals[0].second.size(); i != e; ++i)
1899 ShuffleVec[IntermedVals[0].second[i]] = i;
1900 for (unsigned i = 0, e = IntermedVals[1].second.size(); i != e; ++i)
1901 ShuffleVec[IntermedVals[1].second[i]] = NumElems + i;
1904 Res = DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
1905 else if (!TLI.isShuffleMaskLegal(ShuffleVec, VT))
1912 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
1913 /// support the operation, but do support the resultant vector type.
1914 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1915 unsigned NumElems = Node->getNumOperands();
1916 SDValue Value1, Value2;
1918 EVT VT = Node->getValueType(0);
1919 EVT OpVT = Node->getOperand(0).getValueType();
1920 EVT EltVT = VT.getVectorElementType();
1922 // If the only non-undef value is the low element, turn this into a
1923 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1924 bool isOnlyLowElement = true;
1925 bool MoreThanTwoValues = false;
1926 bool isConstant = true;
1927 for (unsigned i = 0; i < NumElems; ++i) {
1928 SDValue V = Node->getOperand(i);
1929 if (V.getOpcode() == ISD::UNDEF)
1932 isOnlyLowElement = false;
1933 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1936 if (!Value1.getNode()) {
1938 } else if (!Value2.getNode()) {
1941 } else if (V != Value1 && V != Value2) {
1942 MoreThanTwoValues = true;
1946 if (!Value1.getNode())
1947 return DAG.getUNDEF(VT);
1949 if (isOnlyLowElement)
1950 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1952 // If all elements are constants, create a load from the constant pool.
1954 SmallVector<Constant*, 16> CV;
1955 for (unsigned i = 0, e = NumElems; i != e; ++i) {
1956 if (ConstantFPSDNode *V =
1957 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1958 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1959 } else if (ConstantSDNode *V =
1960 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1962 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1964 // If OpVT and EltVT don't match, EltVT is not legal and the
1965 // element values have been promoted/truncated earlier. Undo this;
1966 // we don't want a v16i8 to become a v16i32 for example.
1967 const ConstantInt *CI = V->getConstantIntValue();
1968 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
1969 CI->getZExtValue()));
1972 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
1973 Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
1974 CV.push_back(UndefValue::get(OpNTy));
1977 Constant *CP = ConstantVector::get(CV);
1978 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
1979 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
1980 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
1981 MachinePointerInfo::getConstantPool(),
1982 false, false, false, Alignment);
1985 SmallSet<SDValue, 16> DefinedValues;
1986 for (unsigned i = 0; i < NumElems; ++i) {
1987 if (Node->getOperand(i).getOpcode() == ISD::UNDEF)
1989 DefinedValues.insert(Node->getOperand(i));
1992 if (TLI.shouldExpandBuildVectorWithShuffles(VT, DefinedValues.size())) {
1993 if (!MoreThanTwoValues) {
1994 SmallVector<int, 8> ShuffleVec(NumElems, -1);
1995 for (unsigned i = 0; i < NumElems; ++i) {
1996 SDValue V = Node->getOperand(i);
1997 if (V.getOpcode() == ISD::UNDEF)
1999 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
2001 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
2002 // Get the splatted value into the low element of a vector register.
2003 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
2005 if (Value2.getNode())
2006 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
2008 Vec2 = DAG.getUNDEF(VT);
2010 // Return shuffle(LowValVec, undef, <0,0,0,0>)
2011 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
2015 if (ExpandBVWithShuffles(Node, DAG, TLI, Res))
2020 // Otherwise, we can't handle this case efficiently.
2021 return ExpandVectorBuildThroughStack(Node);
2024 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
2025 // does not fit into a register, return the lo part and set the hi part to the
2026 // by-reg argument. If it does fit into a single register, return the result
2027 // and leave the Hi part unset.
2028 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
2030 TargetLowering::ArgListTy Args;
2031 TargetLowering::ArgListEntry Entry;
2032 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2033 EVT ArgVT = Node->getOperand(i).getValueType();
2034 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2035 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
2036 Entry.isSExt = isSigned;
2037 Entry.isZExt = !isSigned;
2038 Args.push_back(Entry);
2040 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2041 TLI.getPointerTy());
2043 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2045 // By default, the input chain to this libcall is the entry node of the
2046 // function. If the libcall is going to be emitted as a tail call then
2047 // TLI.isUsedByReturnOnly will change it to the right chain if the return
2048 // node which is being folded has a non-entry input chain.
2049 SDValue InChain = DAG.getEntryNode();
2051 // isTailCall may be true since the callee does not reference caller stack
2052 // frame. Check if it's in the right position.
2053 SDValue TCChain = InChain;
2054 bool isTailCall = TLI.isInTailCallPosition(DAG, Node, TCChain);
2059 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
2060 0, TLI.getLibcallCallingConv(LC), isTailCall,
2061 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2062 Callee, Args, DAG, SDLoc(Node));
2063 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2066 if (!CallInfo.second.getNode())
2067 // It's a tailcall, return the chain (which is the DAG root).
2068 return DAG.getRoot();
2070 return CallInfo.first;
2073 /// ExpandLibCall - Generate a libcall taking the given operands as arguments
2074 /// and returning a result of type RetVT.
2075 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, EVT RetVT,
2076 const SDValue *Ops, unsigned NumOps,
2077 bool isSigned, SDLoc dl) {
2078 TargetLowering::ArgListTy Args;
2079 Args.reserve(NumOps);
2081 TargetLowering::ArgListEntry Entry;
2082 for (unsigned i = 0; i != NumOps; ++i) {
2083 Entry.Node = Ops[i];
2084 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
2085 Entry.isSExt = isSigned;
2086 Entry.isZExt = !isSigned;
2087 Args.push_back(Entry);
2089 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2090 TLI.getPointerTy());
2092 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2094 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
2095 false, 0, TLI.getLibcallCallingConv(LC),
2096 /*isTailCall=*/false,
2097 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2098 Callee, Args, DAG, dl);
2099 std::pair<SDValue,SDValue> CallInfo = TLI.LowerCallTo(CLI);
2101 return CallInfo.first;
2104 // ExpandChainLibCall - Expand a node into a call to a libcall. Similar to
2105 // ExpandLibCall except that the first operand is the in-chain.
2106 std::pair<SDValue, SDValue>
2107 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
2110 SDValue InChain = Node->getOperand(0);
2112 TargetLowering::ArgListTy Args;
2113 TargetLowering::ArgListEntry Entry;
2114 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) {
2115 EVT ArgVT = Node->getOperand(i).getValueType();
2116 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2117 Entry.Node = Node->getOperand(i);
2119 Entry.isSExt = isSigned;
2120 Entry.isZExt = !isSigned;
2121 Args.push_back(Entry);
2123 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2124 TLI.getPointerTy());
2126 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2128 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
2129 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
2130 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2131 Callee, Args, DAG, SDLoc(Node));
2132 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2137 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
2138 RTLIB::Libcall Call_F32,
2139 RTLIB::Libcall Call_F64,
2140 RTLIB::Libcall Call_F80,
2141 RTLIB::Libcall Call_F128,
2142 RTLIB::Libcall Call_PPCF128) {
2144 switch (Node->getSimpleValueType(0).SimpleTy) {
2145 default: llvm_unreachable("Unexpected request for libcall!");
2146 case MVT::f32: LC = Call_F32; break;
2147 case MVT::f64: LC = Call_F64; break;
2148 case MVT::f80: LC = Call_F80; break;
2149 case MVT::f128: LC = Call_F128; break;
2150 case MVT::ppcf128: LC = Call_PPCF128; break;
2152 return ExpandLibCall(LC, Node, false);
2155 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
2156 RTLIB::Libcall Call_I8,
2157 RTLIB::Libcall Call_I16,
2158 RTLIB::Libcall Call_I32,
2159 RTLIB::Libcall Call_I64,
2160 RTLIB::Libcall Call_I128) {
2162 switch (Node->getSimpleValueType(0).SimpleTy) {
2163 default: llvm_unreachable("Unexpected request for libcall!");
2164 case MVT::i8: LC = Call_I8; break;
2165 case MVT::i16: LC = Call_I16; break;
2166 case MVT::i32: LC = Call_I32; break;
2167 case MVT::i64: LC = Call_I64; break;
2168 case MVT::i128: LC = Call_I128; break;
2170 return ExpandLibCall(LC, Node, isSigned);
2173 /// isDivRemLibcallAvailable - Return true if divmod libcall is available.
2174 static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
2175 const TargetLowering &TLI) {
2177 switch (Node->getSimpleValueType(0).SimpleTy) {
2178 default: llvm_unreachable("Unexpected request for libcall!");
2179 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2180 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2181 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2182 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2183 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2186 return TLI.getLibcallName(LC) != 0;
2189 /// useDivRem - Only issue divrem libcall if both quotient and remainder are
2191 static bool useDivRem(SDNode *Node, bool isSigned, bool isDIV) {
2192 // The other use might have been replaced with a divrem already.
2193 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2194 unsigned OtherOpcode = 0;
2196 OtherOpcode = isDIV ? ISD::SREM : ISD::SDIV;
2198 OtherOpcode = isDIV ? ISD::UREM : ISD::UDIV;
2200 SDValue Op0 = Node->getOperand(0);
2201 SDValue Op1 = Node->getOperand(1);
2202 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2203 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2207 if ((User->getOpcode() == OtherOpcode || User->getOpcode() == DivRemOpc) &&
2208 User->getOperand(0) == Op0 &&
2209 User->getOperand(1) == Op1)
2215 /// ExpandDivRemLibCall - Issue libcalls to __{u}divmod to compute div / rem
2218 SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
2219 SmallVectorImpl<SDValue> &Results) {
2220 unsigned Opcode = Node->getOpcode();
2221 bool isSigned = Opcode == ISD::SDIVREM;
2224 switch (Node->getSimpleValueType(0).SimpleTy) {
2225 default: llvm_unreachable("Unexpected request for libcall!");
2226 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2227 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2228 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2229 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2230 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2233 // The input chain to this libcall is the entry node of the function.
2234 // Legalizing the call will automatically add the previous call to the
2236 SDValue InChain = DAG.getEntryNode();
2238 EVT RetVT = Node->getValueType(0);
2239 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2241 TargetLowering::ArgListTy Args;
2242 TargetLowering::ArgListEntry Entry;
2243 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2244 EVT ArgVT = Node->getOperand(i).getValueType();
2245 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2246 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
2247 Entry.isSExt = isSigned;
2248 Entry.isZExt = !isSigned;
2249 Args.push_back(Entry);
2252 // Also pass the return address of the remainder.
2253 SDValue FIPtr = DAG.CreateStackTemporary(RetVT);
2255 Entry.Ty = RetTy->getPointerTo();
2256 Entry.isSExt = isSigned;
2257 Entry.isZExt = !isSigned;
2258 Args.push_back(Entry);
2260 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2261 TLI.getPointerTy());
2265 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
2266 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
2267 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2268 Callee, Args, DAG, dl);
2269 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2271 // Remainder is loaded back from the stack frame.
2272 SDValue Rem = DAG.getLoad(RetVT, dl, CallInfo.second, FIPtr,
2273 MachinePointerInfo(), false, false, false, 0);
2274 Results.push_back(CallInfo.first);
2275 Results.push_back(Rem);
2278 /// isSinCosLibcallAvailable - Return true if sincos libcall is available.
2279 static bool isSinCosLibcallAvailable(SDNode *Node, const TargetLowering &TLI) {
2281 switch (Node->getSimpleValueType(0).SimpleTy) {
2282 default: llvm_unreachable("Unexpected request for libcall!");
2283 case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2284 case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2285 case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2286 case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2287 case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2289 return TLI.getLibcallName(LC) != 0;
2292 /// canCombineSinCosLibcall - Return true if sincos libcall is available and
2293 /// can be used to combine sin and cos.
2294 static bool canCombineSinCosLibcall(SDNode *Node, const TargetLowering &TLI,
2295 const TargetMachine &TM) {
2296 if (!isSinCosLibcallAvailable(Node, TLI))
2298 // GNU sin/cos functions set errno while sincos does not. Therefore
2299 // combining sin and cos is only safe if unsafe-fpmath is enabled.
2300 bool isGNU = Triple(TM.getTargetTriple()).getEnvironment() == Triple::GNU;
2301 if (isGNU && !TM.Options.UnsafeFPMath)
2306 /// useSinCos - Only issue sincos libcall if both sin and cos are
2308 static bool useSinCos(SDNode *Node) {
2309 unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN
2310 ? ISD::FCOS : ISD::FSIN;
2312 SDValue Op0 = Node->getOperand(0);
2313 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2314 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2318 // The other user might have been turned into sincos already.
2319 if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS)
2325 /// ExpandSinCosLibCall - Issue libcalls to sincos to compute sin / cos
2328 SelectionDAGLegalize::ExpandSinCosLibCall(SDNode *Node,
2329 SmallVectorImpl<SDValue> &Results) {
2331 switch (Node->getSimpleValueType(0).SimpleTy) {
2332 default: llvm_unreachable("Unexpected request for libcall!");
2333 case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2334 case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2335 case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2336 case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2337 case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2340 // The input chain to this libcall is the entry node of the function.
2341 // Legalizing the call will automatically add the previous call to the
2343 SDValue InChain = DAG.getEntryNode();
2345 EVT RetVT = Node->getValueType(0);
2346 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2348 TargetLowering::ArgListTy Args;
2349 TargetLowering::ArgListEntry Entry;
2351 // Pass the argument.
2352 Entry.Node = Node->getOperand(0);
2354 Entry.isSExt = false;
2355 Entry.isZExt = false;
2356 Args.push_back(Entry);
2358 // Pass the return address of sin.
2359 SDValue SinPtr = DAG.CreateStackTemporary(RetVT);
2360 Entry.Node = SinPtr;
2361 Entry.Ty = RetTy->getPointerTo();
2362 Entry.isSExt = false;
2363 Entry.isZExt = false;
2364 Args.push_back(Entry);
2366 // Also pass the return address of the cos.
2367 SDValue CosPtr = DAG.CreateStackTemporary(RetVT);
2368 Entry.Node = CosPtr;
2369 Entry.Ty = RetTy->getPointerTo();
2370 Entry.isSExt = false;
2371 Entry.isZExt = false;
2372 Args.push_back(Entry);
2374 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2375 TLI.getPointerTy());
2379 CallLoweringInfo CLI(InChain, Type::getVoidTy(*DAG.getContext()),
2380 false, false, false, false,
2381 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
2382 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2383 Callee, Args, DAG, dl);
2384 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2386 Results.push_back(DAG.getLoad(RetVT, dl, CallInfo.second, SinPtr,
2387 MachinePointerInfo(), false, false, false, 0));
2388 Results.push_back(DAG.getLoad(RetVT, dl, CallInfo.second, CosPtr,
2389 MachinePointerInfo(), false, false, false, 0));
2392 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
2393 /// INT_TO_FP operation of the specified operand when the target requests that
2394 /// we expand it. At this point, we know that the result and operand types are
2395 /// legal for the target.
2396 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
2400 if (Op0.getValueType() == MVT::i32 && TLI.isTypeLegal(MVT::f64)) {
2401 // simple 32-bit [signed|unsigned] integer to float/double expansion
2403 // Get the stack frame index of a 8 byte buffer.
2404 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2406 // word offset constant for Hi/Lo address computation
2407 SDValue WordOff = DAG.getConstant(sizeof(int), StackSlot.getValueType());
2408 // set up Hi and Lo (into buffer) address based on endian
2409 SDValue Hi = StackSlot;
2410 SDValue Lo = DAG.getNode(ISD::ADD, dl, StackSlot.getValueType(),
2411 StackSlot, WordOff);
2412 if (TLI.isLittleEndian())
2415 // if signed map to unsigned space
2418 // constant used to invert sign bit (signed to unsigned mapping)
2419 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
2420 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2424 // store the lo of the constructed double - based on integer input
2425 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
2426 Op0Mapped, Lo, MachinePointerInfo(),
2428 // initial hi portion of constructed double
2429 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
2430 // store the hi of the constructed double - biased exponent
2431 SDValue Store2 = DAG.getStore(Store1, dl, InitialHi, Hi,
2432 MachinePointerInfo(),
2434 // load the constructed double
2435 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot,
2436 MachinePointerInfo(), false, false, false, 0);
2437 // FP constant to bias correct the final result
2438 SDValue Bias = DAG.getConstantFP(isSigned ?
2439 BitsToDouble(0x4330000080000000ULL) :
2440 BitsToDouble(0x4330000000000000ULL),
2442 // subtract the bias
2443 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2446 // handle final rounding
2447 if (DestVT == MVT::f64) {
2450 } else if (DestVT.bitsLT(MVT::f64)) {
2451 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2452 DAG.getIntPtrConstant(0));
2453 } else if (DestVT.bitsGT(MVT::f64)) {
2454 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2458 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2459 // Code below here assumes !isSigned without checking again.
2461 // Implementation of unsigned i64 to f64 following the algorithm in
2462 // __floatundidf in compiler_rt. This implementation has the advantage
2463 // of performing rounding correctly, both in the default rounding mode
2464 // and in all alternate rounding modes.
2465 // TODO: Generalize this for use with other types.
2466 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
2468 DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64);
2469 SDValue TwoP84PlusTwoP52 =
2470 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64);
2472 DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64);
2474 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32);
2475 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2476 DAG.getConstant(32, MVT::i64));
2477 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2478 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2479 SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr);
2480 SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr);
2481 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
2483 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
2486 // Implementation of unsigned i64 to f32.
2487 // TODO: Generalize this for use with other types.
2488 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) {
2489 // For unsigned conversions, convert them to signed conversions using the
2490 // algorithm from the x86_64 __floatundidf in compiler_rt.
2492 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0);
2494 SDValue ShiftConst =
2495 DAG.getConstant(1, TLI.getShiftAmountTy(Op0.getValueType()));
2496 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
2497 SDValue AndConst = DAG.getConstant(1, MVT::i64);
2498 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst);
2499 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr);
2501 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or);
2502 SDValue Slow = DAG.getNode(ISD::FADD, dl, MVT::f32, SignCvt, SignCvt);
2504 // TODO: This really should be implemented using a branch rather than a
2505 // select. We happen to get lucky and machinesink does the right
2506 // thing most of the time. This would be a good candidate for a
2507 //pseudo-op, or, even better, for whole-function isel.
2508 SDValue SignBitTest = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
2509 Op0, DAG.getConstant(0, MVT::i64), ISD::SETLT);
2510 return DAG.getSelect(dl, MVT::f32, SignBitTest, Slow, Fast);
2513 // Otherwise, implement the fully general conversion.
2515 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2516 DAG.getConstant(UINT64_C(0xfffffffffffff800), MVT::i64));
2517 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
2518 DAG.getConstant(UINT64_C(0x800), MVT::i64));
2519 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2520 DAG.getConstant(UINT64_C(0x7ff), MVT::i64));
2521 SDValue Ne = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
2522 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE);
2523 SDValue Sel = DAG.getSelect(dl, MVT::i64, Ne, Or, Op0);
2524 SDValue Ge = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
2525 Op0, DAG.getConstant(UINT64_C(0x0020000000000000), MVT::i64),
2527 SDValue Sel2 = DAG.getSelect(dl, MVT::i64, Ge, Sel, Op0);
2528 EVT SHVT = TLI.getShiftAmountTy(Sel2.getValueType());
2530 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2531 DAG.getConstant(32, SHVT));
2532 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh);
2533 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc);
2535 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), MVT::f64);
2536 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt);
2537 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2);
2538 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo);
2539 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2);
2540 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd,
2541 DAG.getIntPtrConstant(0));
2544 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2546 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(Op0.getValueType()),
2547 Op0, DAG.getConstant(0, Op0.getValueType()),
2549 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
2550 SDValue CstOffset = DAG.getSelect(dl, Zero.getValueType(),
2551 SignSet, Four, Zero);
2553 // If the sign bit of the integer is set, the large number will be treated
2554 // as a negative number. To counteract this, the dynamic code adds an
2555 // offset depending on the data type.
2557 switch (Op0.getSimpleValueType().SimpleTy) {
2558 default: llvm_unreachable("Unsupported integer type!");
2559 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2560 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2561 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2562 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2564 if (TLI.isLittleEndian()) FF <<= 32;
2565 Constant *FudgeFactor = ConstantInt::get(
2566 Type::getInt64Ty(*DAG.getContext()), FF);
2568 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
2569 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2570 CPIdx = DAG.getNode(ISD::ADD, dl, CPIdx.getValueType(), CPIdx, CstOffset);
2571 Alignment = std::min(Alignment, 4u);
2573 if (DestVT == MVT::f32)
2574 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2575 MachinePointerInfo::getConstantPool(),
2576 false, false, false, Alignment);
2578 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
2579 DAG.getEntryNode(), CPIdx,
2580 MachinePointerInfo::getConstantPool(),
2581 MVT::f32, false, false, Alignment);
2582 HandleSDNode Handle(Load);
2583 LegalizeOp(Load.getNode());
2584 FudgeInReg = Handle.getValue();
2587 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2590 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
2591 /// *INT_TO_FP operation of the specified operand when the target requests that
2592 /// we promote it. At this point, we know that the result and operand types are
2593 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2594 /// operation that takes a larger input.
2595 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2599 // First step, figure out the appropriate *INT_TO_FP operation to use.
2600 EVT NewInTy = LegalOp.getValueType();
2602 unsigned OpToUse = 0;
2604 // Scan for the appropriate larger type to use.
2606 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2607 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2609 // If the target supports SINT_TO_FP of this type, use it.
2610 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2611 OpToUse = ISD::SINT_TO_FP;
2614 if (isSigned) continue;
2616 // If the target supports UINT_TO_FP of this type, use it.
2617 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2618 OpToUse = ISD::UINT_TO_FP;
2622 // Otherwise, try a larger type.
2625 // Okay, we found the operation and type to use. Zero extend our input to the
2626 // desired type then run the operation on it.
2627 return DAG.getNode(OpToUse, dl, DestVT,
2628 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2629 dl, NewInTy, LegalOp));
2632 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
2633 /// FP_TO_*INT operation of the specified operand when the target requests that
2634 /// we promote it. At this point, we know that the result and operand types are
2635 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2636 /// operation that returns a larger result.
2637 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2641 // First step, figure out the appropriate FP_TO*INT operation to use.
2642 EVT NewOutTy = DestVT;
2644 unsigned OpToUse = 0;
2646 // Scan for the appropriate larger type to use.
2648 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2649 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2651 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2652 OpToUse = ISD::FP_TO_SINT;
2656 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2657 OpToUse = ISD::FP_TO_UINT;
2661 // Otherwise, try a larger type.
2665 // Okay, we found the operation and type to use.
2666 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2668 // Truncate the result of the extended FP_TO_*INT operation to the desired
2670 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2673 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
2675 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, SDLoc dl) {
2676 EVT VT = Op.getValueType();
2677 EVT SHVT = TLI.getShiftAmountTy(VT);
2678 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2679 switch (VT.getSimpleVT().SimpleTy) {
2680 default: llvm_unreachable("Unhandled Expand type in BSWAP!");
2682 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2683 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2684 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2686 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2687 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2688 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2689 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2690 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
2691 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
2692 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2693 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2694 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2696 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
2697 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
2698 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2699 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2700 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2701 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2702 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
2703 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
2704 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
2705 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
2706 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
2707 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
2708 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
2709 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
2710 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2711 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2712 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2713 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2714 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2715 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2716 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2720 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
2722 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2725 default: llvm_unreachable("Cannot expand this yet!");
2727 EVT VT = Op.getValueType();
2728 EVT ShVT = TLI.getShiftAmountTy(VT);
2729 unsigned Len = VT.getSizeInBits();
2731 assert(VT.isInteger() && Len <= 128 && Len % 8 == 0 &&
2732 "CTPOP not implemented for this type.");
2734 // This is the "best" algorithm from
2735 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
2737 SDValue Mask55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)), VT);
2738 SDValue Mask33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)), VT);
2739 SDValue Mask0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)), VT);
2740 SDValue Mask01 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x01)), VT);
2742 // v = v - ((v >> 1) & 0x55555555...)
2743 Op = DAG.getNode(ISD::SUB, dl, VT, Op,
2744 DAG.getNode(ISD::AND, dl, VT,
2745 DAG.getNode(ISD::SRL, dl, VT, Op,
2746 DAG.getConstant(1, ShVT)),
2748 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
2749 Op = DAG.getNode(ISD::ADD, dl, VT,
2750 DAG.getNode(ISD::AND, dl, VT, Op, Mask33),
2751 DAG.getNode(ISD::AND, dl, VT,
2752 DAG.getNode(ISD::SRL, dl, VT, Op,
2753 DAG.getConstant(2, ShVT)),
2755 // v = (v + (v >> 4)) & 0x0F0F0F0F...
2756 Op = DAG.getNode(ISD::AND, dl, VT,
2757 DAG.getNode(ISD::ADD, dl, VT, Op,
2758 DAG.getNode(ISD::SRL, dl, VT, Op,
2759 DAG.getConstant(4, ShVT))),
2761 // v = (v * 0x01010101...) >> (Len - 8)
2762 Op = DAG.getNode(ISD::SRL, dl, VT,
2763 DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
2764 DAG.getConstant(Len - 8, ShVT));
2768 case ISD::CTLZ_ZERO_UNDEF:
2769 // This trivially expands to CTLZ.
2770 return DAG.getNode(ISD::CTLZ, dl, Op.getValueType(), Op);
2772 // for now, we do this:
2773 // x = x | (x >> 1);
2774 // x = x | (x >> 2);
2776 // x = x | (x >>16);
2777 // x = x | (x >>32); // for 64-bit input
2778 // return popcount(~x);
2780 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
2781 EVT VT = Op.getValueType();
2782 EVT ShVT = TLI.getShiftAmountTy(VT);
2783 unsigned len = VT.getSizeInBits();
2784 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2785 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2786 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2787 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2789 Op = DAG.getNOT(dl, Op, VT);
2790 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2792 case ISD::CTTZ_ZERO_UNDEF:
2793 // This trivially expands to CTTZ.
2794 return DAG.getNode(ISD::CTTZ, dl, Op.getValueType(), Op);
2796 // for now, we use: { return popcount(~x & (x - 1)); }
2797 // unless the target has ctlz but not ctpop, in which case we use:
2798 // { return 32 - nlz(~x & (x-1)); }
2799 // see also http://www.hackersdelight.org/HDcode/ntz.cc
2800 EVT VT = Op.getValueType();
2801 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2802 DAG.getNOT(dl, Op, VT),
2803 DAG.getNode(ISD::SUB, dl, VT, Op,
2804 DAG.getConstant(1, VT)));
2805 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2806 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2807 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2808 return DAG.getNode(ISD::SUB, dl, VT,
2809 DAG.getConstant(VT.getSizeInBits(), VT),
2810 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2811 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2816 std::pair <SDValue, SDValue> SelectionDAGLegalize::ExpandAtomic(SDNode *Node) {
2817 unsigned Opc = Node->getOpcode();
2818 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
2823 llvm_unreachable("Unhandled atomic intrinsic Expand!");
2824 case ISD::ATOMIC_SWAP:
2825 switch (VT.SimpleTy) {
2826 default: llvm_unreachable("Unexpected value type for atomic!");
2827 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break;
2828 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
2829 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
2830 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
2831 case MVT::i128:LC = RTLIB::SYNC_LOCK_TEST_AND_SET_16;break;
2834 case ISD::ATOMIC_CMP_SWAP:
2835 switch (VT.SimpleTy) {
2836 default: llvm_unreachable("Unexpected value type for atomic!");
2837 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break;
2838 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;
2839 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;
2840 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
2841 case MVT::i128:LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16;break;
2844 case ISD::ATOMIC_LOAD_ADD:
2845 switch (VT.SimpleTy) {
2846 default: llvm_unreachable("Unexpected value type for atomic!");
2847 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break;
2848 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;
2849 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;
2850 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
2851 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_ADD_16;break;
2854 case ISD::ATOMIC_LOAD_SUB:
2855 switch (VT.SimpleTy) {
2856 default: llvm_unreachable("Unexpected value type for atomic!");
2857 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break;
2858 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;
2859 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;
2860 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
2861 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_SUB_16;break;
2864 case ISD::ATOMIC_LOAD_AND:
2865 switch (VT.SimpleTy) {
2866 default: llvm_unreachable("Unexpected value type for atomic!");
2867 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break;
2868 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;
2869 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;
2870 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
2871 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_AND_16;break;
2874 case ISD::ATOMIC_LOAD_OR:
2875 switch (VT.SimpleTy) {
2876 default: llvm_unreachable("Unexpected value type for atomic!");
2877 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break;
2878 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;
2879 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;
2880 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
2881 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_OR_16;break;
2884 case ISD::ATOMIC_LOAD_XOR:
2885 switch (VT.SimpleTy) {
2886 default: llvm_unreachable("Unexpected value type for atomic!");
2887 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break;
2888 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;
2889 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;
2890 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
2891 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_XOR_16;break;
2894 case ISD::ATOMIC_LOAD_NAND:
2895 switch (VT.SimpleTy) {
2896 default: llvm_unreachable("Unexpected value type for atomic!");
2897 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break;
2898 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;
2899 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;
2900 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
2901 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_NAND_16;break;
2904 case ISD::ATOMIC_LOAD_MAX:
2905 switch (VT.SimpleTy) {
2906 default: llvm_unreachable("Unexpected value type for atomic!");
2907 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_MAX_1; break;
2908 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_MAX_2; break;
2909 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_MAX_4; break;
2910 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_MAX_8; break;
2911 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_MAX_16;break;
2914 case ISD::ATOMIC_LOAD_UMAX:
2915 switch (VT.SimpleTy) {
2916 default: llvm_unreachable("Unexpected value type for atomic!");
2917 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_UMAX_1; break;
2918 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_UMAX_2; break;
2919 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_UMAX_4; break;
2920 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_UMAX_8; break;
2921 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_UMAX_16;break;
2924 case ISD::ATOMIC_LOAD_MIN:
2925 switch (VT.SimpleTy) {
2926 default: llvm_unreachable("Unexpected value type for atomic!");
2927 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_MIN_1; break;
2928 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_MIN_2; break;
2929 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_MIN_4; break;
2930 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_MIN_8; break;
2931 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_MIN_16;break;
2934 case ISD::ATOMIC_LOAD_UMIN:
2935 switch (VT.SimpleTy) {
2936 default: llvm_unreachable("Unexpected value type for atomic!");
2937 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_UMIN_1; break;
2938 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_UMIN_2; break;
2939 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_UMIN_4; break;
2940 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_UMIN_8; break;
2941 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_UMIN_16;break;
2946 return ExpandChainLibCall(LC, Node, false);
2949 void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
2950 SmallVector<SDValue, 8> Results;
2952 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2954 switch (Node->getOpcode()) {
2957 case ISD::CTLZ_ZERO_UNDEF:
2959 case ISD::CTTZ_ZERO_UNDEF:
2960 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
2961 Results.push_back(Tmp1);
2964 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2966 case ISD::FRAMEADDR:
2967 case ISD::RETURNADDR:
2968 case ISD::FRAME_TO_ARGS_OFFSET:
2969 Results.push_back(DAG.getConstant(0, Node->getValueType(0)));
2971 case ISD::FLT_ROUNDS_:
2972 Results.push_back(DAG.getConstant(1, Node->getValueType(0)));
2974 case ISD::EH_RETURN:
2978 case ISD::EH_SJLJ_LONGJMP:
2979 // If the target didn't expand these, there's nothing to do, so just
2980 // preserve the chain and be done.
2981 Results.push_back(Node->getOperand(0));
2983 case ISD::EH_SJLJ_SETJMP:
2984 // If the target didn't expand this, just return 'zero' and preserve the
2986 Results.push_back(DAG.getConstant(0, MVT::i32));
2987 Results.push_back(Node->getOperand(0));
2989 case ISD::ATOMIC_FENCE: {
2990 // If the target didn't lower this, lower it to '__sync_synchronize()' call
2991 // FIXME: handle "fence singlethread" more efficiently.
2992 TargetLowering::ArgListTy Args;
2994 CallLoweringInfo CLI(Node->getOperand(0),
2995 Type::getVoidTy(*DAG.getContext()),
2996 false, false, false, false, 0, CallingConv::C,
2997 /*isTailCall=*/false,
2998 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2999 DAG.getExternalSymbol("__sync_synchronize",
3000 TLI.getPointerTy()),
3002 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
3004 Results.push_back(CallResult.second);
3007 case ISD::ATOMIC_LOAD: {
3008 // There is no libcall for atomic load; fake it with ATOMIC_CMP_SWAP.
3009 SDValue Zero = DAG.getConstant(0, Node->getValueType(0));
3010 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl,
3011 cast<AtomicSDNode>(Node)->getMemoryVT(),
3012 Node->getOperand(0),
3013 Node->getOperand(1), Zero, Zero,
3014 cast<AtomicSDNode>(Node)->getMemOperand(),
3015 cast<AtomicSDNode>(Node)->getOrdering(),
3016 cast<AtomicSDNode>(Node)->getOrdering(),
3017 cast<AtomicSDNode>(Node)->getSynchScope());
3018 Results.push_back(Swap.getValue(0));
3019 Results.push_back(Swap.getValue(1));
3022 case ISD::ATOMIC_STORE: {
3023 // There is no libcall for atomic store; fake it with ATOMIC_SWAP.
3024 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
3025 cast<AtomicSDNode>(Node)->getMemoryVT(),
3026 Node->getOperand(0),
3027 Node->getOperand(1), Node->getOperand(2),
3028 cast<AtomicSDNode>(Node)->getMemOperand(),
3029 cast<AtomicSDNode>(Node)->getOrdering(),
3030 cast<AtomicSDNode>(Node)->getSynchScope());
3031 Results.push_back(Swap.getValue(1));
3034 // By default, atomic intrinsics are marked Legal and lowered. Targets
3035 // which don't support them directly, however, may want libcalls, in which
3036 // case they mark them Expand, and we get here.
3037 case ISD::ATOMIC_SWAP:
3038 case ISD::ATOMIC_LOAD_ADD:
3039 case ISD::ATOMIC_LOAD_SUB:
3040 case ISD::ATOMIC_LOAD_AND:
3041 case ISD::ATOMIC_LOAD_OR:
3042 case ISD::ATOMIC_LOAD_XOR:
3043 case ISD::ATOMIC_LOAD_NAND:
3044 case ISD::ATOMIC_LOAD_MIN:
3045 case ISD::ATOMIC_LOAD_MAX:
3046 case ISD::ATOMIC_LOAD_UMIN:
3047 case ISD::ATOMIC_LOAD_UMAX:
3048 case ISD::ATOMIC_CMP_SWAP: {
3049 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node);
3050 Results.push_back(Tmp.first);
3051 Results.push_back(Tmp.second);
3054 case ISD::DYNAMIC_STACKALLOC:
3055 ExpandDYNAMIC_STACKALLOC(Node, Results);
3057 case ISD::MERGE_VALUES:
3058 for (unsigned i = 0; i < Node->getNumValues(); i++)
3059 Results.push_back(Node->getOperand(i));
3062 EVT VT = Node->getValueType(0);
3064 Results.push_back(DAG.getConstant(0, VT));
3066 assert(VT.isFloatingPoint() && "Unknown value type!");
3067 Results.push_back(DAG.getConstantFP(0, VT));
3072 // If this operation is not supported, lower it to 'abort()' call
3073 TargetLowering::ArgListTy Args;
3075 CallLoweringInfo CLI(Node->getOperand(0),
3076 Type::getVoidTy(*DAG.getContext()),
3077 false, false, false, false, 0, CallingConv::C,
3078 /*isTailCall=*/false,
3079 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
3080 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
3082 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
3084 Results.push_back(CallResult.second);
3089 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3090 Node->getValueType(0), dl);
3091 Results.push_back(Tmp1);
3093 case ISD::FP_EXTEND:
3094 Tmp1 = EmitStackConvert(Node->getOperand(0),
3095 Node->getOperand(0).getValueType(),
3096 Node->getValueType(0), dl);
3097 Results.push_back(Tmp1);
3099 case ISD::SIGN_EXTEND_INREG: {
3100 // NOTE: we could fall back on load/store here too for targets without
3101 // SAR. However, it is doubtful that any exist.
3102 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3103 EVT VT = Node->getValueType(0);
3104 EVT ShiftAmountTy = TLI.getShiftAmountTy(VT);
3107 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
3108 ExtraVT.getScalarType().getSizeInBits();
3109 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy);
3110 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
3111 Node->getOperand(0), ShiftCst);
3112 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
3113 Results.push_back(Tmp1);
3116 case ISD::FP_ROUND_INREG: {
3117 // The only way we can lower this is to turn it into a TRUNCSTORE,
3118 // EXTLOAD pair, targeting a temporary location (a stack slot).
3120 // NOTE: there is a choice here between constantly creating new stack
3121 // slots and always reusing the same one. We currently always create
3122 // new ones, as reuse may inhibit scheduling.
3123 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3124 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
3125 Node->getValueType(0), dl);
3126 Results.push_back(Tmp1);
3129 case ISD::SINT_TO_FP:
3130 case ISD::UINT_TO_FP:
3131 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
3132 Node->getOperand(0), Node->getValueType(0), dl);
3133 Results.push_back(Tmp1);
3135 case ISD::FP_TO_UINT: {
3136 SDValue True, False;
3137 EVT VT = Node->getOperand(0).getValueType();
3138 EVT NVT = Node->getValueType(0);
3139 APFloat apf(DAG.EVTToAPFloatSemantics(VT),
3140 APInt::getNullValue(VT.getSizeInBits()));
3141 APInt x = APInt::getSignBit(NVT.getSizeInBits());
3142 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
3143 Tmp1 = DAG.getConstantFP(apf, VT);
3144 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(VT),
3145 Node->getOperand(0),
3147 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
3148 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
3149 DAG.getNode(ISD::FSUB, dl, VT,
3150 Node->getOperand(0), Tmp1));
3151 False = DAG.getNode(ISD::XOR, dl, NVT, False,
3152 DAG.getConstant(x, NVT));
3153 Tmp1 = DAG.getSelect(dl, NVT, Tmp2, True, False);
3154 Results.push_back(Tmp1);
3158 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3159 EVT VT = Node->getValueType(0);
3160 Tmp1 = Node->getOperand(0);
3161 Tmp2 = Node->getOperand(1);
3162 unsigned Align = Node->getConstantOperandVal(3);
3164 SDValue VAListLoad = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2,
3165 MachinePointerInfo(V),
3166 false, false, false, 0);
3167 SDValue VAList = VAListLoad;
3169 if (Align > TLI.getMinStackArgumentAlignment()) {
3170 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
3172 VAList = DAG.getNode(ISD::ADD, dl, VAList.getValueType(), VAList,
3173 DAG.getConstant(Align - 1,
3174 VAList.getValueType()));
3176 VAList = DAG.getNode(ISD::AND, dl, VAList.getValueType(), VAList,
3177 DAG.getConstant(-(int64_t)Align,
3178 VAList.getValueType()));
3181 // Increment the pointer, VAList, to the next vaarg
3182 Tmp3 = DAG.getNode(ISD::ADD, dl, VAList.getValueType(), VAList,
3183 DAG.getConstant(TLI.getDataLayout()->
3184 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())),
3185 VAList.getValueType()));
3186 // Store the incremented VAList to the legalized pointer
3187 Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2,
3188 MachinePointerInfo(V), false, false, 0);
3189 // Load the actual argument out of the pointer VAList
3190 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(),
3191 false, false, false, 0));
3192 Results.push_back(Results[0].getValue(1));
3196 // This defaults to loading a pointer from the input and storing it to the
3197 // output, returning the chain.
3198 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3199 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3200 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0),
3201 Node->getOperand(2), MachinePointerInfo(VS),
3202 false, false, false, 0);
3203 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1),
3204 MachinePointerInfo(VD), false, false, 0);
3205 Results.push_back(Tmp1);
3208 case ISD::EXTRACT_VECTOR_ELT:
3209 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
3210 // This must be an access of the only element. Return it.
3211 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
3212 Node->getOperand(0));
3214 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
3215 Results.push_back(Tmp1);
3217 case ISD::EXTRACT_SUBVECTOR:
3218 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
3220 case ISD::INSERT_SUBVECTOR:
3221 Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0)));
3223 case ISD::CONCAT_VECTORS: {
3224 Results.push_back(ExpandVectorBuildThroughStack(Node));
3227 case ISD::SCALAR_TO_VECTOR:
3228 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
3230 case ISD::INSERT_VECTOR_ELT:
3231 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
3232 Node->getOperand(1),
3233 Node->getOperand(2), dl));
3235 case ISD::VECTOR_SHUFFLE: {
3236 SmallVector<int, 32> NewMask;
3237 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
3239 EVT VT = Node->getValueType(0);
3240 EVT EltVT = VT.getVectorElementType();
3241 SDValue Op0 = Node->getOperand(0);
3242 SDValue Op1 = Node->getOperand(1);
3243 if (!TLI.isTypeLegal(EltVT)) {
3245 EVT NewEltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
3247 // BUILD_VECTOR operands are allowed to be wider than the element type.
3248 // But if NewEltVT is smaller that EltVT the BUILD_VECTOR does not accept
3250 if (NewEltVT.bitsLT(EltVT)) {
3252 // Convert shuffle node.
3253 // If original node was v4i64 and the new EltVT is i32,
3254 // cast operands to v8i32 and re-build the mask.
3256 // Calculate new VT, the size of the new VT should be equal to original.
3258 EVT::getVectorVT(*DAG.getContext(), NewEltVT,
3259 VT.getSizeInBits() / NewEltVT.getSizeInBits());
3260 assert(NewVT.bitsEq(VT));
3262 // cast operands to new VT
3263 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0);
3264 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1);
3266 // Convert the shuffle mask
3267 unsigned int factor =
3268 NewVT.getVectorNumElements()/VT.getVectorNumElements();
3270 // EltVT gets smaller
3273 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
3275 for (unsigned fi = 0; fi < factor; ++fi)
3276 NewMask.push_back(Mask[i]);
3279 for (unsigned fi = 0; fi < factor; ++fi)
3280 NewMask.push_back(Mask[i]*factor+fi);
3288 unsigned NumElems = VT.getVectorNumElements();
3289 SmallVector<SDValue, 16> Ops;
3290 for (unsigned i = 0; i != NumElems; ++i) {
3292 Ops.push_back(DAG.getUNDEF(EltVT));
3295 unsigned Idx = Mask[i];
3297 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3299 DAG.getConstant(Idx, TLI.getVectorIdxTy())));
3301 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3303 DAG.getConstant(Idx - NumElems,
3304 TLI.getVectorIdxTy())));
3307 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
3308 // We may have changed the BUILD_VECTOR type. Cast it back to the Node type.
3309 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), Tmp1);
3310 Results.push_back(Tmp1);
3313 case ISD::EXTRACT_ELEMENT: {
3314 EVT OpTy = Node->getOperand(0).getValueType();
3315 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
3317 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
3318 DAG.getConstant(OpTy.getSizeInBits()/2,
3319 TLI.getShiftAmountTy(Node->getOperand(0).getValueType())));
3320 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
3323 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
3324 Node->getOperand(0));
3326 Results.push_back(Tmp1);
3329 case ISD::STACKSAVE:
3330 // Expand to CopyFromReg if the target set
3331 // StackPointerRegisterToSaveRestore.
3332 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3333 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
3334 Node->getValueType(0)));
3335 Results.push_back(Results[0].getValue(1));
3337 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
3338 Results.push_back(Node->getOperand(0));
3341 case ISD::STACKRESTORE:
3342 // Expand to CopyToReg if the target set
3343 // StackPointerRegisterToSaveRestore.
3344 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3345 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
3346 Node->getOperand(1)));
3348 Results.push_back(Node->getOperand(0));
3351 case ISD::FCOPYSIGN:
3352 Results.push_back(ExpandFCOPYSIGN(Node));
3355 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3356 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3357 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
3358 Node->getOperand(0));
3359 Results.push_back(Tmp1);
3362 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3363 EVT VT = Node->getValueType(0);
3364 Tmp1 = Node->getOperand(0);
3365 Tmp2 = DAG.getConstantFP(0.0, VT);
3366 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(Tmp1.getValueType()),
3367 Tmp1, Tmp2, ISD::SETUGT);
3368 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
3369 Tmp1 = DAG.getSelect(dl, VT, Tmp2, Tmp1, Tmp3);
3370 Results.push_back(Tmp1);
3374 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3375 RTLIB::SQRT_F80, RTLIB::SQRT_F128,
3376 RTLIB::SQRT_PPCF128));
3380 EVT VT = Node->getValueType(0);
3381 bool isSIN = Node->getOpcode() == ISD::FSIN;
3382 // Turn fsin / fcos into ISD::FSINCOS node if there are a pair of fsin /
3383 // fcos which share the same operand and both are used.
3384 if ((TLI.isOperationLegalOrCustom(ISD::FSINCOS, VT) ||
3385 canCombineSinCosLibcall(Node, TLI, TM))
3386 && useSinCos(Node)) {
3387 SDVTList VTs = DAG.getVTList(VT, VT);
3388 Tmp1 = DAG.getNode(ISD::FSINCOS, dl, VTs, Node->getOperand(0));
3390 Tmp1 = Tmp1.getValue(1);
3391 Results.push_back(Tmp1);
3393 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
3394 RTLIB::SIN_F80, RTLIB::SIN_F128,
3395 RTLIB::SIN_PPCF128));
3397 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
3398 RTLIB::COS_F80, RTLIB::COS_F128,
3399 RTLIB::COS_PPCF128));
3404 // Expand into sincos libcall.
3405 ExpandSinCosLibCall(Node, Results);
3408 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
3409 RTLIB::LOG_F80, RTLIB::LOG_F128,
3410 RTLIB::LOG_PPCF128));
3413 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3414 RTLIB::LOG2_F80, RTLIB::LOG2_F128,
3415 RTLIB::LOG2_PPCF128));
3418 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3419 RTLIB::LOG10_F80, RTLIB::LOG10_F128,
3420 RTLIB::LOG10_PPCF128));
3423 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
3424 RTLIB::EXP_F80, RTLIB::EXP_F128,
3425 RTLIB::EXP_PPCF128));
3428 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3429 RTLIB::EXP2_F80, RTLIB::EXP2_F128,
3430 RTLIB::EXP2_PPCF128));
3433 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3434 RTLIB::TRUNC_F80, RTLIB::TRUNC_F128,
3435 RTLIB::TRUNC_PPCF128));
3438 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3439 RTLIB::FLOOR_F80, RTLIB::FLOOR_F128,
3440 RTLIB::FLOOR_PPCF128));
3443 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3444 RTLIB::CEIL_F80, RTLIB::CEIL_F128,
3445 RTLIB::CEIL_PPCF128));
3448 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
3449 RTLIB::RINT_F80, RTLIB::RINT_F128,
3450 RTLIB::RINT_PPCF128));
3452 case ISD::FNEARBYINT:
3453 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
3454 RTLIB::NEARBYINT_F64,
3455 RTLIB::NEARBYINT_F80,
3456 RTLIB::NEARBYINT_F128,
3457 RTLIB::NEARBYINT_PPCF128));
3460 Results.push_back(ExpandFPLibCall(Node, RTLIB::ROUND_F32,
3464 RTLIB::ROUND_PPCF128));
3467 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
3468 RTLIB::POWI_F80, RTLIB::POWI_F128,
3469 RTLIB::POWI_PPCF128));
3472 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
3473 RTLIB::POW_F80, RTLIB::POW_F128,
3474 RTLIB::POW_PPCF128));
3477 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
3478 RTLIB::DIV_F80, RTLIB::DIV_F128,
3479 RTLIB::DIV_PPCF128));
3482 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
3483 RTLIB::REM_F80, RTLIB::REM_F128,
3484 RTLIB::REM_PPCF128));
3487 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMA_F32, RTLIB::FMA_F64,
3488 RTLIB::FMA_F80, RTLIB::FMA_F128,
3489 RTLIB::FMA_PPCF128));
3491 case ISD::FP16_TO_FP32:
3492 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
3494 case ISD::FP32_TO_FP16:
3495 Results.push_back(ExpandLibCall(RTLIB::FPROUND_F32_F16, Node, false));
3497 case ISD::ConstantFP: {
3498 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
3499 // Check to see if this FP immediate is already legal.
3500 // If this is a legal constant, turn it into a TargetConstantFP node.
3501 if (!TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
3502 Results.push_back(ExpandConstantFP(CFP, true));
3506 EVT VT = Node->getValueType(0);
3507 assert(TLI.isOperationLegalOrCustom(ISD::FADD, VT) &&
3508 TLI.isOperationLegalOrCustom(ISD::FNEG, VT) &&
3509 "Don't know how to expand this FP subtraction!");
3510 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1));
3511 Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1);
3512 Results.push_back(Tmp1);
3516 EVT VT = Node->getValueType(0);
3517 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3518 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3519 "Don't know how to expand this subtraction!");
3520 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3521 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
3522 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, VT));
3523 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3528 EVT VT = Node->getValueType(0);
3529 bool isSigned = Node->getOpcode() == ISD::SREM;
3530 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3531 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3532 Tmp2 = Node->getOperand(0);
3533 Tmp3 = Node->getOperand(1);
3534 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3535 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3536 // If div is legal, it's better to do the normal expansion
3537 !TLI.isOperationLegalOrCustom(DivOpc, Node->getValueType(0)) &&
3538 useDivRem(Node, isSigned, false))) {
3539 SDVTList VTs = DAG.getVTList(VT, VT);
3540 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
3541 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
3543 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
3544 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3545 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3546 } else if (isSigned)
3547 Tmp1 = ExpandIntLibCall(Node, true,
3549 RTLIB::SREM_I16, RTLIB::SREM_I32,
3550 RTLIB::SREM_I64, RTLIB::SREM_I128);
3552 Tmp1 = ExpandIntLibCall(Node, false,
3554 RTLIB::UREM_I16, RTLIB::UREM_I32,
3555 RTLIB::UREM_I64, RTLIB::UREM_I128);
3556 Results.push_back(Tmp1);
3561 bool isSigned = Node->getOpcode() == ISD::SDIV;
3562 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3563 EVT VT = Node->getValueType(0);
3564 SDVTList VTs = DAG.getVTList(VT, VT);
3565 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3566 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3567 useDivRem(Node, isSigned, true)))
3568 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
3569 Node->getOperand(1));
3571 Tmp1 = ExpandIntLibCall(Node, true,
3573 RTLIB::SDIV_I16, RTLIB::SDIV_I32,
3574 RTLIB::SDIV_I64, RTLIB::SDIV_I128);
3576 Tmp1 = ExpandIntLibCall(Node, false,
3578 RTLIB::UDIV_I16, RTLIB::UDIV_I32,
3579 RTLIB::UDIV_I64, RTLIB::UDIV_I128);
3580 Results.push_back(Tmp1);
3585 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
3587 EVT VT = Node->getValueType(0);
3588 SDVTList VTs = DAG.getVTList(VT, VT);
3589 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
3590 "If this wasn't legal, it shouldn't have been created!");
3591 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
3592 Node->getOperand(1));
3593 Results.push_back(Tmp1.getValue(1));
3598 // Expand into divrem libcall
3599 ExpandDivRemLibCall(Node, Results);
3602 EVT VT = Node->getValueType(0);
3603 SDVTList VTs = DAG.getVTList(VT, VT);
3604 // See if multiply or divide can be lowered using two-result operations.
3605 // We just need the low half of the multiply; try both the signed
3606 // and unsigned forms. If the target supports both SMUL_LOHI and
3607 // UMUL_LOHI, form a preference by checking which forms of plain
3608 // MULH it supports.
3609 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3610 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3611 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3612 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3613 unsigned OpToUse = 0;
3614 if (HasSMUL_LOHI && !HasMULHS) {
3615 OpToUse = ISD::SMUL_LOHI;
3616 } else if (HasUMUL_LOHI && !HasMULHU) {
3617 OpToUse = ISD::UMUL_LOHI;
3618 } else if (HasSMUL_LOHI) {
3619 OpToUse = ISD::SMUL_LOHI;
3620 } else if (HasUMUL_LOHI) {
3621 OpToUse = ISD::UMUL_LOHI;
3624 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
3625 Node->getOperand(1)));
3628 Tmp1 = ExpandIntLibCall(Node, false,
3630 RTLIB::MUL_I16, RTLIB::MUL_I32,
3631 RTLIB::MUL_I64, RTLIB::MUL_I128);
3632 Results.push_back(Tmp1);
3637 SDValue LHS = Node->getOperand(0);
3638 SDValue RHS = Node->getOperand(1);
3639 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3640 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3642 Results.push_back(Sum);
3643 EVT OType = Node->getValueType(1);
3645 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
3647 // LHSSign -> LHS >= 0
3648 // RHSSign -> RHS >= 0
3649 // SumSign -> Sum >= 0
3652 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3654 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3656 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3657 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3658 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
3659 Node->getOpcode() == ISD::SADDO ?
3660 ISD::SETEQ : ISD::SETNE);
3662 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3663 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3665 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3666 Results.push_back(Cmp);
3671 SDValue LHS = Node->getOperand(0);
3672 SDValue RHS = Node->getOperand(1);
3673 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
3674 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3676 Results.push_back(Sum);
3677 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS,
3678 Node->getOpcode () == ISD::UADDO ?
3679 ISD::SETULT : ISD::SETUGT));
3684 EVT VT = Node->getValueType(0);
3685 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
3686 SDValue LHS = Node->getOperand(0);
3687 SDValue RHS = Node->getOperand(1);
3690 static const unsigned Ops[2][3] =
3691 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
3692 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
3693 bool isSigned = Node->getOpcode() == ISD::SMULO;
3694 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3695 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3696 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3697 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3698 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3700 TopHalf = BottomHalf.getValue(1);
3701 } else if (TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(),
3702 VT.getSizeInBits() * 2))) {
3703 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
3704 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
3705 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
3706 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3707 DAG.getIntPtrConstant(0));
3708 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3709 DAG.getIntPtrConstant(1));
3711 // We can fall back to a libcall with an illegal type for the MUL if we
3712 // have a libcall big enough.
3713 // Also, we can fall back to a division in some cases, but that's a big
3714 // performance hit in the general case.
3715 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3716 if (WideVT == MVT::i16)
3717 LC = RTLIB::MUL_I16;
3718 else if (WideVT == MVT::i32)
3719 LC = RTLIB::MUL_I32;
3720 else if (WideVT == MVT::i64)
3721 LC = RTLIB::MUL_I64;
3722 else if (WideVT == MVT::i128)
3723 LC = RTLIB::MUL_I128;
3724 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!");
3726 // The high part is obtained by SRA'ing all but one of the bits of low
3728 unsigned LoSize = VT.getSizeInBits();
3729 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, RHS,
3730 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
3731 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, VT, LHS,
3732 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
3734 // Here we're passing the 2 arguments explicitly as 4 arguments that are
3735 // pre-lowered to the correct types. This all depends upon WideVT not
3736 // being a legal type for the architecture and thus has to be split to
3738 SDValue Args[] = { LHS, HiLHS, RHS, HiRHS };
3739 SDValue Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl);
3740 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3741 DAG.getIntPtrConstant(0));
3742 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3743 DAG.getIntPtrConstant(1));
3744 // Ret is a node with an illegal type. Because such things are not
3745 // generally permitted during this phase of legalization, delete the
3746 // node. The above EXTRACT_ELEMENT nodes should have been folded.
3747 DAG.DeleteNode(Ret.getNode());
3751 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1,
3752 TLI.getShiftAmountTy(BottomHalf.getValueType()));
3753 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3754 TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf, Tmp1,
3757 TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf,
3758 DAG.getConstant(0, VT), ISD::SETNE);
3760 Results.push_back(BottomHalf);
3761 Results.push_back(TopHalf);
3764 case ISD::BUILD_PAIR: {
3765 EVT PairTy = Node->getValueType(0);
3766 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3767 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3768 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
3769 DAG.getConstant(PairTy.getSizeInBits()/2,
3770 TLI.getShiftAmountTy(PairTy)));
3771 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3775 Tmp1 = Node->getOperand(0);
3776 Tmp2 = Node->getOperand(1);
3777 Tmp3 = Node->getOperand(2);
3778 if (Tmp1.getOpcode() == ISD::SETCC) {
3779 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3781 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3783 Tmp1 = DAG.getSelectCC(dl, Tmp1,
3784 DAG.getConstant(0, Tmp1.getValueType()),
3785 Tmp2, Tmp3, ISD::SETNE);
3787 Results.push_back(Tmp1);
3790 SDValue Chain = Node->getOperand(0);
3791 SDValue Table = Node->getOperand(1);
3792 SDValue Index = Node->getOperand(2);
3794 EVT PTy = TLI.getPointerTy();
3796 const DataLayout &TD = *TLI.getDataLayout();
3797 unsigned EntrySize =
3798 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
3800 Index = DAG.getNode(ISD::MUL, dl, Index.getValueType(),
3801 Index, DAG.getConstant(EntrySize, Index.getValueType()));
3802 SDValue Addr = DAG.getNode(ISD::ADD, dl, Index.getValueType(),
3805 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
3806 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
3807 MachinePointerInfo::getJumpTable(), MemVT,
3810 if (TM.getRelocationModel() == Reloc::PIC_) {
3811 // For PIC, the sequence is:
3812 // BRIND(load(Jumptable + index) + RelocBase)
3813 // RelocBase can be JumpTable, GOT or some sort of global base.
3814 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3815 TLI.getPICJumpTableRelocBase(Table, DAG));
3817 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
3818 Results.push_back(Tmp1);
3822 // Expand brcond's setcc into its constituent parts and create a BR_CC
3824 Tmp1 = Node->getOperand(0);
3825 Tmp2 = Node->getOperand(1);
3826 if (Tmp2.getOpcode() == ISD::SETCC) {
3827 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3828 Tmp1, Tmp2.getOperand(2),
3829 Tmp2.getOperand(0), Tmp2.getOperand(1),
3830 Node->getOperand(2));
3832 // We test only the i1 bit. Skip the AND if UNDEF.
3833 Tmp3 = (Tmp2.getOpcode() == ISD::UNDEF) ? Tmp2 :
3834 DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2,
3835 DAG.getConstant(1, Tmp2.getValueType()));
3836 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3837 DAG.getCondCode(ISD::SETNE), Tmp3,
3838 DAG.getConstant(0, Tmp3.getValueType()),
3839 Node->getOperand(2));
3841 Results.push_back(Tmp1);
3844 Tmp1 = Node->getOperand(0);
3845 Tmp2 = Node->getOperand(1);
3846 Tmp3 = Node->getOperand(2);
3847 bool Legalized = LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2,
3848 Tmp3, NeedInvert, dl);
3851 // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3852 // condition code, create a new SETCC node.
3854 Tmp1 = DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3857 // If we expanded the SETCC by inverting the condition code, then wrap
3858 // the existing SETCC in a NOT to restore the intended condition.
3860 Tmp1 = DAG.getNOT(dl, Tmp1, Tmp1->getValueType(0));
3862 Results.push_back(Tmp1);
3866 // Otherwise, SETCC for the given comparison type must be completely
3867 // illegal; expand it into a SELECT_CC.
3868 EVT VT = Node->getValueType(0);
3870 switch (TLI.getBooleanContents(VT.isVector())) {
3871 case TargetLowering::ZeroOrOneBooleanContent:
3872 case TargetLowering::UndefinedBooleanContent:
3875 case TargetLowering::ZeroOrNegativeOneBooleanContent:
3879 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3880 DAG.getConstant(TrueValue, VT), DAG.getConstant(0, VT),
3882 Results.push_back(Tmp1);
3885 case ISD::SELECT_CC: {
3886 Tmp1 = Node->getOperand(0); // LHS
3887 Tmp2 = Node->getOperand(1); // RHS
3888 Tmp3 = Node->getOperand(2); // True
3889 Tmp4 = Node->getOperand(3); // False
3890 SDValue CC = Node->getOperand(4);
3892 bool Legalized = false;
3893 // Try to legalize by inverting the condition. This is for targets that
3894 // might support an ordered version of a condition, but not the unordered
3895 // version (or vice versa).
3896 ISD::CondCode InvCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
3897 Tmp1.getValueType().isInteger());
3898 if (TLI.isCondCodeLegal(InvCC, Tmp1.getSimpleValueType())) {
3899 // Use the new condition code and swap true and false
3901 Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp4, Tmp3, InvCC);
3903 // If The inverse is not legal, then try to swap the arguments using
3904 // the inverse condition code.
3905 ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(InvCC);
3906 if (TLI.isCondCodeLegal(SwapInvCC, Tmp1.getSimpleValueType())) {
3907 // The swapped inverse condition is legal, so swap true and false,
3910 Tmp1 = DAG.getSelectCC(dl, Tmp2, Tmp1, Tmp4, Tmp3, SwapInvCC);
3915 Legalized = LegalizeSetCCCondCode(
3916 getSetCCResultType(Tmp1.getValueType()), Tmp1, Tmp2, CC, NeedInvert,
3919 assert(Legalized && "Can't legalize SELECT_CC with legal condition!");
3921 // If we expanded the SETCC by inverting the condition code, then swap
3922 // the True/False operands to match.
3924 std::swap(Tmp3, Tmp4);
3926 // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3927 // condition code, create a new SELECT_CC node.
3929 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0),
3930 Tmp1, Tmp2, Tmp3, Tmp4, CC);
3932 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3933 CC = DAG.getCondCode(ISD::SETNE);
3934 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1,
3935 Tmp2, Tmp3, Tmp4, CC);
3938 Results.push_back(Tmp1);
3942 Tmp1 = Node->getOperand(0); // Chain
3943 Tmp2 = Node->getOperand(2); // LHS
3944 Tmp3 = Node->getOperand(3); // RHS
3945 Tmp4 = Node->getOperand(1); // CC
3947 bool Legalized = LegalizeSetCCCondCode(getSetCCResultType(
3948 Tmp2.getValueType()), Tmp2, Tmp3, Tmp4, NeedInvert, dl);
3950 assert(Legalized && "Can't legalize BR_CC with legal condition!");
3952 // If we expanded the SETCC by inverting the condition code, then wrap
3953 // the existing SETCC in a NOT to restore the intended condition.
3955 Tmp4 = DAG.getNOT(dl, Tmp4, Tmp4->getValueType(0));
3957 // If we expanded the SETCC by swapping LHS and RHS, create a new BR_CC
3959 if (Tmp4.getNode()) {
3960 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1,
3961 Tmp4, Tmp2, Tmp3, Node->getOperand(4));
3963 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
3964 Tmp4 = DAG.getCondCode(ISD::SETNE);
3965 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4,
3966 Tmp2, Tmp3, Node->getOperand(4));
3968 Results.push_back(Tmp1);
3971 case ISD::BUILD_VECTOR:
3972 Results.push_back(ExpandBUILD_VECTOR(Node));
3977 // Scalarize vector SRA/SRL/SHL.
3978 EVT VT = Node->getValueType(0);
3979 assert(VT.isVector() && "Unable to legalize non-vector shift");
3980 assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
3981 unsigned NumElem = VT.getVectorNumElements();
3983 SmallVector<SDValue, 8> Scalars;
3984 for (unsigned Idx = 0; Idx < NumElem; Idx++) {
3985 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3987 Node->getOperand(0), DAG.getConstant(Idx,
3988 TLI.getVectorIdxTy()));
3989 SDValue Sh = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3991 Node->getOperand(1), DAG.getConstant(Idx,
3992 TLI.getVectorIdxTy()));
3993 Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
3994 VT.getScalarType(), Ex, Sh));
3997 DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0),
3998 &Scalars[0], Scalars.size());
3999 ReplaceNode(SDValue(Node, 0), Result);
4002 case ISD::GLOBAL_OFFSET_TABLE:
4003 case ISD::GlobalAddress:
4004 case ISD::GlobalTLSAddress:
4005 case ISD::ExternalSymbol:
4006 case ISD::ConstantPool:
4007 case ISD::JumpTable:
4008 case ISD::INTRINSIC_W_CHAIN:
4009 case ISD::INTRINSIC_WO_CHAIN:
4010 case ISD::INTRINSIC_VOID:
4011 // FIXME: Custom lowering for these operations shouldn't return null!
4015 // Replace the original node with the legalized result.
4016 if (!Results.empty())
4017 ReplaceNode(Node, Results.data());
4020 void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
4021 SmallVector<SDValue, 8> Results;
4022 MVT OVT = Node->getSimpleValueType(0);
4023 if (Node->getOpcode() == ISD::UINT_TO_FP ||
4024 Node->getOpcode() == ISD::SINT_TO_FP ||
4025 Node->getOpcode() == ISD::SETCC) {
4026 OVT = Node->getOperand(0).getSimpleValueType();
4028 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
4030 SDValue Tmp1, Tmp2, Tmp3;
4031 switch (Node->getOpcode()) {
4033 case ISD::CTTZ_ZERO_UNDEF:
4035 case ISD::CTLZ_ZERO_UNDEF:
4037 // Zero extend the argument.
4038 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4039 // Perform the larger operation. For CTPOP and CTTZ_ZERO_UNDEF, this is
4040 // already the correct result.
4041 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4042 if (Node->getOpcode() == ISD::CTTZ) {
4043 // FIXME: This should set a bit in the zero extended value instead.
4044 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT),
4045 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
4047 Tmp1 = DAG.getSelect(dl, NVT, Tmp2,
4048 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
4049 } else if (Node->getOpcode() == ISD::CTLZ ||
4050 Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) {
4051 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4052 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
4053 DAG.getConstant(NVT.getSizeInBits() -
4054 OVT.getSizeInBits(), NVT));
4056 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
4059 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
4060 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4061 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
4062 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
4063 DAG.getConstant(DiffBits, TLI.getShiftAmountTy(NVT)));
4064 Results.push_back(Tmp1);
4067 case ISD::FP_TO_UINT:
4068 case ISD::FP_TO_SINT:
4069 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
4070 Node->getOpcode() == ISD::FP_TO_SINT, dl);
4071 Results.push_back(Tmp1);
4073 case ISD::UINT_TO_FP:
4074 case ISD::SINT_TO_FP:
4075 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
4076 Node->getOpcode() == ISD::SINT_TO_FP, dl);
4077 Results.push_back(Tmp1);
4080 SDValue Chain = Node->getOperand(0); // Get the chain.
4081 SDValue Ptr = Node->getOperand(1); // Get the pointer.
4084 if (OVT.isVector()) {
4085 TruncOp = ISD::BITCAST;
4087 assert(OVT.isInteger()
4088 && "VAARG promotion is supported only for vectors or integer types");
4089 TruncOp = ISD::TRUNCATE;
4092 // Perform the larger operation, then convert back
4093 Tmp1 = DAG.getVAArg(NVT, dl, Chain, Ptr, Node->getOperand(2),
4094 Node->getConstantOperandVal(3));
4095 Chain = Tmp1.getValue(1);
4097 Tmp2 = DAG.getNode(TruncOp, dl, OVT, Tmp1);
4099 // Modified the chain result - switch anything that used the old chain to
4101 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp2);
4102 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
4109 unsigned ExtOp, TruncOp;
4110 if (OVT.isVector()) {
4111 ExtOp = ISD::BITCAST;
4112 TruncOp = ISD::BITCAST;
4114 assert(OVT.isInteger() && "Cannot promote logic operation");
4115 ExtOp = ISD::ANY_EXTEND;
4116 TruncOp = ISD::TRUNCATE;
4118 // Promote each of the values to the new type.
4119 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4120 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4121 // Perform the larger operation, then convert back
4122 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4123 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
4127 unsigned ExtOp, TruncOp;
4128 if (Node->getValueType(0).isVector() ||
4129 Node->getValueType(0).getSizeInBits() == NVT.getSizeInBits()) {
4130 ExtOp = ISD::BITCAST;
4131 TruncOp = ISD::BITCAST;
4132 } else if (Node->getValueType(0).isInteger()) {
4133 ExtOp = ISD::ANY_EXTEND;
4134 TruncOp = ISD::TRUNCATE;
4136 ExtOp = ISD::FP_EXTEND;
4137 TruncOp = ISD::FP_ROUND;
4139 Tmp1 = Node->getOperand(0);
4140 // Promote each of the values to the new type.
4141 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4142 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
4143 // Perform the larger operation, then round down.
4144 Tmp1 = DAG.getSelect(dl, NVT, Tmp1, Tmp2, Tmp3);
4145 if (TruncOp != ISD::FP_ROUND)
4146 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
4148 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
4149 DAG.getIntPtrConstant(0));
4150 Results.push_back(Tmp1);
4153 case ISD::VECTOR_SHUFFLE: {
4154 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
4156 // Cast the two input vectors.
4157 Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
4158 Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
4160 // Convert the shuffle mask to the right # elements.
4161 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
4162 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
4163 Results.push_back(Tmp1);
4167 unsigned ExtOp = ISD::FP_EXTEND;
4168 if (NVT.isInteger()) {
4169 ISD::CondCode CCCode =
4170 cast<CondCodeSDNode>(Node->getOperand(2))->get();
4171 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4173 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4174 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4175 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
4176 Tmp1, Tmp2, Node->getOperand(2)));
4182 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4183 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
4184 Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4185 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4186 Tmp3, DAG.getIntPtrConstant(0)));
4193 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4194 Tmp2 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4195 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4196 Tmp2, DAG.getIntPtrConstant(0)));
4201 // Replace the original node with the legalized result.
4202 if (!Results.empty())
4203 ReplaceNode(Node, Results.data());
4206 // SelectionDAG::Legalize - This is the entry point for the file.
4208 void SelectionDAG::Legalize() {
4209 /// run - This is the main entry point to this class.
4211 SelectionDAGLegalize(*this).LegalizeDAG();