1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CallingConv.h"
15 #include "llvm/Constants.h"
16 #include "llvm/DebugInfo.h"
17 #include "llvm/DerivedTypes.h"
18 #include "llvm/LLVMContext.h"
19 #include "llvm/CodeGen/Analysis.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineJumpTableInfo.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/Target/TargetFrameLowering.h"
24 #include "llvm/Target/TargetLowering.h"
25 #include "llvm/Target/TargetData.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/MathExtras.h"
30 #include "llvm/Support/raw_ostream.h"
31 #include "llvm/ADT/DenseMap.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/SmallPtrSet.h"
36 //===----------------------------------------------------------------------===//
37 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
38 /// hacks on it until the target machine can handle it. This involves
39 /// eliminating value sizes the machine cannot handle (promoting small sizes to
40 /// large sizes or splitting up large values into small values) as well as
41 /// eliminating operations the machine cannot handle.
43 /// This code also does a small amount of optimization and recognition of idioms
44 /// as part of its processing. For example, if a target does not support a
45 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
46 /// will attempt merge setcc and brc instructions into brcc's.
49 class SelectionDAGLegalize : public SelectionDAG::DAGUpdateListener {
50 const TargetMachine &TM;
51 const TargetLowering &TLI;
54 /// LegalizePosition - The iterator for walking through the node list.
55 SelectionDAG::allnodes_iterator LegalizePosition;
57 /// LegalizedNodes - The set of nodes which have already been legalized.
58 SmallPtrSet<SDNode *, 16> LegalizedNodes;
60 // Libcall insertion helpers.
63 explicit SelectionDAGLegalize(SelectionDAG &DAG);
68 /// LegalizeOp - Legalizes the given operation.
69 void LegalizeOp(SDNode *Node);
71 SDValue OptimizeFloatStore(StoreSDNode *ST);
73 void LegalizeLoadOps(SDNode *Node);
74 void LegalizeStoreOps(SDNode *Node);
76 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
77 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
78 /// is necessary to spill the vector being inserted into to memory, perform
79 /// the insert there, and then read the result back.
80 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
81 SDValue Idx, DebugLoc dl);
82 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
83 SDValue Idx, DebugLoc dl);
85 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
86 /// performs the same shuffe in terms of order or result bytes, but on a type
87 /// whose vector element type is narrower than the original shuffle type.
88 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
89 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
90 SDValue N1, SDValue N2,
91 ArrayRef<int> Mask) const;
93 void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
96 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
97 SDValue ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops,
98 unsigned NumOps, bool isSigned, DebugLoc dl);
100 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
101 SDNode *Node, bool isSigned);
102 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
103 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
104 RTLIB::Libcall Call_PPCF128);
105 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
106 RTLIB::Libcall Call_I8,
107 RTLIB::Libcall Call_I16,
108 RTLIB::Libcall Call_I32,
109 RTLIB::Libcall Call_I64,
110 RTLIB::Libcall Call_I128);
111 void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
113 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl);
114 SDValue ExpandBUILD_VECTOR(SDNode *Node);
115 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
116 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
117 SmallVectorImpl<SDValue> &Results);
118 SDValue ExpandFCOPYSIGN(SDNode *Node);
119 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
121 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
123 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
126 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl);
127 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl);
129 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
130 SDValue ExpandInsertToVectorThroughStack(SDValue Op);
131 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
133 SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP);
135 std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node);
137 void ExpandNode(SDNode *Node);
138 void PromoteNode(SDNode *Node);
140 void ForgetNode(SDNode *N) {
141 LegalizedNodes.erase(N);
142 if (LegalizePosition == SelectionDAG::allnodes_iterator(N))
147 // DAGUpdateListener implementation.
148 virtual void NodeDeleted(SDNode *N, SDNode *E) {
151 virtual void NodeUpdated(SDNode *N) {}
153 // Node replacement helpers
154 void ReplacedNode(SDNode *N) {
155 if (N->use_empty()) {
156 DAG.RemoveDeadNode(N);
161 void ReplaceNode(SDNode *Old, SDNode *New) {
162 DAG.ReplaceAllUsesWith(Old, New);
165 void ReplaceNode(SDValue Old, SDValue New) {
166 DAG.ReplaceAllUsesWith(Old, New);
167 ReplacedNode(Old.getNode());
169 void ReplaceNode(SDNode *Old, const SDValue *New) {
170 DAG.ReplaceAllUsesWith(Old, New);
176 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
177 /// performs the same shuffe in terms of order or result bytes, but on a type
178 /// whose vector element type is narrower than the original shuffle type.
179 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
181 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
182 SDValue N1, SDValue N2,
183 ArrayRef<int> Mask) const {
184 unsigned NumMaskElts = VT.getVectorNumElements();
185 unsigned NumDestElts = NVT.getVectorNumElements();
186 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
188 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
190 if (NumEltsGrowth == 1)
191 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
193 SmallVector<int, 8> NewMask;
194 for (unsigned i = 0; i != NumMaskElts; ++i) {
196 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
198 NewMask.push_back(-1);
200 NewMask.push_back(Idx * NumEltsGrowth + j);
203 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
204 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
205 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
208 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
209 : SelectionDAG::DAGUpdateListener(dag),
210 TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()),
214 void SelectionDAGLegalize::LegalizeDAG() {
215 DAG.AssignTopologicalOrder();
217 // Visit all the nodes. We start in topological order, so that we see
218 // nodes with their original operands intact. Legalization can produce
219 // new nodes which may themselves need to be legalized. Iterate until all
220 // nodes have been legalized.
222 bool AnyLegalized = false;
223 for (LegalizePosition = DAG.allnodes_end();
224 LegalizePosition != DAG.allnodes_begin(); ) {
227 SDNode *N = LegalizePosition;
228 if (LegalizedNodes.insert(N)) {
238 // Remove dead nodes now.
239 DAG.RemoveDeadNodes();
242 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
243 /// a load from the constant pool.
245 SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) {
247 DebugLoc dl = CFP->getDebugLoc();
249 // If a FP immediate is precise when represented as a float and if the
250 // target can do an extending load from float to double, we put it into
251 // the constant pool as a float, even if it's is statically typed as a
252 // double. This shrinks FP constants and canonicalizes them for targets where
253 // an FP extending load is the same cost as a normal load (such as on the x87
254 // fp stack or PPC FP unit).
255 EVT VT = CFP->getValueType(0);
256 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
258 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
259 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
260 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
265 while (SVT != MVT::f32) {
266 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
267 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) &&
268 // Only do this if the target has a native EXTLOAD instruction from
270 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
271 TLI.ShouldShrinkFPConstant(OrigVT)) {
272 Type *SType = SVT.getTypeForEVT(*DAG.getContext());
273 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
279 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
280 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
283 DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT,
285 CPIdx, MachinePointerInfo::getConstantPool(),
286 VT, false, false, Alignment);
290 DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
291 MachinePointerInfo::getConstantPool(), false, false, false,
296 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
297 static void ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
298 const TargetLowering &TLI,
299 SelectionDAGLegalize *DAGLegalize) {
300 assert(ST->getAddressingMode() == ISD::UNINDEXED &&
301 "unaligned indexed stores not implemented!");
302 SDValue Chain = ST->getChain();
303 SDValue Ptr = ST->getBasePtr();
304 SDValue Val = ST->getValue();
305 EVT VT = Val.getValueType();
306 int Alignment = ST->getAlignment();
307 DebugLoc dl = ST->getDebugLoc();
308 if (ST->getMemoryVT().isFloatingPoint() ||
309 ST->getMemoryVT().isVector()) {
310 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
311 if (TLI.isTypeLegal(intVT)) {
312 // Expand to a bitconvert of the value to the integer type of the
313 // same size, then a (misaligned) int store.
314 // FIXME: Does not handle truncating floating point stores!
315 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
316 Result = DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
317 ST->isVolatile(), ST->isNonTemporal(), Alignment);
318 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
321 // Do a (aligned) store to a stack slot, then copy from the stack slot
322 // to the final destination using (unaligned) integer loads and stores.
323 EVT StoredVT = ST->getMemoryVT();
325 TLI.getRegisterType(*DAG.getContext(),
326 EVT::getIntegerVT(*DAG.getContext(),
327 StoredVT.getSizeInBits()));
328 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
329 unsigned RegBytes = RegVT.getSizeInBits() / 8;
330 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
332 // Make sure the stack slot is also aligned for the register type.
333 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
335 // Perform the original store, only redirected to the stack slot.
336 SDValue Store = DAG.getTruncStore(Chain, dl,
337 Val, StackPtr, MachinePointerInfo(),
338 StoredVT, false, false, 0);
339 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
340 SmallVector<SDValue, 8> Stores;
343 // Do all but one copies using the full register width.
344 for (unsigned i = 1; i < NumRegs; i++) {
345 // Load one integer register's worth from the stack slot.
346 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr,
347 MachinePointerInfo(),
348 false, false, false, 0);
349 // Store it to the final location. Remember the store.
350 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
351 ST->getPointerInfo().getWithOffset(Offset),
352 ST->isVolatile(), ST->isNonTemporal(),
353 MinAlign(ST->getAlignment(), Offset)));
354 // Increment the pointers.
356 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
358 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
361 // The last store may be partial. Do a truncating store. On big-endian
362 // machines this requires an extending load from the stack slot to ensure
363 // that the bits are in the right place.
364 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
365 8 * (StoredBytes - Offset));
367 // Load from the stack slot.
368 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
369 MachinePointerInfo(),
370 MemVT, false, false, 0);
372 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
374 .getWithOffset(Offset),
375 MemVT, ST->isVolatile(),
377 MinAlign(ST->getAlignment(), Offset)));
378 // The order of the stores doesn't matter - say it with a TokenFactor.
380 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
382 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
385 assert(ST->getMemoryVT().isInteger() &&
386 !ST->getMemoryVT().isVector() &&
387 "Unaligned store of unknown type.");
388 // Get the half-size VT
389 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext());
390 int NumBits = NewStoredVT.getSizeInBits();
391 int IncrementSize = NumBits / 8;
393 // Divide the stored value in two parts.
394 SDValue ShiftAmount = DAG.getConstant(NumBits,
395 TLI.getShiftAmountTy(Val.getValueType()));
397 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
399 // Store the two parts
400 SDValue Store1, Store2;
401 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
402 ST->getPointerInfo(), NewStoredVT,
403 ST->isVolatile(), ST->isNonTemporal(), Alignment);
404 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
405 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
406 Alignment = MinAlign(Alignment, IncrementSize);
407 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
408 ST->getPointerInfo().getWithOffset(IncrementSize),
409 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(),
413 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
414 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
417 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
419 ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
420 const TargetLowering &TLI,
421 SDValue &ValResult, SDValue &ChainResult) {
422 assert(LD->getAddressingMode() == ISD::UNINDEXED &&
423 "unaligned indexed loads not implemented!");
424 SDValue Chain = LD->getChain();
425 SDValue Ptr = LD->getBasePtr();
426 EVT VT = LD->getValueType(0);
427 EVT LoadedVT = LD->getMemoryVT();
428 DebugLoc dl = LD->getDebugLoc();
429 if (VT.isFloatingPoint() || VT.isVector()) {
430 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
431 if (TLI.isTypeLegal(intVT)) {
432 // Expand to a (misaligned) integer load of the same size,
433 // then bitconvert to floating point or vector.
434 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getPointerInfo(),
437 LD->isInvariant(), LD->getAlignment());
438 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad);
439 if (VT.isFloatingPoint() && LoadedVT != VT)
440 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result);
447 // Copy the value to a (aligned) stack slot using (unaligned) integer
448 // loads and stores, then do a (aligned) load from the stack slot.
449 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
450 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
451 unsigned RegBytes = RegVT.getSizeInBits() / 8;
452 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
454 // Make sure the stack slot is also aligned for the register type.
455 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
457 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
458 SmallVector<SDValue, 8> Stores;
459 SDValue StackPtr = StackBase;
462 // Do all but one copies using the full register width.
463 for (unsigned i = 1; i < NumRegs; i++) {
464 // Load one integer register's worth from the original location.
465 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr,
466 LD->getPointerInfo().getWithOffset(Offset),
467 LD->isVolatile(), LD->isNonTemporal(),
469 MinAlign(LD->getAlignment(), Offset));
470 // Follow the load with a store to the stack slot. Remember the store.
471 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
472 MachinePointerInfo(), false, false, 0));
473 // Increment the pointers.
475 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
476 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
480 // The last copy may be partial. Do an extending load.
481 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
482 8 * (LoadedBytes - Offset));
483 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
484 LD->getPointerInfo().getWithOffset(Offset),
485 MemVT, LD->isVolatile(),
487 MinAlign(LD->getAlignment(), Offset));
488 // Follow the load with a store to the stack slot. Remember the store.
489 // On big-endian machines this requires a truncating store to ensure
490 // that the bits end up in the right place.
491 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
492 MachinePointerInfo(), MemVT,
495 // The order of the stores doesn't matter - say it with a TokenFactor.
496 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
499 // Finally, perform the original load only redirected to the stack slot.
500 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
501 MachinePointerInfo(), LoadedVT, false, false, 0);
503 // Callers expect a MERGE_VALUES node.
508 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
509 "Unaligned load of unsupported type.");
511 // Compute the new VT that is half the size of the old one. This is an
513 unsigned NumBits = LoadedVT.getSizeInBits();
515 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
518 unsigned Alignment = LD->getAlignment();
519 unsigned IncrementSize = NumBits / 8;
520 ISD::LoadExtType HiExtType = LD->getExtensionType();
522 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
523 if (HiExtType == ISD::NON_EXTLOAD)
524 HiExtType = ISD::ZEXTLOAD;
526 // Load the value in two parts
528 if (TLI.isLittleEndian()) {
529 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
530 NewLoadedVT, LD->isVolatile(),
531 LD->isNonTemporal(), Alignment);
532 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
533 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
534 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr,
535 LD->getPointerInfo().getWithOffset(IncrementSize),
536 NewLoadedVT, LD->isVolatile(),
537 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
539 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(),
540 NewLoadedVT, LD->isVolatile(),
541 LD->isNonTemporal(), Alignment);
542 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
543 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
544 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
545 LD->getPointerInfo().getWithOffset(IncrementSize),
546 NewLoadedVT, LD->isVolatile(),
547 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
550 // aggregate the two parts
551 SDValue ShiftAmount = DAG.getConstant(NumBits,
552 TLI.getShiftAmountTy(Hi.getValueType()));
553 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
554 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
556 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
563 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
564 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
565 /// is necessary to spill the vector being inserted into to memory, perform
566 /// the insert there, and then read the result back.
567 SDValue SelectionDAGLegalize::
568 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
574 // If the target doesn't support this, we have to spill the input vector
575 // to a temporary stack slot, update the element, then reload it. This is
576 // badness. We could also load the value into a vector register (either
577 // with a "move to register" or "extload into register" instruction, then
578 // permute it into place, if the idx is a constant and if the idx is
579 // supported by the target.
580 EVT VT = Tmp1.getValueType();
581 EVT EltVT = VT.getVectorElementType();
582 EVT IdxVT = Tmp3.getValueType();
583 EVT PtrVT = TLI.getPointerTy();
584 SDValue StackPtr = DAG.CreateStackTemporary(VT);
586 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
589 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
590 MachinePointerInfo::getFixedStack(SPFI),
593 // Truncate or zero extend offset to target pointer type.
594 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
595 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
596 // Add the offset to the index.
597 unsigned EltSize = EltVT.getSizeInBits()/8;
598 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
599 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
600 // Store the scalar value.
601 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT,
603 // Load the updated vector.
604 return DAG.getLoad(VT, dl, Ch, StackPtr,
605 MachinePointerInfo::getFixedStack(SPFI), false, false,
610 SDValue SelectionDAGLegalize::
611 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) {
612 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
613 // SCALAR_TO_VECTOR requires that the type of the value being inserted
614 // match the element type of the vector being created, except for
615 // integers in which case the inserted value can be over width.
616 EVT EltVT = Vec.getValueType().getVectorElementType();
617 if (Val.getValueType() == EltVT ||
618 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
619 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
620 Vec.getValueType(), Val);
622 unsigned NumElts = Vec.getValueType().getVectorNumElements();
623 // We generate a shuffle of InVec and ScVec, so the shuffle mask
624 // should be 0,1,2,3,4,5... with the appropriate element replaced with
626 SmallVector<int, 8> ShufOps;
627 for (unsigned i = 0; i != NumElts; ++i)
628 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
630 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
634 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
637 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
638 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
639 // FIXME: We shouldn't do this for TargetConstantFP's.
640 // FIXME: move this to the DAG Combiner! Note that we can't regress due
641 // to phase ordering between legalized code and the dag combiner. This
642 // probably means that we need to integrate dag combiner and legalizer
644 // We generally can't do this one for long doubles.
645 SDValue Tmp1 = ST->getChain();
646 SDValue Tmp2 = ST->getBasePtr();
648 unsigned Alignment = ST->getAlignment();
649 bool isVolatile = ST->isVolatile();
650 bool isNonTemporal = ST->isNonTemporal();
651 DebugLoc dl = ST->getDebugLoc();
652 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
653 if (CFP->getValueType(0) == MVT::f32 &&
654 TLI.isTypeLegal(MVT::i32)) {
655 Tmp3 = DAG.getConstant(CFP->getValueAPF().
656 bitcastToAPInt().zextOrTrunc(32),
658 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
659 isVolatile, isNonTemporal, Alignment);
662 if (CFP->getValueType(0) == MVT::f64) {
663 // If this target supports 64-bit registers, do a single 64-bit store.
664 if (TLI.isTypeLegal(MVT::i64)) {
665 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
666 zextOrTrunc(64), MVT::i64);
667 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
668 isVolatile, isNonTemporal, Alignment);
671 if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) {
672 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
673 // stores. If the target supports neither 32- nor 64-bits, this
674 // xform is certainly not worth it.
675 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
676 SDValue Lo = DAG.getConstant(IntVal.trunc(32), MVT::i32);
677 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
678 if (TLI.isBigEndian()) std::swap(Lo, Hi);
680 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getPointerInfo(), isVolatile,
681 isNonTemporal, Alignment);
682 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
683 DAG.getIntPtrConstant(4));
684 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2,
685 ST->getPointerInfo().getWithOffset(4),
686 isVolatile, isNonTemporal, MinAlign(Alignment, 4U));
688 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
692 return SDValue(0, 0);
695 void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
696 StoreSDNode *ST = cast<StoreSDNode>(Node);
697 SDValue Tmp1 = ST->getChain();
698 SDValue Tmp2 = ST->getBasePtr();
699 DebugLoc dl = Node->getDebugLoc();
701 unsigned Alignment = ST->getAlignment();
702 bool isVolatile = ST->isVolatile();
703 bool isNonTemporal = ST->isNonTemporal();
705 if (!ST->isTruncatingStore()) {
706 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
707 ReplaceNode(ST, OptStore);
712 SDValue Tmp3 = ST->getValue();
713 EVT VT = Tmp3.getValueType();
714 switch (TLI.getOperationAction(ISD::STORE, VT)) {
715 default: llvm_unreachable("This action is not supported yet!");
716 case TargetLowering::Legal:
717 // If this is an unaligned store and the target doesn't support it,
719 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
720 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
721 unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty);
722 if (ST->getAlignment() < ABIAlignment)
723 ExpandUnalignedStore(cast<StoreSDNode>(Node),
727 case TargetLowering::Custom:
728 Tmp1 = TLI.LowerOperation(SDValue(Node, 0), DAG);
730 ReplaceNode(SDValue(Node, 0), Tmp1);
732 case TargetLowering::Promote: {
733 assert(VT.isVector() && "Unknown legal promote case!");
734 Tmp3 = DAG.getNode(ISD::BITCAST, dl,
735 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
737 DAG.getStore(Tmp1, dl, Tmp3, Tmp2,
738 ST->getPointerInfo(), isVolatile,
739 isNonTemporal, Alignment);
740 ReplaceNode(SDValue(Node, 0), Result);
747 SDValue Tmp3 = ST->getValue();
749 EVT StVT = ST->getMemoryVT();
750 unsigned StWidth = StVT.getSizeInBits();
752 if (StWidth != StVT.getStoreSizeInBits()) {
753 // Promote to a byte-sized store with upper bits zero if not
754 // storing an integral number of bytes. For example, promote
755 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
756 EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
757 StVT.getStoreSizeInBits());
758 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT);
760 DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
761 NVT, isVolatile, isNonTemporal, Alignment);
762 ReplaceNode(SDValue(Node, 0), Result);
763 } else if (StWidth & (StWidth - 1)) {
764 // If not storing a power-of-2 number of bits, expand as two stores.
765 assert(!StVT.isVector() && "Unsupported truncstore!");
766 unsigned RoundWidth = 1 << Log2_32(StWidth);
767 assert(RoundWidth < StWidth);
768 unsigned ExtraWidth = StWidth - RoundWidth;
769 assert(ExtraWidth < RoundWidth);
770 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
771 "Store size not an integral number of bytes!");
772 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
773 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
775 unsigned IncrementSize;
777 if (TLI.isLittleEndian()) {
778 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
779 // Store the bottom RoundWidth bits.
780 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
782 isVolatile, isNonTemporal, Alignment);
784 // Store the remaining ExtraWidth bits.
785 IncrementSize = RoundWidth / 8;
786 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
787 DAG.getIntPtrConstant(IncrementSize));
788 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
789 DAG.getConstant(RoundWidth,
790 TLI.getShiftAmountTy(Tmp3.getValueType())));
791 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2,
792 ST->getPointerInfo().getWithOffset(IncrementSize),
793 ExtraVT, isVolatile, isNonTemporal,
794 MinAlign(Alignment, IncrementSize));
796 // Big endian - avoid unaligned stores.
797 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
798 // Store the top RoundWidth bits.
799 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
800 DAG.getConstant(ExtraWidth,
801 TLI.getShiftAmountTy(Tmp3.getValueType())));
802 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getPointerInfo(),
803 RoundVT, isVolatile, isNonTemporal, Alignment);
805 // Store the remaining ExtraWidth bits.
806 IncrementSize = RoundWidth / 8;
807 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
808 DAG.getIntPtrConstant(IncrementSize));
809 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2,
810 ST->getPointerInfo().getWithOffset(IncrementSize),
811 ExtraVT, isVolatile, isNonTemporal,
812 MinAlign(Alignment, IncrementSize));
815 // The order of the stores doesn't matter.
816 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
817 ReplaceNode(SDValue(Node, 0), Result);
819 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
820 default: llvm_unreachable("This action is not supported yet!");
821 case TargetLowering::Legal:
822 // If this is an unaligned store and the target doesn't support it,
824 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
825 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
826 unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty);
827 if (ST->getAlignment() < ABIAlignment)
828 ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this);
831 case TargetLowering::Custom:
832 Tmp1 = TLI.LowerOperation(SDValue(Node, 0), DAG);
834 ReplaceNode(SDValue(Node, 0), Tmp1);
836 case TargetLowering::Expand:
837 assert(!StVT.isVector() &&
838 "Vector Stores are handled in LegalizeVectorOps");
840 // TRUNCSTORE:i16 i32 -> STORE i16
841 assert(TLI.isTypeLegal(StVT) && "Do not know how to expand this store!");
842 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3);
844 DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
845 isVolatile, isNonTemporal, Alignment);
846 ReplaceNode(SDValue(Node, 0), Result);
853 void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
854 LoadSDNode *LD = cast<LoadSDNode>(Node);
855 SDValue Tmp1 = LD->getChain(); // Legalize the chain.
856 SDValue Tmp2 = LD->getBasePtr(); // Legalize the base pointer.
857 DebugLoc dl = Node->getDebugLoc();
859 ISD::LoadExtType ExtType = LD->getExtensionType();
860 if (ExtType == ISD::NON_EXTLOAD) {
861 EVT VT = Node->getValueType(0);
862 SDValue Tmp3 = SDValue(Node, 0);
863 SDValue Tmp4 = SDValue(Node, 1);
865 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
866 default: llvm_unreachable("This action is not supported yet!");
867 case TargetLowering::Legal:
868 // If this is an unaligned load and the target doesn't support it,
870 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
871 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
872 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
873 if (LD->getAlignment() < ABIAlignment){
874 ExpandUnalignedLoad(cast<LoadSDNode>(Node),
875 DAG, TLI, Tmp3, Tmp4);
879 case TargetLowering::Custom:
880 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
881 if (Tmp1.getNode()) {
883 Tmp4 = Tmp1.getValue(1);
886 case TargetLowering::Promote: {
887 // Only promote a load of vector type to another.
888 assert(VT.isVector() && "Cannot promote this load!");
889 // Change base type to a different vector type.
890 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
892 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getPointerInfo(),
893 LD->isVolatile(), LD->isNonTemporal(),
894 LD->isInvariant(), LD->getAlignment());
895 Tmp3 = DAG.getNode(ISD::BITCAST, dl, VT, Tmp1);
896 Tmp4 = Tmp1.getValue(1);
900 if (Tmp4.getNode() != Node) {
901 assert(Tmp3.getNode() != Node && "Load must be completely replaced");
902 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp3);
903 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Tmp4);
909 EVT SrcVT = LD->getMemoryVT();
910 unsigned SrcWidth = SrcVT.getSizeInBits();
911 unsigned Alignment = LD->getAlignment();
912 bool isVolatile = LD->isVolatile();
913 bool isNonTemporal = LD->isNonTemporal();
915 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
916 // Some targets pretend to have an i1 loading operation, and actually
917 // load an i8. This trick is correct for ZEXTLOAD because the top 7
918 // bits are guaranteed to be zero; it helps the optimizers understand
919 // that these bits are zero. It is also useful for EXTLOAD, since it
920 // tells the optimizers that those bits are undefined. It would be
921 // nice to have an effective generic way of getting these benefits...
922 // Until such a way is found, don't insist on promoting i1 here.
924 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
925 // Promote to a byte-sized load if not loading an integral number of
926 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
927 unsigned NewWidth = SrcVT.getStoreSizeInBits();
928 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
931 // The extra bits are guaranteed to be zero, since we stored them that
932 // way. A zext load from NVT thus automatically gives zext from SrcVT.
934 ISD::LoadExtType NewExtType =
935 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
938 DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
939 Tmp1, Tmp2, LD->getPointerInfo(),
940 NVT, isVolatile, isNonTemporal, Alignment);
942 Ch = Result.getValue(1); // The chain.
944 if (ExtType == ISD::SEXTLOAD)
945 // Having the top bits zero doesn't help when sign extending.
946 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
947 Result.getValueType(),
948 Result, DAG.getValueType(SrcVT));
949 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
950 // All the top bits are guaranteed to be zero - inform the optimizers.
951 Result = DAG.getNode(ISD::AssertZext, dl,
952 Result.getValueType(), Result,
953 DAG.getValueType(SrcVT));
957 } else if (SrcWidth & (SrcWidth - 1)) {
958 // If not loading a power-of-2 number of bits, expand as two loads.
959 assert(!SrcVT.isVector() && "Unsupported extload!");
960 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
961 assert(RoundWidth < SrcWidth);
962 unsigned ExtraWidth = SrcWidth - RoundWidth;
963 assert(ExtraWidth < RoundWidth);
964 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
965 "Load size not an integral number of bytes!");
966 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
967 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
969 unsigned IncrementSize;
971 if (TLI.isLittleEndian()) {
972 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
973 // Load the bottom RoundWidth bits.
974 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0),
976 LD->getPointerInfo(), RoundVT, isVolatile,
977 isNonTemporal, Alignment);
979 // Load the remaining ExtraWidth bits.
980 IncrementSize = RoundWidth / 8;
981 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
982 DAG.getIntPtrConstant(IncrementSize));
983 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
984 LD->getPointerInfo().getWithOffset(IncrementSize),
985 ExtraVT, isVolatile, isNonTemporal,
986 MinAlign(Alignment, IncrementSize));
988 // Build a factor node to remember that this load is independent of
990 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
993 // Move the top bits to the right place.
994 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
995 DAG.getConstant(RoundWidth,
996 TLI.getShiftAmountTy(Hi.getValueType())));
998 // Join the hi and lo parts.
999 Tmp1 = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1001 // Big endian - avoid unaligned loads.
1002 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1003 // Load the top RoundWidth bits.
1004 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
1005 LD->getPointerInfo(), RoundVT, isVolatile,
1006 isNonTemporal, Alignment);
1008 // Load the remaining ExtraWidth bits.
1009 IncrementSize = RoundWidth / 8;
1010 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1011 DAG.getIntPtrConstant(IncrementSize));
1012 Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
1013 dl, Node->getValueType(0), Tmp1, Tmp2,
1014 LD->getPointerInfo().getWithOffset(IncrementSize),
1015 ExtraVT, isVolatile, isNonTemporal,
1016 MinAlign(Alignment, IncrementSize));
1018 // Build a factor node to remember that this load is independent of
1020 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1023 // Move the top bits to the right place.
1024 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1025 DAG.getConstant(ExtraWidth,
1026 TLI.getShiftAmountTy(Hi.getValueType())));
1028 // Join the hi and lo parts.
1029 Tmp1 = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1034 bool isCustom = false;
1035 switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
1036 default: llvm_unreachable("This action is not supported yet!");
1037 case TargetLowering::Custom:
1040 case TargetLowering::Legal:
1041 Tmp1 = SDValue(Node, 0);
1042 Tmp2 = SDValue(Node, 1);
1045 SDValue Tmp3 = TLI.LowerOperation(SDValue(Node, 0), DAG);
1046 if (Tmp3.getNode()) {
1048 Tmp2 = Tmp3.getValue(1);
1051 // If this is an unaligned load and the target doesn't support it,
1053 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
1055 LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1056 unsigned ABIAlignment =
1057 TLI.getTargetData()->getABITypeAlignment(Ty);
1058 if (LD->getAlignment() < ABIAlignment){
1059 ExpandUnalignedLoad(cast<LoadSDNode>(Node),
1060 DAG, TLI, Tmp1, Tmp2);
1065 case TargetLowering::Expand:
1066 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) && TLI.isTypeLegal(SrcVT)) {
1067 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2,
1068 LD->getPointerInfo(),
1069 LD->isVolatile(), LD->isNonTemporal(),
1070 LD->isInvariant(), LD->getAlignment());
1074 ExtendOp = (SrcVT.isFloatingPoint() ?
1075 ISD::FP_EXTEND : ISD::ANY_EXTEND);
1077 case ISD::SEXTLOAD: ExtendOp = ISD::SIGN_EXTEND; break;
1078 case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break;
1079 default: llvm_unreachable("Unexpected extend load type!");
1081 Tmp1 = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
1082 Tmp2 = Load.getValue(1);
1086 assert(!SrcVT.isVector() &&
1087 "Vector Loads are handled in LegalizeVectorOps");
1089 // FIXME: This does not work for vectors on most targets. Sign- and
1090 // zero-extend operations are currently folded into extending loads,
1091 // whether they are legal or not, and then we end up here without any
1092 // support for legalizing them.
1093 assert(ExtType != ISD::EXTLOAD &&
1094 "EXTLOAD should always be supported!");
1095 // Turn the unsupported load into an EXTLOAD followed by an explicit
1096 // zero/sign extend inreg.
1097 SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
1098 Tmp1, Tmp2, LD->getPointerInfo(), SrcVT,
1099 LD->isVolatile(), LD->isNonTemporal(),
1100 LD->getAlignment());
1102 if (ExtType == ISD::SEXTLOAD)
1103 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1104 Result.getValueType(),
1105 Result, DAG.getValueType(SrcVT));
1107 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType());
1109 Tmp2 = Result.getValue(1);
1114 // Since loads produce two values, make sure to remember that we legalized
1116 if (Tmp2.getNode() != Node) {
1117 assert(Tmp1.getNode() != Node && "Load must be completely replaced");
1118 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp1);
1119 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Tmp2);
1124 /// LegalizeOp - Return a legal replacement for the given operation, with
1125 /// all legal operands.
1126 void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
1127 if (Node->getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
1130 DebugLoc dl = Node->getDebugLoc();
1132 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1133 assert(TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) ==
1134 TargetLowering::TypeLegal &&
1135 "Unexpected illegal type!");
1137 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1138 assert((TLI.getTypeAction(*DAG.getContext(),
1139 Node->getOperand(i).getValueType()) ==
1140 TargetLowering::TypeLegal ||
1141 Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
1142 "Unexpected illegal type!");
1144 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
1146 // Figure out the correct action; the way to query this varies by opcode
1147 TargetLowering::LegalizeAction Action = TargetLowering::Legal;
1148 bool SimpleFinishLegalizing = true;
1149 switch (Node->getOpcode()) {
1150 case ISD::INTRINSIC_W_CHAIN:
1151 case ISD::INTRINSIC_WO_CHAIN:
1152 case ISD::INTRINSIC_VOID:
1153 case ISD::STACKSAVE:
1154 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1157 Action = TLI.getOperationAction(Node->getOpcode(),
1158 Node->getValueType(0));
1159 if (Action != TargetLowering::Promote)
1160 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1162 case ISD::SINT_TO_FP:
1163 case ISD::UINT_TO_FP:
1164 case ISD::EXTRACT_VECTOR_ELT:
1165 Action = TLI.getOperationAction(Node->getOpcode(),
1166 Node->getOperand(0).getValueType());
1168 case ISD::FP_ROUND_INREG:
1169 case ISD::SIGN_EXTEND_INREG: {
1170 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
1171 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
1174 case ISD::ATOMIC_STORE: {
1175 Action = TLI.getOperationAction(Node->getOpcode(),
1176 Node->getOperand(2).getValueType());
1179 case ISD::SELECT_CC:
1182 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
1183 Node->getOpcode() == ISD::SETCC ? 2 : 1;
1184 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
1185 EVT OpVT = Node->getOperand(CompareOperand).getValueType();
1186 ISD::CondCode CCCode =
1187 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
1188 Action = TLI.getCondCodeAction(CCCode, OpVT);
1189 if (Action == TargetLowering::Legal) {
1190 if (Node->getOpcode() == ISD::SELECT_CC)
1191 Action = TLI.getOperationAction(Node->getOpcode(),
1192 Node->getValueType(0));
1194 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
1200 // FIXME: Model these properly. LOAD and STORE are complicated, and
1201 // STORE expects the unlegalized operand in some cases.
1202 SimpleFinishLegalizing = false;
1204 case ISD::CALLSEQ_START:
1205 case ISD::CALLSEQ_END:
1206 // FIXME: This shouldn't be necessary. These nodes have special properties
1207 // dealing with the recursive nature of legalization. Removing this
1208 // special case should be done as part of making LegalizeDAG non-recursive.
1209 SimpleFinishLegalizing = false;
1211 case ISD::EXTRACT_ELEMENT:
1212 case ISD::FLT_ROUNDS_:
1220 case ISD::MERGE_VALUES:
1221 case ISD::EH_RETURN:
1222 case ISD::FRAME_TO_ARGS_OFFSET:
1223 case ISD::EH_SJLJ_SETJMP:
1224 case ISD::EH_SJLJ_LONGJMP:
1225 // These operations lie about being legal: when they claim to be legal,
1226 // they should actually be expanded.
1227 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1228 if (Action == TargetLowering::Legal)
1229 Action = TargetLowering::Expand;
1231 case ISD::INIT_TRAMPOLINE:
1232 case ISD::ADJUST_TRAMPOLINE:
1233 case ISD::FRAMEADDR:
1234 case ISD::RETURNADDR:
1235 // These operations lie about being legal: when they claim to be legal,
1236 // they should actually be custom-lowered.
1237 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1238 if (Action == TargetLowering::Legal)
1239 Action = TargetLowering::Custom;
1242 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1243 Action = TargetLowering::Legal;
1245 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1250 if (SimpleFinishLegalizing) {
1251 SDNode *NewNode = Node;
1252 switch (Node->getOpcode()) {
1259 // Legalizing shifts/rotates requires adjusting the shift amount
1260 // to the appropriate width.
1261 if (!Node->getOperand(1).getValueType().isVector()) {
1263 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1264 Node->getOperand(1));
1265 HandleSDNode Handle(SAO);
1266 LegalizeOp(SAO.getNode());
1267 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1271 case ISD::SRL_PARTS:
1272 case ISD::SRA_PARTS:
1273 case ISD::SHL_PARTS:
1274 // Legalizing shifts/rotates requires adjusting the shift amount
1275 // to the appropriate width.
1276 if (!Node->getOperand(2).getValueType().isVector()) {
1278 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1279 Node->getOperand(2));
1280 HandleSDNode Handle(SAO);
1281 LegalizeOp(SAO.getNode());
1282 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1283 Node->getOperand(1),
1289 if (NewNode != Node) {
1290 DAG.ReplaceAllUsesWith(Node, NewNode);
1291 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1292 DAG.TransferDbgValues(SDValue(Node, i), SDValue(NewNode, i));
1297 case TargetLowering::Legal:
1299 case TargetLowering::Custom:
1300 // FIXME: The handling for custom lowering with multiple results is
1302 Tmp1 = TLI.LowerOperation(SDValue(Node, 0), DAG);
1303 if (Tmp1.getNode()) {
1304 SmallVector<SDValue, 8> ResultVals;
1305 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
1307 ResultVals.push_back(Tmp1);
1309 ResultVals.push_back(Tmp1.getValue(i));
1311 if (Tmp1.getNode() != Node || Tmp1.getResNo() != 0) {
1312 DAG.ReplaceAllUsesWith(Node, ResultVals.data());
1313 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1314 DAG.TransferDbgValues(SDValue(Node, i), ResultVals[i]);
1321 case TargetLowering::Expand:
1324 case TargetLowering::Promote:
1330 switch (Node->getOpcode()) {
1337 llvm_unreachable("Do not know how to legalize this operator!");
1339 case ISD::CALLSEQ_START:
1340 case ISD::CALLSEQ_END:
1343 return LegalizeLoadOps(Node);
1346 return LegalizeStoreOps(Node);
1351 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1352 SDValue Vec = Op.getOperand(0);
1353 SDValue Idx = Op.getOperand(1);
1354 DebugLoc dl = Op.getDebugLoc();
1355 // Store the value to a temporary stack slot, then LOAD the returned part.
1356 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1357 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1358 MachinePointerInfo(), false, false, 0);
1360 // Add the offset to the index.
1362 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1363 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1364 DAG.getConstant(EltSize, Idx.getValueType()));
1366 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1367 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1369 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1371 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1373 if (Op.getValueType().isVector())
1374 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,MachinePointerInfo(),
1375 false, false, false, 0);
1376 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
1377 MachinePointerInfo(),
1378 Vec.getValueType().getVectorElementType(),
1382 SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
1383 assert(Op.getValueType().isVector() && "Non-vector insert subvector!");
1385 SDValue Vec = Op.getOperand(0);
1386 SDValue Part = Op.getOperand(1);
1387 SDValue Idx = Op.getOperand(2);
1388 DebugLoc dl = Op.getDebugLoc();
1390 // Store the value to a temporary stack slot, then LOAD the returned part.
1392 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1393 int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1394 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1396 // First store the whole vector.
1397 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo,
1400 // Then store the inserted part.
1402 // Add the offset to the index.
1404 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1406 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1407 DAG.getConstant(EltSize, Idx.getValueType()));
1409 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1410 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1412 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1414 SDValue SubStackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
1417 // Store the subvector.
1418 Ch = DAG.getStore(DAG.getEntryNode(), dl, Part, SubStackPtr,
1419 MachinePointerInfo(), false, false, 0);
1421 // Finally, load the updated vector.
1422 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo,
1423 false, false, false, 0);
1426 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1427 // We can't handle this case efficiently. Allocate a sufficiently
1428 // aligned object on the stack, store each element into it, then load
1429 // the result as a vector.
1430 // Create the stack frame object.
1431 EVT VT = Node->getValueType(0);
1432 EVT EltVT = VT.getVectorElementType();
1433 DebugLoc dl = Node->getDebugLoc();
1434 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1435 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1436 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1438 // Emit a store of each element to the stack slot.
1439 SmallVector<SDValue, 8> Stores;
1440 unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1441 // Store (in the right endianness) the elements to memory.
1442 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1443 // Ignore undef elements.
1444 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1446 unsigned Offset = TypeByteSize*i;
1448 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
1449 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1451 // If the destination vector element type is narrower than the source
1452 // element type, only store the bits necessary.
1453 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1454 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1455 Node->getOperand(i), Idx,
1456 PtrInfo.getWithOffset(Offset),
1457 EltVT, false, false, 0));
1459 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
1460 Node->getOperand(i), Idx,
1461 PtrInfo.getWithOffset(Offset),
1466 if (!Stores.empty()) // Not all undef elements?
1467 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1468 &Stores[0], Stores.size());
1470 StoreChain = DAG.getEntryNode();
1472 // Result is a load from the stack slot.
1473 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo,
1474 false, false, false, 0);
1477 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
1478 DebugLoc dl = Node->getDebugLoc();
1479 SDValue Tmp1 = Node->getOperand(0);
1480 SDValue Tmp2 = Node->getOperand(1);
1482 // Get the sign bit of the RHS. First obtain a value that has the same
1483 // sign as the sign bit, i.e. negative if and only if the sign bit is 1.
1485 EVT FloatVT = Tmp2.getValueType();
1486 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits());
1487 if (TLI.isTypeLegal(IVT)) {
1488 // Convert to an integer with the same sign bit.
1489 SignBit = DAG.getNode(ISD::BITCAST, dl, IVT, Tmp2);
1491 // Store the float to memory, then load the sign part out as an integer.
1492 MVT LoadTy = TLI.getPointerTy();
1493 // First create a temporary that is aligned for both the load and store.
1494 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1495 // Then store the float to it.
1497 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, MachinePointerInfo(),
1499 if (TLI.isBigEndian()) {
1500 assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1501 // Load out a legal integer with the same sign bit as the float.
1502 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, MachinePointerInfo(),
1503 false, false, false, 0);
1504 } else { // Little endian
1505 SDValue LoadPtr = StackPtr;
1506 // The float may be wider than the integer we are going to load. Advance
1507 // the pointer so that the loaded integer will contain the sign bit.
1508 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits();
1509 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8;
1510 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(),
1511 LoadPtr, DAG.getIntPtrConstant(ByteOffset));
1512 // Load a legal integer containing the sign bit.
1513 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(),
1514 false, false, false, 0);
1515 // Move the sign bit to the top bit of the loaded integer.
1516 unsigned BitShift = LoadTy.getSizeInBits() -
1517 (FloatVT.getSizeInBits() - 8 * ByteOffset);
1518 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?");
1520 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit,
1521 DAG.getConstant(BitShift,
1522 TLI.getShiftAmountTy(SignBit.getValueType())));
1525 // Now get the sign bit proper, by seeing whether the value is negative.
1526 SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()),
1527 SignBit, DAG.getConstant(0, SignBit.getValueType()),
1529 // Get the absolute value of the result.
1530 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1531 // Select between the nabs and abs value based on the sign bit of
1533 return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit,
1534 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1538 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1539 SmallVectorImpl<SDValue> &Results) {
1540 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1541 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1542 " not tell us which reg is the stack pointer!");
1543 DebugLoc dl = Node->getDebugLoc();
1544 EVT VT = Node->getValueType(0);
1545 SDValue Tmp1 = SDValue(Node, 0);
1546 SDValue Tmp2 = SDValue(Node, 1);
1547 SDValue Tmp3 = Node->getOperand(2);
1548 SDValue Chain = Tmp1.getOperand(0);
1550 // Chain the dynamic stack allocation so that it doesn't modify the stack
1551 // pointer when other instructions are using the stack.
1552 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1554 SDValue Size = Tmp2.getOperand(1);
1555 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1556 Chain = SP.getValue(1);
1557 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1558 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
1559 if (Align > StackAlign)
1560 SP = DAG.getNode(ISD::AND, dl, VT, SP,
1561 DAG.getConstant(-(uint64_t)Align, VT));
1562 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1563 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1565 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1566 DAG.getIntPtrConstant(0, true), SDValue());
1568 Results.push_back(Tmp1);
1569 Results.push_back(Tmp2);
1572 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
1573 /// condition code CC on the current target. This routine expands SETCC with
1574 /// illegal condition code into AND / OR of multiple SETCC values.
1575 void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1576 SDValue &LHS, SDValue &RHS,
1579 EVT OpVT = LHS.getValueType();
1580 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1581 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1582 default: llvm_unreachable("Unknown condition code action!");
1583 case TargetLowering::Legal:
1586 case TargetLowering::Expand: {
1587 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1590 default: llvm_unreachable("Don't know how to expand this condition!");
1591 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break;
1592 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1593 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1594 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1595 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1596 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1597 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1598 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1599 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1600 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1601 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1602 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1603 // FIXME: Implement more expansions.
1606 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1607 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1608 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1616 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
1617 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1618 /// a load from the stack slot to DestVT, extending it if needed.
1619 /// The resultant code need not be legal.
1620 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
1624 // Create the stack frame object.
1626 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType().
1627 getTypeForEVT(*DAG.getContext()));
1628 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1630 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1631 int SPFI = StackPtrFI->getIndex();
1632 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(SPFI);
1634 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
1635 unsigned SlotSize = SlotVT.getSizeInBits();
1636 unsigned DestSize = DestVT.getSizeInBits();
1637 Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
1638 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(DestType);
1640 // Emit a store to the stack slot. Use a truncstore if the input value is
1641 // later than DestVT.
1644 if (SrcSize > SlotSize)
1645 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1646 PtrInfo, SlotVT, false, false, SrcAlign);
1648 assert(SrcSize == SlotSize && "Invalid store");
1649 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1650 PtrInfo, false, false, SrcAlign);
1653 // Result is a load from the stack slot.
1654 if (SlotSize == DestSize)
1655 return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo,
1656 false, false, false, DestAlign);
1658 assert(SlotSize < DestSize && "Unknown extension!");
1659 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr,
1660 PtrInfo, SlotVT, false, false, DestAlign);
1663 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1664 DebugLoc dl = Node->getDebugLoc();
1665 // Create a vector sized/aligned stack slot, store the value to element #0,
1666 // then load the whole vector back out.
1667 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1669 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1670 int SPFI = StackPtrFI->getIndex();
1672 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0),
1674 MachinePointerInfo::getFixedStack(SPFI),
1675 Node->getValueType(0).getVectorElementType(),
1677 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
1678 MachinePointerInfo::getFixedStack(SPFI),
1679 false, false, false, 0);
1683 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
1684 /// support the operation, but do support the resultant vector type.
1685 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1686 unsigned NumElems = Node->getNumOperands();
1687 SDValue Value1, Value2;
1688 DebugLoc dl = Node->getDebugLoc();
1689 EVT VT = Node->getValueType(0);
1690 EVT OpVT = Node->getOperand(0).getValueType();
1691 EVT EltVT = VT.getVectorElementType();
1693 // If the only non-undef value is the low element, turn this into a
1694 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1695 bool isOnlyLowElement = true;
1696 bool MoreThanTwoValues = false;
1697 bool isConstant = true;
1698 for (unsigned i = 0; i < NumElems; ++i) {
1699 SDValue V = Node->getOperand(i);
1700 if (V.getOpcode() == ISD::UNDEF)
1703 isOnlyLowElement = false;
1704 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1707 if (!Value1.getNode()) {
1709 } else if (!Value2.getNode()) {
1712 } else if (V != Value1 && V != Value2) {
1713 MoreThanTwoValues = true;
1717 if (!Value1.getNode())
1718 return DAG.getUNDEF(VT);
1720 if (isOnlyLowElement)
1721 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1723 // If all elements are constants, create a load from the constant pool.
1725 SmallVector<Constant*, 16> CV;
1726 for (unsigned i = 0, e = NumElems; i != e; ++i) {
1727 if (ConstantFPSDNode *V =
1728 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1729 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1730 } else if (ConstantSDNode *V =
1731 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1733 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1735 // If OpVT and EltVT don't match, EltVT is not legal and the
1736 // element values have been promoted/truncated earlier. Undo this;
1737 // we don't want a v16i8 to become a v16i32 for example.
1738 const ConstantInt *CI = V->getConstantIntValue();
1739 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
1740 CI->getZExtValue()));
1743 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
1744 Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
1745 CV.push_back(UndefValue::get(OpNTy));
1748 Constant *CP = ConstantVector::get(CV);
1749 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
1750 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
1751 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
1752 MachinePointerInfo::getConstantPool(),
1753 false, false, false, Alignment);
1756 if (!MoreThanTwoValues) {
1757 SmallVector<int, 8> ShuffleVec(NumElems, -1);
1758 for (unsigned i = 0; i < NumElems; ++i) {
1759 SDValue V = Node->getOperand(i);
1760 if (V.getOpcode() == ISD::UNDEF)
1762 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
1764 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
1765 // Get the splatted value into the low element of a vector register.
1766 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
1768 if (Value2.getNode())
1769 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
1771 Vec2 = DAG.getUNDEF(VT);
1773 // Return shuffle(LowValVec, undef, <0,0,0,0>)
1774 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
1778 // Otherwise, we can't handle this case efficiently.
1779 return ExpandVectorBuildThroughStack(Node);
1782 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
1783 // does not fit into a register, return the lo part and set the hi part to the
1784 // by-reg argument. If it does fit into a single register, return the result
1785 // and leave the Hi part unset.
1786 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
1788 TargetLowering::ArgListTy Args;
1789 TargetLowering::ArgListEntry Entry;
1790 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1791 EVT ArgVT = Node->getOperand(i).getValueType();
1792 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1793 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
1794 Entry.isSExt = isSigned;
1795 Entry.isZExt = !isSigned;
1796 Args.push_back(Entry);
1798 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1799 TLI.getPointerTy());
1801 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
1803 // By default, the input chain to this libcall is the entry node of the
1804 // function. If the libcall is going to be emitted as a tail call then
1805 // TLI.isUsedByReturnOnly will change it to the right chain if the return
1806 // node which is being folded has a non-entry input chain.
1807 SDValue InChain = DAG.getEntryNode();
1809 // isTailCall may be true since the callee does not reference caller stack
1810 // frame. Check if it's in the right position.
1811 SDValue TCChain = InChain;
1812 bool isTailCall = isInTailCallPosition(DAG, Node, TCChain, TLI);
1817 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
1818 0, TLI.getLibcallCallingConv(LC), isTailCall,
1819 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
1820 Callee, Args, DAG, Node->getDebugLoc());
1821 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
1824 if (!CallInfo.second.getNode())
1825 // It's a tailcall, return the chain (which is the DAG root).
1826 return DAG.getRoot();
1828 return CallInfo.first;
1831 /// ExpandLibCall - Generate a libcall taking the given operands as arguments
1832 /// and returning a result of type RetVT.
1833 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, EVT RetVT,
1834 const SDValue *Ops, unsigned NumOps,
1835 bool isSigned, DebugLoc dl) {
1836 TargetLowering::ArgListTy Args;
1837 Args.reserve(NumOps);
1839 TargetLowering::ArgListEntry Entry;
1840 for (unsigned i = 0; i != NumOps; ++i) {
1841 Entry.Node = Ops[i];
1842 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
1843 Entry.isSExt = isSigned;
1844 Entry.isZExt = !isSigned;
1845 Args.push_back(Entry);
1847 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1848 TLI.getPointerTy());
1850 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
1852 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
1853 false, 0, TLI.getLibcallCallingConv(LC),
1854 /*isTailCall=*/false,
1855 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
1856 Callee, Args, DAG, dl);
1857 std::pair<SDValue,SDValue> CallInfo = TLI.LowerCallTo(CLI);
1859 return CallInfo.first;
1862 // ExpandChainLibCall - Expand a node into a call to a libcall. Similar to
1863 // ExpandLibCall except that the first operand is the in-chain.
1864 std::pair<SDValue, SDValue>
1865 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
1868 SDValue InChain = Node->getOperand(0);
1870 TargetLowering::ArgListTy Args;
1871 TargetLowering::ArgListEntry Entry;
1872 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) {
1873 EVT ArgVT = Node->getOperand(i).getValueType();
1874 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1875 Entry.Node = Node->getOperand(i);
1877 Entry.isSExt = isSigned;
1878 Entry.isZExt = !isSigned;
1879 Args.push_back(Entry);
1881 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1882 TLI.getPointerTy());
1884 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
1886 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
1887 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
1888 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
1889 Callee, Args, DAG, Node->getDebugLoc());
1890 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
1895 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
1896 RTLIB::Libcall Call_F32,
1897 RTLIB::Libcall Call_F64,
1898 RTLIB::Libcall Call_F80,
1899 RTLIB::Libcall Call_PPCF128) {
1901 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
1902 default: llvm_unreachable("Unexpected request for libcall!");
1903 case MVT::f32: LC = Call_F32; break;
1904 case MVT::f64: LC = Call_F64; break;
1905 case MVT::f80: LC = Call_F80; break;
1906 case MVT::ppcf128: LC = Call_PPCF128; break;
1908 return ExpandLibCall(LC, Node, false);
1911 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
1912 RTLIB::Libcall Call_I8,
1913 RTLIB::Libcall Call_I16,
1914 RTLIB::Libcall Call_I32,
1915 RTLIB::Libcall Call_I64,
1916 RTLIB::Libcall Call_I128) {
1918 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
1919 default: llvm_unreachable("Unexpected request for libcall!");
1920 case MVT::i8: LC = Call_I8; break;
1921 case MVT::i16: LC = Call_I16; break;
1922 case MVT::i32: LC = Call_I32; break;
1923 case MVT::i64: LC = Call_I64; break;
1924 case MVT::i128: LC = Call_I128; break;
1926 return ExpandLibCall(LC, Node, isSigned);
1929 /// isDivRemLibcallAvailable - Return true if divmod libcall is available.
1930 static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
1931 const TargetLowering &TLI) {
1933 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
1934 default: llvm_unreachable("Unexpected request for libcall!");
1935 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
1936 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
1937 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
1938 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
1939 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
1942 return TLI.getLibcallName(LC) != 0;
1945 /// useDivRem - Only issue divrem libcall if both quotient and remainder are
1947 static bool useDivRem(SDNode *Node, bool isSigned, bool isDIV) {
1948 // The other use might have been replaced with a divrem already.
1949 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
1950 unsigned OtherOpcode = 0;
1952 OtherOpcode = isDIV ? ISD::SREM : ISD::SDIV;
1954 OtherOpcode = isDIV ? ISD::UREM : ISD::UDIV;
1956 SDValue Op0 = Node->getOperand(0);
1957 SDValue Op1 = Node->getOperand(1);
1958 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
1959 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
1963 if ((User->getOpcode() == OtherOpcode || User->getOpcode() == DivRemOpc) &&
1964 User->getOperand(0) == Op0 &&
1965 User->getOperand(1) == Op1)
1971 /// ExpandDivRemLibCall - Issue libcalls to __{u}divmod to compute div / rem
1974 SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
1975 SmallVectorImpl<SDValue> &Results) {
1976 unsigned Opcode = Node->getOpcode();
1977 bool isSigned = Opcode == ISD::SDIVREM;
1980 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
1981 default: llvm_unreachable("Unexpected request for libcall!");
1982 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
1983 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
1984 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
1985 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
1986 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
1989 // The input chain to this libcall is the entry node of the function.
1990 // Legalizing the call will automatically add the previous call to the
1992 SDValue InChain = DAG.getEntryNode();
1994 EVT RetVT = Node->getValueType(0);
1995 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
1997 TargetLowering::ArgListTy Args;
1998 TargetLowering::ArgListEntry Entry;
1999 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2000 EVT ArgVT = Node->getOperand(i).getValueType();
2001 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2002 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
2003 Entry.isSExt = isSigned;
2004 Entry.isZExt = !isSigned;
2005 Args.push_back(Entry);
2008 // Also pass the return address of the remainder.
2009 SDValue FIPtr = DAG.CreateStackTemporary(RetVT);
2011 Entry.Ty = RetTy->getPointerTo();
2012 Entry.isSExt = isSigned;
2013 Entry.isZExt = !isSigned;
2014 Args.push_back(Entry);
2016 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2017 TLI.getPointerTy());
2019 DebugLoc dl = Node->getDebugLoc();
2021 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
2022 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
2023 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2024 Callee, Args, DAG, dl);
2025 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2027 // Remainder is loaded back from the stack frame.
2028 SDValue Rem = DAG.getLoad(RetVT, dl, CallInfo.second, FIPtr,
2029 MachinePointerInfo(), false, false, false, 0);
2030 Results.push_back(CallInfo.first);
2031 Results.push_back(Rem);
2034 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
2035 /// INT_TO_FP operation of the specified operand when the target requests that
2036 /// we expand it. At this point, we know that the result and operand types are
2037 /// legal for the target.
2038 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
2042 if (Op0.getValueType() == MVT::i32) {
2043 // simple 32-bit [signed|unsigned] integer to float/double expansion
2045 // Get the stack frame index of a 8 byte buffer.
2046 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2048 // word offset constant for Hi/Lo address computation
2049 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
2050 // set up Hi and Lo (into buffer) address based on endian
2051 SDValue Hi = StackSlot;
2052 SDValue Lo = DAG.getNode(ISD::ADD, dl,
2053 TLI.getPointerTy(), StackSlot, WordOff);
2054 if (TLI.isLittleEndian())
2057 // if signed map to unsigned space
2060 // constant used to invert sign bit (signed to unsigned mapping)
2061 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
2062 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2066 // store the lo of the constructed double - based on integer input
2067 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
2068 Op0Mapped, Lo, MachinePointerInfo(),
2070 // initial hi portion of constructed double
2071 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
2072 // store the hi of the constructed double - biased exponent
2073 SDValue Store2 = DAG.getStore(Store1, dl, InitialHi, Hi,
2074 MachinePointerInfo(),
2076 // load the constructed double
2077 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot,
2078 MachinePointerInfo(), false, false, false, 0);
2079 // FP constant to bias correct the final result
2080 SDValue Bias = DAG.getConstantFP(isSigned ?
2081 BitsToDouble(0x4330000080000000ULL) :
2082 BitsToDouble(0x4330000000000000ULL),
2084 // subtract the bias
2085 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2088 // handle final rounding
2089 if (DestVT == MVT::f64) {
2092 } else if (DestVT.bitsLT(MVT::f64)) {
2093 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2094 DAG.getIntPtrConstant(0));
2095 } else if (DestVT.bitsGT(MVT::f64)) {
2096 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2100 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2101 // Code below here assumes !isSigned without checking again.
2103 // Implementation of unsigned i64 to f64 following the algorithm in
2104 // __floatundidf in compiler_rt. This implementation has the advantage
2105 // of performing rounding correctly, both in the default rounding mode
2106 // and in all alternate rounding modes.
2107 // TODO: Generalize this for use with other types.
2108 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
2110 DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64);
2111 SDValue TwoP84PlusTwoP52 =
2112 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64);
2114 DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64);
2116 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32);
2117 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2118 DAG.getConstant(32, MVT::i64));
2119 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2120 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2121 SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr);
2122 SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr);
2123 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
2125 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
2128 // Implementation of unsigned i64 to f32.
2129 // TODO: Generalize this for use with other types.
2130 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) {
2131 // For unsigned conversions, convert them to signed conversions using the
2132 // algorithm from the x86_64 __floatundidf in compiler_rt.
2134 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0);
2136 SDValue ShiftConst =
2137 DAG.getConstant(1, TLI.getShiftAmountTy(Op0.getValueType()));
2138 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
2139 SDValue AndConst = DAG.getConstant(1, MVT::i64);
2140 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst);
2141 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr);
2143 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or);
2144 SDValue Slow = DAG.getNode(ISD::FADD, dl, MVT::f32, SignCvt, SignCvt);
2146 // TODO: This really should be implemented using a branch rather than a
2147 // select. We happen to get lucky and machinesink does the right
2148 // thing most of the time. This would be a good candidate for a
2149 //pseudo-op, or, even better, for whole-function isel.
2150 SDValue SignBitTest = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2151 Op0, DAG.getConstant(0, MVT::i64), ISD::SETLT);
2152 return DAG.getNode(ISD::SELECT, dl, MVT::f32, SignBitTest, Slow, Fast);
2155 // Otherwise, implement the fully general conversion.
2157 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2158 DAG.getConstant(UINT64_C(0xfffffffffffff800), MVT::i64));
2159 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
2160 DAG.getConstant(UINT64_C(0x800), MVT::i64));
2161 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2162 DAG.getConstant(UINT64_C(0x7ff), MVT::i64));
2163 SDValue Ne = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2164 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE);
2165 SDValue Sel = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ne, Or, Op0);
2166 SDValue Ge = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2167 Op0, DAG.getConstant(UINT64_C(0x0020000000000000), MVT::i64),
2169 SDValue Sel2 = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ge, Sel, Op0);
2170 EVT SHVT = TLI.getShiftAmountTy(Sel2.getValueType());
2172 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2173 DAG.getConstant(32, SHVT));
2174 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh);
2175 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc);
2177 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), MVT::f64);
2178 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt);
2179 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2);
2180 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo);
2181 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2);
2182 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd,
2183 DAG.getIntPtrConstant(0));
2186 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2188 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()),
2189 Op0, DAG.getConstant(0, Op0.getValueType()),
2191 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
2192 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
2193 SignSet, Four, Zero);
2195 // If the sign bit of the integer is set, the large number will be treated
2196 // as a negative number. To counteract this, the dynamic code adds an
2197 // offset depending on the data type.
2199 switch (Op0.getValueType().getSimpleVT().SimpleTy) {
2200 default: llvm_unreachable("Unsupported integer type!");
2201 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2202 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2203 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2204 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2206 if (TLI.isLittleEndian()) FF <<= 32;
2207 Constant *FudgeFactor = ConstantInt::get(
2208 Type::getInt64Ty(*DAG.getContext()), FF);
2210 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
2211 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2212 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
2213 Alignment = std::min(Alignment, 4u);
2215 if (DestVT == MVT::f32)
2216 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2217 MachinePointerInfo::getConstantPool(),
2218 false, false, false, Alignment);
2220 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
2221 DAG.getEntryNode(), CPIdx,
2222 MachinePointerInfo::getConstantPool(),
2223 MVT::f32, false, false, Alignment);
2224 HandleSDNode Handle(Load);
2225 LegalizeOp(Load.getNode());
2226 FudgeInReg = Handle.getValue();
2229 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2232 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
2233 /// *INT_TO_FP operation of the specified operand when the target requests that
2234 /// we promote it. At this point, we know that the result and operand types are
2235 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2236 /// operation that takes a larger input.
2237 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2241 // First step, figure out the appropriate *INT_TO_FP operation to use.
2242 EVT NewInTy = LegalOp.getValueType();
2244 unsigned OpToUse = 0;
2246 // Scan for the appropriate larger type to use.
2248 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2249 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2251 // If the target supports SINT_TO_FP of this type, use it.
2252 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2253 OpToUse = ISD::SINT_TO_FP;
2256 if (isSigned) continue;
2258 // If the target supports UINT_TO_FP of this type, use it.
2259 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2260 OpToUse = ISD::UINT_TO_FP;
2264 // Otherwise, try a larger type.
2267 // Okay, we found the operation and type to use. Zero extend our input to the
2268 // desired type then run the operation on it.
2269 return DAG.getNode(OpToUse, dl, DestVT,
2270 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2271 dl, NewInTy, LegalOp));
2274 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
2275 /// FP_TO_*INT operation of the specified operand when the target requests that
2276 /// we promote it. At this point, we know that the result and operand types are
2277 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2278 /// operation that returns a larger result.
2279 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2283 // First step, figure out the appropriate FP_TO*INT operation to use.
2284 EVT NewOutTy = DestVT;
2286 unsigned OpToUse = 0;
2288 // Scan for the appropriate larger type to use.
2290 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2291 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2293 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2294 OpToUse = ISD::FP_TO_SINT;
2298 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2299 OpToUse = ISD::FP_TO_UINT;
2303 // Otherwise, try a larger type.
2307 // Okay, we found the operation and type to use.
2308 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2310 // Truncate the result of the extended FP_TO_*INT operation to the desired
2312 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2315 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
2317 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) {
2318 EVT VT = Op.getValueType();
2319 EVT SHVT = TLI.getShiftAmountTy(VT);
2320 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2321 switch (VT.getSimpleVT().SimpleTy) {
2322 default: llvm_unreachable("Unhandled Expand type in BSWAP!");
2324 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2325 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2326 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2328 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2329 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2330 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2331 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2332 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
2333 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
2334 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2335 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2336 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2338 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
2339 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
2340 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2341 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2342 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2343 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2344 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
2345 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
2346 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
2347 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
2348 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
2349 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
2350 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
2351 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
2352 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2353 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2354 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2355 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2356 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2357 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2358 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2362 /// SplatByte - Distribute ByteVal over NumBits bits.
2363 // FIXME: Move this helper to a common place.
2364 static APInt SplatByte(unsigned NumBits, uint8_t ByteVal) {
2365 APInt Val = APInt(NumBits, ByteVal);
2367 for (unsigned i = NumBits; i > 8; i >>= 1) {
2368 Val = (Val << Shift) | Val;
2374 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
2376 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2379 default: llvm_unreachable("Cannot expand this yet!");
2381 EVT VT = Op.getValueType();
2382 EVT ShVT = TLI.getShiftAmountTy(VT);
2383 unsigned Len = VT.getSizeInBits();
2385 assert(VT.isInteger() && Len <= 128 && Len % 8 == 0 &&
2386 "CTPOP not implemented for this type.");
2388 // This is the "best" algorithm from
2389 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
2391 SDValue Mask55 = DAG.getConstant(SplatByte(Len, 0x55), VT);
2392 SDValue Mask33 = DAG.getConstant(SplatByte(Len, 0x33), VT);
2393 SDValue Mask0F = DAG.getConstant(SplatByte(Len, 0x0F), VT);
2394 SDValue Mask01 = DAG.getConstant(SplatByte(Len, 0x01), VT);
2396 // v = v - ((v >> 1) & 0x55555555...)
2397 Op = DAG.getNode(ISD::SUB, dl, VT, Op,
2398 DAG.getNode(ISD::AND, dl, VT,
2399 DAG.getNode(ISD::SRL, dl, VT, Op,
2400 DAG.getConstant(1, ShVT)),
2402 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
2403 Op = DAG.getNode(ISD::ADD, dl, VT,
2404 DAG.getNode(ISD::AND, dl, VT, Op, Mask33),
2405 DAG.getNode(ISD::AND, dl, VT,
2406 DAG.getNode(ISD::SRL, dl, VT, Op,
2407 DAG.getConstant(2, ShVT)),
2409 // v = (v + (v >> 4)) & 0x0F0F0F0F...
2410 Op = DAG.getNode(ISD::AND, dl, VT,
2411 DAG.getNode(ISD::ADD, dl, VT, Op,
2412 DAG.getNode(ISD::SRL, dl, VT, Op,
2413 DAG.getConstant(4, ShVT))),
2415 // v = (v * 0x01010101...) >> (Len - 8)
2416 Op = DAG.getNode(ISD::SRL, dl, VT,
2417 DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
2418 DAG.getConstant(Len - 8, ShVT));
2422 case ISD::CTLZ_ZERO_UNDEF:
2423 // This trivially expands to CTLZ.
2424 return DAG.getNode(ISD::CTLZ, dl, Op.getValueType(), Op);
2426 // for now, we do this:
2427 // x = x | (x >> 1);
2428 // x = x | (x >> 2);
2430 // x = x | (x >>16);
2431 // x = x | (x >>32); // for 64-bit input
2432 // return popcount(~x);
2434 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
2435 EVT VT = Op.getValueType();
2436 EVT ShVT = TLI.getShiftAmountTy(VT);
2437 unsigned len = VT.getSizeInBits();
2438 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2439 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2440 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2441 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2443 Op = DAG.getNOT(dl, Op, VT);
2444 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2446 case ISD::CTTZ_ZERO_UNDEF:
2447 // This trivially expands to CTTZ.
2448 return DAG.getNode(ISD::CTTZ, dl, Op.getValueType(), Op);
2450 // for now, we use: { return popcount(~x & (x - 1)); }
2451 // unless the target has ctlz but not ctpop, in which case we use:
2452 // { return 32 - nlz(~x & (x-1)); }
2453 // see also http://www.hackersdelight.org/HDcode/ntz.cc
2454 EVT VT = Op.getValueType();
2455 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2456 DAG.getNOT(dl, Op, VT),
2457 DAG.getNode(ISD::SUB, dl, VT, Op,
2458 DAG.getConstant(1, VT)));
2459 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2460 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2461 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2462 return DAG.getNode(ISD::SUB, dl, VT,
2463 DAG.getConstant(VT.getSizeInBits(), VT),
2464 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2465 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2470 std::pair <SDValue, SDValue> SelectionDAGLegalize::ExpandAtomic(SDNode *Node) {
2471 unsigned Opc = Node->getOpcode();
2472 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
2477 llvm_unreachable("Unhandled atomic intrinsic Expand!");
2478 case ISD::ATOMIC_SWAP:
2479 switch (VT.SimpleTy) {
2480 default: llvm_unreachable("Unexpected value type for atomic!");
2481 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break;
2482 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
2483 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
2484 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
2487 case ISD::ATOMIC_CMP_SWAP:
2488 switch (VT.SimpleTy) {
2489 default: llvm_unreachable("Unexpected value type for atomic!");
2490 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break;
2491 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;
2492 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;
2493 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
2496 case ISD::ATOMIC_LOAD_ADD:
2497 switch (VT.SimpleTy) {
2498 default: llvm_unreachable("Unexpected value type for atomic!");
2499 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break;
2500 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;
2501 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;
2502 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
2505 case ISD::ATOMIC_LOAD_SUB:
2506 switch (VT.SimpleTy) {
2507 default: llvm_unreachable("Unexpected value type for atomic!");
2508 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break;
2509 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;
2510 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;
2511 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
2514 case ISD::ATOMIC_LOAD_AND:
2515 switch (VT.SimpleTy) {
2516 default: llvm_unreachable("Unexpected value type for atomic!");
2517 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break;
2518 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;
2519 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;
2520 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
2523 case ISD::ATOMIC_LOAD_OR:
2524 switch (VT.SimpleTy) {
2525 default: llvm_unreachable("Unexpected value type for atomic!");
2526 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break;
2527 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;
2528 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;
2529 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
2532 case ISD::ATOMIC_LOAD_XOR:
2533 switch (VT.SimpleTy) {
2534 default: llvm_unreachable("Unexpected value type for atomic!");
2535 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break;
2536 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;
2537 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;
2538 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
2541 case ISD::ATOMIC_LOAD_NAND:
2542 switch (VT.SimpleTy) {
2543 default: llvm_unreachable("Unexpected value type for atomic!");
2544 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break;
2545 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;
2546 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;
2547 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
2552 return ExpandChainLibCall(LC, Node, false);
2555 void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
2556 SmallVector<SDValue, 8> Results;
2557 DebugLoc dl = Node->getDebugLoc();
2558 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2559 switch (Node->getOpcode()) {
2562 case ISD::CTLZ_ZERO_UNDEF:
2564 case ISD::CTTZ_ZERO_UNDEF:
2565 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
2566 Results.push_back(Tmp1);
2569 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2571 case ISD::FRAMEADDR:
2572 case ISD::RETURNADDR:
2573 case ISD::FRAME_TO_ARGS_OFFSET:
2574 Results.push_back(DAG.getConstant(0, Node->getValueType(0)));
2576 case ISD::FLT_ROUNDS_:
2577 Results.push_back(DAG.getConstant(1, Node->getValueType(0)));
2579 case ISD::EH_RETURN:
2583 case ISD::EH_SJLJ_LONGJMP:
2584 // If the target didn't expand these, there's nothing to do, so just
2585 // preserve the chain and be done.
2586 Results.push_back(Node->getOperand(0));
2588 case ISD::EH_SJLJ_SETJMP:
2589 // If the target didn't expand this, just return 'zero' and preserve the
2591 Results.push_back(DAG.getConstant(0, MVT::i32));
2592 Results.push_back(Node->getOperand(0));
2594 case ISD::ATOMIC_FENCE:
2595 case ISD::MEMBARRIER: {
2596 // If the target didn't lower this, lower it to '__sync_synchronize()' call
2597 // FIXME: handle "fence singlethread" more efficiently.
2598 TargetLowering::ArgListTy Args;
2600 CallLoweringInfo CLI(Node->getOperand(0),
2601 Type::getVoidTy(*DAG.getContext()),
2602 false, false, false, false, 0, CallingConv::C,
2603 /*isTailCall=*/false,
2604 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2605 DAG.getExternalSymbol("__sync_synchronize",
2606 TLI.getPointerTy()),
2608 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
2610 Results.push_back(CallResult.second);
2613 case ISD::ATOMIC_LOAD: {
2614 // There is no libcall for atomic load; fake it with ATOMIC_CMP_SWAP.
2615 SDValue Zero = DAG.getConstant(0, Node->getValueType(0));
2616 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl,
2617 cast<AtomicSDNode>(Node)->getMemoryVT(),
2618 Node->getOperand(0),
2619 Node->getOperand(1), Zero, Zero,
2620 cast<AtomicSDNode>(Node)->getMemOperand(),
2621 cast<AtomicSDNode>(Node)->getOrdering(),
2622 cast<AtomicSDNode>(Node)->getSynchScope());
2623 Results.push_back(Swap.getValue(0));
2624 Results.push_back(Swap.getValue(1));
2627 case ISD::ATOMIC_STORE: {
2628 // There is no libcall for atomic store; fake it with ATOMIC_SWAP.
2629 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
2630 cast<AtomicSDNode>(Node)->getMemoryVT(),
2631 Node->getOperand(0),
2632 Node->getOperand(1), Node->getOperand(2),
2633 cast<AtomicSDNode>(Node)->getMemOperand(),
2634 cast<AtomicSDNode>(Node)->getOrdering(),
2635 cast<AtomicSDNode>(Node)->getSynchScope());
2636 Results.push_back(Swap.getValue(1));
2639 // By default, atomic intrinsics are marked Legal and lowered. Targets
2640 // which don't support them directly, however, may want libcalls, in which
2641 // case they mark them Expand, and we get here.
2642 case ISD::ATOMIC_SWAP:
2643 case ISD::ATOMIC_LOAD_ADD:
2644 case ISD::ATOMIC_LOAD_SUB:
2645 case ISD::ATOMIC_LOAD_AND:
2646 case ISD::ATOMIC_LOAD_OR:
2647 case ISD::ATOMIC_LOAD_XOR:
2648 case ISD::ATOMIC_LOAD_NAND:
2649 case ISD::ATOMIC_LOAD_MIN:
2650 case ISD::ATOMIC_LOAD_MAX:
2651 case ISD::ATOMIC_LOAD_UMIN:
2652 case ISD::ATOMIC_LOAD_UMAX:
2653 case ISD::ATOMIC_CMP_SWAP: {
2654 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node);
2655 Results.push_back(Tmp.first);
2656 Results.push_back(Tmp.second);
2659 case ISD::DYNAMIC_STACKALLOC:
2660 ExpandDYNAMIC_STACKALLOC(Node, Results);
2662 case ISD::MERGE_VALUES:
2663 for (unsigned i = 0; i < Node->getNumValues(); i++)
2664 Results.push_back(Node->getOperand(i));
2667 EVT VT = Node->getValueType(0);
2669 Results.push_back(DAG.getConstant(0, VT));
2671 assert(VT.isFloatingPoint() && "Unknown value type!");
2672 Results.push_back(DAG.getConstantFP(0, VT));
2677 // If this operation is not supported, lower it to 'abort()' call
2678 TargetLowering::ArgListTy Args;
2680 CallLoweringInfo CLI(Node->getOperand(0),
2681 Type::getVoidTy(*DAG.getContext()),
2682 false, false, false, false, 0, CallingConv::C,
2683 /*isTailCall=*/false,
2684 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2685 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
2687 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
2689 Results.push_back(CallResult.second);
2694 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
2695 Node->getValueType(0), dl);
2696 Results.push_back(Tmp1);
2698 case ISD::FP_EXTEND:
2699 Tmp1 = EmitStackConvert(Node->getOperand(0),
2700 Node->getOperand(0).getValueType(),
2701 Node->getValueType(0), dl);
2702 Results.push_back(Tmp1);
2704 case ISD::SIGN_EXTEND_INREG: {
2705 // NOTE: we could fall back on load/store here too for targets without
2706 // SAR. However, it is doubtful that any exist.
2707 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2708 EVT VT = Node->getValueType(0);
2709 EVT ShiftAmountTy = TLI.getShiftAmountTy(VT);
2712 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
2713 ExtraVT.getScalarType().getSizeInBits();
2714 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy);
2715 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
2716 Node->getOperand(0), ShiftCst);
2717 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
2718 Results.push_back(Tmp1);
2721 case ISD::FP_ROUND_INREG: {
2722 // The only way we can lower this is to turn it into a TRUNCSTORE,
2723 // EXTLOAD pair, targeting a temporary location (a stack slot).
2725 // NOTE: there is a choice here between constantly creating new stack
2726 // slots and always reusing the same one. We currently always create
2727 // new ones, as reuse may inhibit scheduling.
2728 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2729 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
2730 Node->getValueType(0), dl);
2731 Results.push_back(Tmp1);
2734 case ISD::SINT_TO_FP:
2735 case ISD::UINT_TO_FP:
2736 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
2737 Node->getOperand(0), Node->getValueType(0), dl);
2738 Results.push_back(Tmp1);
2740 case ISD::FP_TO_UINT: {
2741 SDValue True, False;
2742 EVT VT = Node->getOperand(0).getValueType();
2743 EVT NVT = Node->getValueType(0);
2744 APFloat apf(APInt::getNullValue(VT.getSizeInBits()));
2745 APInt x = APInt::getSignBit(NVT.getSizeInBits());
2746 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
2747 Tmp1 = DAG.getConstantFP(apf, VT);
2748 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
2749 Node->getOperand(0),
2751 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
2752 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
2753 DAG.getNode(ISD::FSUB, dl, VT,
2754 Node->getOperand(0), Tmp1));
2755 False = DAG.getNode(ISD::XOR, dl, NVT, False,
2756 DAG.getConstant(x, NVT));
2757 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False);
2758 Results.push_back(Tmp1);
2762 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2763 EVT VT = Node->getValueType(0);
2764 Tmp1 = Node->getOperand(0);
2765 Tmp2 = Node->getOperand(1);
2766 unsigned Align = Node->getConstantOperandVal(3);
2768 SDValue VAListLoad = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2,
2769 MachinePointerInfo(V),
2770 false, false, false, 0);
2771 SDValue VAList = VAListLoad;
2773 if (Align > TLI.getMinStackArgumentAlignment()) {
2774 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
2776 VAList = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
2777 DAG.getConstant(Align - 1,
2778 TLI.getPointerTy()));
2780 VAList = DAG.getNode(ISD::AND, dl, TLI.getPointerTy(), VAList,
2781 DAG.getConstant(-(int64_t)Align,
2782 TLI.getPointerTy()));
2785 // Increment the pointer, VAList, to the next vaarg
2786 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
2787 DAG.getConstant(TLI.getTargetData()->
2788 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())),
2789 TLI.getPointerTy()));
2790 // Store the incremented VAList to the legalized pointer
2791 Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2,
2792 MachinePointerInfo(V), false, false, 0);
2793 // Load the actual argument out of the pointer VAList
2794 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(),
2795 false, false, false, 0));
2796 Results.push_back(Results[0].getValue(1));
2800 // This defaults to loading a pointer from the input and storing it to the
2801 // output, returning the chain.
2802 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
2803 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
2804 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0),
2805 Node->getOperand(2), MachinePointerInfo(VS),
2806 false, false, false, 0);
2807 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1),
2808 MachinePointerInfo(VD), false, false, 0);
2809 Results.push_back(Tmp1);
2812 case ISD::EXTRACT_VECTOR_ELT:
2813 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
2814 // This must be an access of the only element. Return it.
2815 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
2816 Node->getOperand(0));
2818 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
2819 Results.push_back(Tmp1);
2821 case ISD::EXTRACT_SUBVECTOR:
2822 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
2824 case ISD::INSERT_SUBVECTOR:
2825 Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0)));
2827 case ISD::CONCAT_VECTORS: {
2828 Results.push_back(ExpandVectorBuildThroughStack(Node));
2831 case ISD::SCALAR_TO_VECTOR:
2832 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
2834 case ISD::INSERT_VECTOR_ELT:
2835 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
2836 Node->getOperand(1),
2837 Node->getOperand(2), dl));
2839 case ISD::VECTOR_SHUFFLE: {
2840 SmallVector<int, 32> NewMask;
2841 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
2843 EVT VT = Node->getValueType(0);
2844 EVT EltVT = VT.getVectorElementType();
2845 SDValue Op0 = Node->getOperand(0);
2846 SDValue Op1 = Node->getOperand(1);
2847 if (!TLI.isTypeLegal(EltVT)) {
2849 EVT NewEltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
2851 // BUILD_VECTOR operands are allowed to be wider than the element type.
2852 // But if NewEltVT is smaller that EltVT the BUILD_VECTOR does not accept it
2853 if (NewEltVT.bitsLT(EltVT)) {
2855 // Convert shuffle node.
2856 // If original node was v4i64 and the new EltVT is i32,
2857 // cast operands to v8i32 and re-build the mask.
2859 // Calculate new VT, the size of the new VT should be equal to original.
2860 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), NewEltVT,
2861 VT.getSizeInBits()/NewEltVT.getSizeInBits());
2862 assert(NewVT.bitsEq(VT));
2864 // cast operands to new VT
2865 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0);
2866 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1);
2868 // Convert the shuffle mask
2869 unsigned int factor = NewVT.getVectorNumElements()/VT.getVectorNumElements();
2871 // EltVT gets smaller
2874 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
2876 for (unsigned fi = 0; fi < factor; ++fi)
2877 NewMask.push_back(Mask[i]);
2880 for (unsigned fi = 0; fi < factor; ++fi)
2881 NewMask.push_back(Mask[i]*factor+fi);
2889 unsigned NumElems = VT.getVectorNumElements();
2890 SmallVector<SDValue, 16> Ops;
2891 for (unsigned i = 0; i != NumElems; ++i) {
2893 Ops.push_back(DAG.getUNDEF(EltVT));
2896 unsigned Idx = Mask[i];
2898 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
2900 DAG.getIntPtrConstant(Idx)));
2902 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
2904 DAG.getIntPtrConstant(Idx - NumElems)));
2907 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
2908 // We may have changed the BUILD_VECTOR type. Cast it back to the Node type.
2909 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), Tmp1);
2910 Results.push_back(Tmp1);
2913 case ISD::EXTRACT_ELEMENT: {
2914 EVT OpTy = Node->getOperand(0).getValueType();
2915 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
2917 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
2918 DAG.getConstant(OpTy.getSizeInBits()/2,
2919 TLI.getShiftAmountTy(Node->getOperand(0).getValueType())));
2920 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
2923 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
2924 Node->getOperand(0));
2926 Results.push_back(Tmp1);
2929 case ISD::STACKSAVE:
2930 // Expand to CopyFromReg if the target set
2931 // StackPointerRegisterToSaveRestore.
2932 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2933 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
2934 Node->getValueType(0)));
2935 Results.push_back(Results[0].getValue(1));
2937 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
2938 Results.push_back(Node->getOperand(0));
2941 case ISD::STACKRESTORE:
2942 // Expand to CopyToReg if the target set
2943 // StackPointerRegisterToSaveRestore.
2944 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2945 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
2946 Node->getOperand(1)));
2948 Results.push_back(Node->getOperand(0));
2951 case ISD::FCOPYSIGN:
2952 Results.push_back(ExpandFCOPYSIGN(Node));
2955 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2956 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2957 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
2958 Node->getOperand(0));
2959 Results.push_back(Tmp1);
2962 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2963 EVT VT = Node->getValueType(0);
2964 Tmp1 = Node->getOperand(0);
2965 Tmp2 = DAG.getConstantFP(0.0, VT);
2966 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
2967 Tmp1, Tmp2, ISD::SETUGT);
2968 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
2969 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3);
2970 Results.push_back(Tmp1);
2974 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
2975 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128));
2978 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
2979 RTLIB::SIN_F80, RTLIB::SIN_PPCF128));
2982 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
2983 RTLIB::COS_F80, RTLIB::COS_PPCF128));
2986 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
2987 RTLIB::LOG_F80, RTLIB::LOG_PPCF128));
2990 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
2991 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128));
2994 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
2995 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128));
2998 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
2999 RTLIB::EXP_F80, RTLIB::EXP_PPCF128));
3002 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3003 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128));
3006 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3007 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128));
3010 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3011 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128));
3014 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3015 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128));
3018 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
3019 RTLIB::RINT_F80, RTLIB::RINT_PPCF128));
3021 case ISD::FNEARBYINT:
3022 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
3023 RTLIB::NEARBYINT_F64,
3024 RTLIB::NEARBYINT_F80,
3025 RTLIB::NEARBYINT_PPCF128));
3028 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
3029 RTLIB::POWI_F80, RTLIB::POWI_PPCF128));
3032 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
3033 RTLIB::POW_F80, RTLIB::POW_PPCF128));
3036 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
3037 RTLIB::DIV_F80, RTLIB::DIV_PPCF128));
3040 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
3041 RTLIB::REM_F80, RTLIB::REM_PPCF128));
3044 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMA_F32, RTLIB::FMA_F64,
3045 RTLIB::FMA_F80, RTLIB::FMA_PPCF128));
3047 case ISD::FP16_TO_FP32:
3048 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
3050 case ISD::FP32_TO_FP16:
3051 Results.push_back(ExpandLibCall(RTLIB::FPROUND_F32_F16, Node, false));
3053 case ISD::ConstantFP: {
3054 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
3055 // Check to see if this FP immediate is already legal.
3056 // If this is a legal constant, turn it into a TargetConstantFP node.
3057 if (!TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
3058 Results.push_back(ExpandConstantFP(CFP, true));
3061 case ISD::EHSELECTION: {
3062 unsigned Reg = TLI.getExceptionSelectorRegister();
3063 assert(Reg && "Can't expand to unknown register!");
3064 Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg,
3065 Node->getValueType(0)));
3066 Results.push_back(Results[0].getValue(1));
3069 case ISD::EXCEPTIONADDR: {
3070 unsigned Reg = TLI.getExceptionPointerRegister();
3071 assert(Reg && "Can't expand to unknown register!");
3072 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg,
3073 Node->getValueType(0)));
3074 Results.push_back(Results[0].getValue(1));
3078 EVT VT = Node->getValueType(0);
3079 assert(TLI.isOperationLegalOrCustom(ISD::FADD, VT) &&
3080 TLI.isOperationLegalOrCustom(ISD::FNEG, VT) &&
3081 "Don't know how to expand this FP subtraction!");
3082 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1));
3083 Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1);
3084 Results.push_back(Tmp1);
3088 EVT VT = Node->getValueType(0);
3089 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3090 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3091 "Don't know how to expand this subtraction!");
3092 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3093 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
3094 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, VT));
3095 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3100 EVT VT = Node->getValueType(0);
3101 SDVTList VTs = DAG.getVTList(VT, VT);
3102 bool isSigned = Node->getOpcode() == ISD::SREM;
3103 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3104 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3105 Tmp2 = Node->getOperand(0);
3106 Tmp3 = Node->getOperand(1);
3107 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3108 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3109 useDivRem(Node, isSigned, false))) {
3110 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
3111 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
3113 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
3114 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3115 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3116 } else if (isSigned)
3117 Tmp1 = ExpandIntLibCall(Node, true,
3119 RTLIB::SREM_I16, RTLIB::SREM_I32,
3120 RTLIB::SREM_I64, RTLIB::SREM_I128);
3122 Tmp1 = ExpandIntLibCall(Node, false,
3124 RTLIB::UREM_I16, RTLIB::UREM_I32,
3125 RTLIB::UREM_I64, RTLIB::UREM_I128);
3126 Results.push_back(Tmp1);
3131 bool isSigned = Node->getOpcode() == ISD::SDIV;
3132 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3133 EVT VT = Node->getValueType(0);
3134 SDVTList VTs = DAG.getVTList(VT, VT);
3135 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3136 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3137 useDivRem(Node, isSigned, true)))
3138 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
3139 Node->getOperand(1));
3141 Tmp1 = ExpandIntLibCall(Node, true,
3143 RTLIB::SDIV_I16, RTLIB::SDIV_I32,
3144 RTLIB::SDIV_I64, RTLIB::SDIV_I128);
3146 Tmp1 = ExpandIntLibCall(Node, false,
3148 RTLIB::UDIV_I16, RTLIB::UDIV_I32,
3149 RTLIB::UDIV_I64, RTLIB::UDIV_I128);
3150 Results.push_back(Tmp1);
3155 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
3157 EVT VT = Node->getValueType(0);
3158 SDVTList VTs = DAG.getVTList(VT, VT);
3159 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
3160 "If this wasn't legal, it shouldn't have been created!");
3161 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
3162 Node->getOperand(1));
3163 Results.push_back(Tmp1.getValue(1));
3168 // Expand into divrem libcall
3169 ExpandDivRemLibCall(Node, Results);
3172 EVT VT = Node->getValueType(0);
3173 SDVTList VTs = DAG.getVTList(VT, VT);
3174 // See if multiply or divide can be lowered using two-result operations.
3175 // We just need the low half of the multiply; try both the signed
3176 // and unsigned forms. If the target supports both SMUL_LOHI and
3177 // UMUL_LOHI, form a preference by checking which forms of plain
3178 // MULH it supports.
3179 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3180 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3181 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3182 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3183 unsigned OpToUse = 0;
3184 if (HasSMUL_LOHI && !HasMULHS) {
3185 OpToUse = ISD::SMUL_LOHI;
3186 } else if (HasUMUL_LOHI && !HasMULHU) {
3187 OpToUse = ISD::UMUL_LOHI;
3188 } else if (HasSMUL_LOHI) {
3189 OpToUse = ISD::SMUL_LOHI;
3190 } else if (HasUMUL_LOHI) {
3191 OpToUse = ISD::UMUL_LOHI;
3194 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
3195 Node->getOperand(1)));
3198 Tmp1 = ExpandIntLibCall(Node, false,
3200 RTLIB::MUL_I16, RTLIB::MUL_I32,
3201 RTLIB::MUL_I64, RTLIB::MUL_I128);
3202 Results.push_back(Tmp1);
3207 SDValue LHS = Node->getOperand(0);
3208 SDValue RHS = Node->getOperand(1);
3209 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3210 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3212 Results.push_back(Sum);
3213 EVT OType = Node->getValueType(1);
3215 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
3217 // LHSSign -> LHS >= 0
3218 // RHSSign -> RHS >= 0
3219 // SumSign -> Sum >= 0
3222 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3224 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3226 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3227 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3228 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
3229 Node->getOpcode() == ISD::SADDO ?
3230 ISD::SETEQ : ISD::SETNE);
3232 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3233 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3235 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3236 Results.push_back(Cmp);
3241 SDValue LHS = Node->getOperand(0);
3242 SDValue RHS = Node->getOperand(1);
3243 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
3244 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3246 Results.push_back(Sum);
3247 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS,
3248 Node->getOpcode () == ISD::UADDO ?
3249 ISD::SETULT : ISD::SETUGT));
3254 EVT VT = Node->getValueType(0);
3255 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
3256 SDValue LHS = Node->getOperand(0);
3257 SDValue RHS = Node->getOperand(1);
3260 static const unsigned Ops[2][3] =
3261 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
3262 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
3263 bool isSigned = Node->getOpcode() == ISD::SMULO;
3264 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3265 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3266 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3267 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3268 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3270 TopHalf = BottomHalf.getValue(1);
3271 } else if (TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(),
3272 VT.getSizeInBits() * 2))) {
3273 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
3274 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
3275 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
3276 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3277 DAG.getIntPtrConstant(0));
3278 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3279 DAG.getIntPtrConstant(1));
3281 // We can fall back to a libcall with an illegal type for the MUL if we
3282 // have a libcall big enough.
3283 // Also, we can fall back to a division in some cases, but that's a big
3284 // performance hit in the general case.
3285 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3286 if (WideVT == MVT::i16)
3287 LC = RTLIB::MUL_I16;
3288 else if (WideVT == MVT::i32)
3289 LC = RTLIB::MUL_I32;
3290 else if (WideVT == MVT::i64)
3291 LC = RTLIB::MUL_I64;
3292 else if (WideVT == MVT::i128)
3293 LC = RTLIB::MUL_I128;
3294 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!");
3296 // The high part is obtained by SRA'ing all but one of the bits of low
3298 unsigned LoSize = VT.getSizeInBits();
3299 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, RHS,
3300 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
3301 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, VT, LHS,
3302 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
3304 // Here we're passing the 2 arguments explicitly as 4 arguments that are
3305 // pre-lowered to the correct types. This all depends upon WideVT not
3306 // being a legal type for the architecture and thus has to be split to
3308 SDValue Args[] = { LHS, HiLHS, RHS, HiRHS };
3309 SDValue Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl);
3310 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3311 DAG.getIntPtrConstant(0));
3312 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3313 DAG.getIntPtrConstant(1));
3314 // Ret is a node with an illegal type. Because such things are not
3315 // generally permitted during this phase of legalization, delete the
3316 // node. The above EXTRACT_ELEMENT nodes should have been folded.
3317 DAG.DeleteNode(Ret.getNode());
3321 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1,
3322 TLI.getShiftAmountTy(BottomHalf.getValueType()));
3323 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3324 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1,
3327 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf,
3328 DAG.getConstant(0, VT), ISD::SETNE);
3330 Results.push_back(BottomHalf);
3331 Results.push_back(TopHalf);
3334 case ISD::BUILD_PAIR: {
3335 EVT PairTy = Node->getValueType(0);
3336 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3337 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3338 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
3339 DAG.getConstant(PairTy.getSizeInBits()/2,
3340 TLI.getShiftAmountTy(PairTy)));
3341 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3345 Tmp1 = Node->getOperand(0);
3346 Tmp2 = Node->getOperand(1);
3347 Tmp3 = Node->getOperand(2);
3348 if (Tmp1.getOpcode() == ISD::SETCC) {
3349 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3351 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3353 Tmp1 = DAG.getSelectCC(dl, Tmp1,
3354 DAG.getConstant(0, Tmp1.getValueType()),
3355 Tmp2, Tmp3, ISD::SETNE);
3357 Results.push_back(Tmp1);
3360 SDValue Chain = Node->getOperand(0);
3361 SDValue Table = Node->getOperand(1);
3362 SDValue Index = Node->getOperand(2);
3364 EVT PTy = TLI.getPointerTy();
3366 const TargetData &TD = *TLI.getTargetData();
3367 unsigned EntrySize =
3368 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
3370 Index = DAG.getNode(ISD::MUL, dl, PTy,
3371 Index, DAG.getConstant(EntrySize, PTy));
3372 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
3374 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
3375 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
3376 MachinePointerInfo::getJumpTable(), MemVT,
3379 if (TM.getRelocationModel() == Reloc::PIC_) {
3380 // For PIC, the sequence is:
3381 // BRIND(load(Jumptable + index) + RelocBase)
3382 // RelocBase can be JumpTable, GOT or some sort of global base.
3383 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3384 TLI.getPICJumpTableRelocBase(Table, DAG));
3386 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
3387 Results.push_back(Tmp1);
3391 // Expand brcond's setcc into its constituent parts and create a BR_CC
3393 Tmp1 = Node->getOperand(0);
3394 Tmp2 = Node->getOperand(1);
3395 if (Tmp2.getOpcode() == ISD::SETCC) {
3396 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3397 Tmp1, Tmp2.getOperand(2),
3398 Tmp2.getOperand(0), Tmp2.getOperand(1),
3399 Node->getOperand(2));
3401 // We test only the i1 bit. Skip the AND if UNDEF.
3402 Tmp3 = (Tmp2.getOpcode() == ISD::UNDEF) ? Tmp2 :
3403 DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2,
3404 DAG.getConstant(1, Tmp2.getValueType()));
3405 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3406 DAG.getCondCode(ISD::SETNE), Tmp3,
3407 DAG.getConstant(0, Tmp3.getValueType()),
3408 Node->getOperand(2));
3410 Results.push_back(Tmp1);
3413 Tmp1 = Node->getOperand(0);
3414 Tmp2 = Node->getOperand(1);
3415 Tmp3 = Node->getOperand(2);
3416 LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl);
3418 // If we expanded the SETCC into an AND/OR, return the new node
3419 if (Tmp2.getNode() == 0) {
3420 Results.push_back(Tmp1);
3424 // Otherwise, SETCC for the given comparison type must be completely
3425 // illegal; expand it into a SELECT_CC.
3426 EVT VT = Node->getValueType(0);
3427 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3428 DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3);
3429 Results.push_back(Tmp1);
3432 case ISD::SELECT_CC: {
3433 Tmp1 = Node->getOperand(0); // LHS
3434 Tmp2 = Node->getOperand(1); // RHS
3435 Tmp3 = Node->getOperand(2); // True
3436 Tmp4 = Node->getOperand(3); // False
3437 SDValue CC = Node->getOperand(4);
3439 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()),
3440 Tmp1, Tmp2, CC, dl);
3442 assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!");
3443 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3444 CC = DAG.getCondCode(ISD::SETNE);
3445 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2,
3447 Results.push_back(Tmp1);
3451 Tmp1 = Node->getOperand(0); // Chain
3452 Tmp2 = Node->getOperand(2); // LHS
3453 Tmp3 = Node->getOperand(3); // RHS
3454 Tmp4 = Node->getOperand(1); // CC
3456 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()),
3457 Tmp2, Tmp3, Tmp4, dl);
3459 assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!");
3460 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
3461 Tmp4 = DAG.getCondCode(ISD::SETNE);
3462 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2,
3463 Tmp3, Node->getOperand(4));
3464 Results.push_back(Tmp1);
3467 case ISD::BUILD_VECTOR:
3468 Results.push_back(ExpandBUILD_VECTOR(Node));
3473 // Scalarize vector SRA/SRL/SHL.
3474 EVT VT = Node->getValueType(0);
3475 assert(VT.isVector() && "Unable to legalize non-vector shift");
3476 assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
3477 unsigned NumElem = VT.getVectorNumElements();
3479 SmallVector<SDValue, 8> Scalars;
3480 for (unsigned Idx = 0; Idx < NumElem; Idx++) {
3481 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3483 Node->getOperand(0), DAG.getIntPtrConstant(Idx));
3484 SDValue Sh = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3486 Node->getOperand(1), DAG.getIntPtrConstant(Idx));
3487 Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
3488 VT.getScalarType(), Ex, Sh));
3491 DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0),
3492 &Scalars[0], Scalars.size());
3493 ReplaceNode(SDValue(Node, 0), Result);
3496 case ISD::GLOBAL_OFFSET_TABLE:
3497 case ISD::GlobalAddress:
3498 case ISD::GlobalTLSAddress:
3499 case ISD::ExternalSymbol:
3500 case ISD::ConstantPool:
3501 case ISD::JumpTable:
3502 case ISD::INTRINSIC_W_CHAIN:
3503 case ISD::INTRINSIC_WO_CHAIN:
3504 case ISD::INTRINSIC_VOID:
3505 // FIXME: Custom lowering for these operations shouldn't return null!
3509 // Replace the original node with the legalized result.
3510 if (!Results.empty())
3511 ReplaceNode(Node, Results.data());
3514 void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
3515 SmallVector<SDValue, 8> Results;
3516 EVT OVT = Node->getValueType(0);
3517 if (Node->getOpcode() == ISD::UINT_TO_FP ||
3518 Node->getOpcode() == ISD::SINT_TO_FP ||
3519 Node->getOpcode() == ISD::SETCC) {
3520 OVT = Node->getOperand(0).getValueType();
3522 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3523 DebugLoc dl = Node->getDebugLoc();
3524 SDValue Tmp1, Tmp2, Tmp3;
3525 switch (Node->getOpcode()) {
3527 case ISD::CTTZ_ZERO_UNDEF:
3529 case ISD::CTLZ_ZERO_UNDEF:
3531 // Zero extend the argument.
3532 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3533 // Perform the larger operation. For CTPOP and CTTZ_ZERO_UNDEF, this is
3534 // already the correct result.
3535 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
3536 if (Node->getOpcode() == ISD::CTTZ) {
3537 // FIXME: This should set a bit in the zero extended value instead.
3538 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
3539 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
3541 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
3542 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3543 } else if (Node->getOpcode() == ISD::CTLZ ||
3544 Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) {
3545 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3546 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
3547 DAG.getConstant(NVT.getSizeInBits() -
3548 OVT.getSizeInBits(), NVT));
3550 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
3553 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3554 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3555 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
3556 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
3557 DAG.getConstant(DiffBits, TLI.getShiftAmountTy(NVT)));
3558 Results.push_back(Tmp1);
3561 case ISD::FP_TO_UINT:
3562 case ISD::FP_TO_SINT:
3563 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
3564 Node->getOpcode() == ISD::FP_TO_SINT, dl);
3565 Results.push_back(Tmp1);
3567 case ISD::UINT_TO_FP:
3568 case ISD::SINT_TO_FP:
3569 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
3570 Node->getOpcode() == ISD::SINT_TO_FP, dl);
3571 Results.push_back(Tmp1);
3574 SDValue Chain = Node->getOperand(0); // Get the chain.
3575 SDValue Ptr = Node->getOperand(1); // Get the pointer.
3578 if (OVT.isVector()) {
3579 TruncOp = ISD::BITCAST;
3581 assert(OVT.isInteger()
3582 && "VAARG promotion is supported only for vectors or integer types");
3583 TruncOp = ISD::TRUNCATE;
3586 // Perform the larger operation, then convert back
3587 Tmp1 = DAG.getVAArg(NVT, dl, Chain, Ptr, Node->getOperand(2),
3588 Node->getConstantOperandVal(3));
3589 Chain = Tmp1.getValue(1);
3591 Tmp2 = DAG.getNode(TruncOp, dl, OVT, Tmp1);
3593 // Modified the chain result - switch anything that used the old chain to
3595 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp2);
3596 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
3603 unsigned ExtOp, TruncOp;
3604 if (OVT.isVector()) {
3605 ExtOp = ISD::BITCAST;
3606 TruncOp = ISD::BITCAST;
3608 assert(OVT.isInteger() && "Cannot promote logic operation");
3609 ExtOp = ISD::ANY_EXTEND;
3610 TruncOp = ISD::TRUNCATE;
3612 // Promote each of the values to the new type.
3613 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3614 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3615 // Perform the larger operation, then convert back
3616 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3617 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
3621 unsigned ExtOp, TruncOp;
3622 if (Node->getValueType(0).isVector()) {
3623 ExtOp = ISD::BITCAST;
3624 TruncOp = ISD::BITCAST;
3625 } else if (Node->getValueType(0).isInteger()) {
3626 ExtOp = ISD::ANY_EXTEND;
3627 TruncOp = ISD::TRUNCATE;
3629 ExtOp = ISD::FP_EXTEND;
3630 TruncOp = ISD::FP_ROUND;
3632 Tmp1 = Node->getOperand(0);
3633 // Promote each of the values to the new type.
3634 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3635 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
3636 // Perform the larger operation, then round down.
3637 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3);
3638 if (TruncOp != ISD::FP_ROUND)
3639 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
3641 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
3642 DAG.getIntPtrConstant(0));
3643 Results.push_back(Tmp1);
3646 case ISD::VECTOR_SHUFFLE: {
3647 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
3649 // Cast the two input vectors.
3650 Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
3651 Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
3653 // Convert the shuffle mask to the right # elements.
3654 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
3655 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
3656 Results.push_back(Tmp1);
3660 unsigned ExtOp = ISD::FP_EXTEND;
3661 if (NVT.isInteger()) {
3662 ISD::CondCode CCCode =
3663 cast<CondCodeSDNode>(Node->getOperand(2))->get();
3664 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3666 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3667 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3668 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3669 Tmp1, Tmp2, Node->getOperand(2)));
3675 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
3676 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
3677 Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3678 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
3679 Tmp3, DAG.getIntPtrConstant(0)));
3686 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
3687 Tmp2 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
3688 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
3689 Tmp2, DAG.getIntPtrConstant(0)));
3694 // Replace the original node with the legalized result.
3695 if (!Results.empty())
3696 ReplaceNode(Node, Results.data());
3699 // SelectionDAG::Legalize - This is the entry point for the file.
3701 void SelectionDAG::Legalize() {
3702 /// run - This is the main entry point to this class.
3704 SelectionDAGLegalize(*this).LegalizeDAG();