1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/CodeGen/PseudoSourceValue.h"
20 #include "llvm/Target/TargetFrameInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/Target/TargetData.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/Target/TargetSubtarget.h"
26 #include "llvm/CallingConv.h"
27 #include "llvm/Constants.h"
28 #include "llvm/DerivedTypes.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Compiler.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/ADT/DenseMap.h"
33 #include "llvm/ADT/SmallVector.h"
34 #include "llvm/ADT/SmallPtrSet.h"
40 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
41 cl::desc("Pop up a window to show dags before legalize"));
43 static const bool ViewLegalizeDAGs = 0;
46 //===----------------------------------------------------------------------===//
47 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
48 /// hacks on it until the target machine can handle it. This involves
49 /// eliminating value sizes the machine cannot handle (promoting small sizes to
50 /// large sizes or splitting up large values into small values) as well as
51 /// eliminating operations the machine cannot handle.
53 /// This code also does a small amount of optimization and recognition of idioms
54 /// as part of its processing. For example, if a target does not support a
55 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
56 /// will attempt merge setcc and brc instructions into brcc's.
59 class VISIBILITY_HIDDEN SelectionDAGLegalize {
63 // Libcall insertion helpers.
65 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
66 /// legalized. We use this to ensure that calls are properly serialized
67 /// against each other, including inserted libcalls.
68 SDOperand LastCALLSEQ_END;
70 /// IsLegalizingCall - This member is used *only* for purposes of providing
71 /// helpful assertions that a libcall isn't created while another call is
72 /// being legalized (which could lead to non-serialized call sequences).
73 bool IsLegalizingCall;
76 Legal, // The target natively supports this operation.
77 Promote, // This operation should be executed in a larger type.
78 Expand // Try to expand this to other ops, otherwise use a libcall.
81 /// ValueTypeActions - This is a bitvector that contains two bits for each
82 /// value type, where the two bits correspond to the LegalizeAction enum.
83 /// This can be queried with "getTypeAction(VT)".
84 TargetLowering::ValueTypeActionImpl ValueTypeActions;
86 /// LegalizedNodes - For nodes that are of legal width, and that have more
87 /// than one use, this map indicates what regularized operand to use. This
88 /// allows us to avoid legalizing the same thing more than once.
89 DenseMap<SDOperandImpl, SDOperand> LegalizedNodes;
91 /// PromotedNodes - For nodes that are below legal width, and that have more
92 /// than one use, this map indicates what promoted value to use. This allows
93 /// us to avoid promoting the same thing more than once.
94 DenseMap<SDOperandImpl, SDOperand> PromotedNodes;
96 /// ExpandedNodes - For nodes that need to be expanded this map indicates
97 /// which which operands are the expanded version of the input. This allows
98 /// us to avoid expanding the same node more than once.
99 DenseMap<SDOperandImpl, std::pair<SDOperand, SDOperand> > ExpandedNodes;
101 /// SplitNodes - For vector nodes that need to be split, this map indicates
102 /// which which operands are the split version of the input. This allows us
103 /// to avoid splitting the same node more than once.
104 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
106 /// ScalarizedNodes - For nodes that need to be converted from vector types to
107 /// scalar types, this contains the mapping of ones we have already
108 /// processed to the result.
109 std::map<SDOperand, SDOperand> ScalarizedNodes;
111 void AddLegalizedOperand(SDOperand From, SDOperand To) {
112 LegalizedNodes.insert(std::make_pair(From, To));
113 // If someone requests legalization of the new node, return itself.
115 LegalizedNodes.insert(std::make_pair(To, To));
117 void AddPromotedOperand(SDOperand From, SDOperand To) {
118 bool isNew = PromotedNodes.insert(std::make_pair(From, To));
119 assert(isNew && "Got into the map somehow?");
120 // If someone requests legalization of the new node, return itself.
121 LegalizedNodes.insert(std::make_pair(To, To));
126 SelectionDAGLegalize(SelectionDAG &DAG);
128 /// getTypeAction - Return how we should legalize values of this type, either
129 /// it is already legal or we need to expand it into multiple registers of
130 /// smaller integer type, or we need to promote it to a larger type.
131 LegalizeAction getTypeAction(MVT::ValueType VT) const {
132 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
135 /// isTypeLegal - Return true if this type is legal on this target.
137 bool isTypeLegal(MVT::ValueType VT) const {
138 return getTypeAction(VT) == Legal;
144 /// HandleOp - Legalize, Promote, or Expand the specified operand as
145 /// appropriate for its type.
146 void HandleOp(SDOperand Op);
148 /// LegalizeOp - We know that the specified value has a legal type.
149 /// Recursively ensure that the operands have legal types, then return the
151 SDOperand LegalizeOp(SDOperand O);
153 /// UnrollVectorOp - We know that the given vector has a legal type, however
154 /// the operation it performs is not legal and is an operation that we have
155 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
156 /// operating on each element individually.
157 SDOperand UnrollVectorOp(SDOperand O);
159 /// PromoteOp - Given an operation that produces a value in an invalid type,
160 /// promote it to compute the value into a larger type. The produced value
161 /// will have the correct bits for the low portion of the register, but no
162 /// guarantee is made about the top bits: it may be zero, sign-extended, or
164 SDOperand PromoteOp(SDOperand O);
166 /// ExpandOp - Expand the specified SDOperand into its two component pieces
167 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
168 /// the LegalizeNodes map is filled in for any results that are not expanded,
169 /// the ExpandedNodes map is filled in for any results that are expanded, and
170 /// the Lo/Hi values are returned. This applies to integer types and Vector
172 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
174 /// SplitVectorOp - Given an operand of vector type, break it down into
175 /// two smaller values.
176 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
178 /// ScalarizeVectorOp - Given an operand of single-element vector type
179 /// (e.g. v1f32), convert it into the equivalent operation that returns a
180 /// scalar (e.g. f32) value.
181 SDOperand ScalarizeVectorOp(SDOperand O);
183 /// isShuffleLegal - Return true if a vector shuffle is legal with the
184 /// specified mask and type. Targets can specify exactly which masks they
185 /// support and the code generator is tasked with not creating illegal masks.
187 /// Note that this will also return true for shuffles that are promoted to a
190 /// If this is a legal shuffle, this method returns the (possibly promoted)
191 /// build_vector Mask. If it's not a legal shuffle, it returns null.
192 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
194 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
195 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
197 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
199 SDOperand ExpandLibCall(const char *Name, SDNode *Node, bool isSigned,
201 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
204 SDOperand EmitStackConvert(SDOperand SrcOp, MVT::ValueType SlotVT,
205 MVT::ValueType DestVT);
206 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
207 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
208 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
210 MVT::ValueType DestVT);
211 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
213 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
216 SDOperand ExpandBSWAP(SDOperand Op);
217 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
218 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
219 SDOperand &Lo, SDOperand &Hi);
220 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
221 SDOperand &Lo, SDOperand &Hi);
223 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op);
224 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
228 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
229 /// specified mask and type. Targets can specify exactly which masks they
230 /// support and the code generator is tasked with not creating illegal masks.
232 /// Note that this will also return true for shuffles that are promoted to a
234 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
235 SDOperand Mask) const {
236 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
238 case TargetLowering::Legal:
239 case TargetLowering::Custom:
241 case TargetLowering::Promote: {
242 // If this is promoted to a different type, convert the shuffle mask and
243 // ask if it is legal in the promoted type!
244 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
246 // If we changed # elements, change the shuffle mask.
247 unsigned NumEltsGrowth =
248 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
249 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
250 if (NumEltsGrowth > 1) {
251 // Renumber the elements.
252 SmallVector<SDOperand, 8> Ops;
253 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
254 SDOperand InOp = Mask.getOperand(i);
255 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
256 if (InOp.getOpcode() == ISD::UNDEF)
257 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
259 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
260 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
264 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
270 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
273 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
274 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
275 ValueTypeActions(TLI.getValueTypeActions()) {
276 assert(MVT::LAST_VALUETYPE <= 32 &&
277 "Too many value types for ValueTypeActions to hold!");
280 /// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order
281 /// contains all of a nodes operands before it contains the node.
282 static void ComputeTopDownOrdering(SelectionDAG &DAG,
283 SmallVector<SDNode*, 64> &Order) {
285 DenseMap<SDNode*, unsigned> Visited;
286 std::vector<SDNode*> Worklist;
287 Worklist.reserve(128);
289 // Compute ordering from all of the leaves in the graphs, those (like the
290 // entry node) that have no operands.
291 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
292 E = DAG.allnodes_end(); I != E; ++I) {
293 if (I->getNumOperands() == 0) {
295 Worklist.push_back(I);
299 while (!Worklist.empty()) {
300 SDNode *N = Worklist.back();
303 if (++Visited[N] != N->getNumOperands())
304 continue; // Haven't visited all operands yet
308 // Now that we have N in, add anything that uses it if all of their operands
310 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
312 Worklist.push_back(UI->getUser());
315 assert(Order.size() == Visited.size() &&
317 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
318 "Error: DAG is cyclic!");
322 void SelectionDAGLegalize::LegalizeDAG() {
323 LastCALLSEQ_END = DAG.getEntryNode();
324 IsLegalizingCall = false;
326 // The legalize process is inherently a bottom-up recursive process (users
327 // legalize their uses before themselves). Given infinite stack space, we
328 // could just start legalizing on the root and traverse the whole graph. In
329 // practice however, this causes us to run out of stack space on large basic
330 // blocks. To avoid this problem, compute an ordering of the nodes where each
331 // node is only legalized after all of its operands are legalized.
332 SmallVector<SDNode*, 64> Order;
333 ComputeTopDownOrdering(DAG, Order);
335 for (unsigned i = 0, e = Order.size(); i != e; ++i)
336 HandleOp(SDOperand(Order[i], 0));
338 // Finally, it's possible the root changed. Get the new root.
339 SDOperand OldRoot = DAG.getRoot();
340 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
341 DAG.setRoot(LegalizedNodes[OldRoot]);
343 ExpandedNodes.clear();
344 LegalizedNodes.clear();
345 PromotedNodes.clear();
347 ScalarizedNodes.clear();
349 // Remove dead nodes now.
350 DAG.RemoveDeadNodes();
354 /// FindCallEndFromCallStart - Given a chained node that is part of a call
355 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
356 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
357 if (Node->getOpcode() == ISD::CALLSEQ_END)
359 if (Node->use_empty())
360 return 0; // No CallSeqEnd
362 // The chain is usually at the end.
363 SDOperand TheChain(Node, Node->getNumValues()-1);
364 if (TheChain.getValueType() != MVT::Other) {
365 // Sometimes it's at the beginning.
366 TheChain = SDOperand(Node, 0);
367 if (TheChain.getValueType() != MVT::Other) {
368 // Otherwise, hunt for it.
369 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
370 if (Node->getValueType(i) == MVT::Other) {
371 TheChain = SDOperand(Node, i);
375 // Otherwise, we walked into a node without a chain.
376 if (TheChain.getValueType() != MVT::Other)
381 for (SDNode::use_iterator UI = Node->use_begin(),
382 E = Node->use_end(); UI != E; ++UI) {
384 // Make sure to only follow users of our token chain.
385 SDNode *User = UI->getUser();
386 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
387 if (User->getOperand(i) == TheChain)
388 if (SDNode *Result = FindCallEndFromCallStart(User))
394 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
395 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
396 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
397 assert(Node && "Didn't find callseq_start for a call??");
398 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
400 assert(Node->getOperand(0).getValueType() == MVT::Other &&
401 "Node doesn't have a token chain argument!");
402 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
405 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
406 /// see if any uses can reach Dest. If no dest operands can get to dest,
407 /// legalize them, legalize ourself, and return false, otherwise, return true.
409 /// Keep track of the nodes we fine that actually do lead to Dest in
410 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
412 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
413 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
414 if (N == Dest) return true; // N certainly leads to Dest :)
416 // If we've already processed this node and it does lead to Dest, there is no
417 // need to reprocess it.
418 if (NodesLeadingTo.count(N)) return true;
420 // If the first result of this node has been already legalized, then it cannot
422 switch (getTypeAction(N->getValueType(0))) {
424 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
427 if (PromotedNodes.count(SDOperand(N, 0))) return false;
430 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
434 // Okay, this node has not already been legalized. Check and legalize all
435 // operands. If none lead to Dest, then we can legalize this node.
436 bool OperandsLeadToDest = false;
437 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
438 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
439 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
441 if (OperandsLeadToDest) {
442 NodesLeadingTo.insert(N);
446 // Okay, this node looks safe, legalize it and return false.
447 HandleOp(SDOperand(N, 0));
451 /// HandleOp - Legalize, Promote, or Expand the specified operand as
452 /// appropriate for its type.
453 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
454 MVT::ValueType VT = Op.getValueType();
455 switch (getTypeAction(VT)) {
456 default: assert(0 && "Bad type action!");
457 case Legal: (void)LegalizeOp(Op); break;
458 case Promote: (void)PromoteOp(Op); break;
460 if (!MVT::isVector(VT)) {
461 // If this is an illegal scalar, expand it into its two component
464 if (Op.getOpcode() == ISD::TargetConstant)
465 break; // Allow illegal target nodes.
467 } else if (MVT::getVectorNumElements(VT) == 1) {
468 // If this is an illegal single element vector, convert it to a
470 (void)ScalarizeVectorOp(Op);
472 // Otherwise, this is an illegal multiple element vector.
473 // Split it in half and legalize both parts.
475 SplitVectorOp(Op, X, Y);
481 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
482 /// a load from the constant pool.
483 static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
484 SelectionDAG &DAG, TargetLowering &TLI) {
487 // If a FP immediate is precise when represented as a float and if the
488 // target can do an extending load from float to double, we put it into
489 // the constant pool as a float, even if it's is statically typed as a
490 // double. This shrinks FP constants and canonicalizes them for targets where
491 // an FP extending load is the same cost as a normal load (such as on the x87
492 // fp stack or PPC FP unit).
493 MVT::ValueType VT = CFP->getValueType(0);
494 ConstantFP *LLVMC = ConstantFP::get(MVT::getTypeForValueType(VT),
497 if (VT!=MVT::f64 && VT!=MVT::f32)
498 assert(0 && "Invalid type expansion");
499 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt(),
500 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
503 MVT::ValueType OrigVT = VT;
504 MVT::ValueType SVT = VT;
505 while (SVT != MVT::f32) {
506 SVT = (unsigned)SVT - 1;
507 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
508 // Only do this if the target has a native EXTLOAD instruction from
510 TLI.isLoadXLegal(ISD::EXTLOAD, SVT) &&
511 TLI.ShouldShrinkFPConstant(OrigVT)) {
512 const Type *SType = MVT::getTypeForValueType(SVT);
513 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
519 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
521 return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, DAG.getEntryNode(),
522 CPIdx, PseudoSourceValue::getConstantPool(),
524 return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx,
525 PseudoSourceValue::getConstantPool(), 0);
529 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
532 SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT,
533 SelectionDAG &DAG, TargetLowering &TLI) {
534 MVT::ValueType VT = Node->getValueType(0);
535 MVT::ValueType SrcVT = Node->getOperand(1).getValueType();
536 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
537 "fcopysign expansion only supported for f32 and f64");
538 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
540 // First get the sign bit of second operand.
541 SDOperand Mask1 = (SrcVT == MVT::f64)
542 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
543 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
544 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
545 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
546 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
547 // Shift right or sign-extend it if the two operands have different types.
548 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT);
550 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
551 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
552 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
553 } else if (SizeDiff < 0)
554 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit);
556 // Clear the sign bit of first operand.
557 SDOperand Mask2 = (VT == MVT::f64)
558 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
559 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
560 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
561 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
562 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
564 // Or the value with the sign bit.
565 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
569 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
571 SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
572 TargetLowering &TLI) {
573 SDOperand Chain = ST->getChain();
574 SDOperand Ptr = ST->getBasePtr();
575 SDOperand Val = ST->getValue();
576 MVT::ValueType VT = Val.getValueType();
577 int Alignment = ST->getAlignment();
578 int SVOffset = ST->getSrcValueOffset();
579 if (MVT::isFloatingPoint(ST->getMemoryVT()) ||
580 MVT::isVector(ST->getMemoryVT())) {
581 // Expand to a bitconvert of the value to the integer type of the
582 // same size, then a (misaligned) int store.
583 MVT::ValueType intVT;
584 if (MVT::is128BitVector(VT) || VT == MVT::ppcf128 || VT == MVT::f128)
586 else if (MVT::is64BitVector(VT) || VT==MVT::f64)
588 else if (VT==MVT::f32)
591 assert(0 && "Unaligned store of unsupported type");
593 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val);
594 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(),
595 SVOffset, ST->isVolatile(), Alignment);
597 assert(MVT::isInteger(ST->getMemoryVT()) &&
598 !MVT::isVector(ST->getMemoryVT()) &&
599 "Unaligned store of unknown type.");
600 // Get the half-size VT
601 MVT::ValueType NewStoredVT = ST->getMemoryVT() - 1;
602 int NumBits = MVT::getSizeInBits(NewStoredVT);
603 int IncrementSize = NumBits / 8;
605 // Divide the stored value in two parts.
606 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
608 SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
610 // Store the two parts
611 SDOperand Store1, Store2;
612 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr,
613 ST->getSrcValue(), SVOffset, NewStoredVT,
614 ST->isVolatile(), Alignment);
615 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
616 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
617 Alignment = MinAlign(Alignment, IncrementSize);
618 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr,
619 ST->getSrcValue(), SVOffset + IncrementSize,
620 NewStoredVT, ST->isVolatile(), Alignment);
622 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2);
625 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
627 SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
628 TargetLowering &TLI) {
629 int SVOffset = LD->getSrcValueOffset();
630 SDOperand Chain = LD->getChain();
631 SDOperand Ptr = LD->getBasePtr();
632 MVT::ValueType VT = LD->getValueType(0);
633 MVT::ValueType LoadedVT = LD->getMemoryVT();
634 if (MVT::isFloatingPoint(VT) || MVT::isVector(VT)) {
635 // Expand to a (misaligned) integer load of the same size,
636 // then bitconvert to floating point or vector.
637 MVT::ValueType intVT;
638 if (MVT::is128BitVector(LoadedVT) ||
639 LoadedVT == MVT::ppcf128 || LoadedVT == MVT::f128)
641 else if (MVT::is64BitVector(LoadedVT) || LoadedVT == MVT::f64)
643 else if (LoadedVT == MVT::f32)
646 assert(0 && "Unaligned load of unsupported type");
648 SDOperand newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(),
649 SVOffset, LD->isVolatile(),
651 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad);
652 if (MVT::isFloatingPoint(VT) && LoadedVT != VT)
653 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result);
655 SDOperand Ops[] = { Result, Chain };
656 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
659 assert(MVT::isInteger(LoadedVT) && !MVT::isVector(LoadedVT) &&
660 "Unaligned load of unsupported type.");
662 // Compute the new VT that is half the size of the old one. This is an
664 unsigned NumBits = MVT::getSizeInBits(LoadedVT);
665 MVT::ValueType NewLoadedVT;
666 NewLoadedVT = MVT::getIntegerType(NumBits/2);
669 unsigned Alignment = LD->getAlignment();
670 unsigned IncrementSize = NumBits / 8;
671 ISD::LoadExtType HiExtType = LD->getExtensionType();
673 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
674 if (HiExtType == ISD::NON_EXTLOAD)
675 HiExtType = ISD::ZEXTLOAD;
677 // Load the value in two parts
679 if (TLI.isLittleEndian()) {
680 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
681 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
682 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
683 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
684 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(),
685 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
686 MinAlign(Alignment, IncrementSize));
688 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset,
689 NewLoadedVT,LD->isVolatile(), Alignment);
690 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
691 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
692 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
693 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
694 MinAlign(Alignment, IncrementSize));
697 // aggregate the two parts
698 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
699 SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
700 Result = DAG.getNode(ISD::OR, VT, Result, Lo);
702 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
705 SDOperand Ops[] = { Result, TF };
706 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2);
709 /// UnrollVectorOp - We know that the given vector has a legal type, however
710 /// the operation it performs is not legal and is an operation that we have
711 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
712 /// operating on each element individually.
713 SDOperand SelectionDAGLegalize::UnrollVectorOp(SDOperand Op) {
714 MVT::ValueType VT = Op.getValueType();
715 assert(isTypeLegal(VT) &&
716 "Caller should expand or promote operands that are not legal!");
717 assert(Op.Val->getNumValues() == 1 &&
718 "Can't unroll a vector with multiple results!");
719 unsigned NE = MVT::getVectorNumElements(VT);
720 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
722 SmallVector<SDOperand, 8> Scalars;
723 SmallVector<SDOperand, 4> Operands(Op.getNumOperands());
724 for (unsigned i = 0; i != NE; ++i) {
725 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
726 SDOperand Operand = Op.getOperand(j);
727 MVT::ValueType OperandVT = Operand.getValueType();
728 if (MVT::isVector(OperandVT)) {
729 // A vector operand; extract a single element.
730 MVT::ValueType OperandEltVT = MVT::getVectorElementType(OperandVT);
731 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
734 DAG.getConstant(i, MVT::i32));
736 // A scalar operand; just use it as is.
737 Operands[j] = Operand;
740 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT,
741 &Operands[0], Operands.size()));
744 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size());
747 /// GetFPLibCall - Return the right libcall for the given floating point type.
748 static RTLIB::Libcall GetFPLibCall(MVT::ValueType VT,
749 RTLIB::Libcall Call_F32,
750 RTLIB::Libcall Call_F64,
751 RTLIB::Libcall Call_F80,
752 RTLIB::Libcall Call_PPCF128) {
754 VT == MVT::f32 ? Call_F32 :
755 VT == MVT::f64 ? Call_F64 :
756 VT == MVT::f80 ? Call_F80 :
757 VT == MVT::ppcf128 ? Call_PPCF128 :
758 RTLIB::UNKNOWN_LIBCALL;
761 /// LegalizeOp - We know that the specified value has a legal type, and
762 /// that its operands are legal. Now ensure that the operation itself
763 /// is legal, recursively ensuring that the operands' operations remain
765 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
766 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
769 assert(isTypeLegal(Op.getValueType()) &&
770 "Caller should expand or promote operands that are not legal!");
771 SDNode *Node = Op.Val;
773 // If this operation defines any values that cannot be represented in a
774 // register on this target, make sure to expand or promote them.
775 if (Node->getNumValues() > 1) {
776 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
777 if (getTypeAction(Node->getValueType(i)) != Legal) {
778 HandleOp(Op.getValue(i));
779 assert(LegalizedNodes.count(Op) &&
780 "Handling didn't add legal operands!");
781 return LegalizedNodes[Op];
785 // Note that LegalizeOp may be reentered even from single-use nodes, which
786 // means that we always must cache transformed nodes.
787 DenseMap<SDOperandImpl, SDOperand>::iterator I = LegalizedNodes.find(Op);
788 if (I != LegalizedNodes.end()) return I->second;
790 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
791 SDOperand Result = Op;
792 bool isCustom = false;
794 switch (Node->getOpcode()) {
795 case ISD::FrameIndex:
796 case ISD::EntryToken:
798 case ISD::BasicBlock:
799 case ISD::TargetFrameIndex:
800 case ISD::TargetJumpTable:
801 case ISD::TargetConstant:
802 case ISD::TargetConstantFP:
803 case ISD::TargetConstantPool:
804 case ISD::TargetGlobalAddress:
805 case ISD::TargetGlobalTLSAddress:
806 case ISD::TargetExternalSymbol:
809 case ISD::MEMOPERAND:
813 // Primitives must all be legal.
814 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
815 "This must be legal!");
818 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
819 // If this is a target node, legalize it by legalizing the operands then
820 // passing it through.
821 SmallVector<SDOperand, 8> Ops;
822 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
823 Ops.push_back(LegalizeOp(Node->getOperand(i)));
825 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
827 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
828 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
829 return Result.getValue(Op.ResNo);
831 // Otherwise this is an unhandled builtin node. splat.
833 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
835 assert(0 && "Do not know how to legalize this operator!");
837 case ISD::GLOBAL_OFFSET_TABLE:
838 case ISD::GlobalAddress:
839 case ISD::GlobalTLSAddress:
840 case ISD::ExternalSymbol:
841 case ISD::ConstantPool:
842 case ISD::JumpTable: // Nothing to do.
843 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
844 default: assert(0 && "This action is not supported yet!");
845 case TargetLowering::Custom:
846 Tmp1 = TLI.LowerOperation(Op, DAG);
847 if (Tmp1.Val) Result = Tmp1;
848 // FALLTHROUGH if the target doesn't want to lower this op after all.
849 case TargetLowering::Legal:
854 case ISD::RETURNADDR:
855 // The only option for these nodes is to custom lower them. If the target
856 // does not custom lower them, then return zero.
857 Tmp1 = TLI.LowerOperation(Op, DAG);
861 Result = DAG.getConstant(0, TLI.getPointerTy());
863 case ISD::FRAME_TO_ARGS_OFFSET: {
864 MVT::ValueType VT = Node->getValueType(0);
865 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
866 default: assert(0 && "This action is not supported yet!");
867 case TargetLowering::Custom:
868 Result = TLI.LowerOperation(Op, DAG);
869 if (Result.Val) break;
871 case TargetLowering::Legal:
872 Result = DAG.getConstant(0, VT);
877 case ISD::EXCEPTIONADDR: {
878 Tmp1 = LegalizeOp(Node->getOperand(0));
879 MVT::ValueType VT = Node->getValueType(0);
880 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
881 default: assert(0 && "This action is not supported yet!");
882 case TargetLowering::Expand: {
883 unsigned Reg = TLI.getExceptionAddressRegister();
884 Result = DAG.getCopyFromReg(Tmp1, Reg, VT);
887 case TargetLowering::Custom:
888 Result = TLI.LowerOperation(Op, DAG);
889 if (Result.Val) break;
891 case TargetLowering::Legal: {
892 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 };
893 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
899 if (Result.Val->getNumValues() == 1) break;
901 assert(Result.Val->getNumValues() == 2 &&
902 "Cannot return more than two values!");
904 // Since we produced two values, make sure to remember that we
905 // legalized both of them.
906 Tmp1 = LegalizeOp(Result);
907 Tmp2 = LegalizeOp(Result.getValue(1));
908 AddLegalizedOperand(Op.getValue(0), Tmp1);
909 AddLegalizedOperand(Op.getValue(1), Tmp2);
910 return Op.ResNo ? Tmp2 : Tmp1;
911 case ISD::EHSELECTION: {
912 Tmp1 = LegalizeOp(Node->getOperand(0));
913 Tmp2 = LegalizeOp(Node->getOperand(1));
914 MVT::ValueType VT = Node->getValueType(0);
915 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
916 default: assert(0 && "This action is not supported yet!");
917 case TargetLowering::Expand: {
918 unsigned Reg = TLI.getExceptionSelectorRegister();
919 Result = DAG.getCopyFromReg(Tmp2, Reg, VT);
922 case TargetLowering::Custom:
923 Result = TLI.LowerOperation(Op, DAG);
924 if (Result.Val) break;
926 case TargetLowering::Legal: {
927 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 };
928 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
934 if (Result.Val->getNumValues() == 1) break;
936 assert(Result.Val->getNumValues() == 2 &&
937 "Cannot return more than two values!");
939 // Since we produced two values, make sure to remember that we
940 // legalized both of them.
941 Tmp1 = LegalizeOp(Result);
942 Tmp2 = LegalizeOp(Result.getValue(1));
943 AddLegalizedOperand(Op.getValue(0), Tmp1);
944 AddLegalizedOperand(Op.getValue(1), Tmp2);
945 return Op.ResNo ? Tmp2 : Tmp1;
946 case ISD::EH_RETURN: {
947 MVT::ValueType VT = Node->getValueType(0);
948 // The only "good" option for this node is to custom lower it.
949 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
950 default: assert(0 && "This action is not supported at all!");
951 case TargetLowering::Custom:
952 Result = TLI.LowerOperation(Op, DAG);
953 if (Result.Val) break;
955 case TargetLowering::Legal:
956 // Target does not know, how to lower this, lower to noop
957 Result = LegalizeOp(Node->getOperand(0));
962 case ISD::AssertSext:
963 case ISD::AssertZext:
964 Tmp1 = LegalizeOp(Node->getOperand(0));
965 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
967 case ISD::MERGE_VALUES:
968 // Legalize eliminates MERGE_VALUES nodes.
969 Result = Node->getOperand(Op.ResNo);
971 case ISD::CopyFromReg:
972 Tmp1 = LegalizeOp(Node->getOperand(0));
973 Result = Op.getValue(0);
974 if (Node->getNumValues() == 2) {
975 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
977 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
978 if (Node->getNumOperands() == 3) {
979 Tmp2 = LegalizeOp(Node->getOperand(2));
980 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
982 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
984 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
986 // Since CopyFromReg produces two values, make sure to remember that we
987 // legalized both of them.
988 AddLegalizedOperand(Op.getValue(0), Result);
989 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
990 return Result.getValue(Op.ResNo);
992 MVT::ValueType VT = Op.getValueType();
993 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
994 default: assert(0 && "This action is not supported yet!");
995 case TargetLowering::Expand:
996 if (MVT::isInteger(VT))
997 Result = DAG.getConstant(0, VT);
998 else if (MVT::isFloatingPoint(VT))
999 Result = DAG.getConstantFP(APFloat(APInt(MVT::getSizeInBits(VT), 0)),
1002 assert(0 && "Unknown value type!");
1004 case TargetLowering::Legal:
1010 case ISD::INTRINSIC_W_CHAIN:
1011 case ISD::INTRINSIC_WO_CHAIN:
1012 case ISD::INTRINSIC_VOID: {
1013 SmallVector<SDOperand, 8> Ops;
1014 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1015 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1016 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1018 // Allow the target to custom lower its intrinsics if it wants to.
1019 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
1020 TargetLowering::Custom) {
1021 Tmp3 = TLI.LowerOperation(Result, DAG);
1022 if (Tmp3.Val) Result = Tmp3;
1025 if (Result.Val->getNumValues() == 1) break;
1027 // Must have return value and chain result.
1028 assert(Result.Val->getNumValues() == 2 &&
1029 "Cannot return more than two values!");
1031 // Since loads produce two values, make sure to remember that we
1032 // legalized both of them.
1033 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1034 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1035 return Result.getValue(Op.ResNo);
1039 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
1040 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
1042 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
1043 case TargetLowering::Promote:
1044 default: assert(0 && "This action is not supported yet!");
1045 case TargetLowering::Expand: {
1046 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
1047 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
1048 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other);
1050 if (MMI && (useDEBUG_LOC || useLABEL)) {
1051 const std::string &FName =
1052 cast<StringSDNode>(Node->getOperand(3))->getValue();
1053 const std::string &DirName =
1054 cast<StringSDNode>(Node->getOperand(4))->getValue();
1055 unsigned SrcFile = MMI->RecordSource(DirName, FName);
1057 SmallVector<SDOperand, 8> Ops;
1058 Ops.push_back(Tmp1); // chain
1059 SDOperand LineOp = Node->getOperand(1);
1060 SDOperand ColOp = Node->getOperand(2);
1063 Ops.push_back(LineOp); // line #
1064 Ops.push_back(ColOp); // col #
1065 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
1066 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
1068 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
1069 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
1070 unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile);
1071 Ops.push_back(DAG.getConstant(ID, MVT::i32));
1072 Ops.push_back(DAG.getConstant(0, MVT::i32)); // a debug label
1073 Result = DAG.getNode(ISD::LABEL, MVT::Other, &Ops[0], Ops.size());
1076 Result = Tmp1; // chain
1080 case TargetLowering::Legal:
1081 if (Tmp1 != Node->getOperand(0) ||
1082 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
1083 SmallVector<SDOperand, 8> Ops;
1084 Ops.push_back(Tmp1);
1085 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
1086 Ops.push_back(Node->getOperand(1)); // line # must be legal.
1087 Ops.push_back(Node->getOperand(2)); // col # must be legal.
1089 // Otherwise promote them.
1090 Ops.push_back(PromoteOp(Node->getOperand(1)));
1091 Ops.push_back(PromoteOp(Node->getOperand(2)));
1093 Ops.push_back(Node->getOperand(3)); // filename must be legal.
1094 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
1095 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1102 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!");
1103 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) {
1104 default: assert(0 && "This action is not supported yet!");
1105 case TargetLowering::Legal:
1106 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1107 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1108 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable.
1109 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1111 case TargetLowering::Expand:
1112 Result = LegalizeOp(Node->getOperand(0));
1117 case ISD::DEBUG_LOC:
1118 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
1119 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
1120 default: assert(0 && "This action is not supported yet!");
1121 case TargetLowering::Legal:
1122 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1123 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1124 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1125 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1126 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1132 assert(Node->getNumOperands() == 3 && "Invalid LABEL node!");
1133 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) {
1134 default: assert(0 && "This action is not supported yet!");
1135 case TargetLowering::Legal:
1136 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1137 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
1138 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the "flavor" operand.
1139 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1141 case TargetLowering::Expand:
1142 Result = LegalizeOp(Node->getOperand(0));
1148 assert(Node->getNumOperands() == 4 && "Invalid Prefetch node!");
1149 switch (TLI.getOperationAction(ISD::PREFETCH, MVT::Other)) {
1150 default: assert(0 && "This action is not supported yet!");
1151 case TargetLowering::Legal:
1152 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1153 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1154 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the rw specifier.
1155 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize locality specifier.
1156 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1158 case TargetLowering::Expand:
1160 Result = LegalizeOp(Node->getOperand(0));
1165 case ISD::MEMBARRIER: {
1166 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!");
1167 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) {
1168 default: assert(0 && "This action is not supported yet!");
1169 case TargetLowering::Legal: {
1171 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1172 for (int x = 1; x < 6; ++x) {
1173 Ops[x] = Node->getOperand(x);
1174 if (!isTypeLegal(Ops[x].getValueType()))
1175 Ops[x] = PromoteOp(Ops[x]);
1177 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6);
1180 case TargetLowering::Expand:
1181 //There is no libgcc call for this op
1182 Result = Node->getOperand(0); // Noop
1188 case ISD::ATOMIC_LCS:
1189 case ISD::ATOMIC_LAS:
1190 case ISD::ATOMIC_SWAP: {
1191 assert(((Node->getNumOperands() == 4 && Node->getOpcode() == ISD::ATOMIC_LCS) ||
1192 (Node->getNumOperands() == 3 && Node->getOpcode() == ISD::ATOMIC_LAS) ||
1193 (Node->getNumOperands() == 3 && Node->getOpcode() == ISD::ATOMIC_SWAP)) &&
1194 "Invalid Atomic node!");
1195 int num = Node->getOpcode() == ISD::ATOMIC_LCS ? 4 : 3;
1197 for (int x = 0; x < num; ++x)
1198 Ops[x] = LegalizeOp(Node->getOperand(x));
1199 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num);
1201 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1202 default: assert(0 && "This action is not supported yet!");
1203 case TargetLowering::Custom:
1204 Result = TLI.LowerOperation(Result, DAG);
1206 case TargetLowering::Legal:
1209 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1210 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1211 return Result.getValue(Op.ResNo);
1214 case ISD::Constant: {
1215 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1217 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1219 // We know we don't need to expand constants here, constants only have one
1220 // value and we check that it is fine above.
1222 if (opAction == TargetLowering::Custom) {
1223 Tmp1 = TLI.LowerOperation(Result, DAG);
1229 case ISD::ConstantFP: {
1230 // Spill FP immediates to the constant pool if the target cannot directly
1231 // codegen them. Targets often have some immediate values that can be
1232 // efficiently generated into an FP register without a load. We explicitly
1233 // leave these constants as ConstantFP nodes for the target to deal with.
1234 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1236 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1237 default: assert(0 && "This action is not supported yet!");
1238 case TargetLowering::Legal:
1240 case TargetLowering::Custom:
1241 Tmp3 = TLI.LowerOperation(Result, DAG);
1247 case TargetLowering::Expand: {
1248 // Check to see if this FP immediate is already legal.
1249 bool isLegal = false;
1250 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1251 E = TLI.legal_fpimm_end(); I != E; ++I) {
1252 if (CFP->isExactlyValue(*I)) {
1257 // If this is a legal constant, turn it into a TargetConstantFP node.
1260 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1265 case ISD::TokenFactor:
1266 if (Node->getNumOperands() == 2) {
1267 Tmp1 = LegalizeOp(Node->getOperand(0));
1268 Tmp2 = LegalizeOp(Node->getOperand(1));
1269 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1270 } else if (Node->getNumOperands() == 3) {
1271 Tmp1 = LegalizeOp(Node->getOperand(0));
1272 Tmp2 = LegalizeOp(Node->getOperand(1));
1273 Tmp3 = LegalizeOp(Node->getOperand(2));
1274 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1276 SmallVector<SDOperand, 8> Ops;
1277 // Legalize the operands.
1278 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1279 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1280 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1284 case ISD::FORMAL_ARGUMENTS:
1286 // The only option for this is to custom lower it.
1287 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1288 assert(Tmp3.Val && "Target didn't custom lower this node!");
1289 // A call within a calling sequence must be legalized to something
1290 // other than the normal CALLSEQ_END. Violating this gets Legalize
1291 // into an infinite loop.
1292 assert ((!IsLegalizingCall ||
1293 Node->getOpcode() != ISD::CALL ||
1294 Tmp3.Val->getOpcode() != ISD::CALLSEQ_END) &&
1295 "Nested CALLSEQ_START..CALLSEQ_END not supported.");
1297 // The number of incoming and outgoing values should match; unless the final
1298 // outgoing value is a flag.
1299 assert((Tmp3.Val->getNumValues() == Result.Val->getNumValues() ||
1300 (Tmp3.Val->getNumValues() == Result.Val->getNumValues() + 1 &&
1301 Tmp3.Val->getValueType(Tmp3.Val->getNumValues() - 1) ==
1303 "Lowering call/formal_arguments produced unexpected # results!");
1305 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1306 // remember that we legalized all of them, so it doesn't get relegalized.
1307 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
1308 if (Tmp3.Val->getValueType(i) == MVT::Flag)
1310 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1313 AddLegalizedOperand(SDOperand(Node, i), Tmp1);
1316 case ISD::EXTRACT_SUBREG: {
1317 Tmp1 = LegalizeOp(Node->getOperand(0));
1318 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1319 assert(idx && "Operand must be a constant");
1320 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1321 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1324 case ISD::INSERT_SUBREG: {
1325 Tmp1 = LegalizeOp(Node->getOperand(0));
1326 Tmp2 = LegalizeOp(Node->getOperand(1));
1327 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1328 assert(idx && "Operand must be a constant");
1329 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1330 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1333 case ISD::BUILD_VECTOR:
1334 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1335 default: assert(0 && "This action is not supported yet!");
1336 case TargetLowering::Custom:
1337 Tmp3 = TLI.LowerOperation(Result, DAG);
1343 case TargetLowering::Expand:
1344 Result = ExpandBUILD_VECTOR(Result.Val);
1348 case ISD::INSERT_VECTOR_ELT:
1349 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1350 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1352 // The type of the value to insert may not be legal, even though the vector
1353 // type is legal. Legalize/Promote accordingly. We do not handle Expand
1355 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1356 default: assert(0 && "Cannot expand insert element operand");
1357 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
1358 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
1360 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1362 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1363 Node->getValueType(0))) {
1364 default: assert(0 && "This action is not supported yet!");
1365 case TargetLowering::Legal:
1367 case TargetLowering::Custom:
1368 Tmp4 = TLI.LowerOperation(Result, DAG);
1374 case TargetLowering::Expand: {
1375 // If the insert index is a constant, codegen this as a scalar_to_vector,
1376 // then a shuffle that inserts it into the right position in the vector.
1377 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1378 // SCALAR_TO_VECTOR requires that the type of the value being inserted
1379 // match the element type of the vector being created.
1380 if (Tmp2.getValueType() ==
1381 MVT::getVectorElementType(Op.getValueType())) {
1382 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
1383 Tmp1.getValueType(), Tmp2);
1385 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
1386 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
1387 MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT);
1389 // We generate a shuffle of InVec and ScVec, so the shuffle mask
1390 // should be 0,1,2,3,4,5... with the appropriate element replaced with
1391 // elt 0 of the RHS.
1392 SmallVector<SDOperand, 8> ShufOps;
1393 for (unsigned i = 0; i != NumElts; ++i) {
1394 if (i != InsertPos->getValue())
1395 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1397 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1399 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1400 &ShufOps[0], ShufOps.size());
1402 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1403 Tmp1, ScVec, ShufMask);
1404 Result = LegalizeOp(Result);
1409 // If the target doesn't support this, we have to spill the input vector
1410 // to a temporary stack slot, update the element, then reload it. This is
1411 // badness. We could also load the value into a vector register (either
1412 // with a "move to register" or "extload into register" instruction, then
1413 // permute it into place, if the idx is a constant and if the idx is
1414 // supported by the target.
1415 MVT::ValueType VT = Tmp1.getValueType();
1416 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
1417 MVT::ValueType IdxVT = Tmp3.getValueType();
1418 MVT::ValueType PtrVT = TLI.getPointerTy();
1419 SDOperand StackPtr = DAG.CreateStackTemporary(VT);
1421 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr.Val);
1422 int SPFI = StackPtrFI->getIndex();
1424 // Store the vector.
1425 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr,
1426 PseudoSourceValue::getFixedStack(),
1429 // Truncate or zero extend offset to target pointer type.
1430 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
1431 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
1432 // Add the offset to the index.
1433 unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
1434 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
1435 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
1436 // Store the scalar value.
1437 Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2,
1438 PseudoSourceValue::getFixedStack(), SPFI, EltVT);
1439 // Load the updated vector.
1440 Result = DAG.getLoad(VT, Ch, StackPtr,
1441 PseudoSourceValue::getFixedStack(), SPFI);
1446 case ISD::SCALAR_TO_VECTOR:
1447 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1448 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1452 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1453 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1454 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1455 Node->getValueType(0))) {
1456 default: assert(0 && "This action is not supported yet!");
1457 case TargetLowering::Legal:
1459 case TargetLowering::Custom:
1460 Tmp3 = TLI.LowerOperation(Result, DAG);
1466 case TargetLowering::Expand:
1467 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1471 case ISD::VECTOR_SHUFFLE:
1472 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1473 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1474 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1476 // Allow targets to custom lower the SHUFFLEs they support.
1477 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1478 default: assert(0 && "Unknown operation action!");
1479 case TargetLowering::Legal:
1480 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1481 "vector shuffle should not be created if not legal!");
1483 case TargetLowering::Custom:
1484 Tmp3 = TLI.LowerOperation(Result, DAG);
1490 case TargetLowering::Expand: {
1491 MVT::ValueType VT = Node->getValueType(0);
1492 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
1493 MVT::ValueType PtrVT = TLI.getPointerTy();
1494 SDOperand Mask = Node->getOperand(2);
1495 unsigned NumElems = Mask.getNumOperands();
1496 SmallVector<SDOperand,8> Ops;
1497 for (unsigned i = 0; i != NumElems; ++i) {
1498 SDOperand Arg = Mask.getOperand(i);
1499 if (Arg.getOpcode() == ISD::UNDEF) {
1500 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1502 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1503 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
1505 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1506 DAG.getConstant(Idx, PtrVT)));
1508 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1509 DAG.getConstant(Idx - NumElems, PtrVT)));
1512 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1515 case TargetLowering::Promote: {
1516 // Change base type to a different vector type.
1517 MVT::ValueType OVT = Node->getValueType(0);
1518 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1520 // Cast the two input vectors.
1521 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1522 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1524 // Convert the shuffle mask to the right # elements.
1525 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1526 assert(Tmp3.Val && "Shuffle not legal?");
1527 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1528 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1534 case ISD::EXTRACT_VECTOR_ELT:
1535 Tmp1 = Node->getOperand(0);
1536 Tmp2 = LegalizeOp(Node->getOperand(1));
1537 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1538 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1541 case ISD::EXTRACT_SUBVECTOR:
1542 Tmp1 = Node->getOperand(0);
1543 Tmp2 = LegalizeOp(Node->getOperand(1));
1544 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1545 Result = ExpandEXTRACT_SUBVECTOR(Result);
1548 case ISD::CALLSEQ_START: {
1549 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1551 // Recursively Legalize all of the inputs of the call end that do not lead
1552 // to this call start. This ensures that any libcalls that need be inserted
1553 // are inserted *before* the CALLSEQ_START.
1554 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1555 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1556 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
1560 // Now that we legalized all of the inputs (which may have inserted
1561 // libcalls) create the new CALLSEQ_START node.
1562 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1564 // Merge in the last call, to ensure that this call start after the last
1566 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1567 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1568 Tmp1 = LegalizeOp(Tmp1);
1571 // Do not try to legalize the target-specific arguments (#1+).
1572 if (Tmp1 != Node->getOperand(0)) {
1573 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1575 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1578 // Remember that the CALLSEQ_START is legalized.
1579 AddLegalizedOperand(Op.getValue(0), Result);
1580 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1581 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1583 // Now that the callseq_start and all of the non-call nodes above this call
1584 // sequence have been legalized, legalize the call itself. During this
1585 // process, no libcalls can/will be inserted, guaranteeing that no calls
1587 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1588 SDOperand InCallSEQ = LastCALLSEQ_END;
1589 // Note that we are selecting this call!
1590 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1591 IsLegalizingCall = true;
1593 // Legalize the call, starting from the CALLSEQ_END.
1594 LegalizeOp(LastCALLSEQ_END);
1595 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1598 case ISD::CALLSEQ_END:
1599 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1600 // will cause this node to be legalized as well as handling libcalls right.
1601 if (LastCALLSEQ_END.Val != Node) {
1602 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1603 DenseMap<SDOperandImpl, SDOperand>::iterator I = LegalizedNodes.find(Op);
1604 assert(I != LegalizedNodes.end() &&
1605 "Legalizing the call start should have legalized this node!");
1609 // Otherwise, the call start has been legalized and everything is going
1610 // according to plan. Just legalize ourselves normally here.
1611 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1612 // Do not try to legalize the target-specific arguments (#1+), except for
1613 // an optional flag input.
1614 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1615 if (Tmp1 != Node->getOperand(0)) {
1616 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1618 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1621 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1622 if (Tmp1 != Node->getOperand(0) ||
1623 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1624 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1627 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1630 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1631 // This finishes up call legalization.
1632 IsLegalizingCall = false;
1634 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1635 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1636 if (Node->getNumValues() == 2)
1637 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1638 return Result.getValue(Op.ResNo);
1639 case ISD::DYNAMIC_STACKALLOC: {
1640 MVT::ValueType VT = Node->getValueType(0);
1641 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1642 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1643 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1644 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1646 Tmp1 = Result.getValue(0);
1647 Tmp2 = Result.getValue(1);
1648 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1649 default: assert(0 && "This action is not supported yet!");
1650 case TargetLowering::Expand: {
1651 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1652 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1653 " not tell us which reg is the stack pointer!");
1654 SDOperand Chain = Tmp1.getOperand(0);
1656 // Chain the dynamic stack allocation so that it doesn't modify the stack
1657 // pointer when other instructions are using the stack.
1658 Chain = DAG.getCALLSEQ_START(Chain,
1659 DAG.getConstant(0, TLI.getPointerTy()));
1661 SDOperand Size = Tmp2.getOperand(1);
1662 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT);
1663 Chain = SP.getValue(1);
1664 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue();
1665 unsigned StackAlign =
1666 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1667 if (Align > StackAlign)
1668 SP = DAG.getNode(ISD::AND, VT, SP,
1669 DAG.getConstant(-(uint64_t)Align, VT));
1670 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value
1671 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
1674 DAG.getCALLSEQ_END(Chain,
1675 DAG.getConstant(0, TLI.getPointerTy()),
1676 DAG.getConstant(0, TLI.getPointerTy()),
1679 Tmp1 = LegalizeOp(Tmp1);
1680 Tmp2 = LegalizeOp(Tmp2);
1683 case TargetLowering::Custom:
1684 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1686 Tmp1 = LegalizeOp(Tmp3);
1687 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1690 case TargetLowering::Legal:
1693 // Since this op produce two values, make sure to remember that we
1694 // legalized both of them.
1695 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1696 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1697 return Op.ResNo ? Tmp2 : Tmp1;
1699 case ISD::INLINEASM: {
1700 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1701 bool Changed = false;
1702 // Legalize all of the operands of the inline asm, in case they are nodes
1703 // that need to be expanded or something. Note we skip the asm string and
1704 // all of the TargetConstant flags.
1705 SDOperand Op = LegalizeOp(Ops[0]);
1706 Changed = Op != Ops[0];
1709 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1710 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1711 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1712 for (++i; NumVals; ++i, --NumVals) {
1713 SDOperand Op = LegalizeOp(Ops[i]);
1722 Op = LegalizeOp(Ops.back());
1723 Changed |= Op != Ops.back();
1728 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1730 // INLINE asm returns a chain and flag, make sure to add both to the map.
1731 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1732 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1733 return Result.getValue(Op.ResNo);
1736 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1737 // Ensure that libcalls are emitted before a branch.
1738 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1739 Tmp1 = LegalizeOp(Tmp1);
1740 LastCALLSEQ_END = DAG.getEntryNode();
1742 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1745 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1746 // Ensure that libcalls are emitted before a branch.
1747 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1748 Tmp1 = LegalizeOp(Tmp1);
1749 LastCALLSEQ_END = DAG.getEntryNode();
1751 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1752 default: assert(0 && "Indirect target must be legal type (pointer)!");
1754 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1757 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1760 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1761 // Ensure that libcalls are emitted before a branch.
1762 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1763 Tmp1 = LegalizeOp(Tmp1);
1764 LastCALLSEQ_END = DAG.getEntryNode();
1766 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1767 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1769 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1770 default: assert(0 && "This action is not supported yet!");
1771 case TargetLowering::Legal: break;
1772 case TargetLowering::Custom:
1773 Tmp1 = TLI.LowerOperation(Result, DAG);
1774 if (Tmp1.Val) Result = Tmp1;
1776 case TargetLowering::Expand: {
1777 SDOperand Chain = Result.getOperand(0);
1778 SDOperand Table = Result.getOperand(1);
1779 SDOperand Index = Result.getOperand(2);
1781 MVT::ValueType PTy = TLI.getPointerTy();
1782 MachineFunction &MF = DAG.getMachineFunction();
1783 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
1784 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1785 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1788 switch (EntrySize) {
1789 default: assert(0 && "Size of jump table not supported yet."); break;
1790 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr,
1791 PseudoSourceValue::getJumpTable(), 0); break;
1792 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr,
1793 PseudoSourceValue::getJumpTable(), 0); break;
1797 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1798 // For PIC, the sequence is:
1799 // BRIND(load(Jumptable + index) + RelocBase)
1800 // RelocBase can be JumpTable, GOT or some sort of global base.
1801 if (PTy != MVT::i32)
1802 Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr);
1803 Addr = DAG.getNode(ISD::ADD, PTy, Addr,
1804 TLI.getPICJumpTableRelocBase(Table, DAG));
1806 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1811 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1812 // Ensure that libcalls are emitted before a return.
1813 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1814 Tmp1 = LegalizeOp(Tmp1);
1815 LastCALLSEQ_END = DAG.getEntryNode();
1817 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1818 case Expand: assert(0 && "It's impossible to expand bools");
1820 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1823 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1825 // The top bits of the promoted condition are not necessarily zero, ensure
1826 // that the value is properly zero extended.
1827 unsigned BitWidth = Tmp2.getValueSizeInBits();
1828 if (!DAG.MaskedValueIsZero(Tmp2,
1829 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
1830 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1835 // Basic block destination (Op#2) is always legal.
1836 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1838 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1839 default: assert(0 && "This action is not supported yet!");
1840 case TargetLowering::Legal: break;
1841 case TargetLowering::Custom:
1842 Tmp1 = TLI.LowerOperation(Result, DAG);
1843 if (Tmp1.Val) Result = Tmp1;
1845 case TargetLowering::Expand:
1846 // Expand brcond's setcc into its constituent parts and create a BR_CC
1848 if (Tmp2.getOpcode() == ISD::SETCC) {
1849 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1850 Tmp2.getOperand(0), Tmp2.getOperand(1),
1851 Node->getOperand(2));
1853 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1854 DAG.getCondCode(ISD::SETNE), Tmp2,
1855 DAG.getConstant(0, Tmp2.getValueType()),
1856 Node->getOperand(2));
1862 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1863 // Ensure that libcalls are emitted before a branch.
1864 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1865 Tmp1 = LegalizeOp(Tmp1);
1866 Tmp2 = Node->getOperand(2); // LHS
1867 Tmp3 = Node->getOperand(3); // RHS
1868 Tmp4 = Node->getOperand(1); // CC
1870 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1871 LastCALLSEQ_END = DAG.getEntryNode();
1873 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1874 // the LHS is a legal SETCC itself. In this case, we need to compare
1875 // the result against zero to select between true and false values.
1876 if (Tmp3.Val == 0) {
1877 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1878 Tmp4 = DAG.getCondCode(ISD::SETNE);
1881 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1882 Node->getOperand(4));
1884 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1885 default: assert(0 && "Unexpected action for BR_CC!");
1886 case TargetLowering::Legal: break;
1887 case TargetLowering::Custom:
1888 Tmp4 = TLI.LowerOperation(Result, DAG);
1889 if (Tmp4.Val) Result = Tmp4;
1894 LoadSDNode *LD = cast<LoadSDNode>(Node);
1895 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1896 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1898 ISD::LoadExtType ExtType = LD->getExtensionType();
1899 if (ExtType == ISD::NON_EXTLOAD) {
1900 MVT::ValueType VT = Node->getValueType(0);
1901 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1902 Tmp3 = Result.getValue(0);
1903 Tmp4 = Result.getValue(1);
1905 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1906 default: assert(0 && "This action is not supported yet!");
1907 case TargetLowering::Legal:
1908 // If this is an unaligned load and the target doesn't support it,
1910 if (!TLI.allowsUnalignedMemoryAccesses()) {
1911 unsigned ABIAlignment = TLI.getTargetData()->
1912 getABITypeAlignment(MVT::getTypeForValueType(LD->getMemoryVT()));
1913 if (LD->getAlignment() < ABIAlignment){
1914 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
1916 Tmp3 = Result.getOperand(0);
1917 Tmp4 = Result.getOperand(1);
1918 Tmp3 = LegalizeOp(Tmp3);
1919 Tmp4 = LegalizeOp(Tmp4);
1923 case TargetLowering::Custom:
1924 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1926 Tmp3 = LegalizeOp(Tmp1);
1927 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1930 case TargetLowering::Promote: {
1931 // Only promote a load of vector type to another.
1932 assert(MVT::isVector(VT) && "Cannot promote this load!");
1933 // Change base type to a different vector type.
1934 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1936 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1937 LD->getSrcValueOffset(),
1938 LD->isVolatile(), LD->getAlignment());
1939 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1940 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1944 // Since loads produce two values, make sure to remember that we
1945 // legalized both of them.
1946 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1947 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1948 return Op.ResNo ? Tmp4 : Tmp3;
1950 MVT::ValueType SrcVT = LD->getMemoryVT();
1951 unsigned SrcWidth = MVT::getSizeInBits(SrcVT);
1952 int SVOffset = LD->getSrcValueOffset();
1953 unsigned Alignment = LD->getAlignment();
1954 bool isVolatile = LD->isVolatile();
1956 if (SrcWidth != MVT::getStoreSizeInBits(SrcVT) &&
1957 // Some targets pretend to have an i1 loading operation, and actually
1958 // load an i8. This trick is correct for ZEXTLOAD because the top 7
1959 // bits are guaranteed to be zero; it helps the optimizers understand
1960 // that these bits are zero. It is also useful for EXTLOAD, since it
1961 // tells the optimizers that those bits are undefined. It would be
1962 // nice to have an effective generic way of getting these benefits...
1963 // Until such a way is found, don't insist on promoting i1 here.
1964 (SrcVT != MVT::i1 ||
1965 TLI.getLoadXAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
1966 // Promote to a byte-sized load if not loading an integral number of
1967 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
1968 unsigned NewWidth = MVT::getStoreSizeInBits(SrcVT);
1969 MVT::ValueType NVT = MVT::getIntegerType(NewWidth);
1972 // The extra bits are guaranteed to be zero, since we stored them that
1973 // way. A zext load from NVT thus automatically gives zext from SrcVT.
1975 ISD::LoadExtType NewExtType =
1976 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
1978 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0),
1979 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
1980 NVT, isVolatile, Alignment);
1982 Ch = Result.getValue(1); // The chain.
1984 if (ExtType == ISD::SEXTLOAD)
1985 // Having the top bits zero doesn't help when sign extending.
1986 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1987 Result, DAG.getValueType(SrcVT));
1988 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
1989 // All the top bits are guaranteed to be zero - inform the optimizers.
1990 Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result,
1991 DAG.getValueType(SrcVT));
1993 Tmp1 = LegalizeOp(Result);
1994 Tmp2 = LegalizeOp(Ch);
1995 } else if (SrcWidth & (SrcWidth - 1)) {
1996 // If not loading a power-of-2 number of bits, expand as two loads.
1997 assert(MVT::isExtendedVT(SrcVT) && !MVT::isVector(SrcVT) &&
1998 "Unsupported extload!");
1999 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
2000 assert(RoundWidth < SrcWidth);
2001 unsigned ExtraWidth = SrcWidth - RoundWidth;
2002 assert(ExtraWidth < RoundWidth);
2003 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2004 "Load size not an integral number of bytes!");
2005 MVT::ValueType RoundVT = MVT::getIntegerType(RoundWidth);
2006 MVT::ValueType ExtraVT = MVT::getIntegerType(ExtraWidth);
2007 SDOperand Lo, Hi, Ch;
2008 unsigned IncrementSize;
2010 if (TLI.isLittleEndian()) {
2011 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
2012 // Load the bottom RoundWidth bits.
2013 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2014 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2017 // Load the remaining ExtraWidth bits.
2018 IncrementSize = RoundWidth / 8;
2019 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2020 DAG.getIntPtrConstant(IncrementSize));
2021 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2022 LD->getSrcValue(), SVOffset + IncrementSize,
2023 ExtraVT, isVolatile,
2024 MinAlign(Alignment, IncrementSize));
2026 // Build a factor node to remember that this load is independent of the
2028 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2031 // Move the top bits to the right place.
2032 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2033 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2035 // Join the hi and lo parts.
2036 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2038 // Big endian - avoid unaligned loads.
2039 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
2040 // Load the top RoundWidth bits.
2041 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2042 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2045 // Load the remaining ExtraWidth bits.
2046 IncrementSize = RoundWidth / 8;
2047 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2048 DAG.getIntPtrConstant(IncrementSize));
2049 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2050 LD->getSrcValue(), SVOffset + IncrementSize,
2051 ExtraVT, isVolatile,
2052 MinAlign(Alignment, IncrementSize));
2054 // Build a factor node to remember that this load is independent of the
2056 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2059 // Move the top bits to the right place.
2060 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2061 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2063 // Join the hi and lo parts.
2064 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2067 Tmp1 = LegalizeOp(Result);
2068 Tmp2 = LegalizeOp(Ch);
2070 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
2071 default: assert(0 && "This action is not supported yet!");
2072 case TargetLowering::Custom:
2075 case TargetLowering::Legal:
2076 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2077 Tmp1 = Result.getValue(0);
2078 Tmp2 = Result.getValue(1);
2081 Tmp3 = TLI.LowerOperation(Result, DAG);
2083 Tmp1 = LegalizeOp(Tmp3);
2084 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2087 // If this is an unaligned load and the target doesn't support it,
2089 if (!TLI.allowsUnalignedMemoryAccesses()) {
2090 unsigned ABIAlignment = TLI.getTargetData()->
2091 getABITypeAlignment(MVT::getTypeForValueType(LD->getMemoryVT()));
2092 if (LD->getAlignment() < ABIAlignment){
2093 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
2095 Tmp1 = Result.getOperand(0);
2096 Tmp2 = Result.getOperand(1);
2097 Tmp1 = LegalizeOp(Tmp1);
2098 Tmp2 = LegalizeOp(Tmp2);
2103 case TargetLowering::Expand:
2104 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
2105 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
2106 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
2107 LD->getSrcValueOffset(),
2108 LD->isVolatile(), LD->getAlignment());
2109 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
2110 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
2111 Tmp2 = LegalizeOp(Load.getValue(1));
2114 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
2115 // Turn the unsupported load into an EXTLOAD followed by an explicit
2116 // zero/sign extend inreg.
2117 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2118 Tmp1, Tmp2, LD->getSrcValue(),
2119 LD->getSrcValueOffset(), SrcVT,
2120 LD->isVolatile(), LD->getAlignment());
2122 if (ExtType == ISD::SEXTLOAD)
2123 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2124 Result, DAG.getValueType(SrcVT));
2126 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
2127 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
2128 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
2133 // Since loads produce two values, make sure to remember that we legalized
2135 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2136 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2137 return Op.ResNo ? Tmp2 : Tmp1;
2140 case ISD::EXTRACT_ELEMENT: {
2141 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
2142 switch (getTypeAction(OpTy)) {
2143 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
2145 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
2147 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
2148 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
2149 TLI.getShiftAmountTy()));
2150 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
2153 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
2154 Node->getOperand(0));
2158 // Get both the low and high parts.
2159 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2160 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
2161 Result = Tmp2; // 1 -> Hi
2163 Result = Tmp1; // 0 -> Lo
2169 case ISD::CopyToReg:
2170 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2172 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
2173 "Register type must be legal!");
2174 // Legalize the incoming value (must be a legal type).
2175 Tmp2 = LegalizeOp(Node->getOperand(2));
2176 if (Node->getNumValues() == 1) {
2177 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
2179 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
2180 if (Node->getNumOperands() == 4) {
2181 Tmp3 = LegalizeOp(Node->getOperand(3));
2182 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
2185 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
2188 // Since this produces two values, make sure to remember that we legalized
2190 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2191 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2197 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2199 // Ensure that libcalls are emitted before a return.
2200 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2201 Tmp1 = LegalizeOp(Tmp1);
2202 LastCALLSEQ_END = DAG.getEntryNode();
2204 switch (Node->getNumOperands()) {
2206 Tmp2 = Node->getOperand(1);
2207 Tmp3 = Node->getOperand(2); // Signness
2208 switch (getTypeAction(Tmp2.getValueType())) {
2210 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
2213 if (!MVT::isVector(Tmp2.getValueType())) {
2215 ExpandOp(Tmp2, Lo, Hi);
2217 // Big endian systems want the hi reg first.
2218 if (TLI.isBigEndian())
2222 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2224 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
2225 Result = LegalizeOp(Result);
2227 SDNode *InVal = Tmp2.Val;
2228 int InIx = Tmp2.ResNo;
2229 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx));
2230 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx));
2232 // Figure out if there is a simple type corresponding to this Vector
2233 // type. If so, convert to the vector type.
2234 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2235 if (TLI.isTypeLegal(TVT)) {
2236 // Turn this into a return of the vector type.
2237 Tmp2 = LegalizeOp(Tmp2);
2238 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2239 } else if (NumElems == 1) {
2240 // Turn this into a return of the scalar type.
2241 Tmp2 = ScalarizeVectorOp(Tmp2);
2242 Tmp2 = LegalizeOp(Tmp2);
2243 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2245 // FIXME: Returns of gcc generic vectors smaller than a legal type
2246 // should be returned in integer registers!
2248 // The scalarized value type may not be legal, e.g. it might require
2249 // promotion or expansion. Relegalize the return.
2250 Result = LegalizeOp(Result);
2252 // FIXME: Returns of gcc generic vectors larger than a legal vector
2253 // type should be returned by reference!
2255 SplitVectorOp(Tmp2, Lo, Hi);
2256 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2257 Result = LegalizeOp(Result);
2262 Tmp2 = PromoteOp(Node->getOperand(1));
2263 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2264 Result = LegalizeOp(Result);
2269 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2271 default: { // ret <values>
2272 SmallVector<SDOperand, 8> NewValues;
2273 NewValues.push_back(Tmp1);
2274 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
2275 switch (getTypeAction(Node->getOperand(i).getValueType())) {
2277 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
2278 NewValues.push_back(Node->getOperand(i+1));
2282 assert(!MVT::isExtendedVT(Node->getOperand(i).getValueType()) &&
2283 "FIXME: TODO: implement returning non-legal vector types!");
2284 ExpandOp(Node->getOperand(i), Lo, Hi);
2285 NewValues.push_back(Lo);
2286 NewValues.push_back(Node->getOperand(i+1));
2288 NewValues.push_back(Hi);
2289 NewValues.push_back(Node->getOperand(i+1));
2294 assert(0 && "Can't promote multiple return value yet!");
2297 if (NewValues.size() == Node->getNumOperands())
2298 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
2300 Result = DAG.getNode(ISD::RET, MVT::Other,
2301 &NewValues[0], NewValues.size());
2306 if (Result.getOpcode() == ISD::RET) {
2307 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
2308 default: assert(0 && "This action is not supported yet!");
2309 case TargetLowering::Legal: break;
2310 case TargetLowering::Custom:
2311 Tmp1 = TLI.LowerOperation(Result, DAG);
2312 if (Tmp1.Val) Result = Tmp1;
2318 StoreSDNode *ST = cast<StoreSDNode>(Node);
2319 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
2320 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
2321 int SVOffset = ST->getSrcValueOffset();
2322 unsigned Alignment = ST->getAlignment();
2323 bool isVolatile = ST->isVolatile();
2325 if (!ST->isTruncatingStore()) {
2326 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
2327 // FIXME: We shouldn't do this for TargetConstantFP's.
2328 // FIXME: move this to the DAG Combiner! Note that we can't regress due
2329 // to phase ordering between legalized code and the dag combiner. This
2330 // probably means that we need to integrate dag combiner and legalizer
2332 // We generally can't do this one for long doubles.
2333 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
2334 if (CFP->getValueType(0) == MVT::f32 &&
2335 getTypeAction(MVT::i32) == Legal) {
2336 Tmp3 = DAG.getConstant(CFP->getValueAPF().
2337 convertToAPInt().zextOrTrunc(32),
2339 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2340 SVOffset, isVolatile, Alignment);
2342 } else if (CFP->getValueType(0) == MVT::f64) {
2343 // If this target supports 64-bit registers, do a single 64-bit store.
2344 if (getTypeAction(MVT::i64) == Legal) {
2345 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt().
2346 zextOrTrunc(64), MVT::i64);
2347 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2348 SVOffset, isVolatile, Alignment);
2350 } else if (getTypeAction(MVT::i32) == Legal) {
2351 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
2352 // stores. If the target supports neither 32- nor 64-bits, this
2353 // xform is certainly not worth it.
2354 const APInt &IntVal =CFP->getValueAPF().convertToAPInt();
2355 SDOperand Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
2356 SDOperand Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
2357 if (TLI.isBigEndian()) std::swap(Lo, Hi);
2359 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2360 SVOffset, isVolatile, Alignment);
2361 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2362 DAG.getIntPtrConstant(4));
2363 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
2364 isVolatile, MinAlign(Alignment, 4U));
2366 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2372 switch (getTypeAction(ST->getMemoryVT())) {
2374 Tmp3 = LegalizeOp(ST->getValue());
2375 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2378 MVT::ValueType VT = Tmp3.getValueType();
2379 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2380 default: assert(0 && "This action is not supported yet!");
2381 case TargetLowering::Legal:
2382 // If this is an unaligned store and the target doesn't support it,
2384 if (!TLI.allowsUnalignedMemoryAccesses()) {
2385 unsigned ABIAlignment = TLI.getTargetData()->
2386 getABITypeAlignment(MVT::getTypeForValueType(ST->getMemoryVT()));
2387 if (ST->getAlignment() < ABIAlignment)
2388 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2392 case TargetLowering::Custom:
2393 Tmp1 = TLI.LowerOperation(Result, DAG);
2394 if (Tmp1.Val) Result = Tmp1;
2396 case TargetLowering::Promote:
2397 assert(MVT::isVector(VT) && "Unknown legal promote case!");
2398 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
2399 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2400 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
2401 ST->getSrcValue(), SVOffset, isVolatile,
2408 // Truncate the value and store the result.
2409 Tmp3 = PromoteOp(ST->getValue());
2410 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2411 SVOffset, ST->getMemoryVT(),
2412 isVolatile, Alignment);
2416 unsigned IncrementSize = 0;
2419 // If this is a vector type, then we have to calculate the increment as
2420 // the product of the element size in bytes, and the number of elements
2421 // in the high half of the vector.
2422 if (MVT::isVector(ST->getValue().getValueType())) {
2423 SDNode *InVal = ST->getValue().Val;
2424 int InIx = ST->getValue().ResNo;
2425 MVT::ValueType InVT = InVal->getValueType(InIx);
2426 unsigned NumElems = MVT::getVectorNumElements(InVT);
2427 MVT::ValueType EVT = MVT::getVectorElementType(InVT);
2429 // Figure out if there is a simple type corresponding to this Vector
2430 // type. If so, convert to the vector type.
2431 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2432 if (TLI.isTypeLegal(TVT)) {
2433 // Turn this into a normal store of the vector type.
2434 Tmp3 = LegalizeOp(ST->getValue());
2435 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2436 SVOffset, isVolatile, Alignment);
2437 Result = LegalizeOp(Result);
2439 } else if (NumElems == 1) {
2440 // Turn this into a normal store of the scalar type.
2441 Tmp3 = ScalarizeVectorOp(ST->getValue());
2442 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2443 SVOffset, isVolatile, Alignment);
2444 // The scalarized value type may not be legal, e.g. it might require
2445 // promotion or expansion. Relegalize the scalar store.
2446 Result = LegalizeOp(Result);
2449 SplitVectorOp(ST->getValue(), Lo, Hi);
2450 IncrementSize = MVT::getVectorNumElements(Lo.Val->getValueType(0)) *
2451 MVT::getSizeInBits(EVT)/8;
2454 ExpandOp(ST->getValue(), Lo, Hi);
2455 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0;
2457 if (TLI.isBigEndian())
2461 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2462 SVOffset, isVolatile, Alignment);
2464 if (Hi.Val == NULL) {
2465 // Must be int <-> float one-to-one expansion.
2470 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2471 DAG.getIntPtrConstant(IncrementSize));
2472 assert(isTypeLegal(Tmp2.getValueType()) &&
2473 "Pointers must be legal!");
2474 SVOffset += IncrementSize;
2475 Alignment = MinAlign(Alignment, IncrementSize);
2476 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2477 SVOffset, isVolatile, Alignment);
2478 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2482 switch (getTypeAction(ST->getValue().getValueType())) {
2484 Tmp3 = LegalizeOp(ST->getValue());
2487 // We can promote the value, the truncstore will still take care of it.
2488 Tmp3 = PromoteOp(ST->getValue());
2491 // Just store the low part. This may become a non-trunc store, so make
2492 // sure to use getTruncStore, not UpdateNodeOperands below.
2493 ExpandOp(ST->getValue(), Tmp3, Tmp4);
2494 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2495 SVOffset, MVT::i8, isVolatile, Alignment);
2498 MVT::ValueType StVT = ST->getMemoryVT();
2499 unsigned StWidth = MVT::getSizeInBits(StVT);
2501 if (StWidth != MVT::getStoreSizeInBits(StVT)) {
2502 // Promote to a byte-sized store with upper bits zero if not
2503 // storing an integral number of bytes. For example, promote
2504 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
2505 MVT::ValueType NVT = MVT::getIntegerType(MVT::getStoreSizeInBits(StVT));
2506 Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT);
2507 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2508 SVOffset, NVT, isVolatile, Alignment);
2509 } else if (StWidth & (StWidth - 1)) {
2510 // If not storing a power-of-2 number of bits, expand as two stores.
2511 assert(MVT::isExtendedVT(StVT) && !MVT::isVector(StVT) &&
2512 "Unsupported truncstore!");
2513 unsigned RoundWidth = 1 << Log2_32(StWidth);
2514 assert(RoundWidth < StWidth);
2515 unsigned ExtraWidth = StWidth - RoundWidth;
2516 assert(ExtraWidth < RoundWidth);
2517 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2518 "Store size not an integral number of bytes!");
2519 MVT::ValueType RoundVT = MVT::getIntegerType(RoundWidth);
2520 MVT::ValueType ExtraVT = MVT::getIntegerType(ExtraWidth);
2522 unsigned IncrementSize;
2524 if (TLI.isLittleEndian()) {
2525 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
2526 // Store the bottom RoundWidth bits.
2527 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2529 isVolatile, Alignment);
2531 // Store the remaining ExtraWidth bits.
2532 IncrementSize = RoundWidth / 8;
2533 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2534 DAG.getIntPtrConstant(IncrementSize));
2535 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2536 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2537 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2538 SVOffset + IncrementSize, ExtraVT, isVolatile,
2539 MinAlign(Alignment, IncrementSize));
2541 // Big endian - avoid unaligned stores.
2542 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
2543 // Store the top RoundWidth bits.
2544 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2545 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2546 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset,
2547 RoundVT, isVolatile, Alignment);
2549 // Store the remaining ExtraWidth bits.
2550 IncrementSize = RoundWidth / 8;
2551 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2552 DAG.getIntPtrConstant(IncrementSize));
2553 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2554 SVOffset + IncrementSize, ExtraVT, isVolatile,
2555 MinAlign(Alignment, IncrementSize));
2558 // The order of the stores doesn't matter.
2559 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2561 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2562 Tmp2 != ST->getBasePtr())
2563 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2566 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
2567 default: assert(0 && "This action is not supported yet!");
2568 case TargetLowering::Legal:
2569 // If this is an unaligned store and the target doesn't support it,
2571 if (!TLI.allowsUnalignedMemoryAccesses()) {
2572 unsigned ABIAlignment = TLI.getTargetData()->
2573 getABITypeAlignment(MVT::getTypeForValueType(ST->getMemoryVT()));
2574 if (ST->getAlignment() < ABIAlignment)
2575 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2579 case TargetLowering::Custom:
2580 Result = TLI.LowerOperation(Result, DAG);
2583 // TRUNCSTORE:i16 i32 -> STORE i16
2584 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
2585 Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3);
2586 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset,
2587 isVolatile, Alignment);
2595 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2596 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2598 case ISD::STACKSAVE:
2599 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2600 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2601 Tmp1 = Result.getValue(0);
2602 Tmp2 = Result.getValue(1);
2604 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2605 default: assert(0 && "This action is not supported yet!");
2606 case TargetLowering::Legal: break;
2607 case TargetLowering::Custom:
2608 Tmp3 = TLI.LowerOperation(Result, DAG);
2610 Tmp1 = LegalizeOp(Tmp3);
2611 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2614 case TargetLowering::Expand:
2615 // Expand to CopyFromReg if the target set
2616 // StackPointerRegisterToSaveRestore.
2617 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2618 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
2619 Node->getValueType(0));
2620 Tmp2 = Tmp1.getValue(1);
2622 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
2623 Tmp2 = Node->getOperand(0);
2628 // Since stacksave produce two values, make sure to remember that we
2629 // legalized both of them.
2630 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2631 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2632 return Op.ResNo ? Tmp2 : Tmp1;
2634 case ISD::STACKRESTORE:
2635 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2636 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2637 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2639 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2640 default: assert(0 && "This action is not supported yet!");
2641 case TargetLowering::Legal: break;
2642 case TargetLowering::Custom:
2643 Tmp1 = TLI.LowerOperation(Result, DAG);
2644 if (Tmp1.Val) Result = Tmp1;
2646 case TargetLowering::Expand:
2647 // Expand to CopyToReg if the target set
2648 // StackPointerRegisterToSaveRestore.
2649 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2650 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
2658 case ISD::READCYCLECOUNTER:
2659 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2660 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2661 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2662 Node->getValueType(0))) {
2663 default: assert(0 && "This action is not supported yet!");
2664 case TargetLowering::Legal:
2665 Tmp1 = Result.getValue(0);
2666 Tmp2 = Result.getValue(1);
2668 case TargetLowering::Custom:
2669 Result = TLI.LowerOperation(Result, DAG);
2670 Tmp1 = LegalizeOp(Result.getValue(0));
2671 Tmp2 = LegalizeOp(Result.getValue(1));
2675 // Since rdcc produce two values, make sure to remember that we legalized
2677 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2678 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2682 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2683 case Expand: assert(0 && "It's impossible to expand bools");
2685 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2688 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2689 // Make sure the condition is either zero or one.
2690 unsigned BitWidth = Tmp1.getValueSizeInBits();
2691 if (!DAG.MaskedValueIsZero(Tmp1,
2692 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2693 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2697 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2698 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2700 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2702 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2703 default: assert(0 && "This action is not supported yet!");
2704 case TargetLowering::Legal: break;
2705 case TargetLowering::Custom: {
2706 Tmp1 = TLI.LowerOperation(Result, DAG);
2707 if (Tmp1.Val) Result = Tmp1;
2710 case TargetLowering::Expand:
2711 if (Tmp1.getOpcode() == ISD::SETCC) {
2712 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2714 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2716 Result = DAG.getSelectCC(Tmp1,
2717 DAG.getConstant(0, Tmp1.getValueType()),
2718 Tmp2, Tmp3, ISD::SETNE);
2721 case TargetLowering::Promote: {
2722 MVT::ValueType NVT =
2723 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2724 unsigned ExtOp, TruncOp;
2725 if (MVT::isVector(Tmp2.getValueType())) {
2726 ExtOp = ISD::BIT_CONVERT;
2727 TruncOp = ISD::BIT_CONVERT;
2728 } else if (MVT::isInteger(Tmp2.getValueType())) {
2729 ExtOp = ISD::ANY_EXTEND;
2730 TruncOp = ISD::TRUNCATE;
2732 ExtOp = ISD::FP_EXTEND;
2733 TruncOp = ISD::FP_ROUND;
2735 // Promote each of the values to the new type.
2736 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2737 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2738 // Perform the larger operation, then round down.
2739 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2740 if (TruncOp != ISD::FP_ROUND)
2741 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2743 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result,
2744 DAG.getIntPtrConstant(0));
2749 case ISD::SELECT_CC: {
2750 Tmp1 = Node->getOperand(0); // LHS
2751 Tmp2 = Node->getOperand(1); // RHS
2752 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2753 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2754 SDOperand CC = Node->getOperand(4);
2756 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
2758 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
2759 // the LHS is a legal SETCC itself. In this case, we need to compare
2760 // the result against zero to select between true and false values.
2761 if (Tmp2.Val == 0) {
2762 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2763 CC = DAG.getCondCode(ISD::SETNE);
2765 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
2767 // Everything is legal, see if we should expand this op or something.
2768 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
2769 default: assert(0 && "This action is not supported yet!");
2770 case TargetLowering::Legal: break;
2771 case TargetLowering::Custom:
2772 Tmp1 = TLI.LowerOperation(Result, DAG);
2773 if (Tmp1.Val) Result = Tmp1;
2779 Tmp1 = Node->getOperand(0);
2780 Tmp2 = Node->getOperand(1);
2781 Tmp3 = Node->getOperand(2);
2782 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
2784 // If we had to Expand the SetCC operands into a SELECT node, then it may
2785 // not always be possible to return a true LHS & RHS. In this case, just
2786 // return the value we legalized, returned in the LHS
2787 if (Tmp2.Val == 0) {
2792 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
2793 default: assert(0 && "Cannot handle this action for SETCC yet!");
2794 case TargetLowering::Custom:
2797 case TargetLowering::Legal:
2798 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2800 Tmp4 = TLI.LowerOperation(Result, DAG);
2801 if (Tmp4.Val) Result = Tmp4;
2804 case TargetLowering::Promote: {
2805 // First step, figure out the appropriate operation to use.
2806 // Allow SETCC to not be supported for all legal data types
2807 // Mostly this targets FP
2808 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
2809 MVT::ValueType OldVT = NewInTy; OldVT = OldVT;
2811 // Scan for the appropriate larger type to use.
2813 NewInTy = (MVT::ValueType)(NewInTy+1);
2815 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
2816 "Fell off of the edge of the integer world");
2817 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
2818 "Fell off of the edge of the floating point world");
2820 // If the target supports SETCC of this type, use it.
2821 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2824 if (MVT::isInteger(NewInTy))
2825 assert(0 && "Cannot promote Legal Integer SETCC yet");
2827 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2828 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2830 Tmp1 = LegalizeOp(Tmp1);
2831 Tmp2 = LegalizeOp(Tmp2);
2832 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2833 Result = LegalizeOp(Result);
2836 case TargetLowering::Expand:
2837 // Expand a setcc node into a select_cc of the same condition, lhs, and
2838 // rhs that selects between const 1 (true) and const 0 (false).
2839 MVT::ValueType VT = Node->getValueType(0);
2840 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2841 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2847 case ISD::SHL_PARTS:
2848 case ISD::SRA_PARTS:
2849 case ISD::SRL_PARTS: {
2850 SmallVector<SDOperand, 8> Ops;
2851 bool Changed = false;
2852 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2853 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2854 Changed |= Ops.back() != Node->getOperand(i);
2857 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2859 switch (TLI.getOperationAction(Node->getOpcode(),
2860 Node->getValueType(0))) {
2861 default: assert(0 && "This action is not supported yet!");
2862 case TargetLowering::Legal: break;
2863 case TargetLowering::Custom:
2864 Tmp1 = TLI.LowerOperation(Result, DAG);
2866 SDOperand Tmp2, RetVal(0, 0);
2867 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2868 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2869 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2873 assert(RetVal.Val && "Illegal result number");
2879 // Since these produce multiple values, make sure to remember that we
2880 // legalized all of them.
2881 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2882 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2883 return Result.getValue(Op.ResNo);
2905 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2906 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2907 case Expand: assert(0 && "Not possible");
2909 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2912 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2916 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2918 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2919 default: assert(0 && "BinOp legalize operation not supported");
2920 case TargetLowering::Legal: break;
2921 case TargetLowering::Custom:
2922 Tmp1 = TLI.LowerOperation(Result, DAG);
2923 if (Tmp1.Val) Result = Tmp1;
2925 case TargetLowering::Expand: {
2926 MVT::ValueType VT = Op.getValueType();
2928 // See if multiply or divide can be lowered using two-result operations.
2929 SDVTList VTs = DAG.getVTList(VT, VT);
2930 if (Node->getOpcode() == ISD::MUL) {
2931 // We just need the low half of the multiply; try both the signed
2932 // and unsigned forms. If the target supports both SMUL_LOHI and
2933 // UMUL_LOHI, form a preference by checking which forms of plain
2934 // MULH it supports.
2935 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT);
2936 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT);
2937 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT);
2938 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT);
2939 unsigned OpToUse = 0;
2940 if (HasSMUL_LOHI && !HasMULHS) {
2941 OpToUse = ISD::SMUL_LOHI;
2942 } else if (HasUMUL_LOHI && !HasMULHU) {
2943 OpToUse = ISD::UMUL_LOHI;
2944 } else if (HasSMUL_LOHI) {
2945 OpToUse = ISD::SMUL_LOHI;
2946 } else if (HasUMUL_LOHI) {
2947 OpToUse = ISD::UMUL_LOHI;
2950 Result = SDOperand(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).Val, 0);
2954 if (Node->getOpcode() == ISD::MULHS &&
2955 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) {
2956 Result = SDOperand(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
2959 if (Node->getOpcode() == ISD::MULHU &&
2960 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) {
2961 Result = SDOperand(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
2964 if (Node->getOpcode() == ISD::SDIV &&
2965 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
2966 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 0);
2969 if (Node->getOpcode() == ISD::UDIV &&
2970 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
2971 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 0);
2975 // Check to see if we have a libcall for this operator.
2976 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2977 bool isSigned = false;
2978 switch (Node->getOpcode()) {
2981 if (VT == MVT::i32) {
2982 LC = Node->getOpcode() == ISD::UDIV
2983 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
2984 isSigned = Node->getOpcode() == ISD::SDIV;
2988 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
2989 RTLIB::POW_PPCF128);
2993 if (LC != RTLIB::UNKNOWN_LIBCALL) {
2995 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
2999 assert(MVT::isVector(Node->getValueType(0)) &&
3000 "Cannot expand this binary operator!");
3001 // Expand the operation into a bunch of nasty scalar code.
3002 Result = LegalizeOp(UnrollVectorOp(Op));
3005 case TargetLowering::Promote: {
3006 switch (Node->getOpcode()) {
3007 default: assert(0 && "Do not know how to promote this BinOp!");
3011 MVT::ValueType OVT = Node->getValueType(0);
3012 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3013 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
3014 // Bit convert each of the values to the new type.
3015 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
3016 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
3017 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3018 // Bit convert the result back the original type.
3019 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
3027 case ISD::SMUL_LOHI:
3028 case ISD::UMUL_LOHI:
3031 // These nodes will only be produced by target-specific lowering, so
3032 // they shouldn't be here if they aren't legal.
3033 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
3034 "This must be legal!");
3036 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3037 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3038 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3041 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
3042 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3043 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3044 case Expand: assert(0 && "Not possible");
3046 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3049 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3053 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3055 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3056 default: assert(0 && "Operation not supported");
3057 case TargetLowering::Custom:
3058 Tmp1 = TLI.LowerOperation(Result, DAG);
3059 if (Tmp1.Val) Result = Tmp1;
3061 case TargetLowering::Legal: break;
3062 case TargetLowering::Expand: {
3063 // If this target supports fabs/fneg natively and select is cheap,
3064 // do this efficiently.
3065 if (!TLI.isSelectExpensive() &&
3066 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
3067 TargetLowering::Legal &&
3068 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
3069 TargetLowering::Legal) {
3070 // Get the sign bit of the RHS.
3071 MVT::ValueType IVT =
3072 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
3073 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
3074 SignBit = DAG.getSetCC(TLI.getSetCCResultType(SignBit),
3075 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
3076 // Get the absolute value of the result.
3077 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
3078 // Select between the nabs and abs value based on the sign bit of
3080 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
3081 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
3084 Result = LegalizeOp(Result);
3088 // Otherwise, do bitwise ops!
3089 MVT::ValueType NVT =
3090 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
3091 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
3092 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
3093 Result = LegalizeOp(Result);
3101 Tmp1 = LegalizeOp(Node->getOperand(0));
3102 Tmp2 = LegalizeOp(Node->getOperand(1));
3103 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3104 // Since this produces two values, make sure to remember that we legalized
3106 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
3107 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
3112 Tmp1 = LegalizeOp(Node->getOperand(0));
3113 Tmp2 = LegalizeOp(Node->getOperand(1));
3114 Tmp3 = LegalizeOp(Node->getOperand(2));
3115 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3116 // Since this produces two values, make sure to remember that we legalized
3118 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
3119 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
3122 case ISD::BUILD_PAIR: {
3123 MVT::ValueType PairTy = Node->getValueType(0);
3124 // TODO: handle the case where the Lo and Hi operands are not of legal type
3125 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
3126 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
3127 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
3128 case TargetLowering::Promote:
3129 case TargetLowering::Custom:
3130 assert(0 && "Cannot promote/custom this yet!");
3131 case TargetLowering::Legal:
3132 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
3133 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
3135 case TargetLowering::Expand:
3136 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
3137 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
3138 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
3139 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
3140 TLI.getShiftAmountTy()));
3141 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
3150 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3151 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3153 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3154 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
3155 case TargetLowering::Custom:
3158 case TargetLowering::Legal:
3159 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3161 Tmp1 = TLI.LowerOperation(Result, DAG);
3162 if (Tmp1.Val) Result = Tmp1;
3165 case TargetLowering::Expand: {
3166 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
3167 bool isSigned = DivOpc == ISD::SDIV;
3168 MVT::ValueType VT = Node->getValueType(0);
3170 // See if remainder can be lowered using two-result operations.
3171 SDVTList VTs = DAG.getVTList(VT, VT);
3172 if (Node->getOpcode() == ISD::SREM &&
3173 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3174 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 1);
3177 if (Node->getOpcode() == ISD::UREM &&
3178 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3179 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 1);
3183 if (MVT::isInteger(VT)) {
3184 if (TLI.getOperationAction(DivOpc, VT) ==
3185 TargetLowering::Legal) {
3187 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
3188 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
3189 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
3190 } else if (MVT::isVector(VT)) {
3191 Result = LegalizeOp(UnrollVectorOp(Op));
3193 assert(VT == MVT::i32 &&
3194 "Cannot expand this binary operator!");
3195 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
3196 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
3198 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
3201 assert(MVT::isFloatingPoint(VT) &&
3202 "remainder op must have integer or floating-point type");
3203 if (MVT::isVector(VT)) {
3204 Result = LegalizeOp(UnrollVectorOp(Op));
3206 // Floating point mod -> fmod libcall.
3207 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
3208 RTLIB::REM_F80, RTLIB::REM_PPCF128);
3210 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3211 false/*sign irrelevant*/, Dummy);
3219 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3220 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3222 MVT::ValueType VT = Node->getValueType(0);
3223 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
3224 default: assert(0 && "This action is not supported yet!");
3225 case TargetLowering::Custom:
3228 case TargetLowering::Legal:
3229 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3230 Result = Result.getValue(0);
3231 Tmp1 = Result.getValue(1);
3234 Tmp2 = TLI.LowerOperation(Result, DAG);
3236 Result = LegalizeOp(Tmp2);
3237 Tmp1 = LegalizeOp(Tmp2.getValue(1));
3241 case TargetLowering::Expand: {
3242 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3243 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
3244 // Increment the pointer, VAList, to the next vaarg
3245 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3246 DAG.getConstant(MVT::getSizeInBits(VT)/8,
3247 TLI.getPointerTy()));
3248 // Store the incremented VAList to the legalized pointer
3249 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
3250 // Load the actual argument out of the pointer VAList
3251 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
3252 Tmp1 = LegalizeOp(Result.getValue(1));
3253 Result = LegalizeOp(Result);
3257 // Since VAARG produces two values, make sure to remember that we
3258 // legalized both of them.
3259 AddLegalizedOperand(SDOperand(Node, 0), Result);
3260 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
3261 return Op.ResNo ? Tmp1 : Result;
3265 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3266 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
3267 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
3269 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
3270 default: assert(0 && "This action is not supported yet!");
3271 case TargetLowering::Custom:
3274 case TargetLowering::Legal:
3275 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
3276 Node->getOperand(3), Node->getOperand(4));
3278 Tmp1 = TLI.LowerOperation(Result, DAG);
3279 if (Tmp1.Val) Result = Tmp1;
3282 case TargetLowering::Expand:
3283 // This defaults to loading a pointer from the input and storing it to the
3284 // output, returning the chain.
3285 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3286 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3287 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VD, 0);
3288 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VS, 0);
3294 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3295 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3297 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
3298 default: assert(0 && "This action is not supported yet!");
3299 case TargetLowering::Custom:
3302 case TargetLowering::Legal:
3303 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3305 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
3306 if (Tmp1.Val) Result = Tmp1;
3309 case TargetLowering::Expand:
3310 Result = Tmp1; // Default to a no-op, return the chain
3316 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3317 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3319 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3321 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
3322 default: assert(0 && "This action is not supported yet!");
3323 case TargetLowering::Legal: break;
3324 case TargetLowering::Custom:
3325 Tmp1 = TLI.LowerOperation(Result, DAG);
3326 if (Tmp1.Val) Result = Tmp1;
3333 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3334 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3335 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3336 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3338 assert(0 && "ROTL/ROTR legalize operation not supported");
3340 case TargetLowering::Legal:
3342 case TargetLowering::Custom:
3343 Tmp1 = TLI.LowerOperation(Result, DAG);
3344 if (Tmp1.Val) Result = Tmp1;
3346 case TargetLowering::Promote:
3347 assert(0 && "Do not know how to promote ROTL/ROTR");
3349 case TargetLowering::Expand:
3350 assert(0 && "Do not know how to expand ROTL/ROTR");
3356 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3357 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3358 case TargetLowering::Custom:
3359 assert(0 && "Cannot custom legalize this yet!");
3360 case TargetLowering::Legal:
3361 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3363 case TargetLowering::Promote: {
3364 MVT::ValueType OVT = Tmp1.getValueType();
3365 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3366 unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT);
3368 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3369 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3370 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3371 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3374 case TargetLowering::Expand:
3375 Result = ExpandBSWAP(Tmp1);
3383 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3384 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3385 case TargetLowering::Custom:
3386 case TargetLowering::Legal:
3387 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3388 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3389 TargetLowering::Custom) {
3390 Tmp1 = TLI.LowerOperation(Result, DAG);
3396 case TargetLowering::Promote: {
3397 MVT::ValueType OVT = Tmp1.getValueType();
3398 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3400 // Zero extend the argument.
3401 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3402 // Perform the larger operation, then subtract if needed.
3403 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
3404 switch (Node->getOpcode()) {
3409 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3410 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
3411 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
3413 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3414 DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1);
3417 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3418 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3419 DAG.getConstant(MVT::getSizeInBits(NVT) -
3420 MVT::getSizeInBits(OVT), NVT));
3425 case TargetLowering::Expand:
3426 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
3437 Tmp1 = LegalizeOp(Node->getOperand(0));
3438 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3439 case TargetLowering::Promote:
3440 case TargetLowering::Custom:
3443 case TargetLowering::Legal:
3444 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3446 Tmp1 = TLI.LowerOperation(Result, DAG);
3447 if (Tmp1.Val) Result = Tmp1;
3450 case TargetLowering::Expand:
3451 switch (Node->getOpcode()) {
3452 default: assert(0 && "Unreachable!");
3454 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3455 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3456 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
3459 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3460 MVT::ValueType VT = Node->getValueType(0);
3461 Tmp2 = DAG.getConstantFP(0.0, VT);
3462 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
3464 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
3465 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
3471 MVT::ValueType VT = Node->getValueType(0);
3473 // Expand unsupported unary vector operators by unrolling them.
3474 if (MVT::isVector(VT)) {
3475 Result = LegalizeOp(UnrollVectorOp(Op));
3479 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3480 switch(Node->getOpcode()) {
3482 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3483 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
3486 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
3487 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
3490 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
3491 RTLIB::COS_F80, RTLIB::COS_PPCF128);
3493 default: assert(0 && "Unreachable!");
3496 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3497 false/*sign irrelevant*/, Dummy);
3505 MVT::ValueType VT = Node->getValueType(0);
3507 // Expand unsupported unary vector operators by unrolling them.
3508 if (MVT::isVector(VT)) {
3509 Result = LegalizeOp(UnrollVectorOp(Op));
3513 // We always lower FPOWI into a libcall. No target support for it yet.
3514 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
3515 RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
3517 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3518 false/*sign irrelevant*/, Dummy);
3521 case ISD::BIT_CONVERT:
3522 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3523 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3524 Node->getValueType(0));
3525 } else if (MVT::isVector(Op.getOperand(0).getValueType())) {
3526 // The input has to be a vector type, we have to either scalarize it, pack
3527 // it, or convert it based on whether the input vector type is legal.
3528 SDNode *InVal = Node->getOperand(0).Val;
3529 int InIx = Node->getOperand(0).ResNo;
3530 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx));
3531 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx));
3533 // Figure out if there is a simple type corresponding to this Vector
3534 // type. If so, convert to the vector type.
3535 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
3536 if (TLI.isTypeLegal(TVT)) {
3537 // Turn this into a bit convert of the vector input.
3538 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3539 LegalizeOp(Node->getOperand(0)));
3541 } else if (NumElems == 1) {
3542 // Turn this into a bit convert of the scalar input.
3543 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3544 ScalarizeVectorOp(Node->getOperand(0)));
3547 // FIXME: UNIMP! Store then reload
3548 assert(0 && "Cast from unsupported vector type not implemented yet!");
3551 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3552 Node->getOperand(0).getValueType())) {
3553 default: assert(0 && "Unknown operation action!");
3554 case TargetLowering::Expand:
3555 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3556 Node->getValueType(0));
3558 case TargetLowering::Legal:
3559 Tmp1 = LegalizeOp(Node->getOperand(0));
3560 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3566 // Conversion operators. The source and destination have different types.
3567 case ISD::SINT_TO_FP:
3568 case ISD::UINT_TO_FP: {
3569 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
3570 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3572 switch (TLI.getOperationAction(Node->getOpcode(),
3573 Node->getOperand(0).getValueType())) {
3574 default: assert(0 && "Unknown operation action!");
3575 case TargetLowering::Custom:
3578 case TargetLowering::Legal:
3579 Tmp1 = LegalizeOp(Node->getOperand(0));
3580 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3582 Tmp1 = TLI.LowerOperation(Result, DAG);
3583 if (Tmp1.Val) Result = Tmp1;
3586 case TargetLowering::Expand:
3587 Result = ExpandLegalINT_TO_FP(isSigned,
3588 LegalizeOp(Node->getOperand(0)),
3589 Node->getValueType(0));
3591 case TargetLowering::Promote:
3592 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
3593 Node->getValueType(0),
3599 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
3600 Node->getValueType(0), Node->getOperand(0));
3603 Tmp1 = PromoteOp(Node->getOperand(0));
3605 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
3606 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
3608 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
3609 Node->getOperand(0).getValueType());
3611 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3612 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
3618 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3620 Tmp1 = LegalizeOp(Node->getOperand(0));
3621 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3624 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3626 // Since the result is legal, we should just be able to truncate the low
3627 // part of the source.
3628 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
3631 Result = PromoteOp(Node->getOperand(0));
3632 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
3637 case ISD::FP_TO_SINT:
3638 case ISD::FP_TO_UINT:
3639 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3641 Tmp1 = LegalizeOp(Node->getOperand(0));
3643 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
3644 default: assert(0 && "Unknown operation action!");
3645 case TargetLowering::Custom:
3648 case TargetLowering::Legal:
3649 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3651 Tmp1 = TLI.LowerOperation(Result, DAG);
3652 if (Tmp1.Val) Result = Tmp1;
3655 case TargetLowering::Promote:
3656 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
3657 Node->getOpcode() == ISD::FP_TO_SINT);
3659 case TargetLowering::Expand:
3660 if (Node->getOpcode() == ISD::FP_TO_UINT) {
3661 SDOperand True, False;
3662 MVT::ValueType VT = Node->getOperand(0).getValueType();
3663 MVT::ValueType NVT = Node->getValueType(0);
3664 const uint64_t zero[] = {0, 0};
3665 APFloat apf = APFloat(APInt(MVT::getSizeInBits(VT), 2, zero));
3666 APInt x = APInt::getSignBit(MVT::getSizeInBits(NVT));
3667 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
3668 Tmp2 = DAG.getConstantFP(apf, VT);
3669 Tmp3 = DAG.getSetCC(TLI.getSetCCResultType(Node->getOperand(0)),
3670 Node->getOperand(0), Tmp2, ISD::SETLT);
3671 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
3672 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
3673 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
3675 False = DAG.getNode(ISD::XOR, NVT, False,
3676 DAG.getConstant(x, NVT));
3677 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
3680 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
3686 MVT::ValueType VT = Op.getValueType();
3687 MVT::ValueType OVT = Node->getOperand(0).getValueType();
3688 // Convert ppcf128 to i32
3689 if (OVT == MVT::ppcf128 && VT == MVT::i32) {
3690 if (Node->getOpcode() == ISD::FP_TO_SINT) {
3691 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128,
3692 Node->getOperand(0), DAG.getValueType(MVT::f64));
3693 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result,
3694 DAG.getIntPtrConstant(1));
3695 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result);
3697 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
3698 APFloat apf = APFloat(APInt(128, 2, TwoE31));
3699 Tmp2 = DAG.getConstantFP(apf, OVT);
3700 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
3701 // FIXME: generated code sucks.
3702 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2,
3703 DAG.getNode(ISD::ADD, MVT::i32,
3704 DAG.getNode(ISD::FP_TO_SINT, VT,
3705 DAG.getNode(ISD::FSUB, OVT,
3706 Node->getOperand(0), Tmp2)),
3707 DAG.getConstant(0x80000000, MVT::i32)),
3708 DAG.getNode(ISD::FP_TO_SINT, VT,
3709 Node->getOperand(0)),
3710 DAG.getCondCode(ISD::SETGE));
3714 // Convert f32 / f64 to i32 / i64 / i128.
3715 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3716 switch (Node->getOpcode()) {
3717 case ISD::FP_TO_SINT: {
3718 if (VT == MVT::i32) {
3719 if (OVT == MVT::f32)
3720 LC = RTLIB::FPTOSINT_F32_I32;
3721 else if (OVT == MVT::f64)
3722 LC = RTLIB::FPTOSINT_F64_I32;
3724 assert(0 && "Unexpected i32-to-fp conversion!");
3725 } else if (VT == MVT::i64) {
3726 if (OVT == MVT::f32)
3727 LC = RTLIB::FPTOSINT_F32_I64;
3728 else if (OVT == MVT::f64)
3729 LC = RTLIB::FPTOSINT_F64_I64;
3730 else if (OVT == MVT::f80)
3731 LC = RTLIB::FPTOSINT_F80_I64;
3732 else if (OVT == MVT::ppcf128)
3733 LC = RTLIB::FPTOSINT_PPCF128_I64;
3735 assert(0 && "Unexpected i64-to-fp conversion!");
3736 } else if (VT == MVT::i128) {
3737 if (OVT == MVT::f32)
3738 LC = RTLIB::FPTOSINT_F32_I128;
3739 else if (OVT == MVT::f64)
3740 LC = RTLIB::FPTOSINT_F64_I128;
3741 else if (OVT == MVT::f80)
3742 LC = RTLIB::FPTOSINT_F80_I128;
3743 else if (OVT == MVT::ppcf128)
3744 LC = RTLIB::FPTOSINT_PPCF128_I128;
3746 assert(0 && "Unexpected i128-to-fp conversion!");
3748 assert(0 && "Unexpectd int-to-fp conversion!");
3752 case ISD::FP_TO_UINT: {
3753 if (VT == MVT::i32) {
3754 if (OVT == MVT::f32)
3755 LC = RTLIB::FPTOUINT_F32_I32;
3756 else if (OVT == MVT::f64)
3757 LC = RTLIB::FPTOUINT_F64_I32;
3758 else if (OVT == MVT::f80)
3759 LC = RTLIB::FPTOUINT_F80_I32;
3761 assert(0 && "Unexpected i32-to-fp conversion!");
3762 } else if (VT == MVT::i64) {
3763 if (OVT == MVT::f32)
3764 LC = RTLIB::FPTOUINT_F32_I64;
3765 else if (OVT == MVT::f64)
3766 LC = RTLIB::FPTOUINT_F64_I64;
3767 else if (OVT == MVT::f80)
3768 LC = RTLIB::FPTOUINT_F80_I64;
3769 else if (OVT == MVT::ppcf128)
3770 LC = RTLIB::FPTOUINT_PPCF128_I64;
3772 assert(0 && "Unexpected i64-to-fp conversion!");
3773 } else if (VT == MVT::i128) {
3774 if (OVT == MVT::f32)
3775 LC = RTLIB::FPTOUINT_F32_I128;
3776 else if (OVT == MVT::f64)
3777 LC = RTLIB::FPTOUINT_F64_I128;
3778 else if (OVT == MVT::f80)
3779 LC = RTLIB::FPTOUINT_F80_I128;
3780 else if (OVT == MVT::ppcf128)
3781 LC = RTLIB::FPTOUINT_PPCF128_I128;
3783 assert(0 && "Unexpected i128-to-fp conversion!");
3785 assert(0 && "Unexpectd int-to-fp conversion!");
3789 default: assert(0 && "Unreachable!");
3792 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3793 false/*sign irrelevant*/, Dummy);
3797 Tmp1 = PromoteOp(Node->getOperand(0));
3798 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
3799 Result = LegalizeOp(Result);
3804 case ISD::FP_EXTEND: {
3805 MVT::ValueType DstVT = Op.getValueType();
3806 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3807 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3808 // The only other way we can lower this is to turn it into a STORE,
3809 // LOAD pair, targetting a temporary location (a stack slot).
3810 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT);
3813 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3814 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3816 Tmp1 = LegalizeOp(Node->getOperand(0));
3817 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3820 Tmp1 = PromoteOp(Node->getOperand(0));
3821 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1);
3826 case ISD::FP_ROUND: {
3827 MVT::ValueType DstVT = Op.getValueType();
3828 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3829 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3830 if (SrcVT == MVT::ppcf128) {
3832 ExpandOp(Node->getOperand(0), Lo, Result);
3833 // Round it the rest of the way (e.g. to f32) if needed.
3834 if (DstVT!=MVT::f64)
3835 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1));
3838 // The only other way we can lower this is to turn it into a STORE,
3839 // LOAD pair, targetting a temporary location (a stack slot).
3840 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT);
3843 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3844 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3846 Tmp1 = LegalizeOp(Node->getOperand(0));
3847 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3850 Tmp1 = PromoteOp(Node->getOperand(0));
3851 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1,
3852 Node->getOperand(1));
3857 case ISD::ANY_EXTEND:
3858 case ISD::ZERO_EXTEND:
3859 case ISD::SIGN_EXTEND:
3860 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3861 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3863 Tmp1 = LegalizeOp(Node->getOperand(0));
3864 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3865 TargetLowering::Custom) {
3866 Tmp2 = TLI.LowerOperation(Result, DAG);
3871 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3874 switch (Node->getOpcode()) {
3875 case ISD::ANY_EXTEND:
3876 Tmp1 = PromoteOp(Node->getOperand(0));
3877 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
3879 case ISD::ZERO_EXTEND:
3880 Result = PromoteOp(Node->getOperand(0));
3881 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3882 Result = DAG.getZeroExtendInReg(Result,
3883 Node->getOperand(0).getValueType());
3885 case ISD::SIGN_EXTEND:
3886 Result = PromoteOp(Node->getOperand(0));
3887 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3888 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3890 DAG.getValueType(Node->getOperand(0).getValueType()));
3895 case ISD::FP_ROUND_INREG:
3896 case ISD::SIGN_EXTEND_INREG: {
3897 Tmp1 = LegalizeOp(Node->getOperand(0));
3898 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3900 // If this operation is not supported, convert it to a shl/shr or load/store
3902 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
3903 default: assert(0 && "This action not supported for this op yet!");
3904 case TargetLowering::Legal:
3905 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3907 case TargetLowering::Expand:
3908 // If this is an integer extend and shifts are supported, do that.
3909 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
3910 // NOTE: we could fall back on load/store here too for targets without
3911 // SAR. However, it is doubtful that any exist.
3912 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
3913 MVT::getSizeInBits(ExtraVT);
3914 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
3915 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
3916 Node->getOperand(0), ShiftCst);
3917 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
3919 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
3920 // The only way we can lower this is to turn it into a TRUNCSTORE,
3921 // EXTLOAD pair, targetting a temporary location (a stack slot).
3923 // NOTE: there is a choice here between constantly creating new stack
3924 // slots and always reusing the same one. We currently always create
3925 // new ones, as reuse may inhibit scheduling.
3926 Result = EmitStackConvert(Node->getOperand(0), ExtraVT,
3927 Node->getValueType(0));
3929 assert(0 && "Unknown op");
3935 case ISD::TRAMPOLINE: {
3937 for (unsigned i = 0; i != 6; ++i)
3938 Ops[i] = LegalizeOp(Node->getOperand(i));
3939 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
3940 // The only option for this node is to custom lower it.
3941 Result = TLI.LowerOperation(Result, DAG);
3942 assert(Result.Val && "Should always custom lower!");
3944 // Since trampoline produces two values, make sure to remember that we
3945 // legalized both of them.
3946 Tmp1 = LegalizeOp(Result.getValue(1));
3947 Result = LegalizeOp(Result);
3948 AddLegalizedOperand(SDOperand(Node, 0), Result);
3949 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
3950 return Op.ResNo ? Tmp1 : Result;
3952 case ISD::FLT_ROUNDS_: {
3953 MVT::ValueType VT = Node->getValueType(0);
3954 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
3955 default: assert(0 && "This action not supported for this op yet!");
3956 case TargetLowering::Custom:
3957 Result = TLI.LowerOperation(Op, DAG);
3958 if (Result.Val) break;
3960 case TargetLowering::Legal:
3961 // If this operation is not supported, lower it to constant 1
3962 Result = DAG.getConstant(1, VT);
3967 MVT::ValueType VT = Node->getValueType(0);
3968 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
3969 default: assert(0 && "This action not supported for this op yet!");
3970 case TargetLowering::Legal:
3971 Tmp1 = LegalizeOp(Node->getOperand(0));
3972 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3974 case TargetLowering::Custom:
3975 Result = TLI.LowerOperation(Op, DAG);
3976 if (Result.Val) break;
3978 case TargetLowering::Expand:
3979 // If this operation is not supported, lower it to 'abort()' call
3980 Tmp1 = LegalizeOp(Node->getOperand(0));
3981 TargetLowering::ArgListTy Args;
3982 std::pair<SDOperand,SDOperand> CallResult =
3983 TLI.LowerCallTo(Tmp1, Type::VoidTy,
3984 false, false, false, CallingConv::C, false,
3985 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
3987 Result = CallResult.second;
3994 assert(Result.getValueType() == Op.getValueType() &&
3995 "Bad legalization!");
3997 // Make sure that the generated code is itself legal.
3999 Result = LegalizeOp(Result);
4001 // Note that LegalizeOp may be reentered even from single-use nodes, which
4002 // means that we always must cache transformed nodes.
4003 AddLegalizedOperand(Op, Result);
4007 /// PromoteOp - Given an operation that produces a value in an invalid type,
4008 /// promote it to compute the value into a larger type. The produced value will
4009 /// have the correct bits for the low portion of the register, but no guarantee
4010 /// is made about the top bits: it may be zero, sign-extended, or garbage.
4011 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
4012 MVT::ValueType VT = Op.getValueType();
4013 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4014 assert(getTypeAction(VT) == Promote &&
4015 "Caller should expand or legalize operands that are not promotable!");
4016 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
4017 "Cannot promote to smaller type!");
4019 SDOperand Tmp1, Tmp2, Tmp3;
4021 SDNode *Node = Op.Val;
4023 DenseMap<SDOperandImpl, SDOperand>::iterator I = PromotedNodes.find(Op);
4024 if (I != PromotedNodes.end()) return I->second;
4026 switch (Node->getOpcode()) {
4027 case ISD::CopyFromReg:
4028 assert(0 && "CopyFromReg must be legal!");
4031 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
4033 assert(0 && "Do not know how to promote this operator!");
4036 Result = DAG.getNode(ISD::UNDEF, NVT);
4040 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
4042 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
4043 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
4045 case ISD::ConstantFP:
4046 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
4047 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
4051 assert(isTypeLegal(TLI.getSetCCResultType(Node->getOperand(0)))
4052 && "SetCC type is not legal??");
4053 Result = DAG.getNode(ISD::SETCC,
4054 TLI.getSetCCResultType(Node->getOperand(0)),
4055 Node->getOperand(0), Node->getOperand(1),
4056 Node->getOperand(2));
4060 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4062 Result = LegalizeOp(Node->getOperand(0));
4063 assert(Result.getValueType() >= NVT &&
4064 "This truncation doesn't make sense!");
4065 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
4066 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
4069 // The truncation is not required, because we don't guarantee anything
4070 // about high bits anyway.
4071 Result = PromoteOp(Node->getOperand(0));
4074 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4075 // Truncate the low part of the expanded value to the result type
4076 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
4079 case ISD::SIGN_EXTEND:
4080 case ISD::ZERO_EXTEND:
4081 case ISD::ANY_EXTEND:
4082 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4083 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
4085 // Input is legal? Just do extend all the way to the larger type.
4086 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4089 // Promote the reg if it's smaller.
4090 Result = PromoteOp(Node->getOperand(0));
4091 // The high bits are not guaranteed to be anything. Insert an extend.
4092 if (Node->getOpcode() == ISD::SIGN_EXTEND)
4093 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4094 DAG.getValueType(Node->getOperand(0).getValueType()));
4095 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
4096 Result = DAG.getZeroExtendInReg(Result,
4097 Node->getOperand(0).getValueType());
4101 case ISD::BIT_CONVERT:
4102 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
4103 Node->getValueType(0));
4104 Result = PromoteOp(Result);
4107 case ISD::FP_EXTEND:
4108 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
4110 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4111 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
4112 case Promote: assert(0 && "Unreachable with 2 FP types!");
4114 if (Node->getConstantOperandVal(1) == 0) {
4115 // Input is legal? Do an FP_ROUND_INREG.
4116 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
4117 DAG.getValueType(VT));
4119 // Just remove the truncate, it isn't affecting the value.
4120 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0),
4121 Node->getOperand(1));
4126 case ISD::SINT_TO_FP:
4127 case ISD::UINT_TO_FP:
4128 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4130 // No extra round required here.
4131 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4135 Result = PromoteOp(Node->getOperand(0));
4136 if (Node->getOpcode() == ISD::SINT_TO_FP)
4137 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
4139 DAG.getValueType(Node->getOperand(0).getValueType()));
4141 Result = DAG.getZeroExtendInReg(Result,
4142 Node->getOperand(0).getValueType());
4143 // No extra round required here.
4144 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
4147 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
4148 Node->getOperand(0));
4149 // Round if we cannot tolerate excess precision.
4150 if (NoExcessFPPrecision)
4151 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4152 DAG.getValueType(VT));
4157 case ISD::SIGN_EXTEND_INREG:
4158 Result = PromoteOp(Node->getOperand(0));
4159 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4160 Node->getOperand(1));
4162 case ISD::FP_TO_SINT:
4163 case ISD::FP_TO_UINT:
4164 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4167 Tmp1 = Node->getOperand(0);
4170 // The input result is prerounded, so we don't have to do anything
4172 Tmp1 = PromoteOp(Node->getOperand(0));
4175 // If we're promoting a UINT to a larger size, check to see if the new node
4176 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
4177 // we can use that instead. This allows us to generate better code for
4178 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
4179 // legal, such as PowerPC.
4180 if (Node->getOpcode() == ISD::FP_TO_UINT &&
4181 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
4182 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
4183 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
4184 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
4186 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4192 Tmp1 = PromoteOp(Node->getOperand(0));
4193 assert(Tmp1.getValueType() == NVT);
4194 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4195 // NOTE: we do not have to do any extra rounding here for
4196 // NoExcessFPPrecision, because we know the input will have the appropriate
4197 // precision, and these operations don't modify precision at all.
4203 Tmp1 = PromoteOp(Node->getOperand(0));
4204 assert(Tmp1.getValueType() == NVT);
4205 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4206 if (NoExcessFPPrecision)
4207 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4208 DAG.getValueType(VT));
4212 // Promote f32 powi to f64 powi. Note that this could insert a libcall
4213 // directly as well, which may be better.
4214 Tmp1 = PromoteOp(Node->getOperand(0));
4215 assert(Tmp1.getValueType() == NVT);
4216 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1));
4217 if (NoExcessFPPrecision)
4218 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4219 DAG.getValueType(VT));
4223 case ISD::ATOMIC_LCS: {
4224 Tmp2 = PromoteOp(Node->getOperand(2));
4225 Tmp3 = PromoteOp(Node->getOperand(3));
4226 Result = DAG.getAtomic(Node->getOpcode(), Node->getOperand(0),
4227 Node->getOperand(1), Tmp2, Tmp3,
4228 cast<AtomicSDNode>(Node)->getVT());
4229 // Remember that we legalized the chain.
4230 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4233 case ISD::ATOMIC_LAS:
4234 case ISD::ATOMIC_SWAP: {
4235 Tmp2 = PromoteOp(Node->getOperand(2));
4236 Result = DAG.getAtomic(Node->getOpcode(), Node->getOperand(0),
4237 Node->getOperand(1), Tmp2,
4238 cast<AtomicSDNode>(Node)->getVT());
4239 // Remember that we legalized the chain.
4240 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4250 // The input may have strange things in the top bits of the registers, but
4251 // these operations don't care. They may have weird bits going out, but
4252 // that too is okay if they are integer operations.
4253 Tmp1 = PromoteOp(Node->getOperand(0));
4254 Tmp2 = PromoteOp(Node->getOperand(1));
4255 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4256 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4261 Tmp1 = PromoteOp(Node->getOperand(0));
4262 Tmp2 = PromoteOp(Node->getOperand(1));
4263 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4264 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4266 // Floating point operations will give excess precision that we may not be
4267 // able to tolerate. If we DO allow excess precision, just leave it,
4268 // otherwise excise it.
4269 // FIXME: Why would we need to round FP ops more than integer ones?
4270 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
4271 if (NoExcessFPPrecision)
4272 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4273 DAG.getValueType(VT));
4278 // These operators require that their input be sign extended.
4279 Tmp1 = PromoteOp(Node->getOperand(0));
4280 Tmp2 = PromoteOp(Node->getOperand(1));
4281 if (MVT::isInteger(NVT)) {
4282 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4283 DAG.getValueType(VT));
4284 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4285 DAG.getValueType(VT));
4287 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4289 // Perform FP_ROUND: this is probably overly pessimistic.
4290 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
4291 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4292 DAG.getValueType(VT));
4296 case ISD::FCOPYSIGN:
4297 // These operators require that their input be fp extended.
4298 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4299 case Expand: assert(0 && "not implemented");
4300 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break;
4301 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break;
4303 switch (getTypeAction(Node->getOperand(1).getValueType())) {
4304 case Expand: assert(0 && "not implemented");
4305 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
4306 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
4308 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4310 // Perform FP_ROUND: this is probably overly pessimistic.
4311 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
4312 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4313 DAG.getValueType(VT));
4318 // These operators require that their input be zero extended.
4319 Tmp1 = PromoteOp(Node->getOperand(0));
4320 Tmp2 = PromoteOp(Node->getOperand(1));
4321 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
4322 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4323 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4324 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4328 Tmp1 = PromoteOp(Node->getOperand(0));
4329 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
4332 // The input value must be properly sign extended.
4333 Tmp1 = PromoteOp(Node->getOperand(0));
4334 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4335 DAG.getValueType(VT));
4336 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
4339 // The input value must be properly zero extended.
4340 Tmp1 = PromoteOp(Node->getOperand(0));
4341 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4342 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
4346 Tmp1 = Node->getOperand(0); // Get the chain.
4347 Tmp2 = Node->getOperand(1); // Get the pointer.
4348 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
4349 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
4350 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
4352 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
4353 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
4354 // Increment the pointer, VAList, to the next vaarg
4355 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
4356 DAG.getConstant(MVT::getSizeInBits(VT)/8,
4357 TLI.getPointerTy()));
4358 // Store the incremented VAList to the legalized pointer
4359 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
4360 // Load the actual argument out of the pointer VAList
4361 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
4363 // Remember that we legalized the chain.
4364 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4368 LoadSDNode *LD = cast<LoadSDNode>(Node);
4369 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
4370 ? ISD::EXTLOAD : LD->getExtensionType();
4371 Result = DAG.getExtLoad(ExtType, NVT,
4372 LD->getChain(), LD->getBasePtr(),
4373 LD->getSrcValue(), LD->getSrcValueOffset(),
4376 LD->getAlignment());
4377 // Remember that we legalized the chain.
4378 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4382 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
4383 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
4384 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
4386 case ISD::SELECT_CC:
4387 Tmp2 = PromoteOp(Node->getOperand(2)); // True
4388 Tmp3 = PromoteOp(Node->getOperand(3)); // False
4389 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4390 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
4393 Tmp1 = Node->getOperand(0);
4394 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
4395 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
4396 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
4397 DAG.getConstant(MVT::getSizeInBits(NVT) -
4398 MVT::getSizeInBits(VT),
4399 TLI.getShiftAmountTy()));
4404 // Zero extend the argument
4405 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4406 // Perform the larger operation, then subtract if needed.
4407 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4408 switch(Node->getOpcode()) {
4413 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
4414 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
4415 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
4417 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
4418 DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1);
4421 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4422 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
4423 DAG.getConstant(MVT::getSizeInBits(NVT) -
4424 MVT::getSizeInBits(VT), NVT));
4428 case ISD::EXTRACT_SUBVECTOR:
4429 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
4431 case ISD::EXTRACT_VECTOR_ELT:
4432 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
4436 assert(Result.Val && "Didn't set a result!");
4438 // Make sure the result is itself legal.
4439 Result = LegalizeOp(Result);
4441 // Remember that we promoted this!
4442 AddPromotedOperand(Op, Result);
4446 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
4447 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
4448 /// based on the vector type. The return type of this matches the element type
4449 /// of the vector, which may not be legal for the target.
4450 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
4451 // We know that operand #0 is the Vec vector. If the index is a constant
4452 // or if the invec is a supported hardware type, we can use it. Otherwise,
4453 // lower to a store then an indexed load.
4454 SDOperand Vec = Op.getOperand(0);
4455 SDOperand Idx = Op.getOperand(1);
4457 MVT::ValueType TVT = Vec.getValueType();
4458 unsigned NumElems = MVT::getVectorNumElements(TVT);
4460 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
4461 default: assert(0 && "This action is not supported yet!");
4462 case TargetLowering::Custom: {
4463 Vec = LegalizeOp(Vec);
4464 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4465 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG);
4470 case TargetLowering::Legal:
4471 if (isTypeLegal(TVT)) {
4472 Vec = LegalizeOp(Vec);
4473 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4477 case TargetLowering::Expand:
4481 if (NumElems == 1) {
4482 // This must be an access of the only element. Return it.
4483 Op = ScalarizeVectorOp(Vec);
4484 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
4485 unsigned NumLoElts = 1 << Log2_32(NumElems-1);
4486 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4488 SplitVectorOp(Vec, Lo, Hi);
4489 if (CIdx->getValue() < NumLoElts) {
4493 Idx = DAG.getConstant(CIdx->getValue() - NumLoElts,
4494 Idx.getValueType());
4497 // It's now an extract from the appropriate high or low part. Recurse.
4498 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4499 Op = ExpandEXTRACT_VECTOR_ELT(Op);
4501 // Store the value to a temporary stack slot, then LOAD the scalar
4502 // element back out.
4503 SDOperand StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
4504 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
4506 // Add the offset to the index.
4507 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
4508 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
4509 DAG.getConstant(EltSize, Idx.getValueType()));
4511 if (MVT::getSizeInBits(Idx.getValueType()) >
4512 MVT::getSizeInBits(TLI.getPointerTy()))
4513 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx);
4515 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
4517 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
4519 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
4524 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
4525 /// we assume the operation can be split if it is not already legal.
4526 SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) {
4527 // We know that operand #0 is the Vec vector. For now we assume the index
4528 // is a constant and that the extracted result is a supported hardware type.
4529 SDOperand Vec = Op.getOperand(0);
4530 SDOperand Idx = LegalizeOp(Op.getOperand(1));
4532 unsigned NumElems = MVT::getVectorNumElements(Vec.getValueType());
4534 if (NumElems == MVT::getVectorNumElements(Op.getValueType())) {
4535 // This must be an access of the desired vector length. Return it.
4539 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4541 SplitVectorOp(Vec, Lo, Hi);
4542 if (CIdx->getValue() < NumElems/2) {
4546 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
4549 // It's now an extract from the appropriate high or low part. Recurse.
4550 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4551 return ExpandEXTRACT_SUBVECTOR(Op);
4554 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
4555 /// with condition CC on the current target. This usually involves legalizing
4556 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
4557 /// there may be no choice but to create a new SetCC node to represent the
4558 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
4559 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
4560 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
4563 SDOperand Tmp1, Tmp2, Tmp3, Result;
4565 switch (getTypeAction(LHS.getValueType())) {
4567 Tmp1 = LegalizeOp(LHS); // LHS
4568 Tmp2 = LegalizeOp(RHS); // RHS
4571 Tmp1 = PromoteOp(LHS); // LHS
4572 Tmp2 = PromoteOp(RHS); // RHS
4574 // If this is an FP compare, the operands have already been extended.
4575 if (MVT::isInteger(LHS.getValueType())) {
4576 MVT::ValueType VT = LHS.getValueType();
4577 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4579 // Otherwise, we have to insert explicit sign or zero extends. Note
4580 // that we could insert sign extends for ALL conditions, but zero extend
4581 // is cheaper on many machines (an AND instead of two shifts), so prefer
4583 switch (cast<CondCodeSDNode>(CC)->get()) {
4584 default: assert(0 && "Unknown integer comparison!");
4591 // ALL of these operations will work if we either sign or zero extend
4592 // the operands (including the unsigned comparisons!). Zero extend is
4593 // usually a simpler/cheaper operation, so prefer it.
4594 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4595 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4601 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4602 DAG.getValueType(VT));
4603 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4604 DAG.getValueType(VT));
4610 MVT::ValueType VT = LHS.getValueType();
4611 if (VT == MVT::f32 || VT == MVT::f64) {
4612 // Expand into one or more soft-fp libcall(s).
4613 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL;
4614 switch (cast<CondCodeSDNode>(CC)->get()) {
4617 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4621 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
4625 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4629 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4633 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4637 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4640 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4643 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
4646 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4647 switch (cast<CondCodeSDNode>(CC)->get()) {
4649 // SETONE = SETOLT | SETOGT
4650 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4653 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4656 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4659 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4662 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4665 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4667 default: assert(0 && "Unsupported FP setcc!");
4672 Tmp1 = ExpandLibCall(TLI.getLibcallName(LC1),
4673 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4674 false /*sign irrelevant*/, Dummy);
4675 Tmp2 = DAG.getConstant(0, MVT::i32);
4676 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
4677 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
4678 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
4680 LHS = ExpandLibCall(TLI.getLibcallName(LC2),
4681 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4682 false /*sign irrelevant*/, Dummy);
4683 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, Tmp2,
4684 DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
4685 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4693 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
4694 ExpandOp(LHS, LHSLo, LHSHi);
4695 ExpandOp(RHS, RHSLo, RHSHi);
4696 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
4698 if (VT==MVT::ppcf128) {
4699 // FIXME: This generated code sucks. We want to generate
4700 // FCMP crN, hi1, hi2
4702 // FCMP crN, lo1, lo2
4703 // The following can be improved, but not that much.
4704 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETEQ);
4705 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, CCCode);
4706 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4707 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETNE);
4708 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode);
4709 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4710 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
4719 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
4720 if (RHSCST->isAllOnesValue()) {
4721 // Comparison to -1.
4722 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
4727 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
4728 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
4729 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4730 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
4733 // If this is a comparison of the sign bit, just look at the top part.
4735 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
4736 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
4737 CST->isNullValue()) || // X < 0
4738 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
4739 CST->isAllOnesValue())) { // X > -1
4745 // FIXME: This generated code sucks.
4746 ISD::CondCode LowCC;
4748 default: assert(0 && "Unknown integer setcc!");
4750 case ISD::SETULT: LowCC = ISD::SETULT; break;
4752 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
4754 case ISD::SETULE: LowCC = ISD::SETULE; break;
4756 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
4759 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
4760 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
4761 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
4763 // NOTE: on targets without efficient SELECT of bools, we can always use
4764 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
4765 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
4766 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo,
4767 LowCC, false, DagCombineInfo);
4769 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC);
4770 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4771 CCCode, false, DagCombineInfo);
4773 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi,
4776 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
4777 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
4778 if ((Tmp1C && Tmp1C->isNullValue()) ||
4779 (Tmp2C && Tmp2C->isNullValue() &&
4780 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
4781 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
4782 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
4783 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
4784 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
4785 // low part is known false, returns high part.
4786 // For LE / GE, if high part is known false, ignore the low part.
4787 // For LT / GT, if high part is known true, ignore the low part.
4791 Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4792 ISD::SETEQ, false, DagCombineInfo);
4794 Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4796 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
4797 Result, Tmp1, Tmp2));
4808 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
4809 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
4810 /// a load from the stack slot to DestVT, extending it if needed.
4811 /// The resultant code need not be legal.
4812 SDOperand SelectionDAGLegalize::EmitStackConvert(SDOperand SrcOp,
4813 MVT::ValueType SlotVT,
4814 MVT::ValueType DestVT) {
4815 // Create the stack frame object.
4816 SDOperand FIPtr = DAG.CreateStackTemporary(SlotVT);
4818 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
4819 int SPFI = StackPtrFI->getIndex();
4821 unsigned SrcSize = MVT::getSizeInBits(SrcOp.getValueType());
4822 unsigned SlotSize = MVT::getSizeInBits(SlotVT);
4823 unsigned DestSize = MVT::getSizeInBits(DestVT);
4825 // Emit a store to the stack slot. Use a truncstore if the input value is
4826 // later than DestVT.
4828 if (SrcSize > SlotSize)
4829 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr,
4830 PseudoSourceValue::getFixedStack(),
4833 assert(SrcSize == SlotSize && "Invalid store");
4834 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr,
4835 PseudoSourceValue::getFixedStack(),
4839 // Result is a load from the stack slot.
4840 if (SlotSize == DestSize)
4841 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0);
4843 assert(SlotSize < DestSize && "Unknown extension!");
4844 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT);
4847 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
4848 // Create a vector sized/aligned stack slot, store the value to element #0,
4849 // then load the whole vector back out.
4850 SDOperand StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
4852 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
4853 int SPFI = StackPtrFI->getIndex();
4855 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
4856 PseudoSourceValue::getFixedStack(), SPFI);
4857 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,
4858 PseudoSourceValue::getFixedStack(), SPFI);
4862 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
4863 /// support the operation, but do support the resultant vector type.
4864 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
4866 // If the only non-undef value is the low element, turn this into a
4867 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
4868 unsigned NumElems = Node->getNumOperands();
4869 bool isOnlyLowElement = true;
4870 SDOperand SplatValue = Node->getOperand(0);
4872 // FIXME: it would be far nicer to change this into map<SDOperand,uint64_t>
4873 // and use a bitmask instead of a list of elements.
4874 std::map<SDOperand, std::vector<unsigned> > Values;
4875 Values[SplatValue].push_back(0);
4876 bool isConstant = true;
4877 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
4878 SplatValue.getOpcode() != ISD::UNDEF)
4881 for (unsigned i = 1; i < NumElems; ++i) {
4882 SDOperand V = Node->getOperand(i);
4883 Values[V].push_back(i);
4884 if (V.getOpcode() != ISD::UNDEF)
4885 isOnlyLowElement = false;
4886 if (SplatValue != V)
4887 SplatValue = SDOperand(0,0);
4889 // If this isn't a constant element or an undef, we can't use a constant
4891 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
4892 V.getOpcode() != ISD::UNDEF)
4896 if (isOnlyLowElement) {
4897 // If the low element is an undef too, then this whole things is an undef.
4898 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
4899 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
4900 // Otherwise, turn this into a scalar_to_vector node.
4901 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4902 Node->getOperand(0));
4905 // If all elements are constants, create a load from the constant pool.
4907 MVT::ValueType VT = Node->getValueType(0);
4909 MVT::getTypeForValueType(Node->getOperand(0).getValueType());
4910 std::vector<Constant*> CV;
4911 for (unsigned i = 0, e = NumElems; i != e; ++i) {
4912 if (ConstantFPSDNode *V =
4913 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
4914 CV.push_back(ConstantFP::get(OpNTy, V->getValueAPF()));
4915 } else if (ConstantSDNode *V =
4916 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
4917 CV.push_back(ConstantInt::get(OpNTy, V->getValue()));
4919 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
4920 CV.push_back(UndefValue::get(OpNTy));
4923 Constant *CP = ConstantVector::get(CV);
4924 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
4925 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4926 PseudoSourceValue::getConstantPool(), 0);
4929 if (SplatValue.Val) { // Splat of one value?
4930 // Build the shuffle constant vector: <0, 0, 0, 0>
4931 MVT::ValueType MaskVT =
4932 MVT::getIntVectorWithNumElements(NumElems);
4933 SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT));
4934 std::vector<SDOperand> ZeroVec(NumElems, Zero);
4935 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4936 &ZeroVec[0], ZeroVec.size());
4938 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4939 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
4940 // Get the splatted value into the low element of a vector register.
4941 SDOperand LowValVec =
4942 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
4944 // Return shuffle(LowValVec, undef, <0,0,0,0>)
4945 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
4946 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
4951 // If there are only two unique elements, we may be able to turn this into a
4953 if (Values.size() == 2) {
4954 // Get the two values in deterministic order.
4955 SDOperand Val1 = Node->getOperand(1);
4957 std::map<SDOperand, std::vector<unsigned> >::iterator MI = Values.begin();
4958 if (MI->first != Val1)
4961 Val2 = (++MI)->first;
4963 // If Val1 is an undef, make sure end ends up as Val2, to ensure that our
4964 // vector shuffle has the undef vector on the RHS.
4965 if (Val1.getOpcode() == ISD::UNDEF)
4966 std::swap(Val1, Val2);
4968 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
4969 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
4970 MVT::ValueType MaskEltVT = MVT::getVectorElementType(MaskVT);
4971 std::vector<SDOperand> MaskVec(NumElems);
4973 // Set elements of the shuffle mask for Val1.
4974 std::vector<unsigned> &Val1Elts = Values[Val1];
4975 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i)
4976 MaskVec[Val1Elts[i]] = DAG.getConstant(0, MaskEltVT);
4978 // Set elements of the shuffle mask for Val2.
4979 std::vector<unsigned> &Val2Elts = Values[Val2];
4980 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i)
4981 if (Val2.getOpcode() != ISD::UNDEF)
4982 MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT);
4984 MaskVec[Val2Elts[i]] = DAG.getNode(ISD::UNDEF, MaskEltVT);
4986 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4987 &MaskVec[0], MaskVec.size());
4989 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it.
4990 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
4991 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
4992 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val1);
4993 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val2);
4994 SDOperand Ops[] = { Val1, Val2, ShuffleMask };
4996 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
4997 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops, 3);
5001 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
5002 // aligned object on the stack, store each element into it, then load
5003 // the result as a vector.
5004 MVT::ValueType VT = Node->getValueType(0);
5005 // Create the stack frame object.
5006 SDOperand FIPtr = DAG.CreateStackTemporary(VT);
5008 // Emit a store of each element to the stack slot.
5009 SmallVector<SDOperand, 8> Stores;
5010 unsigned TypeByteSize =
5011 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
5012 // Store (in the right endianness) the elements to memory.
5013 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5014 // Ignore undef elements.
5015 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
5017 unsigned Offset = TypeByteSize*i;
5019 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
5020 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
5022 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
5026 SDOperand StoreChain;
5027 if (!Stores.empty()) // Not all undef elements?
5028 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
5029 &Stores[0], Stores.size());
5031 StoreChain = DAG.getEntryNode();
5033 // Result is a load from the stack slot.
5034 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
5037 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
5038 SDOperand Op, SDOperand Amt,
5039 SDOperand &Lo, SDOperand &Hi) {
5040 // Expand the subcomponents.
5041 SDOperand LHSL, LHSH;
5042 ExpandOp(Op, LHSL, LHSH);
5044 SDOperand Ops[] = { LHSL, LHSH, Amt };
5045 MVT::ValueType VT = LHSL.getValueType();
5046 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
5047 Hi = Lo.getValue(1);
5051 /// ExpandShift - Try to find a clever way to expand this shift operation out to
5052 /// smaller elements. If we can't find a way that is more efficient than a
5053 /// libcall on this target, return false. Otherwise, return true with the
5054 /// low-parts expanded into Lo and Hi.
5055 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
5056 SDOperand &Lo, SDOperand &Hi) {
5057 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
5058 "This is not a shift!");
5060 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
5061 SDOperand ShAmt = LegalizeOp(Amt);
5062 MVT::ValueType ShTy = ShAmt.getValueType();
5063 unsigned ShBits = MVT::getSizeInBits(ShTy);
5064 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
5065 unsigned NVTBits = MVT::getSizeInBits(NVT);
5067 // Handle the case when Amt is an immediate.
5068 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
5069 unsigned Cst = CN->getValue();
5070 // Expand the incoming operand to be shifted, so that we have its parts
5072 ExpandOp(Op, InL, InH);
5076 Lo = DAG.getConstant(0, NVT);
5077 Hi = DAG.getConstant(0, NVT);
5078 } else if (Cst > NVTBits) {
5079 Lo = DAG.getConstant(0, NVT);
5080 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
5081 } else if (Cst == NVTBits) {
5082 Lo = DAG.getConstant(0, NVT);
5085 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
5086 Hi = DAG.getNode(ISD::OR, NVT,
5087 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
5088 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
5093 Lo = DAG.getConstant(0, NVT);
5094 Hi = DAG.getConstant(0, NVT);
5095 } else if (Cst > NVTBits) {
5096 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
5097 Hi = DAG.getConstant(0, NVT);
5098 } else if (Cst == NVTBits) {
5100 Hi = DAG.getConstant(0, NVT);
5102 Lo = DAG.getNode(ISD::OR, NVT,
5103 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5104 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5105 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
5110 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
5111 DAG.getConstant(NVTBits-1, ShTy));
5112 } else if (Cst > NVTBits) {
5113 Lo = DAG.getNode(ISD::SRA, NVT, InH,
5114 DAG.getConstant(Cst-NVTBits, ShTy));
5115 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5116 DAG.getConstant(NVTBits-1, ShTy));
5117 } else if (Cst == NVTBits) {
5119 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5120 DAG.getConstant(NVTBits-1, ShTy));
5122 Lo = DAG.getNode(ISD::OR, NVT,
5123 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5124 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5125 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
5131 // Okay, the shift amount isn't constant. However, if we can tell that it is
5132 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
5133 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
5134 APInt KnownZero, KnownOne;
5135 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
5137 // If we know that if any of the high bits of the shift amount are one, then
5138 // we can do this as a couple of simple shifts.
5139 if (KnownOne.intersects(Mask)) {
5140 // Mask out the high bit, which we know is set.
5141 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
5142 DAG.getConstant(~Mask, Amt.getValueType()));
5144 // Expand the incoming operand to be shifted, so that we have its parts
5146 ExpandOp(Op, InL, InH);
5149 Lo = DAG.getConstant(0, NVT); // Low part is zero.
5150 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
5153 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
5154 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
5157 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
5158 DAG.getConstant(NVTBits-1, Amt.getValueType()));
5159 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
5164 // If we know that the high bits of the shift amount are all zero, then we can
5165 // do this as a couple of simple shifts.
5166 if ((KnownZero & Mask) == Mask) {
5168 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
5169 DAG.getConstant(NVTBits, Amt.getValueType()),
5172 // Expand the incoming operand to be shifted, so that we have its parts
5174 ExpandOp(Op, InL, InH);
5177 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
5178 Hi = DAG.getNode(ISD::OR, NVT,
5179 DAG.getNode(ISD::SHL, NVT, InH, Amt),
5180 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
5183 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
5184 Lo = DAG.getNode(ISD::OR, NVT,
5185 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5186 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5189 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
5190 Lo = DAG.getNode(ISD::OR, NVT,
5191 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5192 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5201 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
5202 // does not fit into a register, return the lo part and set the hi part to the
5203 // by-reg argument. If it does fit into a single register, return the result
5204 // and leave the Hi part unset.
5205 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
5206 bool isSigned, SDOperand &Hi) {
5207 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
5208 // The input chain to this libcall is the entry node of the function.
5209 // Legalizing the call will automatically add the previous call to the
5211 SDOperand InChain = DAG.getEntryNode();
5213 TargetLowering::ArgListTy Args;
5214 TargetLowering::ArgListEntry Entry;
5215 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5216 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
5217 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
5218 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
5219 Entry.isSExt = isSigned;
5220 Entry.isZExt = !isSigned;
5221 Args.push_back(Entry);
5223 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
5225 // Splice the libcall in wherever FindInputOutputChains tells us to.
5226 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
5227 std::pair<SDOperand,SDOperand> CallInfo =
5228 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, CallingConv::C,
5229 false, Callee, Args, DAG);
5231 // Legalize the call sequence, starting with the chain. This will advance
5232 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
5233 // was added by LowerCallTo (guaranteeing proper serialization of calls).
5234 LegalizeOp(CallInfo.second);
5236 switch (getTypeAction(CallInfo.first.getValueType())) {
5237 default: assert(0 && "Unknown thing");
5239 Result = CallInfo.first;
5242 ExpandOp(CallInfo.first, Result, Hi);
5249 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
5251 SDOperand SelectionDAGLegalize::
5252 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
5253 MVT::ValueType SourceVT = Source.getValueType();
5254 bool ExpandSource = getTypeAction(SourceVT) == Expand;
5256 // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc.
5257 if (!isSigned && SourceVT != MVT::i32) {
5258 // The integer value loaded will be incorrectly if the 'sign bit' of the
5259 // incoming integer is set. To handle this, we dynamically test to see if
5260 // it is set, and, if so, add a fudge factor.
5264 ExpandOp(Source, Lo, Hi);
5265 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi);
5267 // The comparison for the sign bit will use the entire operand.
5271 // If this is unsigned, and not supported, first perform the conversion to
5272 // signed, then adjust the result if the sign bit is set.
5273 SDOperand SignedConv = ExpandIntToFP(true, DestTy, Source);
5275 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
5276 DAG.getConstant(0, Hi.getValueType()),
5278 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5279 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5280 SignSet, Four, Zero);
5281 uint64_t FF = 0x5f800000ULL;
5282 if (TLI.isLittleEndian()) FF <<= 32;
5283 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5285 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5286 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5287 SDOperand FudgeInReg;
5288 if (DestTy == MVT::f32)
5289 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5290 PseudoSourceValue::getConstantPool(), 0);
5291 else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32))
5292 // FIXME: Avoid the extend by construction the right constantpool?
5293 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
5295 PseudoSourceValue::getConstantPool(), 0,
5298 assert(0 && "Unexpected conversion");
5300 MVT::ValueType SCVT = SignedConv.getValueType();
5301 if (SCVT != DestTy) {
5302 // Destination type needs to be expanded as well. The FADD now we are
5303 // constructing will be expanded into a libcall.
5304 if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) {
5305 assert(MVT::getSizeInBits(SCVT) * 2 == MVT::getSizeInBits(DestTy));
5306 SignedConv = DAG.getNode(ISD::BUILD_PAIR, DestTy,
5307 SignedConv, SignedConv.getValue(1));
5309 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
5311 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
5314 // Check to see if the target has a custom way to lower this. If so, use it.
5315 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) {
5316 default: assert(0 && "This action not implemented for this operation!");
5317 case TargetLowering::Legal:
5318 case TargetLowering::Expand:
5319 break; // This case is handled below.
5320 case TargetLowering::Custom: {
5321 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
5324 return LegalizeOp(NV);
5325 break; // The target decided this was legal after all
5329 // Expand the source, then glue it back together for the call. We must expand
5330 // the source in case it is shared (this pass of legalize must traverse it).
5332 SDOperand SrcLo, SrcHi;
5333 ExpandOp(Source, SrcLo, SrcHi);
5334 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, SrcLo, SrcHi);
5338 if (SourceVT == MVT::i32) {
5339 if (DestTy == MVT::f32)
5340 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32;
5342 assert(DestTy == MVT::f64 && "Unknown fp value type!");
5343 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64;
5345 } else if (SourceVT == MVT::i64) {
5346 if (DestTy == MVT::f32)
5347 LC = RTLIB::SINTTOFP_I64_F32;
5348 else if (DestTy == MVT::f64)
5349 LC = RTLIB::SINTTOFP_I64_F64;
5350 else if (DestTy == MVT::f80)
5351 LC = RTLIB::SINTTOFP_I64_F80;
5353 assert(DestTy == MVT::ppcf128 && "Unknown fp value type!");
5354 LC = RTLIB::SINTTOFP_I64_PPCF128;
5356 } else if (SourceVT == MVT::i128) {
5357 if (DestTy == MVT::f32)
5358 LC = RTLIB::SINTTOFP_I128_F32;
5359 else if (DestTy == MVT::f64)
5360 LC = RTLIB::SINTTOFP_I128_F64;
5361 else if (DestTy == MVT::f80)
5362 LC = RTLIB::SINTTOFP_I128_F80;
5364 assert(DestTy == MVT::ppcf128 && "Unknown fp value type!");
5365 LC = RTLIB::SINTTOFP_I128_PPCF128;
5368 assert(0 && "Unknown int value type");
5371 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!");
5372 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
5374 SDOperand Result = ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned,
5376 if (Result.getValueType() != DestTy && HiPart.Val)
5377 Result = DAG.getNode(ISD::BUILD_PAIR, DestTy, Result, HiPart);
5381 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
5382 /// INT_TO_FP operation of the specified operand when the target requests that
5383 /// we expand it. At this point, we know that the result and operand types are
5384 /// legal for the target.
5385 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
5387 MVT::ValueType DestVT) {
5388 if (Op0.getValueType() == MVT::i32) {
5389 // simple 32-bit [signed|unsigned] integer to float/double expansion
5391 // Get the stack frame index of a 8 byte buffer.
5392 SDOperand StackSlot = DAG.CreateStackTemporary(MVT::f64);
5394 // word offset constant for Hi/Lo address computation
5395 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
5396 // set up Hi and Lo (into buffer) address based on endian
5397 SDOperand Hi = StackSlot;
5398 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
5399 if (TLI.isLittleEndian())
5402 // if signed map to unsigned space
5403 SDOperand Op0Mapped;
5405 // constant used to invert sign bit (signed to unsigned mapping)
5406 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
5407 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
5411 // store the lo of the constructed double - based on integer input
5412 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(),
5413 Op0Mapped, Lo, NULL, 0);
5414 // initial hi portion of constructed double
5415 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
5416 // store the hi of the constructed double - biased exponent
5417 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
5418 // load the constructed double
5419 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
5420 // FP constant to bias correct the final result
5421 SDOperand Bias = DAG.getConstantFP(isSigned ?
5422 BitsToDouble(0x4330000080000000ULL)
5423 : BitsToDouble(0x4330000000000000ULL),
5425 // subtract the bias
5426 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
5429 // handle final rounding
5430 if (DestVT == MVT::f64) {
5433 } else if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(MVT::f64)) {
5434 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub,
5435 DAG.getIntPtrConstant(0));
5436 } else if (MVT::getSizeInBits(DestVT) > MVT::getSizeInBits(MVT::f64)) {
5437 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
5441 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
5442 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
5444 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Op0), Op0,
5445 DAG.getConstant(0, Op0.getValueType()),
5447 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5448 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5449 SignSet, Four, Zero);
5451 // If the sign bit of the integer is set, the large number will be treated
5452 // as a negative number. To counteract this, the dynamic code adds an
5453 // offset depending on the data type.
5455 switch (Op0.getValueType()) {
5456 default: assert(0 && "Unsupported integer type!");
5457 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
5458 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
5459 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
5460 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
5462 if (TLI.isLittleEndian()) FF <<= 32;
5463 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5465 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5466 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5467 SDOperand FudgeInReg;
5468 if (DestVT == MVT::f32)
5469 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5470 PseudoSourceValue::getConstantPool(), 0);
5473 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT,
5474 DAG.getEntryNode(), CPIdx,
5475 PseudoSourceValue::getConstantPool(), 0,
5479 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
5482 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
5483 /// *INT_TO_FP operation of the specified operand when the target requests that
5484 /// we promote it. At this point, we know that the result and operand types are
5485 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
5486 /// operation that takes a larger input.
5487 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
5488 MVT::ValueType DestVT,
5490 // First step, figure out the appropriate *INT_TO_FP operation to use.
5491 MVT::ValueType NewInTy = LegalOp.getValueType();
5493 unsigned OpToUse = 0;
5495 // Scan for the appropriate larger type to use.
5497 NewInTy = (MVT::ValueType)(NewInTy+1);
5498 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
5500 // If the target supports SINT_TO_FP of this type, use it.
5501 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
5503 case TargetLowering::Legal:
5504 if (!TLI.isTypeLegal(NewInTy))
5505 break; // Can't use this datatype.
5507 case TargetLowering::Custom:
5508 OpToUse = ISD::SINT_TO_FP;
5512 if (isSigned) continue;
5514 // If the target supports UINT_TO_FP of this type, use it.
5515 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
5517 case TargetLowering::Legal:
5518 if (!TLI.isTypeLegal(NewInTy))
5519 break; // Can't use this datatype.
5521 case TargetLowering::Custom:
5522 OpToUse = ISD::UINT_TO_FP;
5527 // Otherwise, try a larger type.
5530 // Okay, we found the operation and type to use. Zero extend our input to the
5531 // desired type then run the operation on it.
5532 return DAG.getNode(OpToUse, DestVT,
5533 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
5537 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
5538 /// FP_TO_*INT operation of the specified operand when the target requests that
5539 /// we promote it. At this point, we know that the result and operand types are
5540 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
5541 /// operation that returns a larger result.
5542 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
5543 MVT::ValueType DestVT,
5545 // First step, figure out the appropriate FP_TO*INT operation to use.
5546 MVT::ValueType NewOutTy = DestVT;
5548 unsigned OpToUse = 0;
5550 // Scan for the appropriate larger type to use.
5552 NewOutTy = (MVT::ValueType)(NewOutTy+1);
5553 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
5555 // If the target supports FP_TO_SINT returning this type, use it.
5556 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
5558 case TargetLowering::Legal:
5559 if (!TLI.isTypeLegal(NewOutTy))
5560 break; // Can't use this datatype.
5562 case TargetLowering::Custom:
5563 OpToUse = ISD::FP_TO_SINT;
5568 // If the target supports FP_TO_UINT of this type, use it.
5569 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
5571 case TargetLowering::Legal:
5572 if (!TLI.isTypeLegal(NewOutTy))
5573 break; // Can't use this datatype.
5575 case TargetLowering::Custom:
5576 OpToUse = ISD::FP_TO_UINT;
5581 // Otherwise, try a larger type.
5585 // Okay, we found the operation and type to use.
5586 SDOperand Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp);
5588 // If the operation produces an invalid type, it must be custom lowered. Use
5589 // the target lowering hooks to expand it. Just keep the low part of the
5590 // expanded operation, we know that we're truncating anyway.
5591 if (getTypeAction(NewOutTy) == Expand) {
5592 Operation = SDOperand(TLI.ExpandOperationResult(Operation.Val, DAG), 0);
5593 assert(Operation.Val && "Didn't return anything");
5596 // Truncate the result of the extended FP_TO_*INT operation to the desired
5598 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation);
5601 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
5603 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
5604 MVT::ValueType VT = Op.getValueType();
5605 MVT::ValueType SHVT = TLI.getShiftAmountTy();
5606 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
5608 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
5610 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5611 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5612 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
5614 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5615 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5616 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5617 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5618 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
5619 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
5620 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5621 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5622 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5624 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
5625 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
5626 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5627 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5628 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5629 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5630 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
5631 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
5632 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
5633 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
5634 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
5635 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
5636 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
5637 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
5638 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
5639 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
5640 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5641 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5642 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
5643 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5644 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
5648 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
5650 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
5652 default: assert(0 && "Cannot expand this yet!");
5654 static const uint64_t mask[6] = {
5655 0x5555555555555555ULL, 0x3333333333333333ULL,
5656 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
5657 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
5659 MVT::ValueType VT = Op.getValueType();
5660 MVT::ValueType ShVT = TLI.getShiftAmountTy();
5661 unsigned len = MVT::getSizeInBits(VT);
5662 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5663 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
5664 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
5665 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5666 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
5667 DAG.getNode(ISD::AND, VT,
5668 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
5673 // for now, we do this:
5674 // x = x | (x >> 1);
5675 // x = x | (x >> 2);
5677 // x = x | (x >>16);
5678 // x = x | (x >>32); // for 64-bit input
5679 // return popcount(~x);
5681 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
5682 MVT::ValueType VT = Op.getValueType();
5683 MVT::ValueType ShVT = TLI.getShiftAmountTy();
5684 unsigned len = MVT::getSizeInBits(VT);
5685 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5686 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5687 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
5689 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
5690 return DAG.getNode(ISD::CTPOP, VT, Op);
5693 // for now, we use: { return popcount(~x & (x - 1)); }
5694 // unless the target has ctlz but not ctpop, in which case we use:
5695 // { return 32 - nlz(~x & (x-1)); }
5696 // see also http://www.hackersdelight.org/HDcode/ntz.cc
5697 MVT::ValueType VT = Op.getValueType();
5698 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
5699 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
5700 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
5701 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
5702 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
5703 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
5704 TLI.isOperationLegal(ISD::CTLZ, VT))
5705 return DAG.getNode(ISD::SUB, VT,
5706 DAG.getConstant(MVT::getSizeInBits(VT), VT),
5707 DAG.getNode(ISD::CTLZ, VT, Tmp3));
5708 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
5713 /// ExpandOp - Expand the specified SDOperand into its two component pieces
5714 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
5715 /// LegalizeNodes map is filled in for any results that are not expanded, the
5716 /// ExpandedNodes map is filled in for any results that are expanded, and the
5717 /// Lo/Hi values are returned.
5718 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
5719 MVT::ValueType VT = Op.getValueType();
5720 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
5721 SDNode *Node = Op.Val;
5722 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
5723 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) ||
5724 MVT::isVector(VT)) &&
5725 "Cannot expand to FP value or to larger int value!");
5727 // See if we already expanded it.
5728 DenseMap<SDOperandImpl, std::pair<SDOperand, SDOperand> >::iterator I
5729 = ExpandedNodes.find(Op);
5730 if (I != ExpandedNodes.end()) {
5731 Lo = I->second.first;
5732 Hi = I->second.second;
5736 switch (Node->getOpcode()) {
5737 case ISD::CopyFromReg:
5738 assert(0 && "CopyFromReg must be legal!");
5739 case ISD::FP_ROUND_INREG:
5740 if (VT == MVT::ppcf128 &&
5741 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
5742 TargetLowering::Custom) {
5743 SDOperand SrcLo, SrcHi, Src;
5744 ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
5745 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi);
5746 SDOperand Result = TLI.LowerOperation(
5747 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG);
5748 assert(Result.Val->getOpcode() == ISD::BUILD_PAIR);
5749 Lo = Result.Val->getOperand(0);
5750 Hi = Result.Val->getOperand(1);
5756 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
5758 assert(0 && "Do not know how to expand this operator!");
5760 case ISD::EXTRACT_ELEMENT:
5761 ExpandOp(Node->getOperand(0), Lo, Hi);
5762 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
5763 return ExpandOp(Hi, Lo, Hi);
5764 return ExpandOp(Lo, Lo, Hi);
5765 case ISD::EXTRACT_VECTOR_ELT:
5766 assert(VT==MVT::i64 && "Do not know how to expand this operator!");
5767 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types.
5768 Lo = ExpandEXTRACT_VECTOR_ELT(Op);
5769 return ExpandOp(Lo, Lo, Hi);
5771 NVT = TLI.getTypeToExpandTo(VT);
5772 Lo = DAG.getNode(ISD::UNDEF, NVT);
5773 Hi = DAG.getNode(ISD::UNDEF, NVT);
5775 case ISD::Constant: {
5776 unsigned NVTBits = MVT::getSizeInBits(NVT);
5777 const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue();
5778 Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT);
5779 Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT);
5782 case ISD::ConstantFP: {
5783 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
5784 if (CFP->getValueType(0) == MVT::ppcf128) {
5785 APInt api = CFP->getValueAPF().convertToAPInt();
5786 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
5788 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
5792 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
5793 if (getTypeAction(Lo.getValueType()) == Expand)
5794 ExpandOp(Lo, Lo, Hi);
5797 case ISD::BUILD_PAIR:
5798 // Return the operands.
5799 Lo = Node->getOperand(0);
5800 Hi = Node->getOperand(1);
5803 case ISD::MERGE_VALUES:
5804 if (Node->getNumValues() == 1) {
5805 ExpandOp(Op.getOperand(0), Lo, Hi);
5808 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y)
5809 assert(Op.ResNo == 0 && Node->getNumValues() == 2 &&
5810 Op.getValue(1).getValueType() == MVT::Other &&
5811 "unhandled MERGE_VALUES");
5812 ExpandOp(Op.getOperand(0), Lo, Hi);
5813 // Remember that we legalized the chain.
5814 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1)));
5817 case ISD::SIGN_EXTEND_INREG:
5818 ExpandOp(Node->getOperand(0), Lo, Hi);
5819 // sext_inreg the low part if needed.
5820 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
5822 // The high part gets the sign extension from the lo-part. This handles
5823 // things like sextinreg V:i64 from i8.
5824 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5825 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
5826 TLI.getShiftAmountTy()));
5830 ExpandOp(Node->getOperand(0), Lo, Hi);
5831 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
5832 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
5838 ExpandOp(Node->getOperand(0), Lo, Hi);
5839 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
5840 DAG.getNode(ISD::CTPOP, NVT, Lo),
5841 DAG.getNode(ISD::CTPOP, NVT, Hi));
5842 Hi = DAG.getConstant(0, NVT);
5846 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
5847 ExpandOp(Node->getOperand(0), Lo, Hi);
5848 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5849 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
5850 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(HLZ), HLZ, BitsC,
5852 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
5853 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
5855 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
5856 Hi = DAG.getConstant(0, NVT);
5861 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
5862 ExpandOp(Node->getOperand(0), Lo, Hi);
5863 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5864 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
5865 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(LTZ), LTZ, BitsC,
5867 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
5868 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
5870 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
5871 Hi = DAG.getConstant(0, NVT);
5876 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
5877 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
5878 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
5879 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
5881 // Remember that we legalized the chain.
5882 Hi = LegalizeOp(Hi);
5883 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
5884 if (TLI.isBigEndian())
5890 LoadSDNode *LD = cast<LoadSDNode>(Node);
5891 SDOperand Ch = LD->getChain(); // Legalize the chain.
5892 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer.
5893 ISD::LoadExtType ExtType = LD->getExtensionType();
5894 int SVOffset = LD->getSrcValueOffset();
5895 unsigned Alignment = LD->getAlignment();
5896 bool isVolatile = LD->isVolatile();
5898 if (ExtType == ISD::NON_EXTLOAD) {
5899 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5900 isVolatile, Alignment);
5901 if (VT == MVT::f32 || VT == MVT::f64) {
5902 // f32->i32 or f64->i64 one to one expansion.
5903 // Remember that we legalized the chain.
5904 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5905 // Recursively expand the new load.
5906 if (getTypeAction(NVT) == Expand)
5907 ExpandOp(Lo, Lo, Hi);
5911 // Increment the pointer to the other half.
5912 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
5913 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
5914 DAG.getIntPtrConstant(IncrementSize));
5915 SVOffset += IncrementSize;
5916 Alignment = MinAlign(Alignment, IncrementSize);
5917 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5918 isVolatile, Alignment);
5920 // Build a factor node to remember that this load is independent of the
5922 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
5925 // Remember that we legalized the chain.
5926 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
5927 if (TLI.isBigEndian())
5930 MVT::ValueType EVT = LD->getMemoryVT();
5932 if ((VT == MVT::f64 && EVT == MVT::f32) ||
5933 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
5934 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
5935 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(),
5936 SVOffset, isVolatile, Alignment);
5937 // Remember that we legalized the chain.
5938 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1)));
5939 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
5944 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),
5945 SVOffset, isVolatile, Alignment);
5947 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(),
5948 SVOffset, EVT, isVolatile,
5951 // Remember that we legalized the chain.
5952 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5954 if (ExtType == ISD::SEXTLOAD) {
5955 // The high part is obtained by SRA'ing all but one of the bits of the
5957 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
5958 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5959 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5960 } else if (ExtType == ISD::ZEXTLOAD) {
5961 // The high part is just a zero.
5962 Hi = DAG.getConstant(0, NVT);
5963 } else /* if (ExtType == ISD::EXTLOAD) */ {
5964 // The high part is undefined.
5965 Hi = DAG.getNode(ISD::UNDEF, NVT);
5972 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
5973 SDOperand LL, LH, RL, RH;
5974 ExpandOp(Node->getOperand(0), LL, LH);
5975 ExpandOp(Node->getOperand(1), RL, RH);
5976 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
5977 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
5981 SDOperand LL, LH, RL, RH;
5982 ExpandOp(Node->getOperand(1), LL, LH);
5983 ExpandOp(Node->getOperand(2), RL, RH);
5984 if (getTypeAction(NVT) == Expand)
5985 NVT = TLI.getTypeToExpandTo(NVT);
5986 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
5988 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
5991 case ISD::SELECT_CC: {
5992 SDOperand TL, TH, FL, FH;
5993 ExpandOp(Node->getOperand(2), TL, TH);
5994 ExpandOp(Node->getOperand(3), FL, FH);
5995 if (getTypeAction(NVT) == Expand)
5996 NVT = TLI.getTypeToExpandTo(NVT);
5997 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
5998 Node->getOperand(1), TL, FL, Node->getOperand(4));
6000 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
6001 Node->getOperand(1), TH, FH, Node->getOperand(4));
6004 case ISD::ANY_EXTEND:
6005 // The low part is any extension of the input (which degenerates to a copy).
6006 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
6007 // The high part is undefined.
6008 Hi = DAG.getNode(ISD::UNDEF, NVT);
6010 case ISD::SIGN_EXTEND: {
6011 // The low part is just a sign extension of the input (which degenerates to
6013 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
6015 // The high part is obtained by SRA'ing all but one of the bits of the lo
6017 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
6018 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6019 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6022 case ISD::ZERO_EXTEND:
6023 // The low part is just a zero extension of the input (which degenerates to
6025 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
6027 // The high part is just a zero.
6028 Hi = DAG.getConstant(0, NVT);
6031 case ISD::TRUNCATE: {
6032 // The input value must be larger than this value. Expand *it*.
6034 ExpandOp(Node->getOperand(0), NewLo, Hi);
6036 // The low part is now either the right size, or it is closer. If not the
6037 // right size, make an illegal truncate so we recursively expand it.
6038 if (NewLo.getValueType() != Node->getValueType(0))
6039 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
6040 ExpandOp(NewLo, Lo, Hi);
6044 case ISD::BIT_CONVERT: {
6046 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
6047 // If the target wants to, allow it to lower this itself.
6048 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6049 case Expand: assert(0 && "cannot expand FP!");
6050 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
6051 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
6053 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
6056 // f32 / f64 must be expanded to i32 / i64.
6057 if (VT == MVT::f32 || VT == MVT::f64) {
6058 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6059 if (getTypeAction(NVT) == Expand)
6060 ExpandOp(Lo, Lo, Hi);
6064 // If source operand will be expanded to the same type as VT, i.e.
6065 // i64 <- f64, i32 <- f32, expand the source operand instead.
6066 MVT::ValueType VT0 = Node->getOperand(0).getValueType();
6067 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
6068 ExpandOp(Node->getOperand(0), Lo, Hi);
6072 // Turn this into a load/store pair by default.
6074 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT);
6076 ExpandOp(Tmp, Lo, Hi);
6080 case ISD::READCYCLECOUNTER: {
6081 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
6082 TargetLowering::Custom &&
6083 "Must custom expand ReadCycleCounter");
6084 SDOperand Tmp = TLI.LowerOperation(Op, DAG);
6085 assert(Tmp.Val && "Node must be custom expanded!");
6086 ExpandOp(Tmp.getValue(0), Lo, Hi);
6087 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
6088 LegalizeOp(Tmp.getValue(1)));
6092 case ISD::ATOMIC_LCS: {
6093 SDOperand Tmp = TLI.LowerOperation(Op, DAG);
6094 assert(Tmp.Val && "Node must be custom expanded!");
6095 ExpandOp(Tmp.getValue(0), Lo, Hi);
6096 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
6097 LegalizeOp(Tmp.getValue(1)));
6103 // These operators cannot be expanded directly, emit them as calls to
6104 // library functions.
6105 case ISD::FP_TO_SINT: {
6106 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
6108 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6109 case Expand: assert(0 && "cannot expand FP!");
6110 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6111 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6114 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
6116 // Now that the custom expander is done, expand the result, which is still
6119 ExpandOp(Op, Lo, Hi);
6124 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6125 if (VT == MVT::i64) {
6126 if (Node->getOperand(0).getValueType() == MVT::f32)
6127 LC = RTLIB::FPTOSINT_F32_I64;
6128 else if (Node->getOperand(0).getValueType() == MVT::f64)
6129 LC = RTLIB::FPTOSINT_F64_I64;
6130 else if (Node->getOperand(0).getValueType() == MVT::f80)
6131 LC = RTLIB::FPTOSINT_F80_I64;
6132 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
6133 LC = RTLIB::FPTOSINT_PPCF128_I64;
6134 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
6135 false/*sign irrelevant*/, Hi);
6136 } else if (VT == MVT::i128) {
6137 if (Node->getOperand(0).getValueType() == MVT::f32)
6138 LC = RTLIB::FPTOSINT_F32_I128;
6139 else if (Node->getOperand(0).getValueType() == MVT::f64)
6140 LC = RTLIB::FPTOSINT_F64_I128;
6141 else if (Node->getOperand(0).getValueType() == MVT::f80)
6142 LC = RTLIB::FPTOSINT_F80_I128;
6143 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
6144 LC = RTLIB::FPTOSINT_PPCF128_I128;
6145 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
6146 false/*sign irrelevant*/, Hi);
6148 assert(0 && "Unexpected uint-to-fp conversion!");
6153 case ISD::FP_TO_UINT: {
6154 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
6156 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6157 case Expand: assert(0 && "cannot expand FP!");
6158 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6159 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6162 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
6164 // Now that the custom expander is done, expand the result.
6166 ExpandOp(Op, Lo, Hi);
6171 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6172 if (VT == MVT::i64) {
6173 if (Node->getOperand(0).getValueType() == MVT::f32)
6174 LC = RTLIB::FPTOUINT_F32_I64;
6175 else if (Node->getOperand(0).getValueType() == MVT::f64)
6176 LC = RTLIB::FPTOUINT_F64_I64;
6177 else if (Node->getOperand(0).getValueType() == MVT::f80)
6178 LC = RTLIB::FPTOUINT_F80_I64;
6179 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
6180 LC = RTLIB::FPTOUINT_PPCF128_I64;
6181 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
6182 false/*sign irrelevant*/, Hi);
6183 } else if (VT == MVT::i128) {
6184 if (Node->getOperand(0).getValueType() == MVT::f32)
6185 LC = RTLIB::FPTOUINT_F32_I128;
6186 else if (Node->getOperand(0).getValueType() == MVT::f64)
6187 LC = RTLIB::FPTOUINT_F64_I128;
6188 else if (Node->getOperand(0).getValueType() == MVT::f80)
6189 LC = RTLIB::FPTOUINT_F80_I128;
6190 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
6191 LC = RTLIB::FPTOUINT_PPCF128_I128;
6192 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
6193 false/*sign irrelevant*/, Hi);
6195 assert(0 && "Unexpected uint-to-fp conversion!");
6201 // If the target wants custom lowering, do so.
6202 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6203 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
6204 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
6205 Op = TLI.LowerOperation(Op, DAG);
6207 // Now that the custom expander is done, expand the result, which is
6209 ExpandOp(Op, Lo, Hi);
6214 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
6215 // this X << 1 as X+X.
6216 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
6217 if (ShAmt->getAPIntValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
6218 TLI.isOperationLegal(ISD::ADDE, NVT)) {
6219 SDOperand LoOps[2], HiOps[3];
6220 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
6221 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
6222 LoOps[1] = LoOps[0];
6223 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6225 HiOps[1] = HiOps[0];
6226 HiOps[2] = Lo.getValue(1);
6227 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6232 // If we can emit an efficient shift operation, do so now.
6233 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6236 // If this target supports SHL_PARTS, use it.
6237 TargetLowering::LegalizeAction Action =
6238 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
6239 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6240 Action == TargetLowering::Custom) {
6241 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6245 // Otherwise, emit a libcall.
6246 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SHL_I64), Node,
6247 false/*left shift=unsigned*/, Hi);
6252 // If the target wants custom lowering, do so.
6253 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6254 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
6255 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
6256 Op = TLI.LowerOperation(Op, DAG);
6258 // Now that the custom expander is done, expand the result, which is
6260 ExpandOp(Op, Lo, Hi);
6265 // If we can emit an efficient shift operation, do so now.
6266 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
6269 // If this target supports SRA_PARTS, use it.
6270 TargetLowering::LegalizeAction Action =
6271 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
6272 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6273 Action == TargetLowering::Custom) {
6274 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6278 // Otherwise, emit a libcall.
6279 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRA_I64), Node,
6280 true/*ashr is signed*/, Hi);
6285 // If the target wants custom lowering, do so.
6286 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6287 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
6288 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
6289 Op = TLI.LowerOperation(Op, DAG);
6291 // Now that the custom expander is done, expand the result, which is
6293 ExpandOp(Op, Lo, Hi);
6298 // If we can emit an efficient shift operation, do so now.
6299 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6302 // If this target supports SRL_PARTS, use it.
6303 TargetLowering::LegalizeAction Action =
6304 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
6305 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6306 Action == TargetLowering::Custom) {
6307 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6311 // Otherwise, emit a libcall.
6312 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), Node,
6313 false/*lshr is unsigned*/, Hi);
6319 // If the target wants to custom expand this, let them.
6320 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
6321 TargetLowering::Custom) {
6322 Op = TLI.LowerOperation(Op, DAG);
6324 ExpandOp(Op, Lo, Hi);
6329 // Expand the subcomponents.
6330 SDOperand LHSL, LHSH, RHSL, RHSH;
6331 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6332 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6333 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6334 SDOperand LoOps[2], HiOps[3];
6339 if (Node->getOpcode() == ISD::ADD) {
6340 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6341 HiOps[2] = Lo.getValue(1);
6342 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6344 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6345 HiOps[2] = Lo.getValue(1);
6346 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6353 // Expand the subcomponents.
6354 SDOperand LHSL, LHSH, RHSL, RHSH;
6355 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6356 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6357 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6358 SDOperand LoOps[2] = { LHSL, RHSL };
6359 SDOperand HiOps[3] = { LHSH, RHSH };
6361 if (Node->getOpcode() == ISD::ADDC) {
6362 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6363 HiOps[2] = Lo.getValue(1);
6364 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6366 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6367 HiOps[2] = Lo.getValue(1);
6368 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6370 // Remember that we legalized the flag.
6371 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6376 // Expand the subcomponents.
6377 SDOperand LHSL, LHSH, RHSL, RHSH;
6378 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6379 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6380 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6381 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
6382 SDOperand HiOps[3] = { LHSH, RHSH };
6384 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
6385 HiOps[2] = Lo.getValue(1);
6386 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
6388 // Remember that we legalized the flag.
6389 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6393 // If the target wants to custom expand this, let them.
6394 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
6395 SDOperand New = TLI.LowerOperation(Op, DAG);
6397 ExpandOp(New, Lo, Hi);
6402 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
6403 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
6404 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
6405 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
6406 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
6407 SDOperand LL, LH, RL, RH;
6408 ExpandOp(Node->getOperand(0), LL, LH);
6409 ExpandOp(Node->getOperand(1), RL, RH);
6410 unsigned OuterBitSize = Op.getValueSizeInBits();
6411 unsigned InnerBitSize = RH.getValueSizeInBits();
6412 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
6413 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
6414 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
6415 if (DAG.MaskedValueIsZero(Node->getOperand(0), HighMask) &&
6416 DAG.MaskedValueIsZero(Node->getOperand(1), HighMask)) {
6417 // The inputs are both zero-extended.
6419 // We can emit a umul_lohi.
6420 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6421 Hi = SDOperand(Lo.Val, 1);
6425 // We can emit a mulhu+mul.
6426 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6427 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6431 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
6432 // The input values are both sign-extended.
6434 // We can emit a smul_lohi.
6435 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6436 Hi = SDOperand(Lo.Val, 1);
6440 // We can emit a mulhs+mul.
6441 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6442 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
6447 // Lo,Hi = umul LHS, RHS.
6448 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
6449 DAG.getVTList(NVT, NVT), LL, RL);
6451 Hi = UMulLOHI.getValue(1);
6452 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6453 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6454 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6455 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6459 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6460 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6461 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6462 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6463 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6464 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6469 // If nothing else, we can make a libcall.
6470 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), Node,
6471 false/*sign irrelevant*/, Hi);
6475 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SDIV_I64), Node, true, Hi);
6478 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UDIV_I64), Node, true, Hi);
6481 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SREM_I64), Node, true, Hi);
6484 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UREM_I64), Node, true, Hi);
6488 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::ADD_F32,
6491 RTLIB::ADD_PPCF128)),
6495 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::SUB_F32,
6498 RTLIB::SUB_PPCF128)),
6502 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::MUL_F32,
6505 RTLIB::MUL_PPCF128)),
6509 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::DIV_F32,
6512 RTLIB::DIV_PPCF128)),
6515 case ISD::FP_EXTEND:
6516 if (VT == MVT::ppcf128) {
6517 assert(Node->getOperand(0).getValueType()==MVT::f32 ||
6518 Node->getOperand(0).getValueType()==MVT::f64);
6519 const uint64_t zero = 0;
6520 if (Node->getOperand(0).getValueType()==MVT::f32)
6521 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0));
6523 Hi = Node->getOperand(0);
6524 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6527 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPEXT_F32_F64), Node, true,Hi);
6530 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi);
6533 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::POWI_F32,
6536 RTLIB::POWI_PPCF128)),
6542 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6543 switch(Node->getOpcode()) {
6545 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
6546 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
6549 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
6550 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
6553 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
6554 RTLIB::COS_F80, RTLIB::COS_PPCF128);
6556 default: assert(0 && "Unreachable!");
6558 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false, Hi);
6562 if (VT == MVT::ppcf128) {
6564 ExpandOp(Node->getOperand(0), Lo, Tmp);
6565 Hi = DAG.getNode(ISD::FABS, NVT, Tmp);
6566 // lo = hi==fabs(hi) ? lo : -lo;
6567 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp,
6568 Lo, DAG.getNode(ISD::FNEG, NVT, Lo),
6569 DAG.getCondCode(ISD::SETEQ));
6572 SDOperand Mask = (VT == MVT::f64)
6573 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
6574 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
6575 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6576 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6577 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
6578 if (getTypeAction(NVT) == Expand)
6579 ExpandOp(Lo, Lo, Hi);
6583 if (VT == MVT::ppcf128) {
6584 ExpandOp(Node->getOperand(0), Lo, Hi);
6585 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo);
6586 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi);
6589 SDOperand Mask = (VT == MVT::f64)
6590 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
6591 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
6592 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6593 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6594 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
6595 if (getTypeAction(NVT) == Expand)
6596 ExpandOp(Lo, Lo, Hi);
6599 case ISD::FCOPYSIGN: {
6600 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
6601 if (getTypeAction(NVT) == Expand)
6602 ExpandOp(Lo, Lo, Hi);
6605 case ISD::SINT_TO_FP:
6606 case ISD::UINT_TO_FP: {
6607 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
6608 MVT::ValueType SrcVT = Node->getOperand(0).getValueType();
6610 // Promote the operand if needed. Do this before checking for
6611 // ppcf128 so conversions of i16 and i8 work.
6612 if (getTypeAction(SrcVT) == Promote) {
6613 SDOperand Tmp = PromoteOp(Node->getOperand(0));
6615 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
6616 DAG.getValueType(SrcVT))
6617 : DAG.getZeroExtendInReg(Tmp, SrcVT);
6618 Node = DAG.UpdateNodeOperands(Op, Tmp).Val;
6619 SrcVT = Node->getOperand(0).getValueType();
6622 if (VT == MVT::ppcf128 && SrcVT == MVT::i32) {
6623 static const uint64_t zero = 0;
6625 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6626 Node->getOperand(0)));
6627 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6629 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
6630 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6631 Node->getOperand(0)));
6632 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6633 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6634 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
6635 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6636 DAG.getConstant(0, MVT::i32),
6637 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6639 APFloat(APInt(128, 2, TwoE32)),
6642 DAG.getCondCode(ISD::SETLT)),
6647 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) {
6648 // si64->ppcf128 done by libcall, below
6649 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
6650 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)),
6652 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6653 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
6654 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6655 DAG.getConstant(0, MVT::i64),
6656 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6658 APFloat(APInt(128, 2, TwoE64)),
6661 DAG.getCondCode(ISD::SETLT)),
6666 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
6667 Node->getOperand(0));
6668 if (getTypeAction(Lo.getValueType()) == Expand)
6669 // float to i32 etc. can be 'expanded' to a single node.
6670 ExpandOp(Lo, Lo, Hi);
6675 // Make sure the resultant values have been legalized themselves, unless this
6676 // is a type that requires multi-step expansion.
6677 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
6678 Lo = LegalizeOp(Lo);
6680 // Don't legalize the high part if it is expanded to a single node.
6681 Hi = LegalizeOp(Hi);
6684 // Remember in a map if the values will be reused later.
6685 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi)));
6686 assert(isNew && "Value already expanded?!?");
6689 /// SplitVectorOp - Given an operand of vector type, break it down into
6690 /// two smaller values, still of vector type.
6691 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
6693 assert(MVT::isVector(Op.getValueType()) && "Cannot split non-vector type!");
6694 SDNode *Node = Op.Val;
6695 unsigned NumElements = MVT::getVectorNumElements(Op.getValueType());
6696 assert(NumElements > 1 && "Cannot split a single element vector!");
6698 MVT::ValueType NewEltVT = MVT::getVectorElementType(Op.getValueType());
6700 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
6701 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
6703 MVT::ValueType NewVT_Lo = MVT::getVectorType(NewEltVT, NewNumElts_Lo);
6704 MVT::ValueType NewVT_Hi = MVT::getVectorType(NewEltVT, NewNumElts_Hi);
6706 // See if we already split it.
6707 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
6708 = SplitNodes.find(Op);
6709 if (I != SplitNodes.end()) {
6710 Lo = I->second.first;
6711 Hi = I->second.second;
6715 switch (Node->getOpcode()) {
6720 assert(0 && "Unhandled operation in SplitVectorOp!");
6722 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo);
6723 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi);
6725 case ISD::BUILD_PAIR:
6726 Lo = Node->getOperand(0);
6727 Hi = Node->getOperand(1);
6729 case ISD::INSERT_VECTOR_ELT: {
6730 SplitVectorOp(Node->getOperand(0), Lo, Hi);
6731 unsigned Index = cast<ConstantSDNode>(Node->getOperand(2))->getValue();
6732 SDOperand ScalarOp = Node->getOperand(1);
6733 if (Index < NewNumElts_Lo)
6734 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp,
6735 DAG.getIntPtrConstant(Index));
6737 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp,
6738 DAG.getIntPtrConstant(Index - NewNumElts_Lo));
6741 case ISD::VECTOR_SHUFFLE: {
6742 // Build the low part.
6743 SDOperand Mask = Node->getOperand(2);
6744 SmallVector<SDOperand, 8> Ops;
6745 MVT::ValueType PtrVT = TLI.getPointerTy();
6747 // Insert all of the elements from the input that are needed. We use
6748 // buildvector of extractelement here because the input vectors will have
6749 // to be legalized, so this makes the code simpler.
6750 for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
6751 SDOperand IdxNode = Mask.getOperand(i);
6752 if (IdxNode.getOpcode() == ISD::UNDEF) {
6753 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
6756 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getValue();
6757 SDOperand InVec = Node->getOperand(0);
6758 if (Idx >= NumElements) {
6759 InVec = Node->getOperand(1);
6762 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6763 DAG.getConstant(Idx, PtrVT)));
6765 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6768 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
6769 SDOperand IdxNode = Mask.getOperand(i);
6770 if (IdxNode.getOpcode() == ISD::UNDEF) {
6771 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
6774 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getValue();
6775 SDOperand InVec = Node->getOperand(0);
6776 if (Idx >= NumElements) {
6777 InVec = Node->getOperand(1);
6780 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6781 DAG.getConstant(Idx, PtrVT)));
6783 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6786 case ISD::BUILD_VECTOR: {
6787 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
6788 Node->op_begin()+NewNumElts_Lo);
6789 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size());
6791 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
6793 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size());
6796 case ISD::CONCAT_VECTORS: {
6797 // FIXME: Handle non-power-of-two vectors?
6798 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
6799 if (NewNumSubvectors == 1) {
6800 Lo = Node->getOperand(0);
6801 Hi = Node->getOperand(1);
6803 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
6804 Node->op_begin()+NewNumSubvectors);
6805 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size());
6807 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors,
6809 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size());
6814 SDOperand Cond = Node->getOperand(0);
6816 SDOperand LL, LH, RL, RH;
6817 SplitVectorOp(Node->getOperand(1), LL, LH);
6818 SplitVectorOp(Node->getOperand(2), RL, RH);
6820 if (MVT::isVector(Cond.getValueType())) {
6821 // Handle a vector merge.
6823 SplitVectorOp(Cond, CL, CH);
6824 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL);
6825 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH);
6827 // Handle a simple select with vector operands.
6828 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL);
6829 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH);
6849 SDOperand LL, LH, RL, RH;
6850 SplitVectorOp(Node->getOperand(0), LL, LH);
6851 SplitVectorOp(Node->getOperand(1), RL, RH);
6853 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL);
6854 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH);
6859 SplitVectorOp(Node->getOperand(0), L, H);
6861 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1));
6862 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1));
6873 case ISD::FP_TO_SINT:
6874 case ISD::FP_TO_UINT:
6875 case ISD::SINT_TO_FP:
6876 case ISD::UINT_TO_FP: {
6878 SplitVectorOp(Node->getOperand(0), L, H);
6880 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L);
6881 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H);
6885 LoadSDNode *LD = cast<LoadSDNode>(Node);
6886 SDOperand Ch = LD->getChain();
6887 SDOperand Ptr = LD->getBasePtr();
6888 const Value *SV = LD->getSrcValue();
6889 int SVOffset = LD->getSrcValueOffset();
6890 unsigned Alignment = LD->getAlignment();
6891 bool isVolatile = LD->isVolatile();
6893 Lo = DAG.getLoad(NewVT_Lo, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
6894 unsigned IncrementSize = NewNumElts_Lo * MVT::getSizeInBits(NewEltVT)/8;
6895 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
6896 DAG.getIntPtrConstant(IncrementSize));
6897 SVOffset += IncrementSize;
6898 Alignment = MinAlign(Alignment, IncrementSize);
6899 Hi = DAG.getLoad(NewVT_Hi, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
6901 // Build a factor node to remember that this load is independent of the
6903 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
6906 // Remember that we legalized the chain.
6907 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
6910 case ISD::BIT_CONVERT: {
6911 // We know the result is a vector. The input may be either a vector or a
6913 SDOperand InOp = Node->getOperand(0);
6914 if (!MVT::isVector(InOp.getValueType()) ||
6915 MVT::getVectorNumElements(InOp.getValueType()) == 1) {
6916 // The input is a scalar or single-element vector.
6917 // Lower to a store/load so that it can be split.
6918 // FIXME: this could be improved probably.
6919 SDOperand Ptr = DAG.CreateStackTemporary(InOp.getValueType());
6920 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(Ptr.Val);
6922 SDOperand St = DAG.getStore(DAG.getEntryNode(),
6924 PseudoSourceValue::getFixedStack(),
6926 InOp = DAG.getLoad(Op.getValueType(), St, Ptr,
6927 PseudoSourceValue::getFixedStack(),
6930 // Split the vector and convert each of the pieces now.
6931 SplitVectorOp(InOp, Lo, Hi);
6932 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo);
6933 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi);
6938 // Remember in a map if the values will be reused later.
6940 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
6941 assert(isNew && "Value already split?!?");
6945 /// ScalarizeVectorOp - Given an operand of single-element vector type
6946 /// (e.g. v1f32), convert it into the equivalent operation that returns a
6947 /// scalar (e.g. f32) value.
6948 SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) {
6949 assert(MVT::isVector(Op.getValueType()) &&
6950 "Bad ScalarizeVectorOp invocation!");
6951 SDNode *Node = Op.Val;
6952 MVT::ValueType NewVT = MVT::getVectorElementType(Op.getValueType());
6953 assert(MVT::getVectorNumElements(Op.getValueType()) == 1);
6955 // See if we already scalarized it.
6956 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op);
6957 if (I != ScalarizedNodes.end()) return I->second;
6960 switch (Node->getOpcode()) {
6963 Node->dump(&DAG); cerr << "\n";
6965 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
6982 Result = DAG.getNode(Node->getOpcode(),
6984 ScalarizeVectorOp(Node->getOperand(0)),
6985 ScalarizeVectorOp(Node->getOperand(1)));
6992 Result = DAG.getNode(Node->getOpcode(),
6994 ScalarizeVectorOp(Node->getOperand(0)));
6997 Result = DAG.getNode(Node->getOpcode(),
6999 ScalarizeVectorOp(Node->getOperand(0)),
7000 Node->getOperand(1));
7003 LoadSDNode *LD = cast<LoadSDNode>(Node);
7004 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
7005 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
7007 const Value *SV = LD->getSrcValue();
7008 int SVOffset = LD->getSrcValueOffset();
7009 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset,
7010 LD->isVolatile(), LD->getAlignment());
7012 // Remember that we legalized the chain.
7013 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
7016 case ISD::BUILD_VECTOR:
7017 Result = Node->getOperand(0);
7019 case ISD::INSERT_VECTOR_ELT:
7020 // Returning the inserted scalar element.
7021 Result = Node->getOperand(1);
7023 case ISD::CONCAT_VECTORS:
7024 assert(Node->getOperand(0).getValueType() == NewVT &&
7025 "Concat of non-legal vectors not yet supported!");
7026 Result = Node->getOperand(0);
7028 case ISD::VECTOR_SHUFFLE: {
7029 // Figure out if the scalar is the LHS or RHS and return it.
7030 SDOperand EltNum = Node->getOperand(2).getOperand(0);
7031 if (cast<ConstantSDNode>(EltNum)->getValue())
7032 Result = ScalarizeVectorOp(Node->getOperand(1));
7034 Result = ScalarizeVectorOp(Node->getOperand(0));
7037 case ISD::EXTRACT_SUBVECTOR:
7038 Result = Node->getOperand(0);
7039 assert(Result.getValueType() == NewVT);
7041 case ISD::BIT_CONVERT:
7042 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));
7045 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
7046 ScalarizeVectorOp(Op.getOperand(1)),
7047 ScalarizeVectorOp(Op.getOperand(2)));
7051 if (TLI.isTypeLegal(NewVT))
7052 Result = LegalizeOp(Result);
7053 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
7054 assert(isNew && "Value already scalarized?");
7059 // SelectionDAG::Legalize - This is the entry point for the file.
7061 void SelectionDAG::Legalize() {
7062 if (ViewLegalizeDAGs) viewGraph();
7064 /// run - This is the main entry point to this class.
7066 SelectionDAGLegalize(*this).LegalizeDAG();