1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/Support/MathExtras.h"
18 #include "llvm/Target/TargetLowering.h"
19 #include "llvm/Target/TargetData.h"
20 #include "llvm/Target/TargetOptions.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/Constants.h"
27 //===----------------------------------------------------------------------===//
28 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
29 /// hacks on it until the target machine can handle it. This involves
30 /// eliminating value sizes the machine cannot handle (promoting small sizes to
31 /// large sizes or splitting up large values into small values) as well as
32 /// eliminating operations the machine cannot handle.
34 /// This code also does a small amount of optimization and recognition of idioms
35 /// as part of its processing. For example, if a target does not support a
36 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
37 /// will attempt merge setcc and brc instructions into brcc's.
40 class SelectionDAGLegalize {
44 /// LegalizeAction - This enum indicates what action we should take for each
45 /// value type the can occur in the program.
47 Legal, // The target natively supports this value type.
48 Promote, // This should be promoted to the next larger type.
49 Expand, // This integer type should be broken into smaller pieces.
52 /// ValueTypeActions - This is a bitvector that contains two bits for each
53 /// value type, where the two bits correspond to the LegalizeAction enum.
54 /// This can be queried with "getTypeAction(VT)".
55 unsigned long long ValueTypeActions;
57 /// NeedsAnotherIteration - This is set when we expand a large integer
58 /// operation into smaller integer operations, but the smaller operations are
59 /// not set. This occurs only rarely in practice, for targets that don't have
60 /// 32-bit or larger integer registers.
61 bool NeedsAnotherIteration;
63 /// LegalizedNodes - For nodes that are of legal width, and that have more
64 /// than one use, this map indicates what regularized operand to use. This
65 /// allows us to avoid legalizing the same thing more than once.
66 std::map<SDOperand, SDOperand> LegalizedNodes;
68 /// PromotedNodes - For nodes that are below legal width, and that have more
69 /// than one use, this map indicates what promoted value to use. This allows
70 /// us to avoid promoting the same thing more than once.
71 std::map<SDOperand, SDOperand> PromotedNodes;
73 /// ExpandedNodes - For nodes that need to be expanded, and which have more
74 /// than one use, this map indicates which which operands are the expanded
75 /// version of the input. This allows us to avoid expanding the same node
77 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
79 void AddLegalizedOperand(SDOperand From, SDOperand To) {
80 bool isNew = LegalizedNodes.insert(std::make_pair(From, To)).second;
81 assert(isNew && "Got into the map somehow?");
83 void AddPromotedOperand(SDOperand From, SDOperand To) {
84 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
85 assert(isNew && "Got into the map somehow?");
90 SelectionDAGLegalize(SelectionDAG &DAG);
92 /// Run - While there is still lowering to do, perform a pass over the DAG.
93 /// Most regularization can be done in a single pass, but targets that require
94 /// large values to be split into registers multiple times (e.g. i64 -> 4x
95 /// i16) require iteration for these values (the first iteration will demote
96 /// to i32, the second will demote to i16).
99 NeedsAnotherIteration = false;
101 } while (NeedsAnotherIteration);
104 /// getTypeAction - Return how we should legalize values of this type, either
105 /// it is already legal or we need to expand it into multiple registers of
106 /// smaller integer type, or we need to promote it to a larger type.
107 LegalizeAction getTypeAction(MVT::ValueType VT) const {
108 return (LegalizeAction)((ValueTypeActions >> (2*VT)) & 3);
111 /// isTypeLegal - Return true if this type is legal on this target.
113 bool isTypeLegal(MVT::ValueType VT) const {
114 return getTypeAction(VT) == Legal;
120 SDOperand LegalizeOp(SDOperand O);
121 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
122 SDOperand PromoteOp(SDOperand O);
124 SDOperand ExpandLibCall(const char *Name, SDNode *Node,
126 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
129 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
131 MVT::ValueType DestVT);
132 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
134 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
137 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
138 SDOperand &Lo, SDOperand &Hi);
139 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
140 SDOperand &Lo, SDOperand &Hi);
141 void ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS,
142 SDOperand &Lo, SDOperand &Hi);
144 void SpliceCallInto(const SDOperand &CallResult, SDNode *OutChain);
146 SDOperand getIntPtrConstant(uint64_t Val) {
147 return DAG.getConstant(Val, TLI.getPointerTy());
152 static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) {
154 default: assert(0 && "Don't know how to scalarize this opcode!");
155 case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD;
156 case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB;
157 case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL;
161 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
162 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
163 ValueTypeActions(TLI.getValueTypeActions()) {
164 assert(MVT::LAST_VALUETYPE <= 32 &&
165 "Too many value types for ValueTypeActions to hold!");
168 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
169 /// INT_TO_FP operation of the specified operand when the target requests that
170 /// we expand it. At this point, we know that the result and operand types are
171 /// legal for the target.
172 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
174 MVT::ValueType DestVT) {
175 if (Op0.getValueType() == MVT::i32) {
176 // simple 32-bit [signed|unsigned] integer to float/double expansion
178 // get the stack frame index of a 8 byte buffer
179 MachineFunction &MF = DAG.getMachineFunction();
180 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
181 // get address of 8 byte buffer
182 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
183 // word offset constant for Hi/Lo address computation
184 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
185 // set up Hi and Lo (into buffer) address based on endian
187 if (TLI.isLittleEndian()) {
188 Hi = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff);
192 Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff);
194 // if signed map to unsigned space
197 // constant used to invert sign bit (signed to unsigned mapping)
198 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
199 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
203 // store the lo of the constructed double - based on integer input
204 SDOperand Store1 = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
205 Op0Mapped, Lo, DAG.getSrcValue(NULL));
206 // initial hi portion of constructed double
207 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
208 // store the hi of the constructed double - biased exponent
209 SDOperand Store2 = DAG.getNode(ISD::STORE, MVT::Other, Store1,
210 InitialHi, Hi, DAG.getSrcValue(NULL));
211 // load the constructed double
212 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot,
213 DAG.getSrcValue(NULL));
214 // FP constant to bias correct the final result
215 SDOperand Bias = DAG.getConstantFP(isSigned ?
216 BitsToDouble(0x4330000080000000ULL)
217 : BitsToDouble(0x4330000000000000ULL),
220 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
223 // handle final rounding
224 if (DestVT == MVT::f64) {
228 // if f32 then cast to f32
229 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub);
231 NeedsAnotherIteration = true;
234 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
235 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
237 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
238 DAG.getConstant(0, Op0.getValueType()),
240 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
241 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
242 SignSet, Four, Zero);
244 // If the sign bit of the integer is set, the large number will be treated
245 // as a negative number. To counteract this, the dynamic code adds an
246 // offset depending on the data type.
248 switch (Op0.getValueType()) {
249 default: assert(0 && "Unsupported integer type!");
250 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
251 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
252 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
253 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
255 if (TLI.isLittleEndian()) FF <<= 32;
256 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
258 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
259 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
260 SDOperand FudgeInReg;
261 if (DestVT == MVT::f32)
262 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
263 DAG.getSrcValue(NULL));
265 assert(DestVT == MVT::f64 && "Unexpected conversion");
266 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64,
267 DAG.getEntryNode(), CPIdx,
268 DAG.getSrcValue(NULL), MVT::f32));
271 NeedsAnotherIteration = true;
272 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
275 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
276 /// *INT_TO_FP operation of the specified operand when the target requests that
277 /// we promote it. At this point, we know that the result and operand types are
278 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
279 /// operation that takes a larger input.
280 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
281 MVT::ValueType DestVT,
283 // First step, figure out the appropriate *INT_TO_FP operation to use.
284 MVT::ValueType NewInTy = LegalOp.getValueType();
286 unsigned OpToUse = 0;
288 // Scan for the appropriate larger type to use.
290 NewInTy = (MVT::ValueType)(NewInTy+1);
291 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
293 // If the target supports SINT_TO_FP of this type, use it.
294 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
296 case TargetLowering::Legal:
297 if (!TLI.isTypeLegal(NewInTy))
298 break; // Can't use this datatype.
300 case TargetLowering::Custom:
301 OpToUse = ISD::SINT_TO_FP;
305 if (isSigned) continue;
307 // If the target supports UINT_TO_FP of this type, use it.
308 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
310 case TargetLowering::Legal:
311 if (!TLI.isTypeLegal(NewInTy))
312 break; // Can't use this datatype.
314 case TargetLowering::Custom:
315 OpToUse = ISD::UINT_TO_FP;
320 // Otherwise, try a larger type.
323 // Make sure to legalize any nodes we create here in the next pass.
324 NeedsAnotherIteration = true;
326 // Okay, we found the operation and type to use. Zero extend our input to the
327 // desired type then run the operation on it.
328 return DAG.getNode(OpToUse, DestVT,
329 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
333 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
334 /// FP_TO_*INT operation of the specified operand when the target requests that
335 /// we promote it. At this point, we know that the result and operand types are
336 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
337 /// operation that returns a larger result.
338 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
339 MVT::ValueType DestVT,
341 // First step, figure out the appropriate FP_TO*INT operation to use.
342 MVT::ValueType NewOutTy = DestVT;
344 unsigned OpToUse = 0;
346 // Scan for the appropriate larger type to use.
348 NewOutTy = (MVT::ValueType)(NewOutTy+1);
349 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
351 // If the target supports FP_TO_SINT returning this type, use it.
352 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
354 case TargetLowering::Legal:
355 if (!TLI.isTypeLegal(NewOutTy))
356 break; // Can't use this datatype.
358 case TargetLowering::Custom:
359 OpToUse = ISD::FP_TO_SINT;
364 // If the target supports FP_TO_UINT of this type, use it.
365 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
367 case TargetLowering::Legal:
368 if (!TLI.isTypeLegal(NewOutTy))
369 break; // Can't use this datatype.
371 case TargetLowering::Custom:
372 OpToUse = ISD::FP_TO_UINT;
377 // Otherwise, try a larger type.
380 // Make sure to legalize any nodes we create here in the next pass.
381 NeedsAnotherIteration = true;
383 // Okay, we found the operation and type to use. Truncate the result of the
384 // extended FP_TO_*INT operation to the desired size.
385 return DAG.getNode(ISD::TRUNCATE, DestVT,
386 DAG.getNode(OpToUse, NewOutTy, LegalOp));
389 /// ComputeTopDownOrdering - Add the specified node to the Order list if it has
390 /// not been visited yet and if all of its operands have already been visited.
391 static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order,
392 std::map<SDNode*, unsigned> &Visited) {
393 if (++Visited[N] != N->getNumOperands())
394 return; // Haven't visited all operands yet
398 if (N->hasOneUse()) { // Tail recurse in common case.
399 ComputeTopDownOrdering(*N->use_begin(), Order, Visited);
403 // Now that we have N in, add anything that uses it if all of their operands
405 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI)
406 ComputeTopDownOrdering(*UI, Order, Visited);
410 void SelectionDAGLegalize::LegalizeDAG() {
411 // The legalize process is inherently a bottom-up recursive process (users
412 // legalize their uses before themselves). Given infinite stack space, we
413 // could just start legalizing on the root and traverse the whole graph. In
414 // practice however, this causes us to run out of stack space on large basic
415 // blocks. To avoid this problem, compute an ordering of the nodes where each
416 // node is only legalized after all of its operands are legalized.
417 std::map<SDNode*, unsigned> Visited;
418 std::vector<SDNode*> Order;
420 // Compute ordering from all of the leaves in the graphs, those (like the
421 // entry node) that have no operands.
422 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
423 E = DAG.allnodes_end(); I != E; ++I) {
424 if (I->getNumOperands() == 0) {
426 ComputeTopDownOrdering(I, Order, Visited);
430 assert(Order.size() == Visited.size() &&
432 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
433 "Error: DAG is cyclic!");
436 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
437 SDNode *N = Order[i];
438 switch (getTypeAction(N->getValueType(0))) {
439 default: assert(0 && "Bad type action!");
441 LegalizeOp(SDOperand(N, 0));
444 PromoteOp(SDOperand(N, 0));
448 ExpandOp(SDOperand(N, 0), X, Y);
454 // Finally, it's possible the root changed. Get the new root.
455 SDOperand OldRoot = DAG.getRoot();
456 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
457 DAG.setRoot(LegalizedNodes[OldRoot]);
459 ExpandedNodes.clear();
460 LegalizedNodes.clear();
461 PromotedNodes.clear();
463 // Remove dead nodes now.
464 DAG.RemoveDeadNodes(OldRoot.Val);
467 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
468 assert(isTypeLegal(Op.getValueType()) &&
469 "Caller should expand or promote operands that are not legal!");
470 SDNode *Node = Op.Val;
472 // If this operation defines any values that cannot be represented in a
473 // register on this target, make sure to expand or promote them.
474 if (Node->getNumValues() > 1) {
475 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
476 switch (getTypeAction(Node->getValueType(i))) {
477 case Legal: break; // Nothing to do.
480 ExpandOp(Op.getValue(i), T1, T2);
481 assert(LegalizedNodes.count(Op) &&
482 "Expansion didn't add legal operands!");
483 return LegalizedNodes[Op];
486 PromoteOp(Op.getValue(i));
487 assert(LegalizedNodes.count(Op) &&
488 "Expansion didn't add legal operands!");
489 return LegalizedNodes[Op];
493 // Note that LegalizeOp may be reentered even from single-use nodes, which
494 // means that we always must cache transformed nodes.
495 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
496 if (I != LegalizedNodes.end()) return I->second;
498 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
500 SDOperand Result = Op;
502 switch (Node->getOpcode()) {
504 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
505 // If this is a target node, legalize it by legalizing the operands then
506 // passing it through.
507 std::vector<SDOperand> Ops;
508 bool Changed = false;
509 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
510 Ops.push_back(LegalizeOp(Node->getOperand(i)));
511 Changed = Changed || Node->getOperand(i) != Ops.back();
514 if (Node->getNumValues() == 1)
515 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Ops);
517 std::vector<MVT::ValueType> VTs(Node->value_begin(),
519 Result = DAG.getNode(Node->getOpcode(), VTs, Ops);
522 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
523 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
524 return Result.getValue(Op.ResNo);
526 // Otherwise this is an unhandled builtin node. splat.
527 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
528 assert(0 && "Do not know how to legalize this operator!");
530 case ISD::EntryToken:
531 case ISD::FrameIndex:
532 case ISD::TargetFrameIndex:
534 case ISD::TargetConstant:
535 case ISD::GlobalAddress:
536 case ISD::TargetGlobalAddress:
537 case ISD::ExternalSymbol:
538 case ISD::ConstantPool: // Nothing to do.
539 case ISD::BasicBlock:
544 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
545 default: assert(0 && "This action is not supported yet!");
546 case TargetLowering::Custom: {
547 SDOperand Tmp = TLI.LowerOperation(Op, DAG);
549 Result = LegalizeOp(Tmp);
552 } // FALLTHROUGH if the target doesn't want to lower this op after all.
553 case TargetLowering::Legal:
554 assert(isTypeLegal(Node->getValueType(0)) && "This must be legal!");
558 case ISD::AssertSext:
559 case ISD::AssertZext:
560 Tmp1 = LegalizeOp(Node->getOperand(0));
561 if (Tmp1 != Node->getOperand(0))
562 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,
563 Node->getOperand(1));
565 case ISD::MERGE_VALUES:
566 return LegalizeOp(Node->getOperand(Op.ResNo));
567 case ISD::CopyFromReg:
568 Tmp1 = LegalizeOp(Node->getOperand(0));
569 if (Tmp1 != Node->getOperand(0))
570 Result = DAG.getCopyFromReg(Tmp1,
571 cast<RegisterSDNode>(Node->getOperand(1))->getReg(),
572 Node->getValueType(0));
574 Result = Op.getValue(0);
576 // Since CopyFromReg produces two values, make sure to remember that we
577 // legalized both of them.
578 AddLegalizedOperand(Op.getValue(0), Result);
579 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
580 return Result.getValue(Op.ResNo);
581 case ISD::ImplicitDef:
582 Tmp1 = LegalizeOp(Node->getOperand(0));
583 if (Tmp1 != Node->getOperand(0))
584 Result = DAG.getNode(ISD::ImplicitDef, MVT::Other,
585 Tmp1, Node->getOperand(1));
588 MVT::ValueType VT = Op.getValueType();
589 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
590 default: assert(0 && "This action is not supported yet!");
591 case TargetLowering::Expand:
592 case TargetLowering::Promote:
593 if (MVT::isInteger(VT))
594 Result = DAG.getConstant(0, VT);
595 else if (MVT::isFloatingPoint(VT))
596 Result = DAG.getConstantFP(0, VT);
598 assert(0 && "Unknown value type!");
600 case TargetLowering::Legal:
607 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
608 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
610 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
611 case TargetLowering::Promote:
612 default: assert(0 && "This action is not supported yet!");
613 case TargetLowering::Expand:
614 // If the target doesn't support line numbers, ignore this node.
617 case TargetLowering::Legal:
618 if (Tmp1 != Node->getOperand(0)) {
619 std::vector<SDOperand> Ops;
621 Ops.push_back(Node->getOperand(1)); // line # must be legal.
622 Ops.push_back(Node->getOperand(2)); // col # must be legal.
623 Ops.push_back(Node->getOperand(3)); // filename must be legal.
624 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
625 Result = DAG.getNode(ISD::LOCATION, MVT::Other, Ops);
632 // We know we don't need to expand constants here, constants only have one
633 // value and we check that it is fine above.
635 // FIXME: Maybe we should handle things like targets that don't support full
636 // 32-bit immediates?
638 case ISD::ConstantFP: {
639 // Spill FP immediates to the constant pool if the target cannot directly
640 // codegen them. Targets often have some immediate values that can be
641 // efficiently generated into an FP register without a load. We explicitly
642 // leave these constants as ConstantFP nodes for the target to deal with.
644 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
646 // Check to see if this FP immediate is already legal.
647 bool isLegal = false;
648 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
649 E = TLI.legal_fpimm_end(); I != E; ++I)
650 if (CFP->isExactlyValue(*I)) {
656 // Otherwise we need to spill the constant to memory.
659 // If a FP immediate is precise when represented as a float, we put it
660 // into the constant pool as a float, even if it's is statically typed
662 MVT::ValueType VT = CFP->getValueType(0);
663 bool isDouble = VT == MVT::f64;
664 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy :
665 Type::FloatTy, CFP->getValue());
666 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) &&
667 // Only do this if the target has a native EXTLOAD instruction from
669 TLI.isOperationLegal(ISD::EXTLOAD, MVT::f32)) {
670 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy));
675 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
677 Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
678 CPIdx, DAG.getSrcValue(NULL), MVT::f32);
680 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
681 DAG.getSrcValue(NULL));
686 case ISD::TokenFactor:
687 if (Node->getNumOperands() == 2) {
688 bool Changed = false;
689 SDOperand Op0 = LegalizeOp(Node->getOperand(0));
690 SDOperand Op1 = LegalizeOp(Node->getOperand(1));
691 if (Op0 != Node->getOperand(0) || Op1 != Node->getOperand(1))
692 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Op0, Op1);
694 std::vector<SDOperand> Ops;
695 bool Changed = false;
696 // Legalize the operands.
697 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
698 SDOperand Op = Node->getOperand(i);
699 Ops.push_back(LegalizeOp(Op));
700 Changed |= Ops[i] != Op;
703 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Ops);
707 case ISD::CALLSEQ_START:
708 case ISD::CALLSEQ_END:
709 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
710 // Do not try to legalize the target-specific arguments (#1+)
711 Tmp2 = Node->getOperand(0);
713 Node->setAdjCallChain(Tmp1);
715 // Note that we do not create new CALLSEQ_DOWN/UP nodes here. These
716 // nodes are treated specially and are mutated in place. This makes the dag
717 // legalization process more efficient and also makes libcall insertion
720 case ISD::DYNAMIC_STACKALLOC:
721 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
722 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
723 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
724 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
725 Tmp3 != Node->getOperand(2)) {
726 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end());
727 std::vector<SDOperand> Ops;
728 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3);
729 Result = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, Ops);
731 Result = Op.getValue(0);
733 // Since this op produces two values, make sure to remember that we
734 // legalized both of them.
735 AddLegalizedOperand(SDOperand(Node, 0), Result);
736 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
737 return Result.getValue(Op.ResNo);
741 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
742 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee.
744 bool Changed = false;
745 std::vector<SDOperand> Ops;
746 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) {
747 Ops.push_back(LegalizeOp(Node->getOperand(i)));
748 Changed |= Ops.back() != Node->getOperand(i);
751 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || Changed) {
752 std::vector<MVT::ValueType> RetTyVTs;
753 RetTyVTs.reserve(Node->getNumValues());
754 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
755 RetTyVTs.push_back(Node->getValueType(i));
756 Result = SDOperand(DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops,
757 Node->getOpcode() == ISD::TAILCALL), 0);
759 Result = Result.getValue(0);
761 // Since calls produce multiple values, make sure to remember that we
762 // legalized all of them.
763 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
764 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
765 return Result.getValue(Op.ResNo);
768 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
769 if (Tmp1 != Node->getOperand(0))
770 Result = DAG.getNode(ISD::BR, MVT::Other, Tmp1, Node->getOperand(1));
774 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
776 switch (getTypeAction(Node->getOperand(1).getValueType())) {
777 case Expand: assert(0 && "It's impossible to expand bools");
779 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
782 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
786 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
787 default: assert(0 && "This action is not supported yet!");
788 case TargetLowering::Expand:
789 // Expand brcond's setcc into its constituent parts and create a BR_CC
791 if (Tmp2.getOpcode() == ISD::SETCC) {
792 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
793 Tmp2.getOperand(0), Tmp2.getOperand(1),
794 Node->getOperand(2));
796 // Make sure the condition is either zero or one. It may have been
797 // promoted from something else.
798 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
800 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
801 DAG.getCondCode(ISD::SETNE), Tmp2,
802 DAG.getConstant(0, Tmp2.getValueType()),
803 Node->getOperand(2));
806 case TargetLowering::Legal:
807 // Basic block destination (Op#2) is always legal.
808 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
809 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2,
810 Node->getOperand(2));
815 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
817 if (isTypeLegal(Node->getOperand(2).getValueType())) {
818 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS
819 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS
820 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) ||
821 Tmp3 != Node->getOperand(3)) {
822 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Node->getOperand(1),
823 Tmp2, Tmp3, Node->getOperand(4));
827 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),
828 Node->getOperand(2), // LHS
829 Node->getOperand(3), // RHS
830 Node->getOperand(1)));
831 // If we get a SETCC back from legalizing the SETCC node we just
832 // created, then use its LHS, RHS, and CC directly in creating a new
833 // node. Otherwise, select between the true and false value based on
834 // comparing the result of the legalized with zero.
835 if (Tmp2.getOpcode() == ISD::SETCC) {
836 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
837 Tmp2.getOperand(0), Tmp2.getOperand(1),
838 Node->getOperand(4));
840 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
841 DAG.getCondCode(ISD::SETNE),
842 Tmp2, DAG.getConstant(0, Tmp2.getValueType()),
843 Node->getOperand(4));
847 case ISD::BRCONDTWOWAY:
848 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
849 switch (getTypeAction(Node->getOperand(1).getValueType())) {
850 case Expand: assert(0 && "It's impossible to expand bools");
852 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
855 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
858 // If this target does not support BRCONDTWOWAY, lower it to a BRCOND/BR
860 switch (TLI.getOperationAction(ISD::BRCONDTWOWAY, MVT::Other)) {
861 case TargetLowering::Promote:
862 default: assert(0 && "This action is not supported yet!");
863 case TargetLowering::Legal:
864 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) {
865 std::vector<SDOperand> Ops;
868 Ops.push_back(Node->getOperand(2));
869 Ops.push_back(Node->getOperand(3));
870 Result = DAG.getNode(ISD::BRCONDTWOWAY, MVT::Other, Ops);
873 case TargetLowering::Expand:
874 // If BRTWOWAY_CC is legal for this target, then simply expand this node
875 // to that. Otherwise, skip BRTWOWAY_CC and expand directly to a
877 if (TLI.isOperationLegal(ISD::BRTWOWAY_CC, MVT::Other)) {
878 if (Tmp2.getOpcode() == ISD::SETCC) {
879 Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2),
880 Tmp2.getOperand(0), Tmp2.getOperand(1),
881 Node->getOperand(2), Node->getOperand(3));
883 Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2,
884 DAG.getConstant(0, Tmp2.getValueType()),
885 Node->getOperand(2), Node->getOperand(3));
888 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2,
889 Node->getOperand(2));
890 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(3));
895 case ISD::BRTWOWAY_CC:
896 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
897 if (isTypeLegal(Node->getOperand(2).getValueType())) {
898 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS
899 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS
900 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) ||
901 Tmp3 != Node->getOperand(3)) {
902 Result = DAG.getBR2Way_CC(Tmp1, Node->getOperand(1), Tmp2, Tmp3,
903 Node->getOperand(4), Node->getOperand(5));
907 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),
908 Node->getOperand(2), // LHS
909 Node->getOperand(3), // RHS
910 Node->getOperand(1)));
911 // If this target does not support BRTWOWAY_CC, lower it to a BRCOND/BR
913 switch (TLI.getOperationAction(ISD::BRTWOWAY_CC, MVT::Other)) {
914 default: assert(0 && "This action is not supported yet!");
915 case TargetLowering::Legal:
916 // If we get a SETCC back from legalizing the SETCC node we just
917 // created, then use its LHS, RHS, and CC directly in creating a new
918 // node. Otherwise, select between the true and false value based on
919 // comparing the result of the legalized with zero.
920 if (Tmp2.getOpcode() == ISD::SETCC) {
921 Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2),
922 Tmp2.getOperand(0), Tmp2.getOperand(1),
923 Node->getOperand(4), Node->getOperand(5));
925 Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2,
926 DAG.getConstant(0, Tmp2.getValueType()),
927 Node->getOperand(4), Node->getOperand(5));
930 case TargetLowering::Expand:
931 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2,
932 Node->getOperand(4));
933 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(5));
939 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
940 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
942 if (Tmp1 != Node->getOperand(0) ||
943 Tmp2 != Node->getOperand(1))
944 Result = DAG.getLoad(Node->getValueType(0), Tmp1, Tmp2,
945 Node->getOperand(2));
947 Result = SDOperand(Node, 0);
949 // Since loads produce two values, make sure to remember that we legalized
951 AddLegalizedOperand(SDOperand(Node, 0), Result);
952 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
953 return Result.getValue(Op.ResNo);
957 case ISD::ZEXTLOAD: {
958 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
959 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
961 MVT::ValueType SrcVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
962 switch (TLI.getOperationAction(Node->getOpcode(), SrcVT)) {
963 default: assert(0 && "This action is not supported yet!");
964 case TargetLowering::Promote:
965 assert(SrcVT == MVT::i1 && "Can only promote EXTLOAD from i1 -> i8!");
966 Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0),
967 Tmp1, Tmp2, Node->getOperand(2), MVT::i8);
968 // Since loads produce two values, make sure to remember that we legalized
970 AddLegalizedOperand(SDOperand(Node, 0), Result);
971 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
972 return Result.getValue(Op.ResNo);
974 case TargetLowering::Legal:
975 if (Tmp1 != Node->getOperand(0) ||
976 Tmp2 != Node->getOperand(1))
977 Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0),
978 Tmp1, Tmp2, Node->getOperand(2), SrcVT);
980 Result = SDOperand(Node, 0);
982 // Since loads produce two values, make sure to remember that we legalized
984 AddLegalizedOperand(SDOperand(Node, 0), Result);
985 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
986 return Result.getValue(Op.ResNo);
987 case TargetLowering::Expand:
988 //f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
989 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
990 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, Node->getOperand(2));
991 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
993 return Load.getValue(1);
996 assert(Node->getOpcode() != ISD::EXTLOAD &&
997 "EXTLOAD should always be supported!");
998 // Turn the unsupported load into an EXTLOAD followed by an explicit
999 // zero/sign extend inreg.
1000 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
1001 Tmp1, Tmp2, Node->getOperand(2), SrcVT);
1003 if (Node->getOpcode() == ISD::SEXTLOAD)
1004 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1005 Result, DAG.getValueType(SrcVT));
1007 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
1008 AddLegalizedOperand(SDOperand(Node, 0), ValRes);
1009 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1011 return Result.getValue(1);
1014 assert(0 && "Unreachable");
1016 case ISD::EXTRACT_ELEMENT: {
1017 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
1018 switch (getTypeAction(OpTy)) {
1020 assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
1023 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
1025 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
1026 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
1027 TLI.getShiftAmountTy()));
1028 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
1031 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
1032 Node->getOperand(0));
1034 Result = LegalizeOp(Result);
1037 // Get both the low and high parts.
1038 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1039 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
1040 Result = Tmp2; // 1 -> Hi
1042 Result = Tmp1; // 0 -> Lo
1048 case ISD::CopyToReg:
1049 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1051 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
1052 "Register type must be legal!");
1053 // Legalize the incoming value (must be legal).
1054 Tmp2 = LegalizeOp(Node->getOperand(2));
1055 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2))
1056 Result = DAG.getNode(ISD::CopyToReg, MVT::Other, Tmp1,
1057 Node->getOperand(1), Tmp2);
1061 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1062 switch (Node->getNumOperands()) {
1064 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1066 Tmp2 = LegalizeOp(Node->getOperand(1));
1067 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
1068 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2);
1072 ExpandOp(Node->getOperand(1), Lo, Hi);
1073 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi);
1077 Tmp2 = PromoteOp(Node->getOperand(1));
1078 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2);
1083 if (Tmp1 != Node->getOperand(0))
1084 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1);
1086 default: { // ret <values>
1087 std::vector<SDOperand> NewValues;
1088 NewValues.push_back(Tmp1);
1089 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i)
1090 switch (getTypeAction(Node->getOperand(i).getValueType())) {
1092 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
1096 ExpandOp(Node->getOperand(i), Lo, Hi);
1097 NewValues.push_back(Lo);
1098 NewValues.push_back(Hi);
1102 assert(0 && "Can't promote multiple return value yet!");
1104 Result = DAG.getNode(ISD::RET, MVT::Other, NewValues);
1110 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1111 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
1113 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
1114 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){
1115 if (CFP->getValueType(0) == MVT::f32) {
1116 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1,
1117 DAG.getConstant(FloatToBits(CFP->getValue()),
1120 Node->getOperand(3));
1122 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
1123 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1,
1124 DAG.getConstant(DoubleToBits(CFP->getValue()),
1127 Node->getOperand(3));
1132 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1134 SDOperand Val = LegalizeOp(Node->getOperand(1));
1135 if (Val != Node->getOperand(1) || Tmp1 != Node->getOperand(0) ||
1136 Tmp2 != Node->getOperand(2))
1137 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Val, Tmp2,
1138 Node->getOperand(3));
1142 // Truncate the value and store the result.
1143 Tmp3 = PromoteOp(Node->getOperand(1));
1144 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2,
1145 Node->getOperand(3),
1146 DAG.getValueType(Node->getOperand(1).getValueType()));
1151 unsigned IncrementSize;
1152 ExpandOp(Node->getOperand(1), Lo, Hi);
1154 if (!TLI.isLittleEndian())
1157 Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2,
1158 Node->getOperand(3));
1159 // If this is a vector type, then we have to calculate the increment as
1160 // the product of the element size in bytes, and the number of elements
1161 // in the high half of the vector.
1162 if (MVT::Vector == Hi.getValueType()) {
1163 unsigned NumElems = cast<ConstantSDNode>(Hi.getOperand(2))->getValue();
1164 MVT::ValueType EVT = cast<VTSDNode>(Hi.getOperand(3))->getVT();
1165 IncrementSize = NumElems * MVT::getSizeInBits(EVT)/8;
1167 IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8;
1169 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1170 getIntPtrConstant(IncrementSize));
1171 assert(isTypeLegal(Tmp2.getValueType()) &&
1172 "Pointers must be legal!");
1173 //Again, claiming both parts of the store came form the same Instr
1174 Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2,
1175 Node->getOperand(3));
1176 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
1181 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1182 if (Tmp1 != Node->getOperand(0))
1183 Result = DAG.getNode(ISD::PCMARKER, MVT::Other, Tmp1,Node->getOperand(1));
1185 case ISD::READCYCLECOUNTER:
1186 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
1187 if (Tmp1 != Node->getOperand(0))
1188 Result = DAG.getNode(ISD::READCYCLECOUNTER, MVT::i64, Tmp1);
1191 case ISD::TRUNCSTORE:
1192 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1193 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
1195 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1197 Tmp2 = LegalizeOp(Node->getOperand(1));
1199 // The only promote case we handle is TRUNCSTORE:i1 X into
1200 // -> TRUNCSTORE:i8 (and X, 1)
1201 if (cast<VTSDNode>(Node->getOperand(4))->getVT() == MVT::i1 &&
1202 TLI.getOperationAction(ISD::TRUNCSTORE, MVT::i1) ==
1203 TargetLowering::Promote) {
1204 // Promote the bool to a mask then store.
1205 Tmp2 = DAG.getNode(ISD::AND, Tmp2.getValueType(), Tmp2,
1206 DAG.getConstant(1, Tmp2.getValueType()));
1207 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3,
1208 Node->getOperand(3), DAG.getValueType(MVT::i8));
1210 } else if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1211 Tmp3 != Node->getOperand(2)) {
1212 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3,
1213 Node->getOperand(3), Node->getOperand(4));
1218 assert(0 && "Cannot handle illegal TRUNCSTORE yet!");
1222 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1223 case Expand: assert(0 && "It's impossible to expand bools");
1225 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
1228 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
1231 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
1232 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
1234 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
1235 default: assert(0 && "This action is not supported yet!");
1236 case TargetLowering::Expand:
1237 if (Tmp1.getOpcode() == ISD::SETCC) {
1238 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
1240 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
1242 // Make sure the condition is either zero or one. It may have been
1243 // promoted from something else.
1244 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
1245 Result = DAG.getSelectCC(Tmp1,
1246 DAG.getConstant(0, Tmp1.getValueType()),
1247 Tmp2, Tmp3, ISD::SETNE);
1250 case TargetLowering::Legal:
1251 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1252 Tmp3 != Node->getOperand(2))
1253 Result = DAG.getNode(ISD::SELECT, Node->getValueType(0),
1256 case TargetLowering::Promote: {
1257 MVT::ValueType NVT =
1258 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
1259 unsigned ExtOp, TruncOp;
1260 if (MVT::isInteger(Tmp2.getValueType())) {
1261 ExtOp = ISD::ANY_EXTEND;
1262 TruncOp = ISD::TRUNCATE;
1264 ExtOp = ISD::FP_EXTEND;
1265 TruncOp = ISD::FP_ROUND;
1267 // Promote each of the values to the new type.
1268 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
1269 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
1270 // Perform the larger operation, then round down.
1271 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
1272 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
1277 case ISD::SELECT_CC:
1278 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
1279 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
1281 if (isTypeLegal(Node->getOperand(0).getValueType())) {
1282 // Everything is legal, see if we should expand this op or something.
1283 switch (TLI.getOperationAction(ISD::SELECT_CC,
1284 Node->getOperand(0).getValueType())) {
1285 default: assert(0 && "This action is not supported yet!");
1286 case TargetLowering::Custom: {
1288 TLI.LowerOperation(DAG.getNode(ISD::SELECT_CC, Node->getValueType(0),
1289 Node->getOperand(0),
1290 Node->getOperand(1), Tmp3, Tmp4,
1291 Node->getOperand(4)), DAG);
1293 Result = LegalizeOp(Tmp);
1296 } // FALLTHROUGH if the target can't lower this operation after all.
1297 case TargetLowering::Legal:
1298 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
1299 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
1300 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1301 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3)) {
1302 Result = DAG.getNode(ISD::SELECT_CC, Node->getValueType(0), Tmp1, Tmp2,
1303 Tmp3, Tmp4, Node->getOperand(4));
1309 Tmp1 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),
1310 Node->getOperand(0), // LHS
1311 Node->getOperand(1), // RHS
1312 Node->getOperand(4)));
1313 // If we get a SETCC back from legalizing the SETCC node we just
1314 // created, then use its LHS, RHS, and CC directly in creating a new
1315 // node. Otherwise, select between the true and false value based on
1316 // comparing the result of the legalized with zero.
1317 if (Tmp1.getOpcode() == ISD::SETCC) {
1318 Result = DAG.getNode(ISD::SELECT_CC, Tmp3.getValueType(),
1319 Tmp1.getOperand(0), Tmp1.getOperand(1),
1320 Tmp3, Tmp4, Tmp1.getOperand(2));
1322 Result = DAG.getSelectCC(Tmp1,
1323 DAG.getConstant(0, Tmp1.getValueType()),
1324 Tmp3, Tmp4, ISD::SETNE);
1329 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1331 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
1332 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
1335 Tmp1 = PromoteOp(Node->getOperand(0)); // LHS
1336 Tmp2 = PromoteOp(Node->getOperand(1)); // RHS
1338 // If this is an FP compare, the operands have already been extended.
1339 if (MVT::isInteger(Node->getOperand(0).getValueType())) {
1340 MVT::ValueType VT = Node->getOperand(0).getValueType();
1341 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
1343 // Otherwise, we have to insert explicit sign or zero extends. Note
1344 // that we could insert sign extends for ALL conditions, but zero extend
1345 // is cheaper on many machines (an AND instead of two shifts), so prefer
1347 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) {
1348 default: assert(0 && "Unknown integer comparison!");
1355 // ALL of these operations will work if we either sign or zero extend
1356 // the operands (including the unsigned comparisons!). Zero extend is
1357 // usually a simpler/cheaper operation, so prefer it.
1358 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
1359 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
1365 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
1366 DAG.getValueType(VT));
1367 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
1368 DAG.getValueType(VT));
1374 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
1375 ExpandOp(Node->getOperand(0), LHSLo, LHSHi);
1376 ExpandOp(Node->getOperand(1), RHSLo, RHSHi);
1377 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) {
1381 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
1382 if (RHSCST->isAllOnesValue()) {
1383 // Comparison to -1.
1384 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
1389 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
1390 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
1391 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
1392 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
1395 // If this is a comparison of the sign bit, just look at the top part.
1397 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Node->getOperand(1)))
1398 if ((cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETLT &&
1399 CST->getValue() == 0) || // X < 0
1400 (cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETGT &&
1401 (CST->isAllOnesValue()))) { // X > -1
1407 // FIXME: This generated code sucks.
1408 ISD::CondCode LowCC;
1409 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) {
1410 default: assert(0 && "Unknown integer setcc!");
1412 case ISD::SETULT: LowCC = ISD::SETULT; break;
1414 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
1416 case ISD::SETULE: LowCC = ISD::SETULE; break;
1418 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
1421 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
1422 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
1423 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
1425 // NOTE: on targets without efficient SELECT of bools, we can always use
1426 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
1427 Tmp1 = DAG.getSetCC(Node->getValueType(0), LHSLo, RHSLo, LowCC);
1428 Tmp2 = DAG.getNode(ISD::SETCC, Node->getValueType(0), LHSHi, RHSHi,
1429 Node->getOperand(2));
1430 Result = DAG.getSetCC(Node->getValueType(0), LHSHi, RHSHi, ISD::SETEQ);
1431 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
1432 Result, Tmp1, Tmp2));
1437 switch(TLI.getOperationAction(ISD::SETCC, Node->getOperand(0).getValueType())) {
1439 assert(0 && "Cannot handle this action for SETCC yet!");
1441 case TargetLowering::Promote:
1442 Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2,
1443 Node->getOperand(2));
1445 case TargetLowering::Legal:
1446 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
1447 Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2,
1448 Node->getOperand(2));
1450 case TargetLowering::Expand:
1451 // Expand a setcc node into a select_cc of the same condition, lhs, and
1452 // rhs that selects between const 1 (true) and const 0 (false).
1453 MVT::ValueType VT = Node->getValueType(0);
1454 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
1455 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
1456 Node->getOperand(2));
1457 Result = LegalizeOp(Result);
1464 case ISD::MEMMOVE: {
1465 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
1466 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
1468 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
1469 switch (getTypeAction(Node->getOperand(2).getValueType())) {
1470 case Expand: assert(0 && "Cannot expand a byte!");
1472 Tmp3 = LegalizeOp(Node->getOperand(2));
1475 Tmp3 = PromoteOp(Node->getOperand(2));
1479 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
1483 switch (getTypeAction(Node->getOperand(3).getValueType())) {
1485 // Length is too big, just take the lo-part of the length.
1487 ExpandOp(Node->getOperand(3), HiPart, Tmp4);
1491 Tmp4 = LegalizeOp(Node->getOperand(3));
1494 Tmp4 = PromoteOp(Node->getOperand(3));
1499 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
1500 case Expand: assert(0 && "Cannot expand this yet!");
1502 Tmp5 = LegalizeOp(Node->getOperand(4));
1505 Tmp5 = PromoteOp(Node->getOperand(4));
1509 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
1510 default: assert(0 && "This action not implemented for this operation!");
1511 case TargetLowering::Custom: {
1513 TLI.LowerOperation(DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1,
1514 Tmp2, Tmp3, Tmp4, Tmp5), DAG);
1516 Result = LegalizeOp(Tmp);
1519 // FALLTHROUGH if the target thinks it is legal.
1521 case TargetLowering::Legal:
1522 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1523 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3) ||
1524 Tmp5 != Node->getOperand(4)) {
1525 std::vector<SDOperand> Ops;
1526 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3);
1527 Ops.push_back(Tmp4); Ops.push_back(Tmp5);
1528 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Ops);
1531 case TargetLowering::Expand: {
1532 // Otherwise, the target does not support this operation. Lower the
1533 // operation to an explicit libcall as appropriate.
1534 MVT::ValueType IntPtr = TLI.getPointerTy();
1535 const Type *IntPtrTy = TLI.getTargetData().getIntPtrType();
1536 std::vector<std::pair<SDOperand, const Type*> > Args;
1538 const char *FnName = 0;
1539 if (Node->getOpcode() == ISD::MEMSET) {
1540 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
1541 // Extend the ubyte argument to be an int value for the call.
1542 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
1543 Args.push_back(std::make_pair(Tmp3, Type::IntTy));
1544 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
1547 } else if (Node->getOpcode() == ISD::MEMCPY ||
1548 Node->getOpcode() == ISD::MEMMOVE) {
1549 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
1550 Args.push_back(std::make_pair(Tmp3, IntPtrTy));
1551 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
1552 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
1554 assert(0 && "Unknown op!");
1557 std::pair<SDOperand,SDOperand> CallResult =
1558 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, CallingConv::C, false,
1559 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
1560 Result = CallResult.second;
1561 NeedsAnotherIteration = true;
1569 Tmp1 = LegalizeOp(Node->getOperand(0));
1570 Tmp2 = LegalizeOp(Node->getOperand(1));
1572 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) {
1573 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end());
1574 std::vector<SDOperand> Ops;
1575 Ops.push_back(Tmp1);
1576 Ops.push_back(Tmp2);
1577 Result = DAG.getNode(ISD::READPORT, VTs, Ops);
1579 Result = SDOperand(Node, 0);
1580 // Since these produce two values, make sure to remember that we legalized
1582 AddLegalizedOperand(SDOperand(Node, 0), Result);
1583 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1584 return Result.getValue(Op.ResNo);
1585 case ISD::WRITEPORT:
1586 Tmp1 = LegalizeOp(Node->getOperand(0));
1587 Tmp2 = LegalizeOp(Node->getOperand(1));
1588 Tmp3 = LegalizeOp(Node->getOperand(2));
1589 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1590 Tmp3 != Node->getOperand(2))
1591 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3);
1595 Tmp1 = LegalizeOp(Node->getOperand(0));
1596 Tmp2 = LegalizeOp(Node->getOperand(1));
1598 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1599 case TargetLowering::Custom:
1600 default: assert(0 && "This action not implemented for this operation!");
1601 case TargetLowering::Legal:
1602 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) {
1603 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end());
1604 std::vector<SDOperand> Ops;
1605 Ops.push_back(Tmp1);
1606 Ops.push_back(Tmp2);
1607 Result = DAG.getNode(ISD::READPORT, VTs, Ops);
1609 Result = SDOperand(Node, 0);
1611 case TargetLowering::Expand:
1612 // Replace this with a load from memory.
1613 Result = DAG.getLoad(Node->getValueType(0), Node->getOperand(0),
1614 Node->getOperand(1), DAG.getSrcValue(NULL));
1615 Result = LegalizeOp(Result);
1619 // Since these produce two values, make sure to remember that we legalized
1621 AddLegalizedOperand(SDOperand(Node, 0), Result);
1622 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1623 return Result.getValue(Op.ResNo);
1626 Tmp1 = LegalizeOp(Node->getOperand(0));
1627 Tmp2 = LegalizeOp(Node->getOperand(1));
1628 Tmp3 = LegalizeOp(Node->getOperand(2));
1630 switch (TLI.getOperationAction(Node->getOpcode(),
1631 Node->getOperand(1).getValueType())) {
1632 case TargetLowering::Custom:
1633 default: assert(0 && "This action not implemented for this operation!");
1634 case TargetLowering::Legal:
1635 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1636 Tmp3 != Node->getOperand(2))
1637 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3);
1639 case TargetLowering::Expand:
1640 // Replace this with a store to memory.
1641 Result = DAG.getNode(ISD::STORE, MVT::Other, Node->getOperand(0),
1642 Node->getOperand(1), Node->getOperand(2),
1643 DAG.getSrcValue(NULL));
1644 Result = LegalizeOp(Result);
1649 case ISD::ADD_PARTS:
1650 case ISD::SUB_PARTS:
1651 case ISD::SHL_PARTS:
1652 case ISD::SRA_PARTS:
1653 case ISD::SRL_PARTS: {
1654 std::vector<SDOperand> Ops;
1655 bool Changed = false;
1656 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1657 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1658 Changed |= Ops.back() != Node->getOperand(i);
1661 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end());
1662 Result = DAG.getNode(Node->getOpcode(), VTs, Ops);
1665 // Since these produce multiple values, make sure to remember that we
1666 // legalized all of them.
1667 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1668 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
1669 return Result.getValue(Op.ResNo);
1690 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
1691 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1692 case Expand: assert(0 && "Not possible");
1694 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
1697 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
1700 if (Tmp1 != Node->getOperand(0) ||
1701 Tmp2 != Node->getOperand(1))
1702 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,Tmp2);
1705 case ISD::BUILD_PAIR: {
1706 MVT::ValueType PairTy = Node->getValueType(0);
1707 // TODO: handle the case where the Lo and Hi operands are not of legal type
1708 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
1709 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
1710 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
1711 case TargetLowering::Legal:
1712 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
1713 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
1715 case TargetLowering::Promote:
1716 case TargetLowering::Custom:
1717 assert(0 && "Cannot promote/custom this yet!");
1718 case TargetLowering::Expand:
1719 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
1720 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
1721 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
1722 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
1723 TLI.getShiftAmountTy()));
1724 Result = LegalizeOp(DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2));
1733 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
1734 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
1735 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1736 case TargetLowering::Legal:
1737 if (Tmp1 != Node->getOperand(0) ||
1738 Tmp2 != Node->getOperand(1))
1739 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,
1742 case TargetLowering::Promote:
1743 case TargetLowering::Custom:
1744 assert(0 && "Cannot promote/custom handle this yet!");
1745 case TargetLowering::Expand:
1746 if (MVT::isInteger(Node->getValueType(0))) {
1747 MVT::ValueType VT = Node->getValueType(0);
1748 unsigned Opc = (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
1749 Result = DAG.getNode(Opc, VT, Tmp1, Tmp2);
1750 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
1751 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
1753 // Floating point mod -> fmod libcall.
1754 const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod";
1756 Result = ExpandLibCall(FnName, Node, Dummy);
1765 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
1766 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1767 case TargetLowering::Legal:
1768 if (Tmp1 != Node->getOperand(0))
1769 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
1771 case TargetLowering::Promote: {
1772 MVT::ValueType OVT = Tmp1.getValueType();
1773 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1775 // Zero extend the argument.
1776 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
1777 // Perform the larger operation, then subtract if needed.
1778 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
1779 switch(Node->getOpcode())
1785 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
1786 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
1787 DAG.getConstant(getSizeInBits(NVT), NVT),
1789 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
1790 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1);
1793 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
1794 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
1795 DAG.getConstant(getSizeInBits(NVT) -
1796 getSizeInBits(OVT), NVT));
1801 case TargetLowering::Custom:
1802 assert(0 && "Cannot custom handle this yet!");
1803 case TargetLowering::Expand:
1804 switch(Node->getOpcode())
1807 static const uint64_t mask[6] = {
1808 0x5555555555555555ULL, 0x3333333333333333ULL,
1809 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
1810 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
1812 MVT::ValueType VT = Tmp1.getValueType();
1813 MVT::ValueType ShVT = TLI.getShiftAmountTy();
1814 unsigned len = getSizeInBits(VT);
1815 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
1816 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
1817 Tmp2 = DAG.getConstant(mask[i], VT);
1818 Tmp3 = DAG.getConstant(1ULL << i, ShVT);
1819 Tmp1 = DAG.getNode(ISD::ADD, VT,
1820 DAG.getNode(ISD::AND, VT, Tmp1, Tmp2),
1821 DAG.getNode(ISD::AND, VT,
1822 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3),
1829 /* for now, we do this:
1834 x = x | (x >>32); // for 64-bit input
1835 return popcount(~x);
1837 but see also: http://www.hackersdelight.org/HDcode/nlz.cc */
1838 MVT::ValueType VT = Tmp1.getValueType();
1839 MVT::ValueType ShVT = TLI.getShiftAmountTy();
1840 unsigned len = getSizeInBits(VT);
1841 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
1842 Tmp3 = DAG.getConstant(1ULL << i, ShVT);
1843 Tmp1 = DAG.getNode(ISD::OR, VT, Tmp1,
1844 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3));
1846 Tmp3 = DAG.getNode(ISD::XOR, VT, Tmp1, DAG.getConstant(~0ULL, VT));
1847 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3));
1851 // for now, we use: { return popcount(~x & (x - 1)); }
1852 // unless the target has ctlz but not ctpop, in which case we use:
1853 // { return 32 - nlz(~x & (x-1)); }
1854 // see also http://www.hackersdelight.org/HDcode/ntz.cc
1855 MVT::ValueType VT = Tmp1.getValueType();
1856 Tmp2 = DAG.getConstant(~0ULL, VT);
1857 Tmp3 = DAG.getNode(ISD::AND, VT,
1858 DAG.getNode(ISD::XOR, VT, Tmp1, Tmp2),
1859 DAG.getNode(ISD::SUB, VT, Tmp1,
1860 DAG.getConstant(1, VT)));
1861 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead
1862 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
1863 TLI.isOperationLegal(ISD::CTLZ, VT)) {
1864 Result = LegalizeOp(DAG.getNode(ISD::SUB, VT,
1865 DAG.getConstant(getSizeInBits(VT), VT),
1866 DAG.getNode(ISD::CTLZ, VT, Tmp3)));
1868 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3));
1873 assert(0 && "Cannot expand this yet!");
1886 Tmp1 = LegalizeOp(Node->getOperand(0));
1887 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1888 case TargetLowering::Legal:
1889 if (Tmp1 != Node->getOperand(0))
1890 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
1892 case TargetLowering::Promote:
1893 case TargetLowering::Custom:
1894 assert(0 && "Cannot promote/custom handle this yet!");
1895 case TargetLowering::Expand:
1896 switch(Node->getOpcode()) {
1898 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
1899 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
1900 Result = LegalizeOp(DAG.getNode(ISD::FSUB, Node->getValueType(0),
1905 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
1906 MVT::ValueType VT = Node->getValueType(0);
1907 Tmp2 = DAG.getConstantFP(0.0, VT);
1908 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
1909 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
1910 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
1911 Result = LegalizeOp(Result);
1917 MVT::ValueType VT = Node->getValueType(0);
1918 const char *FnName = 0;
1919 switch(Node->getOpcode()) {
1920 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break;
1921 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break;
1922 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break;
1923 default: assert(0 && "Unreachable!");
1926 Result = ExpandLibCall(FnName, Node, Dummy);
1930 assert(0 && "Unreachable!");
1936 // Conversion operators. The source and destination have different types.
1937 case ISD::SINT_TO_FP:
1938 case ISD::UINT_TO_FP: {
1939 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
1940 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1942 switch (TLI.getOperationAction(Node->getOpcode(),
1943 Node->getOperand(0).getValueType())) {
1944 default: assert(0 && "Unknown operation action!");
1945 case TargetLowering::Expand:
1946 Result = ExpandLegalINT_TO_FP(isSigned,
1947 LegalizeOp(Node->getOperand(0)),
1948 Node->getValueType(0));
1949 AddLegalizedOperand(Op, Result);
1951 case TargetLowering::Promote:
1952 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
1953 Node->getValueType(0),
1955 AddLegalizedOperand(Op, Result);
1957 case TargetLowering::Legal:
1961 Tmp1 = LegalizeOp(Node->getOperand(0));
1962 if (Tmp1 != Node->getOperand(0))
1963 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
1966 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
1967 Node->getValueType(0), Node->getOperand(0));
1971 Result = PromoteOp(Node->getOperand(0));
1972 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1973 Result, DAG.getValueType(Node->getOperand(0).getValueType()));
1974 Result = DAG.getNode(ISD::SINT_TO_FP, Op.getValueType(), Result);
1976 Result = PromoteOp(Node->getOperand(0));
1977 Result = DAG.getZeroExtendInReg(Result,
1978 Node->getOperand(0).getValueType());
1979 Result = DAG.getNode(ISD::UINT_TO_FP, Op.getValueType(), Result);
1986 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1988 Tmp1 = LegalizeOp(Node->getOperand(0));
1989 if (Tmp1 != Node->getOperand(0))
1990 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
1993 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1995 // Since the result is legal, we should just be able to truncate the low
1996 // part of the source.
1997 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
2000 Result = PromoteOp(Node->getOperand(0));
2001 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
2006 case ISD::FP_TO_SINT:
2007 case ISD::FP_TO_UINT:
2008 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2010 Tmp1 = LegalizeOp(Node->getOperand(0));
2012 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
2013 default: assert(0 && "Unknown operation action!");
2014 case TargetLowering::Expand:
2015 if (Node->getOpcode() == ISD::FP_TO_UINT) {
2016 SDOperand True, False;
2017 MVT::ValueType VT = Node->getOperand(0).getValueType();
2018 MVT::ValueType NVT = Node->getValueType(0);
2019 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1;
2020 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT);
2021 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
2022 Node->getOperand(0), Tmp2, ISD::SETLT);
2023 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
2024 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
2025 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
2027 False = DAG.getNode(ISD::XOR, NVT, False,
2028 DAG.getConstant(1ULL << ShiftAmt, NVT));
2029 Result = LegalizeOp(DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False));
2032 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
2035 case TargetLowering::Promote:
2036 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
2037 Node->getOpcode() == ISD::FP_TO_SINT);
2038 AddLegalizedOperand(Op, Result);
2040 case TargetLowering::Custom: {
2042 DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2043 Tmp = TLI.LowerOperation(Tmp, DAG);
2045 AddLegalizedOperand(Op, Tmp);
2046 NeedsAnotherIteration = true;
2049 // The target thinks this is legal afterall.
2053 case TargetLowering::Legal:
2057 if (Tmp1 != Node->getOperand(0))
2058 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2061 assert(0 && "Shouldn't need to expand other operators here!");
2063 Result = PromoteOp(Node->getOperand(0));
2064 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
2069 case ISD::ANY_EXTEND:
2070 case ISD::ZERO_EXTEND:
2071 case ISD::SIGN_EXTEND:
2072 case ISD::FP_EXTEND:
2074 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2076 Tmp1 = LegalizeOp(Node->getOperand(0));
2077 if (Tmp1 != Node->getOperand(0))
2078 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2081 assert(0 && "Shouldn't need to expand other operators here!");
2084 switch (Node->getOpcode()) {
2085 case ISD::ANY_EXTEND:
2086 Result = PromoteOp(Node->getOperand(0));
2087 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2089 case ISD::ZERO_EXTEND:
2090 Result = PromoteOp(Node->getOperand(0));
2091 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2092 Result = DAG.getZeroExtendInReg(Result,
2093 Node->getOperand(0).getValueType());
2095 case ISD::SIGN_EXTEND:
2096 Result = PromoteOp(Node->getOperand(0));
2097 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2098 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2100 DAG.getValueType(Node->getOperand(0).getValueType()));
2102 case ISD::FP_EXTEND:
2103 Result = PromoteOp(Node->getOperand(0));
2104 if (Result.getValueType() != Op.getValueType())
2105 // Dynamically dead while we have only 2 FP types.
2106 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result);
2109 Result = PromoteOp(Node->getOperand(0));
2110 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
2115 case ISD::FP_ROUND_INREG:
2116 case ISD::SIGN_EXTEND_INREG: {
2117 Tmp1 = LegalizeOp(Node->getOperand(0));
2118 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2120 // If this operation is not supported, convert it to a shl/shr or load/store
2122 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
2123 default: assert(0 && "This action not supported for this op yet!");
2124 case TargetLowering::Legal:
2125 if (Tmp1 != Node->getOperand(0))
2126 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,
2127 DAG.getValueType(ExtraVT));
2129 case TargetLowering::Expand:
2130 // If this is an integer extend and shifts are supported, do that.
2131 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
2132 // NOTE: we could fall back on load/store here too for targets without
2133 // SAR. However, it is doubtful that any exist.
2134 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
2135 MVT::getSizeInBits(ExtraVT);
2136 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
2137 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
2138 Node->getOperand(0), ShiftCst);
2139 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
2141 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
2142 // The only way we can lower this is to turn it into a STORETRUNC,
2143 // EXTLOAD pair, targetting a temporary location (a stack slot).
2145 // NOTE: there is a choice here between constantly creating new stack
2146 // slots and always reusing the same one. We currently always create
2147 // new ones, as reuse may inhibit scheduling.
2148 const Type *Ty = MVT::getTypeForValueType(ExtraVT);
2149 unsigned TySize = (unsigned)TLI.getTargetData().getTypeSize(Ty);
2150 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty);
2151 MachineFunction &MF = DAG.getMachineFunction();
2153 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
2154 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
2155 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(),
2156 Node->getOperand(0), StackSlot,
2157 DAG.getSrcValue(NULL), DAG.getValueType(ExtraVT));
2158 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2159 Result, StackSlot, DAG.getSrcValue(NULL),
2162 assert(0 && "Unknown op");
2164 Result = LegalizeOp(Result);
2171 // Note that LegalizeOp may be reentered even from single-use nodes, which
2172 // means that we always must cache transformed nodes.
2173 AddLegalizedOperand(Op, Result);
2177 /// PromoteOp - Given an operation that produces a value in an invalid type,
2178 /// promote it to compute the value into a larger type. The produced value will
2179 /// have the correct bits for the low portion of the register, but no guarantee
2180 /// is made about the top bits: it may be zero, sign-extended, or garbage.
2181 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
2182 MVT::ValueType VT = Op.getValueType();
2183 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
2184 assert(getTypeAction(VT) == Promote &&
2185 "Caller should expand or legalize operands that are not promotable!");
2186 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
2187 "Cannot promote to smaller type!");
2189 SDOperand Tmp1, Tmp2, Tmp3;
2192 SDNode *Node = Op.Val;
2194 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
2195 if (I != PromotedNodes.end()) return I->second;
2197 // Promotion needs an optimization step to clean up after it, and is not
2198 // careful to avoid operations the target does not support. Make sure that
2199 // all generated operations are legalized in the next iteration.
2200 NeedsAnotherIteration = true;
2202 switch (Node->getOpcode()) {
2203 case ISD::CopyFromReg:
2204 assert(0 && "CopyFromReg must be legal!");
2206 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
2207 assert(0 && "Do not know how to promote this operator!");
2210 Result = DAG.getNode(ISD::UNDEF, NVT);
2214 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
2216 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
2217 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
2219 case ISD::ConstantFP:
2220 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
2221 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
2225 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
2226 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
2227 Node->getOperand(1), Node->getOperand(2));
2228 Result = LegalizeOp(Result);
2232 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2234 Result = LegalizeOp(Node->getOperand(0));
2235 assert(Result.getValueType() >= NVT &&
2236 "This truncation doesn't make sense!");
2237 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
2238 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
2241 // The truncation is not required, because we don't guarantee anything
2242 // about high bits anyway.
2243 Result = PromoteOp(Node->getOperand(0));
2246 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2247 // Truncate the low part of the expanded value to the result type
2248 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
2251 case ISD::SIGN_EXTEND:
2252 case ISD::ZERO_EXTEND:
2253 case ISD::ANY_EXTEND:
2254 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2255 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
2257 // Input is legal? Just do extend all the way to the larger type.
2258 Result = LegalizeOp(Node->getOperand(0));
2259 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
2262 // Promote the reg if it's smaller.
2263 Result = PromoteOp(Node->getOperand(0));
2264 // The high bits are not guaranteed to be anything. Insert an extend.
2265 if (Node->getOpcode() == ISD::SIGN_EXTEND)
2266 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
2267 DAG.getValueType(Node->getOperand(0).getValueType()));
2268 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
2269 Result = DAG.getZeroExtendInReg(Result,
2270 Node->getOperand(0).getValueType());
2275 case ISD::FP_EXTEND:
2276 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
2278 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2279 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
2280 case Promote: assert(0 && "Unreachable with 2 FP types!");
2282 // Input is legal? Do an FP_ROUND_INREG.
2283 Result = LegalizeOp(Node->getOperand(0));
2284 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2285 DAG.getValueType(VT));
2290 case ISD::SINT_TO_FP:
2291 case ISD::UINT_TO_FP:
2292 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2294 Result = LegalizeOp(Node->getOperand(0));
2295 // No extra round required here.
2296 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
2300 Result = PromoteOp(Node->getOperand(0));
2301 if (Node->getOpcode() == ISD::SINT_TO_FP)
2302 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2304 DAG.getValueType(Node->getOperand(0).getValueType()));
2306 Result = DAG.getZeroExtendInReg(Result,
2307 Node->getOperand(0).getValueType());
2308 // No extra round required here.
2309 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
2312 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
2313 Node->getOperand(0));
2314 // Round if we cannot tolerate excess precision.
2315 if (NoExcessFPPrecision)
2316 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2317 DAG.getValueType(VT));
2322 case ISD::FP_TO_SINT:
2323 case ISD::FP_TO_UINT:
2324 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2326 Tmp1 = LegalizeOp(Node->getOperand(0));
2329 // The input result is prerounded, so we don't have to do anything
2331 Tmp1 = PromoteOp(Node->getOperand(0));
2334 assert(0 && "not implemented");
2336 // If we're promoting a UINT to a larger size, check to see if the new node
2337 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
2338 // we can use that instead. This allows us to generate better code for
2339 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
2340 // legal, such as PowerPC.
2341 if (Node->getOpcode() == ISD::FP_TO_UINT &&
2342 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
2343 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
2344 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
2345 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
2347 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2353 Tmp1 = PromoteOp(Node->getOperand(0));
2354 assert(Tmp1.getValueType() == NVT);
2355 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2356 // NOTE: we do not have to do any extra rounding here for
2357 // NoExcessFPPrecision, because we know the input will have the appropriate
2358 // precision, and these operations don't modify precision at all.
2364 Tmp1 = PromoteOp(Node->getOperand(0));
2365 assert(Tmp1.getValueType() == NVT);
2366 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2367 if(NoExcessFPPrecision)
2368 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2369 DAG.getValueType(VT));
2378 // The input may have strange things in the top bits of the registers, but
2379 // these operations don't care. They may have weird bits going out, but
2380 // that too is okay if they are integer operations.
2381 Tmp1 = PromoteOp(Node->getOperand(0));
2382 Tmp2 = PromoteOp(Node->getOperand(1));
2383 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
2384 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2389 // The input may have strange things in the top bits of the registers, but
2390 // these operations don't care.
2391 Tmp1 = PromoteOp(Node->getOperand(0));
2392 Tmp2 = PromoteOp(Node->getOperand(1));
2393 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
2394 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2396 // Floating point operations will give excess precision that we may not be
2397 // able to tolerate. If we DO allow excess precision, just leave it,
2398 // otherwise excise it.
2399 // FIXME: Why would we need to round FP ops more than integer ones?
2400 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
2401 if (NoExcessFPPrecision)
2402 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2403 DAG.getValueType(VT));
2408 // These operators require that their input be sign extended.
2409 Tmp1 = PromoteOp(Node->getOperand(0));
2410 Tmp2 = PromoteOp(Node->getOperand(1));
2411 if (MVT::isInteger(NVT)) {
2412 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
2413 DAG.getValueType(VT));
2414 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
2415 DAG.getValueType(VT));
2417 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2419 // Perform FP_ROUND: this is probably overly pessimistic.
2420 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
2421 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2422 DAG.getValueType(VT));
2426 // These operators require that their input be fp extended.
2427 Tmp1 = PromoteOp(Node->getOperand(0));
2428 Tmp2 = PromoteOp(Node->getOperand(1));
2429 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2431 // Perform FP_ROUND: this is probably overly pessimistic.
2432 if (NoExcessFPPrecision)
2433 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2434 DAG.getValueType(VT));
2439 // These operators require that their input be zero extended.
2440 Tmp1 = PromoteOp(Node->getOperand(0));
2441 Tmp2 = PromoteOp(Node->getOperand(1));
2442 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
2443 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
2444 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
2445 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2449 Tmp1 = PromoteOp(Node->getOperand(0));
2450 Tmp2 = LegalizeOp(Node->getOperand(1));
2451 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Tmp2);
2454 // The input value must be properly sign extended.
2455 Tmp1 = PromoteOp(Node->getOperand(0));
2456 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
2457 DAG.getValueType(VT));
2458 Tmp2 = LegalizeOp(Node->getOperand(1));
2459 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Tmp2);
2462 // The input value must be properly zero extended.
2463 Tmp1 = PromoteOp(Node->getOperand(0));
2464 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
2465 Tmp2 = LegalizeOp(Node->getOperand(1));
2466 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Tmp2);
2469 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2470 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2471 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp1, Tmp2,
2472 Node->getOperand(2), VT);
2473 // Remember that we legalized the chain.
2474 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
2479 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2480 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2481 Result = DAG.getExtLoad(Node->getOpcode(), NVT, Tmp1, Tmp2,
2482 Node->getOperand(2),
2483 cast<VTSDNode>(Node->getOperand(3))->getVT());
2484 // Remember that we legalized the chain.
2485 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
2488 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2489 case Expand: assert(0 && "It's impossible to expand bools");
2491 Tmp1 = LegalizeOp(Node->getOperand(0));// Legalize the condition.
2494 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2497 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
2498 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
2499 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2, Tmp3);
2501 case ISD::SELECT_CC:
2502 Tmp2 = PromoteOp(Node->getOperand(2)); // True
2503 Tmp3 = PromoteOp(Node->getOperand(3)); // False
2504 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
2505 Node->getOperand(1), Tmp2, Tmp3,
2506 Node->getOperand(4));
2510 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2511 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee.
2513 std::vector<SDOperand> Ops;
2514 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i)
2515 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2517 assert(Node->getNumValues() == 2 && Op.ResNo == 0 &&
2518 "Can only promote single result calls");
2519 std::vector<MVT::ValueType> RetTyVTs;
2520 RetTyVTs.reserve(2);
2521 RetTyVTs.push_back(NVT);
2522 RetTyVTs.push_back(MVT::Other);
2523 SDNode *NC = DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops,
2524 Node->getOpcode() == ISD::TAILCALL);
2525 Result = SDOperand(NC, 0);
2527 // Insert the new chain mapping.
2528 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
2534 Tmp1 = Node->getOperand(0);
2535 //Zero extend the argument
2536 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2537 // Perform the larger operation, then subtract if needed.
2538 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2539 switch(Node->getOpcode())
2545 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2546 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
2547 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ);
2548 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
2549 DAG.getConstant(getSizeInBits(VT),NVT), Tmp1);
2552 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2553 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
2554 DAG.getConstant(getSizeInBits(NVT) -
2555 getSizeInBits(VT), NVT));
2561 assert(Result.Val && "Didn't set a result!");
2562 AddPromotedOperand(Op, Result);
2566 /// ExpandAddSub - Find a clever way to expand this add operation into
2568 void SelectionDAGLegalize::
2569 ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS,
2570 SDOperand &Lo, SDOperand &Hi) {
2571 // Expand the subcomponents.
2572 SDOperand LHSL, LHSH, RHSL, RHSH;
2573 ExpandOp(LHS, LHSL, LHSH);
2574 ExpandOp(RHS, RHSL, RHSH);
2576 std::vector<SDOperand> Ops;
2577 Ops.push_back(LHSL);
2578 Ops.push_back(LHSH);
2579 Ops.push_back(RHSL);
2580 Ops.push_back(RHSH);
2581 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType());
2582 Lo = DAG.getNode(NodeOp, VTs, Ops);
2583 Hi = Lo.getValue(1);
2586 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
2587 SDOperand Op, SDOperand Amt,
2588 SDOperand &Lo, SDOperand &Hi) {
2589 // Expand the subcomponents.
2590 SDOperand LHSL, LHSH;
2591 ExpandOp(Op, LHSL, LHSH);
2593 std::vector<SDOperand> Ops;
2594 Ops.push_back(LHSL);
2595 Ops.push_back(LHSH);
2597 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType());
2598 Lo = DAG.getNode(NodeOp, VTs, Ops);
2599 Hi = Lo.getValue(1);
2603 /// ExpandShift - Try to find a clever way to expand this shift operation out to
2604 /// smaller elements. If we can't find a way that is more efficient than a
2605 /// libcall on this target, return false. Otherwise, return true with the
2606 /// low-parts expanded into Lo and Hi.
2607 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
2608 SDOperand &Lo, SDOperand &Hi) {
2609 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
2610 "This is not a shift!");
2612 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
2613 SDOperand ShAmt = LegalizeOp(Amt);
2614 MVT::ValueType ShTy = ShAmt.getValueType();
2615 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
2616 unsigned NVTBits = MVT::getSizeInBits(NVT);
2618 // Handle the case when Amt is an immediate. Other cases are currently broken
2619 // and are disabled.
2620 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
2621 unsigned Cst = CN->getValue();
2622 // Expand the incoming operand to be shifted, so that we have its parts
2624 ExpandOp(Op, InL, InH);
2628 Lo = DAG.getConstant(0, NVT);
2629 Hi = DAG.getConstant(0, NVT);
2630 } else if (Cst > NVTBits) {
2631 Lo = DAG.getConstant(0, NVT);
2632 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
2633 } else if (Cst == NVTBits) {
2634 Lo = DAG.getConstant(0, NVT);
2637 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
2638 Hi = DAG.getNode(ISD::OR, NVT,
2639 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
2640 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
2645 Lo = DAG.getConstant(0, NVT);
2646 Hi = DAG.getConstant(0, NVT);
2647 } else if (Cst > NVTBits) {
2648 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
2649 Hi = DAG.getConstant(0, NVT);
2650 } else if (Cst == NVTBits) {
2652 Hi = DAG.getConstant(0, NVT);
2654 Lo = DAG.getNode(ISD::OR, NVT,
2655 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
2656 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
2657 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
2662 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
2663 DAG.getConstant(NVTBits-1, ShTy));
2664 } else if (Cst > NVTBits) {
2665 Lo = DAG.getNode(ISD::SRA, NVT, InH,
2666 DAG.getConstant(Cst-NVTBits, ShTy));
2667 Hi = DAG.getNode(ISD::SRA, NVT, InH,
2668 DAG.getConstant(NVTBits-1, ShTy));
2669 } else if (Cst == NVTBits) {
2671 Hi = DAG.getNode(ISD::SRA, NVT, InH,
2672 DAG.getConstant(NVTBits-1, ShTy));
2674 Lo = DAG.getNode(ISD::OR, NVT,
2675 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
2676 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
2677 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
2682 // FIXME: The following code for expanding shifts using ISD::SELECT is buggy,
2683 // so disable it for now. Currently targets are handling this via SHL_PARTS
2687 // If we have an efficient select operation (or if the selects will all fold
2688 // away), lower to some complex code, otherwise just emit the libcall.
2689 if (!TLI.isOperationLegal(ISD::SELECT, NVT) && !isa<ConstantSDNode>(Amt))
2693 ExpandOp(Op, InL, InH);
2694 SDOperand NAmt = DAG.getNode(ISD::SUB, ShTy, // NAmt = 32-ShAmt
2695 DAG.getConstant(NVTBits, ShTy), ShAmt);
2697 // Compare the unmasked shift amount against 32.
2698 SDOperand Cond = DAG.getSetCC(TLI.getSetCCResultTy(), ShAmt,
2699 DAG.getConstant(NVTBits, ShTy), ISD::SETGE);
2701 if (TLI.getShiftAmountFlavor() != TargetLowering::Mask) {
2702 ShAmt = DAG.getNode(ISD::AND, ShTy, ShAmt, // ShAmt &= 31
2703 DAG.getConstant(NVTBits-1, ShTy));
2704 NAmt = DAG.getNode(ISD::AND, ShTy, NAmt, // NAmt &= 31
2705 DAG.getConstant(NVTBits-1, ShTy));
2708 if (Opc == ISD::SHL) {
2709 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << Amt) | (Lo >> NAmt)
2710 DAG.getNode(ISD::SHL, NVT, InH, ShAmt),
2711 DAG.getNode(ISD::SRL, NVT, InL, NAmt));
2712 SDOperand T2 = DAG.getNode(ISD::SHL, NVT, InL, ShAmt); // T2 = Lo << Amt&31
2714 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1);
2715 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, DAG.getConstant(0, NVT), T2);
2717 SDOperand HiLoPart = DAG.getNode(ISD::SELECT, NVT,
2718 DAG.getSetCC(TLI.getSetCCResultTy(), NAmt,
2719 DAG.getConstant(32, ShTy),
2721 DAG.getConstant(0, NVT),
2722 DAG.getNode(ISD::SHL, NVT, InH, NAmt));
2723 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << NAmt) | (Lo >> Amt)
2725 DAG.getNode(ISD::SRL, NVT, InL, ShAmt));
2726 SDOperand T2 = DAG.getNode(Opc, NVT, InH, ShAmt); // T2 = InH >> ShAmt&31
2729 if (Opc == ISD::SRA)
2730 HiPart = DAG.getNode(ISD::SRA, NVT, InH,
2731 DAG.getConstant(NVTBits-1, ShTy));
2733 HiPart = DAG.getConstant(0, NVT);
2734 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1);
2735 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, HiPart, T2);
2740 /// FindLatestCallSeqStart - Scan up the dag to find the latest (highest
2741 /// NodeDepth) node that is an CallSeqStart operation and occurs later than
2743 static void FindLatestCallSeqStart(SDNode *Node, SDNode *&Found) {
2744 if (Node->getNodeDepth() <= Found->getNodeDepth()) return;
2746 // If we found an CALLSEQ_START, we already know this node occurs later
2747 // than the Found node. Just remember this node and return.
2748 if (Node->getOpcode() == ISD::CALLSEQ_START) {
2753 // Otherwise, scan the operands of Node to see if any of them is a call.
2754 assert(Node->getNumOperands() != 0 &&
2755 "All leaves should have depth equal to the entry node!");
2756 for (unsigned i = 0, e = Node->getNumOperands()-1; i != e; ++i)
2757 FindLatestCallSeqStart(Node->getOperand(i).Val, Found);
2759 // Tail recurse for the last iteration.
2760 FindLatestCallSeqStart(Node->getOperand(Node->getNumOperands()-1).Val,
2765 /// FindEarliestCallSeqEnd - Scan down the dag to find the earliest (lowest
2766 /// NodeDepth) node that is an CallSeqEnd operation and occurs more recent
2768 static void FindEarliestCallSeqEnd(SDNode *Node, SDNode *&Found,
2769 std::set<SDNode*> &Visited) {
2770 if ((Found && Node->getNodeDepth() >= Found->getNodeDepth()) ||
2771 !Visited.insert(Node).second) return;
2773 // If we found an CALLSEQ_END, we already know this node occurs earlier
2774 // than the Found node. Just remember this node and return.
2775 if (Node->getOpcode() == ISD::CALLSEQ_END) {
2780 // Otherwise, scan the operands of Node to see if any of them is a call.
2781 SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
2782 if (UI == E) return;
2783 for (--E; UI != E; ++UI)
2784 FindEarliestCallSeqEnd(*UI, Found, Visited);
2786 // Tail recurse for the last iteration.
2787 FindEarliestCallSeqEnd(*UI, Found, Visited);
2790 /// FindCallSeqEnd - Given a chained node that is part of a call sequence,
2791 /// find the CALLSEQ_END node that terminates the call sequence.
2792 static SDNode *FindCallSeqEnd(SDNode *Node) {
2793 if (Node->getOpcode() == ISD::CALLSEQ_END)
2795 if (Node->use_empty())
2796 return 0; // No CallSeqEnd
2798 SDOperand TheChain(Node, Node->getNumValues()-1);
2799 if (TheChain.getValueType() != MVT::Other)
2800 TheChain = SDOperand(Node, 0);
2801 if (TheChain.getValueType() != MVT::Other)
2804 for (SDNode::use_iterator UI = Node->use_begin(),
2805 E = Node->use_end(); UI != E; ++UI) {
2807 // Make sure to only follow users of our token chain.
2809 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
2810 if (User->getOperand(i) == TheChain)
2811 if (SDNode *Result = FindCallSeqEnd(User))
2817 /// FindCallSeqStart - Given a chained node that is part of a call sequence,
2818 /// find the CALLSEQ_START node that initiates the call sequence.
2819 static SDNode *FindCallSeqStart(SDNode *Node) {
2820 assert(Node && "Didn't find callseq_start for a call??");
2821 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
2823 assert(Node->getOperand(0).getValueType() == MVT::Other &&
2824 "Node doesn't have a token chain argument!");
2825 return FindCallSeqStart(Node->getOperand(0).Val);
2829 /// FindInputOutputChains - If we are replacing an operation with a call we need
2830 /// to find the call that occurs before and the call that occurs after it to
2831 /// properly serialize the calls in the block. The returned operand is the
2832 /// input chain value for the new call (e.g. the entry node or the previous
2833 /// call), and OutChain is set to be the chain node to update to point to the
2834 /// end of the call chain.
2835 static SDOperand FindInputOutputChains(SDNode *OpNode, SDNode *&OutChain,
2837 SDNode *LatestCallSeqStart = Entry.Val;
2838 SDNode *LatestCallSeqEnd = 0;
2839 FindLatestCallSeqStart(OpNode, LatestCallSeqStart);
2840 //std::cerr<<"Found node: "; LatestCallSeqStart->dump(); std::cerr <<"\n";
2842 // It is possible that no ISD::CALLSEQ_START was found because there is no
2843 // previous call in the function. LatestCallStackDown may in that case be
2844 // the entry node itself. Do not attempt to find a matching CALLSEQ_END
2845 // unless LatestCallStackDown is an CALLSEQ_START.
2846 if (LatestCallSeqStart->getOpcode() == ISD::CALLSEQ_START) {
2847 LatestCallSeqEnd = FindCallSeqEnd(LatestCallSeqStart);
2848 //std::cerr<<"Found end node: "; LatestCallSeqEnd->dump(); std::cerr <<"\n";
2850 LatestCallSeqEnd = Entry.Val;
2852 assert(LatestCallSeqEnd && "NULL return from FindCallSeqEnd");
2854 // Finally, find the first call that this must come before, first we find the
2855 // CallSeqEnd that ends the call.
2857 std::set<SDNode*> Visited;
2858 FindEarliestCallSeqEnd(OpNode, OutChain, Visited);
2860 // If we found one, translate from the adj up to the callseq_start.
2862 OutChain = FindCallSeqStart(OutChain);
2864 return SDOperand(LatestCallSeqEnd, 0);
2867 /// SpliceCallInto - Given the result chain of a libcall (CallResult), and a
2868 void SelectionDAGLegalize::SpliceCallInto(const SDOperand &CallResult,
2870 // Nothing to splice it into?
2871 if (OutChain == 0) return;
2873 assert(OutChain->getOperand(0).getValueType() == MVT::Other);
2876 // Form a token factor node merging the old inval and the new inval.
2877 SDOperand InToken = DAG.getNode(ISD::TokenFactor, MVT::Other, CallResult,
2878 OutChain->getOperand(0));
2879 // Change the node to refer to the new token.
2880 OutChain->setAdjCallChain(InToken);
2884 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
2885 // does not fit into a register, return the lo part and set the hi part to the
2886 // by-reg argument. If it does fit into a single register, return the result
2887 // and leave the Hi part unset.
2888 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
2891 SDOperand InChain = FindInputOutputChains(Node, OutChain,
2892 DAG.getEntryNode());
2893 if (InChain.Val == 0)
2894 InChain = DAG.getEntryNode();
2896 TargetLowering::ArgListTy Args;
2897 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2898 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
2899 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
2900 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy));
2902 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
2904 // Splice the libcall in wherever FindInputOutputChains tells us to.
2905 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
2906 std::pair<SDOperand,SDOperand> CallInfo =
2907 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, false,
2911 switch (getTypeAction(CallInfo.first.getValueType())) {
2912 default: assert(0 && "Unknown thing");
2914 Result = CallInfo.first;
2917 assert(0 && "Cannot promote this yet!");
2919 ExpandOp(CallInfo.first, Result, Hi);
2920 CallInfo.second = LegalizeOp(CallInfo.second);
2924 SpliceCallInto(CallInfo.second, OutChain);
2925 NeedsAnotherIteration = true;
2930 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the
2931 /// destination type is legal.
2932 SDOperand SelectionDAGLegalize::
2933 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
2934 assert(isTypeLegal(DestTy) && "Destination type is not legal!");
2935 assert(getTypeAction(Source.getValueType()) == Expand &&
2936 "This is not an expansion!");
2937 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
2940 assert(Source.getValueType() == MVT::i64 &&
2941 "This only works for 64-bit -> FP");
2942 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
2943 // incoming integer is set. To handle this, we dynamically test to see if
2944 // it is set, and, if so, add a fudge factor.
2946 ExpandOp(Source, Lo, Hi);
2948 // If this is unsigned, and not supported, first perform the conversion to
2949 // signed, then adjust the result if the sign bit is set.
2950 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
2951 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
2953 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
2954 DAG.getConstant(0, Hi.getValueType()),
2956 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
2957 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
2958 SignSet, Four, Zero);
2959 uint64_t FF = 0x5f800000ULL;
2960 if (TLI.isLittleEndian()) FF <<= 32;
2961 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
2963 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
2964 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
2965 SDOperand FudgeInReg;
2966 if (DestTy == MVT::f32)
2967 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
2968 DAG.getSrcValue(NULL));
2970 assert(DestTy == MVT::f64 && "Unexpected conversion");
2971 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
2972 CPIdx, DAG.getSrcValue(NULL), MVT::f32);
2974 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
2977 // Check to see if the target has a custom way to lower this. If so, use it.
2978 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
2979 default: assert(0 && "This action not implemented for this operation!");
2980 case TargetLowering::Legal:
2981 case TargetLowering::Expand:
2982 break; // This case is handled below.
2983 case TargetLowering::Custom: {
2984 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
2987 return LegalizeOp(NV);
2988 break; // The target decided this was legal after all
2992 // Expand the source, then glue it back together for the call. We must expand
2993 // the source in case it is shared (this pass of legalize must traverse it).
2994 SDOperand SrcLo, SrcHi;
2995 ExpandOp(Source, SrcLo, SrcHi);
2996 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
2998 SDNode *OutChain = 0;
2999 SDOperand InChain = FindInputOutputChains(Source.Val, OutChain,
3000 DAG.getEntryNode());
3001 const char *FnName = 0;
3002 if (DestTy == MVT::f32)
3003 FnName = "__floatdisf";
3005 assert(DestTy == MVT::f64 && "Unknown fp value type!");
3006 FnName = "__floatdidf";
3009 SDOperand Callee = DAG.getExternalSymbol(FnName, TLI.getPointerTy());
3011 TargetLowering::ArgListTy Args;
3012 const Type *ArgTy = MVT::getTypeForValueType(Source.getValueType());
3014 Args.push_back(std::make_pair(Source, ArgTy));
3016 // We don't care about token chains for libcalls. We just use the entry
3017 // node as our input and ignore the output chain. This allows us to place
3018 // calls wherever we need them to satisfy data dependences.
3019 const Type *RetTy = MVT::getTypeForValueType(DestTy);
3021 std::pair<SDOperand,SDOperand> CallResult =
3022 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, true,
3025 SpliceCallInto(CallResult.second, OutChain);
3026 return CallResult.first;
3031 /// ExpandOp - Expand the specified SDOperand into its two component pieces
3032 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
3033 /// LegalizeNodes map is filled in for any results that are not expanded, the
3034 /// ExpandedNodes map is filled in for any results that are expanded, and the
3035 /// Lo/Hi values are returned.
3036 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
3037 MVT::ValueType VT = Op.getValueType();
3038 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3039 SDNode *Node = Op.Val;
3040 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
3041 assert((MVT::isInteger(VT) || VT == MVT::Vector) &&
3042 "Cannot expand FP values!");
3043 assert(((MVT::isInteger(NVT) && NVT < VT) || VT == MVT::Vector) &&
3044 "Cannot expand to FP value or to larger int value!");
3046 // See if we already expanded it.
3047 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
3048 = ExpandedNodes.find(Op);
3049 if (I != ExpandedNodes.end()) {
3050 Lo = I->second.first;
3051 Hi = I->second.second;
3055 // Expanding to multiple registers needs to perform an optimization step, and
3056 // is not careful to avoid operations the target does not support. Make sure
3057 // that all generated operations are legalized in the next iteration.
3058 NeedsAnotherIteration = true;
3060 switch (Node->getOpcode()) {
3061 case ISD::CopyFromReg:
3062 assert(0 && "CopyFromReg must be legal!");
3064 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
3065 assert(0 && "Do not know how to expand this operator!");
3068 Lo = DAG.getNode(ISD::UNDEF, NVT);
3069 Hi = DAG.getNode(ISD::UNDEF, NVT);
3071 case ISD::Constant: {
3072 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
3073 Lo = DAG.getConstant(Cst, NVT);
3074 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
3078 case ISD::BUILD_PAIR:
3079 // Legalize both operands. FIXME: in the future we should handle the case
3080 // where the two elements are not legal.
3081 assert(isTypeLegal(NVT) && "Cannot expand this multiple times yet!");
3082 Lo = LegalizeOp(Node->getOperand(0));
3083 Hi = LegalizeOp(Node->getOperand(1));
3087 ExpandOp(Node->getOperand(0), Lo, Hi);
3088 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
3089 DAG.getNode(ISD::CTPOP, NVT, Lo),
3090 DAG.getNode(ISD::CTPOP, NVT, Hi));
3091 Hi = DAG.getConstant(0, NVT);
3095 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
3096 ExpandOp(Node->getOperand(0), Lo, Hi);
3097 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
3098 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
3099 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
3101 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
3102 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
3104 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
3105 Hi = DAG.getConstant(0, NVT);
3110 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
3111 ExpandOp(Node->getOperand(0), Lo, Hi);
3112 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
3113 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
3114 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
3116 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
3117 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
3119 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
3120 Hi = DAG.getConstant(0, NVT);
3125 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3126 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3127 Lo = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
3129 // Increment the pointer to the other half.
3130 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
3131 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
3132 getIntPtrConstant(IncrementSize));
3133 //Is this safe? declaring that the two parts of the split load
3134 //are from the same instruction?
3135 Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
3137 // Build a factor node to remember that this load is independent of the
3139 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
3142 // Remember that we legalized the chain.
3143 AddLegalizedOperand(Op.getValue(1), TF);
3144 if (!TLI.isLittleEndian())
3149 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3150 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3151 unsigned NumElements =cast<ConstantSDNode>(Node->getOperand(2))->getValue();
3152 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3154 // If we only have two elements, turn into a pair of scalar loads.
3155 // FIXME: handle case where a vector of two elements is fine, such as
3156 // 2 x double on SSE2.
3157 if (NumElements == 2) {
3158 Lo = DAG.getLoad(EVT, Ch, Ptr, Node->getOperand(4));
3159 // Increment the pointer to the other half.
3160 unsigned IncrementSize = MVT::getSizeInBits(EVT)/8;
3161 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
3162 getIntPtrConstant(IncrementSize));
3163 //Is this safe? declaring that the two parts of the split load
3164 //are from the same instruction?
3165 Hi = DAG.getLoad(EVT, Ch, Ptr, Node->getOperand(4));
3167 NumElements /= 2; // Split the vector in half
3168 Lo = DAG.getVecLoad(NumElements, EVT, Ch, Ptr, Node->getOperand(4));
3169 unsigned IncrementSize = NumElements * MVT::getSizeInBits(EVT)/8;
3170 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
3171 getIntPtrConstant(IncrementSize));
3172 //Is this safe? declaring that the two parts of the split load
3173 //are from the same instruction?
3174 Hi = DAG.getVecLoad(NumElements, EVT, Ch, Ptr, Node->getOperand(4));
3177 // Build a factor node to remember that this load is independent of the
3179 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
3182 // Remember that we legalized the chain.
3183 AddLegalizedOperand(Op.getValue(1), TF);
3184 if (!TLI.isLittleEndian())
3191 unsigned NumElements =cast<ConstantSDNode>(Node->getOperand(2))->getValue();
3192 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3193 SDOperand LL, LH, RL, RH;
3195 ExpandOp(Node->getOperand(0), LL, LH);
3196 ExpandOp(Node->getOperand(1), RL, RH);
3198 // If we only have two elements, turn into a pair of scalar loads.
3199 // FIXME: handle case where a vector of two elements is fine, such as
3200 // 2 x double on SSE2.
3201 if (NumElements == 2) {
3202 unsigned Opc = getScalarizedOpcode(Node->getOpcode(), EVT);
3203 Lo = DAG.getNode(Opc, EVT, LL, RL);
3204 Hi = DAG.getNode(Opc, EVT, LH, RH);
3206 Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL, LL.getOperand(2),
3208 Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH, LH.getOperand(2),
3215 SDOperand Chain = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3216 SDOperand Callee = LegalizeOp(Node->getOperand(1)); // Legalize the callee.
3218 bool Changed = false;
3219 std::vector<SDOperand> Ops;
3220 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) {
3221 Ops.push_back(LegalizeOp(Node->getOperand(i)));
3222 Changed |= Ops.back() != Node->getOperand(i);
3225 assert(Node->getNumValues() == 2 && Op.ResNo == 0 &&
3226 "Can only expand a call once so far, not i64 -> i16!");
3228 std::vector<MVT::ValueType> RetTyVTs;
3229 RetTyVTs.reserve(3);
3230 RetTyVTs.push_back(NVT);
3231 RetTyVTs.push_back(NVT);
3232 RetTyVTs.push_back(MVT::Other);
3233 SDNode *NC = DAG.getCall(RetTyVTs, Chain, Callee, Ops,
3234 Node->getOpcode() == ISD::TAILCALL);
3235 Lo = SDOperand(NC, 0);
3236 Hi = SDOperand(NC, 1);
3238 // Insert the new chain mapping.
3239 AddLegalizedOperand(Op.getValue(1), Hi.getValue(2));
3244 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
3245 SDOperand LL, LH, RL, RH;
3246 ExpandOp(Node->getOperand(0), LL, LH);
3247 ExpandOp(Node->getOperand(1), RL, RH);
3248 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
3249 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
3253 SDOperand C, LL, LH, RL, RH;
3255 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3256 case Expand: assert(0 && "It's impossible to expand bools");
3258 C = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
3261 C = PromoteOp(Node->getOperand(0)); // Promote the condition.
3264 ExpandOp(Node->getOperand(1), LL, LH);
3265 ExpandOp(Node->getOperand(2), RL, RH);
3266 Lo = DAG.getNode(ISD::SELECT, NVT, C, LL, RL);
3267 Hi = DAG.getNode(ISD::SELECT, NVT, C, LH, RH);
3270 case ISD::SELECT_CC: {
3271 SDOperand TL, TH, FL, FH;
3272 ExpandOp(Node->getOperand(2), TL, TH);
3273 ExpandOp(Node->getOperand(3), FL, FH);
3274 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3275 Node->getOperand(1), TL, FL, Node->getOperand(4));
3276 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3277 Node->getOperand(1), TH, FH, Node->getOperand(4));
3278 Lo = LegalizeOp(Lo);
3279 Hi = LegalizeOp(Hi);
3282 case ISD::SEXTLOAD: {
3283 SDOperand Chain = LegalizeOp(Node->getOperand(0));
3284 SDOperand Ptr = LegalizeOp(Node->getOperand(1));
3285 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3288 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
3290 Lo = DAG.getExtLoad(ISD::SEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
3293 // Remember that we legalized the chain.
3294 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1));
3296 // The high part is obtained by SRA'ing all but one of the bits of the lo
3298 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
3299 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1,
3300 TLI.getShiftAmountTy()));
3301 Lo = LegalizeOp(Lo);
3302 Hi = LegalizeOp(Hi);
3305 case ISD::ZEXTLOAD: {
3306 SDOperand Chain = LegalizeOp(Node->getOperand(0));
3307 SDOperand Ptr = LegalizeOp(Node->getOperand(1));
3308 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3311 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
3313 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
3316 // Remember that we legalized the chain.
3317 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1));
3319 // The high part is just a zero.
3320 Hi = LegalizeOp(DAG.getConstant(0, NVT));
3321 Lo = LegalizeOp(Lo);
3324 case ISD::EXTLOAD: {
3325 SDOperand Chain = LegalizeOp(Node->getOperand(0));
3326 SDOperand Ptr = LegalizeOp(Node->getOperand(1));
3327 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3330 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
3332 Lo = DAG.getExtLoad(ISD::EXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
3335 // Remember that we legalized the chain.
3336 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1));
3338 // The high part is undefined.
3339 Hi = LegalizeOp(DAG.getNode(ISD::UNDEF, NVT));
3340 Lo = LegalizeOp(Lo);
3343 case ISD::ANY_EXTEND: {
3345 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3346 case Expand: assert(0 && "expand-expand not implemented yet!");
3347 case Legal: In = LegalizeOp(Node->getOperand(0)); break;
3349 In = PromoteOp(Node->getOperand(0));
3353 // The low part is any extension of the input (which degenerates to a copy).
3354 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, In);
3355 // The high part is undefined.
3356 Hi = DAG.getNode(ISD::UNDEF, NVT);
3359 case ISD::SIGN_EXTEND: {
3361 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3362 case Expand: assert(0 && "expand-expand not implemented yet!");
3363 case Legal: In = LegalizeOp(Node->getOperand(0)); break;
3365 In = PromoteOp(Node->getOperand(0));
3366 // Emit the appropriate sign_extend_inreg to get the value we want.
3367 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(), In,
3368 DAG.getValueType(Node->getOperand(0).getValueType()));
3372 // The low part is just a sign extension of the input (which degenerates to
3374 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, In);
3376 // The high part is obtained by SRA'ing all but one of the bits of the lo
3378 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
3379 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1,
3380 TLI.getShiftAmountTy()));
3383 case ISD::ZERO_EXTEND: {
3385 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3386 case Expand: assert(0 && "expand-expand not implemented yet!");
3387 case Legal: In = LegalizeOp(Node->getOperand(0)); break;
3389 In = PromoteOp(Node->getOperand(0));
3390 // Emit the appropriate zero_extend_inreg to get the value we want.
3391 In = DAG.getZeroExtendInReg(In, Node->getOperand(0).getValueType());
3395 // The low part is just a zero extension of the input (which degenerates to
3397 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, In);
3399 // The high part is just a zero.
3400 Hi = DAG.getConstant(0, NVT);
3404 case ISD::READCYCLECOUNTER: {
3405 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
3406 TargetLowering::Custom &&
3407 "Must custom expand ReadCycleCounter");
3408 SDOperand T = TLI.LowerOperation(Op, DAG);
3409 assert(T.Val && "Node must be custom expanded!");
3410 Lo = LegalizeOp(T.getValue(0));
3411 Hi = LegalizeOp(T.getValue(1));
3412 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
3413 LegalizeOp(T.getValue(2)));
3417 // These operators cannot be expanded directly, emit them as calls to
3418 // library functions.
3419 case ISD::FP_TO_SINT:
3420 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
3422 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3423 case Expand: assert(0 && "cannot expand FP!");
3424 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
3425 case Promote: Op = PromoteOp(Node->getOperand(0)); break;
3428 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
3430 // Now that the custom expander is done, expand the result, which is still
3433 ExpandOp(Op, Lo, Hi);
3438 if (Node->getOperand(0).getValueType() == MVT::f32)
3439 Lo = ExpandLibCall("__fixsfdi", Node, Hi);
3441 Lo = ExpandLibCall("__fixdfdi", Node, Hi);
3444 case ISD::FP_TO_UINT:
3445 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
3446 SDOperand Op = DAG.getNode(ISD::FP_TO_UINT, VT,
3447 LegalizeOp(Node->getOperand(0)));
3448 // Now that the custom expander is done, expand the result, which is still
3450 Op = TLI.LowerOperation(Op, DAG);
3452 ExpandOp(Op, Lo, Hi);
3457 if (Node->getOperand(0).getValueType() == MVT::f32)
3458 Lo = ExpandLibCall("__fixunssfdi", Node, Hi);
3460 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi);
3464 // If the target wants custom lowering, do so.
3465 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
3466 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0),
3467 LegalizeOp(Node->getOperand(1)));
3468 Op = TLI.LowerOperation(Op, DAG);
3470 // Now that the custom expander is done, expand the result, which is
3472 ExpandOp(Op, Lo, Hi);
3477 // If we can emit an efficient shift operation, do so now.
3478 if (ExpandShift(ISD::SHL, Node->getOperand(0), Node->getOperand(1), Lo, Hi))
3481 // If this target supports SHL_PARTS, use it.
3482 if (TLI.isOperationLegal(ISD::SHL_PARTS, NVT)) {
3483 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), Node->getOperand(1),
3488 // Otherwise, emit a libcall.
3489 Lo = ExpandLibCall("__ashldi3", Node, Hi);
3493 // If the target wants custom lowering, do so.
3494 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
3495 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0),
3496 LegalizeOp(Node->getOperand(1)));
3497 Op = TLI.LowerOperation(Op, DAG);
3499 // Now that the custom expander is done, expand the result, which is
3501 ExpandOp(Op, Lo, Hi);
3506 // If we can emit an efficient shift operation, do so now.
3507 if (ExpandShift(ISD::SRA, Node->getOperand(0), Node->getOperand(1), Lo, Hi))
3510 // If this target supports SRA_PARTS, use it.
3511 if (TLI.isOperationLegal(ISD::SRA_PARTS, NVT)) {
3512 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), Node->getOperand(1),
3517 // Otherwise, emit a libcall.
3518 Lo = ExpandLibCall("__ashrdi3", Node, Hi);
3521 // If the target wants custom lowering, do so.
3522 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
3523 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0),
3524 LegalizeOp(Node->getOperand(1)));
3525 Op = TLI.LowerOperation(Op, DAG);
3527 // Now that the custom expander is done, expand the result, which is
3529 ExpandOp(Op, Lo, Hi);
3534 // If we can emit an efficient shift operation, do so now.
3535 if (ExpandShift(ISD::SRL, Node->getOperand(0), Node->getOperand(1), Lo, Hi))
3538 // If this target supports SRL_PARTS, use it.
3539 if (TLI.isOperationLegal(ISD::SRL_PARTS, NVT)) {
3540 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), Node->getOperand(1),
3545 // Otherwise, emit a libcall.
3546 Lo = ExpandLibCall("__lshrdi3", Node, Hi);
3550 ExpandByParts(ISD::ADD_PARTS, Node->getOperand(0), Node->getOperand(1),
3554 ExpandByParts(ISD::SUB_PARTS, Node->getOperand(0), Node->getOperand(1),
3558 if (TLI.isOperationLegal(ISD::MULHU, NVT)) {
3559 SDOperand LL, LH, RL, RH;
3560 ExpandOp(Node->getOperand(0), LL, LH);
3561 ExpandOp(Node->getOperand(1), RL, RH);
3562 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1;
3563 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp
3564 // extended the sign bit of the low half through the upper half, and if so
3565 // emit a MULHS instead of the alternate sequence that is valid for any
3566 // i64 x i64 multiply.
3567 if (TLI.isOperationLegal(ISD::MULHS, NVT) &&
3568 // is RH an extension of the sign bit of RL?
3569 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL &&
3570 RH.getOperand(1).getOpcode() == ISD::Constant &&
3571 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH &&
3572 // is LH an extension of the sign bit of LL?
3573 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL &&
3574 LH.getOperand(1).getOpcode() == ISD::Constant &&
3575 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) {
3576 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
3578 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
3579 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
3580 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
3581 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
3582 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
3584 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
3586 Lo = ExpandLibCall("__muldi3" , Node, Hi); break;
3590 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break;
3591 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break;
3592 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break;
3593 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break;
3596 // Remember in a map if the values will be reused later.
3597 bool isNew = ExpandedNodes.insert(std::make_pair(Op,
3598 std::make_pair(Lo, Hi))).second;
3599 assert(isNew && "Value already expanded?!?");
3603 // SelectionDAG::Legalize - This is the entry point for the file.
3605 void SelectionDAG::Legalize() {
3606 /// run - This is the main entry point to this class.
3608 SelectionDAGLegalize(*this).Run();