1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/Analysis/DebugInfo.h"
20 #include "llvm/CodeGen/PseudoSourceValue.h"
21 #include "llvm/Target/TargetFrameInfo.h"
22 #include "llvm/Target/TargetLowering.h"
23 #include "llvm/Target/TargetData.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Target/TargetOptions.h"
26 #include "llvm/CallingConv.h"
27 #include "llvm/Constants.h"
28 #include "llvm/DerivedTypes.h"
29 #include "llvm/Function.h"
30 #include "llvm/GlobalVariable.h"
31 #include "llvm/LLVMContext.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/Support/raw_ostream.h"
37 #include "llvm/ADT/DenseMap.h"
38 #include "llvm/ADT/SmallVector.h"
39 #include "llvm/ADT/SmallPtrSet.h"
42 //===----------------------------------------------------------------------===//
43 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
44 /// hacks on it until the target machine can handle it. This involves
45 /// eliminating value sizes the machine cannot handle (promoting small sizes to
46 /// large sizes or splitting up large values into small values) as well as
47 /// eliminating operations the machine cannot handle.
49 /// This code also does a small amount of optimization and recognition of idioms
50 /// as part of its processing. For example, if a target does not support a
51 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
52 /// will attempt merge setcc and brc instructions into brcc's.
55 class SelectionDAGLegalize {
56 const TargetMachine &TM;
57 const TargetLowering &TLI;
59 CodeGenOpt::Level OptLevel;
61 // Libcall insertion helpers.
63 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
64 /// legalized. We use this to ensure that calls are properly serialized
65 /// against each other, including inserted libcalls.
66 SDValue LastCALLSEQ_END;
68 /// IsLegalizingCall - This member is used *only* for purposes of providing
69 /// helpful assertions that a libcall isn't created while another call is
70 /// being legalized (which could lead to non-serialized call sequences).
71 bool IsLegalizingCall;
74 Legal, // The target natively supports this operation.
75 Promote, // This operation should be executed in a larger type.
76 Expand // Try to expand this to other ops, otherwise use a libcall.
79 /// ValueTypeActions - This is a bitvector that contains two bits for each
80 /// value type, where the two bits correspond to the LegalizeAction enum.
81 /// This can be queried with "getTypeAction(VT)".
82 TargetLowering::ValueTypeActionImpl ValueTypeActions;
84 /// LegalizedNodes - For nodes that are of legal width, and that have more
85 /// than one use, this map indicates what regularized operand to use. This
86 /// allows us to avoid legalizing the same thing more than once.
87 DenseMap<SDValue, SDValue> LegalizedNodes;
89 void AddLegalizedOperand(SDValue From, SDValue To) {
90 LegalizedNodes.insert(std::make_pair(From, To));
91 // If someone requests legalization of the new node, return itself.
93 LegalizedNodes.insert(std::make_pair(To, To));
97 SelectionDAGLegalize(SelectionDAG &DAG, CodeGenOpt::Level ol);
99 /// getTypeAction - Return how we should legalize values of this type, either
100 /// it is already legal or we need to expand it into multiple registers of
101 /// smaller integer type, or we need to promote it to a larger type.
102 LegalizeAction getTypeAction(EVT VT) const {
103 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
106 /// isTypeLegal - Return true if this type is legal on this target.
108 bool isTypeLegal(EVT VT) const {
109 return getTypeAction(VT) == Legal;
115 /// LegalizeOp - We know that the specified value has a legal type.
116 /// Recursively ensure that the operands have legal types, then return the
118 SDValue LegalizeOp(SDValue O);
120 SDValue OptimizeFloatStore(StoreSDNode *ST);
122 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
123 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
124 /// is necessary to spill the vector being inserted into to memory, perform
125 /// the insert there, and then read the result back.
126 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
127 SDValue Idx, DebugLoc dl);
128 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
129 SDValue Idx, DebugLoc dl);
131 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
132 /// performs the same shuffe in terms of order or result bytes, but on a type
133 /// whose vector element type is narrower than the original shuffle type.
134 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
135 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
136 SDValue N1, SDValue N2,
137 SmallVectorImpl<int> &Mask) const;
139 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
140 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
142 void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
145 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
146 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
147 SDNode *Node, bool isSigned);
148 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
149 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
150 RTLIB::Libcall Call_PPCF128);
151 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
152 RTLIB::Libcall Call_I8,
153 RTLIB::Libcall Call_I16,
154 RTLIB::Libcall Call_I32,
155 RTLIB::Libcall Call_I64,
156 RTLIB::Libcall Call_I128);
158 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl);
159 SDValue ExpandBUILD_VECTOR(SDNode *Node);
160 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
161 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
162 SmallVectorImpl<SDValue> &Results);
163 SDValue ExpandFCOPYSIGN(SDNode *Node);
164 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
166 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
168 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
171 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl);
172 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl);
174 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
175 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
177 std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node);
179 void ExpandNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
180 void PromoteNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
184 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
185 /// performs the same shuffe in terms of order or result bytes, but on a type
186 /// whose vector element type is narrower than the original shuffle type.
187 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
189 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
190 SDValue N1, SDValue N2,
191 SmallVectorImpl<int> &Mask) const {
192 unsigned NumMaskElts = VT.getVectorNumElements();
193 unsigned NumDestElts = NVT.getVectorNumElements();
194 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
196 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
198 if (NumEltsGrowth == 1)
199 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
201 SmallVector<int, 8> NewMask;
202 for (unsigned i = 0; i != NumMaskElts; ++i) {
204 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
206 NewMask.push_back(-1);
208 NewMask.push_back(Idx * NumEltsGrowth + j);
211 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
212 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
213 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
216 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag,
217 CodeGenOpt::Level ol)
218 : TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()),
219 DAG(dag), OptLevel(ol),
220 ValueTypeActions(TLI.getValueTypeActions()) {
221 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
222 "Too many value types for ValueTypeActions to hold!");
225 void SelectionDAGLegalize::LegalizeDAG() {
226 LastCALLSEQ_END = DAG.getEntryNode();
227 IsLegalizingCall = false;
229 // The legalize process is inherently a bottom-up recursive process (users
230 // legalize their uses before themselves). Given infinite stack space, we
231 // could just start legalizing on the root and traverse the whole graph. In
232 // practice however, this causes us to run out of stack space on large basic
233 // blocks. To avoid this problem, compute an ordering of the nodes where each
234 // node is only legalized after all of its operands are legalized.
235 DAG.AssignTopologicalOrder();
236 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
237 E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I)
238 LegalizeOp(SDValue(I, 0));
240 // Finally, it's possible the root changed. Get the new root.
241 SDValue OldRoot = DAG.getRoot();
242 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
243 DAG.setRoot(LegalizedNodes[OldRoot]);
245 LegalizedNodes.clear();
247 // Remove dead nodes now.
248 DAG.RemoveDeadNodes();
252 /// FindCallEndFromCallStart - Given a chained node that is part of a call
253 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
254 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
255 if (Node->getOpcode() == ISD::CALLSEQ_END)
257 if (Node->use_empty())
258 return 0; // No CallSeqEnd
260 // The chain is usually at the end.
261 SDValue TheChain(Node, Node->getNumValues()-1);
262 if (TheChain.getValueType() != MVT::Other) {
263 // Sometimes it's at the beginning.
264 TheChain = SDValue(Node, 0);
265 if (TheChain.getValueType() != MVT::Other) {
266 // Otherwise, hunt for it.
267 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
268 if (Node->getValueType(i) == MVT::Other) {
269 TheChain = SDValue(Node, i);
273 // Otherwise, we walked into a node without a chain.
274 if (TheChain.getValueType() != MVT::Other)
279 for (SDNode::use_iterator UI = Node->use_begin(),
280 E = Node->use_end(); UI != E; ++UI) {
282 // Make sure to only follow users of our token chain.
284 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
285 if (User->getOperand(i) == TheChain)
286 if (SDNode *Result = FindCallEndFromCallStart(User))
292 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
293 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
294 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
295 assert(Node && "Didn't find callseq_start for a call??");
296 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
298 assert(Node->getOperand(0).getValueType() == MVT::Other &&
299 "Node doesn't have a token chain argument!");
300 return FindCallStartFromCallEnd(Node->getOperand(0).getNode());
303 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
304 /// see if any uses can reach Dest. If no dest operands can get to dest,
305 /// legalize them, legalize ourself, and return false, otherwise, return true.
307 /// Keep track of the nodes we fine that actually do lead to Dest in
308 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
310 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
311 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
312 if (N == Dest) return true; // N certainly leads to Dest :)
314 // If we've already processed this node and it does lead to Dest, there is no
315 // need to reprocess it.
316 if (NodesLeadingTo.count(N)) return true;
318 // If the first result of this node has been already legalized, then it cannot
320 if (LegalizedNodes.count(SDValue(N, 0))) return false;
322 // Okay, this node has not already been legalized. Check and legalize all
323 // operands. If none lead to Dest, then we can legalize this node.
324 bool OperandsLeadToDest = false;
325 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
326 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
327 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest,
330 if (OperandsLeadToDest) {
331 NodesLeadingTo.insert(N);
335 // Okay, this node looks safe, legalize it and return false.
336 LegalizeOp(SDValue(N, 0));
340 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
341 /// a load from the constant pool.
342 static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
343 SelectionDAG &DAG, const TargetLowering &TLI) {
345 DebugLoc dl = CFP->getDebugLoc();
347 // If a FP immediate is precise when represented as a float and if the
348 // target can do an extending load from float to double, we put it into
349 // the constant pool as a float, even if it's is statically typed as a
350 // double. This shrinks FP constants and canonicalizes them for targets where
351 // an FP extending load is the same cost as a normal load (such as on the x87
352 // fp stack or PPC FP unit).
353 EVT VT = CFP->getValueType(0);
354 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
356 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
357 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
358 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
363 while (SVT != MVT::f32) {
364 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
365 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) &&
366 // Only do this if the target has a native EXTLOAD instruction from
368 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
369 TLI.ShouldShrinkFPConstant(OrigVT)) {
370 const Type *SType = SVT.getTypeForEVT(*DAG.getContext());
371 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
377 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
378 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
380 return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, dl,
382 CPIdx, PseudoSourceValue::getConstantPool(),
383 0, VT, false, false, Alignment);
384 return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
385 PseudoSourceValue::getConstantPool(), 0, false, false,
389 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
391 SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
392 const TargetLowering &TLI) {
393 SDValue Chain = ST->getChain();
394 SDValue Ptr = ST->getBasePtr();
395 SDValue Val = ST->getValue();
396 EVT VT = Val.getValueType();
397 int Alignment = ST->getAlignment();
398 int SVOffset = ST->getSrcValueOffset();
399 DebugLoc dl = ST->getDebugLoc();
400 if (ST->getMemoryVT().isFloatingPoint() ||
401 ST->getMemoryVT().isVector()) {
402 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
403 if (TLI.isTypeLegal(intVT)) {
404 // Expand to a bitconvert of the value to the integer type of the
405 // same size, then a (misaligned) int store.
406 // FIXME: Does not handle truncating floating point stores!
407 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, intVT, Val);
408 return DAG.getStore(Chain, dl, Result, Ptr, ST->getSrcValue(),
409 SVOffset, ST->isVolatile(), ST->isNonTemporal(),
412 // Do a (aligned) store to a stack slot, then copy from the stack slot
413 // to the final destination using (unaligned) integer loads and stores.
414 EVT StoredVT = ST->getMemoryVT();
416 TLI.getRegisterType(*DAG.getContext(),
417 EVT::getIntegerVT(*DAG.getContext(),
418 StoredVT.getSizeInBits()));
419 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
420 unsigned RegBytes = RegVT.getSizeInBits() / 8;
421 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
423 // Make sure the stack slot is also aligned for the register type.
424 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
426 // Perform the original store, only redirected to the stack slot.
427 SDValue Store = DAG.getTruncStore(Chain, dl,
428 Val, StackPtr, NULL, 0, StoredVT,
430 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
431 SmallVector<SDValue, 8> Stores;
434 // Do all but one copies using the full register width.
435 for (unsigned i = 1; i < NumRegs; i++) {
436 // Load one integer register's worth from the stack slot.
437 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, NULL, 0,
439 // Store it to the final location. Remember the store.
440 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
441 ST->getSrcValue(), SVOffset + Offset,
442 ST->isVolatile(), ST->isNonTemporal(),
443 MinAlign(ST->getAlignment(), Offset)));
444 // Increment the pointers.
446 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
448 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
451 // The last store may be partial. Do a truncating store. On big-endian
452 // machines this requires an extending load from the stack slot to ensure
453 // that the bits are in the right place.
454 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
455 8 * (StoredBytes - Offset));
457 // Load from the stack slot.
458 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, RegVT, dl, Store, StackPtr,
459 NULL, 0, MemVT, false, false, 0);
461 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
462 ST->getSrcValue(), SVOffset + Offset,
463 MemVT, ST->isVolatile(),
465 MinAlign(ST->getAlignment(), Offset)));
466 // The order of the stores doesn't matter - say it with a TokenFactor.
467 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
471 assert(ST->getMemoryVT().isInteger() &&
472 !ST->getMemoryVT().isVector() &&
473 "Unaligned store of unknown type.");
474 // Get the half-size VT
475 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext());
476 int NumBits = NewStoredVT.getSizeInBits();
477 int IncrementSize = NumBits / 8;
479 // Divide the stored value in two parts.
480 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
482 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
484 // Store the two parts
485 SDValue Store1, Store2;
486 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
487 ST->getSrcValue(), SVOffset, NewStoredVT,
488 ST->isVolatile(), ST->isNonTemporal(), Alignment);
489 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
490 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
491 Alignment = MinAlign(Alignment, IncrementSize);
492 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
493 ST->getSrcValue(), SVOffset + IncrementSize,
494 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(),
497 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
500 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
502 SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
503 const TargetLowering &TLI) {
504 int SVOffset = LD->getSrcValueOffset();
505 SDValue Chain = LD->getChain();
506 SDValue Ptr = LD->getBasePtr();
507 EVT VT = LD->getValueType(0);
508 EVT LoadedVT = LD->getMemoryVT();
509 DebugLoc dl = LD->getDebugLoc();
510 if (VT.isFloatingPoint() || VT.isVector()) {
511 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
512 if (TLI.isTypeLegal(intVT)) {
513 // Expand to a (misaligned) integer load of the same size,
514 // then bitconvert to floating point or vector.
515 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getSrcValue(),
516 SVOffset, LD->isVolatile(),
517 LD->isNonTemporal(), LD->getAlignment());
518 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, LoadedVT, newLoad);
519 if (VT.isFloatingPoint() && LoadedVT != VT)
520 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result);
522 SDValue Ops[] = { Result, Chain };
523 return DAG.getMergeValues(Ops, 2, dl);
525 // Copy the value to a (aligned) stack slot using (unaligned) integer
526 // loads and stores, then do a (aligned) load from the stack slot.
527 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
528 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
529 unsigned RegBytes = RegVT.getSizeInBits() / 8;
530 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
532 // Make sure the stack slot is also aligned for the register type.
533 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
535 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
536 SmallVector<SDValue, 8> Stores;
537 SDValue StackPtr = StackBase;
540 // Do all but one copies using the full register width.
541 for (unsigned i = 1; i < NumRegs; i++) {
542 // Load one integer register's worth from the original location.
543 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, LD->getSrcValue(),
544 SVOffset + Offset, LD->isVolatile(),
546 MinAlign(LD->getAlignment(), Offset));
547 // Follow the load with a store to the stack slot. Remember the store.
548 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
549 NULL, 0, false, false, 0));
550 // Increment the pointers.
552 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
553 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
557 // The last copy may be partial. Do an extending load.
558 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
559 8 * (LoadedBytes - Offset));
560 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, RegVT, dl, Chain, Ptr,
561 LD->getSrcValue(), SVOffset + Offset,
562 MemVT, LD->isVolatile(),
564 MinAlign(LD->getAlignment(), Offset));
565 // Follow the load with a store to the stack slot. Remember the store.
566 // On big-endian machines this requires a truncating store to ensure
567 // that the bits end up in the right place.
568 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
569 NULL, 0, MemVT, false, false, 0));
571 // The order of the stores doesn't matter - say it with a TokenFactor.
572 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
575 // Finally, perform the original load only redirected to the stack slot.
576 Load = DAG.getExtLoad(LD->getExtensionType(), VT, dl, TF, StackBase,
577 NULL, 0, LoadedVT, false, false, 0);
579 // Callers expect a MERGE_VALUES node.
580 SDValue Ops[] = { Load, TF };
581 return DAG.getMergeValues(Ops, 2, dl);
584 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
585 "Unaligned load of unsupported type.");
587 // Compute the new VT that is half the size of the old one. This is an
589 unsigned NumBits = LoadedVT.getSizeInBits();
591 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
594 unsigned Alignment = LD->getAlignment();
595 unsigned IncrementSize = NumBits / 8;
596 ISD::LoadExtType HiExtType = LD->getExtensionType();
598 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
599 if (HiExtType == ISD::NON_EXTLOAD)
600 HiExtType = ISD::ZEXTLOAD;
602 // Load the value in two parts
604 if (TLI.isLittleEndian()) {
605 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, dl, Chain, Ptr, LD->getSrcValue(),
606 SVOffset, NewLoadedVT, LD->isVolatile(),
607 LD->isNonTemporal(), Alignment);
608 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
609 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
610 Hi = DAG.getExtLoad(HiExtType, VT, dl, Chain, Ptr, LD->getSrcValue(),
611 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
612 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
614 Hi = DAG.getExtLoad(HiExtType, VT, dl, Chain, Ptr, LD->getSrcValue(),
615 SVOffset, NewLoadedVT, LD->isVolatile(),
616 LD->isNonTemporal(), Alignment);
617 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
618 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
619 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, dl, Chain, Ptr, LD->getSrcValue(),
620 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
621 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
624 // aggregate the two parts
625 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
626 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
627 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
629 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
632 SDValue Ops[] = { Result, TF };
633 return DAG.getMergeValues(Ops, 2, dl);
636 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
637 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
638 /// is necessary to spill the vector being inserted into to memory, perform
639 /// the insert there, and then read the result back.
640 SDValue SelectionDAGLegalize::
641 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
647 // If the target doesn't support this, we have to spill the input vector
648 // to a temporary stack slot, update the element, then reload it. This is
649 // badness. We could also load the value into a vector register (either
650 // with a "move to register" or "extload into register" instruction, then
651 // permute it into place, if the idx is a constant and if the idx is
652 // supported by the target.
653 EVT VT = Tmp1.getValueType();
654 EVT EltVT = VT.getVectorElementType();
655 EVT IdxVT = Tmp3.getValueType();
656 EVT PtrVT = TLI.getPointerTy();
657 SDValue StackPtr = DAG.CreateStackTemporary(VT);
659 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
662 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
663 PseudoSourceValue::getFixedStack(SPFI), 0,
666 // Truncate or zero extend offset to target pointer type.
667 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
668 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
669 // Add the offset to the index.
670 unsigned EltSize = EltVT.getSizeInBits()/8;
671 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
672 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
673 // Store the scalar value.
674 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2,
675 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT,
677 // Load the updated vector.
678 return DAG.getLoad(VT, dl, Ch, StackPtr,
679 PseudoSourceValue::getFixedStack(SPFI), 0,
684 SDValue SelectionDAGLegalize::
685 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) {
686 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
687 // SCALAR_TO_VECTOR requires that the type of the value being inserted
688 // match the element type of the vector being created, except for
689 // integers in which case the inserted value can be over width.
690 EVT EltVT = Vec.getValueType().getVectorElementType();
691 if (Val.getValueType() == EltVT ||
692 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
693 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
694 Vec.getValueType(), Val);
696 unsigned NumElts = Vec.getValueType().getVectorNumElements();
697 // We generate a shuffle of InVec and ScVec, so the shuffle mask
698 // should be 0,1,2,3,4,5... with the appropriate element replaced with
700 SmallVector<int, 8> ShufOps;
701 for (unsigned i = 0; i != NumElts; ++i)
702 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
704 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
708 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
711 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
712 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
713 // FIXME: We shouldn't do this for TargetConstantFP's.
714 // FIXME: move this to the DAG Combiner! Note that we can't regress due
715 // to phase ordering between legalized code and the dag combiner. This
716 // probably means that we need to integrate dag combiner and legalizer
718 // We generally can't do this one for long doubles.
719 SDValue Tmp1 = ST->getChain();
720 SDValue Tmp2 = ST->getBasePtr();
722 int SVOffset = ST->getSrcValueOffset();
723 unsigned Alignment = ST->getAlignment();
724 bool isVolatile = ST->isVolatile();
725 bool isNonTemporal = ST->isNonTemporal();
726 DebugLoc dl = ST->getDebugLoc();
727 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
728 if (CFP->getValueType(0) == MVT::f32 &&
729 getTypeAction(MVT::i32) == Legal) {
730 Tmp3 = DAG.getConstant(CFP->getValueAPF().
731 bitcastToAPInt().zextOrTrunc(32),
733 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
734 SVOffset, isVolatile, isNonTemporal, Alignment);
735 } else if (CFP->getValueType(0) == MVT::f64) {
736 // If this target supports 64-bit registers, do a single 64-bit store.
737 if (getTypeAction(MVT::i64) == Legal) {
738 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
739 zextOrTrunc(64), MVT::i64);
740 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
741 SVOffset, isVolatile, isNonTemporal, Alignment);
742 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
743 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
744 // stores. If the target supports neither 32- nor 64-bits, this
745 // xform is certainly not worth it.
746 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
747 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
748 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
749 if (TLI.isBigEndian()) std::swap(Lo, Hi);
751 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(),
752 SVOffset, isVolatile, isNonTemporal, Alignment);
753 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
754 DAG.getIntPtrConstant(4));
755 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
756 isVolatile, isNonTemporal, MinAlign(Alignment, 4U));
758 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
765 /// LegalizeOp - We know that the specified value has a legal type, and
766 /// that its operands are legal. Now ensure that the operation itself
767 /// is legal, recursively ensuring that the operands' operations remain
769 SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
770 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
773 SDNode *Node = Op.getNode();
774 DebugLoc dl = Node->getDebugLoc();
776 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
777 assert(getTypeAction(Node->getValueType(i)) == Legal &&
778 "Unexpected illegal type!");
780 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
781 assert((isTypeLegal(Node->getOperand(i).getValueType()) ||
782 Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
783 "Unexpected illegal type!");
785 // Note that LegalizeOp may be reentered even from single-use nodes, which
786 // means that we always must cache transformed nodes.
787 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
788 if (I != LegalizedNodes.end()) return I->second;
790 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
792 bool isCustom = false;
794 // Figure out the correct action; the way to query this varies by opcode
795 TargetLowering::LegalizeAction Action;
796 bool SimpleFinishLegalizing = true;
797 switch (Node->getOpcode()) {
798 case ISD::INTRINSIC_W_CHAIN:
799 case ISD::INTRINSIC_WO_CHAIN:
800 case ISD::INTRINSIC_VOID:
803 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
805 case ISD::SINT_TO_FP:
806 case ISD::UINT_TO_FP:
807 case ISD::EXTRACT_VECTOR_ELT:
808 Action = TLI.getOperationAction(Node->getOpcode(),
809 Node->getOperand(0).getValueType());
811 case ISD::FP_ROUND_INREG:
812 case ISD::SIGN_EXTEND_INREG: {
813 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
814 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
820 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
821 Node->getOpcode() == ISD::SETCC ? 2 : 1;
822 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
823 EVT OpVT = Node->getOperand(CompareOperand).getValueType();
824 ISD::CondCode CCCode =
825 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
826 Action = TLI.getCondCodeAction(CCCode, OpVT);
827 if (Action == TargetLowering::Legal) {
828 if (Node->getOpcode() == ISD::SELECT_CC)
829 Action = TLI.getOperationAction(Node->getOpcode(),
830 Node->getValueType(0));
832 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
838 // FIXME: Model these properly. LOAD and STORE are complicated, and
839 // STORE expects the unlegalized operand in some cases.
840 SimpleFinishLegalizing = false;
842 case ISD::CALLSEQ_START:
843 case ISD::CALLSEQ_END:
844 // FIXME: This shouldn't be necessary. These nodes have special properties
845 // dealing with the recursive nature of legalization. Removing this
846 // special case should be done as part of making LegalizeDAG non-recursive.
847 SimpleFinishLegalizing = false;
849 case ISD::EXTRACT_ELEMENT:
850 case ISD::FLT_ROUNDS_:
858 case ISD::MERGE_VALUES:
860 case ISD::FRAME_TO_ARGS_OFFSET:
861 case ISD::EH_SJLJ_SETJMP:
862 case ISD::EH_SJLJ_LONGJMP:
863 // These operations lie about being legal: when they claim to be legal,
864 // they should actually be expanded.
865 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
866 if (Action == TargetLowering::Legal)
867 Action = TargetLowering::Expand;
869 case ISD::TRAMPOLINE:
871 case ISD::RETURNADDR:
872 // These operations lie about being legal: when they claim to be legal,
873 // they should actually be custom-lowered.
874 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
875 if (Action == TargetLowering::Legal)
876 Action = TargetLowering::Custom;
878 case ISD::BUILD_VECTOR:
879 // A weird case: legalization for BUILD_VECTOR never legalizes the
881 // FIXME: This really sucks... changing it isn't semantically incorrect,
882 // but it massively pessimizes the code for floating-point BUILD_VECTORs
883 // because ConstantFP operands get legalized into constant pool loads
884 // before the BUILD_VECTOR code can see them. It doesn't usually bite,
885 // though, because BUILD_VECTORS usually get lowered into other nodes
886 // which get legalized properly.
887 SimpleFinishLegalizing = false;
890 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
891 Action = TargetLowering::Legal;
893 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
898 if (SimpleFinishLegalizing) {
899 SmallVector<SDValue, 8> Ops, ResultVals;
900 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
901 Ops.push_back(LegalizeOp(Node->getOperand(i)));
902 switch (Node->getOpcode()) {
909 // Branches tweak the chain to include LastCALLSEQ_END
910 Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0],
912 Ops[0] = LegalizeOp(Ops[0]);
913 LastCALLSEQ_END = DAG.getEntryNode();
920 // Legalizing shifts/rotates requires adjusting the shift amount
921 // to the appropriate width.
922 if (!Ops[1].getValueType().isVector())
923 Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[1]));
928 // Legalizing shifts/rotates requires adjusting the shift amount
929 // to the appropriate width.
930 if (!Ops[2].getValueType().isVector())
931 Ops[2] = LegalizeOp(DAG.getShiftAmountOperand(Ops[2]));
935 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), Ops.data(),
938 case TargetLowering::Legal:
939 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
940 ResultVals.push_back(Result.getValue(i));
942 case TargetLowering::Custom:
943 // FIXME: The handling for custom lowering with multiple results is
945 Tmp1 = TLI.LowerOperation(Result, DAG);
946 if (Tmp1.getNode()) {
947 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
949 ResultVals.push_back(Tmp1);
951 ResultVals.push_back(Tmp1.getValue(i));
957 case TargetLowering::Expand:
958 ExpandNode(Result.getNode(), ResultVals);
960 case TargetLowering::Promote:
961 PromoteNode(Result.getNode(), ResultVals);
964 if (!ResultVals.empty()) {
965 for (unsigned i = 0, e = ResultVals.size(); i != e; ++i) {
966 if (ResultVals[i] != SDValue(Node, i))
967 ResultVals[i] = LegalizeOp(ResultVals[i]);
968 AddLegalizedOperand(SDValue(Node, i), ResultVals[i]);
970 return ResultVals[Op.getResNo()];
974 switch (Node->getOpcode()) {
981 assert(0 && "Do not know how to legalize this operator!");
983 case ISD::BUILD_VECTOR:
984 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
985 default: assert(0 && "This action is not supported yet!");
986 case TargetLowering::Custom:
987 Tmp3 = TLI.LowerOperation(Result, DAG);
988 if (Tmp3.getNode()) {
993 case TargetLowering::Expand:
994 Result = ExpandBUILD_VECTOR(Result.getNode());
998 case ISD::CALLSEQ_START: {
999 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1001 // Recursively Legalize all of the inputs of the call end that do not lead
1002 // to this call start. This ensures that any libcalls that need be inserted
1003 // are inserted *before* the CALLSEQ_START.
1004 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1005 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1006 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
1010 // Now that we have legalized all of the inputs (which may have inserted
1011 // libcalls), create the new CALLSEQ_START node.
1012 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1014 // Merge in the last call to ensure that this call starts after the last
1016 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1017 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1018 Tmp1, LastCALLSEQ_END);
1019 Tmp1 = LegalizeOp(Tmp1);
1022 // Do not try to legalize the target-specific arguments (#1+).
1023 if (Tmp1 != Node->getOperand(0)) {
1024 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1026 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), &Ops[0],
1027 Ops.size()), Result.getResNo());
1030 // Remember that the CALLSEQ_START is legalized.
1031 AddLegalizedOperand(Op.getValue(0), Result);
1032 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1033 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1035 // Now that the callseq_start and all of the non-call nodes above this call
1036 // sequence have been legalized, legalize the call itself. During this
1037 // process, no libcalls can/will be inserted, guaranteeing that no calls
1039 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1040 // Note that we are selecting this call!
1041 LastCALLSEQ_END = SDValue(CallEnd, 0);
1042 IsLegalizingCall = true;
1044 // Legalize the call, starting from the CALLSEQ_END.
1045 LegalizeOp(LastCALLSEQ_END);
1046 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1049 case ISD::CALLSEQ_END:
1050 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1051 // will cause this node to be legalized as well as handling libcalls right.
1052 if (LastCALLSEQ_END.getNode() != Node) {
1053 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
1054 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1055 assert(I != LegalizedNodes.end() &&
1056 "Legalizing the call start should have legalized this node!");
1060 // Otherwise, the call start has been legalized and everything is going
1061 // according to plan. Just legalize ourselves normally here.
1062 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1063 // Do not try to legalize the target-specific arguments (#1+), except for
1064 // an optional flag input.
1065 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1066 if (Tmp1 != Node->getOperand(0)) {
1067 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1069 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1070 &Ops[0], Ops.size()),
1074 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1075 if (Tmp1 != Node->getOperand(0) ||
1076 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1077 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1080 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1081 &Ops[0], Ops.size()),
1085 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1086 // This finishes up call legalization.
1087 IsLegalizingCall = false;
1089 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1090 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1091 if (Node->getNumValues() == 2)
1092 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1093 return Result.getValue(Op.getResNo());
1095 LoadSDNode *LD = cast<LoadSDNode>(Node);
1096 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1097 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1099 ISD::LoadExtType ExtType = LD->getExtensionType();
1100 if (ExtType == ISD::NON_EXTLOAD) {
1101 EVT VT = Node->getValueType(0);
1102 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1103 Tmp1, Tmp2, LD->getOffset()),
1105 Tmp3 = Result.getValue(0);
1106 Tmp4 = Result.getValue(1);
1108 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1109 default: assert(0 && "This action is not supported yet!");
1110 case TargetLowering::Legal:
1111 // If this is an unaligned load and the target doesn't support it,
1113 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
1114 const Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1115 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
1116 if (LD->getAlignment() < ABIAlignment){
1117 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
1119 Tmp3 = Result.getOperand(0);
1120 Tmp4 = Result.getOperand(1);
1121 Tmp3 = LegalizeOp(Tmp3);
1122 Tmp4 = LegalizeOp(Tmp4);
1126 case TargetLowering::Custom:
1127 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1128 if (Tmp1.getNode()) {
1129 Tmp3 = LegalizeOp(Tmp1);
1130 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1133 case TargetLowering::Promote: {
1134 // Only promote a load of vector type to another.
1135 assert(VT.isVector() && "Cannot promote this load!");
1136 // Change base type to a different vector type.
1137 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1139 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
1140 LD->getSrcValueOffset(),
1141 LD->isVolatile(), LD->isNonTemporal(),
1142 LD->getAlignment());
1143 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp1));
1144 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1148 // Since loads produce two values, make sure to remember that we
1149 // legalized both of them.
1150 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
1151 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
1152 return Op.getResNo() ? Tmp4 : Tmp3;
1154 EVT SrcVT = LD->getMemoryVT();
1155 unsigned SrcWidth = SrcVT.getSizeInBits();
1156 int SVOffset = LD->getSrcValueOffset();
1157 unsigned Alignment = LD->getAlignment();
1158 bool isVolatile = LD->isVolatile();
1159 bool isNonTemporal = LD->isNonTemporal();
1161 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
1162 // Some targets pretend to have an i1 loading operation, and actually
1163 // load an i8. This trick is correct for ZEXTLOAD because the top 7
1164 // bits are guaranteed to be zero; it helps the optimizers understand
1165 // that these bits are zero. It is also useful for EXTLOAD, since it
1166 // tells the optimizers that those bits are undefined. It would be
1167 // nice to have an effective generic way of getting these benefits...
1168 // Until such a way is found, don't insist on promoting i1 here.
1169 (SrcVT != MVT::i1 ||
1170 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
1171 // Promote to a byte-sized load if not loading an integral number of
1172 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
1173 unsigned NewWidth = SrcVT.getStoreSizeInBits();
1174 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
1177 // The extra bits are guaranteed to be zero, since we stored them that
1178 // way. A zext load from NVT thus automatically gives zext from SrcVT.
1180 ISD::LoadExtType NewExtType =
1181 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
1183 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0), dl,
1184 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
1185 NVT, isVolatile, isNonTemporal, Alignment);
1187 Ch = Result.getValue(1); // The chain.
1189 if (ExtType == ISD::SEXTLOAD)
1190 // Having the top bits zero doesn't help when sign extending.
1191 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1192 Result.getValueType(),
1193 Result, DAG.getValueType(SrcVT));
1194 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
1195 // All the top bits are guaranteed to be zero - inform the optimizers.
1196 Result = DAG.getNode(ISD::AssertZext, dl,
1197 Result.getValueType(), Result,
1198 DAG.getValueType(SrcVT));
1200 Tmp1 = LegalizeOp(Result);
1201 Tmp2 = LegalizeOp(Ch);
1202 } else if (SrcWidth & (SrcWidth - 1)) {
1203 // If not loading a power-of-2 number of bits, expand as two loads.
1204 assert(!SrcVT.isVector() && "Unsupported extload!");
1205 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
1206 assert(RoundWidth < SrcWidth);
1207 unsigned ExtraWidth = SrcWidth - RoundWidth;
1208 assert(ExtraWidth < RoundWidth);
1209 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1210 "Load size not an integral number of bytes!");
1211 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
1212 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
1214 unsigned IncrementSize;
1216 if (TLI.isLittleEndian()) {
1217 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1218 // Load the bottom RoundWidth bits.
1219 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), dl,
1221 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
1222 isNonTemporal, Alignment);
1224 // Load the remaining ExtraWidth bits.
1225 IncrementSize = RoundWidth / 8;
1226 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1227 DAG.getIntPtrConstant(IncrementSize));
1228 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), dl, Tmp1, Tmp2,
1229 LD->getSrcValue(), SVOffset + IncrementSize,
1230 ExtraVT, isVolatile, isNonTemporal,
1231 MinAlign(Alignment, IncrementSize));
1233 // Build a factor node to remember that this load is independent of
1235 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1238 // Move the top bits to the right place.
1239 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1240 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
1242 // Join the hi and lo parts.
1243 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1245 // Big endian - avoid unaligned loads.
1246 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1247 // Load the top RoundWidth bits.
1248 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), dl, Tmp1, Tmp2,
1249 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
1250 isNonTemporal, Alignment);
1252 // Load the remaining ExtraWidth bits.
1253 IncrementSize = RoundWidth / 8;
1254 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1255 DAG.getIntPtrConstant(IncrementSize));
1256 Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
1257 Node->getValueType(0), dl, Tmp1, Tmp2,
1258 LD->getSrcValue(), SVOffset + IncrementSize,
1259 ExtraVT, isVolatile, isNonTemporal,
1260 MinAlign(Alignment, IncrementSize));
1262 // Build a factor node to remember that this load is independent of
1264 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1267 // Move the top bits to the right place.
1268 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1269 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
1271 // Join the hi and lo parts.
1272 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1275 Tmp1 = LegalizeOp(Result);
1276 Tmp2 = LegalizeOp(Ch);
1278 switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
1279 default: assert(0 && "This action is not supported yet!");
1280 case TargetLowering::Custom:
1283 case TargetLowering::Legal:
1284 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1285 Tmp1, Tmp2, LD->getOffset()),
1287 Tmp1 = Result.getValue(0);
1288 Tmp2 = Result.getValue(1);
1291 Tmp3 = TLI.LowerOperation(Result, DAG);
1292 if (Tmp3.getNode()) {
1293 Tmp1 = LegalizeOp(Tmp3);
1294 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1297 // If this is an unaligned load and the target doesn't support it,
1299 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
1301 LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1302 unsigned ABIAlignment =
1303 TLI.getTargetData()->getABITypeAlignment(Ty);
1304 if (LD->getAlignment() < ABIAlignment){
1305 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
1307 Tmp1 = Result.getOperand(0);
1308 Tmp2 = Result.getOperand(1);
1309 Tmp1 = LegalizeOp(Tmp1);
1310 Tmp2 = LegalizeOp(Tmp2);
1315 case TargetLowering::Expand:
1316 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT)) {
1317 // FIXME: If SrcVT isn't legal, then this introduces an illegal
1319 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
1320 LD->getSrcValueOffset(),
1321 LD->isVolatile(), LD->isNonTemporal(),
1322 LD->getAlignment());
1326 ExtendOp = (SrcVT.isFloatingPoint() ?
1327 ISD::FP_EXTEND : ISD::ANY_EXTEND);
1329 case ISD::SEXTLOAD: ExtendOp = ISD::SIGN_EXTEND; break;
1330 case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break;
1331 default: llvm_unreachable("Unexpected extend load type!");
1333 Result = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
1334 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1335 Tmp2 = LegalizeOp(Load.getValue(1));
1338 assert(ExtType != ISD::EXTLOAD &&
1339 "EXTLOAD should always be supported!");
1340 // Turn the unsupported load into an EXTLOAD followed by an explicit
1341 // zero/sign extend inreg.
1342 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), dl,
1343 Tmp1, Tmp2, LD->getSrcValue(),
1344 LD->getSrcValueOffset(), SrcVT,
1345 LD->isVolatile(), LD->isNonTemporal(),
1346 LD->getAlignment());
1348 if (ExtType == ISD::SEXTLOAD)
1349 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1350 Result.getValueType(),
1351 Result, DAG.getValueType(SrcVT));
1353 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT);
1354 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1355 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1360 // Since loads produce two values, make sure to remember that we legalized
1362 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
1363 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
1364 return Op.getResNo() ? Tmp2 : Tmp1;
1368 StoreSDNode *ST = cast<StoreSDNode>(Node);
1369 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
1370 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
1371 int SVOffset = ST->getSrcValueOffset();
1372 unsigned Alignment = ST->getAlignment();
1373 bool isVolatile = ST->isVolatile();
1374 bool isNonTemporal = ST->isNonTemporal();
1376 if (!ST->isTruncatingStore()) {
1377 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
1378 Result = SDValue(OptStore, 0);
1383 Tmp3 = LegalizeOp(ST->getValue());
1384 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1389 EVT VT = Tmp3.getValueType();
1390 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1391 default: assert(0 && "This action is not supported yet!");
1392 case TargetLowering::Legal:
1393 // If this is an unaligned store and the target doesn't support it,
1395 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
1396 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
1397 unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty);
1398 if (ST->getAlignment() < ABIAlignment)
1399 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()),
1403 case TargetLowering::Custom:
1404 Tmp1 = TLI.LowerOperation(Result, DAG);
1405 if (Tmp1.getNode()) Result = Tmp1;
1407 case TargetLowering::Promote:
1408 assert(VT.isVector() && "Unknown legal promote case!");
1409 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, dl,
1410 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
1411 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2,
1412 ST->getSrcValue(), SVOffset, isVolatile,
1413 isNonTemporal, Alignment);
1419 Tmp3 = LegalizeOp(ST->getValue());
1421 EVT StVT = ST->getMemoryVT();
1422 unsigned StWidth = StVT.getSizeInBits();
1424 if (StWidth != StVT.getStoreSizeInBits()) {
1425 // Promote to a byte-sized store with upper bits zero if not
1426 // storing an integral number of bytes. For example, promote
1427 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
1428 EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
1429 StVT.getStoreSizeInBits());
1430 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT);
1431 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1432 SVOffset, NVT, isVolatile, isNonTemporal,
1434 } else if (StWidth & (StWidth - 1)) {
1435 // If not storing a power-of-2 number of bits, expand as two stores.
1436 assert(!StVT.isVector() && "Unsupported truncstore!");
1437 unsigned RoundWidth = 1 << Log2_32(StWidth);
1438 assert(RoundWidth < StWidth);
1439 unsigned ExtraWidth = StWidth - RoundWidth;
1440 assert(ExtraWidth < RoundWidth);
1441 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1442 "Store size not an integral number of bytes!");
1443 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
1444 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
1446 unsigned IncrementSize;
1448 if (TLI.isLittleEndian()) {
1449 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
1450 // Store the bottom RoundWidth bits.
1451 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1453 isVolatile, isNonTemporal, Alignment);
1455 // Store the remaining ExtraWidth bits.
1456 IncrementSize = RoundWidth / 8;
1457 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1458 DAG.getIntPtrConstant(IncrementSize));
1459 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
1460 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
1461 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
1462 SVOffset + IncrementSize, ExtraVT, isVolatile,
1464 MinAlign(Alignment, IncrementSize));
1466 // Big endian - avoid unaligned stores.
1467 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
1468 // Store the top RoundWidth bits.
1469 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
1470 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
1471 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
1472 SVOffset, RoundVT, isVolatile, isNonTemporal,
1475 // Store the remaining ExtraWidth bits.
1476 IncrementSize = RoundWidth / 8;
1477 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1478 DAG.getIntPtrConstant(IncrementSize));
1479 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1480 SVOffset + IncrementSize, ExtraVT, isVolatile,
1482 MinAlign(Alignment, IncrementSize));
1485 // The order of the stores doesn't matter.
1486 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
1488 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
1489 Tmp2 != ST->getBasePtr())
1490 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1495 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
1496 default: assert(0 && "This action is not supported yet!");
1497 case TargetLowering::Legal:
1498 // If this is an unaligned store and the target doesn't support it,
1500 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
1501 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
1502 unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty);
1503 if (ST->getAlignment() < ABIAlignment)
1504 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()),
1508 case TargetLowering::Custom:
1509 Result = TLI.LowerOperation(Result, DAG);
1512 // TRUNCSTORE:i16 i32 -> STORE i16
1513 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
1514 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3);
1515 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1516 SVOffset, isVolatile, isNonTemporal,
1525 assert(Result.getValueType() == Op.getValueType() &&
1526 "Bad legalization!");
1528 // Make sure that the generated code is itself legal.
1530 Result = LegalizeOp(Result);
1532 // Note that LegalizeOp may be reentered even from single-use nodes, which
1533 // means that we always must cache transformed nodes.
1534 AddLegalizedOperand(Op, Result);
1538 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1539 SDValue Vec = Op.getOperand(0);
1540 SDValue Idx = Op.getOperand(1);
1541 DebugLoc dl = Op.getDebugLoc();
1542 // Store the value to a temporary stack slot, then LOAD the returned part.
1543 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1544 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0,
1547 // Add the offset to the index.
1549 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1550 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1551 DAG.getConstant(EltSize, Idx.getValueType()));
1553 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1554 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1556 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1558 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1560 if (Op.getValueType().isVector())
1561 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, NULL, 0,
1564 return DAG.getExtLoad(ISD::EXTLOAD, Op.getValueType(), dl, Ch, StackPtr,
1565 NULL, 0, Vec.getValueType().getVectorElementType(),
1569 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1570 // We can't handle this case efficiently. Allocate a sufficiently
1571 // aligned object on the stack, store each element into it, then load
1572 // the result as a vector.
1573 // Create the stack frame object.
1574 EVT VT = Node->getValueType(0);
1575 EVT EltVT = VT.getVectorElementType();
1576 DebugLoc dl = Node->getDebugLoc();
1577 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1578 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1579 const Value *SV = PseudoSourceValue::getFixedStack(FI);
1581 // Emit a store of each element to the stack slot.
1582 SmallVector<SDValue, 8> Stores;
1583 unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1584 // Store (in the right endianness) the elements to memory.
1585 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1586 // Ignore undef elements.
1587 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1589 unsigned Offset = TypeByteSize*i;
1591 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
1592 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1594 // If the destination vector element type is narrower than the source
1595 // element type, only store the bits necessary.
1596 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1597 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1598 Node->getOperand(i), Idx, SV, Offset,
1599 EltVT, false, false, 0));
1601 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
1602 Node->getOperand(i), Idx, SV, Offset,
1607 if (!Stores.empty()) // Not all undef elements?
1608 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1609 &Stores[0], Stores.size());
1611 StoreChain = DAG.getEntryNode();
1613 // Result is a load from the stack slot.
1614 return DAG.getLoad(VT, dl, StoreChain, FIPtr, SV, 0, false, false, 0);
1617 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
1618 DebugLoc dl = Node->getDebugLoc();
1619 SDValue Tmp1 = Node->getOperand(0);
1620 SDValue Tmp2 = Node->getOperand(1);
1622 // Get the sign bit of the RHS. First obtain a value that has the same
1623 // sign as the sign bit, i.e. negative if and only if the sign bit is 1.
1625 EVT FloatVT = Tmp2.getValueType();
1626 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits());
1627 if (isTypeLegal(IVT)) {
1628 // Convert to an integer with the same sign bit.
1629 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, IVT, Tmp2);
1631 // Store the float to memory, then load the sign part out as an integer.
1632 MVT LoadTy = TLI.getPointerTy();
1633 // First create a temporary that is aligned for both the load and store.
1634 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1635 // Then store the float to it.
1637 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, NULL, 0,
1639 if (TLI.isBigEndian()) {
1640 assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1641 // Load out a legal integer with the same sign bit as the float.
1642 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, NULL, 0, false, false, 0);
1643 } else { // Little endian
1644 SDValue LoadPtr = StackPtr;
1645 // The float may be wider than the integer we are going to load. Advance
1646 // the pointer so that the loaded integer will contain the sign bit.
1647 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits();
1648 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8;
1649 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(),
1650 LoadPtr, DAG.getIntPtrConstant(ByteOffset));
1651 // Load a legal integer containing the sign bit.
1652 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, NULL, 0, false, false, 0);
1653 // Move the sign bit to the top bit of the loaded integer.
1654 unsigned BitShift = LoadTy.getSizeInBits() -
1655 (FloatVT.getSizeInBits() - 8 * ByteOffset);
1656 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?");
1658 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit,
1659 DAG.getConstant(BitShift,TLI.getShiftAmountTy()));
1662 // Now get the sign bit proper, by seeing whether the value is negative.
1663 SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()),
1664 SignBit, DAG.getConstant(0, SignBit.getValueType()),
1666 // Get the absolute value of the result.
1667 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1668 // Select between the nabs and abs value based on the sign bit of
1670 return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit,
1671 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1675 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1676 SmallVectorImpl<SDValue> &Results) {
1677 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1678 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1679 " not tell us which reg is the stack pointer!");
1680 DebugLoc dl = Node->getDebugLoc();
1681 EVT VT = Node->getValueType(0);
1682 SDValue Tmp1 = SDValue(Node, 0);
1683 SDValue Tmp2 = SDValue(Node, 1);
1684 SDValue Tmp3 = Node->getOperand(2);
1685 SDValue Chain = Tmp1.getOperand(0);
1687 // Chain the dynamic stack allocation so that it doesn't modify the stack
1688 // pointer when other instructions are using the stack.
1689 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1691 SDValue Size = Tmp2.getOperand(1);
1692 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1693 Chain = SP.getValue(1);
1694 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1695 unsigned StackAlign = TM.getFrameInfo()->getStackAlignment();
1696 if (Align > StackAlign)
1697 SP = DAG.getNode(ISD::AND, dl, VT, SP,
1698 DAG.getConstant(-(uint64_t)Align, VT));
1699 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1700 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1702 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1703 DAG.getIntPtrConstant(0, true), SDValue());
1705 Results.push_back(Tmp1);
1706 Results.push_back(Tmp2);
1709 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
1710 /// condition code CC on the current target. This routine expands SETCC with
1711 /// illegal condition code into AND / OR of multiple SETCC values.
1712 void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1713 SDValue &LHS, SDValue &RHS,
1716 EVT OpVT = LHS.getValueType();
1717 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1718 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1719 default: assert(0 && "Unknown condition code action!");
1720 case TargetLowering::Legal:
1723 case TargetLowering::Expand: {
1724 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1727 default: assert(0 && "Don't know how to expand this condition!");
1728 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break;
1729 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1730 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1731 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1732 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1733 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1734 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1735 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1736 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1737 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1738 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1739 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1740 // FIXME: Implement more expansions.
1743 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1744 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1745 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1753 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
1754 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1755 /// a load from the stack slot to DestVT, extending it if needed.
1756 /// The resultant code need not be legal.
1757 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
1761 // Create the stack frame object.
1763 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType().
1764 getTypeForEVT(*DAG.getContext()));
1765 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1767 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1768 int SPFI = StackPtrFI->getIndex();
1769 const Value *SV = PseudoSourceValue::getFixedStack(SPFI);
1771 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
1772 unsigned SlotSize = SlotVT.getSizeInBits();
1773 unsigned DestSize = DestVT.getSizeInBits();
1774 const Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
1775 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(DestType);
1777 // Emit a store to the stack slot. Use a truncstore if the input value is
1778 // later than DestVT.
1781 if (SrcSize > SlotSize)
1782 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1783 SV, 0, SlotVT, false, false, SrcAlign);
1785 assert(SrcSize == SlotSize && "Invalid store");
1786 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1787 SV, 0, false, false, SrcAlign);
1790 // Result is a load from the stack slot.
1791 if (SlotSize == DestSize)
1792 return DAG.getLoad(DestVT, dl, Store, FIPtr, SV, 0, false, false,
1795 assert(SlotSize < DestSize && "Unknown extension!");
1796 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, dl, Store, FIPtr, SV, 0, SlotVT,
1797 false, false, DestAlign);
1800 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1801 DebugLoc dl = Node->getDebugLoc();
1802 // Create a vector sized/aligned stack slot, store the value to element #0,
1803 // then load the whole vector back out.
1804 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1806 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1807 int SPFI = StackPtrFI->getIndex();
1809 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0),
1811 PseudoSourceValue::getFixedStack(SPFI), 0,
1812 Node->getValueType(0).getVectorElementType(),
1814 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
1815 PseudoSourceValue::getFixedStack(SPFI), 0,
1820 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
1821 /// support the operation, but do support the resultant vector type.
1822 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1823 unsigned NumElems = Node->getNumOperands();
1824 SDValue Value1, Value2;
1825 DebugLoc dl = Node->getDebugLoc();
1826 EVT VT = Node->getValueType(0);
1827 EVT OpVT = Node->getOperand(0).getValueType();
1828 EVT EltVT = VT.getVectorElementType();
1830 // If the only non-undef value is the low element, turn this into a
1831 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1832 bool isOnlyLowElement = true;
1833 bool MoreThanTwoValues = false;
1834 bool isConstant = true;
1835 for (unsigned i = 0; i < NumElems; ++i) {
1836 SDValue V = Node->getOperand(i);
1837 if (V.getOpcode() == ISD::UNDEF)
1840 isOnlyLowElement = false;
1841 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1844 if (!Value1.getNode()) {
1846 } else if (!Value2.getNode()) {
1849 } else if (V != Value1 && V != Value2) {
1850 MoreThanTwoValues = true;
1854 if (!Value1.getNode())
1855 return DAG.getUNDEF(VT);
1857 if (isOnlyLowElement)
1858 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1860 // If all elements are constants, create a load from the constant pool.
1862 std::vector<Constant*> CV;
1863 for (unsigned i = 0, e = NumElems; i != e; ++i) {
1864 if (ConstantFPSDNode *V =
1865 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1866 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1867 } else if (ConstantSDNode *V =
1868 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1870 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1872 // If OpVT and EltVT don't match, EltVT is not legal and the
1873 // element values have been promoted/truncated earlier. Undo this;
1874 // we don't want a v16i8 to become a v16i32 for example.
1875 const ConstantInt *CI = V->getConstantIntValue();
1876 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
1877 CI->getZExtValue()));
1880 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
1881 const Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
1882 CV.push_back(UndefValue::get(OpNTy));
1885 Constant *CP = ConstantVector::get(CV);
1886 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
1887 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
1888 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
1889 PseudoSourceValue::getConstantPool(), 0,
1890 false, false, Alignment);
1893 if (!MoreThanTwoValues) {
1894 SmallVector<int, 8> ShuffleVec(NumElems, -1);
1895 for (unsigned i = 0; i < NumElems; ++i) {
1896 SDValue V = Node->getOperand(i);
1897 if (V.getOpcode() == ISD::UNDEF)
1899 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
1901 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
1902 // Get the splatted value into the low element of a vector register.
1903 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
1905 if (Value2.getNode())
1906 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
1908 Vec2 = DAG.getUNDEF(VT);
1910 // Return shuffle(LowValVec, undef, <0,0,0,0>)
1911 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
1915 // Otherwise, we can't handle this case efficiently.
1916 return ExpandVectorBuildThroughStack(Node);
1919 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
1920 // does not fit into a register, return the lo part and set the hi part to the
1921 // by-reg argument. If it does fit into a single register, return the result
1922 // and leave the Hi part unset.
1923 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
1925 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
1926 // The input chain to this libcall is the entry node of the function.
1927 // Legalizing the call will automatically add the previous call to the
1929 SDValue InChain = DAG.getEntryNode();
1931 TargetLowering::ArgListTy Args;
1932 TargetLowering::ArgListEntry Entry;
1933 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1934 EVT ArgVT = Node->getOperand(i).getValueType();
1935 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1936 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
1937 Entry.isSExt = isSigned;
1938 Entry.isZExt = !isSigned;
1939 Args.push_back(Entry);
1941 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1942 TLI.getPointerTy());
1944 // Splice the libcall in wherever FindInputOutputChains tells us to.
1945 const Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
1946 std::pair<SDValue, SDValue> CallInfo =
1947 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
1948 0, TLI.getLibcallCallingConv(LC), false,
1949 /*isReturnValueUsed=*/true,
1950 Callee, Args, DAG, Node->getDebugLoc());
1952 // Legalize the call sequence, starting with the chain. This will advance
1953 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
1954 // was added by LowerCallTo (guaranteeing proper serialization of calls).
1955 LegalizeOp(CallInfo.second);
1956 return CallInfo.first;
1959 // ExpandChainLibCall - Expand a node into a call to a libcall. Similar to
1960 // ExpandLibCall except that the first operand is the in-chain.
1961 std::pair<SDValue, SDValue>
1962 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
1965 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
1966 SDValue InChain = Node->getOperand(0);
1968 TargetLowering::ArgListTy Args;
1969 TargetLowering::ArgListEntry Entry;
1970 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) {
1971 EVT ArgVT = Node->getOperand(i).getValueType();
1972 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1973 Entry.Node = Node->getOperand(i);
1975 Entry.isSExt = isSigned;
1976 Entry.isZExt = !isSigned;
1977 Args.push_back(Entry);
1979 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1980 TLI.getPointerTy());
1982 // Splice the libcall in wherever FindInputOutputChains tells us to.
1983 const Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
1984 std::pair<SDValue, SDValue> CallInfo =
1985 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
1986 0, TLI.getLibcallCallingConv(LC), false,
1987 /*isReturnValueUsed=*/true,
1988 Callee, Args, DAG, Node->getDebugLoc());
1990 // Legalize the call sequence, starting with the chain. This will advance
1991 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
1992 // was added by LowerCallTo (guaranteeing proper serialization of calls).
1993 LegalizeOp(CallInfo.second);
1997 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
1998 RTLIB::Libcall Call_F32,
1999 RTLIB::Libcall Call_F64,
2000 RTLIB::Libcall Call_F80,
2001 RTLIB::Libcall Call_PPCF128) {
2003 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
2004 default: assert(0 && "Unexpected request for libcall!");
2005 case MVT::f32: LC = Call_F32; break;
2006 case MVT::f64: LC = Call_F64; break;
2007 case MVT::f80: LC = Call_F80; break;
2008 case MVT::ppcf128: LC = Call_PPCF128; break;
2010 return ExpandLibCall(LC, Node, false);
2013 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
2014 RTLIB::Libcall Call_I8,
2015 RTLIB::Libcall Call_I16,
2016 RTLIB::Libcall Call_I32,
2017 RTLIB::Libcall Call_I64,
2018 RTLIB::Libcall Call_I128) {
2020 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
2021 default: assert(0 && "Unexpected request for libcall!");
2022 case MVT::i8: LC = Call_I8; break;
2023 case MVT::i16: LC = Call_I16; break;
2024 case MVT::i32: LC = Call_I32; break;
2025 case MVT::i64: LC = Call_I64; break;
2026 case MVT::i128: LC = Call_I128; break;
2028 return ExpandLibCall(LC, Node, isSigned);
2031 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
2032 /// INT_TO_FP operation of the specified operand when the target requests that
2033 /// we expand it. At this point, we know that the result and operand types are
2034 /// legal for the target.
2035 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
2039 if (Op0.getValueType() == MVT::i32) {
2040 // simple 32-bit [signed|unsigned] integer to float/double expansion
2042 // Get the stack frame index of a 8 byte buffer.
2043 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2045 // word offset constant for Hi/Lo address computation
2046 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
2047 // set up Hi and Lo (into buffer) address based on endian
2048 SDValue Hi = StackSlot;
2049 SDValue Lo = DAG.getNode(ISD::ADD, dl,
2050 TLI.getPointerTy(), StackSlot, WordOff);
2051 if (TLI.isLittleEndian())
2054 // if signed map to unsigned space
2057 // constant used to invert sign bit (signed to unsigned mapping)
2058 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
2059 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2063 // store the lo of the constructed double - based on integer input
2064 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
2065 Op0Mapped, Lo, NULL, 0,
2067 // initial hi portion of constructed double
2068 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
2069 // store the hi of the constructed double - biased exponent
2070 SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0,
2072 // load the constructed double
2073 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0,
2075 // FP constant to bias correct the final result
2076 SDValue Bias = DAG.getConstantFP(isSigned ?
2077 BitsToDouble(0x4330000080000000ULL) :
2078 BitsToDouble(0x4330000000000000ULL),
2080 // subtract the bias
2081 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2084 // handle final rounding
2085 if (DestVT == MVT::f64) {
2088 } else if (DestVT.bitsLT(MVT::f64)) {
2089 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2090 DAG.getIntPtrConstant(0));
2091 } else if (DestVT.bitsGT(MVT::f64)) {
2092 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2096 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2097 // Code below here assumes !isSigned without checking again.
2099 // Implementation of unsigned i64 to f64 following the algorithm in
2100 // __floatundidf in compiler_rt. This implementation has the advantage
2101 // of performing rounding correctly, both in the default rounding mode
2102 // and in all alternate rounding modes.
2103 // TODO: Generalize this for use with other types.
2104 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
2106 DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64);
2107 SDValue TwoP84PlusTwoP52 =
2108 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64);
2110 DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64);
2112 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32);
2113 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2114 DAG.getConstant(32, MVT::i64));
2115 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2116 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2117 SDValue LoFlt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, LoOr);
2118 SDValue HiFlt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, HiOr);
2119 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
2121 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
2124 // Implementation of unsigned i64 to f32. This implementation has the
2125 // advantage of performing rounding correctly.
2126 // TODO: Generalize this for use with other types.
2127 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) {
2128 EVT SHVT = TLI.getShiftAmountTy();
2130 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2131 DAG.getConstant(UINT64_C(0xfffffffffffff800), MVT::i64));
2132 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
2133 DAG.getConstant(UINT64_C(0x800), MVT::i64));
2134 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2135 DAG.getConstant(UINT64_C(0x7ff), MVT::i64));
2136 SDValue Ne = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2137 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE);
2138 SDValue Sel = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ne, Or, Op0);
2139 SDValue Ge = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2140 Op0, DAG.getConstant(UINT64_C(0x0020000000000000), MVT::i64),
2142 SDValue Sel2 = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ge, Sel, Op0);
2144 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2145 DAG.getConstant(32, SHVT));
2146 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh);
2147 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc);
2149 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), MVT::f64);
2150 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt);
2151 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2);
2152 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo);
2153 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2);
2154 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd,
2155 DAG.getIntPtrConstant(0));
2159 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2161 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()),
2162 Op0, DAG.getConstant(0, Op0.getValueType()),
2164 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
2165 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
2166 SignSet, Four, Zero);
2168 // If the sign bit of the integer is set, the large number will be treated
2169 // as a negative number. To counteract this, the dynamic code adds an
2170 // offset depending on the data type.
2172 switch (Op0.getValueType().getSimpleVT().SimpleTy) {
2173 default: assert(0 && "Unsupported integer type!");
2174 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2175 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2176 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2177 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2179 if (TLI.isLittleEndian()) FF <<= 32;
2180 Constant *FudgeFactor = ConstantInt::get(
2181 Type::getInt64Ty(*DAG.getContext()), FF);
2183 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
2184 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2185 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
2186 Alignment = std::min(Alignment, 4u);
2188 if (DestVT == MVT::f32)
2189 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2190 PseudoSourceValue::getConstantPool(), 0,
2191 false, false, Alignment);
2194 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT, dl,
2195 DAG.getEntryNode(), CPIdx,
2196 PseudoSourceValue::getConstantPool(), 0,
2197 MVT::f32, false, false, Alignment));
2200 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2203 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
2204 /// *INT_TO_FP operation of the specified operand when the target requests that
2205 /// we promote it. At this point, we know that the result and operand types are
2206 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2207 /// operation that takes a larger input.
2208 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2212 // First step, figure out the appropriate *INT_TO_FP operation to use.
2213 EVT NewInTy = LegalOp.getValueType();
2215 unsigned OpToUse = 0;
2217 // Scan for the appropriate larger type to use.
2219 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2220 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2222 // If the target supports SINT_TO_FP of this type, use it.
2223 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2224 OpToUse = ISD::SINT_TO_FP;
2227 if (isSigned) continue;
2229 // If the target supports UINT_TO_FP of this type, use it.
2230 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2231 OpToUse = ISD::UINT_TO_FP;
2235 // Otherwise, try a larger type.
2238 // Okay, we found the operation and type to use. Zero extend our input to the
2239 // desired type then run the operation on it.
2240 return DAG.getNode(OpToUse, dl, DestVT,
2241 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2242 dl, NewInTy, LegalOp));
2245 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
2246 /// FP_TO_*INT operation of the specified operand when the target requests that
2247 /// we promote it. At this point, we know that the result and operand types are
2248 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2249 /// operation that returns a larger result.
2250 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2254 // First step, figure out the appropriate FP_TO*INT operation to use.
2255 EVT NewOutTy = DestVT;
2257 unsigned OpToUse = 0;
2259 // Scan for the appropriate larger type to use.
2261 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2262 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2264 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2265 OpToUse = ISD::FP_TO_SINT;
2269 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2270 OpToUse = ISD::FP_TO_UINT;
2274 // Otherwise, try a larger type.
2278 // Okay, we found the operation and type to use.
2279 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2281 // Truncate the result of the extended FP_TO_*INT operation to the desired
2283 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2286 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
2288 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) {
2289 EVT VT = Op.getValueType();
2290 EVT SHVT = TLI.getShiftAmountTy();
2291 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2292 switch (VT.getSimpleVT().SimpleTy) {
2293 default: assert(0 && "Unhandled Expand type in BSWAP!");
2295 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2296 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2297 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2299 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2300 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2301 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2302 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2303 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
2304 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
2305 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2306 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2307 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2309 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
2310 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
2311 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2312 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2313 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2314 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2315 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
2316 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
2317 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
2318 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
2319 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
2320 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
2321 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
2322 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
2323 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2324 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2325 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2326 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2327 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2328 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2329 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2333 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
2335 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2338 default: assert(0 && "Cannot expand this yet!");
2340 static const uint64_t mask[6] = {
2341 0x5555555555555555ULL, 0x3333333333333333ULL,
2342 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
2343 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
2345 EVT VT = Op.getValueType();
2346 EVT ShVT = TLI.getShiftAmountTy();
2347 unsigned len = VT.getSizeInBits();
2348 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2349 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
2350 unsigned EltSize = VT.isVector() ?
2351 VT.getVectorElementType().getSizeInBits() : len;
2352 SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT);
2353 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2354 Op = DAG.getNode(ISD::ADD, dl, VT,
2355 DAG.getNode(ISD::AND, dl, VT, Op, Tmp2),
2356 DAG.getNode(ISD::AND, dl, VT,
2357 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3),
2363 // for now, we do this:
2364 // x = x | (x >> 1);
2365 // x = x | (x >> 2);
2367 // x = x | (x >>16);
2368 // x = x | (x >>32); // for 64-bit input
2369 // return popcount(~x);
2371 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
2372 EVT VT = Op.getValueType();
2373 EVT ShVT = TLI.getShiftAmountTy();
2374 unsigned len = VT.getSizeInBits();
2375 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2376 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2377 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2378 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2380 Op = DAG.getNOT(dl, Op, VT);
2381 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2384 // for now, we use: { return popcount(~x & (x - 1)); }
2385 // unless the target has ctlz but not ctpop, in which case we use:
2386 // { return 32 - nlz(~x & (x-1)); }
2387 // see also http://www.hackersdelight.org/HDcode/ntz.cc
2388 EVT VT = Op.getValueType();
2389 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2390 DAG.getNOT(dl, Op, VT),
2391 DAG.getNode(ISD::SUB, dl, VT, Op,
2392 DAG.getConstant(1, VT)));
2393 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2394 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2395 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2396 return DAG.getNode(ISD::SUB, dl, VT,
2397 DAG.getConstant(VT.getSizeInBits(), VT),
2398 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2399 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2404 std::pair <SDValue, SDValue> SelectionDAGLegalize::ExpandAtomic(SDNode *Node) {
2405 unsigned Opc = Node->getOpcode();
2406 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
2411 llvm_unreachable("Unhandled atomic intrinsic Expand!");
2413 case ISD::ATOMIC_SWAP:
2414 switch (VT.SimpleTy) {
2415 default: llvm_unreachable("Unexpected value type for atomic!");
2416 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break;
2417 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
2418 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
2419 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
2422 case ISD::ATOMIC_CMP_SWAP:
2423 switch (VT.SimpleTy) {
2424 default: llvm_unreachable("Unexpected value type for atomic!");
2425 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break;
2426 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;
2427 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;
2428 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
2431 case ISD::ATOMIC_LOAD_ADD:
2432 switch (VT.SimpleTy) {
2433 default: llvm_unreachable("Unexpected value type for atomic!");
2434 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break;
2435 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;
2436 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;
2437 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
2440 case ISD::ATOMIC_LOAD_SUB:
2441 switch (VT.SimpleTy) {
2442 default: llvm_unreachable("Unexpected value type for atomic!");
2443 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break;
2444 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;
2445 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;
2446 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
2449 case ISD::ATOMIC_LOAD_AND:
2450 switch (VT.SimpleTy) {
2451 default: llvm_unreachable("Unexpected value type for atomic!");
2452 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break;
2453 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;
2454 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;
2455 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
2458 case ISD::ATOMIC_LOAD_OR:
2459 switch (VT.SimpleTy) {
2460 default: llvm_unreachable("Unexpected value type for atomic!");
2461 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break;
2462 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;
2463 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;
2464 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
2467 case ISD::ATOMIC_LOAD_XOR:
2468 switch (VT.SimpleTy) {
2469 default: llvm_unreachable("Unexpected value type for atomic!");
2470 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break;
2471 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;
2472 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;
2473 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
2476 case ISD::ATOMIC_LOAD_NAND:
2477 switch (VT.SimpleTy) {
2478 default: llvm_unreachable("Unexpected value type for atomic!");
2479 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break;
2480 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;
2481 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;
2482 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
2487 return ExpandChainLibCall(LC, Node, false);
2490 void SelectionDAGLegalize::ExpandNode(SDNode *Node,
2491 SmallVectorImpl<SDValue> &Results) {
2492 DebugLoc dl = Node->getDebugLoc();
2493 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2494 switch (Node->getOpcode()) {
2498 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
2499 Results.push_back(Tmp1);
2502 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2504 case ISD::FRAMEADDR:
2505 case ISD::RETURNADDR:
2506 case ISD::FRAME_TO_ARGS_OFFSET:
2507 Results.push_back(DAG.getConstant(0, Node->getValueType(0)));
2509 case ISD::FLT_ROUNDS_:
2510 Results.push_back(DAG.getConstant(1, Node->getValueType(0)));
2512 case ISD::EH_RETURN:
2516 case ISD::EH_SJLJ_LONGJMP:
2517 Results.push_back(Node->getOperand(0));
2519 case ISD::EH_SJLJ_SETJMP:
2520 Results.push_back(DAG.getConstant(0, MVT::i32));
2521 Results.push_back(Node->getOperand(0));
2523 case ISD::MEMBARRIER: {
2524 // If the target didn't lower this, lower it to '__sync_synchronize()' call
2525 TargetLowering::ArgListTy Args;
2526 std::pair<SDValue, SDValue> CallResult =
2527 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()),
2528 false, false, false, false, 0, CallingConv::C, false,
2529 /*isReturnValueUsed=*/true,
2530 DAG.getExternalSymbol("__sync_synchronize",
2531 TLI.getPointerTy()),
2533 Results.push_back(CallResult.second);
2536 // By default, atomic intrinsics are marked Legal and lowered. Targets
2537 // which don't support them directly, however, may want libcalls, in which
2538 // case they mark them Expand, and we get here.
2539 // FIXME: Unimplemented for now. Add libcalls.
2540 case ISD::ATOMIC_SWAP:
2541 case ISD::ATOMIC_LOAD_ADD:
2542 case ISD::ATOMIC_LOAD_SUB:
2543 case ISD::ATOMIC_LOAD_AND:
2544 case ISD::ATOMIC_LOAD_OR:
2545 case ISD::ATOMIC_LOAD_XOR:
2546 case ISD::ATOMIC_LOAD_NAND:
2547 case ISD::ATOMIC_LOAD_MIN:
2548 case ISD::ATOMIC_LOAD_MAX:
2549 case ISD::ATOMIC_LOAD_UMIN:
2550 case ISD::ATOMIC_LOAD_UMAX:
2551 case ISD::ATOMIC_CMP_SWAP: {
2552 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node);
2553 Results.push_back(Tmp.first);
2554 Results.push_back(Tmp.second);
2557 case ISD::DYNAMIC_STACKALLOC:
2558 ExpandDYNAMIC_STACKALLOC(Node, Results);
2560 case ISD::MERGE_VALUES:
2561 for (unsigned i = 0; i < Node->getNumValues(); i++)
2562 Results.push_back(Node->getOperand(i));
2565 EVT VT = Node->getValueType(0);
2567 Results.push_back(DAG.getConstant(0, VT));
2569 assert(VT.isFloatingPoint() && "Unknown value type!");
2570 Results.push_back(DAG.getConstantFP(0, VT));
2575 // If this operation is not supported, lower it to 'abort()' call
2576 TargetLowering::ArgListTy Args;
2577 std::pair<SDValue, SDValue> CallResult =
2578 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()),
2579 false, false, false, false, 0, CallingConv::C, false,
2580 /*isReturnValueUsed=*/true,
2581 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
2583 Results.push_back(CallResult.second);
2587 case ISD::BIT_CONVERT:
2588 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
2589 Node->getValueType(0), dl);
2590 Results.push_back(Tmp1);
2592 case ISD::FP_EXTEND:
2593 Tmp1 = EmitStackConvert(Node->getOperand(0),
2594 Node->getOperand(0).getValueType(),
2595 Node->getValueType(0), dl);
2596 Results.push_back(Tmp1);
2598 case ISD::SIGN_EXTEND_INREG: {
2599 // NOTE: we could fall back on load/store here too for targets without
2600 // SAR. However, it is doubtful that any exist.
2601 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2602 EVT VT = Node->getValueType(0);
2603 EVT ShiftAmountTy = TLI.getShiftAmountTy();
2606 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
2607 ExtraVT.getScalarType().getSizeInBits();
2608 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy);
2609 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
2610 Node->getOperand(0), ShiftCst);
2611 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
2612 Results.push_back(Tmp1);
2615 case ISD::FP_ROUND_INREG: {
2616 // The only way we can lower this is to turn it into a TRUNCSTORE,
2617 // EXTLOAD pair, targetting a temporary location (a stack slot).
2619 // NOTE: there is a choice here between constantly creating new stack
2620 // slots and always reusing the same one. We currently always create
2621 // new ones, as reuse may inhibit scheduling.
2622 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2623 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
2624 Node->getValueType(0), dl);
2625 Results.push_back(Tmp1);
2628 case ISD::SINT_TO_FP:
2629 case ISD::UINT_TO_FP:
2630 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
2631 Node->getOperand(0), Node->getValueType(0), dl);
2632 Results.push_back(Tmp1);
2634 case ISD::FP_TO_UINT: {
2635 SDValue True, False;
2636 EVT VT = Node->getOperand(0).getValueType();
2637 EVT NVT = Node->getValueType(0);
2638 const uint64_t zero[] = {0, 0};
2639 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero));
2640 APInt x = APInt::getSignBit(NVT.getSizeInBits());
2641 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
2642 Tmp1 = DAG.getConstantFP(apf, VT);
2643 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
2644 Node->getOperand(0),
2646 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
2647 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
2648 DAG.getNode(ISD::FSUB, dl, VT,
2649 Node->getOperand(0), Tmp1));
2650 False = DAG.getNode(ISD::XOR, dl, NVT, False,
2651 DAG.getConstant(x, NVT));
2652 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False);
2653 Results.push_back(Tmp1);
2657 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2658 EVT VT = Node->getValueType(0);
2659 Tmp1 = Node->getOperand(0);
2660 Tmp2 = Node->getOperand(1);
2661 unsigned Align = Node->getConstantOperandVal(3);
2663 SDValue VAListLoad = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0,
2665 SDValue VAList = VAListLoad;
2667 if (Align > TLI.getMinStackArgumentAlignment()) {
2668 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
2670 VAList = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
2671 DAG.getConstant(Align - 1,
2672 TLI.getPointerTy()));
2674 VAList = DAG.getNode(ISD::AND, dl, TLI.getPointerTy(), VAList,
2675 DAG.getConstant(-Align,
2676 TLI.getPointerTy()));
2679 // Increment the pointer, VAList, to the next vaarg
2680 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
2681 DAG.getConstant(TLI.getTargetData()->
2682 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())),
2683 TLI.getPointerTy()));
2684 // Store the incremented VAList to the legalized pointer
2685 Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2, V, 0,
2687 // Load the actual argument out of the pointer VAList
2688 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, NULL, 0,
2690 Results.push_back(Results[0].getValue(1));
2694 // This defaults to loading a pointer from the input and storing it to the
2695 // output, returning the chain.
2696 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
2697 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
2698 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0),
2699 Node->getOperand(2), VS, 0, false, false, 0);
2700 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1), VD, 0,
2702 Results.push_back(Tmp1);
2705 case ISD::EXTRACT_VECTOR_ELT:
2706 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
2707 // This must be an access of the only element. Return it.
2708 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0),
2709 Node->getOperand(0));
2711 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
2712 Results.push_back(Tmp1);
2714 case ISD::EXTRACT_SUBVECTOR:
2715 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
2717 case ISD::CONCAT_VECTORS: {
2718 Results.push_back(ExpandVectorBuildThroughStack(Node));
2721 case ISD::SCALAR_TO_VECTOR:
2722 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
2724 case ISD::INSERT_VECTOR_ELT:
2725 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
2726 Node->getOperand(1),
2727 Node->getOperand(2), dl));
2729 case ISD::VECTOR_SHUFFLE: {
2730 SmallVector<int, 8> Mask;
2731 cast<ShuffleVectorSDNode>(Node)->getMask(Mask);
2733 EVT VT = Node->getValueType(0);
2734 EVT EltVT = VT.getVectorElementType();
2735 if (getTypeAction(EltVT) == Promote)
2736 EltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
2737 unsigned NumElems = VT.getVectorNumElements();
2738 SmallVector<SDValue, 8> Ops;
2739 for (unsigned i = 0; i != NumElems; ++i) {
2741 Ops.push_back(DAG.getUNDEF(EltVT));
2744 unsigned Idx = Mask[i];
2746 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
2747 Node->getOperand(0),
2748 DAG.getIntPtrConstant(Idx)));
2750 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
2751 Node->getOperand(1),
2752 DAG.getIntPtrConstant(Idx - NumElems)));
2754 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
2755 Results.push_back(Tmp1);
2758 case ISD::EXTRACT_ELEMENT: {
2759 EVT OpTy = Node->getOperand(0).getValueType();
2760 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
2762 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
2763 DAG.getConstant(OpTy.getSizeInBits()/2,
2764 TLI.getShiftAmountTy()));
2765 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
2768 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
2769 Node->getOperand(0));
2771 Results.push_back(Tmp1);
2774 case ISD::STACKSAVE:
2775 // Expand to CopyFromReg if the target set
2776 // StackPointerRegisterToSaveRestore.
2777 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2778 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
2779 Node->getValueType(0)));
2780 Results.push_back(Results[0].getValue(1));
2782 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
2783 Results.push_back(Node->getOperand(0));
2786 case ISD::STACKRESTORE:
2787 // Expand to CopyToReg if the target set
2788 // StackPointerRegisterToSaveRestore.
2789 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2790 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
2791 Node->getOperand(1)));
2793 Results.push_back(Node->getOperand(0));
2796 case ISD::FCOPYSIGN:
2797 Results.push_back(ExpandFCOPYSIGN(Node));
2800 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2801 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2802 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
2803 Node->getOperand(0));
2804 Results.push_back(Tmp1);
2807 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2808 EVT VT = Node->getValueType(0);
2809 Tmp1 = Node->getOperand(0);
2810 Tmp2 = DAG.getConstantFP(0.0, VT);
2811 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
2812 Tmp1, Tmp2, ISD::SETUGT);
2813 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
2814 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3);
2815 Results.push_back(Tmp1);
2819 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
2820 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128));
2823 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
2824 RTLIB::SIN_F80, RTLIB::SIN_PPCF128));
2827 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
2828 RTLIB::COS_F80, RTLIB::COS_PPCF128));
2831 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
2832 RTLIB::LOG_F80, RTLIB::LOG_PPCF128));
2835 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
2836 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128));
2839 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
2840 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128));
2843 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
2844 RTLIB::EXP_F80, RTLIB::EXP_PPCF128));
2847 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
2848 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128));
2851 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
2852 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128));
2855 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
2856 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128));
2859 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
2860 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128));
2863 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
2864 RTLIB::RINT_F80, RTLIB::RINT_PPCF128));
2866 case ISD::FNEARBYINT:
2867 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
2868 RTLIB::NEARBYINT_F64,
2869 RTLIB::NEARBYINT_F80,
2870 RTLIB::NEARBYINT_PPCF128));
2873 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
2874 RTLIB::POWI_F80, RTLIB::POWI_PPCF128));
2877 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
2878 RTLIB::POW_F80, RTLIB::POW_PPCF128));
2881 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
2882 RTLIB::DIV_F80, RTLIB::DIV_PPCF128));
2885 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
2886 RTLIB::REM_F80, RTLIB::REM_PPCF128));
2888 case ISD::FP16_TO_FP32:
2889 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
2891 case ISD::FP32_TO_FP16:
2892 Results.push_back(ExpandLibCall(RTLIB::FPROUND_F32_F16, Node, false));
2894 case ISD::ConstantFP: {
2895 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
2896 // Check to see if this FP immediate is already legal.
2897 // If this is a legal constant, turn it into a TargetConstantFP node.
2898 if (TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
2899 Results.push_back(SDValue(Node, 0));
2901 Results.push_back(ExpandConstantFP(CFP, true, DAG, TLI));
2904 case ISD::EHSELECTION: {
2905 unsigned Reg = TLI.getExceptionSelectorRegister();
2906 assert(Reg && "Can't expand to unknown register!");
2907 Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg,
2908 Node->getValueType(0)));
2909 Results.push_back(Results[0].getValue(1));
2912 case ISD::EXCEPTIONADDR: {
2913 unsigned Reg = TLI.getExceptionAddressRegister();
2914 assert(Reg && "Can't expand to unknown register!");
2915 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg,
2916 Node->getValueType(0)));
2917 Results.push_back(Results[0].getValue(1));
2921 EVT VT = Node->getValueType(0);
2922 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
2923 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
2924 "Don't know how to expand this subtraction!");
2925 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
2926 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
2927 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT));
2928 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
2933 EVT VT = Node->getValueType(0);
2934 SDVTList VTs = DAG.getVTList(VT, VT);
2935 bool isSigned = Node->getOpcode() == ISD::SREM;
2936 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
2937 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2938 Tmp2 = Node->getOperand(0);
2939 Tmp3 = Node->getOperand(1);
2940 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) {
2941 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
2942 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
2944 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
2945 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
2946 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
2947 } else if (isSigned) {
2948 Tmp1 = ExpandIntLibCall(Node, true,
2950 RTLIB::SREM_I16, RTLIB::SREM_I32,
2951 RTLIB::SREM_I64, RTLIB::SREM_I128);
2953 Tmp1 = ExpandIntLibCall(Node, false,
2955 RTLIB::UREM_I16, RTLIB::UREM_I32,
2956 RTLIB::UREM_I64, RTLIB::UREM_I128);
2958 Results.push_back(Tmp1);
2963 bool isSigned = Node->getOpcode() == ISD::SDIV;
2964 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2965 EVT VT = Node->getValueType(0);
2966 SDVTList VTs = DAG.getVTList(VT, VT);
2967 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT))
2968 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
2969 Node->getOperand(1));
2971 Tmp1 = ExpandIntLibCall(Node, true,
2973 RTLIB::SDIV_I16, RTLIB::SDIV_I32,
2974 RTLIB::SDIV_I64, RTLIB::SDIV_I128);
2976 Tmp1 = ExpandIntLibCall(Node, false,
2978 RTLIB::UDIV_I16, RTLIB::UDIV_I32,
2979 RTLIB::UDIV_I64, RTLIB::UDIV_I128);
2980 Results.push_back(Tmp1);
2985 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
2987 EVT VT = Node->getValueType(0);
2988 SDVTList VTs = DAG.getVTList(VT, VT);
2989 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
2990 "If this wasn't legal, it shouldn't have been created!");
2991 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
2992 Node->getOperand(1));
2993 Results.push_back(Tmp1.getValue(1));
2997 EVT VT = Node->getValueType(0);
2998 SDVTList VTs = DAG.getVTList(VT, VT);
2999 // See if multiply or divide can be lowered using two-result operations.
3000 // We just need the low half of the multiply; try both the signed
3001 // and unsigned forms. If the target supports both SMUL_LOHI and
3002 // UMUL_LOHI, form a preference by checking which forms of plain
3003 // MULH it supports.
3004 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3005 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3006 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3007 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3008 unsigned OpToUse = 0;
3009 if (HasSMUL_LOHI && !HasMULHS) {
3010 OpToUse = ISD::SMUL_LOHI;
3011 } else if (HasUMUL_LOHI && !HasMULHU) {
3012 OpToUse = ISD::UMUL_LOHI;
3013 } else if (HasSMUL_LOHI) {
3014 OpToUse = ISD::SMUL_LOHI;
3015 } else if (HasUMUL_LOHI) {
3016 OpToUse = ISD::UMUL_LOHI;
3019 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
3020 Node->getOperand(1)));
3023 Tmp1 = ExpandIntLibCall(Node, false,
3025 RTLIB::MUL_I16, RTLIB::MUL_I32,
3026 RTLIB::MUL_I64, RTLIB::MUL_I128);
3027 Results.push_back(Tmp1);
3032 SDValue LHS = Node->getOperand(0);
3033 SDValue RHS = Node->getOperand(1);
3034 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3035 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3037 Results.push_back(Sum);
3038 EVT OType = Node->getValueType(1);
3040 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
3042 // LHSSign -> LHS >= 0
3043 // RHSSign -> RHS >= 0
3044 // SumSign -> Sum >= 0
3047 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3049 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3051 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3052 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3053 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
3054 Node->getOpcode() == ISD::SADDO ?
3055 ISD::SETEQ : ISD::SETNE);
3057 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3058 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3060 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3061 Results.push_back(Cmp);
3066 SDValue LHS = Node->getOperand(0);
3067 SDValue RHS = Node->getOperand(1);
3068 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
3069 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3071 Results.push_back(Sum);
3072 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS,
3073 Node->getOpcode () == ISD::UADDO ?
3074 ISD::SETULT : ISD::SETUGT));
3079 EVT VT = Node->getValueType(0);
3080 SDValue LHS = Node->getOperand(0);
3081 SDValue RHS = Node->getOperand(1);
3084 static const unsigned Ops[2][3] =
3085 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
3086 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
3087 bool isSigned = Node->getOpcode() == ISD::SMULO;
3088 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3089 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3090 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3091 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3092 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3094 TopHalf = BottomHalf.getValue(1);
3096 // FIXME: We should be able to fall back to a libcall with an illegal
3097 // type in some cases.
3098 // Also, we can fall back to a division in some cases, but that's a big
3099 // performance hit in the general case.
3100 assert(TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(),
3101 VT.getSizeInBits() * 2)) &&
3102 "Don't know how to expand this operation yet!");
3103 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
3104 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
3105 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
3106 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
3107 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3108 DAG.getIntPtrConstant(0));
3109 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3110 DAG.getIntPtrConstant(1));
3113 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1, TLI.getShiftAmountTy());
3114 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3115 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1,
3118 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf,
3119 DAG.getConstant(0, VT), ISD::SETNE);
3121 Results.push_back(BottomHalf);
3122 Results.push_back(TopHalf);
3125 case ISD::BUILD_PAIR: {
3126 EVT PairTy = Node->getValueType(0);
3127 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3128 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3129 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
3130 DAG.getConstant(PairTy.getSizeInBits()/2,
3131 TLI.getShiftAmountTy()));
3132 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3136 Tmp1 = Node->getOperand(0);
3137 Tmp2 = Node->getOperand(1);
3138 Tmp3 = Node->getOperand(2);
3139 if (Tmp1.getOpcode() == ISD::SETCC) {
3140 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3142 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3144 Tmp1 = DAG.getSelectCC(dl, Tmp1,
3145 DAG.getConstant(0, Tmp1.getValueType()),
3146 Tmp2, Tmp3, ISD::SETNE);
3148 Results.push_back(Tmp1);
3151 SDValue Chain = Node->getOperand(0);
3152 SDValue Table = Node->getOperand(1);
3153 SDValue Index = Node->getOperand(2);
3155 EVT PTy = TLI.getPointerTy();
3157 const TargetData &TD = *TLI.getTargetData();
3158 unsigned EntrySize =
3159 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
3161 Index = DAG.getNode(ISD::MUL, dl, PTy,
3162 Index, DAG.getConstant(EntrySize, PTy));
3163 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
3165 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
3166 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, PTy, dl, Chain, Addr,
3167 PseudoSourceValue::getJumpTable(), 0, MemVT,
3170 if (TM.getRelocationModel() == Reloc::PIC_) {
3171 // For PIC, the sequence is:
3172 // BRIND(load(Jumptable + index) + RelocBase)
3173 // RelocBase can be JumpTable, GOT or some sort of global base.
3174 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3175 TLI.getPICJumpTableRelocBase(Table, DAG));
3177 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
3178 Results.push_back(Tmp1);
3182 // Expand brcond's setcc into its constituent parts and create a BR_CC
3184 Tmp1 = Node->getOperand(0);
3185 Tmp2 = Node->getOperand(1);
3186 if (Tmp2.getOpcode() == ISD::SETCC) {
3187 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3188 Tmp1, Tmp2.getOperand(2),
3189 Tmp2.getOperand(0), Tmp2.getOperand(1),
3190 Node->getOperand(2));
3192 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3193 DAG.getCondCode(ISD::SETNE), Tmp2,
3194 DAG.getConstant(0, Tmp2.getValueType()),
3195 Node->getOperand(2));
3197 Results.push_back(Tmp1);
3200 Tmp1 = Node->getOperand(0);
3201 Tmp2 = Node->getOperand(1);
3202 Tmp3 = Node->getOperand(2);
3203 LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl);
3205 // If we expanded the SETCC into an AND/OR, return the new node
3206 if (Tmp2.getNode() == 0) {
3207 Results.push_back(Tmp1);
3211 // Otherwise, SETCC for the given comparison type must be completely
3212 // illegal; expand it into a SELECT_CC.
3213 EVT VT = Node->getValueType(0);
3214 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3215 DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3);
3216 Results.push_back(Tmp1);
3219 case ISD::SELECT_CC: {
3220 Tmp1 = Node->getOperand(0); // LHS
3221 Tmp2 = Node->getOperand(1); // RHS
3222 Tmp3 = Node->getOperand(2); // True
3223 Tmp4 = Node->getOperand(3); // False
3224 SDValue CC = Node->getOperand(4);
3226 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()),
3227 Tmp1, Tmp2, CC, dl);
3229 assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!");
3230 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3231 CC = DAG.getCondCode(ISD::SETNE);
3232 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2,
3234 Results.push_back(Tmp1);
3238 Tmp1 = Node->getOperand(0); // Chain
3239 Tmp2 = Node->getOperand(2); // LHS
3240 Tmp3 = Node->getOperand(3); // RHS
3241 Tmp4 = Node->getOperand(1); // CC
3243 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()),
3244 Tmp2, Tmp3, Tmp4, dl);
3245 LastCALLSEQ_END = DAG.getEntryNode();
3247 assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!");
3248 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
3249 Tmp4 = DAG.getCondCode(ISD::SETNE);
3250 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2,
3251 Tmp3, Node->getOperand(4));
3252 Results.push_back(Tmp1);
3255 case ISD::GLOBAL_OFFSET_TABLE:
3256 case ISD::GlobalAddress:
3257 case ISD::GlobalTLSAddress:
3258 case ISD::ExternalSymbol:
3259 case ISD::ConstantPool:
3260 case ISD::JumpTable:
3261 case ISD::INTRINSIC_W_CHAIN:
3262 case ISD::INTRINSIC_WO_CHAIN:
3263 case ISD::INTRINSIC_VOID:
3264 // FIXME: Custom lowering for these operations shouldn't return null!
3265 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
3266 Results.push_back(SDValue(Node, i));
3270 void SelectionDAGLegalize::PromoteNode(SDNode *Node,
3271 SmallVectorImpl<SDValue> &Results) {
3272 EVT OVT = Node->getValueType(0);
3273 if (Node->getOpcode() == ISD::UINT_TO_FP ||
3274 Node->getOpcode() == ISD::SINT_TO_FP ||
3275 Node->getOpcode() == ISD::SETCC) {
3276 OVT = Node->getOperand(0).getValueType();
3278 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3279 DebugLoc dl = Node->getDebugLoc();
3280 SDValue Tmp1, Tmp2, Tmp3;
3281 switch (Node->getOpcode()) {
3285 // Zero extend the argument.
3286 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3287 // Perform the larger operation.
3288 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
3289 if (Node->getOpcode() == ISD::CTTZ) {
3290 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3291 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
3292 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
3294 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
3295 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3296 } else if (Node->getOpcode() == ISD::CTLZ) {
3297 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3298 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
3299 DAG.getConstant(NVT.getSizeInBits() -
3300 OVT.getSizeInBits(), NVT));
3302 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
3305 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3306 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3307 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
3308 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
3309 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3310 Results.push_back(Tmp1);
3313 case ISD::FP_TO_UINT:
3314 case ISD::FP_TO_SINT:
3315 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
3316 Node->getOpcode() == ISD::FP_TO_SINT, dl);
3317 Results.push_back(Tmp1);
3319 case ISD::UINT_TO_FP:
3320 case ISD::SINT_TO_FP:
3321 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
3322 Node->getOpcode() == ISD::SINT_TO_FP, dl);
3323 Results.push_back(Tmp1);
3328 unsigned ExtOp, TruncOp;
3329 if (OVT.isVector()) {
3330 ExtOp = ISD::BIT_CONVERT;
3331 TruncOp = ISD::BIT_CONVERT;
3333 assert(OVT.isInteger() && "Cannot promote logic operation");
3334 ExtOp = ISD::ANY_EXTEND;
3335 TruncOp = ISD::TRUNCATE;
3337 // Promote each of the values to the new type.
3338 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3339 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3340 // Perform the larger operation, then convert back
3341 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3342 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
3346 unsigned ExtOp, TruncOp;
3347 if (Node->getValueType(0).isVector()) {
3348 ExtOp = ISD::BIT_CONVERT;
3349 TruncOp = ISD::BIT_CONVERT;
3350 } else if (Node->getValueType(0).isInteger()) {
3351 ExtOp = ISD::ANY_EXTEND;
3352 TruncOp = ISD::TRUNCATE;
3354 ExtOp = ISD::FP_EXTEND;
3355 TruncOp = ISD::FP_ROUND;
3357 Tmp1 = Node->getOperand(0);
3358 // Promote each of the values to the new type.
3359 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3360 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
3361 // Perform the larger operation, then round down.
3362 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3);
3363 if (TruncOp != ISD::FP_ROUND)
3364 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
3366 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
3367 DAG.getIntPtrConstant(0));
3368 Results.push_back(Tmp1);
3371 case ISD::VECTOR_SHUFFLE: {
3372 SmallVector<int, 8> Mask;
3373 cast<ShuffleVectorSDNode>(Node)->getMask(Mask);
3375 // Cast the two input vectors.
3376 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
3377 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(1));
3379 // Convert the shuffle mask to the right # elements.
3380 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
3381 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Tmp1);
3382 Results.push_back(Tmp1);
3386 unsigned ExtOp = ISD::FP_EXTEND;
3387 if (NVT.isInteger()) {
3388 ISD::CondCode CCCode =
3389 cast<CondCodeSDNode>(Node->getOperand(2))->get();
3390 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3392 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3393 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3394 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3395 Tmp1, Tmp2, Node->getOperand(2)));
3401 // SelectionDAG::Legalize - This is the entry point for the file.
3403 void SelectionDAG::Legalize(CodeGenOpt::Level OptLevel) {
3404 /// run - This is the main entry point to this class.
3406 SelectionDAGLegalize(*this, OptLevel).LegalizeDAG();