1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/CodeGen/DwarfWriter.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/CodeGen/PseudoSourceValue.h"
22 #include "llvm/Target/TargetFrameInfo.h"
23 #include "llvm/Target/TargetLowering.h"
24 #include "llvm/Target/TargetData.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Target/TargetSubtarget.h"
28 #include "llvm/CallingConv.h"
29 #include "llvm/Constants.h"
30 #include "llvm/DerivedTypes.h"
31 #include "llvm/GlobalVariable.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Compiler.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/ADT/DenseMap.h"
36 #include "llvm/ADT/SmallVector.h"
37 #include "llvm/ADT/SmallPtrSet.h"
41 //===----------------------------------------------------------------------===//
42 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
43 /// hacks on it until the target machine can handle it. This involves
44 /// eliminating value sizes the machine cannot handle (promoting small sizes to
45 /// large sizes or splitting up large values into small values) as well as
46 /// eliminating operations the machine cannot handle.
48 /// This code also does a small amount of optimization and recognition of idioms
49 /// as part of its processing. For example, if a target does not support a
50 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
51 /// will attempt merge setcc and brc instructions into brcc's.
54 class VISIBILITY_HIDDEN SelectionDAGLegalize {
57 bool TypesNeedLegalizing;
59 // Libcall insertion helpers.
61 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
62 /// legalized. We use this to ensure that calls are properly serialized
63 /// against each other, including inserted libcalls.
64 SDValue LastCALLSEQ_END;
66 /// IsLegalizingCall - This member is used *only* for purposes of providing
67 /// helpful assertions that a libcall isn't created while another call is
68 /// being legalized (which could lead to non-serialized call sequences).
69 bool IsLegalizingCall;
72 Legal, // The target natively supports this operation.
73 Promote, // This operation should be executed in a larger type.
74 Expand // Try to expand this to other ops, otherwise use a libcall.
77 /// ValueTypeActions - This is a bitvector that contains two bits for each
78 /// value type, where the two bits correspond to the LegalizeAction enum.
79 /// This can be queried with "getTypeAction(VT)".
80 TargetLowering::ValueTypeActionImpl ValueTypeActions;
82 /// LegalizedNodes - For nodes that are of legal width, and that have more
83 /// than one use, this map indicates what regularized operand to use. This
84 /// allows us to avoid legalizing the same thing more than once.
85 DenseMap<SDValue, SDValue> LegalizedNodes;
87 /// PromotedNodes - For nodes that are below legal width, and that have more
88 /// than one use, this map indicates what promoted value to use. This allows
89 /// us to avoid promoting the same thing more than once.
90 DenseMap<SDValue, SDValue> PromotedNodes;
92 /// ExpandedNodes - For nodes that need to be expanded this map indicates
93 /// which operands are the expanded version of the input. This allows
94 /// us to avoid expanding the same node more than once.
95 DenseMap<SDValue, std::pair<SDValue, SDValue> > ExpandedNodes;
97 /// SplitNodes - For vector nodes that need to be split, this map indicates
98 /// which operands are the split version of the input. This allows us
99 /// to avoid splitting the same node more than once.
100 std::map<SDValue, std::pair<SDValue, SDValue> > SplitNodes;
102 /// ScalarizedNodes - For nodes that need to be converted from vector types to
103 /// scalar types, this contains the mapping of ones we have already
104 /// processed to the result.
105 std::map<SDValue, SDValue> ScalarizedNodes;
107 /// WidenNodes - For nodes that need to be widened from one vector type to
108 /// another, this contains the mapping of those that we have already widen.
109 /// This allows us to avoid widening more than once.
110 std::map<SDValue, SDValue> WidenNodes;
112 void AddLegalizedOperand(SDValue From, SDValue To) {
113 LegalizedNodes.insert(std::make_pair(From, To));
114 // If someone requests legalization of the new node, return itself.
116 LegalizedNodes.insert(std::make_pair(To, To));
118 void AddPromotedOperand(SDValue From, SDValue To) {
119 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
120 assert(isNew && "Got into the map somehow?");
122 // If someone requests legalization of the new node, return itself.
123 LegalizedNodes.insert(std::make_pair(To, To));
125 void AddWidenedOperand(SDValue From, SDValue To) {
126 bool isNew = WidenNodes.insert(std::make_pair(From, To)).second;
127 assert(isNew && "Got into the map somehow?");
129 // If someone requests legalization of the new node, return itself.
130 LegalizedNodes.insert(std::make_pair(To, To));
134 explicit SelectionDAGLegalize(SelectionDAG &DAG, bool TypesNeedLegalizing);
136 /// getTypeAction - Return how we should legalize values of this type, either
137 /// it is already legal or we need to expand it into multiple registers of
138 /// smaller integer type, or we need to promote it to a larger type.
139 LegalizeAction getTypeAction(MVT VT) const {
140 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
143 /// isTypeLegal - Return true if this type is legal on this target.
145 bool isTypeLegal(MVT VT) const {
146 return getTypeAction(VT) == Legal;
152 /// HandleOp - Legalize, Promote, or Expand the specified operand as
153 /// appropriate for its type.
154 void HandleOp(SDValue Op);
156 /// LegalizeOp - We know that the specified value has a legal type.
157 /// Recursively ensure that the operands have legal types, then return the
159 SDValue LegalizeOp(SDValue O);
161 /// UnrollVectorOp - We know that the given vector has a legal type, however
162 /// the operation it performs is not legal and is an operation that we have
163 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
164 /// operating on each element individually.
165 SDValue UnrollVectorOp(SDValue O);
167 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
168 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
169 /// is necessary to spill the vector being inserted into to memory, perform
170 /// the insert there, and then read the result back.
171 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
174 /// PromoteOp - Given an operation that produces a value in an invalid type,
175 /// promote it to compute the value into a larger type. The produced value
176 /// will have the correct bits for the low portion of the register, but no
177 /// guarantee is made about the top bits: it may be zero, sign-extended, or
179 SDValue PromoteOp(SDValue O);
181 /// ExpandOp - Expand the specified SDValue into its two component pieces
182 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
183 /// the LegalizedNodes map is filled in for any results that are not expanded,
184 /// the ExpandedNodes map is filled in for any results that are expanded, and
185 /// the Lo/Hi values are returned. This applies to integer types and Vector
187 void ExpandOp(SDValue O, SDValue &Lo, SDValue &Hi);
189 /// WidenVectorOp - Widen a vector operation to a wider type given by WidenVT
190 /// (e.g., v3i32 to v4i32). The produced value will have the correct value
191 /// for the existing elements but no guarantee is made about the new elements
192 /// at the end of the vector: it may be zero, ones, or garbage. This is useful
193 /// when we have an instruction operating on an illegal vector type and we
194 /// want to widen it to do the computation on a legal wider vector type.
195 SDValue WidenVectorOp(SDValue Op, MVT WidenVT);
197 /// SplitVectorOp - Given an operand of vector type, break it down into
198 /// two smaller values.
199 void SplitVectorOp(SDValue O, SDValue &Lo, SDValue &Hi);
201 /// ScalarizeVectorOp - Given an operand of single-element vector type
202 /// (e.g. v1f32), convert it into the equivalent operation that returns a
203 /// scalar (e.g. f32) value.
204 SDValue ScalarizeVectorOp(SDValue O);
206 /// Useful 16 element vector type that is used to pass operands for widening.
207 typedef SmallVector<SDValue, 16> SDValueVector;
209 /// LoadWidenVectorOp - Load a vector for a wider type. Returns true if
210 /// the LdChain contains a single load and false if it contains a token
211 /// factor for multiple loads. It takes
212 /// Result: location to return the result
213 /// LdChain: location to return the load chain
214 /// Op: load operation to widen
215 /// NVT: widen vector result type we want for the load
216 bool LoadWidenVectorOp(SDValue& Result, SDValue& LdChain,
217 SDValue Op, MVT NVT);
219 /// Helper genWidenVectorLoads - Helper function to generate a set of
220 /// loads to load a vector with a resulting wider type. It takes
221 /// LdChain: list of chains for the load we have generated
222 /// Chain: incoming chain for the ld vector
223 /// BasePtr: base pointer to load from
224 /// SV: memory disambiguation source value
225 /// SVOffset: memory disambiugation offset
226 /// Alignment: alignment of the memory
227 /// isVolatile: volatile load
228 /// LdWidth: width of memory that we want to load
229 /// ResType: the wider result result type for the resulting loaded vector
230 SDValue genWidenVectorLoads(SDValueVector& LdChain, SDValue Chain,
231 SDValue BasePtr, const Value *SV,
232 int SVOffset, unsigned Alignment,
233 bool isVolatile, unsigned LdWidth,
236 /// StoreWidenVectorOp - Stores a widen vector into non widen memory
237 /// location. It takes
238 /// ST: store node that we want to replace
239 /// Chain: incoming store chain
240 /// BasePtr: base address of where we want to store into
241 SDValue StoreWidenVectorOp(StoreSDNode *ST, SDValue Chain,
244 /// Helper genWidenVectorStores - Helper function to generate a set of
245 /// stores to store a widen vector into non widen memory
247 // StChain: list of chains for the stores we have generated
248 // Chain: incoming chain for the ld vector
249 // BasePtr: base pointer to load from
250 // SV: memory disambiguation source value
251 // SVOffset: memory disambiugation offset
252 // Alignment: alignment of the memory
253 // isVolatile: volatile lod
254 // ValOp: value to store
255 // StWidth: width of memory that we want to store
256 void genWidenVectorStores(SDValueVector& StChain, SDValue Chain,
257 SDValue BasePtr, const Value *SV,
258 int SVOffset, unsigned Alignment,
259 bool isVolatile, SDValue ValOp,
262 /// isShuffleLegal - Return non-null if a vector shuffle is legal with the
263 /// specified mask and type. Targets can specify exactly which masks they
264 /// support and the code generator is tasked with not creating illegal masks.
266 /// Note that this will also return true for shuffles that are promoted to a
269 /// If this is a legal shuffle, this method returns the (possibly promoted)
270 /// build_vector Mask. If it's not a legal shuffle, it returns null.
271 SDNode *isShuffleLegal(MVT VT, SDValue Mask) const;
273 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
274 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
276 void LegalizeSetCCOperands(SDValue &LHS, SDValue &RHS, SDValue &CC);
277 void LegalizeSetCCCondCode(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC);
278 void LegalizeSetCC(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC) {
279 LegalizeSetCCOperands(LHS, RHS, CC);
280 LegalizeSetCCCondCode(VT, LHS, RHS, CC);
283 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned,
285 SDValue ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source);
287 SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT);
288 SDValue ExpandBUILD_VECTOR(SDNode *Node);
289 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
290 SDValue LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op);
291 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT);
292 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, bool isSigned);
293 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned);
295 SDValue ExpandBSWAP(SDValue Op);
296 SDValue ExpandBitCount(unsigned Opc, SDValue Op);
297 bool ExpandShift(unsigned Opc, SDValue Op, SDValue Amt,
298 SDValue &Lo, SDValue &Hi);
299 void ExpandShiftParts(unsigned NodeOp, SDValue Op, SDValue Amt,
300 SDValue &Lo, SDValue &Hi);
302 SDValue ExpandEXTRACT_SUBVECTOR(SDValue Op);
303 SDValue ExpandEXTRACT_VECTOR_ELT(SDValue Op);
307 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
308 /// specified mask and type. Targets can specify exactly which masks they
309 /// support and the code generator is tasked with not creating illegal masks.
311 /// Note that this will also return true for shuffles that are promoted to a
313 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDValue Mask) const {
314 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
316 case TargetLowering::Legal:
317 case TargetLowering::Custom:
319 case TargetLowering::Promote: {
320 // If this is promoted to a different type, convert the shuffle mask and
321 // ask if it is legal in the promoted type!
322 MVT NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
323 MVT EltVT = NVT.getVectorElementType();
325 // If we changed # elements, change the shuffle mask.
326 unsigned NumEltsGrowth =
327 NVT.getVectorNumElements() / VT.getVectorNumElements();
328 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
329 if (NumEltsGrowth > 1) {
330 // Renumber the elements.
331 SmallVector<SDValue, 8> Ops;
332 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
333 SDValue InOp = Mask.getOperand(i);
334 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
335 if (InOp.getOpcode() == ISD::UNDEF)
336 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
338 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getZExtValue();
339 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, EltVT));
343 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
349 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.getNode() : 0;
352 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag, bool types)
353 : TLI(dag.getTargetLoweringInfo()), DAG(dag), TypesNeedLegalizing(types),
354 ValueTypeActions(TLI.getValueTypeActions()) {
355 assert(MVT::LAST_VALUETYPE <= 32 &&
356 "Too many value types for ValueTypeActions to hold!");
359 void SelectionDAGLegalize::LegalizeDAG() {
360 LastCALLSEQ_END = DAG.getEntryNode();
361 IsLegalizingCall = false;
363 // The legalize process is inherently a bottom-up recursive process (users
364 // legalize their uses before themselves). Given infinite stack space, we
365 // could just start legalizing on the root and traverse the whole graph. In
366 // practice however, this causes us to run out of stack space on large basic
367 // blocks. To avoid this problem, compute an ordering of the nodes where each
368 // node is only legalized after all of its operands are legalized.
369 DAG.AssignTopologicalOrder();
370 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
371 E = prior(DAG.allnodes_end()); I != next(E); ++I)
372 HandleOp(SDValue(I, 0));
374 // Finally, it's possible the root changed. Get the new root.
375 SDValue OldRoot = DAG.getRoot();
376 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
377 DAG.setRoot(LegalizedNodes[OldRoot]);
379 ExpandedNodes.clear();
380 LegalizedNodes.clear();
381 PromotedNodes.clear();
383 ScalarizedNodes.clear();
386 // Remove dead nodes now.
387 DAG.RemoveDeadNodes();
391 /// FindCallEndFromCallStart - Given a chained node that is part of a call
392 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
393 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
394 if (Node->getOpcode() == ISD::CALLSEQ_END)
396 if (Node->use_empty())
397 return 0; // No CallSeqEnd
399 // The chain is usually at the end.
400 SDValue TheChain(Node, Node->getNumValues()-1);
401 if (TheChain.getValueType() != MVT::Other) {
402 // Sometimes it's at the beginning.
403 TheChain = SDValue(Node, 0);
404 if (TheChain.getValueType() != MVT::Other) {
405 // Otherwise, hunt for it.
406 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
407 if (Node->getValueType(i) == MVT::Other) {
408 TheChain = SDValue(Node, i);
412 // Otherwise, we walked into a node without a chain.
413 if (TheChain.getValueType() != MVT::Other)
418 for (SDNode::use_iterator UI = Node->use_begin(),
419 E = Node->use_end(); UI != E; ++UI) {
421 // Make sure to only follow users of our token chain.
423 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
424 if (User->getOperand(i) == TheChain)
425 if (SDNode *Result = FindCallEndFromCallStart(User))
431 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
432 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
433 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
434 assert(Node && "Didn't find callseq_start for a call??");
435 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
437 assert(Node->getOperand(0).getValueType() == MVT::Other &&
438 "Node doesn't have a token chain argument!");
439 return FindCallStartFromCallEnd(Node->getOperand(0).getNode());
442 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
443 /// see if any uses can reach Dest. If no dest operands can get to dest,
444 /// legalize them, legalize ourself, and return false, otherwise, return true.
446 /// Keep track of the nodes we fine that actually do lead to Dest in
447 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
449 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
450 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
451 if (N == Dest) return true; // N certainly leads to Dest :)
453 // If we've already processed this node and it does lead to Dest, there is no
454 // need to reprocess it.
455 if (NodesLeadingTo.count(N)) return true;
457 // If the first result of this node has been already legalized, then it cannot
459 switch (getTypeAction(N->getValueType(0))) {
461 if (LegalizedNodes.count(SDValue(N, 0))) return false;
464 if (PromotedNodes.count(SDValue(N, 0))) return false;
467 if (ExpandedNodes.count(SDValue(N, 0))) return false;
471 // Okay, this node has not already been legalized. Check and legalize all
472 // operands. If none lead to Dest, then we can legalize this node.
473 bool OperandsLeadToDest = false;
474 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
475 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
476 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo);
478 if (OperandsLeadToDest) {
479 NodesLeadingTo.insert(N);
483 // Okay, this node looks safe, legalize it and return false.
484 HandleOp(SDValue(N, 0));
488 /// HandleOp - Legalize, Promote, Widen, or Expand the specified operand as
489 /// appropriate for its type.
490 void SelectionDAGLegalize::HandleOp(SDValue Op) {
491 MVT VT = Op.getValueType();
492 // If the type legalizer was run then we should never see any illegal result
493 // types here except for target constants (the type legalizer does not touch
494 // those) or for build vector used as a mask for a vector shuffle.
495 // FIXME: We can removed the BUILD_VECTOR case when we fix PR2957.
496 assert((TypesNeedLegalizing || getTypeAction(VT) == Legal ||
497 Op.getOpcode() == ISD::TargetConstant ||
498 Op.getOpcode() == ISD::BUILD_VECTOR) &&
499 "Illegal type introduced after type legalization?");
500 switch (getTypeAction(VT)) {
501 default: assert(0 && "Bad type action!");
502 case Legal: (void)LegalizeOp(Op); break;
504 if (!VT.isVector()) {
509 // See if we can widen otherwise use Expand to either scalarize or split
510 MVT WidenVT = TLI.getWidenVectorType(VT);
511 if (WidenVT != MVT::Other) {
512 (void) WidenVectorOp(Op, WidenVT);
515 // else fall thru to expand since we can't widen the vector
518 if (!VT.isVector()) {
519 // If this is an illegal scalar, expand it into its two component
522 if (Op.getOpcode() == ISD::TargetConstant)
523 break; // Allow illegal target nodes.
525 } else if (VT.getVectorNumElements() == 1) {
526 // If this is an illegal single element vector, convert it to a
528 (void)ScalarizeVectorOp(Op);
530 // This is an illegal multiple element vector.
531 // Split it in half and legalize both parts.
533 SplitVectorOp(Op, X, Y);
539 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
540 /// a load from the constant pool.
541 static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
542 SelectionDAG &DAG, const TargetLowering &TLI) {
545 // If a FP immediate is precise when represented as a float and if the
546 // target can do an extending load from float to double, we put it into
547 // the constant pool as a float, even if it's is statically typed as a
548 // double. This shrinks FP constants and canonicalizes them for targets where
549 // an FP extending load is the same cost as a normal load (such as on the x87
550 // fp stack or PPC FP unit).
551 MVT VT = CFP->getValueType(0);
552 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
554 if (VT!=MVT::f64 && VT!=MVT::f32)
555 assert(0 && "Invalid type expansion");
556 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
557 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
562 while (SVT != MVT::f32) {
563 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1);
564 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
565 // Only do this if the target has a native EXTLOAD instruction from
567 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
568 TLI.ShouldShrinkFPConstant(OrigVT)) {
569 const Type *SType = SVT.getTypeForMVT();
570 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
576 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
577 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
579 return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, DAG.getEntryNode(),
580 CPIdx, PseudoSourceValue::getConstantPool(),
581 0, VT, false, Alignment);
582 return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx,
583 PseudoSourceValue::getConstantPool(), 0, false, Alignment);
587 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
590 SDValue ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT,
592 const TargetLowering &TLI) {
593 MVT VT = Node->getValueType(0);
594 MVT SrcVT = Node->getOperand(1).getValueType();
595 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
596 "fcopysign expansion only supported for f32 and f64");
597 MVT SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
599 // First get the sign bit of second operand.
600 SDValue Mask1 = (SrcVT == MVT::f64)
601 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
602 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
603 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
604 SDValue SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
605 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
606 // Shift right or sign-extend it if the two operands have different types.
607 int SizeDiff = SrcNVT.getSizeInBits() - NVT.getSizeInBits();
609 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
610 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
611 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
612 } else if (SizeDiff < 0) {
613 SignBit = DAG.getNode(ISD::ZERO_EXTEND, NVT, SignBit);
614 SignBit = DAG.getNode(ISD::SHL, NVT, SignBit,
615 DAG.getConstant(-SizeDiff, TLI.getShiftAmountTy()));
618 // Clear the sign bit of first operand.
619 SDValue Mask2 = (VT == MVT::f64)
620 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
621 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
622 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
623 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
624 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
626 // Or the value with the sign bit.
627 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
631 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
633 SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
634 const TargetLowering &TLI) {
635 SDValue Chain = ST->getChain();
636 SDValue Ptr = ST->getBasePtr();
637 SDValue Val = ST->getValue();
638 MVT VT = Val.getValueType();
639 int Alignment = ST->getAlignment();
640 int SVOffset = ST->getSrcValueOffset();
641 if (ST->getMemoryVT().isFloatingPoint() ||
642 ST->getMemoryVT().isVector()) {
643 MVT intVT = MVT::getIntegerVT(VT.getSizeInBits());
644 if (TLI.isTypeLegal(intVT)) {
645 // Expand to a bitconvert of the value to the integer type of the
646 // same size, then a (misaligned) int store.
647 // FIXME: Does not handle truncating floating point stores!
648 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val);
649 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(),
650 SVOffset, ST->isVolatile(), Alignment);
652 // Do a (aligned) store to a stack slot, then copy from the stack slot
653 // to the final destination using (unaligned) integer loads and stores.
654 MVT StoredVT = ST->getMemoryVT();
656 TLI.getRegisterType(MVT::getIntegerVT(StoredVT.getSizeInBits()));
657 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
658 unsigned RegBytes = RegVT.getSizeInBits() / 8;
659 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
661 // Make sure the stack slot is also aligned for the register type.
662 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
664 // Perform the original store, only redirected to the stack slot.
665 SDValue Store = DAG.getTruncStore(Chain, Val, StackPtr, NULL, 0,StoredVT);
666 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
667 SmallVector<SDValue, 8> Stores;
670 // Do all but one copies using the full register width.
671 for (unsigned i = 1; i < NumRegs; i++) {
672 // Load one integer register's worth from the stack slot.
673 SDValue Load = DAG.getLoad(RegVT, Store, StackPtr, NULL, 0);
674 // Store it to the final location. Remember the store.
675 Stores.push_back(DAG.getStore(Load.getValue(1), Load, Ptr,
676 ST->getSrcValue(), SVOffset + Offset,
678 MinAlign(ST->getAlignment(), Offset)));
679 // Increment the pointers.
681 StackPtr = DAG.getNode(ISD::ADD, StackPtr.getValueType(), StackPtr,
683 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, Increment);
686 // The last store may be partial. Do a truncating store. On big-endian
687 // machines this requires an extending load from the stack slot to ensure
688 // that the bits are in the right place.
689 MVT MemVT = MVT::getIntegerVT(8 * (StoredBytes - Offset));
691 // Load from the stack slot.
692 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, RegVT, Store, StackPtr,
695 Stores.push_back(DAG.getTruncStore(Load.getValue(1), Load, Ptr,
696 ST->getSrcValue(), SVOffset + Offset,
697 MemVT, ST->isVolatile(),
698 MinAlign(ST->getAlignment(), Offset)));
699 // The order of the stores doesn't matter - say it with a TokenFactor.
700 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0],
704 assert(ST->getMemoryVT().isInteger() &&
705 !ST->getMemoryVT().isVector() &&
706 "Unaligned store of unknown type.");
707 // Get the half-size VT
709 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1);
710 int NumBits = NewStoredVT.getSizeInBits();
711 int IncrementSize = NumBits / 8;
713 // Divide the stored value in two parts.
714 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
716 SDValue Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
718 // Store the two parts
719 SDValue Store1, Store2;
720 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr,
721 ST->getSrcValue(), SVOffset, NewStoredVT,
722 ST->isVolatile(), Alignment);
723 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
724 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
725 Alignment = MinAlign(Alignment, IncrementSize);
726 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr,
727 ST->getSrcValue(), SVOffset + IncrementSize,
728 NewStoredVT, ST->isVolatile(), Alignment);
730 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2);
733 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
735 SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
736 const TargetLowering &TLI) {
737 int SVOffset = LD->getSrcValueOffset();
738 SDValue Chain = LD->getChain();
739 SDValue Ptr = LD->getBasePtr();
740 MVT VT = LD->getValueType(0);
741 MVT LoadedVT = LD->getMemoryVT();
742 if (VT.isFloatingPoint() || VT.isVector()) {
743 MVT intVT = MVT::getIntegerVT(LoadedVT.getSizeInBits());
744 if (TLI.isTypeLegal(intVT)) {
745 // Expand to a (misaligned) integer load of the same size,
746 // then bitconvert to floating point or vector.
747 SDValue newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(),
748 SVOffset, LD->isVolatile(),
750 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad);
751 if (VT.isFloatingPoint() && LoadedVT != VT)
752 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result);
754 SDValue Ops[] = { Result, Chain };
755 return DAG.getMergeValues(Ops, 2);
757 // Copy the value to a (aligned) stack slot using (unaligned) integer
758 // loads and stores, then do a (aligned) load from the stack slot.
759 MVT RegVT = TLI.getRegisterType(intVT);
760 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
761 unsigned RegBytes = RegVT.getSizeInBits() / 8;
762 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
764 // Make sure the stack slot is also aligned for the register type.
765 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
767 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
768 SmallVector<SDValue, 8> Stores;
769 SDValue StackPtr = StackBase;
772 // Do all but one copies using the full register width.
773 for (unsigned i = 1; i < NumRegs; i++) {
774 // Load one integer register's worth from the original location.
775 SDValue Load = DAG.getLoad(RegVT, Chain, Ptr, LD->getSrcValue(),
776 SVOffset + Offset, LD->isVolatile(),
777 MinAlign(LD->getAlignment(), Offset));
778 // Follow the load with a store to the stack slot. Remember the store.
779 Stores.push_back(DAG.getStore(Load.getValue(1), Load, StackPtr,
781 // Increment the pointers.
783 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, Increment);
784 StackPtr = DAG.getNode(ISD::ADD, StackPtr.getValueType(), StackPtr,
788 // The last copy may be partial. Do an extending load.
789 MVT MemVT = MVT::getIntegerVT(8 * (LoadedBytes - Offset));
790 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, RegVT, Chain, Ptr,
791 LD->getSrcValue(), SVOffset + Offset,
792 MemVT, LD->isVolatile(),
793 MinAlign(LD->getAlignment(), Offset));
794 // Follow the load with a store to the stack slot. Remember the store.
795 // On big-endian machines this requires a truncating store to ensure
796 // that the bits end up in the right place.
797 Stores.push_back(DAG.getTruncStore(Load.getValue(1), Load, StackPtr,
800 // The order of the stores doesn't matter - say it with a TokenFactor.
801 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0],
804 // Finally, perform the original load only redirected to the stack slot.
805 Load = DAG.getExtLoad(LD->getExtensionType(), VT, TF, StackBase,
808 // Callers expect a MERGE_VALUES node.
809 SDValue Ops[] = { Load, TF };
810 return DAG.getMergeValues(Ops, 2);
813 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
814 "Unaligned load of unsupported type.");
816 // Compute the new VT that is half the size of the old one. This is an
818 unsigned NumBits = LoadedVT.getSizeInBits();
820 NewLoadedVT = MVT::getIntegerVT(NumBits/2);
823 unsigned Alignment = LD->getAlignment();
824 unsigned IncrementSize = NumBits / 8;
825 ISD::LoadExtType HiExtType = LD->getExtensionType();
827 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
828 if (HiExtType == ISD::NON_EXTLOAD)
829 HiExtType = ISD::ZEXTLOAD;
831 // Load the value in two parts
833 if (TLI.isLittleEndian()) {
834 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
835 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
836 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
837 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
838 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(),
839 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
840 MinAlign(Alignment, IncrementSize));
842 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset,
843 NewLoadedVT,LD->isVolatile(), Alignment);
844 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
845 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
846 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
847 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
848 MinAlign(Alignment, IncrementSize));
851 // aggregate the two parts
852 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
853 SDValue Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
854 Result = DAG.getNode(ISD::OR, VT, Result, Lo);
856 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
859 SDValue Ops[] = { Result, TF };
860 return DAG.getMergeValues(Ops, 2);
863 /// UnrollVectorOp - We know that the given vector has a legal type, however
864 /// the operation it performs is not legal and is an operation that we have
865 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
866 /// operating on each element individually.
867 SDValue SelectionDAGLegalize::UnrollVectorOp(SDValue Op) {
868 MVT VT = Op.getValueType();
869 assert(isTypeLegal(VT) &&
870 "Caller should expand or promote operands that are not legal!");
871 assert(Op.getNode()->getNumValues() == 1 &&
872 "Can't unroll a vector with multiple results!");
873 unsigned NE = VT.getVectorNumElements();
874 MVT EltVT = VT.getVectorElementType();
876 SmallVector<SDValue, 8> Scalars;
877 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
878 for (unsigned i = 0; i != NE; ++i) {
879 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
880 SDValue Operand = Op.getOperand(j);
881 MVT OperandVT = Operand.getValueType();
882 if (OperandVT.isVector()) {
883 // A vector operand; extract a single element.
884 MVT OperandEltVT = OperandVT.getVectorElementType();
885 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
888 DAG.getConstant(i, MVT::i32));
890 // A scalar operand; just use it as is.
891 Operands[j] = Operand;
895 switch (Op.getOpcode()) {
897 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT,
898 &Operands[0], Operands.size()));
905 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT, Operands[0],
906 DAG.getShiftAmountOperand(Operands[1])));
911 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size());
914 /// GetFPLibCall - Return the right libcall for the given floating point type.
915 static RTLIB::Libcall GetFPLibCall(MVT VT,
916 RTLIB::Libcall Call_F32,
917 RTLIB::Libcall Call_F64,
918 RTLIB::Libcall Call_F80,
919 RTLIB::Libcall Call_PPCF128) {
921 VT == MVT::f32 ? Call_F32 :
922 VT == MVT::f64 ? Call_F64 :
923 VT == MVT::f80 ? Call_F80 :
924 VT == MVT::ppcf128 ? Call_PPCF128 :
925 RTLIB::UNKNOWN_LIBCALL;
928 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
929 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
930 /// is necessary to spill the vector being inserted into to memory, perform
931 /// the insert there, and then read the result back.
932 SDValue SelectionDAGLegalize::
933 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx) {
938 // If the target doesn't support this, we have to spill the input vector
939 // to a temporary stack slot, update the element, then reload it. This is
940 // badness. We could also load the value into a vector register (either
941 // with a "move to register" or "extload into register" instruction, then
942 // permute it into place, if the idx is a constant and if the idx is
943 // supported by the target.
944 MVT VT = Tmp1.getValueType();
945 MVT EltVT = VT.getVectorElementType();
946 MVT IdxVT = Tmp3.getValueType();
947 MVT PtrVT = TLI.getPointerTy();
948 SDValue StackPtr = DAG.CreateStackTemporary(VT);
950 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
953 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr,
954 PseudoSourceValue::getFixedStack(SPFI), 0);
956 // Truncate or zero extend offset to target pointer type.
957 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
958 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
959 // Add the offset to the index.
960 unsigned EltSize = EltVT.getSizeInBits()/8;
961 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
962 SDValue StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
963 // Store the scalar value.
964 Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2,
965 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT);
966 // Load the updated vector.
967 return DAG.getLoad(VT, Ch, StackPtr,
968 PseudoSourceValue::getFixedStack(SPFI), 0);
972 /// LegalizeOp - We know that the specified value has a legal type, and
973 /// that its operands are legal. Now ensure that the operation itself
974 /// is legal, recursively ensuring that the operands' operations remain
976 SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
977 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
980 assert(isTypeLegal(Op.getValueType()) &&
981 "Caller should expand or promote operands that are not legal!");
982 SDNode *Node = Op.getNode();
983 DebugLoc dl = Node->getDebugLoc();
985 // If this operation defines any values that cannot be represented in a
986 // register on this target, make sure to expand or promote them.
987 if (Node->getNumValues() > 1) {
988 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
989 if (getTypeAction(Node->getValueType(i)) != Legal) {
990 HandleOp(Op.getValue(i));
991 assert(LegalizedNodes.count(Op) &&
992 "Handling didn't add legal operands!");
993 return LegalizedNodes[Op];
997 // Note that LegalizeOp may be reentered even from single-use nodes, which
998 // means that we always must cache transformed nodes.
999 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1000 if (I != LegalizedNodes.end()) return I->second;
1002 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
1003 SDValue Result = Op;
1004 bool isCustom = false;
1006 switch (Node->getOpcode()) {
1007 case ISD::FrameIndex:
1008 case ISD::EntryToken:
1010 case ISD::BasicBlock:
1011 case ISD::TargetFrameIndex:
1012 case ISD::TargetJumpTable:
1013 case ISD::TargetConstant:
1014 case ISD::TargetConstantFP:
1015 case ISD::TargetConstantPool:
1016 case ISD::TargetGlobalAddress:
1017 case ISD::TargetGlobalTLSAddress:
1018 case ISD::TargetExternalSymbol:
1019 case ISD::VALUETYPE:
1021 case ISD::MEMOPERAND:
1023 case ISD::ARG_FLAGS:
1024 // Primitives must all be legal.
1025 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
1026 "This must be legal!");
1029 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1030 // If this is a target node, legalize it by legalizing the operands then
1031 // passing it through.
1032 SmallVector<SDValue, 8> Ops;
1033 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1034 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1036 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
1038 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1039 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
1040 return Result.getValue(Op.getResNo());
1042 // Otherwise this is an unhandled builtin node. splat.
1044 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
1046 assert(0 && "Do not know how to legalize this operator!");
1048 case ISD::GLOBAL_OFFSET_TABLE:
1049 case ISD::GlobalAddress:
1050 case ISD::GlobalTLSAddress:
1051 case ISD::ExternalSymbol:
1052 case ISD::ConstantPool:
1053 case ISD::JumpTable: // Nothing to do.
1054 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1055 default: assert(0 && "This action is not supported yet!");
1056 case TargetLowering::Custom:
1057 Tmp1 = TLI.LowerOperation(Op, DAG);
1058 if (Tmp1.getNode()) Result = Tmp1;
1059 // FALLTHROUGH if the target doesn't want to lower this op after all.
1060 case TargetLowering::Legal:
1064 case ISD::FRAMEADDR:
1065 case ISD::RETURNADDR:
1066 // The only option for these nodes is to custom lower them. If the target
1067 // does not custom lower them, then return zero.
1068 Tmp1 = TLI.LowerOperation(Op, DAG);
1072 Result = DAG.getConstant(0, TLI.getPointerTy());
1074 case ISD::FRAME_TO_ARGS_OFFSET: {
1075 MVT VT = Node->getValueType(0);
1076 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1077 default: assert(0 && "This action is not supported yet!");
1078 case TargetLowering::Custom:
1079 Result = TLI.LowerOperation(Op, DAG);
1080 if (Result.getNode()) break;
1082 case TargetLowering::Legal:
1083 Result = DAG.getConstant(0, VT);
1088 case ISD::EXCEPTIONADDR: {
1089 Tmp1 = LegalizeOp(Node->getOperand(0));
1090 MVT VT = Node->getValueType(0);
1091 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1092 default: assert(0 && "This action is not supported yet!");
1093 case TargetLowering::Expand: {
1094 unsigned Reg = TLI.getExceptionAddressRegister();
1095 Result = DAG.getCopyFromReg(Tmp1, Reg, VT);
1098 case TargetLowering::Custom:
1099 Result = TLI.LowerOperation(Op, DAG);
1100 if (Result.getNode()) break;
1102 case TargetLowering::Legal: {
1103 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp1 };
1104 Result = DAG.getMergeValues(Ops, 2);
1109 if (Result.getNode()->getNumValues() == 1) break;
1111 assert(Result.getNode()->getNumValues() == 2 &&
1112 "Cannot return more than two values!");
1114 // Since we produced two values, make sure to remember that we
1115 // legalized both of them.
1116 Tmp1 = LegalizeOp(Result);
1117 Tmp2 = LegalizeOp(Result.getValue(1));
1118 AddLegalizedOperand(Op.getValue(0), Tmp1);
1119 AddLegalizedOperand(Op.getValue(1), Tmp2);
1120 return Op.getResNo() ? Tmp2 : Tmp1;
1121 case ISD::EHSELECTION: {
1122 Tmp1 = LegalizeOp(Node->getOperand(0));
1123 Tmp2 = LegalizeOp(Node->getOperand(1));
1124 MVT VT = Node->getValueType(0);
1125 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1126 default: assert(0 && "This action is not supported yet!");
1127 case TargetLowering::Expand: {
1128 unsigned Reg = TLI.getExceptionSelectorRegister();
1129 Result = DAG.getCopyFromReg(Tmp2, Reg, VT);
1132 case TargetLowering::Custom:
1133 Result = TLI.LowerOperation(Op, DAG);
1134 if (Result.getNode()) break;
1136 case TargetLowering::Legal: {
1137 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp2 };
1138 Result = DAG.getMergeValues(Ops, 2);
1143 if (Result.getNode()->getNumValues() == 1) break;
1145 assert(Result.getNode()->getNumValues() == 2 &&
1146 "Cannot return more than two values!");
1148 // Since we produced two values, make sure to remember that we
1149 // legalized both of them.
1150 Tmp1 = LegalizeOp(Result);
1151 Tmp2 = LegalizeOp(Result.getValue(1));
1152 AddLegalizedOperand(Op.getValue(0), Tmp1);
1153 AddLegalizedOperand(Op.getValue(1), Tmp2);
1154 return Op.getResNo() ? Tmp2 : Tmp1;
1155 case ISD::EH_RETURN: {
1156 MVT VT = Node->getValueType(0);
1157 // The only "good" option for this node is to custom lower it.
1158 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1159 default: assert(0 && "This action is not supported at all!");
1160 case TargetLowering::Custom:
1161 Result = TLI.LowerOperation(Op, DAG);
1162 if (Result.getNode()) break;
1164 case TargetLowering::Legal:
1165 // Target does not know, how to lower this, lower to noop
1166 Result = LegalizeOp(Node->getOperand(0));
1171 case ISD::AssertSext:
1172 case ISD::AssertZext:
1173 Tmp1 = LegalizeOp(Node->getOperand(0));
1174 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1176 case ISD::MERGE_VALUES:
1177 // Legalize eliminates MERGE_VALUES nodes.
1178 Result = Node->getOperand(Op.getResNo());
1180 case ISD::CopyFromReg:
1181 Tmp1 = LegalizeOp(Node->getOperand(0));
1182 Result = Op.getValue(0);
1183 if (Node->getNumValues() == 2) {
1184 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1186 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
1187 if (Node->getNumOperands() == 3) {
1188 Tmp2 = LegalizeOp(Node->getOperand(2));
1189 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1191 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1193 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
1195 // Since CopyFromReg produces two values, make sure to remember that we
1196 // legalized both of them.
1197 AddLegalizedOperand(Op.getValue(0), Result);
1198 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1199 return Result.getValue(Op.getResNo());
1201 MVT VT = Op.getValueType();
1202 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
1203 default: assert(0 && "This action is not supported yet!");
1204 case TargetLowering::Expand:
1206 Result = DAG.getConstant(0, VT);
1207 else if (VT.isFloatingPoint())
1208 Result = DAG.getConstantFP(APFloat(APInt(VT.getSizeInBits(), 0)),
1211 assert(0 && "Unknown value type!");
1213 case TargetLowering::Legal:
1219 case ISD::INTRINSIC_W_CHAIN:
1220 case ISD::INTRINSIC_WO_CHAIN:
1221 case ISD::INTRINSIC_VOID: {
1222 SmallVector<SDValue, 8> Ops;
1223 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1224 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1225 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1227 // Allow the target to custom lower its intrinsics if it wants to.
1228 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
1229 TargetLowering::Custom) {
1230 Tmp3 = TLI.LowerOperation(Result, DAG);
1231 if (Tmp3.getNode()) Result = Tmp3;
1234 if (Result.getNode()->getNumValues() == 1) break;
1236 // Must have return value and chain result.
1237 assert(Result.getNode()->getNumValues() == 2 &&
1238 "Cannot return more than two values!");
1240 // Since loads produce two values, make sure to remember that we
1241 // legalized both of them.
1242 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1243 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1244 return Result.getValue(Op.getResNo());
1247 case ISD::DBG_STOPPOINT:
1248 assert(Node->getNumOperands() == 1 && "Invalid DBG_STOPPOINT node!");
1249 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
1251 switch (TLI.getOperationAction(ISD::DBG_STOPPOINT, MVT::Other)) {
1252 case TargetLowering::Promote:
1253 default: assert(0 && "This action is not supported yet!");
1254 case TargetLowering::Expand: {
1255 DwarfWriter *DW = DAG.getDwarfWriter();
1256 bool useDEBUG_LOC = TLI.isOperationLegalOrCustom(ISD::DEBUG_LOC,
1258 bool useLABEL = TLI.isOperationLegalOrCustom(ISD::DBG_LABEL, MVT::Other);
1260 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node);
1261 GlobalVariable *CU_GV = cast<GlobalVariable>(DSP->getCompileUnit());
1262 if (DW && (useDEBUG_LOC || useLABEL) && !CU_GV->isDeclaration()) {
1263 DICompileUnit CU(cast<GlobalVariable>(DSP->getCompileUnit()));
1264 unsigned SrcFile = DW->RecordSource(CU.getDirectory(),
1267 unsigned Line = DSP->getLine();
1268 unsigned Col = DSP->getColumn();
1271 SDValue Ops[] = { Tmp1, DAG.getConstant(Line, MVT::i32),
1272 DAG.getConstant(Col, MVT::i32),
1273 DAG.getConstant(SrcFile, MVT::i32) };
1274 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops, 4);
1276 unsigned ID = DW->RecordSourceLine(Line, Col, SrcFile);
1277 Result = DAG.getLabel(ISD::DBG_LABEL, Tmp1, ID);
1280 Result = Tmp1; // chain
1284 case TargetLowering::Legal: {
1285 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1286 if (Action == Legal && Tmp1 == Node->getOperand(0))
1289 SmallVector<SDValue, 8> Ops;
1290 Ops.push_back(Tmp1);
1291 if (Action == Legal) {
1292 Ops.push_back(Node->getOperand(1)); // line # must be legal.
1293 Ops.push_back(Node->getOperand(2)); // col # must be legal.
1295 // Otherwise promote them.
1296 Ops.push_back(PromoteOp(Node->getOperand(1)));
1297 Ops.push_back(PromoteOp(Node->getOperand(2)));
1299 Ops.push_back(Node->getOperand(3)); // filename must be legal.
1300 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
1301 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1308 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!");
1309 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) {
1310 default: assert(0 && "This action is not supported yet!");
1311 case TargetLowering::Legal:
1312 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1313 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1314 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable.
1315 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1317 case TargetLowering::Expand:
1318 Result = LegalizeOp(Node->getOperand(0));
1323 case ISD::DEBUG_LOC:
1324 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
1325 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
1326 default: assert(0 && "This action is not supported yet!");
1327 case TargetLowering::Legal: {
1328 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1329 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1330 if (Action == Legal && Tmp1 == Node->getOperand(0))
1332 if (Action == Legal) {
1333 Tmp2 = Node->getOperand(1);
1334 Tmp3 = Node->getOperand(2);
1335 Tmp4 = Node->getOperand(3);
1337 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1338 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1339 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1341 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1347 case ISD::DBG_LABEL:
1349 assert(Node->getNumOperands() == 1 && "Invalid LABEL node!");
1350 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
1351 default: assert(0 && "This action is not supported yet!");
1352 case TargetLowering::Legal:
1353 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1354 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1356 case TargetLowering::Expand:
1357 Result = LegalizeOp(Node->getOperand(0));
1363 assert(Node->getNumOperands() == 4 && "Invalid Prefetch node!");
1364 switch (TLI.getOperationAction(ISD::PREFETCH, MVT::Other)) {
1365 default: assert(0 && "This action is not supported yet!");
1366 case TargetLowering::Legal:
1367 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1368 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1369 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the rw specifier.
1370 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize locality specifier.
1371 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1373 case TargetLowering::Expand:
1375 Result = LegalizeOp(Node->getOperand(0));
1380 case ISD::MEMBARRIER: {
1381 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!");
1382 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) {
1383 default: assert(0 && "This action is not supported yet!");
1384 case TargetLowering::Legal: {
1386 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1387 for (int x = 1; x < 6; ++x) {
1388 Ops[x] = Node->getOperand(x);
1389 if (!isTypeLegal(Ops[x].getValueType()))
1390 Ops[x] = PromoteOp(Ops[x]);
1392 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6);
1395 case TargetLowering::Expand:
1396 //There is no libgcc call for this op
1397 Result = Node->getOperand(0); // Noop
1403 case ISD::ATOMIC_CMP_SWAP: {
1404 unsigned int num_operands = 4;
1405 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1407 for (unsigned int x = 0; x < num_operands; ++x)
1408 Ops[x] = LegalizeOp(Node->getOperand(x));
1409 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1411 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1412 default: assert(0 && "This action is not supported yet!");
1413 case TargetLowering::Custom:
1414 Result = TLI.LowerOperation(Result, DAG);
1416 case TargetLowering::Legal:
1419 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1420 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1421 return Result.getValue(Op.getResNo());
1423 case ISD::ATOMIC_LOAD_ADD:
1424 case ISD::ATOMIC_LOAD_SUB:
1425 case ISD::ATOMIC_LOAD_AND:
1426 case ISD::ATOMIC_LOAD_OR:
1427 case ISD::ATOMIC_LOAD_XOR:
1428 case ISD::ATOMIC_LOAD_NAND:
1429 case ISD::ATOMIC_LOAD_MIN:
1430 case ISD::ATOMIC_LOAD_MAX:
1431 case ISD::ATOMIC_LOAD_UMIN:
1432 case ISD::ATOMIC_LOAD_UMAX:
1433 case ISD::ATOMIC_SWAP: {
1434 unsigned int num_operands = 3;
1435 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1437 for (unsigned int x = 0; x < num_operands; ++x)
1438 Ops[x] = LegalizeOp(Node->getOperand(x));
1439 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1441 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1442 default: assert(0 && "This action is not supported yet!");
1443 case TargetLowering::Custom:
1444 Result = TLI.LowerOperation(Result, DAG);
1446 case TargetLowering::Legal:
1449 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1450 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1451 return Result.getValue(Op.getResNo());
1453 case ISD::Constant: {
1454 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1456 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1458 // We know we don't need to expand constants here, constants only have one
1459 // value and we check that it is fine above.
1461 if (opAction == TargetLowering::Custom) {
1462 Tmp1 = TLI.LowerOperation(Result, DAG);
1468 case ISD::ConstantFP: {
1469 // Spill FP immediates to the constant pool if the target cannot directly
1470 // codegen them. Targets often have some immediate values that can be
1471 // efficiently generated into an FP register without a load. We explicitly
1472 // leave these constants as ConstantFP nodes for the target to deal with.
1473 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1475 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1476 default: assert(0 && "This action is not supported yet!");
1477 case TargetLowering::Legal:
1479 case TargetLowering::Custom:
1480 Tmp3 = TLI.LowerOperation(Result, DAG);
1481 if (Tmp3.getNode()) {
1486 case TargetLowering::Expand: {
1487 // Check to see if this FP immediate is already legal.
1488 bool isLegal = false;
1489 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1490 E = TLI.legal_fpimm_end(); I != E; ++I) {
1491 if (CFP->isExactlyValue(*I)) {
1496 // If this is a legal constant, turn it into a TargetConstantFP node.
1499 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1504 case ISD::TokenFactor:
1505 if (Node->getNumOperands() == 2) {
1506 Tmp1 = LegalizeOp(Node->getOperand(0));
1507 Tmp2 = LegalizeOp(Node->getOperand(1));
1508 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1509 } else if (Node->getNumOperands() == 3) {
1510 Tmp1 = LegalizeOp(Node->getOperand(0));
1511 Tmp2 = LegalizeOp(Node->getOperand(1));
1512 Tmp3 = LegalizeOp(Node->getOperand(2));
1513 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1515 SmallVector<SDValue, 8> Ops;
1516 // Legalize the operands.
1517 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1518 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1519 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1523 case ISD::FORMAL_ARGUMENTS:
1525 // The only option for this is to custom lower it.
1526 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1527 assert(Tmp3.getNode() && "Target didn't custom lower this node!");
1528 // A call within a calling sequence must be legalized to something
1529 // other than the normal CALLSEQ_END. Violating this gets Legalize
1530 // into an infinite loop.
1531 assert ((!IsLegalizingCall ||
1532 Node->getOpcode() != ISD::CALL ||
1533 Tmp3.getNode()->getOpcode() != ISD::CALLSEQ_END) &&
1534 "Nested CALLSEQ_START..CALLSEQ_END not supported.");
1536 // The number of incoming and outgoing values should match; unless the final
1537 // outgoing value is a flag.
1538 assert((Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() ||
1539 (Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() + 1 &&
1540 Tmp3.getNode()->getValueType(Tmp3.getNode()->getNumValues() - 1) ==
1542 "Lowering call/formal_arguments produced unexpected # results!");
1544 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1545 // remember that we legalized all of them, so it doesn't get relegalized.
1546 for (unsigned i = 0, e = Tmp3.getNode()->getNumValues(); i != e; ++i) {
1547 if (Tmp3.getNode()->getValueType(i) == MVT::Flag)
1549 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1550 if (Op.getResNo() == i)
1552 AddLegalizedOperand(SDValue(Node, i), Tmp1);
1555 case ISD::EXTRACT_SUBREG: {
1556 Tmp1 = LegalizeOp(Node->getOperand(0));
1557 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1558 assert(idx && "Operand must be a constant");
1559 Tmp2 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0));
1560 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1563 case ISD::INSERT_SUBREG: {
1564 Tmp1 = LegalizeOp(Node->getOperand(0));
1565 Tmp2 = LegalizeOp(Node->getOperand(1));
1566 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1567 assert(idx && "Operand must be a constant");
1568 Tmp3 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0));
1569 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1572 case ISD::BUILD_VECTOR:
1573 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1574 default: assert(0 && "This action is not supported yet!");
1575 case TargetLowering::Custom:
1576 Tmp3 = TLI.LowerOperation(Result, DAG);
1577 if (Tmp3.getNode()) {
1582 case TargetLowering::Expand:
1583 Result = ExpandBUILD_VECTOR(Result.getNode());
1587 case ISD::INSERT_VECTOR_ELT:
1588 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1589 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1591 // The type of the value to insert may not be legal, even though the vector
1592 // type is legal. Legalize/Promote accordingly. We do not handle Expand
1594 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1595 default: assert(0 && "Cannot expand insert element operand");
1596 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
1597 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
1599 // FIXME: An alternative would be to check to see if the target is not
1600 // going to custom lower this operation, we could bitcast to half elt
1601 // width and perform two inserts at that width, if that is legal.
1602 Tmp2 = Node->getOperand(1);
1605 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1607 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1608 Node->getValueType(0))) {
1609 default: assert(0 && "This action is not supported yet!");
1610 case TargetLowering::Legal:
1612 case TargetLowering::Custom:
1613 Tmp4 = TLI.LowerOperation(Result, DAG);
1614 if (Tmp4.getNode()) {
1619 case TargetLowering::Promote:
1620 // Fall thru for vector case
1621 case TargetLowering::Expand: {
1622 // If the insert index is a constant, codegen this as a scalar_to_vector,
1623 // then a shuffle that inserts it into the right position in the vector.
1624 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1625 // SCALAR_TO_VECTOR requires that the type of the value being inserted
1626 // match the element type of the vector being created.
1627 if (Tmp2.getValueType() ==
1628 Op.getValueType().getVectorElementType()) {
1629 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
1630 Tmp1.getValueType(), Tmp2);
1632 unsigned NumElts = Tmp1.getValueType().getVectorNumElements();
1634 MVT::getIntVectorWithNumElements(NumElts);
1635 MVT ShufMaskEltVT = ShufMaskVT.getVectorElementType();
1637 // We generate a shuffle of InVec and ScVec, so the shuffle mask
1638 // should be 0,1,2,3,4,5... with the appropriate element replaced with
1639 // elt 0 of the RHS.
1640 SmallVector<SDValue, 8> ShufOps;
1641 for (unsigned i = 0; i != NumElts; ++i) {
1642 if (i != InsertPos->getZExtValue())
1643 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1645 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1647 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1648 &ShufOps[0], ShufOps.size());
1650 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1651 Tmp1, ScVec, ShufMask);
1652 Result = LegalizeOp(Result);
1656 Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3);
1661 case ISD::SCALAR_TO_VECTOR:
1662 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1663 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1667 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1668 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1669 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1670 Node->getValueType(0))) {
1671 default: assert(0 && "This action is not supported yet!");
1672 case TargetLowering::Legal:
1674 case TargetLowering::Custom:
1675 Tmp3 = TLI.LowerOperation(Result, DAG);
1676 if (Tmp3.getNode()) {
1681 case TargetLowering::Expand:
1682 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1686 case ISD::VECTOR_SHUFFLE:
1687 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1688 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1689 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1691 // Allow targets to custom lower the SHUFFLEs they support.
1692 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1693 default: assert(0 && "Unknown operation action!");
1694 case TargetLowering::Legal:
1695 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1696 "vector shuffle should not be created if not legal!");
1698 case TargetLowering::Custom:
1699 Tmp3 = TLI.LowerOperation(Result, DAG);
1700 if (Tmp3.getNode()) {
1705 case TargetLowering::Expand: {
1706 MVT VT = Node->getValueType(0);
1707 MVT EltVT = VT.getVectorElementType();
1708 MVT PtrVT = TLI.getPointerTy();
1709 SDValue Mask = Node->getOperand(2);
1710 unsigned NumElems = Mask.getNumOperands();
1711 SmallVector<SDValue,8> Ops;
1712 for (unsigned i = 0; i != NumElems; ++i) {
1713 SDValue Arg = Mask.getOperand(i);
1714 if (Arg.getOpcode() == ISD::UNDEF) {
1715 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1717 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1718 unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
1720 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1721 DAG.getConstant(Idx, PtrVT)));
1723 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1724 DAG.getConstant(Idx - NumElems, PtrVT)));
1727 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1730 case TargetLowering::Promote: {
1731 // Change base type to a different vector type.
1732 MVT OVT = Node->getValueType(0);
1733 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1735 // Cast the two input vectors.
1736 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1737 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1739 // Convert the shuffle mask to the right # elements.
1740 Tmp3 = SDValue(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1741 assert(Tmp3.getNode() && "Shuffle not legal?");
1742 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1743 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1749 case ISD::EXTRACT_VECTOR_ELT:
1750 Tmp1 = Node->getOperand(0);
1751 Tmp2 = LegalizeOp(Node->getOperand(1));
1752 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1753 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1756 case ISD::EXTRACT_SUBVECTOR:
1757 Tmp1 = Node->getOperand(0);
1758 Tmp2 = LegalizeOp(Node->getOperand(1));
1759 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1760 Result = ExpandEXTRACT_SUBVECTOR(Result);
1763 case ISD::CONCAT_VECTORS: {
1764 // Use extract/insert/build vector for now. We might try to be
1765 // more clever later.
1766 MVT PtrVT = TLI.getPointerTy();
1767 SmallVector<SDValue, 8> Ops;
1768 unsigned NumOperands = Node->getNumOperands();
1769 for (unsigned i=0; i < NumOperands; ++i) {
1770 SDValue SubOp = Node->getOperand(i);
1771 MVT VVT = SubOp.getNode()->getValueType(0);
1772 MVT EltVT = VVT.getVectorElementType();
1773 unsigned NumSubElem = VVT.getVectorNumElements();
1774 for (unsigned j=0; j < NumSubElem; ++j) {
1775 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, SubOp,
1776 DAG.getConstant(j, PtrVT)));
1779 return LegalizeOp(DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0),
1780 &Ops[0], Ops.size()));
1783 case ISD::CALLSEQ_START: {
1784 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1786 // Recursively Legalize all of the inputs of the call end that do not lead
1787 // to this call start. This ensures that any libcalls that need be inserted
1788 // are inserted *before* the CALLSEQ_START.
1789 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1790 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1791 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
1795 // Now that we legalized all of the inputs (which may have inserted
1796 // libcalls) create the new CALLSEQ_START node.
1797 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1799 // Merge in the last call, to ensure that this call start after the last
1801 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1802 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1803 Tmp1 = LegalizeOp(Tmp1);
1806 // Do not try to legalize the target-specific arguments (#1+).
1807 if (Tmp1 != Node->getOperand(0)) {
1808 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1810 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1813 // Remember that the CALLSEQ_START is legalized.
1814 AddLegalizedOperand(Op.getValue(0), Result);
1815 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1816 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1818 // Now that the callseq_start and all of the non-call nodes above this call
1819 // sequence have been legalized, legalize the call itself. During this
1820 // process, no libcalls can/will be inserted, guaranteeing that no calls
1822 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1823 // Note that we are selecting this call!
1824 LastCALLSEQ_END = SDValue(CallEnd, 0);
1825 IsLegalizingCall = true;
1827 // Legalize the call, starting from the CALLSEQ_END.
1828 LegalizeOp(LastCALLSEQ_END);
1829 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1832 case ISD::CALLSEQ_END:
1833 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1834 // will cause this node to be legalized as well as handling libcalls right.
1835 if (LastCALLSEQ_END.getNode() != Node) {
1836 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
1837 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1838 assert(I != LegalizedNodes.end() &&
1839 "Legalizing the call start should have legalized this node!");
1843 // Otherwise, the call start has been legalized and everything is going
1844 // according to plan. Just legalize ourselves normally here.
1845 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1846 // Do not try to legalize the target-specific arguments (#1+), except for
1847 // an optional flag input.
1848 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1849 if (Tmp1 != Node->getOperand(0)) {
1850 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1852 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1855 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1856 if (Tmp1 != Node->getOperand(0) ||
1857 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1858 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1861 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1864 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1865 // This finishes up call legalization.
1866 IsLegalizingCall = false;
1868 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1869 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1870 if (Node->getNumValues() == 2)
1871 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1872 return Result.getValue(Op.getResNo());
1873 case ISD::DYNAMIC_STACKALLOC: {
1874 MVT VT = Node->getValueType(0);
1875 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1876 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1877 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1878 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1880 Tmp1 = Result.getValue(0);
1881 Tmp2 = Result.getValue(1);
1882 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1883 default: assert(0 && "This action is not supported yet!");
1884 case TargetLowering::Expand: {
1885 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1886 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1887 " not tell us which reg is the stack pointer!");
1888 SDValue Chain = Tmp1.getOperand(0);
1890 // Chain the dynamic stack allocation so that it doesn't modify the stack
1891 // pointer when other instructions are using the stack.
1892 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1894 SDValue Size = Tmp2.getOperand(1);
1895 SDValue SP = DAG.getCopyFromReg(Chain, SPReg, VT);
1896 Chain = SP.getValue(1);
1897 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1898 unsigned StackAlign =
1899 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1900 if (Align > StackAlign)
1901 SP = DAG.getNode(ISD::AND, VT, SP,
1902 DAG.getConstant(-(uint64_t)Align, VT));
1903 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value
1904 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
1906 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1907 DAG.getIntPtrConstant(0, true), SDValue());
1909 Tmp1 = LegalizeOp(Tmp1);
1910 Tmp2 = LegalizeOp(Tmp2);
1913 case TargetLowering::Custom:
1914 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1915 if (Tmp3.getNode()) {
1916 Tmp1 = LegalizeOp(Tmp3);
1917 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1920 case TargetLowering::Legal:
1923 // Since this op produce two values, make sure to remember that we
1924 // legalized both of them.
1925 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
1926 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
1927 return Op.getResNo() ? Tmp2 : Tmp1;
1929 case ISD::INLINEASM: {
1930 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1931 bool Changed = false;
1932 // Legalize all of the operands of the inline asm, in case they are nodes
1933 // that need to be expanded or something. Note we skip the asm string and
1934 // all of the TargetConstant flags.
1935 SDValue Op = LegalizeOp(Ops[0]);
1936 Changed = Op != Ops[0];
1939 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1940 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1941 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getZExtValue() >> 3;
1942 for (++i; NumVals; ++i, --NumVals) {
1943 SDValue Op = LegalizeOp(Ops[i]);
1952 Op = LegalizeOp(Ops.back());
1953 Changed |= Op != Ops.back();
1958 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1960 // INLINE asm returns a chain and flag, make sure to add both to the map.
1961 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1962 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1963 return Result.getValue(Op.getResNo());
1966 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1967 // Ensure that libcalls are emitted before a branch.
1968 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1969 Tmp1 = LegalizeOp(Tmp1);
1970 LastCALLSEQ_END = DAG.getEntryNode();
1972 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1975 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1976 // Ensure that libcalls are emitted before a branch.
1977 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1978 Tmp1 = LegalizeOp(Tmp1);
1979 LastCALLSEQ_END = DAG.getEntryNode();
1981 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1982 default: assert(0 && "Indirect target must be legal type (pointer)!");
1984 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1987 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1990 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1991 // Ensure that libcalls are emitted before a branch.
1992 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1993 Tmp1 = LegalizeOp(Tmp1);
1994 LastCALLSEQ_END = DAG.getEntryNode();
1996 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1997 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1999 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
2000 default: assert(0 && "This action is not supported yet!");
2001 case TargetLowering::Legal: break;
2002 case TargetLowering::Custom:
2003 Tmp1 = TLI.LowerOperation(Result, DAG);
2004 if (Tmp1.getNode()) Result = Tmp1;
2006 case TargetLowering::Expand: {
2007 SDValue Chain = Result.getOperand(0);
2008 SDValue Table = Result.getOperand(1);
2009 SDValue Index = Result.getOperand(2);
2011 MVT PTy = TLI.getPointerTy();
2012 MachineFunction &MF = DAG.getMachineFunction();
2013 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
2014 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
2015 SDValue Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
2017 MVT MemVT = MVT::getIntegerVT(EntrySize * 8);
2018 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, PTy, Chain, Addr,
2019 PseudoSourceValue::getJumpTable(), 0, MemVT);
2021 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2022 // For PIC, the sequence is:
2023 // BRIND(load(Jumptable + index) + RelocBase)
2024 // RelocBase can be JumpTable, GOT or some sort of global base.
2025 Addr = DAG.getNode(ISD::ADD, PTy, Addr,
2026 TLI.getPICJumpTableRelocBase(Table, DAG));
2028 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
2033 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2034 // Ensure that libcalls are emitted before a return.
2035 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2036 Tmp1 = LegalizeOp(Tmp1);
2037 LastCALLSEQ_END = DAG.getEntryNode();
2039 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2040 case Expand: assert(0 && "It's impossible to expand bools");
2042 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
2045 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
2047 // The top bits of the promoted condition are not necessarily zero, ensure
2048 // that the value is properly zero extended.
2049 unsigned BitWidth = Tmp2.getValueSizeInBits();
2050 if (!DAG.MaskedValueIsZero(Tmp2,
2051 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2052 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
2057 // Basic block destination (Op#2) is always legal.
2058 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2060 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
2061 default: assert(0 && "This action is not supported yet!");
2062 case TargetLowering::Legal: break;
2063 case TargetLowering::Custom:
2064 Tmp1 = TLI.LowerOperation(Result, DAG);
2065 if (Tmp1.getNode()) Result = Tmp1;
2067 case TargetLowering::Expand:
2068 // Expand brcond's setcc into its constituent parts and create a BR_CC
2070 if (Tmp2.getOpcode() == ISD::SETCC) {
2071 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
2072 Tmp2.getOperand(0), Tmp2.getOperand(1),
2073 Node->getOperand(2));
2075 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
2076 DAG.getCondCode(ISD::SETNE), Tmp2,
2077 DAG.getConstant(0, Tmp2.getValueType()),
2078 Node->getOperand(2));
2084 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2085 // Ensure that libcalls are emitted before a branch.
2086 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2087 Tmp1 = LegalizeOp(Tmp1);
2088 Tmp2 = Node->getOperand(2); // LHS
2089 Tmp3 = Node->getOperand(3); // RHS
2090 Tmp4 = Node->getOperand(1); // CC
2092 LegalizeSetCC(TLI.getSetCCResultType(Tmp2.getValueType()), Tmp2, Tmp3,Tmp4);
2093 LastCALLSEQ_END = DAG.getEntryNode();
2095 // If we didn't get both a LHS and RHS back from LegalizeSetCC,
2096 // the LHS is a legal SETCC itself. In this case, we need to compare
2097 // the result against zero to select between true and false values.
2098 if (Tmp3.getNode() == 0) {
2099 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
2100 Tmp4 = DAG.getCondCode(ISD::SETNE);
2103 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
2104 Node->getOperand(4));
2106 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
2107 default: assert(0 && "Unexpected action for BR_CC!");
2108 case TargetLowering::Legal: break;
2109 case TargetLowering::Custom:
2110 Tmp4 = TLI.LowerOperation(Result, DAG);
2111 if (Tmp4.getNode()) Result = Tmp4;
2116 LoadSDNode *LD = cast<LoadSDNode>(Node);
2117 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
2118 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
2120 ISD::LoadExtType ExtType = LD->getExtensionType();
2121 if (ExtType == ISD::NON_EXTLOAD) {
2122 MVT VT = Node->getValueType(0);
2123 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2124 Tmp3 = Result.getValue(0);
2125 Tmp4 = Result.getValue(1);
2127 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
2128 default: assert(0 && "This action is not supported yet!");
2129 case TargetLowering::Legal:
2130 // If this is an unaligned load and the target doesn't support it,
2132 if (!TLI.allowsUnalignedMemoryAccesses()) {
2133 unsigned ABIAlignment = TLI.getTargetData()->
2134 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
2135 if (LD->getAlignment() < ABIAlignment){
2136 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
2138 Tmp3 = Result.getOperand(0);
2139 Tmp4 = Result.getOperand(1);
2140 Tmp3 = LegalizeOp(Tmp3);
2141 Tmp4 = LegalizeOp(Tmp4);
2145 case TargetLowering::Custom:
2146 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
2147 if (Tmp1.getNode()) {
2148 Tmp3 = LegalizeOp(Tmp1);
2149 Tmp4 = LegalizeOp(Tmp1.getValue(1));
2152 case TargetLowering::Promote: {
2153 // Only promote a load of vector type to another.
2154 assert(VT.isVector() && "Cannot promote this load!");
2155 // Change base type to a different vector type.
2156 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
2158 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
2159 LD->getSrcValueOffset(),
2160 LD->isVolatile(), LD->getAlignment());
2161 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
2162 Tmp4 = LegalizeOp(Tmp1.getValue(1));
2166 // Since loads produce two values, make sure to remember that we
2167 // legalized both of them.
2168 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
2169 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
2170 return Op.getResNo() ? Tmp4 : Tmp3;
2172 MVT SrcVT = LD->getMemoryVT();
2173 unsigned SrcWidth = SrcVT.getSizeInBits();
2174 int SVOffset = LD->getSrcValueOffset();
2175 unsigned Alignment = LD->getAlignment();
2176 bool isVolatile = LD->isVolatile();
2178 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
2179 // Some targets pretend to have an i1 loading operation, and actually
2180 // load an i8. This trick is correct for ZEXTLOAD because the top 7
2181 // bits are guaranteed to be zero; it helps the optimizers understand
2182 // that these bits are zero. It is also useful for EXTLOAD, since it
2183 // tells the optimizers that those bits are undefined. It would be
2184 // nice to have an effective generic way of getting these benefits...
2185 // Until such a way is found, don't insist on promoting i1 here.
2186 (SrcVT != MVT::i1 ||
2187 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
2188 // Promote to a byte-sized load if not loading an integral number of
2189 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
2190 unsigned NewWidth = SrcVT.getStoreSizeInBits();
2191 MVT NVT = MVT::getIntegerVT(NewWidth);
2194 // The extra bits are guaranteed to be zero, since we stored them that
2195 // way. A zext load from NVT thus automatically gives zext from SrcVT.
2197 ISD::LoadExtType NewExtType =
2198 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
2200 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0),
2201 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
2202 NVT, isVolatile, Alignment);
2204 Ch = Result.getValue(1); // The chain.
2206 if (ExtType == ISD::SEXTLOAD)
2207 // Having the top bits zero doesn't help when sign extending.
2208 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2209 Result, DAG.getValueType(SrcVT));
2210 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
2211 // All the top bits are guaranteed to be zero - inform the optimizers.
2212 Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result,
2213 DAG.getValueType(SrcVT));
2215 Tmp1 = LegalizeOp(Result);
2216 Tmp2 = LegalizeOp(Ch);
2217 } else if (SrcWidth & (SrcWidth - 1)) {
2218 // If not loading a power-of-2 number of bits, expand as two loads.
2219 assert(SrcVT.isExtended() && !SrcVT.isVector() &&
2220 "Unsupported extload!");
2221 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
2222 assert(RoundWidth < SrcWidth);
2223 unsigned ExtraWidth = SrcWidth - RoundWidth;
2224 assert(ExtraWidth < RoundWidth);
2225 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2226 "Load size not an integral number of bytes!");
2227 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2228 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2230 unsigned IncrementSize;
2232 if (TLI.isLittleEndian()) {
2233 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
2234 // Load the bottom RoundWidth bits.
2235 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2236 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2239 // Load the remaining ExtraWidth bits.
2240 IncrementSize = RoundWidth / 8;
2241 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2242 DAG.getIntPtrConstant(IncrementSize));
2243 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2244 LD->getSrcValue(), SVOffset + IncrementSize,
2245 ExtraVT, isVolatile,
2246 MinAlign(Alignment, IncrementSize));
2248 // Build a factor node to remember that this load is independent of the
2250 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2253 // Move the top bits to the right place.
2254 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2255 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2257 // Join the hi and lo parts.
2258 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2260 // Big endian - avoid unaligned loads.
2261 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
2262 // Load the top RoundWidth bits.
2263 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2264 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2267 // Load the remaining ExtraWidth bits.
2268 IncrementSize = RoundWidth / 8;
2269 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2270 DAG.getIntPtrConstant(IncrementSize));
2271 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2272 LD->getSrcValue(), SVOffset + IncrementSize,
2273 ExtraVT, isVolatile,
2274 MinAlign(Alignment, IncrementSize));
2276 // Build a factor node to remember that this load is independent of the
2278 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2281 // Move the top bits to the right place.
2282 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2283 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2285 // Join the hi and lo parts.
2286 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2289 Tmp1 = LegalizeOp(Result);
2290 Tmp2 = LegalizeOp(Ch);
2292 switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
2293 default: assert(0 && "This action is not supported yet!");
2294 case TargetLowering::Custom:
2297 case TargetLowering::Legal:
2298 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2299 Tmp1 = Result.getValue(0);
2300 Tmp2 = Result.getValue(1);
2303 Tmp3 = TLI.LowerOperation(Result, DAG);
2304 if (Tmp3.getNode()) {
2305 Tmp1 = LegalizeOp(Tmp3);
2306 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2309 // If this is an unaligned load and the target doesn't support it,
2311 if (!TLI.allowsUnalignedMemoryAccesses()) {
2312 unsigned ABIAlignment = TLI.getTargetData()->
2313 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
2314 if (LD->getAlignment() < ABIAlignment){
2315 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
2317 Tmp1 = Result.getOperand(0);
2318 Tmp2 = Result.getOperand(1);
2319 Tmp1 = LegalizeOp(Tmp1);
2320 Tmp2 = LegalizeOp(Tmp2);
2325 case TargetLowering::Expand:
2326 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
2327 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
2328 SDValue Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
2329 LD->getSrcValueOffset(),
2330 LD->isVolatile(), LD->getAlignment());
2331 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
2332 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
2333 Tmp2 = LegalizeOp(Load.getValue(1));
2336 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
2337 // Turn the unsupported load into an EXTLOAD followed by an explicit
2338 // zero/sign extend inreg.
2339 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2340 Tmp1, Tmp2, LD->getSrcValue(),
2341 LD->getSrcValueOffset(), SrcVT,
2342 LD->isVolatile(), LD->getAlignment());
2344 if (ExtType == ISD::SEXTLOAD)
2345 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2346 Result, DAG.getValueType(SrcVT));
2348 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
2349 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
2350 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
2355 // Since loads produce two values, make sure to remember that we legalized
2357 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2358 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2359 return Op.getResNo() ? Tmp2 : Tmp1;
2362 case ISD::EXTRACT_ELEMENT: {
2363 MVT OpTy = Node->getOperand(0).getValueType();
2364 switch (getTypeAction(OpTy)) {
2365 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
2367 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
2369 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
2370 DAG.getConstant(OpTy.getSizeInBits()/2,
2371 TLI.getShiftAmountTy()));
2372 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
2375 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
2376 Node->getOperand(0));
2380 // Get both the low and high parts.
2381 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2382 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
2383 Result = Tmp2; // 1 -> Hi
2385 Result = Tmp1; // 0 -> Lo
2391 case ISD::CopyToReg:
2392 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2394 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
2395 "Register type must be legal!");
2396 // Legalize the incoming value (must be a legal type).
2397 Tmp2 = LegalizeOp(Node->getOperand(2));
2398 if (Node->getNumValues() == 1) {
2399 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
2401 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
2402 if (Node->getNumOperands() == 4) {
2403 Tmp3 = LegalizeOp(Node->getOperand(3));
2404 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
2407 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
2410 // Since this produces two values, make sure to remember that we legalized
2412 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
2413 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
2419 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2421 // Ensure that libcalls are emitted before a return.
2422 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2423 Tmp1 = LegalizeOp(Tmp1);
2424 LastCALLSEQ_END = DAG.getEntryNode();
2426 switch (Node->getNumOperands()) {
2428 Tmp2 = Node->getOperand(1);
2429 Tmp3 = Node->getOperand(2); // Signness
2430 switch (getTypeAction(Tmp2.getValueType())) {
2432 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
2435 if (!Tmp2.getValueType().isVector()) {
2437 ExpandOp(Tmp2, Lo, Hi);
2439 // Big endian systems want the hi reg first.
2440 if (TLI.isBigEndian())
2444 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2446 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
2447 Result = LegalizeOp(Result);
2449 SDNode *InVal = Tmp2.getNode();
2450 int InIx = Tmp2.getResNo();
2451 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
2452 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
2454 // Figure out if there is a simple type corresponding to this Vector
2455 // type. If so, convert to the vector type.
2456 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2457 if (TLI.isTypeLegal(TVT)) {
2458 // Turn this into a return of the vector type.
2459 Tmp2 = LegalizeOp(Tmp2);
2460 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2461 } else if (NumElems == 1) {
2462 // Turn this into a return of the scalar type.
2463 Tmp2 = ScalarizeVectorOp(Tmp2);
2464 Tmp2 = LegalizeOp(Tmp2);
2465 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2467 // FIXME: Returns of gcc generic vectors smaller than a legal type
2468 // should be returned in integer registers!
2470 // The scalarized value type may not be legal, e.g. it might require
2471 // promotion or expansion. Relegalize the return.
2472 Result = LegalizeOp(Result);
2474 // FIXME: Returns of gcc generic vectors larger than a legal vector
2475 // type should be returned by reference!
2477 SplitVectorOp(Tmp2, Lo, Hi);
2478 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2479 Result = LegalizeOp(Result);
2484 Tmp2 = PromoteOp(Node->getOperand(1));
2485 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2486 Result = LegalizeOp(Result);
2491 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2493 default: { // ret <values>
2494 SmallVector<SDValue, 8> NewValues;
2495 NewValues.push_back(Tmp1);
2496 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
2497 switch (getTypeAction(Node->getOperand(i).getValueType())) {
2499 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
2500 NewValues.push_back(Node->getOperand(i+1));
2504 assert(!Node->getOperand(i).getValueType().isExtended() &&
2505 "FIXME: TODO: implement returning non-legal vector types!");
2506 ExpandOp(Node->getOperand(i), Lo, Hi);
2507 NewValues.push_back(Lo);
2508 NewValues.push_back(Node->getOperand(i+1));
2510 NewValues.push_back(Hi);
2511 NewValues.push_back(Node->getOperand(i+1));
2516 assert(0 && "Can't promote multiple return value yet!");
2519 if (NewValues.size() == Node->getNumOperands())
2520 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
2522 Result = DAG.getNode(ISD::RET, MVT::Other,
2523 &NewValues[0], NewValues.size());
2528 if (Result.getOpcode() == ISD::RET) {
2529 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
2530 default: assert(0 && "This action is not supported yet!");
2531 case TargetLowering::Legal: break;
2532 case TargetLowering::Custom:
2533 Tmp1 = TLI.LowerOperation(Result, DAG);
2534 if (Tmp1.getNode()) Result = Tmp1;
2540 StoreSDNode *ST = cast<StoreSDNode>(Node);
2541 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
2542 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
2543 int SVOffset = ST->getSrcValueOffset();
2544 unsigned Alignment = ST->getAlignment();
2545 bool isVolatile = ST->isVolatile();
2547 if (!ST->isTruncatingStore()) {
2548 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
2549 // FIXME: We shouldn't do this for TargetConstantFP's.
2550 // FIXME: move this to the DAG Combiner! Note that we can't regress due
2551 // to phase ordering between legalized code and the dag combiner. This
2552 // probably means that we need to integrate dag combiner and legalizer
2554 // We generally can't do this one for long doubles.
2555 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
2556 if (CFP->getValueType(0) == MVT::f32 &&
2557 getTypeAction(MVT::i32) == Legal) {
2558 Tmp3 = DAG.getConstant(CFP->getValueAPF().
2559 bitcastToAPInt().zextOrTrunc(32),
2561 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2562 SVOffset, isVolatile, Alignment);
2564 } else if (CFP->getValueType(0) == MVT::f64) {
2565 // If this target supports 64-bit registers, do a single 64-bit store.
2566 if (getTypeAction(MVT::i64) == Legal) {
2567 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
2568 zextOrTrunc(64), MVT::i64);
2569 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2570 SVOffset, isVolatile, Alignment);
2572 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
2573 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
2574 // stores. If the target supports neither 32- nor 64-bits, this
2575 // xform is certainly not worth it.
2576 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
2577 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
2578 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
2579 if (TLI.isBigEndian()) std::swap(Lo, Hi);
2581 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2582 SVOffset, isVolatile, Alignment);
2583 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2584 DAG.getIntPtrConstant(4));
2585 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
2586 isVolatile, MinAlign(Alignment, 4U));
2588 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2594 switch (getTypeAction(ST->getMemoryVT())) {
2596 Tmp3 = LegalizeOp(ST->getValue());
2597 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2600 MVT VT = Tmp3.getValueType();
2601 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2602 default: assert(0 && "This action is not supported yet!");
2603 case TargetLowering::Legal:
2604 // If this is an unaligned store and the target doesn't support it,
2606 if (!TLI.allowsUnalignedMemoryAccesses()) {
2607 unsigned ABIAlignment = TLI.getTargetData()->
2608 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2609 if (ST->getAlignment() < ABIAlignment)
2610 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
2614 case TargetLowering::Custom:
2615 Tmp1 = TLI.LowerOperation(Result, DAG);
2616 if (Tmp1.getNode()) Result = Tmp1;
2618 case TargetLowering::Promote:
2619 assert(VT.isVector() && "Unknown legal promote case!");
2620 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
2621 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2622 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
2623 ST->getSrcValue(), SVOffset, isVolatile,
2630 if (!ST->getMemoryVT().isVector()) {
2631 // Truncate the value and store the result.
2632 Tmp3 = PromoteOp(ST->getValue());
2633 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2634 SVOffset, ST->getMemoryVT(),
2635 isVolatile, Alignment);
2638 // Fall thru to expand for vector
2640 unsigned IncrementSize = 0;
2643 // If this is a vector type, then we have to calculate the increment as
2644 // the product of the element size in bytes, and the number of elements
2645 // in the high half of the vector.
2646 if (ST->getValue().getValueType().isVector()) {
2647 SDNode *InVal = ST->getValue().getNode();
2648 int InIx = ST->getValue().getResNo();
2649 MVT InVT = InVal->getValueType(InIx);
2650 unsigned NumElems = InVT.getVectorNumElements();
2651 MVT EVT = InVT.getVectorElementType();
2653 // Figure out if there is a simple type corresponding to this Vector
2654 // type. If so, convert to the vector type.
2655 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2656 if (TLI.isTypeLegal(TVT)) {
2657 // Turn this into a normal store of the vector type.
2658 Tmp3 = LegalizeOp(ST->getValue());
2659 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2660 SVOffset, isVolatile, Alignment);
2661 Result = LegalizeOp(Result);
2663 } else if (NumElems == 1) {
2664 // Turn this into a normal store of the scalar type.
2665 Tmp3 = ScalarizeVectorOp(ST->getValue());
2666 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2667 SVOffset, isVolatile, Alignment);
2668 // The scalarized value type may not be legal, e.g. it might require
2669 // promotion or expansion. Relegalize the scalar store.
2670 Result = LegalizeOp(Result);
2673 // Check if we have widen this node with another value
2674 std::map<SDValue, SDValue>::iterator I =
2675 WidenNodes.find(ST->getValue());
2676 if (I != WidenNodes.end()) {
2677 Result = StoreWidenVectorOp(ST, Tmp1, Tmp2);
2681 SplitVectorOp(ST->getValue(), Lo, Hi);
2682 IncrementSize = Lo.getNode()->getValueType(0).getVectorNumElements() *
2683 EVT.getSizeInBits()/8;
2687 ExpandOp(ST->getValue(), Lo, Hi);
2688 IncrementSize = Hi.getNode() ? Hi.getValueType().getSizeInBits()/8 : 0;
2690 if (Hi.getNode() && TLI.isBigEndian())
2694 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2695 SVOffset, isVolatile, Alignment);
2697 if (Hi.getNode() == NULL) {
2698 // Must be int <-> float one-to-one expansion.
2703 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2704 DAG.getIntPtrConstant(IncrementSize));
2705 assert(isTypeLegal(Tmp2.getValueType()) &&
2706 "Pointers must be legal!");
2707 SVOffset += IncrementSize;
2708 Alignment = MinAlign(Alignment, IncrementSize);
2709 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2710 SVOffset, isVolatile, Alignment);
2711 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2716 switch (getTypeAction(ST->getValue().getValueType())) {
2718 Tmp3 = LegalizeOp(ST->getValue());
2721 if (!ST->getValue().getValueType().isVector()) {
2722 // We can promote the value, the truncstore will still take care of it.
2723 Tmp3 = PromoteOp(ST->getValue());
2726 // Vector case falls through to expand
2728 // Just store the low part. This may become a non-trunc store, so make
2729 // sure to use getTruncStore, not UpdateNodeOperands below.
2730 ExpandOp(ST->getValue(), Tmp3, Tmp4);
2731 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2732 SVOffset, MVT::i8, isVolatile, Alignment);
2735 MVT StVT = ST->getMemoryVT();
2736 unsigned StWidth = StVT.getSizeInBits();
2738 if (StWidth != StVT.getStoreSizeInBits()) {
2739 // Promote to a byte-sized store with upper bits zero if not
2740 // storing an integral number of bytes. For example, promote
2741 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
2742 MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits());
2743 Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT);
2744 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2745 SVOffset, NVT, isVolatile, Alignment);
2746 } else if (StWidth & (StWidth - 1)) {
2747 // If not storing a power-of-2 number of bits, expand as two stores.
2748 assert(StVT.isExtended() && !StVT.isVector() &&
2749 "Unsupported truncstore!");
2750 unsigned RoundWidth = 1 << Log2_32(StWidth);
2751 assert(RoundWidth < StWidth);
2752 unsigned ExtraWidth = StWidth - RoundWidth;
2753 assert(ExtraWidth < RoundWidth);
2754 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2755 "Store size not an integral number of bytes!");
2756 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2757 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2759 unsigned IncrementSize;
2761 if (TLI.isLittleEndian()) {
2762 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
2763 // Store the bottom RoundWidth bits.
2764 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2766 isVolatile, Alignment);
2768 // Store the remaining ExtraWidth bits.
2769 IncrementSize = RoundWidth / 8;
2770 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2771 DAG.getIntPtrConstant(IncrementSize));
2772 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2773 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2774 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2775 SVOffset + IncrementSize, ExtraVT, isVolatile,
2776 MinAlign(Alignment, IncrementSize));
2778 // Big endian - avoid unaligned stores.
2779 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
2780 // Store the top RoundWidth bits.
2781 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2782 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2783 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset,
2784 RoundVT, isVolatile, Alignment);
2786 // Store the remaining ExtraWidth bits.
2787 IncrementSize = RoundWidth / 8;
2788 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2789 DAG.getIntPtrConstant(IncrementSize));
2790 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2791 SVOffset + IncrementSize, ExtraVT, isVolatile,
2792 MinAlign(Alignment, IncrementSize));
2795 // The order of the stores doesn't matter.
2796 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2798 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2799 Tmp2 != ST->getBasePtr())
2800 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2803 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
2804 default: assert(0 && "This action is not supported yet!");
2805 case TargetLowering::Legal:
2806 // If this is an unaligned store and the target doesn't support it,
2808 if (!TLI.allowsUnalignedMemoryAccesses()) {
2809 unsigned ABIAlignment = TLI.getTargetData()->
2810 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2811 if (ST->getAlignment() < ABIAlignment)
2812 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
2816 case TargetLowering::Custom:
2817 Result = TLI.LowerOperation(Result, DAG);
2820 // TRUNCSTORE:i16 i32 -> STORE i16
2821 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
2822 Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3);
2823 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset,
2824 isVolatile, Alignment);
2832 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2833 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2835 case ISD::STACKSAVE:
2836 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2837 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2838 Tmp1 = Result.getValue(0);
2839 Tmp2 = Result.getValue(1);
2841 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2842 default: assert(0 && "This action is not supported yet!");
2843 case TargetLowering::Legal: break;
2844 case TargetLowering::Custom:
2845 Tmp3 = TLI.LowerOperation(Result, DAG);
2846 if (Tmp3.getNode()) {
2847 Tmp1 = LegalizeOp(Tmp3);
2848 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2851 case TargetLowering::Expand:
2852 // Expand to CopyFromReg if the target set
2853 // StackPointerRegisterToSaveRestore.
2854 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2855 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
2856 Node->getValueType(0));
2857 Tmp2 = Tmp1.getValue(1);
2859 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
2860 Tmp2 = Node->getOperand(0);
2865 // Since stacksave produce two values, make sure to remember that we
2866 // legalized both of them.
2867 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2868 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2869 return Op.getResNo() ? Tmp2 : Tmp1;
2871 case ISD::STACKRESTORE:
2872 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2873 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2874 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2876 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2877 default: assert(0 && "This action is not supported yet!");
2878 case TargetLowering::Legal: break;
2879 case TargetLowering::Custom:
2880 Tmp1 = TLI.LowerOperation(Result, DAG);
2881 if (Tmp1.getNode()) Result = Tmp1;
2883 case TargetLowering::Expand:
2884 // Expand to CopyToReg if the target set
2885 // StackPointerRegisterToSaveRestore.
2886 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2887 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
2895 case ISD::READCYCLECOUNTER:
2896 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2897 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2898 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2899 Node->getValueType(0))) {
2900 default: assert(0 && "This action is not supported yet!");
2901 case TargetLowering::Legal:
2902 Tmp1 = Result.getValue(0);
2903 Tmp2 = Result.getValue(1);
2905 case TargetLowering::Custom:
2906 Result = TLI.LowerOperation(Result, DAG);
2907 Tmp1 = LegalizeOp(Result.getValue(0));
2908 Tmp2 = LegalizeOp(Result.getValue(1));
2912 // Since rdcc produce two values, make sure to remember that we legalized
2914 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2915 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2919 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2920 case Expand: assert(0 && "It's impossible to expand bools");
2922 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2925 assert(!Node->getOperand(0).getValueType().isVector() && "not possible");
2926 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2927 // Make sure the condition is either zero or one.
2928 unsigned BitWidth = Tmp1.getValueSizeInBits();
2929 if (!DAG.MaskedValueIsZero(Tmp1,
2930 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2931 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2935 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2936 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2938 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2940 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2941 default: assert(0 && "This action is not supported yet!");
2942 case TargetLowering::Legal: break;
2943 case TargetLowering::Custom: {
2944 Tmp1 = TLI.LowerOperation(Result, DAG);
2945 if (Tmp1.getNode()) Result = Tmp1;
2948 case TargetLowering::Expand:
2949 if (Tmp1.getOpcode() == ISD::SETCC) {
2950 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2952 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2954 Result = DAG.getSelectCC(Tmp1,
2955 DAG.getConstant(0, Tmp1.getValueType()),
2956 Tmp2, Tmp3, ISD::SETNE);
2959 case TargetLowering::Promote: {
2961 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2962 unsigned ExtOp, TruncOp;
2963 if (Tmp2.getValueType().isVector()) {
2964 ExtOp = ISD::BIT_CONVERT;
2965 TruncOp = ISD::BIT_CONVERT;
2966 } else if (Tmp2.getValueType().isInteger()) {
2967 ExtOp = ISD::ANY_EXTEND;
2968 TruncOp = ISD::TRUNCATE;
2970 ExtOp = ISD::FP_EXTEND;
2971 TruncOp = ISD::FP_ROUND;
2973 // Promote each of the values to the new type.
2974 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2975 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2976 // Perform the larger operation, then round down.
2977 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2978 if (TruncOp != ISD::FP_ROUND)
2979 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2981 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result,
2982 DAG.getIntPtrConstant(0));
2987 case ISD::SELECT_CC: {
2988 Tmp1 = Node->getOperand(0); // LHS
2989 Tmp2 = Node->getOperand(1); // RHS
2990 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2991 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2992 SDValue CC = Node->getOperand(4);
2994 LegalizeSetCC(TLI.getSetCCResultType(Tmp1.getValueType()), Tmp1, Tmp2, CC);
2996 // If we didn't get both a LHS and RHS back from LegalizeSetCC,
2997 // the LHS is a legal SETCC itself. In this case, we need to compare
2998 // the result against zero to select between true and false values.
2999 if (Tmp2.getNode() == 0) {
3000 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3001 CC = DAG.getCondCode(ISD::SETNE);
3003 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
3005 // Everything is legal, see if we should expand this op or something.
3006 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
3007 default: assert(0 && "This action is not supported yet!");
3008 case TargetLowering::Legal: break;
3009 case TargetLowering::Custom:
3010 Tmp1 = TLI.LowerOperation(Result, DAG);
3011 if (Tmp1.getNode()) Result = Tmp1;
3017 Tmp1 = Node->getOperand(0);
3018 Tmp2 = Node->getOperand(1);
3019 Tmp3 = Node->getOperand(2);
3020 LegalizeSetCC(Node->getValueType(0), Tmp1, Tmp2, Tmp3);
3022 // If we had to Expand the SetCC operands into a SELECT node, then it may
3023 // not always be possible to return a true LHS & RHS. In this case, just
3024 // return the value we legalized, returned in the LHS
3025 if (Tmp2.getNode() == 0) {
3030 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
3031 default: assert(0 && "Cannot handle this action for SETCC yet!");
3032 case TargetLowering::Custom:
3035 case TargetLowering::Legal:
3036 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3038 Tmp4 = TLI.LowerOperation(Result, DAG);
3039 if (Tmp4.getNode()) Result = Tmp4;
3042 case TargetLowering::Promote: {
3043 // First step, figure out the appropriate operation to use.
3044 // Allow SETCC to not be supported for all legal data types
3045 // Mostly this targets FP
3046 MVT NewInTy = Node->getOperand(0).getValueType();
3047 MVT OldVT = NewInTy; OldVT = OldVT;
3049 // Scan for the appropriate larger type to use.
3051 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
3053 assert(NewInTy.isInteger() == OldVT.isInteger() &&
3054 "Fell off of the edge of the integer world");
3055 assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() &&
3056 "Fell off of the edge of the floating point world");
3058 // If the target supports SETCC of this type, use it.
3059 if (TLI.isOperationLegalOrCustom(ISD::SETCC, NewInTy))
3062 if (NewInTy.isInteger())
3063 assert(0 && "Cannot promote Legal Integer SETCC yet");
3065 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
3066 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
3068 Tmp1 = LegalizeOp(Tmp1);
3069 Tmp2 = LegalizeOp(Tmp2);
3070 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3071 Result = LegalizeOp(Result);
3074 case TargetLowering::Expand:
3075 // Expand a setcc node into a select_cc of the same condition, lhs, and
3076 // rhs that selects between const 1 (true) and const 0 (false).
3077 MVT VT = Node->getValueType(0);
3078 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
3079 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3085 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3086 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3087 SDValue CC = Node->getOperand(2);
3089 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, CC);
3091 // Everything is legal, see if we should expand this op or something.
3092 switch (TLI.getOperationAction(ISD::VSETCC, Tmp1.getValueType())) {
3093 default: assert(0 && "This action is not supported yet!");
3094 case TargetLowering::Legal: break;
3095 case TargetLowering::Custom:
3096 Tmp1 = TLI.LowerOperation(Result, DAG);
3097 if (Tmp1.getNode()) Result = Tmp1;
3099 case TargetLowering::Expand: {
3100 // Unroll into a nasty set of scalar code for now.
3101 MVT VT = Node->getValueType(0);
3102 unsigned NumElems = VT.getVectorNumElements();
3103 MVT EltVT = VT.getVectorElementType();
3104 MVT TmpEltVT = Tmp1.getValueType().getVectorElementType();
3105 SmallVector<SDValue, 8> Ops(NumElems);
3106 for (unsigned i = 0; i < NumElems; ++i) {
3107 SDValue In1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, TmpEltVT,
3108 Tmp1, DAG.getIntPtrConstant(i));
3109 Ops[i] = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(TmpEltVT), In1,
3110 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, TmpEltVT,
3111 Tmp2, DAG.getIntPtrConstant(i)),
3113 Ops[i] = DAG.getNode(ISD::SELECT, EltVT, Ops[i],
3114 DAG.getConstant(EltVT.getIntegerVTBitMask(),EltVT),
3115 DAG.getConstant(0, EltVT));
3117 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], NumElems);
3124 case ISD::SHL_PARTS:
3125 case ISD::SRA_PARTS:
3126 case ISD::SRL_PARTS: {
3127 SmallVector<SDValue, 8> Ops;
3128 bool Changed = false;
3129 unsigned N = Node->getNumOperands();
3130 for (unsigned i = 0; i + 1 < N; ++i) {
3131 Ops.push_back(LegalizeOp(Node->getOperand(i)));
3132 Changed |= Ops.back() != Node->getOperand(i);
3134 Ops.push_back(LegalizeOp(DAG.getShiftAmountOperand(Node->getOperand(N-1))));
3135 Changed |= Ops.back() != Node->getOperand(N-1);
3137 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
3139 switch (TLI.getOperationAction(Node->getOpcode(),
3140 Node->getValueType(0))) {
3141 default: assert(0 && "This action is not supported yet!");
3142 case TargetLowering::Legal: break;
3143 case TargetLowering::Custom:
3144 Tmp1 = TLI.LowerOperation(Result, DAG);
3145 if (Tmp1.getNode()) {
3146 SDValue Tmp2, RetVal(0, 0);
3147 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
3148 Tmp2 = LegalizeOp(Tmp1.getValue(i));
3149 AddLegalizedOperand(SDValue(Node, i), Tmp2);
3150 if (i == Op.getResNo())
3153 assert(RetVal.getNode() && "Illegal result number");
3159 // Since these produce multiple values, make sure to remember that we
3160 // legalized all of them.
3161 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
3162 AddLegalizedOperand(SDValue(Node, i), Result.getValue(i));
3163 return Result.getValue(Op.getResNo());
3185 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3186 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3188 if ((Node->getOpcode() == ISD::SHL ||
3189 Node->getOpcode() == ISD::SRL ||
3190 Node->getOpcode() == ISD::SRA) &&
3191 !Node->getValueType(0).isVector())
3192 Tmp2 = DAG.getShiftAmountOperand(Tmp2);
3194 switch (getTypeAction(Tmp2.getValueType())) {
3195 case Expand: assert(0 && "Not possible");
3197 Tmp2 = LegalizeOp(Tmp2); // Legalize the RHS.
3200 Tmp2 = PromoteOp(Tmp2); // Promote the RHS.
3204 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3206 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3207 default: assert(0 && "BinOp legalize operation not supported");
3208 case TargetLowering::Legal: break;
3209 case TargetLowering::Custom:
3210 Tmp1 = TLI.LowerOperation(Result, DAG);
3211 if (Tmp1.getNode()) {
3215 // Fall through if the custom lower can't deal with the operation
3216 case TargetLowering::Expand: {
3217 MVT VT = Op.getValueType();
3219 // See if multiply or divide can be lowered using two-result operations.
3220 SDVTList VTs = DAG.getVTList(VT, VT);
3221 if (Node->getOpcode() == ISD::MUL) {
3222 // We just need the low half of the multiply; try both the signed
3223 // and unsigned forms. If the target supports both SMUL_LOHI and
3224 // UMUL_LOHI, form a preference by checking which forms of plain
3225 // MULH it supports.
3226 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3227 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3228 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3229 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3230 unsigned OpToUse = 0;
3231 if (HasSMUL_LOHI && !HasMULHS) {
3232 OpToUse = ISD::SMUL_LOHI;
3233 } else if (HasUMUL_LOHI && !HasMULHU) {
3234 OpToUse = ISD::UMUL_LOHI;
3235 } else if (HasSMUL_LOHI) {
3236 OpToUse = ISD::SMUL_LOHI;
3237 } else if (HasUMUL_LOHI) {
3238 OpToUse = ISD::UMUL_LOHI;
3241 Result = SDValue(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).getNode(), 0);
3245 if (Node->getOpcode() == ISD::MULHS &&
3246 TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) {
3247 Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).getNode(),
3251 if (Node->getOpcode() == ISD::MULHU &&
3252 TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) {
3253 Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).getNode(),
3257 if (Node->getOpcode() == ISD::SDIV &&
3258 TLI.isOperationLegalOrCustom(ISD::SDIVREM, VT)) {
3259 Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(),
3263 if (Node->getOpcode() == ISD::UDIV &&
3264 TLI.isOperationLegalOrCustom(ISD::UDIVREM, VT)) {
3265 Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(),
3270 // Check to see if we have a libcall for this operator.
3271 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3272 bool isSigned = false;
3273 switch (Node->getOpcode()) {
3276 if (VT == MVT::i32) {
3277 LC = Node->getOpcode() == ISD::UDIV
3278 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
3279 isSigned = Node->getOpcode() == ISD::SDIV;
3284 LC = RTLIB::MUL_I32;
3285 else if (VT == MVT::i64)
3286 LC = RTLIB::MUL_I64;
3289 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
3290 RTLIB::POW_PPCF128);
3293 LC = GetFPLibCall(VT, RTLIB::DIV_F32, RTLIB::DIV_F64, RTLIB::DIV_F80,
3294 RTLIB::DIV_PPCF128);
3298 if (LC != RTLIB::UNKNOWN_LIBCALL) {
3300 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3304 assert(Node->getValueType(0).isVector() &&
3305 "Cannot expand this binary operator!");
3306 // Expand the operation into a bunch of nasty scalar code.
3307 Result = LegalizeOp(UnrollVectorOp(Op));
3310 case TargetLowering::Promote: {
3311 switch (Node->getOpcode()) {
3312 default: assert(0 && "Do not know how to promote this BinOp!");
3316 MVT OVT = Node->getValueType(0);
3317 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3318 assert(OVT.isVector() && "Cannot promote this BinOp!");
3319 // Bit convert each of the values to the new type.
3320 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
3321 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
3322 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3323 // Bit convert the result back the original type.
3324 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
3332 case ISD::SMUL_LOHI:
3333 case ISD::UMUL_LOHI:
3336 // These nodes will only be produced by target-specific lowering, so
3337 // they shouldn't be here if they aren't legal.
3338 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
3339 "This must be legal!");
3341 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3342 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3343 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3346 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
3347 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3348 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3349 case Expand: assert(0 && "Not possible");
3351 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3354 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3358 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3360 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3361 default: assert(0 && "Operation not supported");
3362 case TargetLowering::Custom:
3363 Tmp1 = TLI.LowerOperation(Result, DAG);
3364 if (Tmp1.getNode()) Result = Tmp1;
3366 case TargetLowering::Legal: break;
3367 case TargetLowering::Expand: {
3368 // If this target supports fabs/fneg natively and select is cheap,
3369 // do this efficiently.
3370 if (!TLI.isSelectExpensive() &&
3371 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
3372 TargetLowering::Legal &&
3373 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
3374 TargetLowering::Legal) {
3375 // Get the sign bit of the RHS.
3377 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
3378 SDValue SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
3379 SignBit = DAG.getSetCC(TLI.getSetCCResultType(IVT),
3380 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
3381 // Get the absolute value of the result.
3382 SDValue AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
3383 // Select between the nabs and abs value based on the sign bit of
3385 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
3386 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
3389 Result = LegalizeOp(Result);
3393 // Otherwise, do bitwise ops!
3395 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
3396 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
3397 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
3398 Result = LegalizeOp(Result);
3406 Tmp1 = LegalizeOp(Node->getOperand(0));
3407 Tmp2 = LegalizeOp(Node->getOperand(1));
3408 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3409 Tmp3 = Result.getValue(0);
3410 Tmp4 = Result.getValue(1);
3412 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3413 default: assert(0 && "This action is not supported yet!");
3414 case TargetLowering::Legal:
3416 case TargetLowering::Custom:
3417 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
3418 if (Tmp1.getNode() != NULL) {
3419 Tmp3 = LegalizeOp(Tmp1);
3420 Tmp4 = LegalizeOp(Tmp1.getValue(1));
3424 // Since this produces two values, make sure to remember that we legalized
3426 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
3427 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
3428 return Op.getResNo() ? Tmp4 : Tmp3;
3432 Tmp1 = LegalizeOp(Node->getOperand(0));
3433 Tmp2 = LegalizeOp(Node->getOperand(1));
3434 Tmp3 = LegalizeOp(Node->getOperand(2));
3435 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3436 Tmp3 = Result.getValue(0);
3437 Tmp4 = Result.getValue(1);
3439 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3440 default: assert(0 && "This action is not supported yet!");
3441 case TargetLowering::Legal:
3443 case TargetLowering::Custom:
3444 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
3445 if (Tmp1.getNode() != NULL) {
3446 Tmp3 = LegalizeOp(Tmp1);
3447 Tmp4 = LegalizeOp(Tmp1.getValue(1));
3451 // Since this produces two values, make sure to remember that we legalized
3453 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
3454 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
3455 return Op.getResNo() ? Tmp4 : Tmp3;
3457 case ISD::BUILD_PAIR: {
3458 MVT PairTy = Node->getValueType(0);
3459 // TODO: handle the case where the Lo and Hi operands are not of legal type
3460 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
3461 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
3462 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
3463 case TargetLowering::Promote:
3464 case TargetLowering::Custom:
3465 assert(0 && "Cannot promote/custom this yet!");
3466 case TargetLowering::Legal:
3467 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
3468 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
3470 case TargetLowering::Expand:
3471 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
3472 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
3473 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
3474 DAG.getConstant(PairTy.getSizeInBits()/2,
3475 TLI.getShiftAmountTy()));
3476 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
3485 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3486 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3488 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3489 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
3490 case TargetLowering::Custom:
3493 case TargetLowering::Legal:
3494 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3496 Tmp1 = TLI.LowerOperation(Result, DAG);
3497 if (Tmp1.getNode()) Result = Tmp1;
3500 case TargetLowering::Expand: {
3501 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
3502 bool isSigned = DivOpc == ISD::SDIV;
3503 MVT VT = Node->getValueType(0);
3505 // See if remainder can be lowered using two-result operations.
3506 SDVTList VTs = DAG.getVTList(VT, VT);
3507 if (Node->getOpcode() == ISD::SREM &&
3508 TLI.isOperationLegalOrCustom(ISD::SDIVREM, VT)) {
3509 Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(), 1);
3512 if (Node->getOpcode() == ISD::UREM &&
3513 TLI.isOperationLegalOrCustom(ISD::UDIVREM, VT)) {
3514 Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(), 1);
3518 if (VT.isInteger()) {
3519 if (TLI.getOperationAction(DivOpc, VT) ==
3520 TargetLowering::Legal) {
3522 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
3523 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
3524 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
3525 } else if (VT.isVector()) {
3526 Result = LegalizeOp(UnrollVectorOp(Op));
3528 assert(VT == MVT::i32 &&
3529 "Cannot expand this binary operator!");
3530 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
3531 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
3533 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3536 assert(VT.isFloatingPoint() &&
3537 "remainder op must have integer or floating-point type");
3538 if (VT.isVector()) {
3539 Result = LegalizeOp(UnrollVectorOp(Op));
3541 // Floating point mod -> fmod libcall.
3542 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
3543 RTLIB::REM_F80, RTLIB::REM_PPCF128);
3545 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3553 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3554 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3556 MVT VT = Node->getValueType(0);
3557 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
3558 default: assert(0 && "This action is not supported yet!");
3559 case TargetLowering::Custom:
3562 case TargetLowering::Legal:
3563 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3564 Result = Result.getValue(0);
3565 Tmp1 = Result.getValue(1);
3568 Tmp2 = TLI.LowerOperation(Result, DAG);
3569 if (Tmp2.getNode()) {
3570 Result = LegalizeOp(Tmp2);
3571 Tmp1 = LegalizeOp(Tmp2.getValue(1));
3575 case TargetLowering::Expand: {
3576 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3577 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
3578 // Increment the pointer, VAList, to the next vaarg
3579 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3580 DAG.getConstant(TLI.getTargetData()->
3581 getTypePaddedSize(VT.getTypeForMVT()),
3582 TLI.getPointerTy()));
3583 // Store the incremented VAList to the legalized pointer
3584 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
3585 // Load the actual argument out of the pointer VAList
3586 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
3587 Tmp1 = LegalizeOp(Result.getValue(1));
3588 Result = LegalizeOp(Result);
3592 // Since VAARG produces two values, make sure to remember that we
3593 // legalized both of them.
3594 AddLegalizedOperand(SDValue(Node, 0), Result);
3595 AddLegalizedOperand(SDValue(Node, 1), Tmp1);
3596 return Op.getResNo() ? Tmp1 : Result;
3600 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3601 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
3602 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
3604 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
3605 default: assert(0 && "This action is not supported yet!");
3606 case TargetLowering::Custom:
3609 case TargetLowering::Legal:
3610 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
3611 Node->getOperand(3), Node->getOperand(4));
3613 Tmp1 = TLI.LowerOperation(Result, DAG);
3614 if (Tmp1.getNode()) Result = Tmp1;
3617 case TargetLowering::Expand:
3618 // This defaults to loading a pointer from the input and storing it to the
3619 // output, returning the chain.
3620 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3621 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3622 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VS, 0);
3623 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VD, 0);
3629 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3630 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3632 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
3633 default: assert(0 && "This action is not supported yet!");
3634 case TargetLowering::Custom:
3637 case TargetLowering::Legal:
3638 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3640 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
3641 if (Tmp1.getNode()) Result = Tmp1;
3644 case TargetLowering::Expand:
3645 Result = Tmp1; // Default to a no-op, return the chain
3651 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3652 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3654 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3656 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
3657 default: assert(0 && "This action is not supported yet!");
3658 case TargetLowering::Legal: break;
3659 case TargetLowering::Custom:
3660 Tmp1 = TLI.LowerOperation(Result, DAG);
3661 if (Tmp1.getNode()) Result = Tmp1;
3668 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3669 Tmp2 = LegalizeOp(DAG.getShiftAmountOperand(Node->getOperand(1))); // RHS
3670 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3671 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3673 assert(0 && "ROTL/ROTR legalize operation not supported");
3675 case TargetLowering::Legal:
3677 case TargetLowering::Custom:
3678 Tmp1 = TLI.LowerOperation(Result, DAG);
3679 if (Tmp1.getNode()) Result = Tmp1;
3681 case TargetLowering::Promote:
3682 assert(0 && "Do not know how to promote ROTL/ROTR");
3684 case TargetLowering::Expand:
3685 assert(0 && "Do not know how to expand ROTL/ROTR");
3691 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3692 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3693 case TargetLowering::Custom:
3694 assert(0 && "Cannot custom legalize this yet!");
3695 case TargetLowering::Legal:
3696 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3698 case TargetLowering::Promote: {
3699 MVT OVT = Tmp1.getValueType();
3700 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3701 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3703 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3704 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3705 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3706 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3709 case TargetLowering::Expand:
3710 Result = ExpandBSWAP(Tmp1);
3718 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3719 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3720 case TargetLowering::Custom:
3721 case TargetLowering::Legal:
3722 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3723 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3724 TargetLowering::Custom) {
3725 Tmp1 = TLI.LowerOperation(Result, DAG);
3726 if (Tmp1.getNode()) {
3731 case TargetLowering::Promote: {
3732 MVT OVT = Tmp1.getValueType();
3733 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3735 // Zero extend the argument.
3736 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3737 // Perform the larger operation, then subtract if needed.
3738 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
3739 switch (Node->getOpcode()) {
3744 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3745 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1.getValueType()), Tmp1,
3746 DAG.getConstant(NVT.getSizeInBits(), NVT),
3748 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3749 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3752 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3753 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3754 DAG.getConstant(NVT.getSizeInBits() -
3755 OVT.getSizeInBits(), NVT));
3760 case TargetLowering::Expand:
3761 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
3781 case ISD::FNEARBYINT:
3782 Tmp1 = LegalizeOp(Node->getOperand(0));
3783 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3784 case TargetLowering::Promote:
3785 case TargetLowering::Custom:
3788 case TargetLowering::Legal:
3789 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3791 Tmp1 = TLI.LowerOperation(Result, DAG);
3792 if (Tmp1.getNode()) Result = Tmp1;
3795 case TargetLowering::Expand:
3796 switch (Node->getOpcode()) {
3797 default: assert(0 && "Unreachable!");
3799 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3800 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3801 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
3804 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3805 MVT VT = Node->getValueType(0);
3806 Tmp2 = DAG.getConstantFP(0.0, VT);
3807 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1.getValueType()),
3808 Tmp1, Tmp2, ISD::SETUGT);
3809 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
3810 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
3825 case ISD::FNEARBYINT: {
3826 MVT VT = Node->getValueType(0);
3828 // Expand unsupported unary vector operators by unrolling them.
3829 if (VT.isVector()) {
3830 Result = LegalizeOp(UnrollVectorOp(Op));
3834 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3835 switch(Node->getOpcode()) {
3837 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3838 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
3841 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
3842 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
3845 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
3846 RTLIB::COS_F80, RTLIB::COS_PPCF128);
3849 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
3850 RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
3853 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3854 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
3857 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3858 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
3861 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
3862 RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
3865 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3866 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
3869 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3870 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
3873 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3874 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128);
3877 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3878 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128);
3881 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64,
3882 RTLIB::RINT_F80, RTLIB::RINT_PPCF128);
3884 case ISD::FNEARBYINT:
3885 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
3886 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
3889 default: assert(0 && "Unreachable!");
3892 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3900 MVT VT = Node->getValueType(0);
3902 // Expand unsupported unary vector operators by unrolling them.
3903 if (VT.isVector()) {
3904 Result = LegalizeOp(UnrollVectorOp(Op));
3908 // We always lower FPOWI into a libcall. No target support for it yet.
3909 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
3910 RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
3912 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3915 case ISD::BIT_CONVERT:
3916 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3917 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3918 Node->getValueType(0));
3919 } else if (Op.getOperand(0).getValueType().isVector()) {
3920 // The input has to be a vector type, we have to either scalarize it, pack
3921 // it, or convert it based on whether the input vector type is legal.
3922 SDNode *InVal = Node->getOperand(0).getNode();
3923 int InIx = Node->getOperand(0).getResNo();
3924 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
3925 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
3927 // Figure out if there is a simple type corresponding to this Vector
3928 // type. If so, convert to the vector type.
3929 MVT TVT = MVT::getVectorVT(EVT, NumElems);
3930 if (TLI.isTypeLegal(TVT)) {
3931 // Turn this into a bit convert of the vector input.
3932 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3933 LegalizeOp(Node->getOperand(0)));
3935 } else if (NumElems == 1) {
3936 // Turn this into a bit convert of the scalar input.
3937 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3938 ScalarizeVectorOp(Node->getOperand(0)));
3941 // FIXME: UNIMP! Store then reload
3942 assert(0 && "Cast from unsupported vector type not implemented yet!");
3945 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3946 Node->getOperand(0).getValueType())) {
3947 default: assert(0 && "Unknown operation action!");
3948 case TargetLowering::Expand:
3949 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3950 Node->getValueType(0));
3952 case TargetLowering::Legal:
3953 Tmp1 = LegalizeOp(Node->getOperand(0));
3954 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3959 case ISD::CONVERT_RNDSAT: {
3960 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
3962 default: assert(0 && "Unknown cvt code!");
3973 SDValue DTyOp = Node->getOperand(1);
3974 SDValue STyOp = Node->getOperand(2);
3975 SDValue RndOp = Node->getOperand(3);
3976 SDValue SatOp = Node->getOperand(4);
3977 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3978 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3980 Tmp1 = LegalizeOp(Node->getOperand(0));
3981 Result = DAG.UpdateNodeOperands(Result, Tmp1, DTyOp, STyOp,
3983 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3984 TargetLowering::Custom) {
3985 Tmp1 = TLI.LowerOperation(Result, DAG);
3986 if (Tmp1.getNode()) Result = Tmp1;
3990 Result = PromoteOp(Node->getOperand(0));
3991 // For FP, make Op1 a i32
3993 Result = DAG.getConvertRndSat(Op.getValueType(), Result,
3994 DTyOp, STyOp, RndOp, SatOp, CvtCode);
3999 } // end switch CvtCode
4002 // Conversion operators. The source and destination have different types.
4003 case ISD::SINT_TO_FP:
4004 case ISD::UINT_TO_FP: {
4005 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
4006 Result = LegalizeINT_TO_FP(Result, isSigned,
4007 Node->getValueType(0), Node->getOperand(0));
4011 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4013 Tmp1 = LegalizeOp(Node->getOperand(0));
4014 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
4015 default: assert(0 && "Unknown TRUNCATE legalization operation action!");
4016 case TargetLowering::Custom:
4019 case TargetLowering::Legal:
4020 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4022 Tmp1 = TLI.LowerOperation(Result, DAG);
4023 if (Tmp1.getNode()) Result = Tmp1;
4026 case TargetLowering::Expand:
4027 assert(Result.getValueType().isVector() && "must be vector type");
4028 // Unroll the truncate. We should do better.
4029 Result = LegalizeOp(UnrollVectorOp(Result));
4033 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4035 // Since the result is legal, we should just be able to truncate the low
4036 // part of the source.
4037 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
4040 Result = PromoteOp(Node->getOperand(0));
4041 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
4046 case ISD::FP_TO_SINT:
4047 case ISD::FP_TO_UINT:
4048 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4050 Tmp1 = LegalizeOp(Node->getOperand(0));
4052 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
4053 default: assert(0 && "Unknown operation action!");
4054 case TargetLowering::Custom:
4057 case TargetLowering::Legal:
4058 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4060 Tmp1 = TLI.LowerOperation(Result, DAG);
4061 if (Tmp1.getNode()) Result = Tmp1;
4064 case TargetLowering::Promote:
4065 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
4066 Node->getOpcode() == ISD::FP_TO_SINT);
4068 case TargetLowering::Expand:
4069 if (Node->getOpcode() == ISD::FP_TO_UINT) {
4070 SDValue True, False;
4071 MVT VT = Node->getOperand(0).getValueType();
4072 MVT NVT = Node->getValueType(0);
4073 const uint64_t zero[] = {0, 0};
4074 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero));
4075 APInt x = APInt::getSignBit(NVT.getSizeInBits());
4076 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
4077 Tmp2 = DAG.getConstantFP(apf, VT);
4078 Tmp3 = DAG.getSetCC(TLI.getSetCCResultType(VT), Node->getOperand(0),
4080 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
4081 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
4082 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
4084 False = DAG.getNode(ISD::XOR, NVT, False,
4085 DAG.getConstant(x, NVT));
4086 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
4089 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
4095 MVT VT = Op.getValueType();
4096 MVT OVT = Node->getOperand(0).getValueType();
4097 // Convert ppcf128 to i32
4098 if (OVT == MVT::ppcf128 && VT == MVT::i32) {
4099 if (Node->getOpcode() == ISD::FP_TO_SINT) {
4100 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128,
4101 Node->getOperand(0), DAG.getValueType(MVT::f64));
4102 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result,
4103 DAG.getIntPtrConstant(1));
4104 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result);
4106 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
4107 APFloat apf = APFloat(APInt(128, 2, TwoE31));
4108 Tmp2 = DAG.getConstantFP(apf, OVT);
4109 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
4110 // FIXME: generated code sucks.
4111 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2,
4112 DAG.getNode(ISD::ADD, MVT::i32,
4113 DAG.getNode(ISD::FP_TO_SINT, VT,
4114 DAG.getNode(ISD::FSUB, OVT,
4115 Node->getOperand(0), Tmp2)),
4116 DAG.getConstant(0x80000000, MVT::i32)),
4117 DAG.getNode(ISD::FP_TO_SINT, VT,
4118 Node->getOperand(0)),
4119 DAG.getCondCode(ISD::SETGE));
4123 // Convert f32 / f64 to i32 / i64 / i128.
4124 RTLIB::Libcall LC = (Node->getOpcode() == ISD::FP_TO_SINT) ?
4125 RTLIB::getFPTOSINT(OVT, VT) : RTLIB::getFPTOUINT(OVT, VT);
4126 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpectd fp-to-int conversion!");
4128 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
4132 Tmp1 = PromoteOp(Node->getOperand(0));
4133 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
4134 Result = LegalizeOp(Result);
4139 case ISD::FP_EXTEND: {
4140 MVT DstVT = Op.getValueType();
4141 MVT SrcVT = Op.getOperand(0).getValueType();
4142 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
4143 // The only other way we can lower this is to turn it into a STORE,
4144 // LOAD pair, targetting a temporary location (a stack slot).
4145 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT);
4148 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4149 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4151 Tmp1 = LegalizeOp(Node->getOperand(0));
4152 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4155 Tmp1 = PromoteOp(Node->getOperand(0));
4156 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1);
4161 case ISD::FP_ROUND: {
4162 MVT DstVT = Op.getValueType();
4163 MVT SrcVT = Op.getOperand(0).getValueType();
4164 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
4165 if (SrcVT == MVT::ppcf128) {
4167 ExpandOp(Node->getOperand(0), Lo, Result);
4168 // Round it the rest of the way (e.g. to f32) if needed.
4169 if (DstVT!=MVT::f64)
4170 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1));
4173 // The only other way we can lower this is to turn it into a STORE,
4174 // LOAD pair, targetting a temporary location (a stack slot).
4175 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT);
4178 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4179 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4181 Tmp1 = LegalizeOp(Node->getOperand(0));
4182 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
4185 Tmp1 = PromoteOp(Node->getOperand(0));
4186 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1,
4187 Node->getOperand(1));
4192 case ISD::ANY_EXTEND:
4193 case ISD::ZERO_EXTEND:
4194 case ISD::SIGN_EXTEND:
4195 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4196 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4198 Tmp1 = LegalizeOp(Node->getOperand(0));
4199 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4200 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
4201 TargetLowering::Custom) {
4202 Tmp1 = TLI.LowerOperation(Result, DAG);
4203 if (Tmp1.getNode()) Result = Tmp1;
4207 switch (Node->getOpcode()) {
4208 case ISD::ANY_EXTEND:
4209 Tmp1 = PromoteOp(Node->getOperand(0));
4210 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
4212 case ISD::ZERO_EXTEND:
4213 Result = PromoteOp(Node->getOperand(0));
4214 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
4215 Result = DAG.getZeroExtendInReg(Result,
4216 Node->getOperand(0).getValueType());
4218 case ISD::SIGN_EXTEND:
4219 Result = PromoteOp(Node->getOperand(0));
4220 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
4221 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
4223 DAG.getValueType(Node->getOperand(0).getValueType()));
4228 case ISD::FP_ROUND_INREG:
4229 case ISD::SIGN_EXTEND_INREG: {
4230 Tmp1 = LegalizeOp(Node->getOperand(0));
4231 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
4233 // If this operation is not supported, convert it to a shl/shr or load/store
4235 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
4236 default: assert(0 && "This action not supported for this op yet!");
4237 case TargetLowering::Legal:
4238 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
4240 case TargetLowering::Expand:
4241 // If this is an integer extend and shifts are supported, do that.
4242 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
4243 // NOTE: we could fall back on load/store here too for targets without
4244 // SAR. However, it is doubtful that any exist.
4245 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() -
4246 ExtraVT.getSizeInBits();
4247 SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
4248 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
4249 Node->getOperand(0), ShiftCst);
4250 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
4252 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
4253 // The only way we can lower this is to turn it into a TRUNCSTORE,
4254 // EXTLOAD pair, targetting a temporary location (a stack slot).
4256 // NOTE: there is a choice here between constantly creating new stack
4257 // slots and always reusing the same one. We currently always create
4258 // new ones, as reuse may inhibit scheduling.
4259 Result = EmitStackConvert(Node->getOperand(0), ExtraVT,
4260 Node->getValueType(0));
4262 assert(0 && "Unknown op");
4268 case ISD::TRAMPOLINE: {
4270 for (unsigned i = 0; i != 6; ++i)
4271 Ops[i] = LegalizeOp(Node->getOperand(i));
4272 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
4273 // The only option for this node is to custom lower it.
4274 Result = TLI.LowerOperation(Result, DAG);
4275 assert(Result.getNode() && "Should always custom lower!");
4277 // Since trampoline produces two values, make sure to remember that we
4278 // legalized both of them.
4279 Tmp1 = LegalizeOp(Result.getValue(1));
4280 Result = LegalizeOp(Result);
4281 AddLegalizedOperand(SDValue(Node, 0), Result);
4282 AddLegalizedOperand(SDValue(Node, 1), Tmp1);
4283 return Op.getResNo() ? Tmp1 : Result;
4285 case ISD::FLT_ROUNDS_: {
4286 MVT VT = Node->getValueType(0);
4287 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4288 default: assert(0 && "This action not supported for this op yet!");
4289 case TargetLowering::Custom:
4290 Result = TLI.LowerOperation(Op, DAG);
4291 if (Result.getNode()) break;
4293 case TargetLowering::Legal:
4294 // If this operation is not supported, lower it to constant 1
4295 Result = DAG.getConstant(1, VT);
4301 MVT VT = Node->getValueType(0);
4302 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4303 default: assert(0 && "This action not supported for this op yet!");
4304 case TargetLowering::Legal:
4305 Tmp1 = LegalizeOp(Node->getOperand(0));
4306 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4308 case TargetLowering::Custom:
4309 Result = TLI.LowerOperation(Op, DAG);
4310 if (Result.getNode()) break;
4312 case TargetLowering::Expand:
4313 // If this operation is not supported, lower it to 'abort()' call
4314 Tmp1 = LegalizeOp(Node->getOperand(0));
4315 TargetLowering::ArgListTy Args;
4316 std::pair<SDValue,SDValue> CallResult =
4317 TLI.LowerCallTo(Tmp1, Type::VoidTy,
4318 false, false, false, false, CallingConv::C, false,
4319 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
4321 Result = CallResult.second;
4329 MVT VT = Node->getValueType(0);
4330 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4331 default: assert(0 && "This action not supported for this op yet!");
4332 case TargetLowering::Custom:
4333 Result = TLI.LowerOperation(Op, DAG);
4334 if (Result.getNode()) break;
4336 case TargetLowering::Legal: {
4337 SDValue LHS = LegalizeOp(Node->getOperand(0));
4338 SDValue RHS = LegalizeOp(Node->getOperand(1));
4340 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
4341 ISD::ADD : ISD::SUB, LHS.getValueType(),
4343 MVT OType = Node->getValueType(1);
4345 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
4347 // LHSSign -> LHS >= 0
4348 // RHSSign -> RHS >= 0
4349 // SumSign -> Sum >= 0
4352 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
4354 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
4356 SDValue LHSSign = DAG.getSetCC(OType, LHS, Zero, ISD::SETGE);
4357 SDValue RHSSign = DAG.getSetCC(OType, RHS, Zero, ISD::SETGE);
4358 SDValue SignsMatch = DAG.getSetCC(OType, LHSSign, RHSSign,
4359 Node->getOpcode() == ISD::SADDO ?
4360 ISD::SETEQ : ISD::SETNE);
4362 SDValue SumSign = DAG.getSetCC(OType, Sum, Zero, ISD::SETGE);
4363 SDValue SumSignNE = DAG.getSetCC(OType, LHSSign, SumSign, ISD::SETNE);
4365 SDValue Cmp = DAG.getNode(ISD::AND, OType, SignsMatch, SumSignNE);
4367 MVT ValueVTs[] = { LHS.getValueType(), OType };
4368 SDValue Ops[] = { Sum, Cmp };
4370 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(&ValueVTs[0], 2),
4372 SDNode *RNode = Result.getNode();
4373 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), SDValue(RNode, 0));
4374 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), SDValue(RNode, 1));
4383 MVT VT = Node->getValueType(0);
4384 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4385 default: assert(0 && "This action not supported for this op yet!");
4386 case TargetLowering::Custom:
4387 Result = TLI.LowerOperation(Op, DAG);
4388 if (Result.getNode()) break;
4390 case TargetLowering::Legal: {
4391 SDValue LHS = LegalizeOp(Node->getOperand(0));
4392 SDValue RHS = LegalizeOp(Node->getOperand(1));
4394 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
4395 ISD::ADD : ISD::SUB, LHS.getValueType(),
4397 MVT OType = Node->getValueType(1);
4398 SDValue Cmp = DAG.getSetCC(OType, Sum, LHS,
4399 Node->getOpcode () == ISD::UADDO ?
4400 ISD::SETULT : ISD::SETUGT);
4402 MVT ValueVTs[] = { LHS.getValueType(), OType };
4403 SDValue Ops[] = { Sum, Cmp };
4405 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(&ValueVTs[0], 2),
4407 SDNode *RNode = Result.getNode();
4408 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), SDValue(RNode, 0));
4409 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), SDValue(RNode, 1));
4418 MVT VT = Node->getValueType(0);
4419 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4420 default: assert(0 && "This action is not supported at all!");
4421 case TargetLowering::Custom:
4422 Result = TLI.LowerOperation(Op, DAG);
4423 if (Result.getNode()) break;
4425 case TargetLowering::Legal:
4426 // FIXME: According to Hacker's Delight, this can be implemented in
4427 // target independent lowering, but it would be inefficient, since it
4428 // requires a division + a branch.
4429 assert(0 && "Target independent lowering is not supported for SMULO/UMULO!");
4437 assert(Result.getValueType() == Op.getValueType() &&
4438 "Bad legalization!");
4440 // Make sure that the generated code is itself legal.
4442 Result = LegalizeOp(Result);
4444 // Note that LegalizeOp may be reentered even from single-use nodes, which
4445 // means that we always must cache transformed nodes.
4446 AddLegalizedOperand(Op, Result);
4450 /// PromoteOp - Given an operation that produces a value in an invalid type,
4451 /// promote it to compute the value into a larger type. The produced value will
4452 /// have the correct bits for the low portion of the register, but no guarantee
4453 /// is made about the top bits: it may be zero, sign-extended, or garbage.
4454 SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) {
4455 MVT VT = Op.getValueType();
4456 MVT NVT = TLI.getTypeToTransformTo(VT);
4457 assert(getTypeAction(VT) == Promote &&
4458 "Caller should expand or legalize operands that are not promotable!");
4459 assert(NVT.bitsGT(VT) && NVT.isInteger() == VT.isInteger() &&
4460 "Cannot promote to smaller type!");
4462 SDValue Tmp1, Tmp2, Tmp3;
4464 SDNode *Node = Op.getNode();
4466 DenseMap<SDValue, SDValue>::iterator I = PromotedNodes.find(Op);
4467 if (I != PromotedNodes.end()) return I->second;
4469 switch (Node->getOpcode()) {
4470 case ISD::CopyFromReg:
4471 assert(0 && "CopyFromReg must be legal!");
4474 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
4476 assert(0 && "Do not know how to promote this operator!");
4479 Result = DAG.getNode(ISD::UNDEF, NVT);
4483 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
4485 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
4486 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
4488 case ISD::ConstantFP:
4489 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
4490 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
4494 MVT VT0 = Node->getOperand(0).getValueType();
4495 assert(isTypeLegal(TLI.getSetCCResultType(VT0))
4496 && "SetCC type is not legal??");
4497 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(VT0),
4498 Node->getOperand(0), Node->getOperand(1),
4499 Node->getOperand(2));
4503 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4505 Result = LegalizeOp(Node->getOperand(0));
4506 assert(Result.getValueType().bitsGE(NVT) &&
4507 "This truncation doesn't make sense!");
4508 if (Result.getValueType().bitsGT(NVT)) // Truncate to NVT instead of VT
4509 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
4512 // The truncation is not required, because we don't guarantee anything
4513 // about high bits anyway.
4514 Result = PromoteOp(Node->getOperand(0));
4517 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4518 // Truncate the low part of the expanded value to the result type
4519 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
4522 case ISD::SIGN_EXTEND:
4523 case ISD::ZERO_EXTEND:
4524 case ISD::ANY_EXTEND:
4525 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4526 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
4528 // Input is legal? Just do extend all the way to the larger type.
4529 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4532 // Promote the reg if it's smaller.
4533 Result = PromoteOp(Node->getOperand(0));
4534 // The high bits are not guaranteed to be anything. Insert an extend.
4535 if (Node->getOpcode() == ISD::SIGN_EXTEND)
4536 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4537 DAG.getValueType(Node->getOperand(0).getValueType()));
4538 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
4539 Result = DAG.getZeroExtendInReg(Result,
4540 Node->getOperand(0).getValueType());
4544 case ISD::CONVERT_RNDSAT: {
4545 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
4546 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
4547 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
4548 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
4549 "can only promote integers");
4550 Result = DAG.getConvertRndSat(NVT, Node->getOperand(0),
4551 Node->getOperand(1), Node->getOperand(2),
4552 Node->getOperand(3), Node->getOperand(4),
4557 case ISD::BIT_CONVERT:
4558 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
4559 Node->getValueType(0));
4560 Result = PromoteOp(Result);
4563 case ISD::FP_EXTEND:
4564 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
4566 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4567 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
4568 case Promote: assert(0 && "Unreachable with 2 FP types!");
4570 if (Node->getConstantOperandVal(1) == 0) {
4571 // Input is legal? Do an FP_ROUND_INREG.
4572 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
4573 DAG.getValueType(VT));
4575 // Just remove the truncate, it isn't affecting the value.
4576 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0),
4577 Node->getOperand(1));
4582 case ISD::SINT_TO_FP:
4583 case ISD::UINT_TO_FP:
4584 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4586 // No extra round required here.
4587 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4591 Result = PromoteOp(Node->getOperand(0));
4592 if (Node->getOpcode() == ISD::SINT_TO_FP)
4593 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
4595 DAG.getValueType(Node->getOperand(0).getValueType()));
4597 Result = DAG.getZeroExtendInReg(Result,
4598 Node->getOperand(0).getValueType());
4599 // No extra round required here.
4600 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
4603 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
4604 Node->getOperand(0));
4605 // Round if we cannot tolerate excess precision.
4606 if (NoExcessFPPrecision)
4607 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4608 DAG.getValueType(VT));
4613 case ISD::SIGN_EXTEND_INREG:
4614 Result = PromoteOp(Node->getOperand(0));
4615 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4616 Node->getOperand(1));
4618 case ISD::FP_TO_SINT:
4619 case ISD::FP_TO_UINT:
4620 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4623 Tmp1 = Node->getOperand(0);
4626 // The input result is prerounded, so we don't have to do anything
4628 Tmp1 = PromoteOp(Node->getOperand(0));
4631 // If we're promoting a UINT to a larger size, check to see if the new node
4632 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
4633 // we can use that instead. This allows us to generate better code for
4634 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
4635 // legal, such as PowerPC.
4636 if (Node->getOpcode() == ISD::FP_TO_UINT &&
4637 !TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NVT) &&
4638 (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT) ||
4639 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
4640 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
4642 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4648 Tmp1 = PromoteOp(Node->getOperand(0));
4649 assert(Tmp1.getValueType() == NVT);
4650 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4651 // NOTE: we do not have to do any extra rounding here for
4652 // NoExcessFPPrecision, because we know the input will have the appropriate
4653 // precision, and these operations don't modify precision at all.
4668 case ISD::FNEARBYINT:
4669 Tmp1 = PromoteOp(Node->getOperand(0));
4670 assert(Tmp1.getValueType() == NVT);
4671 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4672 if (NoExcessFPPrecision)
4673 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4674 DAG.getValueType(VT));
4679 // Promote f32 pow(i) to f64 pow(i). Note that this could insert a libcall
4680 // directly as well, which may be better.
4681 Tmp1 = PromoteOp(Node->getOperand(0));
4682 Tmp2 = Node->getOperand(1);
4683 if (Node->getOpcode() == ISD::FPOW)
4684 Tmp2 = PromoteOp(Tmp2);
4685 assert(Tmp1.getValueType() == NVT);
4686 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4687 if (NoExcessFPPrecision)
4688 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4689 DAG.getValueType(VT));
4693 case ISD::ATOMIC_CMP_SWAP: {
4694 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4695 Tmp2 = PromoteOp(Node->getOperand(2));
4696 Tmp3 = PromoteOp(Node->getOperand(3));
4697 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getMemoryVT(),
4698 AtomNode->getChain(),
4699 AtomNode->getBasePtr(), Tmp2, Tmp3,
4700 AtomNode->getSrcValue(),
4701 AtomNode->getAlignment());
4702 // Remember that we legalized the chain.
4703 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4706 case ISD::ATOMIC_LOAD_ADD:
4707 case ISD::ATOMIC_LOAD_SUB:
4708 case ISD::ATOMIC_LOAD_AND:
4709 case ISD::ATOMIC_LOAD_OR:
4710 case ISD::ATOMIC_LOAD_XOR:
4711 case ISD::ATOMIC_LOAD_NAND:
4712 case ISD::ATOMIC_LOAD_MIN:
4713 case ISD::ATOMIC_LOAD_MAX:
4714 case ISD::ATOMIC_LOAD_UMIN:
4715 case ISD::ATOMIC_LOAD_UMAX:
4716 case ISD::ATOMIC_SWAP: {
4717 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4718 Tmp2 = PromoteOp(Node->getOperand(2));
4719 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getMemoryVT(),
4720 AtomNode->getChain(),
4721 AtomNode->getBasePtr(), Tmp2,
4722 AtomNode->getSrcValue(),
4723 AtomNode->getAlignment());
4724 // Remember that we legalized the chain.
4725 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4735 // The input may have strange things in the top bits of the registers, but
4736 // these operations don't care. They may have weird bits going out, but
4737 // that too is okay if they are integer operations.
4738 Tmp1 = PromoteOp(Node->getOperand(0));
4739 Tmp2 = PromoteOp(Node->getOperand(1));
4740 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4741 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4746 Tmp1 = PromoteOp(Node->getOperand(0));
4747 Tmp2 = PromoteOp(Node->getOperand(1));
4748 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4749 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4751 // Floating point operations will give excess precision that we may not be
4752 // able to tolerate. If we DO allow excess precision, just leave it,
4753 // otherwise excise it.
4754 // FIXME: Why would we need to round FP ops more than integer ones?
4755 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
4756 if (NoExcessFPPrecision)
4757 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4758 DAG.getValueType(VT));
4763 // These operators require that their input be sign extended.
4764 Tmp1 = PromoteOp(Node->getOperand(0));
4765 Tmp2 = PromoteOp(Node->getOperand(1));
4766 if (NVT.isInteger()) {
4767 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4768 DAG.getValueType(VT));
4769 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4770 DAG.getValueType(VT));
4772 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4774 // Perform FP_ROUND: this is probably overly pessimistic.
4775 if (NVT.isFloatingPoint() && NoExcessFPPrecision)
4776 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4777 DAG.getValueType(VT));
4781 case ISD::FCOPYSIGN:
4782 // These operators require that their input be fp extended.
4783 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4784 case Expand: assert(0 && "not implemented");
4785 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break;
4786 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break;
4788 switch (getTypeAction(Node->getOperand(1).getValueType())) {
4789 case Expand: assert(0 && "not implemented");
4790 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
4791 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
4793 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4795 // Perform FP_ROUND: this is probably overly pessimistic.
4796 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
4797 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4798 DAG.getValueType(VT));
4803 // These operators require that their input be zero extended.
4804 Tmp1 = PromoteOp(Node->getOperand(0));
4805 Tmp2 = PromoteOp(Node->getOperand(1));
4806 assert(NVT.isInteger() && "Operators don't apply to FP!");
4807 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4808 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4809 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4813 Tmp1 = PromoteOp(Node->getOperand(0));
4814 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
4817 // The input value must be properly sign extended.
4818 Tmp1 = PromoteOp(Node->getOperand(0));
4819 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4820 DAG.getValueType(VT));
4821 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
4824 // The input value must be properly zero extended.
4825 Tmp1 = PromoteOp(Node->getOperand(0));
4826 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4827 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
4831 Tmp1 = Node->getOperand(0); // Get the chain.
4832 Tmp2 = Node->getOperand(1); // Get the pointer.
4833 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
4834 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
4835 Result = TLI.LowerOperation(Tmp3, DAG);
4837 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
4838 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
4839 // Increment the pointer, VAList, to the next vaarg
4840 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
4841 DAG.getConstant(VT.getSizeInBits()/8,
4842 TLI.getPointerTy()));
4843 // Store the incremented VAList to the legalized pointer
4844 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
4845 // Load the actual argument out of the pointer VAList
4846 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
4848 // Remember that we legalized the chain.
4849 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4853 LoadSDNode *LD = cast<LoadSDNode>(Node);
4854 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
4855 ? ISD::EXTLOAD : LD->getExtensionType();
4856 Result = DAG.getExtLoad(ExtType, NVT,
4857 LD->getChain(), LD->getBasePtr(),
4858 LD->getSrcValue(), LD->getSrcValueOffset(),
4861 LD->getAlignment());
4862 // Remember that we legalized the chain.
4863 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4867 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
4868 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
4870 MVT VT2 = Tmp2.getValueType();
4871 assert(VT2 == Tmp3.getValueType()
4872 && "PromoteOp SELECT: Operands 2 and 3 ValueTypes don't match");
4873 // Ensure that the resulting node is at least the same size as the operands'
4874 // value types, because we cannot assume that TLI.getSetCCValueType() is
4876 Result = DAG.getNode(ISD::SELECT, VT2, Node->getOperand(0), Tmp2, Tmp3);
4879 case ISD::SELECT_CC:
4880 Tmp2 = PromoteOp(Node->getOperand(2)); // True
4881 Tmp3 = PromoteOp(Node->getOperand(3)); // False
4882 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4883 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
4886 Tmp1 = Node->getOperand(0);
4887 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
4888 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
4889 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
4890 DAG.getConstant(NVT.getSizeInBits() -
4892 TLI.getShiftAmountTy()));
4897 // Zero extend the argument
4898 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4899 // Perform the larger operation, then subtract if needed.
4900 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4901 switch(Node->getOpcode()) {
4906 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
4907 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1.getValueType()), Tmp1,
4908 DAG.getConstant(NVT.getSizeInBits(), NVT),
4910 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
4911 DAG.getConstant(VT.getSizeInBits(), NVT), Tmp1);
4914 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4915 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
4916 DAG.getConstant(NVT.getSizeInBits() -
4917 VT.getSizeInBits(), NVT));
4921 case ISD::EXTRACT_SUBVECTOR:
4922 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
4924 case ISD::EXTRACT_VECTOR_ELT:
4925 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
4929 assert(Result.getNode() && "Didn't set a result!");
4931 // Make sure the result is itself legal.
4932 Result = LegalizeOp(Result);
4934 // Remember that we promoted this!
4935 AddPromotedOperand(Op, Result);
4939 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
4940 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
4941 /// based on the vector type. The return type of this matches the element type
4942 /// of the vector, which may not be legal for the target.
4943 SDValue SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDValue Op) {
4944 // We know that operand #0 is the Vec vector. If the index is a constant
4945 // or if the invec is a supported hardware type, we can use it. Otherwise,
4946 // lower to a store then an indexed load.
4947 SDValue Vec = Op.getOperand(0);
4948 SDValue Idx = Op.getOperand(1);
4950 MVT TVT = Vec.getValueType();
4951 unsigned NumElems = TVT.getVectorNumElements();
4953 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
4954 default: assert(0 && "This action is not supported yet!");
4955 case TargetLowering::Custom: {
4956 Vec = LegalizeOp(Vec);
4957 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4958 SDValue Tmp3 = TLI.LowerOperation(Op, DAG);
4963 case TargetLowering::Legal:
4964 if (isTypeLegal(TVT)) {
4965 Vec = LegalizeOp(Vec);
4966 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4970 case TargetLowering::Promote:
4971 assert(TVT.isVector() && "not vector type");
4972 // fall thru to expand since vectors are by default are promote
4973 case TargetLowering::Expand:
4977 if (NumElems == 1) {
4978 // This must be an access of the only element. Return it.
4979 Op = ScalarizeVectorOp(Vec);
4980 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
4981 unsigned NumLoElts = 1 << Log2_32(NumElems-1);
4982 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4984 SplitVectorOp(Vec, Lo, Hi);
4985 if (CIdx->getZExtValue() < NumLoElts) {
4989 Idx = DAG.getConstant(CIdx->getZExtValue() - NumLoElts,
4990 Idx.getValueType());
4993 // It's now an extract from the appropriate high or low part. Recurse.
4994 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4995 Op = ExpandEXTRACT_VECTOR_ELT(Op);
4997 // Store the value to a temporary stack slot, then LOAD the scalar
4998 // element back out.
4999 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
5000 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
5002 // Add the offset to the index.
5003 unsigned EltSize = Op.getValueType().getSizeInBits()/8;
5004 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
5005 DAG.getConstant(EltSize, Idx.getValueType()));
5007 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
5008 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx);
5010 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
5012 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
5014 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
5019 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
5020 /// we assume the operation can be split if it is not already legal.
5021 SDValue SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDValue Op) {
5022 // We know that operand #0 is the Vec vector. For now we assume the index
5023 // is a constant and that the extracted result is a supported hardware type.
5024 SDValue Vec = Op.getOperand(0);
5025 SDValue Idx = LegalizeOp(Op.getOperand(1));
5027 unsigned NumElems = Vec.getValueType().getVectorNumElements();
5029 if (NumElems == Op.getValueType().getVectorNumElements()) {
5030 // This must be an access of the desired vector length. Return it.
5034 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
5036 SplitVectorOp(Vec, Lo, Hi);
5037 if (CIdx->getZExtValue() < NumElems/2) {
5041 Idx = DAG.getConstant(CIdx->getZExtValue() - NumElems/2,
5042 Idx.getValueType());
5045 // It's now an extract from the appropriate high or low part. Recurse.
5046 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
5047 return ExpandEXTRACT_SUBVECTOR(Op);
5050 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
5051 /// with condition CC on the current target. This usually involves legalizing
5052 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
5053 /// there may be no choice but to create a new SetCC node to represent the
5054 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
5055 /// LHS, and the SDValue returned in RHS has a nil SDNode value.
5056 void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS,
5059 SDValue Tmp1, Tmp2, Tmp3, Result;
5061 switch (getTypeAction(LHS.getValueType())) {
5063 Tmp1 = LegalizeOp(LHS); // LHS
5064 Tmp2 = LegalizeOp(RHS); // RHS
5067 Tmp1 = PromoteOp(LHS); // LHS
5068 Tmp2 = PromoteOp(RHS); // RHS
5070 // If this is an FP compare, the operands have already been extended.
5071 if (LHS.getValueType().isInteger()) {
5072 MVT VT = LHS.getValueType();
5073 MVT NVT = TLI.getTypeToTransformTo(VT);
5075 // Otherwise, we have to insert explicit sign or zero extends. Note
5076 // that we could insert sign extends for ALL conditions, but zero extend
5077 // is cheaper on many machines (an AND instead of two shifts), so prefer
5079 switch (cast<CondCodeSDNode>(CC)->get()) {
5080 default: assert(0 && "Unknown integer comparison!");
5087 // ALL of these operations will work if we either sign or zero extend
5088 // the operands (including the unsigned comparisons!). Zero extend is
5089 // usually a simpler/cheaper operation, so prefer it.
5090 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
5091 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
5097 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
5098 DAG.getValueType(VT));
5099 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
5100 DAG.getValueType(VT));
5101 Tmp1 = LegalizeOp(Tmp1); // Relegalize new nodes.
5102 Tmp2 = LegalizeOp(Tmp2); // Relegalize new nodes.
5108 MVT VT = LHS.getValueType();
5109 if (VT == MVT::f32 || VT == MVT::f64) {
5110 // Expand into one or more soft-fp libcall(s).
5111 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
5112 switch (cast<CondCodeSDNode>(CC)->get()) {
5115 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
5119 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
5123 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
5127 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
5131 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
5135 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
5138 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
5141 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
5144 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
5145 switch (cast<CondCodeSDNode>(CC)->get()) {
5147 // SETONE = SETOLT | SETOGT
5148 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
5151 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
5154 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
5157 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
5160 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
5163 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
5165 default: assert(0 && "Unsupported FP setcc!");
5170 SDValue Ops[2] = { LHS, RHS };
5171 Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2).getNode(),
5172 false /*sign irrelevant*/, Dummy);
5173 Tmp2 = DAG.getConstant(0, MVT::i32);
5174 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
5175 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
5176 Tmp1 = DAG.getNode(ISD::SETCC,
5177 TLI.getSetCCResultType(Tmp1.getValueType()),
5179 LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2).getNode(),
5180 false /*sign irrelevant*/, Dummy);
5181 Tmp2 = DAG.getNode(ISD::SETCC,
5182 TLI.getSetCCResultType(LHS.getValueType()), LHS,
5183 Tmp2, DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
5184 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
5187 LHS = LegalizeOp(Tmp1);
5192 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
5193 ExpandOp(LHS, LHSLo, LHSHi);
5194 ExpandOp(RHS, RHSLo, RHSHi);
5195 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
5197 if (VT==MVT::ppcf128) {
5198 // FIXME: This generated code sucks. We want to generate
5199 // FCMPU crN, hi1, hi2
5201 // FCMPU crN, lo1, lo2
5202 // The following can be improved, but not that much.
5203 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
5204 LHSHi, RHSHi, ISD::SETOEQ);
5205 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
5206 LHSLo, RHSLo, CCCode);
5207 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
5208 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
5209 LHSHi, RHSHi, ISD::SETUNE);
5210 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
5211 LHSHi, RHSHi, CCCode);
5212 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
5213 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
5222 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
5223 if (RHSCST->isAllOnesValue()) {
5224 // Comparison to -1.
5225 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
5230 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
5231 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
5232 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
5233 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
5236 // If this is a comparison of the sign bit, just look at the top part.
5238 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
5239 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
5240 CST->isNullValue()) || // X < 0
5241 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
5242 CST->isAllOnesValue())) { // X > -1
5248 // FIXME: This generated code sucks.
5249 ISD::CondCode LowCC;
5251 default: assert(0 && "Unknown integer setcc!");
5253 case ISD::SETULT: LowCC = ISD::SETULT; break;
5255 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
5257 case ISD::SETULE: LowCC = ISD::SETULE; break;
5259 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
5262 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
5263 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
5264 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
5266 // NOTE: on targets without efficient SELECT of bools, we can always use
5267 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
5268 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
5269 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
5270 LHSLo, RHSLo, LowCC, false, DagCombineInfo);
5271 if (!Tmp1.getNode())
5272 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
5273 LHSLo, RHSLo, LowCC);
5274 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
5275 LHSHi, RHSHi, CCCode, false, DagCombineInfo);
5276 if (!Tmp2.getNode())
5277 Tmp2 = DAG.getNode(ISD::SETCC,
5278 TLI.getSetCCResultType(LHSHi.getValueType()),
5281 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
5282 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
5283 if ((Tmp1C && Tmp1C->isNullValue()) ||
5284 (Tmp2C && Tmp2C->isNullValue() &&
5285 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
5286 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
5287 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
5288 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
5289 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
5290 // low part is known false, returns high part.
5291 // For LE / GE, if high part is known false, ignore the low part.
5292 // For LT / GT, if high part is known true, ignore the low part.
5296 Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
5297 LHSHi, RHSHi, ISD::SETEQ, false,
5299 if (!Result.getNode())
5300 Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
5301 LHSHi, RHSHi, ISD::SETEQ);
5302 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
5303 Result, Tmp1, Tmp2));
5314 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
5315 /// condition code CC on the current target. This routine assumes LHS and rHS
5316 /// have already been legalized by LegalizeSetCCOperands. It expands SETCC with
5317 /// illegal condition code into AND / OR of multiple SETCC values.
5318 void SelectionDAGLegalize::LegalizeSetCCCondCode(MVT VT,
5319 SDValue &LHS, SDValue &RHS,
5321 MVT OpVT = LHS.getValueType();
5322 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
5323 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
5324 default: assert(0 && "Unknown condition code action!");
5325 case TargetLowering::Legal:
5328 case TargetLowering::Expand: {
5329 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
5332 default: assert(0 && "Don't know how to expand this condition!"); abort();
5333 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break;
5334 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break;
5335 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5336 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break;
5337 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5338 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5339 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5340 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5341 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5342 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5343 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5344 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5345 // FIXME: Implement more expansions.
5348 SDValue SetCC1 = DAG.getSetCC(VT, LHS, RHS, CC1);
5349 SDValue SetCC2 = DAG.getSetCC(VT, LHS, RHS, CC2);
5350 LHS = DAG.getNode(Opc, VT, SetCC1, SetCC2);
5358 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
5359 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
5360 /// a load from the stack slot to DestVT, extending it if needed.
5361 /// The resultant code need not be legal.
5362 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
5365 // Create the stack frame object.
5366 unsigned SrcAlign = TLI.getTargetData()->getPrefTypeAlignment(
5367 SrcOp.getValueType().getTypeForMVT());
5368 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
5370 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
5371 int SPFI = StackPtrFI->getIndex();
5372 const Value *SV = PseudoSourceValue::getFixedStack(SPFI);
5374 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
5375 unsigned SlotSize = SlotVT.getSizeInBits();
5376 unsigned DestSize = DestVT.getSizeInBits();
5377 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(
5378 DestVT.getTypeForMVT());
5380 // Emit a store to the stack slot. Use a truncstore if the input value is
5381 // later than DestVT.
5384 if (SrcSize > SlotSize)
5385 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr,
5386 SV, 0, SlotVT, false, SrcAlign);
5388 assert(SrcSize == SlotSize && "Invalid store");
5389 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr,
5390 SV, 0, false, SrcAlign);
5393 // Result is a load from the stack slot.
5394 if (SlotSize == DestSize)
5395 return DAG.getLoad(DestVT, Store, FIPtr, SV, 0, false, DestAlign);
5397 assert(SlotSize < DestSize && "Unknown extension!");
5398 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, SV, 0, SlotVT,
5402 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
5403 // Create a vector sized/aligned stack slot, store the value to element #0,
5404 // then load the whole vector back out.
5405 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
5407 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
5408 int SPFI = StackPtrFI->getIndex();
5410 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
5411 PseudoSourceValue::getFixedStack(SPFI), 0);
5412 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,
5413 PseudoSourceValue::getFixedStack(SPFI), 0);
5417 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
5418 /// support the operation, but do support the resultant vector type.
5419 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
5421 // If the only non-undef value is the low element, turn this into a
5422 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
5423 unsigned NumElems = Node->getNumOperands();
5424 bool isOnlyLowElement = true;
5425 SDValue SplatValue = Node->getOperand(0);
5427 // FIXME: it would be far nicer to change this into map<SDValue,uint64_t>
5428 // and use a bitmask instead of a list of elements.
5429 std::map<SDValue, std::vector<unsigned> > Values;
5430 Values[SplatValue].push_back(0);
5431 bool isConstant = true;
5432 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
5433 SplatValue.getOpcode() != ISD::UNDEF)
5436 for (unsigned i = 1; i < NumElems; ++i) {
5437 SDValue V = Node->getOperand(i);
5438 Values[V].push_back(i);
5439 if (V.getOpcode() != ISD::UNDEF)
5440 isOnlyLowElement = false;
5441 if (SplatValue != V)
5442 SplatValue = SDValue(0,0);
5444 // If this isn't a constant element or an undef, we can't use a constant
5446 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
5447 V.getOpcode() != ISD::UNDEF)
5451 if (isOnlyLowElement) {
5452 // If the low element is an undef too, then this whole things is an undef.
5453 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
5454 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
5455 // Otherwise, turn this into a scalar_to_vector node.
5456 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
5457 Node->getOperand(0));
5460 // If all elements are constants, create a load from the constant pool.
5462 MVT VT = Node->getValueType(0);
5463 std::vector<Constant*> CV;
5464 for (unsigned i = 0, e = NumElems; i != e; ++i) {
5465 if (ConstantFPSDNode *V =
5466 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
5467 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
5468 } else if (ConstantSDNode *V =
5469 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
5470 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
5472 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
5474 Node->getOperand(0).getValueType().getTypeForMVT();
5475 CV.push_back(UndefValue::get(OpNTy));
5478 Constant *CP = ConstantVector::get(CV);
5479 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
5480 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5481 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
5482 PseudoSourceValue::getConstantPool(), 0,
5486 if (SplatValue.getNode()) { // Splat of one value?
5487 // Build the shuffle constant vector: <0, 0, 0, 0>
5488 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
5489 SDValue Zero = DAG.getConstant(0, MaskVT.getVectorElementType());
5490 std::vector<SDValue> ZeroVec(NumElems, Zero);
5491 SDValue SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
5492 &ZeroVec[0], ZeroVec.size());
5494 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
5495 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
5496 // Get the splatted value into the low element of a vector register.
5498 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
5500 // Return shuffle(LowValVec, undef, <0,0,0,0>)
5501 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
5502 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
5507 // If there are only two unique elements, we may be able to turn this into a
5509 if (Values.size() == 2) {
5510 // Get the two values in deterministic order.
5511 SDValue Val1 = Node->getOperand(1);
5513 std::map<SDValue, std::vector<unsigned> >::iterator MI = Values.begin();
5514 if (MI->first != Val1)
5517 Val2 = (++MI)->first;
5519 // If Val1 is an undef, make sure end ends up as Val2, to ensure that our
5520 // vector shuffle has the undef vector on the RHS.
5521 if (Val1.getOpcode() == ISD::UNDEF)
5522 std::swap(Val1, Val2);
5524 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
5525 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
5526 MVT MaskEltVT = MaskVT.getVectorElementType();
5527 std::vector<SDValue> MaskVec(NumElems);
5529 // Set elements of the shuffle mask for Val1.
5530 std::vector<unsigned> &Val1Elts = Values[Val1];
5531 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i)
5532 MaskVec[Val1Elts[i]] = DAG.getConstant(0, MaskEltVT);
5534 // Set elements of the shuffle mask for Val2.
5535 std::vector<unsigned> &Val2Elts = Values[Val2];
5536 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i)
5537 if (Val2.getOpcode() != ISD::UNDEF)
5538 MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT);
5540 MaskVec[Val2Elts[i]] = DAG.getNode(ISD::UNDEF, MaskEltVT);
5542 SDValue ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
5543 &MaskVec[0], MaskVec.size());
5545 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it.
5546 if (TLI.isOperationLegalOrCustom(ISD::SCALAR_TO_VECTOR,
5547 Node->getValueType(0)) &&
5548 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
5549 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val1);
5550 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val2);
5551 SDValue Ops[] = { Val1, Val2, ShuffleMask };
5553 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
5554 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops, 3);
5558 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
5559 // aligned object on the stack, store each element into it, then load
5560 // the result as a vector.
5561 MVT VT = Node->getValueType(0);
5562 // Create the stack frame object.
5563 SDValue FIPtr = DAG.CreateStackTemporary(VT);
5564 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
5565 const Value *SV = PseudoSourceValue::getFixedStack(FI);
5567 // Emit a store of each element to the stack slot.
5568 SmallVector<SDValue, 8> Stores;
5569 unsigned TypeByteSize = Node->getOperand(0).getValueType().getSizeInBits()/8;
5570 // Store (in the right endianness) the elements to memory.
5571 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5572 // Ignore undef elements.
5573 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
5575 unsigned Offset = TypeByteSize*i;
5577 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
5578 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
5580 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
5585 if (!Stores.empty()) // Not all undef elements?
5586 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
5587 &Stores[0], Stores.size());
5589 StoreChain = DAG.getEntryNode();
5591 // Result is a load from the stack slot.
5592 return DAG.getLoad(VT, StoreChain, FIPtr, SV, 0);
5595 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
5596 SDValue Op, SDValue Amt,
5597 SDValue &Lo, SDValue &Hi) {
5598 // Expand the subcomponents.
5600 ExpandOp(Op, LHSL, LHSH);
5602 SDValue Ops[] = { LHSL, LHSH, Amt };
5603 MVT VT = LHSL.getValueType();
5604 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
5605 Hi = Lo.getValue(1);
5609 /// ExpandShift - Try to find a clever way to expand this shift operation out to
5610 /// smaller elements. If we can't find a way that is more efficient than a
5611 /// libcall on this target, return false. Otherwise, return true with the
5612 /// low-parts expanded into Lo and Hi.
5613 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op,SDValue Amt,
5614 SDValue &Lo, SDValue &Hi) {
5615 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
5616 "This is not a shift!");
5618 MVT NVT = TLI.getTypeToTransformTo(Op.getValueType());
5619 SDValue ShAmt = LegalizeOp(Amt);
5620 MVT ShTy = ShAmt.getValueType();
5621 unsigned ShBits = ShTy.getSizeInBits();
5622 unsigned VTBits = Op.getValueType().getSizeInBits();
5623 unsigned NVTBits = NVT.getSizeInBits();
5625 // Handle the case when Amt is an immediate.
5626 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.getNode())) {
5627 unsigned Cst = CN->getZExtValue();
5628 // Expand the incoming operand to be shifted, so that we have its parts
5630 ExpandOp(Op, InL, InH);
5634 Lo = DAG.getConstant(0, NVT);
5635 Hi = DAG.getConstant(0, NVT);
5636 } else if (Cst > NVTBits) {
5637 Lo = DAG.getConstant(0, NVT);
5638 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
5639 } else if (Cst == NVTBits) {
5640 Lo = DAG.getConstant(0, NVT);
5643 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
5644 Hi = DAG.getNode(ISD::OR, NVT,
5645 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
5646 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
5651 Lo = DAG.getConstant(0, NVT);
5652 Hi = DAG.getConstant(0, NVT);
5653 } else if (Cst > NVTBits) {
5654 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
5655 Hi = DAG.getConstant(0, NVT);
5656 } else if (Cst == NVTBits) {
5658 Hi = DAG.getConstant(0, NVT);
5660 Lo = DAG.getNode(ISD::OR, NVT,
5661 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5662 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5663 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
5668 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
5669 DAG.getConstant(NVTBits-1, ShTy));
5670 } else if (Cst > NVTBits) {
5671 Lo = DAG.getNode(ISD::SRA, NVT, InH,
5672 DAG.getConstant(Cst-NVTBits, ShTy));
5673 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5674 DAG.getConstant(NVTBits-1, ShTy));
5675 } else if (Cst == NVTBits) {
5677 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5678 DAG.getConstant(NVTBits-1, ShTy));
5680 Lo = DAG.getNode(ISD::OR, NVT,
5681 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5682 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5683 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
5689 // Okay, the shift amount isn't constant. However, if we can tell that it is
5690 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
5691 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
5692 APInt KnownZero, KnownOne;
5693 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
5695 // If we know that if any of the high bits of the shift amount are one, then
5696 // we can do this as a couple of simple shifts.
5697 if (KnownOne.intersects(Mask)) {
5698 // Mask out the high bit, which we know is set.
5699 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
5700 DAG.getConstant(~Mask, Amt.getValueType()));
5702 // Expand the incoming operand to be shifted, so that we have its parts
5704 ExpandOp(Op, InL, InH);
5707 Lo = DAG.getConstant(0, NVT); // Low part is zero.
5708 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
5711 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
5712 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
5715 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
5716 DAG.getConstant(NVTBits-1, Amt.getValueType()));
5717 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
5722 // If we know that the high bits of the shift amount are all zero, then we can
5723 // do this as a couple of simple shifts.
5724 if ((KnownZero & Mask) == Mask) {
5726 SDValue Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
5727 DAG.getConstant(NVTBits, Amt.getValueType()),
5730 // Expand the incoming operand to be shifted, so that we have its parts
5732 ExpandOp(Op, InL, InH);
5735 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
5736 Hi = DAG.getNode(ISD::OR, NVT,
5737 DAG.getNode(ISD::SHL, NVT, InH, Amt),
5738 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
5741 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
5742 Lo = DAG.getNode(ISD::OR, NVT,
5743 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5744 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5747 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
5748 Lo = DAG.getNode(ISD::OR, NVT,
5749 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5750 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5759 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
5760 // does not fit into a register, return the lo part and set the hi part to the
5761 // by-reg argument. If it does fit into a single register, return the result
5762 // and leave the Hi part unset.
5763 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
5764 bool isSigned, SDValue &Hi) {
5765 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
5766 // The input chain to this libcall is the entry node of the function.
5767 // Legalizing the call will automatically add the previous call to the
5769 SDValue InChain = DAG.getEntryNode();
5771 TargetLowering::ArgListTy Args;
5772 TargetLowering::ArgListEntry Entry;
5773 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5774 MVT ArgVT = Node->getOperand(i).getValueType();
5775 const Type *ArgTy = ArgVT.getTypeForMVT();
5776 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
5777 Entry.isSExt = isSigned;
5778 Entry.isZExt = !isSigned;
5779 Args.push_back(Entry);
5781 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
5782 TLI.getPointerTy());
5784 // Splice the libcall in wherever FindInputOutputChains tells us to.
5785 const Type *RetTy = Node->getValueType(0).getTypeForMVT();
5786 std::pair<SDValue,SDValue> CallInfo =
5787 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
5788 CallingConv::C, false, Callee, Args, DAG,
5789 Node->getDebugLoc());
5791 // Legalize the call sequence, starting with the chain. This will advance
5792 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
5793 // was added by LowerCallTo (guaranteeing proper serialization of calls).
5794 LegalizeOp(CallInfo.second);
5796 switch (getTypeAction(CallInfo.first.getValueType())) {
5797 default: assert(0 && "Unknown thing");
5799 Result = CallInfo.first;
5802 ExpandOp(CallInfo.first, Result, Hi);
5808 /// LegalizeINT_TO_FP - Legalize a [US]INT_TO_FP operation.
5810 SDValue SelectionDAGLegalize::
5811 LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op) {
5812 bool isCustom = false;
5814 switch (getTypeAction(Op.getValueType())) {
5816 switch (TLI.getOperationAction(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5817 Op.getValueType())) {
5818 default: assert(0 && "Unknown operation action!");
5819 case TargetLowering::Custom:
5822 case TargetLowering::Legal:
5823 Tmp1 = LegalizeOp(Op);
5824 if (Result.getNode())
5825 Result = DAG.UpdateNodeOperands(Result, Tmp1);
5827 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5830 Tmp1 = TLI.LowerOperation(Result, DAG);
5831 if (Tmp1.getNode()) Result = Tmp1;
5834 case TargetLowering::Expand:
5835 Result = ExpandLegalINT_TO_FP(isSigned, LegalizeOp(Op), DestTy);
5837 case TargetLowering::Promote:
5838 Result = PromoteLegalINT_TO_FP(LegalizeOp(Op), DestTy, isSigned);
5843 Result = ExpandIntToFP(isSigned, DestTy, Op);
5846 Tmp1 = PromoteOp(Op);
5848 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
5849 Tmp1, DAG.getValueType(Op.getValueType()));
5851 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
5854 if (Result.getNode())
5855 Result = DAG.UpdateNodeOperands(Result, Tmp1);
5857 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5859 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
5865 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
5867 SDValue SelectionDAGLegalize::
5868 ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source) {
5869 MVT SourceVT = Source.getValueType();
5870 bool ExpandSource = getTypeAction(SourceVT) == Expand;
5872 // Expand unsupported int-to-fp vector casts by unrolling them.
5873 if (DestTy.isVector()) {
5875 return LegalizeOp(UnrollVectorOp(Source));
5876 MVT DestEltTy = DestTy.getVectorElementType();
5877 if (DestTy.getVectorNumElements() == 1) {
5878 SDValue Scalar = ScalarizeVectorOp(Source);
5879 SDValue Result = LegalizeINT_TO_FP(SDValue(), isSigned,
5881 return DAG.getNode(ISD::BUILD_VECTOR, DestTy, Result);
5884 SplitVectorOp(Source, Lo, Hi);
5885 MVT SplitDestTy = MVT::getVectorVT(DestEltTy,
5886 DestTy.getVectorNumElements() / 2);
5887 SDValue LoResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, Lo);
5888 SDValue HiResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, Hi);
5889 return LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, DestTy, LoResult,
5893 // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc.
5894 if (!isSigned && SourceVT != MVT::i32) {
5895 // The integer value loaded will be incorrectly if the 'sign bit' of the
5896 // incoming integer is set. To handle this, we dynamically test to see if
5897 // it is set, and, if so, add a fudge factor.
5901 ExpandOp(Source, Lo, Hi);
5902 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi);
5904 // The comparison for the sign bit will use the entire operand.
5908 // Check to see if the target has a custom way to lower this. If so, use
5909 // it. (Note we've already expanded the operand in this case.)
5910 switch (TLI.getOperationAction(ISD::UINT_TO_FP, SourceVT)) {
5911 default: assert(0 && "This action not implemented for this operation!");
5912 case TargetLowering::Legal:
5913 case TargetLowering::Expand:
5914 break; // This case is handled below.
5915 case TargetLowering::Custom: {
5916 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::UINT_TO_FP, DestTy,
5919 return LegalizeOp(NV);
5920 break; // The target decided this was legal after all
5924 // If this is unsigned, and not supported, first perform the conversion to
5925 // signed, then adjust the result if the sign bit is set.
5926 SDValue SignedConv = ExpandIntToFP(true, DestTy, Source);
5928 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi.getValueType()),
5929 Hi, DAG.getConstant(0, Hi.getValueType()),
5931 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5932 SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5933 SignSet, Four, Zero);
5934 uint64_t FF = 0x5f800000ULL;
5935 if (TLI.isLittleEndian()) FF <<= 32;
5936 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5938 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5939 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5940 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5941 Alignment = std::min(Alignment, 4u);
5943 if (DestTy == MVT::f32)
5944 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5945 PseudoSourceValue::getConstantPool(), 0,
5947 else if (DestTy.bitsGT(MVT::f32))
5948 // FIXME: Avoid the extend by construction the right constantpool?
5949 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
5951 PseudoSourceValue::getConstantPool(), 0,
5952 MVT::f32, false, Alignment);
5954 assert(0 && "Unexpected conversion");
5956 MVT SCVT = SignedConv.getValueType();
5957 if (SCVT != DestTy) {
5958 // Destination type needs to be expanded as well. The FADD now we are
5959 // constructing will be expanded into a libcall.
5960 if (SCVT.getSizeInBits() != DestTy.getSizeInBits()) {
5961 assert(SCVT.getSizeInBits() * 2 == DestTy.getSizeInBits());
5962 SignedConv = DAG.getNode(ISD::BUILD_PAIR, DestTy,
5963 SignedConv, SignedConv.getValue(1));
5965 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
5967 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
5970 // Check to see if the target has a custom way to lower this. If so, use it.
5971 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) {
5972 default: assert(0 && "This action not implemented for this operation!");
5973 case TargetLowering::Legal:
5974 case TargetLowering::Expand:
5975 break; // This case is handled below.
5976 case TargetLowering::Custom: {
5977 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
5980 return LegalizeOp(NV);
5981 break; // The target decided this was legal after all
5985 // Expand the source, then glue it back together for the call. We must expand
5986 // the source in case it is shared (this pass of legalize must traverse it).
5988 SDValue SrcLo, SrcHi;
5989 ExpandOp(Source, SrcLo, SrcHi);
5990 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, SrcLo, SrcHi);
5993 RTLIB::Libcall LC = isSigned ?
5994 RTLIB::getSINTTOFP(SourceVT, DestTy) :
5995 RTLIB::getUINTTOFP(SourceVT, DestTy);
5996 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unknown int value type");
5998 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
6000 SDValue Result = ExpandLibCall(LC, Source.getNode(), isSigned, HiPart);
6001 if (Result.getValueType() != DestTy && HiPart.getNode())
6002 Result = DAG.getNode(ISD::BUILD_PAIR, DestTy, Result, HiPart);
6006 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
6007 /// INT_TO_FP operation of the specified operand when the target requests that
6008 /// we expand it. At this point, we know that the result and operand types are
6009 /// legal for the target.
6010 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
6013 if (Op0.getValueType() == MVT::i32) {
6014 // simple 32-bit [signed|unsigned] integer to float/double expansion
6016 // Get the stack frame index of a 8 byte buffer.
6017 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
6019 // word offset constant for Hi/Lo address computation
6020 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
6021 // set up Hi and Lo (into buffer) address based on endian
6022 SDValue Hi = StackSlot;
6023 SDValue Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
6024 if (TLI.isLittleEndian())
6027 // if signed map to unsigned space
6030 // constant used to invert sign bit (signed to unsigned mapping)
6031 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
6032 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
6036 // store the lo of the constructed double - based on integer input
6037 SDValue Store1 = DAG.getStore(DAG.getEntryNode(),
6038 Op0Mapped, Lo, NULL, 0);
6039 // initial hi portion of constructed double
6040 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
6041 // store the hi of the constructed double - biased exponent
6042 SDValue Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
6043 // load the constructed double
6044 SDValue Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
6045 // FP constant to bias correct the final result
6046 SDValue Bias = DAG.getConstantFP(isSigned ?
6047 BitsToDouble(0x4330000080000000ULL)
6048 : BitsToDouble(0x4330000000000000ULL),
6050 // subtract the bias
6051 SDValue Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
6054 // handle final rounding
6055 if (DestVT == MVT::f64) {
6058 } else if (DestVT.bitsLT(MVT::f64)) {
6059 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub,
6060 DAG.getIntPtrConstant(0));
6061 } else if (DestVT.bitsGT(MVT::f64)) {
6062 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
6066 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
6067 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
6069 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Op0.getValueType()),
6070 Op0, DAG.getConstant(0, Op0.getValueType()),
6072 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
6073 SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
6074 SignSet, Four, Zero);
6076 // If the sign bit of the integer is set, the large number will be treated
6077 // as a negative number. To counteract this, the dynamic code adds an
6078 // offset depending on the data type.
6080 switch (Op0.getValueType().getSimpleVT()) {
6081 default: assert(0 && "Unsupported integer type!");
6082 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
6083 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
6084 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
6085 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
6087 if (TLI.isLittleEndian()) FF <<= 32;
6088 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
6090 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
6091 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
6092 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
6093 Alignment = std::min(Alignment, 4u);
6095 if (DestVT == MVT::f32)
6096 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
6097 PseudoSourceValue::getConstantPool(), 0,
6101 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT,
6102 DAG.getEntryNode(), CPIdx,
6103 PseudoSourceValue::getConstantPool(), 0,
6104 MVT::f32, false, Alignment));
6107 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
6110 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
6111 /// *INT_TO_FP operation of the specified operand when the target requests that
6112 /// we promote it. At this point, we know that the result and operand types are
6113 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
6114 /// operation that takes a larger input.
6115 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
6118 // First step, figure out the appropriate *INT_TO_FP operation to use.
6119 MVT NewInTy = LegalOp.getValueType();
6121 unsigned OpToUse = 0;
6123 // Scan for the appropriate larger type to use.
6125 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
6126 assert(NewInTy.isInteger() && "Ran out of possibilities!");
6128 // If the target supports SINT_TO_FP of this type, use it.
6129 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
6131 case TargetLowering::Legal:
6132 if (!TLI.isTypeLegal(NewInTy))
6133 break; // Can't use this datatype.
6135 case TargetLowering::Custom:
6136 OpToUse = ISD::SINT_TO_FP;
6140 if (isSigned) continue;
6142 // If the target supports UINT_TO_FP of this type, use it.
6143 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
6145 case TargetLowering::Legal:
6146 if (!TLI.isTypeLegal(NewInTy))
6147 break; // Can't use this datatype.
6149 case TargetLowering::Custom:
6150 OpToUse = ISD::UINT_TO_FP;
6155 // Otherwise, try a larger type.
6158 // Okay, we found the operation and type to use. Zero extend our input to the
6159 // desired type then run the operation on it.
6160 return DAG.getNode(OpToUse, DestVT,
6161 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
6165 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
6166 /// FP_TO_*INT operation of the specified operand when the target requests that
6167 /// we promote it. At this point, we know that the result and operand types are
6168 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
6169 /// operation that returns a larger result.
6170 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
6173 // First step, figure out the appropriate FP_TO*INT operation to use.
6174 MVT NewOutTy = DestVT;
6176 unsigned OpToUse = 0;
6178 // Scan for the appropriate larger type to use.
6180 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1);
6181 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
6183 // If the target supports FP_TO_SINT returning this type, use it.
6184 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
6186 case TargetLowering::Legal:
6187 if (!TLI.isTypeLegal(NewOutTy))
6188 break; // Can't use this datatype.
6190 case TargetLowering::Custom:
6191 OpToUse = ISD::FP_TO_SINT;
6196 // If the target supports FP_TO_UINT of this type, use it.
6197 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
6199 case TargetLowering::Legal:
6200 if (!TLI.isTypeLegal(NewOutTy))
6201 break; // Can't use this datatype.
6203 case TargetLowering::Custom:
6204 OpToUse = ISD::FP_TO_UINT;
6209 // Otherwise, try a larger type.
6213 // Okay, we found the operation and type to use.
6214 SDValue Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp);
6216 // If the operation produces an invalid type, it must be custom lowered. Use
6217 // the target lowering hooks to expand it. Just keep the low part of the
6218 // expanded operation, we know that we're truncating anyway.
6219 if (getTypeAction(NewOutTy) == Expand) {
6220 SmallVector<SDValue, 2> Results;
6221 TLI.ReplaceNodeResults(Operation.getNode(), Results, DAG);
6222 assert(Results.size() == 1 && "Incorrect FP_TO_XINT lowering!");
6223 Operation = Results[0];
6226 // Truncate the result of the extended FP_TO_*INT operation to the desired
6228 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation);
6231 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
6233 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op) {
6234 MVT VT = Op.getValueType();
6235 MVT SHVT = TLI.getShiftAmountTy();
6236 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
6237 switch (VT.getSimpleVT()) {
6238 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
6240 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
6241 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
6242 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
6244 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
6245 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
6246 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
6247 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
6248 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
6249 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
6250 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
6251 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
6252 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
6254 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
6255 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
6256 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
6257 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
6258 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
6259 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
6260 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
6261 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
6262 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
6263 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
6264 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
6265 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
6266 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
6267 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
6268 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
6269 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
6270 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
6271 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
6272 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
6273 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
6274 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
6278 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
6280 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op) {
6282 default: assert(0 && "Cannot expand this yet!");
6284 static const uint64_t mask[6] = {
6285 0x5555555555555555ULL, 0x3333333333333333ULL,
6286 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
6287 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
6289 MVT VT = Op.getValueType();
6290 MVT ShVT = TLI.getShiftAmountTy();
6291 unsigned len = VT.getSizeInBits();
6292 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
6293 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
6294 SDValue Tmp2 = DAG.getConstant(VT.getIntegerVTBitMask() & mask[i], VT);
6295 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
6296 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
6297 DAG.getNode(ISD::AND, VT,
6298 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
6303 // for now, we do this:
6304 // x = x | (x >> 1);
6305 // x = x | (x >> 2);
6307 // x = x | (x >>16);
6308 // x = x | (x >>32); // for 64-bit input
6309 // return popcount(~x);
6311 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
6312 MVT VT = Op.getValueType();
6313 MVT ShVT = TLI.getShiftAmountTy();
6314 unsigned len = VT.getSizeInBits();
6315 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
6316 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
6317 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
6319 Op = DAG.getNOT(DebugLoc::getUnknownLoc(), Op, VT);
6320 return DAG.getNode(ISD::CTPOP, VT, Op);
6323 // for now, we use: { return popcount(~x & (x - 1)); }
6324 // unless the target has ctlz but not ctpop, in which case we use:
6325 // { return 32 - nlz(~x & (x-1)); }
6326 // see also http://www.hackersdelight.org/HDcode/ntz.cc
6327 MVT VT = Op.getValueType();
6328 SDValue Tmp3 = DAG.getNode(ISD::AND, VT,
6329 DAG.getNOT(DebugLoc::getUnknownLoc(), Op, VT),
6330 DAG.getNode(ISD::SUB, VT, Op,
6331 DAG.getConstant(1, VT)));
6332 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
6333 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
6334 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
6335 return DAG.getNode(ISD::SUB, VT,
6336 DAG.getConstant(VT.getSizeInBits(), VT),
6337 DAG.getNode(ISD::CTLZ, VT, Tmp3));
6338 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
6343 /// ExpandOp - Expand the specified SDValue into its two component pieces
6344 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
6345 /// LegalizedNodes map is filled in for any results that are not expanded, the
6346 /// ExpandedNodes map is filled in for any results that are expanded, and the
6347 /// Lo/Hi values are returned.
6348 void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
6349 MVT VT = Op.getValueType();
6350 MVT NVT = TLI.getTypeToTransformTo(VT);
6351 SDNode *Node = Op.getNode();
6352 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
6353 assert(((NVT.isInteger() && NVT.bitsLT(VT)) || VT.isFloatingPoint() ||
6354 VT.isVector()) && "Cannot expand to FP value or to larger int value!");
6356 // See if we already expanded it.
6357 DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator I
6358 = ExpandedNodes.find(Op);
6359 if (I != ExpandedNodes.end()) {
6360 Lo = I->second.first;
6361 Hi = I->second.second;
6365 switch (Node->getOpcode()) {
6366 case ISD::CopyFromReg:
6367 assert(0 && "CopyFromReg must be legal!");
6368 case ISD::FP_ROUND_INREG:
6369 if (VT == MVT::ppcf128 &&
6370 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
6371 TargetLowering::Custom) {
6372 SDValue SrcLo, SrcHi, Src;
6373 ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
6374 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi);
6375 SDValue Result = TLI.LowerOperation(
6376 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG);
6377 assert(Result.getNode()->getOpcode() == ISD::BUILD_PAIR);
6378 Lo = Result.getNode()->getOperand(0);
6379 Hi = Result.getNode()->getOperand(1);
6385 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
6387 assert(0 && "Do not know how to expand this operator!");
6389 case ISD::EXTRACT_ELEMENT:
6390 ExpandOp(Node->getOperand(0), Lo, Hi);
6391 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
6392 return ExpandOp(Hi, Lo, Hi);
6393 return ExpandOp(Lo, Lo, Hi);
6394 case ISD::EXTRACT_VECTOR_ELT:
6395 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types.
6396 Lo = ExpandEXTRACT_VECTOR_ELT(Op);
6397 return ExpandOp(Lo, Lo, Hi);
6399 Lo = DAG.getNode(ISD::UNDEF, NVT);
6400 Hi = DAG.getNode(ISD::UNDEF, NVT);
6402 case ISD::Constant: {
6403 unsigned NVTBits = NVT.getSizeInBits();
6404 const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue();
6405 Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT);
6406 Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT);
6409 case ISD::ConstantFP: {
6410 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
6411 if (CFP->getValueType(0) == MVT::ppcf128) {
6412 APInt api = CFP->getValueAPF().bitcastToAPInt();
6413 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
6415 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
6419 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
6420 if (getTypeAction(Lo.getValueType()) == Expand)
6421 ExpandOp(Lo, Lo, Hi);
6424 case ISD::BUILD_PAIR:
6425 // Return the operands.
6426 Lo = Node->getOperand(0);
6427 Hi = Node->getOperand(1);
6430 case ISD::MERGE_VALUES:
6431 if (Node->getNumValues() == 1) {
6432 ExpandOp(Op.getOperand(0), Lo, Hi);
6435 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y)
6436 assert(Op.getResNo() == 0 && Node->getNumValues() == 2 &&
6437 Op.getValue(1).getValueType() == MVT::Other &&
6438 "unhandled MERGE_VALUES");
6439 ExpandOp(Op.getOperand(0), Lo, Hi);
6440 // Remember that we legalized the chain.
6441 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1)));
6444 case ISD::SIGN_EXTEND_INREG:
6445 ExpandOp(Node->getOperand(0), Lo, Hi);
6446 // sext_inreg the low part if needed.
6447 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
6449 // The high part gets the sign extension from the lo-part. This handles
6450 // things like sextinreg V:i64 from i8.
6451 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6452 DAG.getConstant(NVT.getSizeInBits()-1,
6453 TLI.getShiftAmountTy()));
6457 ExpandOp(Node->getOperand(0), Lo, Hi);
6458 SDValue TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
6459 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
6465 ExpandOp(Node->getOperand(0), Lo, Hi);
6466 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
6467 DAG.getNode(ISD::CTPOP, NVT, Lo),
6468 DAG.getNode(ISD::CTPOP, NVT, Hi));
6469 Hi = DAG.getConstant(0, NVT);
6473 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
6474 ExpandOp(Node->getOperand(0), Lo, Hi);
6475 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
6476 SDValue HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
6477 SDValue TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(NVT), HLZ, BitsC,
6479 SDValue LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
6480 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
6482 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
6483 Hi = DAG.getConstant(0, NVT);
6488 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
6489 ExpandOp(Node->getOperand(0), Lo, Hi);
6490 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
6491 SDValue LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
6492 SDValue BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(NVT), LTZ, BitsC,
6494 SDValue HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
6495 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
6497 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
6498 Hi = DAG.getConstant(0, NVT);
6503 SDValue Ch = Node->getOperand(0); // Legalize the chain.
6504 SDValue Ptr = Node->getOperand(1); // Legalize the pointer.
6505 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
6506 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
6508 // Remember that we legalized the chain.
6509 Hi = LegalizeOp(Hi);
6510 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
6511 if (TLI.isBigEndian())
6517 LoadSDNode *LD = cast<LoadSDNode>(Node);
6518 SDValue Ch = LD->getChain(); // Legalize the chain.
6519 SDValue Ptr = LD->getBasePtr(); // Legalize the pointer.
6520 ISD::LoadExtType ExtType = LD->getExtensionType();
6521 const Value *SV = LD->getSrcValue();
6522 int SVOffset = LD->getSrcValueOffset();
6523 unsigned Alignment = LD->getAlignment();
6524 bool isVolatile = LD->isVolatile();
6526 if (ExtType == ISD::NON_EXTLOAD) {
6527 Lo = DAG.getLoad(NVT, Ch, Ptr, SV, SVOffset,
6528 isVolatile, Alignment);
6529 if (VT == MVT::f32 || VT == MVT::f64) {
6530 // f32->i32 or f64->i64 one to one expansion.
6531 // Remember that we legalized the chain.
6532 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
6533 // Recursively expand the new load.
6534 if (getTypeAction(NVT) == Expand)
6535 ExpandOp(Lo, Lo, Hi);
6539 // Increment the pointer to the other half.
6540 unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8;
6541 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
6542 DAG.getIntPtrConstant(IncrementSize));
6543 SVOffset += IncrementSize;
6544 Alignment = MinAlign(Alignment, IncrementSize);
6545 Hi = DAG.getLoad(NVT, Ch, Ptr, SV, SVOffset,
6546 isVolatile, Alignment);
6548 // Build a factor node to remember that this load is independent of the
6550 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
6553 // Remember that we legalized the chain.
6554 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
6555 if (TLI.isBigEndian())
6558 MVT EVT = LD->getMemoryVT();
6560 if ((VT == MVT::f64 && EVT == MVT::f32) ||
6561 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
6562 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
6563 SDValue Load = DAG.getLoad(EVT, Ch, Ptr, SV,
6564 SVOffset, isVolatile, Alignment);
6565 // Remember that we legalized the chain.
6566 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Load.getValue(1)));
6567 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
6572 Lo = DAG.getLoad(NVT, Ch, Ptr, SV,
6573 SVOffset, isVolatile, Alignment);
6575 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, SV,
6576 SVOffset, EVT, isVolatile,
6579 // Remember that we legalized the chain.
6580 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
6582 if (ExtType == ISD::SEXTLOAD) {
6583 // The high part is obtained by SRA'ing all but one of the bits of the
6585 unsigned LoSize = Lo.getValueType().getSizeInBits();
6586 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6587 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6588 } else if (ExtType == ISD::ZEXTLOAD) {
6589 // The high part is just a zero.
6590 Hi = DAG.getConstant(0, NVT);
6591 } else /* if (ExtType == ISD::EXTLOAD) */ {
6592 // The high part is undefined.
6593 Hi = DAG.getNode(ISD::UNDEF, NVT);
6600 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
6601 SDValue LL, LH, RL, RH;
6602 ExpandOp(Node->getOperand(0), LL, LH);
6603 ExpandOp(Node->getOperand(1), RL, RH);
6604 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
6605 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
6609 SDValue LL, LH, RL, RH;
6610 ExpandOp(Node->getOperand(1), LL, LH);
6611 ExpandOp(Node->getOperand(2), RL, RH);
6612 if (getTypeAction(NVT) == Expand)
6613 NVT = TLI.getTypeToExpandTo(NVT);
6614 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
6616 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
6619 case ISD::SELECT_CC: {
6620 SDValue TL, TH, FL, FH;
6621 ExpandOp(Node->getOperand(2), TL, TH);
6622 ExpandOp(Node->getOperand(3), FL, FH);
6623 if (getTypeAction(NVT) == Expand)
6624 NVT = TLI.getTypeToExpandTo(NVT);
6625 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
6626 Node->getOperand(1), TL, FL, Node->getOperand(4));
6628 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
6629 Node->getOperand(1), TH, FH, Node->getOperand(4));
6632 case ISD::ANY_EXTEND:
6633 // The low part is any extension of the input (which degenerates to a copy).
6634 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
6635 // The high part is undefined.
6636 Hi = DAG.getNode(ISD::UNDEF, NVT);
6638 case ISD::SIGN_EXTEND: {
6639 // The low part is just a sign extension of the input (which degenerates to
6641 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
6643 // The high part is obtained by SRA'ing all but one of the bits of the lo
6645 unsigned LoSize = Lo.getValueType().getSizeInBits();
6646 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6647 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6650 case ISD::ZERO_EXTEND:
6651 // The low part is just a zero extension of the input (which degenerates to
6653 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
6655 // The high part is just a zero.
6656 Hi = DAG.getConstant(0, NVT);
6659 case ISD::TRUNCATE: {
6660 // The input value must be larger than this value. Expand *it*.
6662 ExpandOp(Node->getOperand(0), NewLo, Hi);
6664 // The low part is now either the right size, or it is closer. If not the
6665 // right size, make an illegal truncate so we recursively expand it.
6666 if (NewLo.getValueType() != Node->getValueType(0))
6667 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
6668 ExpandOp(NewLo, Lo, Hi);
6672 case ISD::BIT_CONVERT: {
6674 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
6675 // If the target wants to, allow it to lower this itself.
6676 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6677 case Expand: assert(0 && "cannot expand FP!");
6678 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
6679 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
6681 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
6684 // f32 / f64 must be expanded to i32 / i64.
6685 if (VT == MVT::f32 || VT == MVT::f64) {
6686 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6687 if (getTypeAction(NVT) == Expand)
6688 ExpandOp(Lo, Lo, Hi);
6692 // If source operand will be expanded to the same type as VT, i.e.
6693 // i64 <- f64, i32 <- f32, expand the source operand instead.
6694 MVT VT0 = Node->getOperand(0).getValueType();
6695 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
6696 ExpandOp(Node->getOperand(0), Lo, Hi);
6700 // Turn this into a load/store pair by default.
6701 if (Tmp.getNode() == 0)
6702 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT);
6704 ExpandOp(Tmp, Lo, Hi);
6708 case ISD::READCYCLECOUNTER: {
6709 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
6710 TargetLowering::Custom &&
6711 "Must custom expand ReadCycleCounter");
6712 SDValue Tmp = TLI.LowerOperation(Op, DAG);
6713 assert(Tmp.getNode() && "Node must be custom expanded!");
6714 ExpandOp(Tmp.getValue(0), Lo, Hi);
6715 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6716 LegalizeOp(Tmp.getValue(1)));
6720 case ISD::ATOMIC_CMP_SWAP: {
6721 // This operation does not need a loop.
6722 SDValue Tmp = TLI.LowerOperation(Op, DAG);
6723 assert(Tmp.getNode() && "Node must be custom expanded!");
6724 ExpandOp(Tmp.getValue(0), Lo, Hi);
6725 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6726 LegalizeOp(Tmp.getValue(1)));
6730 case ISD::ATOMIC_LOAD_ADD:
6731 case ISD::ATOMIC_LOAD_SUB:
6732 case ISD::ATOMIC_LOAD_AND:
6733 case ISD::ATOMIC_LOAD_OR:
6734 case ISD::ATOMIC_LOAD_XOR:
6735 case ISD::ATOMIC_LOAD_NAND:
6736 case ISD::ATOMIC_SWAP: {
6737 // These operations require a loop to be generated. We can't do that yet,
6738 // so substitute a target-dependent pseudo and expand that later.
6739 SDValue In2Lo, In2Hi, In2;
6740 ExpandOp(Op.getOperand(2), In2Lo, In2Hi);
6741 In2 = DAG.getNode(ISD::BUILD_PAIR, VT, In2Lo, In2Hi);
6742 AtomicSDNode* Anode = cast<AtomicSDNode>(Node);
6744 DAG.getAtomic(Op.getOpcode(), Anode->getMemoryVT(),
6745 Op.getOperand(0), Op.getOperand(1), In2,
6746 Anode->getSrcValue(), Anode->getAlignment());
6747 SDValue Result = TLI.LowerOperation(Replace, DAG);
6748 ExpandOp(Result.getValue(0), Lo, Hi);
6749 // Remember that we legalized the chain.
6750 AddLegalizedOperand(SDValue(Node,1), LegalizeOp(Result.getValue(1)));
6754 // These operators cannot be expanded directly, emit them as calls to
6755 // library functions.
6756 case ISD::FP_TO_SINT: {
6757 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
6759 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6760 case Expand: assert(0 && "cannot expand FP!");
6761 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6762 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6765 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
6767 // Now that the custom expander is done, expand the result, which is still
6770 ExpandOp(Op, Lo, Hi);
6775 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Node->getOperand(0).getValueType(),
6777 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected uint-to-fp conversion!");
6778 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6782 case ISD::FP_TO_UINT: {
6783 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
6785 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6786 case Expand: assert(0 && "cannot expand FP!");
6787 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6788 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6791 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
6793 // Now that the custom expander is done, expand the result.
6795 ExpandOp(Op, Lo, Hi);
6800 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Node->getOperand(0).getValueType(),
6802 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
6803 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6808 // If the target wants custom lowering, do so.
6809 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6810 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
6811 SDValue Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
6812 Op = TLI.LowerOperation(Op, DAG);
6814 // Now that the custom expander is done, expand the result, which is
6816 ExpandOp(Op, Lo, Hi);
6821 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
6822 // this X << 1 as X+X.
6823 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
6824 if (ShAmt->getAPIntValue() == 1 &&
6825 TLI.isOperationLegalOrCustom(ISD::ADDC, NVT) &&
6826 TLI.isOperationLegalOrCustom(ISD::ADDE, NVT)) {
6827 SDValue LoOps[2], HiOps[3];
6828 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
6829 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
6830 LoOps[1] = LoOps[0];
6831 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6833 HiOps[1] = HiOps[0];
6834 HiOps[2] = Lo.getValue(1);
6835 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6840 // If we can emit an efficient shift operation, do so now.
6841 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6844 // If this target supports SHL_PARTS, use it.
6845 TargetLowering::LegalizeAction Action =
6846 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
6847 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6848 Action == TargetLowering::Custom) {
6849 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6853 // Otherwise, emit a libcall.
6854 Lo = ExpandLibCall(RTLIB::SHL_I64, Node, false/*left shift=unsigned*/, Hi);
6859 // If the target wants custom lowering, do so.
6860 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6861 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
6862 SDValue Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
6863 Op = TLI.LowerOperation(Op, DAG);
6865 // Now that the custom expander is done, expand the result, which is
6867 ExpandOp(Op, Lo, Hi);
6872 // If we can emit an efficient shift operation, do so now.
6873 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
6876 // If this target supports SRA_PARTS, use it.
6877 TargetLowering::LegalizeAction Action =
6878 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
6879 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6880 Action == TargetLowering::Custom) {
6881 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6885 // Otherwise, emit a libcall.
6886 Lo = ExpandLibCall(RTLIB::SRA_I64, Node, true/*ashr is signed*/, Hi);
6891 // If the target wants custom lowering, do so.
6892 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6893 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
6894 SDValue Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
6895 Op = TLI.LowerOperation(Op, DAG);
6897 // Now that the custom expander is done, expand the result, which is
6899 ExpandOp(Op, Lo, Hi);
6904 // If we can emit an efficient shift operation, do so now.
6905 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6908 // If this target supports SRL_PARTS, use it.
6909 TargetLowering::LegalizeAction Action =
6910 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
6911 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6912 Action == TargetLowering::Custom) {
6913 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6917 // Otherwise, emit a libcall.
6918 Lo = ExpandLibCall(RTLIB::SRL_I64, Node, false/*lshr is unsigned*/, Hi);
6924 // If the target wants to custom expand this, let them.
6925 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
6926 TargetLowering::Custom) {
6927 SDValue Result = TLI.LowerOperation(Op, DAG);
6928 if (Result.getNode()) {
6929 ExpandOp(Result, Lo, Hi);
6933 // Expand the subcomponents.
6934 SDValue LHSL, LHSH, RHSL, RHSH;
6935 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6936 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6937 SDValue LoOps[2], HiOps[3];
6943 //cascaded check to see if any smaller size has a a carry flag.
6944 unsigned OpV = Node->getOpcode() == ISD::ADD ? ISD::ADDC : ISD::SUBC;
6945 bool hasCarry = false;
6946 for (unsigned BitSize = NVT.getSizeInBits(); BitSize != 0; BitSize /= 2) {
6947 MVT AVT = MVT::getIntegerVT(BitSize);
6948 if (TLI.isOperationLegalOrCustom(OpV, AVT)) {
6955 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6956 if (Node->getOpcode() == ISD::ADD) {
6957 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6958 HiOps[2] = Lo.getValue(1);
6959 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6961 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6962 HiOps[2] = Lo.getValue(1);
6963 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6967 if (Node->getOpcode() == ISD::ADD) {
6968 Lo = DAG.getNode(ISD::ADD, NVT, LoOps, 2);
6969 Hi = DAG.getNode(ISD::ADD, NVT, HiOps, 2);
6970 SDValue Cmp1 = DAG.getSetCC(TLI.getSetCCResultType(NVT),
6971 Lo, LoOps[0], ISD::SETULT);
6972 SDValue Carry1 = DAG.getNode(ISD::SELECT, NVT, Cmp1,
6973 DAG.getConstant(1, NVT),
6974 DAG.getConstant(0, NVT));
6975 SDValue Cmp2 = DAG.getSetCC(TLI.getSetCCResultType(NVT),
6976 Lo, LoOps[1], ISD::SETULT);
6977 SDValue Carry2 = DAG.getNode(ISD::SELECT, NVT, Cmp2,
6978 DAG.getConstant(1, NVT),
6980 Hi = DAG.getNode(ISD::ADD, NVT, Hi, Carry2);
6982 Lo = DAG.getNode(ISD::SUB, NVT, LoOps, 2);
6983 Hi = DAG.getNode(ISD::SUB, NVT, HiOps, 2);
6984 SDValue Cmp = DAG.getSetCC(NVT, LoOps[0], LoOps[1], ISD::SETULT);
6985 SDValue Borrow = DAG.getNode(ISD::SELECT, NVT, Cmp,
6986 DAG.getConstant(1, NVT),
6987 DAG.getConstant(0, NVT));
6988 Hi = DAG.getNode(ISD::SUB, NVT, Hi, Borrow);
6996 // Expand the subcomponents.
6997 SDValue LHSL, LHSH, RHSL, RHSH;
6998 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6999 ExpandOp(Node->getOperand(1), RHSL, RHSH);
7000 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
7001 SDValue LoOps[2] = { LHSL, RHSL };
7002 SDValue HiOps[3] = { LHSH, RHSH };
7004 if (Node->getOpcode() == ISD::ADDC) {
7005 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
7006 HiOps[2] = Lo.getValue(1);
7007 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
7009 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
7010 HiOps[2] = Lo.getValue(1);
7011 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
7013 // Remember that we legalized the flag.
7014 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
7019 // Expand the subcomponents.
7020 SDValue LHSL, LHSH, RHSL, RHSH;
7021 ExpandOp(Node->getOperand(0), LHSL, LHSH);
7022 ExpandOp(Node->getOperand(1), RHSL, RHSH);
7023 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
7024 SDValue LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
7025 SDValue HiOps[3] = { LHSH, RHSH };
7027 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
7028 HiOps[2] = Lo.getValue(1);
7029 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
7031 // Remember that we legalized the flag.
7032 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
7036 // If the target wants to custom expand this, let them.
7037 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
7038 SDValue New = TLI.LowerOperation(Op, DAG);
7039 if (New.getNode()) {
7040 ExpandOp(New, Lo, Hi);
7045 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT);
7046 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT);
7047 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT);
7048 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT);
7049 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
7050 SDValue LL, LH, RL, RH;
7051 ExpandOp(Node->getOperand(0), LL, LH);
7052 ExpandOp(Node->getOperand(1), RL, RH);
7053 unsigned OuterBitSize = Op.getValueSizeInBits();
7054 unsigned InnerBitSize = RH.getValueSizeInBits();
7055 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
7056 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
7057 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
7058 if (DAG.MaskedValueIsZero(Node->getOperand(0), HighMask) &&
7059 DAG.MaskedValueIsZero(Node->getOperand(1), HighMask)) {
7060 // The inputs are both zero-extended.
7062 // We can emit a umul_lohi.
7063 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
7064 Hi = SDValue(Lo.getNode(), 1);
7068 // We can emit a mulhu+mul.
7069 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
7070 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
7074 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
7075 // The input values are both sign-extended.
7077 // We can emit a smul_lohi.
7078 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
7079 Hi = SDValue(Lo.getNode(), 1);
7083 // We can emit a mulhs+mul.
7084 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
7085 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
7090 // Lo,Hi = umul LHS, RHS.
7091 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
7092 DAG.getVTList(NVT, NVT), LL, RL);
7094 Hi = UMulLOHI.getValue(1);
7095 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
7096 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
7097 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
7098 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
7102 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
7103 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
7104 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
7105 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
7106 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
7107 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
7112 // If nothing else, we can make a libcall.
7113 Lo = ExpandLibCall(RTLIB::MUL_I64, Node, false/*sign irrelevant*/, Hi);
7117 Lo = ExpandLibCall(RTLIB::SDIV_I64, Node, true, Hi);
7120 Lo = ExpandLibCall(RTLIB::UDIV_I64, Node, true, Hi);
7123 Lo = ExpandLibCall(RTLIB::SREM_I64, Node, true, Hi);
7126 Lo = ExpandLibCall(RTLIB::UREM_I64, Node, true, Hi);
7130 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::ADD_F32,
7133 RTLIB::ADD_PPCF128),
7137 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::SUB_F32,
7140 RTLIB::SUB_PPCF128),
7144 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::MUL_F32,
7147 RTLIB::MUL_PPCF128),
7151 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::DIV_F32,
7154 RTLIB::DIV_PPCF128),
7157 case ISD::FP_EXTEND: {
7158 if (VT == MVT::ppcf128) {
7159 assert(Node->getOperand(0).getValueType()==MVT::f32 ||
7160 Node->getOperand(0).getValueType()==MVT::f64);
7161 const uint64_t zero = 0;
7162 if (Node->getOperand(0).getValueType()==MVT::f32)
7163 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0));
7165 Hi = Node->getOperand(0);
7166 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7169 RTLIB::Libcall LC = RTLIB::getFPEXT(Node->getOperand(0).getValueType(), VT);
7170 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!");
7171 Lo = ExpandLibCall(LC, Node, true, Hi);
7174 case ISD::FP_ROUND: {
7175 RTLIB::Libcall LC = RTLIB::getFPROUND(Node->getOperand(0).getValueType(),
7177 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!");
7178 Lo = ExpandLibCall(LC, Node, true, Hi);
7193 case ISD::FNEARBYINT:
7196 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
7197 switch(Node->getOpcode()) {
7199 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
7200 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
7203 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
7204 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
7207 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
7208 RTLIB::COS_F80, RTLIB::COS_PPCF128);
7211 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
7212 RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
7215 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
7216 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
7219 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
7220 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
7223 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
7224 RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
7227 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
7228 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
7231 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
7232 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
7235 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
7236 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128);
7239 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
7240 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128);
7243 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64,
7244 RTLIB::RINT_F80, RTLIB::RINT_PPCF128);
7246 case ISD::FNEARBYINT:
7247 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
7248 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
7251 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
7252 RTLIB::POW_PPCF128);
7255 LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64, RTLIB::POWI_F80,
7256 RTLIB::POWI_PPCF128);
7258 default: assert(0 && "Unreachable!");
7260 Lo = ExpandLibCall(LC, Node, false, Hi);
7264 if (VT == MVT::ppcf128) {
7266 ExpandOp(Node->getOperand(0), Lo, Tmp);
7267 Hi = DAG.getNode(ISD::FABS, NVT, Tmp);
7268 // lo = hi==fabs(hi) ? lo : -lo;
7269 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp,
7270 Lo, DAG.getNode(ISD::FNEG, NVT, Lo),
7271 DAG.getCondCode(ISD::SETEQ));
7274 SDValue Mask = (VT == MVT::f64)
7275 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
7276 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
7277 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
7278 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
7279 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
7280 if (getTypeAction(NVT) == Expand)
7281 ExpandOp(Lo, Lo, Hi);
7285 if (VT == MVT::ppcf128) {
7286 ExpandOp(Node->getOperand(0), Lo, Hi);
7287 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo);
7288 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi);
7291 SDValue Mask = (VT == MVT::f64)
7292 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
7293 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
7294 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
7295 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
7296 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
7297 if (getTypeAction(NVT) == Expand)
7298 ExpandOp(Lo, Lo, Hi);
7301 case ISD::FCOPYSIGN: {
7302 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
7303 if (getTypeAction(NVT) == Expand)
7304 ExpandOp(Lo, Lo, Hi);
7307 case ISD::SINT_TO_FP:
7308 case ISD::UINT_TO_FP: {
7309 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
7310 MVT SrcVT = Node->getOperand(0).getValueType();
7312 // Promote the operand if needed. Do this before checking for
7313 // ppcf128 so conversions of i16 and i8 work.
7314 if (getTypeAction(SrcVT) == Promote) {
7315 SDValue Tmp = PromoteOp(Node->getOperand(0));
7317 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
7318 DAG.getValueType(SrcVT))
7319 : DAG.getZeroExtendInReg(Tmp, SrcVT);
7320 Node = DAG.UpdateNodeOperands(Op, Tmp).getNode();
7321 SrcVT = Node->getOperand(0).getValueType();
7324 if (VT == MVT::ppcf128 && SrcVT == MVT::i32) {
7325 static const uint64_t zero = 0;
7327 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
7328 Node->getOperand(0)));
7329 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7331 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
7332 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
7333 Node->getOperand(0)));
7334 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7335 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
7336 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
7337 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
7338 DAG.getConstant(0, MVT::i32),
7339 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
7341 APFloat(APInt(128, 2, TwoE32)),
7344 DAG.getCondCode(ISD::SETLT)),
7349 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) {
7350 // si64->ppcf128 done by libcall, below
7351 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
7352 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)),
7354 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
7355 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
7356 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
7357 DAG.getConstant(0, MVT::i64),
7358 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
7360 APFloat(APInt(128, 2, TwoE64)),
7363 DAG.getCondCode(ISD::SETLT)),
7368 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
7369 Node->getOperand(0));
7370 if (getTypeAction(Lo.getValueType()) == Expand)
7371 // float to i32 etc. can be 'expanded' to a single node.
7372 ExpandOp(Lo, Lo, Hi);
7377 // Make sure the resultant values have been legalized themselves, unless this
7378 // is a type that requires multi-step expansion.
7379 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
7380 Lo = LegalizeOp(Lo);
7382 // Don't legalize the high part if it is expanded to a single node.
7383 Hi = LegalizeOp(Hi);
7386 // Remember in a map if the values will be reused later.
7388 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
7389 assert(isNew && "Value already expanded?!?");
7393 /// SplitVectorOp - Given an operand of vector type, break it down into
7394 /// two smaller values, still of vector type.
7395 void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
7397 assert(Op.getValueType().isVector() && "Cannot split non-vector type!");
7398 SDNode *Node = Op.getNode();
7399 unsigned NumElements = Op.getValueType().getVectorNumElements();
7400 assert(NumElements > 1 && "Cannot split a single element vector!");
7402 MVT NewEltVT = Op.getValueType().getVectorElementType();
7404 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
7405 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
7407 MVT NewVT_Lo = MVT::getVectorVT(NewEltVT, NewNumElts_Lo);
7408 MVT NewVT_Hi = MVT::getVectorVT(NewEltVT, NewNumElts_Hi);
7410 // See if we already split it.
7411 std::map<SDValue, std::pair<SDValue, SDValue> >::iterator I
7412 = SplitNodes.find(Op);
7413 if (I != SplitNodes.end()) {
7414 Lo = I->second.first;
7415 Hi = I->second.second;
7419 switch (Node->getOpcode()) {
7424 assert(0 && "Unhandled operation in SplitVectorOp!");
7426 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo);
7427 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi);
7429 case ISD::BUILD_PAIR:
7430 Lo = Node->getOperand(0);
7431 Hi = Node->getOperand(1);
7433 case ISD::INSERT_VECTOR_ELT: {
7434 if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) {
7435 SplitVectorOp(Node->getOperand(0), Lo, Hi);
7436 unsigned Index = Idx->getZExtValue();
7437 SDValue ScalarOp = Node->getOperand(1);
7438 if (Index < NewNumElts_Lo)
7439 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp,
7440 DAG.getIntPtrConstant(Index));
7442 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp,
7443 DAG.getIntPtrConstant(Index - NewNumElts_Lo));
7446 SDValue Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0),
7447 Node->getOperand(1),
7448 Node->getOperand(2));
7449 SplitVectorOp(Tmp, Lo, Hi);
7452 case ISD::VECTOR_SHUFFLE: {
7453 // Build the low part.
7454 SDValue Mask = Node->getOperand(2);
7455 SmallVector<SDValue, 8> Ops;
7456 MVT PtrVT = TLI.getPointerTy();
7458 // Insert all of the elements from the input that are needed. We use
7459 // buildvector of extractelement here because the input vectors will have
7460 // to be legalized, so this makes the code simpler.
7461 for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
7462 SDValue IdxNode = Mask.getOperand(i);
7463 if (IdxNode.getOpcode() == ISD::UNDEF) {
7464 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
7467 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
7468 SDValue InVec = Node->getOperand(0);
7469 if (Idx >= NumElements) {
7470 InVec = Node->getOperand(1);
7473 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
7474 DAG.getConstant(Idx, PtrVT)));
7476 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
7479 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
7480 SDValue IdxNode = Mask.getOperand(i);
7481 if (IdxNode.getOpcode() == ISD::UNDEF) {
7482 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
7485 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
7486 SDValue InVec = Node->getOperand(0);
7487 if (Idx >= NumElements) {
7488 InVec = Node->getOperand(1);
7491 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
7492 DAG.getConstant(Idx, PtrVT)));
7494 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &Ops[0], Ops.size());
7497 case ISD::BUILD_VECTOR: {
7498 SmallVector<SDValue, 8> LoOps(Node->op_begin(),
7499 Node->op_begin()+NewNumElts_Lo);
7500 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size());
7502 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
7504 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size());
7507 case ISD::CONCAT_VECTORS: {
7508 // FIXME: Handle non-power-of-two vectors?
7509 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
7510 if (NewNumSubvectors == 1) {
7511 Lo = Node->getOperand(0);
7512 Hi = Node->getOperand(1);
7514 SmallVector<SDValue, 8> LoOps(Node->op_begin(),
7515 Node->op_begin()+NewNumSubvectors);
7516 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size());
7518 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumSubvectors,
7520 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size());
7524 case ISD::EXTRACT_SUBVECTOR: {
7525 SDValue Vec = Op.getOperand(0);
7526 SDValue Idx = Op.getOperand(1);
7527 MVT IdxVT = Idx.getValueType();
7529 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, NewVT_Lo, Vec, Idx);
7530 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx);
7532 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, NewVT_Hi, Vec,
7533 DAG.getConstant(CIdx->getZExtValue() + NewNumElts_Lo,
7536 Idx = DAG.getNode(ISD::ADD, IdxVT, Idx,
7537 DAG.getConstant(NewNumElts_Lo, IdxVT));
7538 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, NewVT_Hi, Vec, Idx);
7543 SDValue Cond = Node->getOperand(0);
7545 SDValue LL, LH, RL, RH;
7546 SplitVectorOp(Node->getOperand(1), LL, LH);
7547 SplitVectorOp(Node->getOperand(2), RL, RH);
7549 if (Cond.getValueType().isVector()) {
7550 // Handle a vector merge.
7552 SplitVectorOp(Cond, CL, CH);
7553 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL);
7554 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH);
7556 // Handle a simple select with vector operands.
7557 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL);
7558 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH);
7562 case ISD::SELECT_CC: {
7563 SDValue CondLHS = Node->getOperand(0);
7564 SDValue CondRHS = Node->getOperand(1);
7565 SDValue CondCode = Node->getOperand(4);
7567 SDValue LL, LH, RL, RH;
7568 SplitVectorOp(Node->getOperand(2), LL, LH);
7569 SplitVectorOp(Node->getOperand(3), RL, RH);
7571 // Handle a simple select with vector operands.
7572 Lo = DAG.getNode(ISD::SELECT_CC, NewVT_Lo, CondLHS, CondRHS,
7574 Hi = DAG.getNode(ISD::SELECT_CC, NewVT_Hi, CondLHS, CondRHS,
7579 SDValue LL, LH, RL, RH;
7580 SplitVectorOp(Node->getOperand(0), LL, LH);
7581 SplitVectorOp(Node->getOperand(1), RL, RH);
7582 Lo = DAG.getNode(ISD::VSETCC, NewVT_Lo, LL, RL, Node->getOperand(2));
7583 Hi = DAG.getNode(ISD::VSETCC, NewVT_Hi, LH, RH, Node->getOperand(2));
7605 SDValue LL, LH, RL, RH;
7606 SplitVectorOp(Node->getOperand(0), LL, LH);
7607 SplitVectorOp(Node->getOperand(1), RL, RH);
7609 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL);
7610 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH);
7616 SplitVectorOp(Node->getOperand(0), L, H);
7618 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1));
7619 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1));
7635 case ISD::FP_TO_SINT:
7636 case ISD::FP_TO_UINT:
7637 case ISD::SINT_TO_FP:
7638 case ISD::UINT_TO_FP:
7640 case ISD::ANY_EXTEND:
7641 case ISD::SIGN_EXTEND:
7642 case ISD::ZERO_EXTEND:
7643 case ISD::FP_EXTEND: {
7645 SplitVectorOp(Node->getOperand(0), L, H);
7647 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L);
7648 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H);
7651 case ISD::CONVERT_RNDSAT: {
7652 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
7654 SplitVectorOp(Node->getOperand(0), L, H);
7655 SDValue DTyOpL = DAG.getValueType(NewVT_Lo);
7656 SDValue DTyOpH = DAG.getValueType(NewVT_Hi);
7657 SDValue STyOpL = DAG.getValueType(L.getValueType());
7658 SDValue STyOpH = DAG.getValueType(H.getValueType());
7660 SDValue RndOp = Node->getOperand(3);
7661 SDValue SatOp = Node->getOperand(4);
7663 Lo = DAG.getConvertRndSat(NewVT_Lo, L, DTyOpL, STyOpL,
7664 RndOp, SatOp, CvtCode);
7665 Hi = DAG.getConvertRndSat(NewVT_Hi, H, DTyOpH, STyOpH,
7666 RndOp, SatOp, CvtCode);
7670 LoadSDNode *LD = cast<LoadSDNode>(Node);
7671 SDValue Ch = LD->getChain();
7672 SDValue Ptr = LD->getBasePtr();
7673 ISD::LoadExtType ExtType = LD->getExtensionType();
7674 const Value *SV = LD->getSrcValue();
7675 int SVOffset = LD->getSrcValueOffset();
7676 MVT MemoryVT = LD->getMemoryVT();
7677 unsigned Alignment = LD->getAlignment();
7678 bool isVolatile = LD->isVolatile();
7680 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
7681 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType());
7683 MVT MemNewEltVT = MemoryVT.getVectorElementType();
7684 MVT MemNewVT_Lo = MVT::getVectorVT(MemNewEltVT, NewNumElts_Lo);
7685 MVT MemNewVT_Hi = MVT::getVectorVT(MemNewEltVT, NewNumElts_Hi);
7687 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType,
7688 NewVT_Lo, Ch, Ptr, Offset,
7689 SV, SVOffset, MemNewVT_Lo, isVolatile, Alignment);
7690 unsigned IncrementSize = NewNumElts_Lo * MemNewEltVT.getSizeInBits()/8;
7691 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
7692 DAG.getIntPtrConstant(IncrementSize));
7693 SVOffset += IncrementSize;
7694 Alignment = MinAlign(Alignment, IncrementSize);
7695 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType,
7696 NewVT_Hi, Ch, Ptr, Offset,
7697 SV, SVOffset, MemNewVT_Hi, isVolatile, Alignment);
7699 // Build a factor node to remember that this load is independent of the
7701 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
7704 // Remember that we legalized the chain.
7705 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
7708 case ISD::BIT_CONVERT: {
7709 // We know the result is a vector. The input may be either a vector or a
7711 SDValue InOp = Node->getOperand(0);
7712 if (!InOp.getValueType().isVector() ||
7713 InOp.getValueType().getVectorNumElements() == 1) {
7714 // The input is a scalar or single-element vector.
7715 // Lower to a store/load so that it can be split.
7716 // FIXME: this could be improved probably.
7717 unsigned LdAlign = TLI.getTargetData()->getPrefTypeAlignment(
7718 Op.getValueType().getTypeForMVT());
7719 SDValue Ptr = DAG.CreateStackTemporary(InOp.getValueType(), LdAlign);
7720 int FI = cast<FrameIndexSDNode>(Ptr.getNode())->getIndex();
7722 SDValue St = DAG.getStore(DAG.getEntryNode(),
7724 PseudoSourceValue::getFixedStack(FI), 0);
7725 InOp = DAG.getLoad(Op.getValueType(), St, Ptr,
7726 PseudoSourceValue::getFixedStack(FI), 0);
7728 // Split the vector and convert each of the pieces now.
7729 SplitVectorOp(InOp, Lo, Hi);
7730 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo);
7731 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi);
7736 // Remember in a map if the values will be reused later.
7738 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
7739 assert(isNew && "Value already split?!?");
7744 /// ScalarizeVectorOp - Given an operand of single-element vector type
7745 /// (e.g. v1f32), convert it into the equivalent operation that returns a
7746 /// scalar (e.g. f32) value.
7747 SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) {
7748 assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!");
7749 SDNode *Node = Op.getNode();
7750 MVT NewVT = Op.getValueType().getVectorElementType();
7751 assert(Op.getValueType().getVectorNumElements() == 1);
7753 // See if we already scalarized it.
7754 std::map<SDValue, SDValue>::iterator I = ScalarizedNodes.find(Op);
7755 if (I != ScalarizedNodes.end()) return I->second;
7758 switch (Node->getOpcode()) {
7761 Node->dump(&DAG); cerr << "\n";
7763 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
7780 Result = DAG.getNode(Node->getOpcode(),
7782 ScalarizeVectorOp(Node->getOperand(0)),
7783 ScalarizeVectorOp(Node->getOperand(1)));
7795 case ISD::FP_TO_SINT:
7796 case ISD::FP_TO_UINT:
7797 case ISD::SINT_TO_FP:
7798 case ISD::UINT_TO_FP:
7799 case ISD::SIGN_EXTEND:
7800 case ISD::ZERO_EXTEND:
7801 case ISD::ANY_EXTEND:
7803 case ISD::FP_EXTEND:
7804 Result = DAG.getNode(Node->getOpcode(),
7806 ScalarizeVectorOp(Node->getOperand(0)));
7808 case ISD::CONVERT_RNDSAT: {
7809 SDValue Op0 = ScalarizeVectorOp(Node->getOperand(0));
7810 Result = DAG.getConvertRndSat(NewVT, Op0,
7811 DAG.getValueType(NewVT),
7812 DAG.getValueType(Op0.getValueType()),
7813 Node->getOperand(3),
7814 Node->getOperand(4),
7815 cast<CvtRndSatSDNode>(Node)->getCvtCode());
7820 Result = DAG.getNode(Node->getOpcode(),
7822 ScalarizeVectorOp(Node->getOperand(0)),
7823 Node->getOperand(1));
7826 LoadSDNode *LD = cast<LoadSDNode>(Node);
7827 SDValue Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
7828 SDValue Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
7829 ISD::LoadExtType ExtType = LD->getExtensionType();
7830 const Value *SV = LD->getSrcValue();
7831 int SVOffset = LD->getSrcValueOffset();
7832 MVT MemoryVT = LD->getMemoryVT();
7833 unsigned Alignment = LD->getAlignment();
7834 bool isVolatile = LD->isVolatile();
7836 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
7837 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType());
7839 Result = DAG.getLoad(ISD::UNINDEXED, ExtType,
7840 NewVT, Ch, Ptr, Offset, SV, SVOffset,
7841 MemoryVT.getVectorElementType(),
7842 isVolatile, Alignment);
7844 // Remember that we legalized the chain.
7845 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
7848 case ISD::BUILD_VECTOR:
7849 Result = Node->getOperand(0);
7851 case ISD::INSERT_VECTOR_ELT:
7852 // Returning the inserted scalar element.
7853 Result = Node->getOperand(1);
7855 case ISD::CONCAT_VECTORS:
7856 assert(Node->getOperand(0).getValueType() == NewVT &&
7857 "Concat of non-legal vectors not yet supported!");
7858 Result = Node->getOperand(0);
7860 case ISD::VECTOR_SHUFFLE: {
7861 // Figure out if the scalar is the LHS or RHS and return it.
7862 SDValue EltNum = Node->getOperand(2).getOperand(0);
7863 if (cast<ConstantSDNode>(EltNum)->getZExtValue())
7864 Result = ScalarizeVectorOp(Node->getOperand(1));
7866 Result = ScalarizeVectorOp(Node->getOperand(0));
7869 case ISD::EXTRACT_SUBVECTOR:
7870 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, Node->getOperand(0),
7871 Node->getOperand(1));
7873 case ISD::BIT_CONVERT: {
7874 SDValue Op0 = Op.getOperand(0);
7875 if (Op0.getValueType().getVectorNumElements() == 1)
7876 Op0 = ScalarizeVectorOp(Op0);
7877 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op0);
7881 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
7882 ScalarizeVectorOp(Op.getOperand(1)),
7883 ScalarizeVectorOp(Op.getOperand(2)));
7885 case ISD::SELECT_CC:
7886 Result = DAG.getNode(ISD::SELECT_CC, NewVT, Node->getOperand(0),
7887 Node->getOperand(1),
7888 ScalarizeVectorOp(Op.getOperand(2)),
7889 ScalarizeVectorOp(Op.getOperand(3)),
7890 Node->getOperand(4));
7893 SDValue Op0 = ScalarizeVectorOp(Op.getOperand(0));
7894 SDValue Op1 = ScalarizeVectorOp(Op.getOperand(1));
7895 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Op0.getValueType()),
7896 Op0, Op1, Op.getOperand(2));
7897 Result = DAG.getNode(ISD::SELECT, NewVT, Result,
7898 DAG.getConstant(-1ULL, NewVT),
7899 DAG.getConstant(0ULL, NewVT));
7904 if (TLI.isTypeLegal(NewVT))
7905 Result = LegalizeOp(Result);
7906 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
7907 assert(isNew && "Value already scalarized?");
7913 SDValue SelectionDAGLegalize::WidenVectorOp(SDValue Op, MVT WidenVT) {
7914 std::map<SDValue, SDValue>::iterator I = WidenNodes.find(Op);
7915 if (I != WidenNodes.end()) return I->second;
7917 MVT VT = Op.getValueType();
7918 assert(VT.isVector() && "Cannot widen non-vector type!");
7921 SDNode *Node = Op.getNode();
7922 MVT EVT = VT.getVectorElementType();
7924 unsigned NumElts = VT.getVectorNumElements();
7925 unsigned NewNumElts = WidenVT.getVectorNumElements();
7926 assert(NewNumElts > NumElts && "Cannot widen to smaller type!");
7927 assert(NewNumElts < 17);
7929 // When widen is called, it is assumed that it is more efficient to use a
7930 // wide type. The default action is to widen to operation to a wider legal
7931 // vector type and then do the operation if it is legal by calling LegalizeOp
7932 // again. If there is no vector equivalent, we will unroll the operation, do
7933 // it, and rebuild the vector. If most of the operations are vectorizible to
7934 // the legal type, the resulting code will be more efficient. If this is not
7935 // the case, the resulting code will preform badly as we end up generating
7936 // code to pack/unpack the results. It is the function that calls widen
7937 // that is responsible for seeing this doesn't happen.
7938 switch (Node->getOpcode()) {
7943 assert(0 && "Unexpected operation in WidenVectorOp!");
7945 case ISD::CopyFromReg:
7946 assert(0 && "CopyFromReg doesn't need widening!");
7948 case ISD::ConstantFP:
7949 // To build a vector of these elements, clients should call BuildVector
7950 // and with each element instead of creating a node with a vector type
7951 assert(0 && "Unexpected operation in WidenVectorOp!");
7953 // Variable Arguments with vector types doesn't make any sense to me
7954 assert(0 && "Unexpected operation in WidenVectorOp!");
7957 Result = DAG.getNode(ISD::UNDEF, WidenVT);
7959 case ISD::BUILD_VECTOR: {
7960 // Build a vector with undefined for the new nodes
7961 SDValueVector NewOps(Node->op_begin(), Node->op_end());
7962 for (unsigned i = NumElts; i < NewNumElts; ++i) {
7963 NewOps.push_back(DAG.getNode(ISD::UNDEF,EVT));
7965 Result = DAG.getNode(ISD::BUILD_VECTOR, WidenVT, &NewOps[0], NewOps.size());
7968 case ISD::INSERT_VECTOR_ELT: {
7969 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
7970 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, WidenVT, Tmp1,
7971 Node->getOperand(1), Node->getOperand(2));
7974 case ISD::VECTOR_SHUFFLE: {
7975 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
7976 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT);
7977 // VECTOR_SHUFFLE 3rd operand must be a constant build vector that is
7978 // used as permutation array. We build the vector here instead of widening
7979 // because we don't want to legalize and have it turned to something else.
7980 SDValue PermOp = Node->getOperand(2);
7981 SDValueVector NewOps;
7982 MVT PVT = PermOp.getValueType().getVectorElementType();
7983 for (unsigned i = 0; i < NumElts; ++i) {
7984 if (PermOp.getOperand(i).getOpcode() == ISD::UNDEF) {
7985 NewOps.push_back(PermOp.getOperand(i));
7988 cast<ConstantSDNode>(PermOp.getOperand(i))->getZExtValue();
7989 if (Idx < NumElts) {
7990 NewOps.push_back(PermOp.getOperand(i));
7993 NewOps.push_back(DAG.getConstant(Idx + NewNumElts - NumElts,
7994 PermOp.getOperand(i).getValueType()));
7998 for (unsigned i = NumElts; i < NewNumElts; ++i) {
7999 NewOps.push_back(DAG.getNode(ISD::UNDEF,PVT));
8002 SDValue Tmp3 = DAG.getNode(ISD::BUILD_VECTOR,
8003 MVT::getVectorVT(PVT, NewOps.size()),
8004 &NewOps[0], NewOps.size());
8006 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, WidenVT, Tmp1, Tmp2, Tmp3);
8010 // If the load widen returns true, we can use a single load for the
8011 // vector. Otherwise, it is returning a token factor for multiple
8014 if (LoadWidenVectorOp(Result, TFOp, Op, WidenVT))
8015 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TFOp.getValue(1)));
8017 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TFOp.getValue(0)));
8021 case ISD::BIT_CONVERT: {
8022 SDValue Tmp1 = Node->getOperand(0);
8023 // Converts between two different types so we need to determine
8024 // the correct widen type for the input operand.
8025 MVT InVT = Tmp1.getValueType();
8026 unsigned WidenSize = WidenVT.getSizeInBits();
8027 if (InVT.isVector()) {
8028 MVT InEltVT = InVT.getVectorElementType();
8029 unsigned InEltSize = InEltVT.getSizeInBits();
8030 assert(WidenSize % InEltSize == 0 &&
8031 "can not widen bit convert that are not multiple of element type");
8032 MVT NewInWidenVT = MVT::getVectorVT(InEltVT, WidenSize / InEltSize);
8033 Tmp1 = WidenVectorOp(Tmp1, NewInWidenVT);
8034 assert(Tmp1.getValueType().getSizeInBits() == WidenVT.getSizeInBits());
8035 Result = DAG.getNode(ISD::BIT_CONVERT, WidenVT, Tmp1);
8037 // If the result size is a multiple of the input size, widen the input
8038 // and then convert.
8039 unsigned InSize = InVT.getSizeInBits();
8040 assert(WidenSize % InSize == 0 &&
8041 "can not widen bit convert that are not multiple of element type");
8042 unsigned NewNumElts = WidenSize / InSize;
8043 SmallVector<SDValue, 16> Ops(NewNumElts);
8044 SDValue UndefVal = DAG.getNode(ISD::UNDEF, InVT);
8046 for (unsigned i = 1; i < NewNumElts; ++i)
8049 MVT NewInVT = MVT::getVectorVT(InVT, NewNumElts);
8050 Result = DAG.getNode(ISD::BUILD_VECTOR, NewInVT, &Ops[0], NewNumElts);
8051 Result = DAG.getNode(ISD::BIT_CONVERT, WidenVT, Result);
8056 case ISD::SINT_TO_FP:
8057 case ISD::UINT_TO_FP:
8058 case ISD::FP_TO_SINT:
8059 case ISD::FP_TO_UINT:
8060 case ISD::FP_ROUND: {
8061 SDValue Tmp1 = Node->getOperand(0);
8062 // Converts between two different types so we need to determine
8063 // the correct widen type for the input operand.
8064 MVT TVT = Tmp1.getValueType();
8065 assert(TVT.isVector() && "can not widen non vector type");
8066 MVT TEVT = TVT.getVectorElementType();
8067 MVT TWidenVT = MVT::getVectorVT(TEVT, NewNumElts);
8068 Tmp1 = WidenVectorOp(Tmp1, TWidenVT);
8069 assert(Tmp1.getValueType().getVectorNumElements() == NewNumElts);
8070 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1);
8074 case ISD::FP_EXTEND:
8075 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
8077 case ISD::SIGN_EXTEND:
8078 case ISD::ZERO_EXTEND:
8079 case ISD::ANY_EXTEND:
8080 case ISD::SIGN_EXTEND_INREG:
8089 // Unary op widening
8091 Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8092 assert(Tmp1.getValueType() == WidenVT);
8093 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1);
8096 case ISD::CONVERT_RNDSAT: {
8097 SDValue RndOp = Node->getOperand(3);
8098 SDValue SatOp = Node->getOperand(4);
8099 SDValue SrcOp = Node->getOperand(0);
8101 // Converts between two different types so we need to determine
8102 // the correct widen type for the input operand.
8103 MVT SVT = SrcOp.getValueType();
8104 assert(SVT.isVector() && "can not widen non vector type");
8105 MVT SEVT = SVT.getVectorElementType();
8106 MVT SWidenVT = MVT::getVectorVT(SEVT, NewNumElts);
8108 SrcOp = WidenVectorOp(SrcOp, SWidenVT);
8109 assert(SrcOp.getValueType() == WidenVT);
8110 SDValue DTyOp = DAG.getValueType(WidenVT);
8111 SDValue STyOp = DAG.getValueType(SrcOp.getValueType());
8112 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
8114 Result = DAG.getConvertRndSat(WidenVT, SrcOp, DTyOp, STyOp,
8115 RndOp, SatOp, CvtCode);
8135 case ISD::FCOPYSIGN:
8139 // Binary op widening
8140 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8141 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT);
8142 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT);
8143 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1, Tmp2);
8150 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8151 assert(Tmp1.getValueType() == WidenVT);
8152 SDValue ShOp = Node->getOperand(1);
8153 MVT ShVT = ShOp.getValueType();
8154 MVT NewShVT = MVT::getVectorVT(ShVT.getVectorElementType(),
8155 WidenVT.getVectorNumElements());
8156 ShOp = WidenVectorOp(ShOp, NewShVT);
8157 assert(ShOp.getValueType() == NewShVT);
8158 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1, ShOp);
8162 case ISD::EXTRACT_VECTOR_ELT: {
8163 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8164 assert(Tmp1.getValueType() == WidenVT);
8165 Result = DAG.getNode(Node->getOpcode(), EVT, Tmp1, Node->getOperand(1));
8168 case ISD::CONCAT_VECTORS: {
8169 // We concurrently support only widen on a multiple of the incoming vector.
8170 // We could widen on a multiple of the incoming operand if necessary.
8171 unsigned NumConcat = NewNumElts / NumElts;
8172 assert(NewNumElts % NumElts == 0 && "Can widen only a multiple of vector");
8173 SDValue UndefVal = DAG.getNode(ISD::UNDEF, VT);
8174 SmallVector<SDValue, 8> MOps;
8176 for (unsigned i = 1; i != NumConcat; ++i) {
8177 MOps.push_back(UndefVal);
8179 Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, WidenVT,
8180 &MOps[0], MOps.size()));
8183 case ISD::EXTRACT_SUBVECTOR: {
8184 SDValue Tmp1 = Node->getOperand(0);
8185 SDValue Idx = Node->getOperand(1);
8186 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx);
8187 if (CIdx && CIdx->getZExtValue() == 0) {
8188 // Since we are access the start of the vector, the incoming
8189 // vector type might be the proper.
8190 MVT Tmp1VT = Tmp1.getValueType();
8191 if (Tmp1VT == WidenVT)
8194 unsigned Tmp1VTNumElts = Tmp1VT.getVectorNumElements();
8195 if (Tmp1VTNumElts < NewNumElts)
8196 Result = WidenVectorOp(Tmp1, WidenVT);
8198 Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, WidenVT, Tmp1, Idx);
8200 } else if (NewNumElts % NumElts == 0) {
8201 // Widen the extracted subvector.
8202 unsigned NumConcat = NewNumElts / NumElts;
8203 SDValue UndefVal = DAG.getNode(ISD::UNDEF, VT);
8204 SmallVector<SDValue, 8> MOps;
8206 for (unsigned i = 1; i != NumConcat; ++i) {
8207 MOps.push_back(UndefVal);
8209 Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, WidenVT,
8210 &MOps[0], MOps.size()));
8212 assert(0 && "can not widen extract subvector");
8213 // This could be implemented using insert and build vector but I would
8214 // like to see when this happens.
8220 // Determine new condition widen type and widen
8221 SDValue Cond1 = Node->getOperand(0);
8222 MVT CondVT = Cond1.getValueType();
8223 assert(CondVT.isVector() && "can not widen non vector type");
8224 MVT CondEVT = CondVT.getVectorElementType();
8225 MVT CondWidenVT = MVT::getVectorVT(CondEVT, NewNumElts);
8226 Cond1 = WidenVectorOp(Cond1, CondWidenVT);
8227 assert(Cond1.getValueType() == CondWidenVT && "Condition not widen");
8229 SDValue Tmp1 = WidenVectorOp(Node->getOperand(1), WidenVT);
8230 SDValue Tmp2 = WidenVectorOp(Node->getOperand(2), WidenVT);
8231 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT);
8232 Result = DAG.getNode(Node->getOpcode(), WidenVT, Cond1, Tmp1, Tmp2);
8236 case ISD::SELECT_CC: {
8237 // Determine new condition widen type and widen
8238 SDValue Cond1 = Node->getOperand(0);
8239 SDValue Cond2 = Node->getOperand(1);
8240 MVT CondVT = Cond1.getValueType();
8241 assert(CondVT.isVector() && "can not widen non vector type");
8242 assert(CondVT == Cond2.getValueType() && "mismatch lhs/rhs");
8243 MVT CondEVT = CondVT.getVectorElementType();
8244 MVT CondWidenVT = MVT::getVectorVT(CondEVT, NewNumElts);
8245 Cond1 = WidenVectorOp(Cond1, CondWidenVT);
8246 Cond2 = WidenVectorOp(Cond2, CondWidenVT);
8247 assert(Cond1.getValueType() == CondWidenVT &&
8248 Cond2.getValueType() == CondWidenVT && "condition not widen");
8250 SDValue Tmp1 = WidenVectorOp(Node->getOperand(2), WidenVT);
8251 SDValue Tmp2 = WidenVectorOp(Node->getOperand(3), WidenVT);
8252 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT &&
8253 "operands not widen");
8254 Result = DAG.getNode(Node->getOpcode(), WidenVT, Cond1, Cond2, Tmp1,
8255 Tmp2, Node->getOperand(4));
8259 // Determine widen for the operand
8260 SDValue Tmp1 = Node->getOperand(0);
8261 MVT TmpVT = Tmp1.getValueType();
8262 assert(TmpVT.isVector() && "can not widen non vector type");
8263 MVT TmpEVT = TmpVT.getVectorElementType();
8264 MVT TmpWidenVT = MVT::getVectorVT(TmpEVT, NewNumElts);
8265 Tmp1 = WidenVectorOp(Tmp1, TmpWidenVT);
8266 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), TmpWidenVT);
8267 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1, Tmp2,
8268 Node->getOperand(2));
8271 case ISD::ATOMIC_CMP_SWAP:
8272 case ISD::ATOMIC_LOAD_ADD:
8273 case ISD::ATOMIC_LOAD_SUB:
8274 case ISD::ATOMIC_LOAD_AND:
8275 case ISD::ATOMIC_LOAD_OR:
8276 case ISD::ATOMIC_LOAD_XOR:
8277 case ISD::ATOMIC_LOAD_NAND:
8278 case ISD::ATOMIC_LOAD_MIN:
8279 case ISD::ATOMIC_LOAD_MAX:
8280 case ISD::ATOMIC_LOAD_UMIN:
8281 case ISD::ATOMIC_LOAD_UMAX:
8282 case ISD::ATOMIC_SWAP: {
8283 // For now, we assume that using vectors for these operations don't make
8284 // much sense so we just split it. We return an empty result
8286 SplitVectorOp(Op, X, Y);
8291 } // end switch (Node->getOpcode())
8293 assert(Result.getNode() && "Didn't set a result!");
8295 Result = LegalizeOp(Result);
8297 AddWidenedOperand(Op, Result);
8301 // Utility function to find a legal vector type and its associated element
8302 // type from a preferred width and whose vector type must be the same size
8304 // TLI: Target lowering used to determine legal types
8305 // Width: Preferred width of element type
8306 // VVT: Vector value type whose size we must match.
8307 // Returns VecEVT and EVT - the vector type and its associated element type
8308 static void FindWidenVecType(const TargetLowering &TLI, unsigned Width, MVT VVT,
8309 MVT& EVT, MVT& VecEVT) {
8310 // We start with the preferred width, make it a power of 2 and see if
8311 // we can find a vector type of that width. If not, we reduce it by
8312 // another power of 2. If we have widen the type, a vector of bytes should
8314 assert(TLI.isTypeLegal(VVT));
8315 unsigned EWidth = Width + 1;
8318 EWidth = (1 << Log2_32(EWidth-1));
8319 EVT = MVT::getIntegerVT(EWidth);
8320 unsigned NumEVT = VVT.getSizeInBits()/EWidth;
8321 VecEVT = MVT::getVectorVT(EVT, NumEVT);
8322 } while (!TLI.isTypeLegal(VecEVT) ||
8323 VVT.getSizeInBits() != VecEVT.getSizeInBits());
8326 SDValue SelectionDAGLegalize::genWidenVectorLoads(SDValueVector& LdChain,
8335 // We assume that we have good rules to handle loading power of two loads so
8336 // we break down the operations to power of 2 loads. The strategy is to
8337 // load the largest power of 2 that we can easily transform to a legal vector
8338 // and then insert into that vector, and the cast the result into the legal
8339 // vector that we want. This avoids unnecessary stack converts.
8340 // TODO: If the Ldwidth is legal, alignment is the same as the LdWidth, and
8341 // the load is nonvolatile, we an use a wider load for the value.
8342 // Find a vector length we can load a large chunk
8345 FindWidenVecType(TLI, LdWidth, ResType, EVT, VecEVT);
8346 EVTWidth = EVT.getSizeInBits();
8348 SDValue LdOp = DAG.getLoad(EVT, Chain, BasePtr, SV, SVOffset,
8349 isVolatile, Alignment);
8350 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, VecEVT, LdOp);
8351 LdChain.push_back(LdOp.getValue(1));
8353 // Check if we can load the element with one instruction
8354 if (LdWidth == EVTWidth) {
8355 return DAG.getNode(ISD::BIT_CONVERT, ResType, VecOp);
8358 // The vector element order is endianness dependent.
8360 LdWidth -= EVTWidth;
8361 unsigned Offset = 0;
8363 while (LdWidth > 0) {
8364 unsigned Increment = EVTWidth / 8;
8365 Offset += Increment;
8366 BasePtr = DAG.getNode(ISD::ADD, BasePtr.getValueType(), BasePtr,
8367 DAG.getIntPtrConstant(Increment));
8369 if (LdWidth < EVTWidth) {
8370 // Our current type we are using is too large, use a smaller size by
8371 // using a smaller power of 2
8372 unsigned oEVTWidth = EVTWidth;
8373 FindWidenVecType(TLI, LdWidth, ResType, EVT, VecEVT);
8374 EVTWidth = EVT.getSizeInBits();
8375 // Readjust position and vector position based on new load type
8376 Idx = Idx * (oEVTWidth/EVTWidth);
8377 VecOp = DAG.getNode(ISD::BIT_CONVERT, VecEVT, VecOp);
8380 SDValue LdOp = DAG.getLoad(EVT, Chain, BasePtr, SV,
8381 SVOffset+Offset, isVolatile,
8382 MinAlign(Alignment, Offset));
8383 LdChain.push_back(LdOp.getValue(1));
8384 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, VecEVT, VecOp, LdOp,
8385 DAG.getIntPtrConstant(Idx++));
8387 LdWidth -= EVTWidth;
8390 return DAG.getNode(ISD::BIT_CONVERT, ResType, VecOp);
8393 bool SelectionDAGLegalize::LoadWidenVectorOp(SDValue& Result,
8397 // TODO: Add support for ConcatVec and the ability to load many vector
8398 // types (e.g., v4i8). This will not work when a vector register
8399 // to memory mapping is strange (e.g., vector elements are not
8400 // stored in some sequential order).
8402 // It must be true that the widen vector type is bigger than where
8403 // we need to load from.
8404 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
8405 MVT LdVT = LD->getMemoryVT();
8406 assert(LdVT.isVector() && NVT.isVector());
8407 assert(LdVT.getVectorElementType() == NVT.getVectorElementType());
8410 SDValue Chain = LD->getChain();
8411 SDValue BasePtr = LD->getBasePtr();
8412 int SVOffset = LD->getSrcValueOffset();
8413 unsigned Alignment = LD->getAlignment();
8414 bool isVolatile = LD->isVolatile();
8415 const Value *SV = LD->getSrcValue();
8416 unsigned int LdWidth = LdVT.getSizeInBits();
8418 // Load value as a large register
8419 SDValueVector LdChain;
8420 Result = genWidenVectorLoads(LdChain, Chain, BasePtr, SV, SVOffset,
8421 Alignment, isVolatile, LdWidth, NVT);
8423 if (LdChain.size() == 1) {
8428 TFOp=DAG.getNode(ISD::TokenFactor, MVT::Other, &LdChain[0], LdChain.size());
8434 void SelectionDAGLegalize::genWidenVectorStores(SDValueVector& StChain,
8443 // Breaks the stores into a series of power of 2 width stores. For any
8444 // width, we convert the vector to the vector of element size that we
8445 // want to store. This avoids requiring a stack convert.
8447 // Find a width of the element type we can store with
8448 MVT VVT = ValOp.getValueType();
8451 FindWidenVecType(TLI, StWidth, VVT, EVT, VecEVT);
8452 EVTWidth = EVT.getSizeInBits();
8454 SDValue VecOp = DAG.getNode(ISD::BIT_CONVERT, VecEVT, ValOp);
8455 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EVT, VecOp,
8456 DAG.getIntPtrConstant(0));
8457 SDValue StOp = DAG.getStore(Chain, EOp, BasePtr, SV, SVOffset,
8458 isVolatile, Alignment);
8459 StChain.push_back(StOp);
8461 // Check if we are done
8462 if (StWidth == EVTWidth) {
8467 StWidth -= EVTWidth;
8468 unsigned Offset = 0;
8470 while (StWidth > 0) {
8471 unsigned Increment = EVTWidth / 8;
8472 Offset += Increment;
8473 BasePtr = DAG.getNode(ISD::ADD, BasePtr.getValueType(), BasePtr,
8474 DAG.getIntPtrConstant(Increment));
8476 if (StWidth < EVTWidth) {
8477 // Our current type we are using is too large, use a smaller size by
8478 // using a smaller power of 2
8479 unsigned oEVTWidth = EVTWidth;
8480 FindWidenVecType(TLI, StWidth, VVT, EVT, VecEVT);
8481 EVTWidth = EVT.getSizeInBits();
8482 // Readjust position and vector position based on new load type
8483 Idx = Idx * (oEVTWidth/EVTWidth);
8484 VecOp = DAG.getNode(ISD::BIT_CONVERT, VecEVT, VecOp);
8487 EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EVT, VecOp,
8488 DAG.getIntPtrConstant(Idx++));
8489 StChain.push_back(DAG.getStore(Chain, EOp, BasePtr, SV,
8490 SVOffset + Offset, isVolatile,
8491 MinAlign(Alignment, Offset)));
8492 StWidth -= EVTWidth;
8497 SDValue SelectionDAGLegalize::StoreWidenVectorOp(StoreSDNode *ST,
8500 // TODO: It might be cleaner if we can use SplitVector and have more legal
8501 // vector types that can be stored into memory (e.g., v4xi8 can
8502 // be stored as a word). This will not work when a vector register
8503 // to memory mapping is strange (e.g., vector elements are not
8504 // stored in some sequential order).
8506 MVT StVT = ST->getMemoryVT();
8507 SDValue ValOp = ST->getValue();
8509 // Check if we have widen this node with another value
8510 std::map<SDValue, SDValue>::iterator I = WidenNodes.find(ValOp);
8511 if (I != WidenNodes.end())
8514 MVT VVT = ValOp.getValueType();
8516 // It must be true that we the widen vector type is bigger than where
8517 // we need to store.
8518 assert(StVT.isVector() && VVT.isVector());
8519 assert(StVT.bitsLT(VVT));
8520 assert(StVT.getVectorElementType() == VVT.getVectorElementType());
8523 SDValueVector StChain;
8524 genWidenVectorStores(StChain, Chain, BasePtr, ST->getSrcValue(),
8525 ST->getSrcValueOffset(), ST->getAlignment(),
8526 ST->isVolatile(), ValOp, StVT.getSizeInBits());
8527 if (StChain.size() == 1)
8530 return DAG.getNode(ISD::TokenFactor, MVT::Other,&StChain[0],StChain.size());
8534 // SelectionDAG::Legalize - This is the entry point for the file.
8536 void SelectionDAG::Legalize(bool TypesNeedLegalizing) {
8537 /// run - This is the main entry point to this class.
8539 SelectionDAGLegalize(*this, TypesNeedLegalizing).LegalizeDAG();