1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/ADT/SmallPtrSet.h"
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/ADT/Triple.h"
18 #include "llvm/CodeGen/Analysis.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineJumpTableInfo.h"
21 #include "llvm/DebugInfo.h"
22 #include "llvm/IR/CallingConv.h"
23 #include "llvm/IR/Constants.h"
24 #include "llvm/IR/DataLayout.h"
25 #include "llvm/IR/DerivedTypes.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/IR/LLVMContext.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/MathExtras.h"
31 #include "llvm/Support/raw_ostream.h"
32 #include "llvm/Target/TargetFrameLowering.h"
33 #include "llvm/Target/TargetLowering.h"
34 #include "llvm/Target/TargetMachine.h"
37 //===----------------------------------------------------------------------===//
38 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
39 /// hacks on it until the target machine can handle it. This involves
40 /// eliminating value sizes the machine cannot handle (promoting small sizes to
41 /// large sizes or splitting up large values into small values) as well as
42 /// eliminating operations the machine cannot handle.
44 /// This code also does a small amount of optimization and recognition of idioms
45 /// as part of its processing. For example, if a target does not support a
46 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
47 /// will attempt merge setcc and brc instructions into brcc's.
50 class SelectionDAGLegalize : public SelectionDAG::DAGUpdateListener {
51 const TargetMachine &TM;
52 const TargetLowering &TLI;
55 /// LegalizePosition - The iterator for walking through the node list.
56 SelectionDAG::allnodes_iterator LegalizePosition;
58 /// LegalizedNodes - The set of nodes which have already been legalized.
59 SmallPtrSet<SDNode *, 16> LegalizedNodes;
61 EVT getSetCCResultType(EVT VT) const {
62 return TLI.getSetCCResultType(*DAG.getContext(), VT);
65 // Libcall insertion helpers.
68 explicit SelectionDAGLegalize(SelectionDAG &DAG);
73 /// LegalizeOp - Legalizes the given operation.
74 void LegalizeOp(SDNode *Node);
76 SDValue OptimizeFloatStore(StoreSDNode *ST);
78 void LegalizeLoadOps(SDNode *Node);
79 void LegalizeStoreOps(SDNode *Node);
81 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
82 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
83 /// is necessary to spill the vector being inserted into to memory, perform
84 /// the insert there, and then read the result back.
85 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
86 SDValue Idx, SDLoc dl);
87 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
88 SDValue Idx, SDLoc dl);
90 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
91 /// performs the same shuffe in terms of order or result bytes, but on a type
92 /// whose vector element type is narrower than the original shuffle type.
93 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
94 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl,
95 SDValue N1, SDValue N2,
96 ArrayRef<int> Mask) const;
98 bool LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
99 bool &NeedInvert, SDLoc dl);
101 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
102 SDValue ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops,
103 unsigned NumOps, bool isSigned, SDLoc dl);
105 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
106 SDNode *Node, bool isSigned);
107 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
108 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
109 RTLIB::Libcall Call_F128,
110 RTLIB::Libcall Call_PPCF128);
111 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
112 RTLIB::Libcall Call_I8,
113 RTLIB::Libcall Call_I16,
114 RTLIB::Libcall Call_I32,
115 RTLIB::Libcall Call_I64,
116 RTLIB::Libcall Call_I128);
117 void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
118 void ExpandSinCosLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
120 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, SDLoc dl);
121 SDValue ExpandBUILD_VECTOR(SDNode *Node);
122 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
123 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
124 SmallVectorImpl<SDValue> &Results);
125 SDValue ExpandFCOPYSIGN(SDNode *Node);
126 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
128 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
130 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
133 SDValue ExpandBSWAP(SDValue Op, SDLoc dl);
134 SDValue ExpandBitCount(unsigned Opc, SDValue Op, SDLoc dl);
136 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
137 SDValue ExpandInsertToVectorThroughStack(SDValue Op);
138 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
140 SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP);
142 std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node);
144 void ExpandNode(SDNode *Node);
145 void PromoteNode(SDNode *Node);
147 void ForgetNode(SDNode *N) {
148 LegalizedNodes.erase(N);
149 if (LegalizePosition == SelectionDAG::allnodes_iterator(N))
154 // DAGUpdateListener implementation.
155 virtual void NodeDeleted(SDNode *N, SDNode *E) {
158 virtual void NodeUpdated(SDNode *N) {}
160 // Node replacement helpers
161 void ReplacedNode(SDNode *N) {
162 if (N->use_empty()) {
163 DAG.RemoveDeadNode(N);
168 void ReplaceNode(SDNode *Old, SDNode *New) {
169 DAG.ReplaceAllUsesWith(Old, New);
172 void ReplaceNode(SDValue Old, SDValue New) {
173 DAG.ReplaceAllUsesWith(Old, New);
174 ReplacedNode(Old.getNode());
176 void ReplaceNode(SDNode *Old, const SDValue *New) {
177 DAG.ReplaceAllUsesWith(Old, New);
183 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
184 /// performs the same shuffe in terms of order or result bytes, but on a type
185 /// whose vector element type is narrower than the original shuffle type.
186 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
188 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl,
189 SDValue N1, SDValue N2,
190 ArrayRef<int> Mask) const {
191 unsigned NumMaskElts = VT.getVectorNumElements();
192 unsigned NumDestElts = NVT.getVectorNumElements();
193 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
195 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
197 if (NumEltsGrowth == 1)
198 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
200 SmallVector<int, 8> NewMask;
201 for (unsigned i = 0; i != NumMaskElts; ++i) {
203 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
205 NewMask.push_back(-1);
207 NewMask.push_back(Idx * NumEltsGrowth + j);
210 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
211 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
212 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
215 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
216 : SelectionDAG::DAGUpdateListener(dag),
217 TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()),
221 void SelectionDAGLegalize::LegalizeDAG() {
222 DAG.AssignTopologicalOrder();
224 // Visit all the nodes. We start in topological order, so that we see
225 // nodes with their original operands intact. Legalization can produce
226 // new nodes which may themselves need to be legalized. Iterate until all
227 // nodes have been legalized.
229 bool AnyLegalized = false;
230 for (LegalizePosition = DAG.allnodes_end();
231 LegalizePosition != DAG.allnodes_begin(); ) {
234 SDNode *N = LegalizePosition;
235 if (LegalizedNodes.insert(N)) {
245 // Remove dead nodes now.
246 DAG.RemoveDeadNodes();
249 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
250 /// a load from the constant pool.
252 SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) {
256 // If a FP immediate is precise when represented as a float and if the
257 // target can do an extending load from float to double, we put it into
258 // the constant pool as a float, even if it's is statically typed as a
259 // double. This shrinks FP constants and canonicalizes them for targets where
260 // an FP extending load is the same cost as a normal load (such as on the x87
261 // fp stack or PPC FP unit).
262 EVT VT = CFP->getValueType(0);
263 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
265 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
266 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
267 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
272 while (SVT != MVT::f32) {
273 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
274 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) &&
275 // Only do this if the target has a native EXTLOAD instruction from
277 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
278 TLI.ShouldShrinkFPConstant(OrigVT)) {
279 Type *SType = SVT.getTypeForEVT(*DAG.getContext());
280 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
286 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
287 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
290 DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT,
292 CPIdx, MachinePointerInfo::getConstantPool(),
293 VT, false, false, Alignment);
297 DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
298 MachinePointerInfo::getConstantPool(), false, false, false,
303 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
304 static void ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
305 const TargetLowering &TLI,
306 SelectionDAGLegalize *DAGLegalize) {
307 assert(ST->getAddressingMode() == ISD::UNINDEXED &&
308 "unaligned indexed stores not implemented!");
309 SDValue Chain = ST->getChain();
310 SDValue Ptr = ST->getBasePtr();
311 SDValue Val = ST->getValue();
312 EVT VT = Val.getValueType();
313 int Alignment = ST->getAlignment();
314 unsigned AS = ST->getAddressSpace();
317 if (ST->getMemoryVT().isFloatingPoint() ||
318 ST->getMemoryVT().isVector()) {
319 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
320 if (TLI.isTypeLegal(intVT)) {
321 // Expand to a bitconvert of the value to the integer type of the
322 // same size, then a (misaligned) int store.
323 // FIXME: Does not handle truncating floating point stores!
324 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
325 Result = DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
326 ST->isVolatile(), ST->isNonTemporal(), Alignment);
327 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
330 // Do a (aligned) store to a stack slot, then copy from the stack slot
331 // to the final destination using (unaligned) integer loads and stores.
332 EVT StoredVT = ST->getMemoryVT();
334 TLI.getRegisterType(*DAG.getContext(),
335 EVT::getIntegerVT(*DAG.getContext(),
336 StoredVT.getSizeInBits()));
337 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
338 unsigned RegBytes = RegVT.getSizeInBits() / 8;
339 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
341 // Make sure the stack slot is also aligned for the register type.
342 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
344 // Perform the original store, only redirected to the stack slot.
345 SDValue Store = DAG.getTruncStore(Chain, dl,
346 Val, StackPtr, MachinePointerInfo(),
347 StoredVT, false, false, 0);
348 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy(AS));
349 SmallVector<SDValue, 8> Stores;
352 // Do all but one copies using the full register width.
353 for (unsigned i = 1; i < NumRegs; i++) {
354 // Load one integer register's worth from the stack slot.
355 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr,
356 MachinePointerInfo(),
357 false, false, false, 0);
358 // Store it to the final location. Remember the store.
359 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
360 ST->getPointerInfo().getWithOffset(Offset),
361 ST->isVolatile(), ST->isNonTemporal(),
362 MinAlign(ST->getAlignment(), Offset)));
363 // Increment the pointers.
365 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
367 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
370 // The last store may be partial. Do a truncating store. On big-endian
371 // machines this requires an extending load from the stack slot to ensure
372 // that the bits are in the right place.
373 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
374 8 * (StoredBytes - Offset));
376 // Load from the stack slot.
377 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
378 MachinePointerInfo(),
379 MemVT, false, false, 0);
381 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
383 .getWithOffset(Offset),
384 MemVT, ST->isVolatile(),
386 MinAlign(ST->getAlignment(), Offset),
388 // The order of the stores doesn't matter - say it with a TokenFactor.
390 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
392 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
395 assert(ST->getMemoryVT().isInteger() &&
396 !ST->getMemoryVT().isVector() &&
397 "Unaligned store of unknown type.");
398 // Get the half-size VT
399 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext());
400 int NumBits = NewStoredVT.getSizeInBits();
401 int IncrementSize = NumBits / 8;
403 // Divide the stored value in two parts.
404 SDValue ShiftAmount = DAG.getConstant(NumBits,
405 TLI.getShiftAmountTy(Val.getValueType()));
407 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
409 // Store the two parts
410 SDValue Store1, Store2;
411 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
412 ST->getPointerInfo(), NewStoredVT,
413 ST->isVolatile(), ST->isNonTemporal(), Alignment);
415 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
416 DAG.getConstant(IncrementSize, TLI.getPointerTy(AS)));
417 Alignment = MinAlign(Alignment, IncrementSize);
418 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
419 ST->getPointerInfo().getWithOffset(IncrementSize),
420 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(),
421 Alignment, ST->getTBAAInfo());
424 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
425 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
428 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
430 ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
431 const TargetLowering &TLI,
432 SDValue &ValResult, SDValue &ChainResult) {
433 assert(LD->getAddressingMode() == ISD::UNINDEXED &&
434 "unaligned indexed loads not implemented!");
435 SDValue Chain = LD->getChain();
436 SDValue Ptr = LD->getBasePtr();
437 EVT VT = LD->getValueType(0);
438 EVT LoadedVT = LD->getMemoryVT();
440 if (VT.isFloatingPoint() || VT.isVector()) {
441 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
442 if (TLI.isTypeLegal(intVT) && TLI.isTypeLegal(LoadedVT)) {
443 // Expand to a (misaligned) integer load of the same size,
444 // then bitconvert to floating point or vector.
445 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr,
446 LD->getMemOperand());
447 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad);
449 Result = DAG.getNode(VT.isFloatingPoint() ? ISD::FP_EXTEND :
450 ISD::ANY_EXTEND, dl, VT, Result);
457 // Copy the value to a (aligned) stack slot using (unaligned) integer
458 // loads and stores, then do a (aligned) load from the stack slot.
459 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
460 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
461 unsigned RegBytes = RegVT.getSizeInBits() / 8;
462 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
464 // Make sure the stack slot is also aligned for the register type.
465 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
467 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
468 SmallVector<SDValue, 8> Stores;
469 SDValue StackPtr = StackBase;
472 // Do all but one copies using the full register width.
473 for (unsigned i = 1; i < NumRegs; i++) {
474 // Load one integer register's worth from the original location.
475 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr,
476 LD->getPointerInfo().getWithOffset(Offset),
477 LD->isVolatile(), LD->isNonTemporal(),
479 MinAlign(LD->getAlignment(), Offset),
481 // Follow the load with a store to the stack slot. Remember the store.
482 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
483 MachinePointerInfo(), false, false, 0));
484 // Increment the pointers.
486 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
487 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
491 // The last copy may be partial. Do an extending load.
492 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
493 8 * (LoadedBytes - Offset));
494 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
495 LD->getPointerInfo().getWithOffset(Offset),
496 MemVT, LD->isVolatile(),
498 MinAlign(LD->getAlignment(), Offset),
500 // Follow the load with a store to the stack slot. Remember the store.
501 // On big-endian machines this requires a truncating store to ensure
502 // that the bits end up in the right place.
503 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
504 MachinePointerInfo(), MemVT,
507 // The order of the stores doesn't matter - say it with a TokenFactor.
508 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
511 // Finally, perform the original load only redirected to the stack slot.
512 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
513 MachinePointerInfo(), LoadedVT, false, false, 0);
515 // Callers expect a MERGE_VALUES node.
520 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
521 "Unaligned load of unsupported type.");
523 // Compute the new VT that is half the size of the old one. This is an
525 unsigned NumBits = LoadedVT.getSizeInBits();
527 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
530 unsigned Alignment = LD->getAlignment();
531 unsigned IncrementSize = NumBits / 8;
532 ISD::LoadExtType HiExtType = LD->getExtensionType();
534 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
535 if (HiExtType == ISD::NON_EXTLOAD)
536 HiExtType = ISD::ZEXTLOAD;
538 // Load the value in two parts
540 if (TLI.isLittleEndian()) {
541 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
542 NewLoadedVT, LD->isVolatile(),
543 LD->isNonTemporal(), Alignment, LD->getTBAAInfo());
544 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
545 DAG.getConstant(IncrementSize, Ptr.getValueType()));
546 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr,
547 LD->getPointerInfo().getWithOffset(IncrementSize),
548 NewLoadedVT, LD->isVolatile(),
549 LD->isNonTemporal(), MinAlign(Alignment, IncrementSize),
552 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(),
553 NewLoadedVT, LD->isVolatile(),
554 LD->isNonTemporal(), Alignment, LD->getTBAAInfo());
555 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
556 DAG.getConstant(IncrementSize, Ptr.getValueType()));
557 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
558 LD->getPointerInfo().getWithOffset(IncrementSize),
559 NewLoadedVT, LD->isVolatile(),
560 LD->isNonTemporal(), MinAlign(Alignment, IncrementSize),
564 // aggregate the two parts
565 SDValue ShiftAmount = DAG.getConstant(NumBits,
566 TLI.getShiftAmountTy(Hi.getValueType()));
567 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
568 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
570 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
577 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
578 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
579 /// is necessary to spill the vector being inserted into to memory, perform
580 /// the insert there, and then read the result back.
581 SDValue SelectionDAGLegalize::
582 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
588 // If the target doesn't support this, we have to spill the input vector
589 // to a temporary stack slot, update the element, then reload it. This is
590 // badness. We could also load the value into a vector register (either
591 // with a "move to register" or "extload into register" instruction, then
592 // permute it into place, if the idx is a constant and if the idx is
593 // supported by the target.
594 EVT VT = Tmp1.getValueType();
595 EVT EltVT = VT.getVectorElementType();
596 EVT IdxVT = Tmp3.getValueType();
597 EVT PtrVT = TLI.getPointerTy();
598 SDValue StackPtr = DAG.CreateStackTemporary(VT);
600 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
603 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
604 MachinePointerInfo::getFixedStack(SPFI),
607 // Truncate or zero extend offset to target pointer type.
608 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
609 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
610 // Add the offset to the index.
611 unsigned EltSize = EltVT.getSizeInBits()/8;
612 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
613 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
614 // Store the scalar value.
615 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT,
617 // Load the updated vector.
618 return DAG.getLoad(VT, dl, Ch, StackPtr,
619 MachinePointerInfo::getFixedStack(SPFI), false, false,
624 SDValue SelectionDAGLegalize::
625 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, SDLoc dl) {
626 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
627 // SCALAR_TO_VECTOR requires that the type of the value being inserted
628 // match the element type of the vector being created, except for
629 // integers in which case the inserted value can be over width.
630 EVT EltVT = Vec.getValueType().getVectorElementType();
631 if (Val.getValueType() == EltVT ||
632 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
633 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
634 Vec.getValueType(), Val);
636 unsigned NumElts = Vec.getValueType().getVectorNumElements();
637 // We generate a shuffle of InVec and ScVec, so the shuffle mask
638 // should be 0,1,2,3,4,5... with the appropriate element replaced with
640 SmallVector<int, 8> ShufOps;
641 for (unsigned i = 0; i != NumElts; ++i)
642 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
644 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
648 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
651 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
652 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
653 // FIXME: We shouldn't do this for TargetConstantFP's.
654 // FIXME: move this to the DAG Combiner! Note that we can't regress due
655 // to phase ordering between legalized code and the dag combiner. This
656 // probably means that we need to integrate dag combiner and legalizer
658 // We generally can't do this one for long doubles.
659 SDValue Chain = ST->getChain();
660 SDValue Ptr = ST->getBasePtr();
661 unsigned Alignment = ST->getAlignment();
662 bool isVolatile = ST->isVolatile();
663 bool isNonTemporal = ST->isNonTemporal();
664 const MDNode *TBAAInfo = ST->getTBAAInfo();
666 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
667 if (CFP->getValueType(0) == MVT::f32 &&
668 TLI.isTypeLegal(MVT::i32)) {
669 SDValue Con = DAG.getConstant(CFP->getValueAPF().
670 bitcastToAPInt().zextOrTrunc(32),
672 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
673 isVolatile, isNonTemporal, Alignment, TBAAInfo);
676 if (CFP->getValueType(0) == MVT::f64) {
677 // If this target supports 64-bit registers, do a single 64-bit store.
678 if (TLI.isTypeLegal(MVT::i64)) {
679 SDValue Con = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
680 zextOrTrunc(64), MVT::i64);
681 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
682 isVolatile, isNonTemporal, Alignment, TBAAInfo);
685 if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) {
686 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
687 // stores. If the target supports neither 32- nor 64-bits, this
688 // xform is certainly not worth it.
689 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
690 SDValue Lo = DAG.getConstant(IntVal.trunc(32), MVT::i32);
691 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
692 if (TLI.isBigEndian()) std::swap(Lo, Hi);
694 Lo = DAG.getStore(Chain, dl, Lo, Ptr, ST->getPointerInfo(), isVolatile,
695 isNonTemporal, Alignment, TBAAInfo);
696 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
697 DAG.getConstant(4, Ptr.getValueType()));
698 Hi = DAG.getStore(Chain, dl, Hi, Ptr,
699 ST->getPointerInfo().getWithOffset(4),
700 isVolatile, isNonTemporal, MinAlign(Alignment, 4U),
703 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
707 return SDValue(0, 0);
710 void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
711 StoreSDNode *ST = cast<StoreSDNode>(Node);
712 SDValue Chain = ST->getChain();
713 SDValue Ptr = ST->getBasePtr();
716 unsigned Alignment = ST->getAlignment();
717 bool isVolatile = ST->isVolatile();
718 bool isNonTemporal = ST->isNonTemporal();
719 const MDNode *TBAAInfo = ST->getTBAAInfo();
721 if (!ST->isTruncatingStore()) {
722 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
723 ReplaceNode(ST, OptStore);
728 SDValue Value = ST->getValue();
729 MVT VT = Value.getSimpleValueType();
730 switch (TLI.getOperationAction(ISD::STORE, VT)) {
731 default: llvm_unreachable("This action is not supported yet!");
732 case TargetLowering::Legal: {
733 // If this is an unaligned store and the target doesn't support it,
735 unsigned AS = ST->getAddressSpace();
736 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT(), AS)) {
737 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
738 unsigned ABIAlignment= TLI.getDataLayout()->getABITypeAlignment(Ty);
739 if (ST->getAlignment() < ABIAlignment)
740 ExpandUnalignedStore(cast<StoreSDNode>(Node),
745 case TargetLowering::Custom: {
746 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
748 ReplaceNode(SDValue(Node, 0), Res);
751 case TargetLowering::Promote: {
752 MVT NVT = TLI.getTypeToPromoteTo(ISD::STORE, VT);
753 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
754 "Can only promote stores to same size type");
755 Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value);
757 DAG.getStore(Chain, dl, Value, Ptr,
758 ST->getPointerInfo(), isVolatile,
759 isNonTemporal, Alignment, TBAAInfo);
760 ReplaceNode(SDValue(Node, 0), Result);
767 SDValue Value = ST->getValue();
769 EVT StVT = ST->getMemoryVT();
770 unsigned StWidth = StVT.getSizeInBits();
772 if (StWidth != StVT.getStoreSizeInBits()) {
773 // Promote to a byte-sized store with upper bits zero if not
774 // storing an integral number of bytes. For example, promote
775 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
776 EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
777 StVT.getStoreSizeInBits());
778 Value = DAG.getZeroExtendInReg(Value, dl, StVT);
780 DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
781 NVT, isVolatile, isNonTemporal, Alignment,
783 ReplaceNode(SDValue(Node, 0), Result);
784 } else if (StWidth & (StWidth - 1)) {
785 // If not storing a power-of-2 number of bits, expand as two stores.
786 assert(!StVT.isVector() && "Unsupported truncstore!");
787 unsigned RoundWidth = 1 << Log2_32(StWidth);
788 assert(RoundWidth < StWidth);
789 unsigned ExtraWidth = StWidth - RoundWidth;
790 assert(ExtraWidth < RoundWidth);
791 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
792 "Store size not an integral number of bytes!");
793 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
794 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
796 unsigned IncrementSize;
798 if (TLI.isLittleEndian()) {
799 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
800 // Store the bottom RoundWidth bits.
801 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
803 isVolatile, isNonTemporal, Alignment,
806 // Store the remaining ExtraWidth bits.
807 IncrementSize = RoundWidth / 8;
808 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
809 DAG.getConstant(IncrementSize, Ptr.getValueType()));
810 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
811 DAG.getConstant(RoundWidth,
812 TLI.getShiftAmountTy(Value.getValueType())));
813 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr,
814 ST->getPointerInfo().getWithOffset(IncrementSize),
815 ExtraVT, isVolatile, isNonTemporal,
816 MinAlign(Alignment, IncrementSize), TBAAInfo);
818 // Big endian - avoid unaligned stores.
819 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
820 // Store the top RoundWidth bits.
821 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
822 DAG.getConstant(ExtraWidth,
823 TLI.getShiftAmountTy(Value.getValueType())));
824 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, ST->getPointerInfo(),
825 RoundVT, isVolatile, isNonTemporal, Alignment,
828 // Store the remaining ExtraWidth bits.
829 IncrementSize = RoundWidth / 8;
830 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
831 DAG.getConstant(IncrementSize, Ptr.getValueType()));
832 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr,
833 ST->getPointerInfo().getWithOffset(IncrementSize),
834 ExtraVT, isVolatile, isNonTemporal,
835 MinAlign(Alignment, IncrementSize), TBAAInfo);
838 // The order of the stores doesn't matter.
839 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
840 ReplaceNode(SDValue(Node, 0), Result);
842 switch (TLI.getTruncStoreAction(ST->getValue().getSimpleValueType(),
843 StVT.getSimpleVT())) {
844 default: llvm_unreachable("This action is not supported yet!");
845 case TargetLowering::Legal: {
846 unsigned AS = ST->getAddressSpace();
847 // If this is an unaligned store and the target doesn't support it,
849 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT(), AS)) {
850 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
851 unsigned ABIAlignment= TLI.getDataLayout()->getABITypeAlignment(Ty);
852 if (ST->getAlignment() < ABIAlignment)
853 ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this);
857 case TargetLowering::Custom: {
858 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
860 ReplaceNode(SDValue(Node, 0), Res);
863 case TargetLowering::Expand:
864 assert(!StVT.isVector() &&
865 "Vector Stores are handled in LegalizeVectorOps");
867 // TRUNCSTORE:i16 i32 -> STORE i16
868 assert(TLI.isTypeLegal(StVT) &&
869 "Do not know how to expand this store!");
870 Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value);
872 DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
873 isVolatile, isNonTemporal, Alignment, TBAAInfo);
874 ReplaceNode(SDValue(Node, 0), Result);
881 void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
882 LoadSDNode *LD = cast<LoadSDNode>(Node);
883 SDValue Chain = LD->getChain(); // The chain.
884 SDValue Ptr = LD->getBasePtr(); // The base pointer.
885 SDValue Value; // The value returned by the load op.
888 ISD::LoadExtType ExtType = LD->getExtensionType();
889 if (ExtType == ISD::NON_EXTLOAD) {
890 MVT VT = Node->getSimpleValueType(0);
891 SDValue RVal = SDValue(Node, 0);
892 SDValue RChain = SDValue(Node, 1);
894 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
895 default: llvm_unreachable("This action is not supported yet!");
896 case TargetLowering::Legal: {
897 unsigned AS = LD->getAddressSpace();
898 // If this is an unaligned load and the target doesn't support it,
900 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT(), AS)) {
901 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
902 unsigned ABIAlignment =
903 TLI.getDataLayout()->getABITypeAlignment(Ty);
904 if (LD->getAlignment() < ABIAlignment){
905 ExpandUnalignedLoad(cast<LoadSDNode>(Node), DAG, TLI, RVal, RChain);
910 case TargetLowering::Custom: {
911 SDValue Res = TLI.LowerOperation(RVal, DAG);
914 RChain = Res.getValue(1);
918 case TargetLowering::Promote: {
919 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
920 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
921 "Can only promote loads to same size type");
923 SDValue Res = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getMemOperand());
924 RVal = DAG.getNode(ISD::BITCAST, dl, VT, Res);
925 RChain = Res.getValue(1);
929 if (RChain.getNode() != Node) {
930 assert(RVal.getNode() != Node && "Load must be completely replaced");
931 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), RVal);
932 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), RChain);
938 EVT SrcVT = LD->getMemoryVT();
939 unsigned SrcWidth = SrcVT.getSizeInBits();
940 unsigned Alignment = LD->getAlignment();
941 bool isVolatile = LD->isVolatile();
942 bool isNonTemporal = LD->isNonTemporal();
943 const MDNode *TBAAInfo = LD->getTBAAInfo();
945 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
946 // Some targets pretend to have an i1 loading operation, and actually
947 // load an i8. This trick is correct for ZEXTLOAD because the top 7
948 // bits are guaranteed to be zero; it helps the optimizers understand
949 // that these bits are zero. It is also useful for EXTLOAD, since it
950 // tells the optimizers that those bits are undefined. It would be
951 // nice to have an effective generic way of getting these benefits...
952 // Until such a way is found, don't insist on promoting i1 here.
954 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
955 // Promote to a byte-sized load if not loading an integral number of
956 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
957 unsigned NewWidth = SrcVT.getStoreSizeInBits();
958 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
961 // The extra bits are guaranteed to be zero, since we stored them that
962 // way. A zext load from NVT thus automatically gives zext from SrcVT.
964 ISD::LoadExtType NewExtType =
965 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
968 DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
969 Chain, Ptr, LD->getPointerInfo(),
970 NVT, isVolatile, isNonTemporal, Alignment, TBAAInfo);
972 Ch = Result.getValue(1); // The chain.
974 if (ExtType == ISD::SEXTLOAD)
975 // Having the top bits zero doesn't help when sign extending.
976 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
977 Result.getValueType(),
978 Result, DAG.getValueType(SrcVT));
979 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
980 // All the top bits are guaranteed to be zero - inform the optimizers.
981 Result = DAG.getNode(ISD::AssertZext, dl,
982 Result.getValueType(), Result,
983 DAG.getValueType(SrcVT));
987 } else if (SrcWidth & (SrcWidth - 1)) {
988 // If not loading a power-of-2 number of bits, expand as two loads.
989 assert(!SrcVT.isVector() && "Unsupported extload!");
990 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
991 assert(RoundWidth < SrcWidth);
992 unsigned ExtraWidth = SrcWidth - RoundWidth;
993 assert(ExtraWidth < RoundWidth);
994 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
995 "Load size not an integral number of bytes!");
996 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
997 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
999 unsigned IncrementSize;
1001 if (TLI.isLittleEndian()) {
1002 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1003 // Load the bottom RoundWidth bits.
1004 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0),
1006 LD->getPointerInfo(), RoundVT, isVolatile,
1007 isNonTemporal, Alignment, TBAAInfo);
1009 // Load the remaining ExtraWidth bits.
1010 IncrementSize = RoundWidth / 8;
1011 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1012 DAG.getConstant(IncrementSize, Ptr.getValueType()));
1013 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
1014 LD->getPointerInfo().getWithOffset(IncrementSize),
1015 ExtraVT, isVolatile, isNonTemporal,
1016 MinAlign(Alignment, IncrementSize), TBAAInfo);
1018 // Build a factor node to remember that this load is independent of
1020 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1023 // Move the top bits to the right place.
1024 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1025 DAG.getConstant(RoundWidth,
1026 TLI.getShiftAmountTy(Hi.getValueType())));
1028 // Join the hi and lo parts.
1029 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1031 // Big endian - avoid unaligned loads.
1032 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1033 // Load the top RoundWidth bits.
1034 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
1035 LD->getPointerInfo(), RoundVT, isVolatile,
1036 isNonTemporal, Alignment, TBAAInfo);
1038 // Load the remaining ExtraWidth bits.
1039 IncrementSize = RoundWidth / 8;
1040 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1041 DAG.getConstant(IncrementSize, Ptr.getValueType()));
1042 Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
1043 dl, Node->getValueType(0), Chain, Ptr,
1044 LD->getPointerInfo().getWithOffset(IncrementSize),
1045 ExtraVT, isVolatile, isNonTemporal,
1046 MinAlign(Alignment, IncrementSize), TBAAInfo);
1048 // Build a factor node to remember that this load is independent of
1050 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1053 // Move the top bits to the right place.
1054 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1055 DAG.getConstant(ExtraWidth,
1056 TLI.getShiftAmountTy(Hi.getValueType())));
1058 // Join the hi and lo parts.
1059 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1064 bool isCustom = false;
1065 switch (TLI.getLoadExtAction(ExtType, SrcVT.getSimpleVT())) {
1066 default: llvm_unreachable("This action is not supported yet!");
1067 case TargetLowering::Custom:
1070 case TargetLowering::Legal: {
1071 Value = SDValue(Node, 0);
1072 Chain = SDValue(Node, 1);
1075 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1076 if (Res.getNode()) {
1078 Chain = Res.getValue(1);
1081 // If this is an unaligned load and the target doesn't support
1083 EVT MemVT = LD->getMemoryVT();
1084 unsigned AS = LD->getAddressSpace();
1085 if (!TLI.allowsUnalignedMemoryAccesses(MemVT, AS)) {
1087 LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1088 unsigned ABIAlignment =
1089 TLI.getDataLayout()->getABITypeAlignment(Ty);
1090 if (LD->getAlignment() < ABIAlignment){
1091 ExpandUnalignedLoad(cast<LoadSDNode>(Node),
1092 DAG, TLI, Value, Chain);
1098 case TargetLowering::Expand:
1099 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) &&
1100 TLI.isTypeLegal(SrcVT)) {
1101 SDValue Load = DAG.getLoad(SrcVT, dl, Chain, Ptr,
1102 LD->getMemOperand());
1106 ExtendOp = (SrcVT.isFloatingPoint() ?
1107 ISD::FP_EXTEND : ISD::ANY_EXTEND);
1109 case ISD::SEXTLOAD: ExtendOp = ISD::SIGN_EXTEND; break;
1110 case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break;
1111 default: llvm_unreachable("Unexpected extend load type!");
1113 Value = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
1114 Chain = Load.getValue(1);
1118 assert(!SrcVT.isVector() &&
1119 "Vector Loads are handled in LegalizeVectorOps");
1121 // FIXME: This does not work for vectors on most targets. Sign-
1122 // and zero-extend operations are currently folded into extending
1123 // loads, whether they are legal or not, and then we end up here
1124 // without any support for legalizing them.
1125 assert(ExtType != ISD::EXTLOAD &&
1126 "EXTLOAD should always be supported!");
1127 // Turn the unsupported load into an EXTLOAD followed by an
1128 // explicit zero/sign extend inreg.
1129 SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl,
1130 Node->getValueType(0),
1132 LD->getMemOperand());
1134 if (ExtType == ISD::SEXTLOAD)
1135 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1136 Result.getValueType(),
1137 Result, DAG.getValueType(SrcVT));
1139 ValRes = DAG.getZeroExtendInReg(Result, dl,
1140 SrcVT.getScalarType());
1142 Chain = Result.getValue(1);
1147 // Since loads produce two values, make sure to remember that we legalized
1149 if (Chain.getNode() != Node) {
1150 assert(Value.getNode() != Node && "Load must be completely replaced");
1151 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Value);
1152 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
1157 /// LegalizeOp - Return a legal replacement for the given operation, with
1158 /// all legal operands.
1159 void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
1160 if (Node->getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
1163 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1164 assert(TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) ==
1165 TargetLowering::TypeLegal &&
1166 "Unexpected illegal type!");
1168 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1169 assert((TLI.getTypeAction(*DAG.getContext(),
1170 Node->getOperand(i).getValueType()) ==
1171 TargetLowering::TypeLegal ||
1172 Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
1173 "Unexpected illegal type!");
1175 // Figure out the correct action; the way to query this varies by opcode
1176 TargetLowering::LegalizeAction Action = TargetLowering::Legal;
1177 bool SimpleFinishLegalizing = true;
1178 switch (Node->getOpcode()) {
1179 case ISD::INTRINSIC_W_CHAIN:
1180 case ISD::INTRINSIC_WO_CHAIN:
1181 case ISD::INTRINSIC_VOID:
1182 case ISD::STACKSAVE:
1183 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1186 Action = TLI.getOperationAction(Node->getOpcode(),
1187 Node->getValueType(0));
1188 if (Action != TargetLowering::Promote)
1189 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1191 case ISD::SINT_TO_FP:
1192 case ISD::UINT_TO_FP:
1193 case ISD::EXTRACT_VECTOR_ELT:
1194 Action = TLI.getOperationAction(Node->getOpcode(),
1195 Node->getOperand(0).getValueType());
1197 case ISD::FP_ROUND_INREG:
1198 case ISD::SIGN_EXTEND_INREG: {
1199 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
1200 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
1203 case ISD::ATOMIC_STORE: {
1204 Action = TLI.getOperationAction(Node->getOpcode(),
1205 Node->getOperand(2).getValueType());
1208 case ISD::SELECT_CC:
1211 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
1212 Node->getOpcode() == ISD::SETCC ? 2 : 1;
1213 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
1214 MVT OpVT = Node->getOperand(CompareOperand).getSimpleValueType();
1215 ISD::CondCode CCCode =
1216 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
1217 Action = TLI.getCondCodeAction(CCCode, OpVT);
1218 if (Action == TargetLowering::Legal) {
1219 if (Node->getOpcode() == ISD::SELECT_CC)
1220 Action = TLI.getOperationAction(Node->getOpcode(),
1221 Node->getValueType(0));
1223 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
1229 // FIXME: Model these properly. LOAD and STORE are complicated, and
1230 // STORE expects the unlegalized operand in some cases.
1231 SimpleFinishLegalizing = false;
1233 case ISD::CALLSEQ_START:
1234 case ISD::CALLSEQ_END:
1235 // FIXME: This shouldn't be necessary. These nodes have special properties
1236 // dealing with the recursive nature of legalization. Removing this
1237 // special case should be done as part of making LegalizeDAG non-recursive.
1238 SimpleFinishLegalizing = false;
1240 case ISD::EXTRACT_ELEMENT:
1241 case ISD::FLT_ROUNDS_:
1249 case ISD::MERGE_VALUES:
1250 case ISD::EH_RETURN:
1251 case ISD::FRAME_TO_ARGS_OFFSET:
1252 case ISD::EH_SJLJ_SETJMP:
1253 case ISD::EH_SJLJ_LONGJMP:
1254 // These operations lie about being legal: when they claim to be legal,
1255 // they should actually be expanded.
1256 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1257 if (Action == TargetLowering::Legal)
1258 Action = TargetLowering::Expand;
1260 case ISD::INIT_TRAMPOLINE:
1261 case ISD::ADJUST_TRAMPOLINE:
1262 case ISD::FRAMEADDR:
1263 case ISD::RETURNADDR:
1264 // These operations lie about being legal: when they claim to be legal,
1265 // they should actually be custom-lowered.
1266 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1267 if (Action == TargetLowering::Legal)
1268 Action = TargetLowering::Custom;
1270 case ISD::DEBUGTRAP:
1271 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1272 if (Action == TargetLowering::Expand) {
1273 // replace ISD::DEBUGTRAP with ISD::TRAP
1275 NewVal = DAG.getNode(ISD::TRAP, SDLoc(Node), Node->getVTList(),
1276 Node->getOperand(0));
1277 ReplaceNode(Node, NewVal.getNode());
1278 LegalizeOp(NewVal.getNode());
1284 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1285 Action = TargetLowering::Legal;
1287 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1292 if (SimpleFinishLegalizing) {
1293 SDNode *NewNode = Node;
1294 switch (Node->getOpcode()) {
1301 // Legalizing shifts/rotates requires adjusting the shift amount
1302 // to the appropriate width.
1303 if (!Node->getOperand(1).getValueType().isVector()) {
1305 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1306 Node->getOperand(1));
1307 HandleSDNode Handle(SAO);
1308 LegalizeOp(SAO.getNode());
1309 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1313 case ISD::SRL_PARTS:
1314 case ISD::SRA_PARTS:
1315 case ISD::SHL_PARTS:
1316 // Legalizing shifts/rotates requires adjusting the shift amount
1317 // to the appropriate width.
1318 if (!Node->getOperand(2).getValueType().isVector()) {
1320 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1321 Node->getOperand(2));
1322 HandleSDNode Handle(SAO);
1323 LegalizeOp(SAO.getNode());
1324 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1325 Node->getOperand(1),
1331 if (NewNode != Node) {
1332 DAG.ReplaceAllUsesWith(Node, NewNode);
1333 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1334 DAG.TransferDbgValues(SDValue(Node, i), SDValue(NewNode, i));
1339 case TargetLowering::Legal:
1341 case TargetLowering::Custom: {
1342 // FIXME: The handling for custom lowering with multiple results is
1344 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1345 if (Res.getNode()) {
1346 SmallVector<SDValue, 8> ResultVals;
1347 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
1349 ResultVals.push_back(Res);
1351 ResultVals.push_back(Res.getValue(i));
1353 if (Res.getNode() != Node || Res.getResNo() != 0) {
1354 DAG.ReplaceAllUsesWith(Node, ResultVals.data());
1355 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1356 DAG.TransferDbgValues(SDValue(Node, i), ResultVals[i]);
1363 case TargetLowering::Expand:
1366 case TargetLowering::Promote:
1372 switch (Node->getOpcode()) {
1379 llvm_unreachable("Do not know how to legalize this operator!");
1381 case ISD::CALLSEQ_START:
1382 case ISD::CALLSEQ_END:
1385 return LegalizeLoadOps(Node);
1388 return LegalizeStoreOps(Node);
1393 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1394 SDValue Vec = Op.getOperand(0);
1395 SDValue Idx = Op.getOperand(1);
1397 // Store the value to a temporary stack slot, then LOAD the returned part.
1398 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1399 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1400 MachinePointerInfo(), false, false, 0);
1402 // Add the offset to the index.
1404 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1405 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1406 DAG.getConstant(EltSize, Idx.getValueType()));
1408 Idx = DAG.getZExtOrTrunc(Idx, dl, TLI.getPointerTy());
1409 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1411 if (Op.getValueType().isVector())
1412 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,MachinePointerInfo(),
1413 false, false, false, 0);
1414 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
1415 MachinePointerInfo(),
1416 Vec.getValueType().getVectorElementType(),
1420 SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
1421 assert(Op.getValueType().isVector() && "Non-vector insert subvector!");
1423 SDValue Vec = Op.getOperand(0);
1424 SDValue Part = Op.getOperand(1);
1425 SDValue Idx = Op.getOperand(2);
1428 // Store the value to a temporary stack slot, then LOAD the returned part.
1430 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1431 int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1432 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1434 // First store the whole vector.
1435 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo,
1438 // Then store the inserted part.
1440 // Add the offset to the index.
1442 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1444 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1445 DAG.getConstant(EltSize, Idx.getValueType()));
1446 Idx = DAG.getZExtOrTrunc(Idx, dl, TLI.getPointerTy());
1448 SDValue SubStackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
1451 // Store the subvector.
1452 Ch = DAG.getStore(DAG.getEntryNode(), dl, Part, SubStackPtr,
1453 MachinePointerInfo(), false, false, 0);
1455 // Finally, load the updated vector.
1456 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo,
1457 false, false, false, 0);
1460 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1461 // We can't handle this case efficiently. Allocate a sufficiently
1462 // aligned object on the stack, store each element into it, then load
1463 // the result as a vector.
1464 // Create the stack frame object.
1465 EVT VT = Node->getValueType(0);
1466 EVT EltVT = VT.getVectorElementType();
1468 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1469 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1470 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1472 // Emit a store of each element to the stack slot.
1473 SmallVector<SDValue, 8> Stores;
1474 unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1475 // Store (in the right endianness) the elements to memory.
1476 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1477 // Ignore undef elements.
1478 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1480 unsigned Offset = TypeByteSize*i;
1482 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
1483 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1485 // If the destination vector element type is narrower than the source
1486 // element type, only store the bits necessary.
1487 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1488 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1489 Node->getOperand(i), Idx,
1490 PtrInfo.getWithOffset(Offset),
1491 EltVT, false, false, 0));
1493 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
1494 Node->getOperand(i), Idx,
1495 PtrInfo.getWithOffset(Offset),
1500 if (!Stores.empty()) // Not all undef elements?
1501 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1502 &Stores[0], Stores.size());
1504 StoreChain = DAG.getEntryNode();
1506 // Result is a load from the stack slot.
1507 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo,
1508 false, false, false, 0);
1511 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
1513 SDValue Tmp1 = Node->getOperand(0);
1514 SDValue Tmp2 = Node->getOperand(1);
1516 // Get the sign bit of the RHS. First obtain a value that has the same
1517 // sign as the sign bit, i.e. negative if and only if the sign bit is 1.
1519 EVT FloatVT = Tmp2.getValueType();
1520 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits());
1521 if (TLI.isTypeLegal(IVT)) {
1522 // Convert to an integer with the same sign bit.
1523 SignBit = DAG.getNode(ISD::BITCAST, dl, IVT, Tmp2);
1525 // Store the float to memory, then load the sign part out as an integer.
1526 MVT LoadTy = TLI.getPointerTy();
1527 // First create a temporary that is aligned for both the load and store.
1528 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1529 // Then store the float to it.
1531 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, MachinePointerInfo(),
1533 if (TLI.isBigEndian()) {
1534 assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1535 // Load out a legal integer with the same sign bit as the float.
1536 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, MachinePointerInfo(),
1537 false, false, false, 0);
1538 } else { // Little endian
1539 SDValue LoadPtr = StackPtr;
1540 // The float may be wider than the integer we are going to load. Advance
1541 // the pointer so that the loaded integer will contain the sign bit.
1542 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits();
1543 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8;
1544 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(), LoadPtr,
1545 DAG.getConstant(ByteOffset, LoadPtr.getValueType()));
1546 // Load a legal integer containing the sign bit.
1547 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(),
1548 false, false, false, 0);
1549 // Move the sign bit to the top bit of the loaded integer.
1550 unsigned BitShift = LoadTy.getSizeInBits() -
1551 (FloatVT.getSizeInBits() - 8 * ByteOffset);
1552 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?");
1554 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit,
1555 DAG.getConstant(BitShift,
1556 TLI.getShiftAmountTy(SignBit.getValueType())));
1559 // Now get the sign bit proper, by seeing whether the value is negative.
1560 SignBit = DAG.getSetCC(dl, getSetCCResultType(SignBit.getValueType()),
1561 SignBit, DAG.getConstant(0, SignBit.getValueType()),
1563 // Get the absolute value of the result.
1564 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1565 // Select between the nabs and abs value based on the sign bit of
1567 return DAG.getSelect(dl, AbsVal.getValueType(), SignBit,
1568 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1572 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1573 SmallVectorImpl<SDValue> &Results) {
1574 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1575 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1576 " not tell us which reg is the stack pointer!");
1578 EVT VT = Node->getValueType(0);
1579 SDValue Tmp1 = SDValue(Node, 0);
1580 SDValue Tmp2 = SDValue(Node, 1);
1581 SDValue Tmp3 = Node->getOperand(2);
1582 SDValue Chain = Tmp1.getOperand(0);
1584 // Chain the dynamic stack allocation so that it doesn't modify the stack
1585 // pointer when other instructions are using the stack.
1586 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
1589 SDValue Size = Tmp2.getOperand(1);
1590 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1591 Chain = SP.getValue(1);
1592 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1593 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
1594 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1595 if (Align > StackAlign)
1596 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
1597 DAG.getConstant(-(uint64_t)Align, VT));
1598 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1600 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1601 DAG.getIntPtrConstant(0, true), SDValue(),
1604 Results.push_back(Tmp1);
1605 Results.push_back(Tmp2);
1608 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
1609 /// condition code CC on the current target.
1611 /// If the SETCC has been legalized using AND / OR, then the legalized node
1612 /// will be stored in LHS. RHS and CC will be set to SDValue(). NeedInvert
1613 /// will be set to false.
1615 /// If the SETCC has been legalized by using getSetCCSwappedOperands(),
1616 /// then the values of LHS and RHS will be swapped, CC will be set to the
1617 /// new condition, and NeedInvert will be set to false.
1619 /// If the SETCC has been legalized using the inverse condcode, then LHS and
1620 /// RHS will be unchanged, CC will set to the inverted condcode, and NeedInvert
1621 /// will be set to true. The caller must invert the result of the SETCC with
1622 /// SelectionDAG::getNOT() or take equivalent action to swap the effect of a
1623 /// true/false result.
1625 /// \returns true if the SetCC has been legalized, false if it hasn't.
1626 bool SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1627 SDValue &LHS, SDValue &RHS,
1631 MVT OpVT = LHS.getSimpleValueType();
1632 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1634 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1635 default: llvm_unreachable("Unknown condition code action!");
1636 case TargetLowering::Legal:
1639 case TargetLowering::Expand: {
1640 ISD::CondCode InvCC = ISD::getSetCCSwappedOperands(CCCode);
1641 if (TLI.isCondCodeLegal(InvCC, OpVT)) {
1642 std::swap(LHS, RHS);
1643 CC = DAG.getCondCode(InvCC);
1646 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1649 default: llvm_unreachable("Don't know how to expand this condition!");
1651 assert(TLI.getCondCodeAction(ISD::SETOEQ, OpVT)
1652 == TargetLowering::Legal
1653 && "If SETO is expanded, SETOEQ must be legal!");
1654 CC1 = ISD::SETOEQ; CC2 = ISD::SETOEQ; Opc = ISD::AND; break;
1656 assert(TLI.getCondCodeAction(ISD::SETUNE, OpVT)
1657 == TargetLowering::Legal
1658 && "If SETUO is expanded, SETUNE must be legal!");
1659 CC1 = ISD::SETUNE; CC2 = ISD::SETUNE; Opc = ISD::OR; break;
1672 // If we are floating point, assign and break, otherwise fall through.
1673 if (!OpVT.isInteger()) {
1674 // We can use the 4th bit to tell if we are the unordered
1675 // or ordered version of the opcode.
1676 CC2 = ((unsigned)CCCode & 0x8U) ? ISD::SETUO : ISD::SETO;
1677 Opc = ((unsigned)CCCode & 0x8U) ? ISD::OR : ISD::AND;
1678 CC1 = (ISD::CondCode)(((int)CCCode & 0x7) | 0x10);
1681 // Fallthrough if we are unsigned integer.
1686 // We only support using the inverted operation, which is computed above
1687 // and not a different manner of supporting expanding these cases.
1688 llvm_unreachable("Don't know how to expand this condition!");
1691 // Try inverting the result of the inverse condition.
1692 InvCC = CCCode == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ;
1693 if (TLI.isCondCodeLegal(InvCC, OpVT)) {
1694 CC = DAG.getCondCode(InvCC);
1698 // If inverting the condition didn't work then we have no means to expand
1700 llvm_unreachable("Don't know how to expand this condition!");
1703 SDValue SetCC1, SetCC2;
1704 if (CCCode != ISD::SETO && CCCode != ISD::SETUO) {
1705 // If we aren't the ordered or unorder operation,
1706 // then the pattern is (LHS CC1 RHS) Opc (LHS CC2 RHS).
1707 SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1708 SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1710 // Otherwise, the pattern is (LHS CC1 LHS) Opc (RHS CC2 RHS)
1711 SetCC1 = DAG.getSetCC(dl, VT, LHS, LHS, CC1);
1712 SetCC2 = DAG.getSetCC(dl, VT, RHS, RHS, CC2);
1714 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1723 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
1724 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1725 /// a load from the stack slot to DestVT, extending it if needed.
1726 /// The resultant code need not be legal.
1727 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
1731 // Create the stack frame object.
1733 TLI.getDataLayout()->getPrefTypeAlignment(SrcOp.getValueType().
1734 getTypeForEVT(*DAG.getContext()));
1735 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1737 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1738 int SPFI = StackPtrFI->getIndex();
1739 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(SPFI);
1741 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
1742 unsigned SlotSize = SlotVT.getSizeInBits();
1743 unsigned DestSize = DestVT.getSizeInBits();
1744 Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
1745 unsigned DestAlign = TLI.getDataLayout()->getPrefTypeAlignment(DestType);
1747 // Emit a store to the stack slot. Use a truncstore if the input value is
1748 // later than DestVT.
1751 if (SrcSize > SlotSize)
1752 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1753 PtrInfo, SlotVT, false, false, SrcAlign);
1755 assert(SrcSize == SlotSize && "Invalid store");
1756 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1757 PtrInfo, false, false, SrcAlign);
1760 // Result is a load from the stack slot.
1761 if (SlotSize == DestSize)
1762 return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo,
1763 false, false, false, DestAlign);
1765 assert(SlotSize < DestSize && "Unknown extension!");
1766 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr,
1767 PtrInfo, SlotVT, false, false, DestAlign);
1770 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1772 // Create a vector sized/aligned stack slot, store the value to element #0,
1773 // then load the whole vector back out.
1774 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1776 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1777 int SPFI = StackPtrFI->getIndex();
1779 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0),
1781 MachinePointerInfo::getFixedStack(SPFI),
1782 Node->getValueType(0).getVectorElementType(),
1784 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
1785 MachinePointerInfo::getFixedStack(SPFI),
1786 false, false, false, 0);
1790 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
1791 /// support the operation, but do support the resultant vector type.
1792 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1793 unsigned NumElems = Node->getNumOperands();
1794 SDValue Value1, Value2;
1796 EVT VT = Node->getValueType(0);
1797 EVT OpVT = Node->getOperand(0).getValueType();
1798 EVT EltVT = VT.getVectorElementType();
1800 // If the only non-undef value is the low element, turn this into a
1801 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1802 bool isOnlyLowElement = true;
1803 bool MoreThanTwoValues = false;
1804 bool isConstant = true;
1805 for (unsigned i = 0; i < NumElems; ++i) {
1806 SDValue V = Node->getOperand(i);
1807 if (V.getOpcode() == ISD::UNDEF)
1810 isOnlyLowElement = false;
1811 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1814 if (!Value1.getNode()) {
1816 } else if (!Value2.getNode()) {
1819 } else if (V != Value1 && V != Value2) {
1820 MoreThanTwoValues = true;
1824 if (!Value1.getNode())
1825 return DAG.getUNDEF(VT);
1827 if (isOnlyLowElement)
1828 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1830 // If all elements are constants, create a load from the constant pool.
1832 SmallVector<Constant*, 16> CV;
1833 for (unsigned i = 0, e = NumElems; i != e; ++i) {
1834 if (ConstantFPSDNode *V =
1835 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1836 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1837 } else if (ConstantSDNode *V =
1838 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1840 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1842 // If OpVT and EltVT don't match, EltVT is not legal and the
1843 // element values have been promoted/truncated earlier. Undo this;
1844 // we don't want a v16i8 to become a v16i32 for example.
1845 const ConstantInt *CI = V->getConstantIntValue();
1846 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
1847 CI->getZExtValue()));
1850 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
1851 Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
1852 CV.push_back(UndefValue::get(OpNTy));
1855 Constant *CP = ConstantVector::get(CV);
1856 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
1857 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
1858 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
1859 MachinePointerInfo::getConstantPool(),
1860 false, false, false, Alignment);
1863 if (!MoreThanTwoValues) {
1864 SmallVector<int, 8> ShuffleVec(NumElems, -1);
1865 for (unsigned i = 0; i < NumElems; ++i) {
1866 SDValue V = Node->getOperand(i);
1867 if (V.getOpcode() == ISD::UNDEF)
1869 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
1871 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
1872 // Get the splatted value into the low element of a vector register.
1873 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
1875 if (Value2.getNode())
1876 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
1878 Vec2 = DAG.getUNDEF(VT);
1880 // Return shuffle(LowValVec, undef, <0,0,0,0>)
1881 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
1885 // Otherwise, we can't handle this case efficiently.
1886 return ExpandVectorBuildThroughStack(Node);
1889 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
1890 // does not fit into a register, return the lo part and set the hi part to the
1891 // by-reg argument. If it does fit into a single register, return the result
1892 // and leave the Hi part unset.
1893 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
1895 TargetLowering::ArgListTy Args;
1896 TargetLowering::ArgListEntry Entry;
1897 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1898 EVT ArgVT = Node->getOperand(i).getValueType();
1899 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1900 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
1901 Entry.isSExt = isSigned;
1902 Entry.isZExt = !isSigned;
1903 Args.push_back(Entry);
1905 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1906 TLI.getPointerTy());
1908 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
1910 // By default, the input chain to this libcall is the entry node of the
1911 // function. If the libcall is going to be emitted as a tail call then
1912 // TLI.isUsedByReturnOnly will change it to the right chain if the return
1913 // node which is being folded has a non-entry input chain.
1914 SDValue InChain = DAG.getEntryNode();
1916 // isTailCall may be true since the callee does not reference caller stack
1917 // frame. Check if it's in the right position.
1918 SDValue TCChain = InChain;
1919 bool isTailCall = TLI.isInTailCallPosition(DAG, Node, TCChain);
1924 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
1925 0, TLI.getLibcallCallingConv(LC), isTailCall,
1926 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
1927 Callee, Args, DAG, SDLoc(Node));
1928 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
1931 if (!CallInfo.second.getNode())
1932 // It's a tailcall, return the chain (which is the DAG root).
1933 return DAG.getRoot();
1935 return CallInfo.first;
1938 /// ExpandLibCall - Generate a libcall taking the given operands as arguments
1939 /// and returning a result of type RetVT.
1940 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, EVT RetVT,
1941 const SDValue *Ops, unsigned NumOps,
1942 bool isSigned, SDLoc dl) {
1943 TargetLowering::ArgListTy Args;
1944 Args.reserve(NumOps);
1946 TargetLowering::ArgListEntry Entry;
1947 for (unsigned i = 0; i != NumOps; ++i) {
1948 Entry.Node = Ops[i];
1949 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
1950 Entry.isSExt = isSigned;
1951 Entry.isZExt = !isSigned;
1952 Args.push_back(Entry);
1954 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1955 TLI.getPointerTy());
1957 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
1959 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
1960 false, 0, TLI.getLibcallCallingConv(LC),
1961 /*isTailCall=*/false,
1962 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
1963 Callee, Args, DAG, dl);
1964 std::pair<SDValue,SDValue> CallInfo = TLI.LowerCallTo(CLI);
1966 return CallInfo.first;
1969 // ExpandChainLibCall - Expand a node into a call to a libcall. Similar to
1970 // ExpandLibCall except that the first operand is the in-chain.
1971 std::pair<SDValue, SDValue>
1972 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
1975 SDValue InChain = Node->getOperand(0);
1977 TargetLowering::ArgListTy Args;
1978 TargetLowering::ArgListEntry Entry;
1979 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) {
1980 EVT ArgVT = Node->getOperand(i).getValueType();
1981 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1982 Entry.Node = Node->getOperand(i);
1984 Entry.isSExt = isSigned;
1985 Entry.isZExt = !isSigned;
1986 Args.push_back(Entry);
1988 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1989 TLI.getPointerTy());
1991 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
1993 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
1994 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
1995 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
1996 Callee, Args, DAG, SDLoc(Node));
1997 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2002 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
2003 RTLIB::Libcall Call_F32,
2004 RTLIB::Libcall Call_F64,
2005 RTLIB::Libcall Call_F80,
2006 RTLIB::Libcall Call_F128,
2007 RTLIB::Libcall Call_PPCF128) {
2009 switch (Node->getSimpleValueType(0).SimpleTy) {
2010 default: llvm_unreachable("Unexpected request for libcall!");
2011 case MVT::f32: LC = Call_F32; break;
2012 case MVT::f64: LC = Call_F64; break;
2013 case MVT::f80: LC = Call_F80; break;
2014 case MVT::f128: LC = Call_F128; break;
2015 case MVT::ppcf128: LC = Call_PPCF128; break;
2017 return ExpandLibCall(LC, Node, false);
2020 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
2021 RTLIB::Libcall Call_I8,
2022 RTLIB::Libcall Call_I16,
2023 RTLIB::Libcall Call_I32,
2024 RTLIB::Libcall Call_I64,
2025 RTLIB::Libcall Call_I128) {
2027 switch (Node->getSimpleValueType(0).SimpleTy) {
2028 default: llvm_unreachable("Unexpected request for libcall!");
2029 case MVT::i8: LC = Call_I8; break;
2030 case MVT::i16: LC = Call_I16; break;
2031 case MVT::i32: LC = Call_I32; break;
2032 case MVT::i64: LC = Call_I64; break;
2033 case MVT::i128: LC = Call_I128; break;
2035 return ExpandLibCall(LC, Node, isSigned);
2038 /// isDivRemLibcallAvailable - Return true if divmod libcall is available.
2039 static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
2040 const TargetLowering &TLI) {
2042 switch (Node->getSimpleValueType(0).SimpleTy) {
2043 default: llvm_unreachable("Unexpected request for libcall!");
2044 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2045 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2046 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2047 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2048 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2051 return TLI.getLibcallName(LC) != 0;
2054 /// useDivRem - Only issue divrem libcall if both quotient and remainder are
2056 static bool useDivRem(SDNode *Node, bool isSigned, bool isDIV) {
2057 // The other use might have been replaced with a divrem already.
2058 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2059 unsigned OtherOpcode = 0;
2061 OtherOpcode = isDIV ? ISD::SREM : ISD::SDIV;
2063 OtherOpcode = isDIV ? ISD::UREM : ISD::UDIV;
2065 SDValue Op0 = Node->getOperand(0);
2066 SDValue Op1 = Node->getOperand(1);
2067 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2068 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2072 if ((User->getOpcode() == OtherOpcode || User->getOpcode() == DivRemOpc) &&
2073 User->getOperand(0) == Op0 &&
2074 User->getOperand(1) == Op1)
2080 /// ExpandDivRemLibCall - Issue libcalls to __{u}divmod to compute div / rem
2083 SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
2084 SmallVectorImpl<SDValue> &Results) {
2085 unsigned Opcode = Node->getOpcode();
2086 bool isSigned = Opcode == ISD::SDIVREM;
2089 switch (Node->getSimpleValueType(0).SimpleTy) {
2090 default: llvm_unreachable("Unexpected request for libcall!");
2091 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2092 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2093 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2094 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2095 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2098 // The input chain to this libcall is the entry node of the function.
2099 // Legalizing the call will automatically add the previous call to the
2101 SDValue InChain = DAG.getEntryNode();
2103 EVT RetVT = Node->getValueType(0);
2104 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2106 TargetLowering::ArgListTy Args;
2107 TargetLowering::ArgListEntry Entry;
2108 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2109 EVT ArgVT = Node->getOperand(i).getValueType();
2110 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2111 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
2112 Entry.isSExt = isSigned;
2113 Entry.isZExt = !isSigned;
2114 Args.push_back(Entry);
2117 // Also pass the return address of the remainder.
2118 SDValue FIPtr = DAG.CreateStackTemporary(RetVT);
2120 Entry.Ty = RetTy->getPointerTo();
2121 Entry.isSExt = isSigned;
2122 Entry.isZExt = !isSigned;
2123 Args.push_back(Entry);
2125 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2126 TLI.getPointerTy());
2130 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
2131 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
2132 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2133 Callee, Args, DAG, dl);
2134 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2136 // Remainder is loaded back from the stack frame.
2137 SDValue Rem = DAG.getLoad(RetVT, dl, CallInfo.second, FIPtr,
2138 MachinePointerInfo(), false, false, false, 0);
2139 Results.push_back(CallInfo.first);
2140 Results.push_back(Rem);
2143 /// isSinCosLibcallAvailable - Return true if sincos libcall is available.
2144 static bool isSinCosLibcallAvailable(SDNode *Node, const TargetLowering &TLI) {
2146 switch (Node->getSimpleValueType(0).SimpleTy) {
2147 default: llvm_unreachable("Unexpected request for libcall!");
2148 case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2149 case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2150 case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2151 case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2152 case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2154 return TLI.getLibcallName(LC) != 0;
2157 /// canCombineSinCosLibcall - Return true if sincos libcall is available and
2158 /// can be used to combine sin and cos.
2159 static bool canCombineSinCosLibcall(SDNode *Node, const TargetLowering &TLI,
2160 const TargetMachine &TM) {
2161 if (!isSinCosLibcallAvailable(Node, TLI))
2163 // GNU sin/cos functions set errno while sincos does not. Therefore
2164 // combining sin and cos is only safe if unsafe-fpmath is enabled.
2165 bool isGNU = Triple(TM.getTargetTriple()).getEnvironment() == Triple::GNU;
2166 if (isGNU && !TM.Options.UnsafeFPMath)
2171 /// useSinCos - Only issue sincos libcall if both sin and cos are
2173 static bool useSinCos(SDNode *Node) {
2174 unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN
2175 ? ISD::FCOS : ISD::FSIN;
2177 SDValue Op0 = Node->getOperand(0);
2178 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2179 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2183 // The other user might have been turned into sincos already.
2184 if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS)
2190 /// ExpandSinCosLibCall - Issue libcalls to sincos to compute sin / cos
2193 SelectionDAGLegalize::ExpandSinCosLibCall(SDNode *Node,
2194 SmallVectorImpl<SDValue> &Results) {
2196 switch (Node->getSimpleValueType(0).SimpleTy) {
2197 default: llvm_unreachable("Unexpected request for libcall!");
2198 case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2199 case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2200 case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2201 case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2202 case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2205 // The input chain to this libcall is the entry node of the function.
2206 // Legalizing the call will automatically add the previous call to the
2208 SDValue InChain = DAG.getEntryNode();
2210 EVT RetVT = Node->getValueType(0);
2211 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2213 TargetLowering::ArgListTy Args;
2214 TargetLowering::ArgListEntry Entry;
2216 // Pass the argument.
2217 Entry.Node = Node->getOperand(0);
2219 Entry.isSExt = false;
2220 Entry.isZExt = false;
2221 Args.push_back(Entry);
2223 // Pass the return address of sin.
2224 SDValue SinPtr = DAG.CreateStackTemporary(RetVT);
2225 Entry.Node = SinPtr;
2226 Entry.Ty = RetTy->getPointerTo();
2227 Entry.isSExt = false;
2228 Entry.isZExt = false;
2229 Args.push_back(Entry);
2231 // Also pass the return address of the cos.
2232 SDValue CosPtr = DAG.CreateStackTemporary(RetVT);
2233 Entry.Node = CosPtr;
2234 Entry.Ty = RetTy->getPointerTo();
2235 Entry.isSExt = false;
2236 Entry.isZExt = false;
2237 Args.push_back(Entry);
2239 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2240 TLI.getPointerTy());
2244 CallLoweringInfo CLI(InChain, Type::getVoidTy(*DAG.getContext()),
2245 false, false, false, false,
2246 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
2247 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2248 Callee, Args, DAG, dl);
2249 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2251 Results.push_back(DAG.getLoad(RetVT, dl, CallInfo.second, SinPtr,
2252 MachinePointerInfo(), false, false, false, 0));
2253 Results.push_back(DAG.getLoad(RetVT, dl, CallInfo.second, CosPtr,
2254 MachinePointerInfo(), false, false, false, 0));
2257 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
2258 /// INT_TO_FP operation of the specified operand when the target requests that
2259 /// we expand it. At this point, we know that the result and operand types are
2260 /// legal for the target.
2261 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
2265 if (Op0.getValueType() == MVT::i32 && TLI.isTypeLegal(MVT::f64)) {
2266 // simple 32-bit [signed|unsigned] integer to float/double expansion
2268 // Get the stack frame index of a 8 byte buffer.
2269 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2271 // word offset constant for Hi/Lo address computation
2272 SDValue WordOff = DAG.getConstant(sizeof(int), StackSlot.getValueType());
2273 // set up Hi and Lo (into buffer) address based on endian
2274 SDValue Hi = StackSlot;
2275 SDValue Lo = DAG.getNode(ISD::ADD, dl, StackSlot.getValueType(),
2276 StackSlot, WordOff);
2277 if (TLI.isLittleEndian())
2280 // if signed map to unsigned space
2283 // constant used to invert sign bit (signed to unsigned mapping)
2284 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
2285 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2289 // store the lo of the constructed double - based on integer input
2290 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
2291 Op0Mapped, Lo, MachinePointerInfo(),
2293 // initial hi portion of constructed double
2294 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
2295 // store the hi of the constructed double - biased exponent
2296 SDValue Store2 = DAG.getStore(Store1, dl, InitialHi, Hi,
2297 MachinePointerInfo(),
2299 // load the constructed double
2300 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot,
2301 MachinePointerInfo(), false, false, false, 0);
2302 // FP constant to bias correct the final result
2303 SDValue Bias = DAG.getConstantFP(isSigned ?
2304 BitsToDouble(0x4330000080000000ULL) :
2305 BitsToDouble(0x4330000000000000ULL),
2307 // subtract the bias
2308 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2311 // handle final rounding
2312 if (DestVT == MVT::f64) {
2315 } else if (DestVT.bitsLT(MVT::f64)) {
2316 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2317 DAG.getIntPtrConstant(0));
2318 } else if (DestVT.bitsGT(MVT::f64)) {
2319 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2323 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2324 // Code below here assumes !isSigned without checking again.
2326 // Implementation of unsigned i64 to f64 following the algorithm in
2327 // __floatundidf in compiler_rt. This implementation has the advantage
2328 // of performing rounding correctly, both in the default rounding mode
2329 // and in all alternate rounding modes.
2330 // TODO: Generalize this for use with other types.
2331 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
2333 DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64);
2334 SDValue TwoP84PlusTwoP52 =
2335 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64);
2337 DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64);
2339 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32);
2340 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2341 DAG.getConstant(32, MVT::i64));
2342 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2343 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2344 SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr);
2345 SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr);
2346 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
2348 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
2351 // Implementation of unsigned i64 to f32.
2352 // TODO: Generalize this for use with other types.
2353 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) {
2354 // For unsigned conversions, convert them to signed conversions using the
2355 // algorithm from the x86_64 __floatundidf in compiler_rt.
2357 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0);
2359 SDValue ShiftConst =
2360 DAG.getConstant(1, TLI.getShiftAmountTy(Op0.getValueType()));
2361 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
2362 SDValue AndConst = DAG.getConstant(1, MVT::i64);
2363 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst);
2364 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr);
2366 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or);
2367 SDValue Slow = DAG.getNode(ISD::FADD, dl, MVT::f32, SignCvt, SignCvt);
2369 // TODO: This really should be implemented using a branch rather than a
2370 // select. We happen to get lucky and machinesink does the right
2371 // thing most of the time. This would be a good candidate for a
2372 //pseudo-op, or, even better, for whole-function isel.
2373 SDValue SignBitTest = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
2374 Op0, DAG.getConstant(0, MVT::i64), ISD::SETLT);
2375 return DAG.getSelect(dl, MVT::f32, SignBitTest, Slow, Fast);
2378 // Otherwise, implement the fully general conversion.
2380 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2381 DAG.getConstant(UINT64_C(0xfffffffffffff800), MVT::i64));
2382 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
2383 DAG.getConstant(UINT64_C(0x800), MVT::i64));
2384 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2385 DAG.getConstant(UINT64_C(0x7ff), MVT::i64));
2386 SDValue Ne = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
2387 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE);
2388 SDValue Sel = DAG.getSelect(dl, MVT::i64, Ne, Or, Op0);
2389 SDValue Ge = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
2390 Op0, DAG.getConstant(UINT64_C(0x0020000000000000), MVT::i64),
2392 SDValue Sel2 = DAG.getSelect(dl, MVT::i64, Ge, Sel, Op0);
2393 EVT SHVT = TLI.getShiftAmountTy(Sel2.getValueType());
2395 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2396 DAG.getConstant(32, SHVT));
2397 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh);
2398 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc);
2400 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), MVT::f64);
2401 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt);
2402 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2);
2403 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo);
2404 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2);
2405 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd,
2406 DAG.getIntPtrConstant(0));
2409 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2411 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(Op0.getValueType()),
2412 Op0, DAG.getConstant(0, Op0.getValueType()),
2414 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
2415 SDValue CstOffset = DAG.getSelect(dl, Zero.getValueType(),
2416 SignSet, Four, Zero);
2418 // If the sign bit of the integer is set, the large number will be treated
2419 // as a negative number. To counteract this, the dynamic code adds an
2420 // offset depending on the data type.
2422 switch (Op0.getSimpleValueType().SimpleTy) {
2423 default: llvm_unreachable("Unsupported integer type!");
2424 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2425 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2426 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2427 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2429 if (TLI.isLittleEndian()) FF <<= 32;
2430 Constant *FudgeFactor = ConstantInt::get(
2431 Type::getInt64Ty(*DAG.getContext()), FF);
2433 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
2434 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2435 CPIdx = DAG.getNode(ISD::ADD, dl, CPIdx.getValueType(), CPIdx, CstOffset);
2436 Alignment = std::min(Alignment, 4u);
2438 if (DestVT == MVT::f32)
2439 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2440 MachinePointerInfo::getConstantPool(),
2441 false, false, false, Alignment);
2443 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
2444 DAG.getEntryNode(), CPIdx,
2445 MachinePointerInfo::getConstantPool(),
2446 MVT::f32, false, false, Alignment);
2447 HandleSDNode Handle(Load);
2448 LegalizeOp(Load.getNode());
2449 FudgeInReg = Handle.getValue();
2452 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2455 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
2456 /// *INT_TO_FP operation of the specified operand when the target requests that
2457 /// we promote it. At this point, we know that the result and operand types are
2458 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2459 /// operation that takes a larger input.
2460 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2464 // First step, figure out the appropriate *INT_TO_FP operation to use.
2465 EVT NewInTy = LegalOp.getValueType();
2467 unsigned OpToUse = 0;
2469 // Scan for the appropriate larger type to use.
2471 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2472 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2474 // If the target supports SINT_TO_FP of this type, use it.
2475 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2476 OpToUse = ISD::SINT_TO_FP;
2479 if (isSigned) continue;
2481 // If the target supports UINT_TO_FP of this type, use it.
2482 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2483 OpToUse = ISD::UINT_TO_FP;
2487 // Otherwise, try a larger type.
2490 // Okay, we found the operation and type to use. Zero extend our input to the
2491 // desired type then run the operation on it.
2492 return DAG.getNode(OpToUse, dl, DestVT,
2493 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2494 dl, NewInTy, LegalOp));
2497 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
2498 /// FP_TO_*INT operation of the specified operand when the target requests that
2499 /// we promote it. At this point, we know that the result and operand types are
2500 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2501 /// operation that returns a larger result.
2502 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2506 // First step, figure out the appropriate FP_TO*INT operation to use.
2507 EVT NewOutTy = DestVT;
2509 unsigned OpToUse = 0;
2511 // Scan for the appropriate larger type to use.
2513 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2514 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2516 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2517 OpToUse = ISD::FP_TO_SINT;
2521 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2522 OpToUse = ISD::FP_TO_UINT;
2526 // Otherwise, try a larger type.
2530 // Okay, we found the operation and type to use.
2531 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2533 // Truncate the result of the extended FP_TO_*INT operation to the desired
2535 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2538 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
2540 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, SDLoc dl) {
2541 EVT VT = Op.getValueType();
2542 EVT SHVT = TLI.getShiftAmountTy(VT);
2543 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2544 switch (VT.getSimpleVT().SimpleTy) {
2545 default: llvm_unreachable("Unhandled Expand type in BSWAP!");
2547 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2548 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2549 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2551 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2552 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2553 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2554 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2555 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
2556 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
2557 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2558 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2559 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2561 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
2562 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
2563 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2564 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2565 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2566 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2567 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
2568 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
2569 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
2570 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
2571 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
2572 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
2573 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
2574 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
2575 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2576 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2577 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2578 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2579 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2580 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2581 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2585 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
2587 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2590 default: llvm_unreachable("Cannot expand this yet!");
2592 EVT VT = Op.getValueType();
2593 EVT ShVT = TLI.getShiftAmountTy(VT);
2594 unsigned Len = VT.getSizeInBits();
2596 assert(VT.isInteger() && Len <= 128 && Len % 8 == 0 &&
2597 "CTPOP not implemented for this type.");
2599 // This is the "best" algorithm from
2600 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
2602 SDValue Mask55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)), VT);
2603 SDValue Mask33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)), VT);
2604 SDValue Mask0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)), VT);
2605 SDValue Mask01 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x01)), VT);
2607 // v = v - ((v >> 1) & 0x55555555...)
2608 Op = DAG.getNode(ISD::SUB, dl, VT, Op,
2609 DAG.getNode(ISD::AND, dl, VT,
2610 DAG.getNode(ISD::SRL, dl, VT, Op,
2611 DAG.getConstant(1, ShVT)),
2613 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
2614 Op = DAG.getNode(ISD::ADD, dl, VT,
2615 DAG.getNode(ISD::AND, dl, VT, Op, Mask33),
2616 DAG.getNode(ISD::AND, dl, VT,
2617 DAG.getNode(ISD::SRL, dl, VT, Op,
2618 DAG.getConstant(2, ShVT)),
2620 // v = (v + (v >> 4)) & 0x0F0F0F0F...
2621 Op = DAG.getNode(ISD::AND, dl, VT,
2622 DAG.getNode(ISD::ADD, dl, VT, Op,
2623 DAG.getNode(ISD::SRL, dl, VT, Op,
2624 DAG.getConstant(4, ShVT))),
2626 // v = (v * 0x01010101...) >> (Len - 8)
2627 Op = DAG.getNode(ISD::SRL, dl, VT,
2628 DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
2629 DAG.getConstant(Len - 8, ShVT));
2633 case ISD::CTLZ_ZERO_UNDEF:
2634 // This trivially expands to CTLZ.
2635 return DAG.getNode(ISD::CTLZ, dl, Op.getValueType(), Op);
2637 // for now, we do this:
2638 // x = x | (x >> 1);
2639 // x = x | (x >> 2);
2641 // x = x | (x >>16);
2642 // x = x | (x >>32); // for 64-bit input
2643 // return popcount(~x);
2645 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
2646 EVT VT = Op.getValueType();
2647 EVT ShVT = TLI.getShiftAmountTy(VT);
2648 unsigned len = VT.getSizeInBits();
2649 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2650 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2651 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2652 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2654 Op = DAG.getNOT(dl, Op, VT);
2655 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2657 case ISD::CTTZ_ZERO_UNDEF:
2658 // This trivially expands to CTTZ.
2659 return DAG.getNode(ISD::CTTZ, dl, Op.getValueType(), Op);
2661 // for now, we use: { return popcount(~x & (x - 1)); }
2662 // unless the target has ctlz but not ctpop, in which case we use:
2663 // { return 32 - nlz(~x & (x-1)); }
2664 // see also http://www.hackersdelight.org/HDcode/ntz.cc
2665 EVT VT = Op.getValueType();
2666 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2667 DAG.getNOT(dl, Op, VT),
2668 DAG.getNode(ISD::SUB, dl, VT, Op,
2669 DAG.getConstant(1, VT)));
2670 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2671 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2672 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2673 return DAG.getNode(ISD::SUB, dl, VT,
2674 DAG.getConstant(VT.getSizeInBits(), VT),
2675 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2676 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2681 std::pair <SDValue, SDValue> SelectionDAGLegalize::ExpandAtomic(SDNode *Node) {
2682 unsigned Opc = Node->getOpcode();
2683 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
2688 llvm_unreachable("Unhandled atomic intrinsic Expand!");
2689 case ISD::ATOMIC_SWAP:
2690 switch (VT.SimpleTy) {
2691 default: llvm_unreachable("Unexpected value type for atomic!");
2692 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break;
2693 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
2694 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
2695 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
2696 case MVT::i128:LC = RTLIB::SYNC_LOCK_TEST_AND_SET_16;break;
2699 case ISD::ATOMIC_CMP_SWAP:
2700 switch (VT.SimpleTy) {
2701 default: llvm_unreachable("Unexpected value type for atomic!");
2702 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break;
2703 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;
2704 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;
2705 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
2706 case MVT::i128:LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16;break;
2709 case ISD::ATOMIC_LOAD_ADD:
2710 switch (VT.SimpleTy) {
2711 default: llvm_unreachable("Unexpected value type for atomic!");
2712 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break;
2713 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;
2714 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;
2715 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
2716 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_ADD_16;break;
2719 case ISD::ATOMIC_LOAD_SUB:
2720 switch (VT.SimpleTy) {
2721 default: llvm_unreachable("Unexpected value type for atomic!");
2722 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break;
2723 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;
2724 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;
2725 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
2726 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_SUB_16;break;
2729 case ISD::ATOMIC_LOAD_AND:
2730 switch (VT.SimpleTy) {
2731 default: llvm_unreachable("Unexpected value type for atomic!");
2732 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break;
2733 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;
2734 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;
2735 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
2736 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_AND_16;break;
2739 case ISD::ATOMIC_LOAD_OR:
2740 switch (VT.SimpleTy) {
2741 default: llvm_unreachable("Unexpected value type for atomic!");
2742 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break;
2743 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;
2744 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;
2745 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
2746 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_OR_16;break;
2749 case ISD::ATOMIC_LOAD_XOR:
2750 switch (VT.SimpleTy) {
2751 default: llvm_unreachable("Unexpected value type for atomic!");
2752 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break;
2753 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;
2754 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;
2755 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
2756 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_XOR_16;break;
2759 case ISD::ATOMIC_LOAD_NAND:
2760 switch (VT.SimpleTy) {
2761 default: llvm_unreachable("Unexpected value type for atomic!");
2762 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break;
2763 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;
2764 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;
2765 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
2766 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_NAND_16;break;
2769 case ISD::ATOMIC_LOAD_MAX:
2770 switch (VT.SimpleTy) {
2771 default: llvm_unreachable("Unexpected value type for atomic!");
2772 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_MAX_1; break;
2773 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_MAX_2; break;
2774 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_MAX_4; break;
2775 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_MAX_8; break;
2776 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_MAX_16;break;
2779 case ISD::ATOMIC_LOAD_UMAX:
2780 switch (VT.SimpleTy) {
2781 default: llvm_unreachable("Unexpected value type for atomic!");
2782 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_UMAX_1; break;
2783 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_UMAX_2; break;
2784 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_UMAX_4; break;
2785 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_UMAX_8; break;
2786 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_UMAX_16;break;
2789 case ISD::ATOMIC_LOAD_MIN:
2790 switch (VT.SimpleTy) {
2791 default: llvm_unreachable("Unexpected value type for atomic!");
2792 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_MIN_1; break;
2793 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_MIN_2; break;
2794 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_MIN_4; break;
2795 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_MIN_8; break;
2796 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_MIN_16;break;
2799 case ISD::ATOMIC_LOAD_UMIN:
2800 switch (VT.SimpleTy) {
2801 default: llvm_unreachable("Unexpected value type for atomic!");
2802 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_UMIN_1; break;
2803 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_UMIN_2; break;
2804 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_UMIN_4; break;
2805 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_UMIN_8; break;
2806 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_UMIN_16;break;
2811 return ExpandChainLibCall(LC, Node, false);
2814 void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
2815 SmallVector<SDValue, 8> Results;
2817 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2819 switch (Node->getOpcode()) {
2822 case ISD::CTLZ_ZERO_UNDEF:
2824 case ISD::CTTZ_ZERO_UNDEF:
2825 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
2826 Results.push_back(Tmp1);
2829 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2831 case ISD::FRAMEADDR:
2832 case ISD::RETURNADDR:
2833 case ISD::FRAME_TO_ARGS_OFFSET:
2834 Results.push_back(DAG.getConstant(0, Node->getValueType(0)));
2836 case ISD::FLT_ROUNDS_:
2837 Results.push_back(DAG.getConstant(1, Node->getValueType(0)));
2839 case ISD::EH_RETURN:
2843 case ISD::EH_SJLJ_LONGJMP:
2844 // If the target didn't expand these, there's nothing to do, so just
2845 // preserve the chain and be done.
2846 Results.push_back(Node->getOperand(0));
2848 case ISD::EH_SJLJ_SETJMP:
2849 // If the target didn't expand this, just return 'zero' and preserve the
2851 Results.push_back(DAG.getConstant(0, MVT::i32));
2852 Results.push_back(Node->getOperand(0));
2854 case ISD::ATOMIC_FENCE: {
2855 // If the target didn't lower this, lower it to '__sync_synchronize()' call
2856 // FIXME: handle "fence singlethread" more efficiently.
2857 TargetLowering::ArgListTy Args;
2859 CallLoweringInfo CLI(Node->getOperand(0),
2860 Type::getVoidTy(*DAG.getContext()),
2861 false, false, false, false, 0, CallingConv::C,
2862 /*isTailCall=*/false,
2863 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2864 DAG.getExternalSymbol("__sync_synchronize",
2865 TLI.getPointerTy()),
2867 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
2869 Results.push_back(CallResult.second);
2872 case ISD::ATOMIC_LOAD: {
2873 // There is no libcall for atomic load; fake it with ATOMIC_CMP_SWAP.
2874 SDValue Zero = DAG.getConstant(0, Node->getValueType(0));
2875 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl,
2876 cast<AtomicSDNode>(Node)->getMemoryVT(),
2877 Node->getOperand(0),
2878 Node->getOperand(1), Zero, Zero,
2879 cast<AtomicSDNode>(Node)->getMemOperand(),
2880 cast<AtomicSDNode>(Node)->getOrdering(),
2881 cast<AtomicSDNode>(Node)->getSynchScope());
2882 Results.push_back(Swap.getValue(0));
2883 Results.push_back(Swap.getValue(1));
2886 case ISD::ATOMIC_STORE: {
2887 // There is no libcall for atomic store; fake it with ATOMIC_SWAP.
2888 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
2889 cast<AtomicSDNode>(Node)->getMemoryVT(),
2890 Node->getOperand(0),
2891 Node->getOperand(1), Node->getOperand(2),
2892 cast<AtomicSDNode>(Node)->getMemOperand(),
2893 cast<AtomicSDNode>(Node)->getOrdering(),
2894 cast<AtomicSDNode>(Node)->getSynchScope());
2895 Results.push_back(Swap.getValue(1));
2898 // By default, atomic intrinsics are marked Legal and lowered. Targets
2899 // which don't support them directly, however, may want libcalls, in which
2900 // case they mark them Expand, and we get here.
2901 case ISD::ATOMIC_SWAP:
2902 case ISD::ATOMIC_LOAD_ADD:
2903 case ISD::ATOMIC_LOAD_SUB:
2904 case ISD::ATOMIC_LOAD_AND:
2905 case ISD::ATOMIC_LOAD_OR:
2906 case ISD::ATOMIC_LOAD_XOR:
2907 case ISD::ATOMIC_LOAD_NAND:
2908 case ISD::ATOMIC_LOAD_MIN:
2909 case ISD::ATOMIC_LOAD_MAX:
2910 case ISD::ATOMIC_LOAD_UMIN:
2911 case ISD::ATOMIC_LOAD_UMAX:
2912 case ISD::ATOMIC_CMP_SWAP: {
2913 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node);
2914 Results.push_back(Tmp.first);
2915 Results.push_back(Tmp.second);
2918 case ISD::DYNAMIC_STACKALLOC:
2919 ExpandDYNAMIC_STACKALLOC(Node, Results);
2921 case ISD::MERGE_VALUES:
2922 for (unsigned i = 0; i < Node->getNumValues(); i++)
2923 Results.push_back(Node->getOperand(i));
2926 EVT VT = Node->getValueType(0);
2928 Results.push_back(DAG.getConstant(0, VT));
2930 assert(VT.isFloatingPoint() && "Unknown value type!");
2931 Results.push_back(DAG.getConstantFP(0, VT));
2936 // If this operation is not supported, lower it to 'abort()' call
2937 TargetLowering::ArgListTy Args;
2939 CallLoweringInfo CLI(Node->getOperand(0),
2940 Type::getVoidTy(*DAG.getContext()),
2941 false, false, false, false, 0, CallingConv::C,
2942 /*isTailCall=*/false,
2943 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2944 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
2946 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
2948 Results.push_back(CallResult.second);
2953 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
2954 Node->getValueType(0), dl);
2955 Results.push_back(Tmp1);
2957 case ISD::FP_EXTEND:
2958 Tmp1 = EmitStackConvert(Node->getOperand(0),
2959 Node->getOperand(0).getValueType(),
2960 Node->getValueType(0), dl);
2961 Results.push_back(Tmp1);
2963 case ISD::SIGN_EXTEND_INREG: {
2964 // NOTE: we could fall back on load/store here too for targets without
2965 // SAR. However, it is doubtful that any exist.
2966 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2967 EVT VT = Node->getValueType(0);
2968 EVT ShiftAmountTy = TLI.getShiftAmountTy(VT);
2971 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
2972 ExtraVT.getScalarType().getSizeInBits();
2973 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy);
2974 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
2975 Node->getOperand(0), ShiftCst);
2976 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
2977 Results.push_back(Tmp1);
2980 case ISD::FP_ROUND_INREG: {
2981 // The only way we can lower this is to turn it into a TRUNCSTORE,
2982 // EXTLOAD pair, targeting a temporary location (a stack slot).
2984 // NOTE: there is a choice here between constantly creating new stack
2985 // slots and always reusing the same one. We currently always create
2986 // new ones, as reuse may inhibit scheduling.
2987 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2988 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
2989 Node->getValueType(0), dl);
2990 Results.push_back(Tmp1);
2993 case ISD::SINT_TO_FP:
2994 case ISD::UINT_TO_FP:
2995 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
2996 Node->getOperand(0), Node->getValueType(0), dl);
2997 Results.push_back(Tmp1);
2999 case ISD::FP_TO_UINT: {
3000 SDValue True, False;
3001 EVT VT = Node->getOperand(0).getValueType();
3002 EVT NVT = Node->getValueType(0);
3003 APFloat apf(DAG.EVTToAPFloatSemantics(VT),
3004 APInt::getNullValue(VT.getSizeInBits()));
3005 APInt x = APInt::getSignBit(NVT.getSizeInBits());
3006 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
3007 Tmp1 = DAG.getConstantFP(apf, VT);
3008 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(VT),
3009 Node->getOperand(0),
3011 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
3012 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
3013 DAG.getNode(ISD::FSUB, dl, VT,
3014 Node->getOperand(0), Tmp1));
3015 False = DAG.getNode(ISD::XOR, dl, NVT, False,
3016 DAG.getConstant(x, NVT));
3017 Tmp1 = DAG.getSelect(dl, NVT, Tmp2, True, False);
3018 Results.push_back(Tmp1);
3022 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3023 EVT VT = Node->getValueType(0);
3024 Tmp1 = Node->getOperand(0);
3025 Tmp2 = Node->getOperand(1);
3026 unsigned Align = Node->getConstantOperandVal(3);
3028 SDValue VAListLoad = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2,
3029 MachinePointerInfo(V),
3030 false, false, false, 0);
3031 SDValue VAList = VAListLoad;
3033 if (Align > TLI.getMinStackArgumentAlignment()) {
3034 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
3036 VAList = DAG.getNode(ISD::ADD, dl, VAList.getValueType(), VAList,
3037 DAG.getConstant(Align - 1,
3038 VAList.getValueType()));
3040 VAList = DAG.getNode(ISD::AND, dl, VAList.getValueType(), VAList,
3041 DAG.getConstant(-(int64_t)Align,
3042 VAList.getValueType()));
3045 // Increment the pointer, VAList, to the next vaarg
3046 Tmp3 = DAG.getNode(ISD::ADD, dl, VAList.getValueType(), VAList,
3047 DAG.getConstant(TLI.getDataLayout()->
3048 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())),
3049 VAList.getValueType()));
3050 // Store the incremented VAList to the legalized pointer
3051 Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2,
3052 MachinePointerInfo(V), false, false, 0);
3053 // Load the actual argument out of the pointer VAList
3054 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(),
3055 false, false, false, 0));
3056 Results.push_back(Results[0].getValue(1));
3060 // This defaults to loading a pointer from the input and storing it to the
3061 // output, returning the chain.
3062 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3063 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3064 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0),
3065 Node->getOperand(2), MachinePointerInfo(VS),
3066 false, false, false, 0);
3067 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1),
3068 MachinePointerInfo(VD), false, false, 0);
3069 Results.push_back(Tmp1);
3072 case ISD::EXTRACT_VECTOR_ELT:
3073 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
3074 // This must be an access of the only element. Return it.
3075 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
3076 Node->getOperand(0));
3078 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
3079 Results.push_back(Tmp1);
3081 case ISD::EXTRACT_SUBVECTOR:
3082 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
3084 case ISD::INSERT_SUBVECTOR:
3085 Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0)));
3087 case ISD::CONCAT_VECTORS: {
3088 Results.push_back(ExpandVectorBuildThroughStack(Node));
3091 case ISD::SCALAR_TO_VECTOR:
3092 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
3094 case ISD::INSERT_VECTOR_ELT:
3095 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
3096 Node->getOperand(1),
3097 Node->getOperand(2), dl));
3099 case ISD::VECTOR_SHUFFLE: {
3100 SmallVector<int, 32> NewMask;
3101 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
3103 EVT VT = Node->getValueType(0);
3104 EVT EltVT = VT.getVectorElementType();
3105 SDValue Op0 = Node->getOperand(0);
3106 SDValue Op1 = Node->getOperand(1);
3107 if (!TLI.isTypeLegal(EltVT)) {
3109 EVT NewEltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
3111 // BUILD_VECTOR operands are allowed to be wider than the element type.
3112 // But if NewEltVT is smaller that EltVT the BUILD_VECTOR does not accept
3114 if (NewEltVT.bitsLT(EltVT)) {
3116 // Convert shuffle node.
3117 // If original node was v4i64 and the new EltVT is i32,
3118 // cast operands to v8i32 and re-build the mask.
3120 // Calculate new VT, the size of the new VT should be equal to original.
3122 EVT::getVectorVT(*DAG.getContext(), NewEltVT,
3123 VT.getSizeInBits() / NewEltVT.getSizeInBits());
3124 assert(NewVT.bitsEq(VT));
3126 // cast operands to new VT
3127 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0);
3128 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1);
3130 // Convert the shuffle mask
3131 unsigned int factor =
3132 NewVT.getVectorNumElements()/VT.getVectorNumElements();
3134 // EltVT gets smaller
3137 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
3139 for (unsigned fi = 0; fi < factor; ++fi)
3140 NewMask.push_back(Mask[i]);
3143 for (unsigned fi = 0; fi < factor; ++fi)
3144 NewMask.push_back(Mask[i]*factor+fi);
3152 unsigned NumElems = VT.getVectorNumElements();
3153 SmallVector<SDValue, 16> Ops;
3154 for (unsigned i = 0; i != NumElems; ++i) {
3156 Ops.push_back(DAG.getUNDEF(EltVT));
3159 unsigned Idx = Mask[i];
3161 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3163 DAG.getConstant(Idx, TLI.getVectorIdxTy())));
3165 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3167 DAG.getConstant(Idx - NumElems,
3168 TLI.getVectorIdxTy())));
3171 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
3172 // We may have changed the BUILD_VECTOR type. Cast it back to the Node type.
3173 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), Tmp1);
3174 Results.push_back(Tmp1);
3177 case ISD::EXTRACT_ELEMENT: {
3178 EVT OpTy = Node->getOperand(0).getValueType();
3179 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
3181 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
3182 DAG.getConstant(OpTy.getSizeInBits()/2,
3183 TLI.getShiftAmountTy(Node->getOperand(0).getValueType())));
3184 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
3187 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
3188 Node->getOperand(0));
3190 Results.push_back(Tmp1);
3193 case ISD::STACKSAVE:
3194 // Expand to CopyFromReg if the target set
3195 // StackPointerRegisterToSaveRestore.
3196 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3197 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
3198 Node->getValueType(0)));
3199 Results.push_back(Results[0].getValue(1));
3201 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
3202 Results.push_back(Node->getOperand(0));
3205 case ISD::STACKRESTORE:
3206 // Expand to CopyToReg if the target set
3207 // StackPointerRegisterToSaveRestore.
3208 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3209 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
3210 Node->getOperand(1)));
3212 Results.push_back(Node->getOperand(0));
3215 case ISD::FCOPYSIGN:
3216 Results.push_back(ExpandFCOPYSIGN(Node));
3219 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3220 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3221 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
3222 Node->getOperand(0));
3223 Results.push_back(Tmp1);
3226 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3227 EVT VT = Node->getValueType(0);
3228 Tmp1 = Node->getOperand(0);
3229 Tmp2 = DAG.getConstantFP(0.0, VT);
3230 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(Tmp1.getValueType()),
3231 Tmp1, Tmp2, ISD::SETUGT);
3232 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
3233 Tmp1 = DAG.getSelect(dl, VT, Tmp2, Tmp1, Tmp3);
3234 Results.push_back(Tmp1);
3238 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3239 RTLIB::SQRT_F80, RTLIB::SQRT_F128,
3240 RTLIB::SQRT_PPCF128));
3244 EVT VT = Node->getValueType(0);
3245 bool isSIN = Node->getOpcode() == ISD::FSIN;
3246 // Turn fsin / fcos into ISD::FSINCOS node if there are a pair of fsin /
3247 // fcos which share the same operand and both are used.
3248 if ((TLI.isOperationLegalOrCustom(ISD::FSINCOS, VT) ||
3249 canCombineSinCosLibcall(Node, TLI, TM))
3250 && useSinCos(Node)) {
3251 SDVTList VTs = DAG.getVTList(VT, VT);
3252 Tmp1 = DAG.getNode(ISD::FSINCOS, dl, VTs, Node->getOperand(0));
3254 Tmp1 = Tmp1.getValue(1);
3255 Results.push_back(Tmp1);
3257 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
3258 RTLIB::SIN_F80, RTLIB::SIN_F128,
3259 RTLIB::SIN_PPCF128));
3261 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
3262 RTLIB::COS_F80, RTLIB::COS_F128,
3263 RTLIB::COS_PPCF128));
3268 // Expand into sincos libcall.
3269 ExpandSinCosLibCall(Node, Results);
3272 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
3273 RTLIB::LOG_F80, RTLIB::LOG_F128,
3274 RTLIB::LOG_PPCF128));
3277 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3278 RTLIB::LOG2_F80, RTLIB::LOG2_F128,
3279 RTLIB::LOG2_PPCF128));
3282 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3283 RTLIB::LOG10_F80, RTLIB::LOG10_F128,
3284 RTLIB::LOG10_PPCF128));
3287 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
3288 RTLIB::EXP_F80, RTLIB::EXP_F128,
3289 RTLIB::EXP_PPCF128));
3292 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3293 RTLIB::EXP2_F80, RTLIB::EXP2_F128,
3294 RTLIB::EXP2_PPCF128));
3297 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3298 RTLIB::TRUNC_F80, RTLIB::TRUNC_F128,
3299 RTLIB::TRUNC_PPCF128));
3302 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3303 RTLIB::FLOOR_F80, RTLIB::FLOOR_F128,
3304 RTLIB::FLOOR_PPCF128));
3307 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3308 RTLIB::CEIL_F80, RTLIB::CEIL_F128,
3309 RTLIB::CEIL_PPCF128));
3312 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
3313 RTLIB::RINT_F80, RTLIB::RINT_F128,
3314 RTLIB::RINT_PPCF128));
3316 case ISD::FNEARBYINT:
3317 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
3318 RTLIB::NEARBYINT_F64,
3319 RTLIB::NEARBYINT_F80,
3320 RTLIB::NEARBYINT_F128,
3321 RTLIB::NEARBYINT_PPCF128));
3324 Results.push_back(ExpandFPLibCall(Node, RTLIB::ROUND_F32,
3328 RTLIB::ROUND_PPCF128));
3331 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
3332 RTLIB::POWI_F80, RTLIB::POWI_F128,
3333 RTLIB::POWI_PPCF128));
3336 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
3337 RTLIB::POW_F80, RTLIB::POW_F128,
3338 RTLIB::POW_PPCF128));
3341 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
3342 RTLIB::DIV_F80, RTLIB::DIV_F128,
3343 RTLIB::DIV_PPCF128));
3346 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
3347 RTLIB::REM_F80, RTLIB::REM_F128,
3348 RTLIB::REM_PPCF128));
3351 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMA_F32, RTLIB::FMA_F64,
3352 RTLIB::FMA_F80, RTLIB::FMA_F128,
3353 RTLIB::FMA_PPCF128));
3355 case ISD::FP16_TO_FP32:
3356 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
3358 case ISD::FP32_TO_FP16:
3359 Results.push_back(ExpandLibCall(RTLIB::FPROUND_F32_F16, Node, false));
3361 case ISD::ConstantFP: {
3362 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
3363 // Check to see if this FP immediate is already legal.
3364 // If this is a legal constant, turn it into a TargetConstantFP node.
3365 if (!TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
3366 Results.push_back(ExpandConstantFP(CFP, true));
3370 EVT VT = Node->getValueType(0);
3371 assert(TLI.isOperationLegalOrCustom(ISD::FADD, VT) &&
3372 TLI.isOperationLegalOrCustom(ISD::FNEG, VT) &&
3373 "Don't know how to expand this FP subtraction!");
3374 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1));
3375 Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1);
3376 Results.push_back(Tmp1);
3380 EVT VT = Node->getValueType(0);
3381 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3382 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3383 "Don't know how to expand this subtraction!");
3384 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3385 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
3386 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, VT));
3387 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3392 EVT VT = Node->getValueType(0);
3393 bool isSigned = Node->getOpcode() == ISD::SREM;
3394 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3395 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3396 Tmp2 = Node->getOperand(0);
3397 Tmp3 = Node->getOperand(1);
3398 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3399 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3400 // If div is legal, it's better to do the normal expansion
3401 !TLI.isOperationLegalOrCustom(DivOpc, Node->getValueType(0)) &&
3402 useDivRem(Node, isSigned, false))) {
3403 SDVTList VTs = DAG.getVTList(VT, VT);
3404 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
3405 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
3407 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
3408 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3409 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3410 } else if (isSigned)
3411 Tmp1 = ExpandIntLibCall(Node, true,
3413 RTLIB::SREM_I16, RTLIB::SREM_I32,
3414 RTLIB::SREM_I64, RTLIB::SREM_I128);
3416 Tmp1 = ExpandIntLibCall(Node, false,
3418 RTLIB::UREM_I16, RTLIB::UREM_I32,
3419 RTLIB::UREM_I64, RTLIB::UREM_I128);
3420 Results.push_back(Tmp1);
3425 bool isSigned = Node->getOpcode() == ISD::SDIV;
3426 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3427 EVT VT = Node->getValueType(0);
3428 SDVTList VTs = DAG.getVTList(VT, VT);
3429 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3430 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3431 useDivRem(Node, isSigned, true)))
3432 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
3433 Node->getOperand(1));
3435 Tmp1 = ExpandIntLibCall(Node, true,
3437 RTLIB::SDIV_I16, RTLIB::SDIV_I32,
3438 RTLIB::SDIV_I64, RTLIB::SDIV_I128);
3440 Tmp1 = ExpandIntLibCall(Node, false,
3442 RTLIB::UDIV_I16, RTLIB::UDIV_I32,
3443 RTLIB::UDIV_I64, RTLIB::UDIV_I128);
3444 Results.push_back(Tmp1);
3449 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
3451 EVT VT = Node->getValueType(0);
3452 SDVTList VTs = DAG.getVTList(VT, VT);
3453 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
3454 "If this wasn't legal, it shouldn't have been created!");
3455 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
3456 Node->getOperand(1));
3457 Results.push_back(Tmp1.getValue(1));
3462 // Expand into divrem libcall
3463 ExpandDivRemLibCall(Node, Results);
3466 EVT VT = Node->getValueType(0);
3467 SDVTList VTs = DAG.getVTList(VT, VT);
3468 // See if multiply or divide can be lowered using two-result operations.
3469 // We just need the low half of the multiply; try both the signed
3470 // and unsigned forms. If the target supports both SMUL_LOHI and
3471 // UMUL_LOHI, form a preference by checking which forms of plain
3472 // MULH it supports.
3473 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3474 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3475 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3476 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3477 unsigned OpToUse = 0;
3478 if (HasSMUL_LOHI && !HasMULHS) {
3479 OpToUse = ISD::SMUL_LOHI;
3480 } else if (HasUMUL_LOHI && !HasMULHU) {
3481 OpToUse = ISD::UMUL_LOHI;
3482 } else if (HasSMUL_LOHI) {
3483 OpToUse = ISD::SMUL_LOHI;
3484 } else if (HasUMUL_LOHI) {
3485 OpToUse = ISD::UMUL_LOHI;
3488 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
3489 Node->getOperand(1)));
3492 Tmp1 = ExpandIntLibCall(Node, false,
3494 RTLIB::MUL_I16, RTLIB::MUL_I32,
3495 RTLIB::MUL_I64, RTLIB::MUL_I128);
3496 Results.push_back(Tmp1);
3501 SDValue LHS = Node->getOperand(0);
3502 SDValue RHS = Node->getOperand(1);
3503 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3504 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3506 Results.push_back(Sum);
3507 EVT OType = Node->getValueType(1);
3509 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
3511 // LHSSign -> LHS >= 0
3512 // RHSSign -> RHS >= 0
3513 // SumSign -> Sum >= 0
3516 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3518 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3520 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3521 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3522 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
3523 Node->getOpcode() == ISD::SADDO ?
3524 ISD::SETEQ : ISD::SETNE);
3526 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3527 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3529 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3530 Results.push_back(Cmp);
3535 SDValue LHS = Node->getOperand(0);
3536 SDValue RHS = Node->getOperand(1);
3537 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
3538 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3540 Results.push_back(Sum);
3541 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS,
3542 Node->getOpcode () == ISD::UADDO ?
3543 ISD::SETULT : ISD::SETUGT));
3548 EVT VT = Node->getValueType(0);
3549 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
3550 SDValue LHS = Node->getOperand(0);
3551 SDValue RHS = Node->getOperand(1);
3554 static const unsigned Ops[2][3] =
3555 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
3556 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
3557 bool isSigned = Node->getOpcode() == ISD::SMULO;
3558 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3559 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3560 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3561 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3562 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3564 TopHalf = BottomHalf.getValue(1);
3565 } else if (TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(),
3566 VT.getSizeInBits() * 2))) {
3567 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
3568 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
3569 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
3570 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3571 DAG.getIntPtrConstant(0));
3572 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3573 DAG.getIntPtrConstant(1));
3575 // We can fall back to a libcall with an illegal type for the MUL if we
3576 // have a libcall big enough.
3577 // Also, we can fall back to a division in some cases, but that's a big
3578 // performance hit in the general case.
3579 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3580 if (WideVT == MVT::i16)
3581 LC = RTLIB::MUL_I16;
3582 else if (WideVT == MVT::i32)
3583 LC = RTLIB::MUL_I32;
3584 else if (WideVT == MVT::i64)
3585 LC = RTLIB::MUL_I64;
3586 else if (WideVT == MVT::i128)
3587 LC = RTLIB::MUL_I128;
3588 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!");
3590 // The high part is obtained by SRA'ing all but one of the bits of low
3592 unsigned LoSize = VT.getSizeInBits();
3593 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, RHS,
3594 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
3595 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, VT, LHS,
3596 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
3598 // Here we're passing the 2 arguments explicitly as 4 arguments that are
3599 // pre-lowered to the correct types. This all depends upon WideVT not
3600 // being a legal type for the architecture and thus has to be split to
3602 SDValue Args[] = { LHS, HiLHS, RHS, HiRHS };
3603 SDValue Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl);
3604 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3605 DAG.getIntPtrConstant(0));
3606 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3607 DAG.getIntPtrConstant(1));
3608 // Ret is a node with an illegal type. Because such things are not
3609 // generally permitted during this phase of legalization, delete the
3610 // node. The above EXTRACT_ELEMENT nodes should have been folded.
3611 DAG.DeleteNode(Ret.getNode());
3615 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1,
3616 TLI.getShiftAmountTy(BottomHalf.getValueType()));
3617 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3618 TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf, Tmp1,
3621 TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf,
3622 DAG.getConstant(0, VT), ISD::SETNE);
3624 Results.push_back(BottomHalf);
3625 Results.push_back(TopHalf);
3628 case ISD::BUILD_PAIR: {
3629 EVT PairTy = Node->getValueType(0);
3630 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3631 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3632 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
3633 DAG.getConstant(PairTy.getSizeInBits()/2,
3634 TLI.getShiftAmountTy(PairTy)));
3635 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3639 Tmp1 = Node->getOperand(0);
3640 Tmp2 = Node->getOperand(1);
3641 Tmp3 = Node->getOperand(2);
3642 if (Tmp1.getOpcode() == ISD::SETCC) {
3643 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3645 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3647 Tmp1 = DAG.getSelectCC(dl, Tmp1,
3648 DAG.getConstant(0, Tmp1.getValueType()),
3649 Tmp2, Tmp3, ISD::SETNE);
3651 Results.push_back(Tmp1);
3654 SDValue Chain = Node->getOperand(0);
3655 SDValue Table = Node->getOperand(1);
3656 SDValue Index = Node->getOperand(2);
3658 EVT PTy = TLI.getPointerTy();
3660 const DataLayout &TD = *TLI.getDataLayout();
3661 unsigned EntrySize =
3662 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
3664 Index = DAG.getNode(ISD::MUL, dl, Index.getValueType(),
3665 Index, DAG.getConstant(EntrySize, Index.getValueType()));
3666 SDValue Addr = DAG.getNode(ISD::ADD, dl, Index.getValueType(),
3669 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
3670 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
3671 MachinePointerInfo::getJumpTable(), MemVT,
3674 if (TM.getRelocationModel() == Reloc::PIC_) {
3675 // For PIC, the sequence is:
3676 // BRIND(load(Jumptable + index) + RelocBase)
3677 // RelocBase can be JumpTable, GOT or some sort of global base.
3678 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3679 TLI.getPICJumpTableRelocBase(Table, DAG));
3681 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
3682 Results.push_back(Tmp1);
3686 // Expand brcond's setcc into its constituent parts and create a BR_CC
3688 Tmp1 = Node->getOperand(0);
3689 Tmp2 = Node->getOperand(1);
3690 if (Tmp2.getOpcode() == ISD::SETCC) {
3691 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3692 Tmp1, Tmp2.getOperand(2),
3693 Tmp2.getOperand(0), Tmp2.getOperand(1),
3694 Node->getOperand(2));
3696 // We test only the i1 bit. Skip the AND if UNDEF.
3697 Tmp3 = (Tmp2.getOpcode() == ISD::UNDEF) ? Tmp2 :
3698 DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2,
3699 DAG.getConstant(1, Tmp2.getValueType()));
3700 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3701 DAG.getCondCode(ISD::SETNE), Tmp3,
3702 DAG.getConstant(0, Tmp3.getValueType()),
3703 Node->getOperand(2));
3705 Results.push_back(Tmp1);
3708 Tmp1 = Node->getOperand(0);
3709 Tmp2 = Node->getOperand(1);
3710 Tmp3 = Node->getOperand(2);
3711 bool Legalized = LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2,
3712 Tmp3, NeedInvert, dl);
3715 // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3716 // condition code, create a new SETCC node.
3718 Tmp1 = DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3721 // If we expanded the SETCC by inverting the condition code, then wrap
3722 // the existing SETCC in a NOT to restore the intended condition.
3724 Tmp1 = DAG.getNOT(dl, Tmp1, Tmp1->getValueType(0));
3726 Results.push_back(Tmp1);
3730 // Otherwise, SETCC for the given comparison type must be completely
3731 // illegal; expand it into a SELECT_CC.
3732 EVT VT = Node->getValueType(0);
3734 switch (TLI.getBooleanContents(VT.isVector())) {
3735 case TargetLowering::ZeroOrOneBooleanContent:
3736 case TargetLowering::UndefinedBooleanContent:
3739 case TargetLowering::ZeroOrNegativeOneBooleanContent:
3743 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3744 DAG.getConstant(TrueValue, VT), DAG.getConstant(0, VT),
3746 Results.push_back(Tmp1);
3749 case ISD::SELECT_CC: {
3750 Tmp1 = Node->getOperand(0); // LHS
3751 Tmp2 = Node->getOperand(1); // RHS
3752 Tmp3 = Node->getOperand(2); // True
3753 Tmp4 = Node->getOperand(3); // False
3754 SDValue CC = Node->getOperand(4);
3756 bool Legalized = false;
3757 // Try to legalize by inverting the condition. This is for targets that
3758 // might support an ordered version of a condition, but not the unordered
3759 // version (or vice versa).
3760 ISD::CondCode InvCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
3761 Tmp1.getValueType().isInteger());
3762 if (TLI.isCondCodeLegal(InvCC, Tmp1.getSimpleValueType())) {
3763 // Use the new condition code and swap true and false
3765 Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp4, Tmp3, InvCC);
3767 // If The inverse is not legal, then try to swap the arguments using
3768 // the inverse condition code.
3769 ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(InvCC);
3770 if (TLI.isCondCodeLegal(SwapInvCC, Tmp1.getSimpleValueType())) {
3771 // The swapped inverse condition is legal, so swap true and false,
3774 Tmp1 = DAG.getSelectCC(dl, Tmp2, Tmp1, Tmp4, Tmp3, SwapInvCC);
3779 Legalized = LegalizeSetCCCondCode(
3780 getSetCCResultType(Tmp1.getValueType()), Tmp1, Tmp2, CC, NeedInvert,
3783 assert(Legalized && "Can't legalize SELECT_CC with legal condition!");
3785 // If we expanded the SETCC by inverting the condition code, then swap
3786 // the True/False operands to match.
3788 std::swap(Tmp3, Tmp4);
3790 // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3791 // condition code, create a new SELECT_CC node.
3793 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0),
3794 Tmp1, Tmp2, Tmp3, Tmp4, CC);
3796 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3797 CC = DAG.getCondCode(ISD::SETNE);
3798 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1,
3799 Tmp2, Tmp3, Tmp4, CC);
3802 Results.push_back(Tmp1);
3806 Tmp1 = Node->getOperand(0); // Chain
3807 Tmp2 = Node->getOperand(2); // LHS
3808 Tmp3 = Node->getOperand(3); // RHS
3809 Tmp4 = Node->getOperand(1); // CC
3811 bool Legalized = LegalizeSetCCCondCode(getSetCCResultType(
3812 Tmp2.getValueType()), Tmp2, Tmp3, Tmp4, NeedInvert, dl);
3814 assert(Legalized && "Can't legalize BR_CC with legal condition!");
3816 // If we expanded the SETCC by inverting the condition code, then wrap
3817 // the existing SETCC in a NOT to restore the intended condition.
3819 Tmp4 = DAG.getNOT(dl, Tmp4, Tmp4->getValueType(0));
3821 // If we expanded the SETCC by swapping LHS and RHS, create a new BR_CC
3823 if (Tmp4.getNode()) {
3824 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1,
3825 Tmp4, Tmp2, Tmp3, Node->getOperand(4));
3827 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
3828 Tmp4 = DAG.getCondCode(ISD::SETNE);
3829 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4,
3830 Tmp2, Tmp3, Node->getOperand(4));
3832 Results.push_back(Tmp1);
3835 case ISD::BUILD_VECTOR:
3836 Results.push_back(ExpandBUILD_VECTOR(Node));
3841 // Scalarize vector SRA/SRL/SHL.
3842 EVT VT = Node->getValueType(0);
3843 assert(VT.isVector() && "Unable to legalize non-vector shift");
3844 assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
3845 unsigned NumElem = VT.getVectorNumElements();
3847 SmallVector<SDValue, 8> Scalars;
3848 for (unsigned Idx = 0; Idx < NumElem; Idx++) {
3849 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3851 Node->getOperand(0), DAG.getConstant(Idx,
3852 TLI.getVectorIdxTy()));
3853 SDValue Sh = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3855 Node->getOperand(1), DAG.getConstant(Idx,
3856 TLI.getVectorIdxTy()));
3857 Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
3858 VT.getScalarType(), Ex, Sh));
3861 DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0),
3862 &Scalars[0], Scalars.size());
3863 ReplaceNode(SDValue(Node, 0), Result);
3866 case ISD::GLOBAL_OFFSET_TABLE:
3867 case ISD::GlobalAddress:
3868 case ISD::GlobalTLSAddress:
3869 case ISD::ExternalSymbol:
3870 case ISD::ConstantPool:
3871 case ISD::JumpTable:
3872 case ISD::INTRINSIC_W_CHAIN:
3873 case ISD::INTRINSIC_WO_CHAIN:
3874 case ISD::INTRINSIC_VOID:
3875 // FIXME: Custom lowering for these operations shouldn't return null!
3879 // Replace the original node with the legalized result.
3880 if (!Results.empty())
3881 ReplaceNode(Node, Results.data());
3884 void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
3885 SmallVector<SDValue, 8> Results;
3886 MVT OVT = Node->getSimpleValueType(0);
3887 if (Node->getOpcode() == ISD::UINT_TO_FP ||
3888 Node->getOpcode() == ISD::SINT_TO_FP ||
3889 Node->getOpcode() == ISD::SETCC) {
3890 OVT = Node->getOperand(0).getSimpleValueType();
3892 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3894 SDValue Tmp1, Tmp2, Tmp3;
3895 switch (Node->getOpcode()) {
3897 case ISD::CTTZ_ZERO_UNDEF:
3899 case ISD::CTLZ_ZERO_UNDEF:
3901 // Zero extend the argument.
3902 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3903 // Perform the larger operation. For CTPOP and CTTZ_ZERO_UNDEF, this is
3904 // already the correct result.
3905 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
3906 if (Node->getOpcode() == ISD::CTTZ) {
3907 // FIXME: This should set a bit in the zero extended value instead.
3908 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT),
3909 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
3911 Tmp1 = DAG.getSelect(dl, NVT, Tmp2,
3912 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3913 } else if (Node->getOpcode() == ISD::CTLZ ||
3914 Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) {
3915 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3916 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
3917 DAG.getConstant(NVT.getSizeInBits() -
3918 OVT.getSizeInBits(), NVT));
3920 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
3923 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3924 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3925 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
3926 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
3927 DAG.getConstant(DiffBits, TLI.getShiftAmountTy(NVT)));
3928 Results.push_back(Tmp1);
3931 case ISD::FP_TO_UINT:
3932 case ISD::FP_TO_SINT:
3933 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
3934 Node->getOpcode() == ISD::FP_TO_SINT, dl);
3935 Results.push_back(Tmp1);
3937 case ISD::UINT_TO_FP:
3938 case ISD::SINT_TO_FP:
3939 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
3940 Node->getOpcode() == ISD::SINT_TO_FP, dl);
3941 Results.push_back(Tmp1);
3944 SDValue Chain = Node->getOperand(0); // Get the chain.
3945 SDValue Ptr = Node->getOperand(1); // Get the pointer.
3948 if (OVT.isVector()) {
3949 TruncOp = ISD::BITCAST;
3951 assert(OVT.isInteger()
3952 && "VAARG promotion is supported only for vectors or integer types");
3953 TruncOp = ISD::TRUNCATE;
3956 // Perform the larger operation, then convert back
3957 Tmp1 = DAG.getVAArg(NVT, dl, Chain, Ptr, Node->getOperand(2),
3958 Node->getConstantOperandVal(3));
3959 Chain = Tmp1.getValue(1);
3961 Tmp2 = DAG.getNode(TruncOp, dl, OVT, Tmp1);
3963 // Modified the chain result - switch anything that used the old chain to
3965 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp2);
3966 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
3973 unsigned ExtOp, TruncOp;
3974 if (OVT.isVector()) {
3975 ExtOp = ISD::BITCAST;
3976 TruncOp = ISD::BITCAST;
3978 assert(OVT.isInteger() && "Cannot promote logic operation");
3979 ExtOp = ISD::ANY_EXTEND;
3980 TruncOp = ISD::TRUNCATE;
3982 // Promote each of the values to the new type.
3983 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3984 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3985 // Perform the larger operation, then convert back
3986 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3987 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
3991 unsigned ExtOp, TruncOp;
3992 if (Node->getValueType(0).isVector()) {
3993 ExtOp = ISD::BITCAST;
3994 TruncOp = ISD::BITCAST;
3995 } else if (Node->getValueType(0).isInteger()) {
3996 ExtOp = ISD::ANY_EXTEND;
3997 TruncOp = ISD::TRUNCATE;
3999 ExtOp = ISD::FP_EXTEND;
4000 TruncOp = ISD::FP_ROUND;
4002 Tmp1 = Node->getOperand(0);
4003 // Promote each of the values to the new type.
4004 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4005 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
4006 // Perform the larger operation, then round down.
4007 Tmp1 = DAG.getSelect(dl, NVT, Tmp1, Tmp2, Tmp3);
4008 if (TruncOp != ISD::FP_ROUND)
4009 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
4011 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
4012 DAG.getIntPtrConstant(0));
4013 Results.push_back(Tmp1);
4016 case ISD::VECTOR_SHUFFLE: {
4017 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
4019 // Cast the two input vectors.
4020 Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
4021 Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
4023 // Convert the shuffle mask to the right # elements.
4024 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
4025 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
4026 Results.push_back(Tmp1);
4030 unsigned ExtOp = ISD::FP_EXTEND;
4031 if (NVT.isInteger()) {
4032 ISD::CondCode CCCode =
4033 cast<CondCodeSDNode>(Node->getOperand(2))->get();
4034 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4036 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4037 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4038 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
4039 Tmp1, Tmp2, Node->getOperand(2)));
4045 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4046 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
4047 Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4048 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4049 Tmp3, DAG.getIntPtrConstant(0)));
4056 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4057 Tmp2 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4058 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4059 Tmp2, DAG.getIntPtrConstant(0)));
4064 // Replace the original node with the legalized result.
4065 if (!Results.empty())
4066 ReplaceNode(Node, Results.data());
4069 // SelectionDAG::Legalize - This is the entry point for the file.
4071 void SelectionDAG::Legalize() {
4072 /// run - This is the main entry point to this class.
4074 SelectionDAGLegalize(*this).LegalizeDAG();