1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/CodeGen/PseudoSourceValue.h"
20 #include "llvm/Target/TargetFrameInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/Target/TargetData.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/Target/TargetSubtarget.h"
26 #include "llvm/CallingConv.h"
27 #include "llvm/Constants.h"
28 #include "llvm/DerivedTypes.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Compiler.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/ADT/DenseMap.h"
33 #include "llvm/ADT/SmallVector.h"
34 #include "llvm/ADT/SmallPtrSet.h"
38 //===----------------------------------------------------------------------===//
39 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
40 /// hacks on it until the target machine can handle it. This involves
41 /// eliminating value sizes the machine cannot handle (promoting small sizes to
42 /// large sizes or splitting up large values into small values) as well as
43 /// eliminating operations the machine cannot handle.
45 /// This code also does a small amount of optimization and recognition of idioms
46 /// as part of its processing. For example, if a target does not support a
47 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
48 /// will attempt merge setcc and brc instructions into brcc's.
51 class VISIBILITY_HIDDEN SelectionDAGLegalize {
55 // Libcall insertion helpers.
57 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
58 /// legalized. We use this to ensure that calls are properly serialized
59 /// against each other, including inserted libcalls.
60 SDValue LastCALLSEQ_END;
62 /// IsLegalizingCall - This member is used *only* for purposes of providing
63 /// helpful assertions that a libcall isn't created while another call is
64 /// being legalized (which could lead to non-serialized call sequences).
65 bool IsLegalizingCall;
68 Legal, // The target natively supports this operation.
69 Promote, // This operation should be executed in a larger type.
70 Expand // Try to expand this to other ops, otherwise use a libcall.
73 /// ValueTypeActions - This is a bitvector that contains two bits for each
74 /// value type, where the two bits correspond to the LegalizeAction enum.
75 /// This can be queried with "getTypeAction(VT)".
76 TargetLowering::ValueTypeActionImpl ValueTypeActions;
78 /// LegalizedNodes - For nodes that are of legal width, and that have more
79 /// than one use, this map indicates what regularized operand to use. This
80 /// allows us to avoid legalizing the same thing more than once.
81 DenseMap<SDValue, SDValue> LegalizedNodes;
83 /// PromotedNodes - For nodes that are below legal width, and that have more
84 /// than one use, this map indicates what promoted value to use. This allows
85 /// us to avoid promoting the same thing more than once.
86 DenseMap<SDValue, SDValue> PromotedNodes;
88 /// ExpandedNodes - For nodes that need to be expanded this map indicates
89 /// which operands are the expanded version of the input. This allows
90 /// us to avoid expanding the same node more than once.
91 DenseMap<SDValue, std::pair<SDValue, SDValue> > ExpandedNodes;
93 /// SplitNodes - For vector nodes that need to be split, this map indicates
94 /// which operands are the split version of the input. This allows us
95 /// to avoid splitting the same node more than once.
96 std::map<SDValue, std::pair<SDValue, SDValue> > SplitNodes;
98 /// ScalarizedNodes - For nodes that need to be converted from vector types to
99 /// scalar types, this contains the mapping of ones we have already
100 /// processed to the result.
101 std::map<SDValue, SDValue> ScalarizedNodes;
103 /// WidenNodes - For nodes that need to be widened from one vector type to
104 /// another, this contains the mapping of those that we have already widen.
105 /// This allows us to avoid widening more than once.
106 std::map<SDValue, SDValue> WidenNodes;
108 void AddLegalizedOperand(SDValue From, SDValue To) {
109 LegalizedNodes.insert(std::make_pair(From, To));
110 // If someone requests legalization of the new node, return itself.
112 LegalizedNodes.insert(std::make_pair(To, To));
114 void AddPromotedOperand(SDValue From, SDValue To) {
115 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
116 assert(isNew && "Got into the map somehow?");
117 // If someone requests legalization of the new node, return itself.
118 LegalizedNodes.insert(std::make_pair(To, To));
120 void AddWidenedOperand(SDValue From, SDValue To) {
121 bool isNew = WidenNodes.insert(std::make_pair(From, To)).second;
122 assert(isNew && "Got into the map somehow?");
123 // If someone requests legalization of the new node, return itself.
124 LegalizedNodes.insert(std::make_pair(To, To));
128 explicit SelectionDAGLegalize(SelectionDAG &DAG);
130 /// getTypeAction - Return how we should legalize values of this type, either
131 /// it is already legal or we need to expand it into multiple registers of
132 /// smaller integer type, or we need to promote it to a larger type.
133 LegalizeAction getTypeAction(MVT VT) const {
134 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
137 /// isTypeLegal - Return true if this type is legal on this target.
139 bool isTypeLegal(MVT VT) const {
140 return getTypeAction(VT) == Legal;
146 /// HandleOp - Legalize, Promote, or Expand the specified operand as
147 /// appropriate for its type.
148 void HandleOp(SDValue Op);
150 /// LegalizeOp - We know that the specified value has a legal type.
151 /// Recursively ensure that the operands have legal types, then return the
153 SDValue LegalizeOp(SDValue O);
155 /// UnrollVectorOp - We know that the given vector has a legal type, however
156 /// the operation it performs is not legal and is an operation that we have
157 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
158 /// operating on each element individually.
159 SDValue UnrollVectorOp(SDValue O);
161 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
162 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
163 /// is necessary to spill the vector being inserted into to memory, perform
164 /// the insert there, and then read the result back.
165 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
168 /// PromoteOp - Given an operation that produces a value in an invalid type,
169 /// promote it to compute the value into a larger type. The produced value
170 /// will have the correct bits for the low portion of the register, but no
171 /// guarantee is made about the top bits: it may be zero, sign-extended, or
173 SDValue PromoteOp(SDValue O);
175 /// ExpandOp - Expand the specified SDValue into its two component pieces
176 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
177 /// the LegalizedNodes map is filled in for any results that are not expanded,
178 /// the ExpandedNodes map is filled in for any results that are expanded, and
179 /// the Lo/Hi values are returned. This applies to integer types and Vector
181 void ExpandOp(SDValue O, SDValue &Lo, SDValue &Hi);
183 /// WidenVectorOp - Widen a vector operation to a wider type given by WidenVT
184 /// (e.g., v3i32 to v4i32). The produced value will have the correct value
185 /// for the existing elements but no guarantee is made about the new elements
186 /// at the end of the vector: it may be zero, ones, or garbage. This is useful
187 /// when we have an instruction operating on an illegal vector type and we
188 /// want to widen it to do the computation on a legal wider vector type.
189 SDValue WidenVectorOp(SDValue Op, MVT WidenVT);
191 /// SplitVectorOp - Given an operand of vector type, break it down into
192 /// two smaller values.
193 void SplitVectorOp(SDValue O, SDValue &Lo, SDValue &Hi);
195 /// ScalarizeVectorOp - Given an operand of single-element vector type
196 /// (e.g. v1f32), convert it into the equivalent operation that returns a
197 /// scalar (e.g. f32) value.
198 SDValue ScalarizeVectorOp(SDValue O);
200 /// Useful 16 element vector type that is used to pass operands for widening.
201 typedef SmallVector<SDValue, 16> SDValueVector;
203 /// LoadWidenVectorOp - Load a vector for a wider type. Returns true if
204 /// the LdChain contains a single load and false if it contains a token
205 /// factor for multiple loads. It takes
206 /// Result: location to return the result
207 /// LdChain: location to return the load chain
208 /// Op: load operation to widen
209 /// NVT: widen vector result type we want for the load
210 bool LoadWidenVectorOp(SDValue& Result, SDValue& LdChain,
211 SDValue Op, MVT NVT);
213 /// Helper genWidenVectorLoads - Helper function to generate a set of
214 /// loads to load a vector with a resulting wider type. It takes
215 /// LdChain: list of chains for the load we have generated
216 /// Chain: incoming chain for the ld vector
217 /// BasePtr: base pointer to load from
218 /// SV: memory disambiguation source value
219 /// SVOffset: memory disambiugation offset
220 /// Alignment: alignment of the memory
221 /// isVolatile: volatile load
222 /// LdWidth: width of memory that we want to load
223 /// ResType: the wider result result type for the resulting loaded vector
224 SDValue genWidenVectorLoads(SDValueVector& LdChain, SDValue Chain,
225 SDValue BasePtr, const Value *SV,
226 int SVOffset, unsigned Alignment,
227 bool isVolatile, unsigned LdWidth,
230 /// StoreWidenVectorOp - Stores a widen vector into non widen memory
231 /// location. It takes
232 /// ST: store node that we want to replace
233 /// Chain: incoming store chain
234 /// BasePtr: base address of where we want to store into
235 SDValue StoreWidenVectorOp(StoreSDNode *ST, SDValue Chain,
238 /// Helper genWidenVectorStores - Helper function to generate a set of
239 /// stores to store a widen vector into non widen memory
241 // StChain: list of chains for the stores we have generated
242 // Chain: incoming chain for the ld vector
243 // BasePtr: base pointer to load from
244 // SV: memory disambiguation source value
245 // SVOffset: memory disambiugation offset
246 // Alignment: alignment of the memory
247 // isVolatile: volatile lod
248 // ValOp: value to store
249 // StWidth: width of memory that we want to store
250 void genWidenVectorStores(SDValueVector& StChain, SDValue Chain,
251 SDValue BasePtr, const Value *SV,
252 int SVOffset, unsigned Alignment,
253 bool isVolatile, SDValue ValOp,
256 /// isShuffleLegal - Return non-null if a vector shuffle is legal with the
257 /// specified mask and type. Targets can specify exactly which masks they
258 /// support and the code generator is tasked with not creating illegal masks.
260 /// Note that this will also return true for shuffles that are promoted to a
263 /// If this is a legal shuffle, this method returns the (possibly promoted)
264 /// build_vector Mask. If it's not a legal shuffle, it returns null.
265 SDNode *isShuffleLegal(MVT VT, SDValue Mask) const;
267 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
268 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
270 void LegalizeSetCCOperands(SDValue &LHS, SDValue &RHS, SDValue &CC);
271 void LegalizeSetCCCondCode(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC);
272 void LegalizeSetCC(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC) {
273 LegalizeSetCCOperands(LHS, RHS, CC);
274 LegalizeSetCCCondCode(VT, LHS, RHS, CC);
277 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned,
279 SDValue ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source);
281 SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT);
282 SDValue ExpandBUILD_VECTOR(SDNode *Node);
283 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
284 SDValue LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op);
285 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT);
286 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, bool isSigned);
287 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned);
289 SDValue ExpandBSWAP(SDValue Op);
290 SDValue ExpandBitCount(unsigned Opc, SDValue Op);
291 bool ExpandShift(unsigned Opc, SDValue Op, SDValue Amt,
292 SDValue &Lo, SDValue &Hi);
293 void ExpandShiftParts(unsigned NodeOp, SDValue Op, SDValue Amt,
294 SDValue &Lo, SDValue &Hi);
296 SDValue ExpandEXTRACT_SUBVECTOR(SDValue Op);
297 SDValue ExpandEXTRACT_VECTOR_ELT(SDValue Op);
301 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
302 /// specified mask and type. Targets can specify exactly which masks they
303 /// support and the code generator is tasked with not creating illegal masks.
305 /// Note that this will also return true for shuffles that are promoted to a
307 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDValue Mask) const {
308 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
310 case TargetLowering::Legal:
311 case TargetLowering::Custom:
313 case TargetLowering::Promote: {
314 // If this is promoted to a different type, convert the shuffle mask and
315 // ask if it is legal in the promoted type!
316 MVT NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
317 MVT EltVT = NVT.getVectorElementType();
319 // If we changed # elements, change the shuffle mask.
320 unsigned NumEltsGrowth =
321 NVT.getVectorNumElements() / VT.getVectorNumElements();
322 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
323 if (NumEltsGrowth > 1) {
324 // Renumber the elements.
325 SmallVector<SDValue, 8> Ops;
326 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
327 SDValue InOp = Mask.getOperand(i);
328 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
329 if (InOp.getOpcode() == ISD::UNDEF)
330 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
332 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getZExtValue();
333 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, EltVT));
337 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
343 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.getNode() : 0;
346 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
347 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
348 ValueTypeActions(TLI.getValueTypeActions()) {
349 assert(MVT::LAST_VALUETYPE <= 32 &&
350 "Too many value types for ValueTypeActions to hold!");
353 void SelectionDAGLegalize::LegalizeDAG() {
354 LastCALLSEQ_END = DAG.getEntryNode();
355 IsLegalizingCall = false;
357 // The legalize process is inherently a bottom-up recursive process (users
358 // legalize their uses before themselves). Given infinite stack space, we
359 // could just start legalizing on the root and traverse the whole graph. In
360 // practice however, this causes us to run out of stack space on large basic
361 // blocks. To avoid this problem, compute an ordering of the nodes where each
362 // node is only legalized after all of its operands are legalized.
363 DAG.AssignTopologicalOrder();
364 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
365 E = prior(DAG.allnodes_end()); I != next(E); ++I)
366 HandleOp(SDValue(I, 0));
368 // Finally, it's possible the root changed. Get the new root.
369 SDValue OldRoot = DAG.getRoot();
370 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
371 DAG.setRoot(LegalizedNodes[OldRoot]);
373 ExpandedNodes.clear();
374 LegalizedNodes.clear();
375 PromotedNodes.clear();
377 ScalarizedNodes.clear();
380 // Remove dead nodes now.
381 DAG.RemoveDeadNodes();
385 /// FindCallEndFromCallStart - Given a chained node that is part of a call
386 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
387 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
388 if (Node->getOpcode() == ISD::CALLSEQ_END)
390 if (Node->use_empty())
391 return 0; // No CallSeqEnd
393 // The chain is usually at the end.
394 SDValue TheChain(Node, Node->getNumValues()-1);
395 if (TheChain.getValueType() != MVT::Other) {
396 // Sometimes it's at the beginning.
397 TheChain = SDValue(Node, 0);
398 if (TheChain.getValueType() != MVT::Other) {
399 // Otherwise, hunt for it.
400 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
401 if (Node->getValueType(i) == MVT::Other) {
402 TheChain = SDValue(Node, i);
406 // Otherwise, we walked into a node without a chain.
407 if (TheChain.getValueType() != MVT::Other)
412 for (SDNode::use_iterator UI = Node->use_begin(),
413 E = Node->use_end(); UI != E; ++UI) {
415 // Make sure to only follow users of our token chain.
417 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
418 if (User->getOperand(i) == TheChain)
419 if (SDNode *Result = FindCallEndFromCallStart(User))
425 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
426 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
427 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
428 assert(Node && "Didn't find callseq_start for a call??");
429 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
431 assert(Node->getOperand(0).getValueType() == MVT::Other &&
432 "Node doesn't have a token chain argument!");
433 return FindCallStartFromCallEnd(Node->getOperand(0).getNode());
436 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
437 /// see if any uses can reach Dest. If no dest operands can get to dest,
438 /// legalize them, legalize ourself, and return false, otherwise, return true.
440 /// Keep track of the nodes we fine that actually do lead to Dest in
441 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
443 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
444 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
445 if (N == Dest) return true; // N certainly leads to Dest :)
447 // If we've already processed this node and it does lead to Dest, there is no
448 // need to reprocess it.
449 if (NodesLeadingTo.count(N)) return true;
451 // If the first result of this node has been already legalized, then it cannot
453 switch (getTypeAction(N->getValueType(0))) {
455 if (LegalizedNodes.count(SDValue(N, 0))) return false;
458 if (PromotedNodes.count(SDValue(N, 0))) return false;
461 if (ExpandedNodes.count(SDValue(N, 0))) return false;
465 // Okay, this node has not already been legalized. Check and legalize all
466 // operands. If none lead to Dest, then we can legalize this node.
467 bool OperandsLeadToDest = false;
468 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
469 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
470 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo);
472 if (OperandsLeadToDest) {
473 NodesLeadingTo.insert(N);
477 // Okay, this node looks safe, legalize it and return false.
478 HandleOp(SDValue(N, 0));
482 /// HandleOp - Legalize, Promote, Widen, or Expand the specified operand as
483 /// appropriate for its type.
484 void SelectionDAGLegalize::HandleOp(SDValue Op) {
485 MVT VT = Op.getValueType();
486 switch (getTypeAction(VT)) {
487 default: assert(0 && "Bad type action!");
488 case Legal: (void)LegalizeOp(Op); break;
490 if (!VT.isVector()) {
495 // See if we can widen otherwise use Expand to either scalarize or split
496 MVT WidenVT = TLI.getWidenVectorType(VT);
497 if (WidenVT != MVT::Other) {
498 (void) WidenVectorOp(Op, WidenVT);
501 // else fall thru to expand since we can't widen the vector
504 if (!VT.isVector()) {
505 // If this is an illegal scalar, expand it into its two component
508 if (Op.getOpcode() == ISD::TargetConstant)
509 break; // Allow illegal target nodes.
511 } else if (VT.getVectorNumElements() == 1) {
512 // If this is an illegal single element vector, convert it to a
514 (void)ScalarizeVectorOp(Op);
516 // This is an illegal multiple element vector.
517 // Split it in half and legalize both parts.
519 SplitVectorOp(Op, X, Y);
525 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
526 /// a load from the constant pool.
527 static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
528 SelectionDAG &DAG, TargetLowering &TLI) {
531 // If a FP immediate is precise when represented as a float and if the
532 // target can do an extending load from float to double, we put it into
533 // the constant pool as a float, even if it's is statically typed as a
534 // double. This shrinks FP constants and canonicalizes them for targets where
535 // an FP extending load is the same cost as a normal load (such as on the x87
536 // fp stack or PPC FP unit).
537 MVT VT = CFP->getValueType(0);
538 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
540 if (VT!=MVT::f64 && VT!=MVT::f32)
541 assert(0 && "Invalid type expansion");
542 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
543 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
548 while (SVT != MVT::f32) {
549 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1);
550 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
551 // Only do this if the target has a native EXTLOAD instruction from
553 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
554 TLI.ShouldShrinkFPConstant(OrigVT)) {
555 const Type *SType = SVT.getTypeForMVT();
556 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
562 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
563 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
565 return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, DAG.getEntryNode(),
566 CPIdx, PseudoSourceValue::getConstantPool(),
567 0, VT, false, Alignment);
568 return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx,
569 PseudoSourceValue::getConstantPool(), 0, false, Alignment);
573 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
576 SDValue ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT,
577 SelectionDAG &DAG, TargetLowering &TLI) {
578 MVT VT = Node->getValueType(0);
579 MVT SrcVT = Node->getOperand(1).getValueType();
580 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
581 "fcopysign expansion only supported for f32 and f64");
582 MVT SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
584 // First get the sign bit of second operand.
585 SDValue Mask1 = (SrcVT == MVT::f64)
586 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
587 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
588 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
589 SDValue SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
590 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
591 // Shift right or sign-extend it if the two operands have different types.
592 int SizeDiff = SrcNVT.getSizeInBits() - NVT.getSizeInBits();
594 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
595 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
596 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
597 } else if (SizeDiff < 0) {
598 SignBit = DAG.getNode(ISD::ZERO_EXTEND, NVT, SignBit);
599 SignBit = DAG.getNode(ISD::SHL, NVT, SignBit,
600 DAG.getConstant(-SizeDiff, TLI.getShiftAmountTy()));
603 // Clear the sign bit of first operand.
604 SDValue Mask2 = (VT == MVT::f64)
605 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
606 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
607 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
608 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
609 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
611 // Or the value with the sign bit.
612 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
616 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
618 SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
619 TargetLowering &TLI) {
620 SDValue Chain = ST->getChain();
621 SDValue Ptr = ST->getBasePtr();
622 SDValue Val = ST->getValue();
623 MVT VT = Val.getValueType();
624 int Alignment = ST->getAlignment();
625 int SVOffset = ST->getSrcValueOffset();
626 if (ST->getMemoryVT().isFloatingPoint() ||
627 ST->getMemoryVT().isVector()) {
628 // Expand to a bitconvert of the value to the integer type of the
629 // same size, then a (misaligned) int store.
631 if (VT.is128BitVector() || VT == MVT::ppcf128 || VT == MVT::f128)
633 else if (VT.is64BitVector() || VT==MVT::f64)
635 else if (VT==MVT::f32)
638 assert(0 && "Unaligned store of unsupported type");
640 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val);
641 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(),
642 SVOffset, ST->isVolatile(), Alignment);
644 assert(ST->getMemoryVT().isInteger() &&
645 !ST->getMemoryVT().isVector() &&
646 "Unaligned store of unknown type.");
647 // Get the half-size VT
649 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1);
650 int NumBits = NewStoredVT.getSizeInBits();
651 int IncrementSize = NumBits / 8;
653 // Divide the stored value in two parts.
654 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
656 SDValue Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
658 // Store the two parts
659 SDValue Store1, Store2;
660 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr,
661 ST->getSrcValue(), SVOffset, NewStoredVT,
662 ST->isVolatile(), Alignment);
663 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
664 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
665 Alignment = MinAlign(Alignment, IncrementSize);
666 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr,
667 ST->getSrcValue(), SVOffset + IncrementSize,
668 NewStoredVT, ST->isVolatile(), Alignment);
670 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2);
673 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
675 SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
676 TargetLowering &TLI) {
677 int SVOffset = LD->getSrcValueOffset();
678 SDValue Chain = LD->getChain();
679 SDValue Ptr = LD->getBasePtr();
680 MVT VT = LD->getValueType(0);
681 MVT LoadedVT = LD->getMemoryVT();
682 if (VT.isFloatingPoint() || VT.isVector()) {
683 // Expand to a (misaligned) integer load of the same size,
684 // then bitconvert to floating point or vector.
686 if (LoadedVT.is128BitVector() ||
687 LoadedVT == MVT::ppcf128 || LoadedVT == MVT::f128)
689 else if (LoadedVT.is64BitVector() || LoadedVT == MVT::f64)
691 else if (LoadedVT == MVT::f32)
694 assert(0 && "Unaligned load of unsupported type");
696 SDValue newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(),
697 SVOffset, LD->isVolatile(),
699 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad);
700 if (VT.isFloatingPoint() && LoadedVT != VT)
701 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result);
703 SDValue Ops[] = { Result, Chain };
704 return DAG.getMergeValues(Ops, 2);
706 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
707 "Unaligned load of unsupported type.");
709 // Compute the new VT that is half the size of the old one. This is an
711 unsigned NumBits = LoadedVT.getSizeInBits();
713 NewLoadedVT = MVT::getIntegerVT(NumBits/2);
716 unsigned Alignment = LD->getAlignment();
717 unsigned IncrementSize = NumBits / 8;
718 ISD::LoadExtType HiExtType = LD->getExtensionType();
720 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
721 if (HiExtType == ISD::NON_EXTLOAD)
722 HiExtType = ISD::ZEXTLOAD;
724 // Load the value in two parts
726 if (TLI.isLittleEndian()) {
727 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
728 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
729 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
730 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
731 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(),
732 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
733 MinAlign(Alignment, IncrementSize));
735 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset,
736 NewLoadedVT,LD->isVolatile(), Alignment);
737 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
738 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
739 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
740 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
741 MinAlign(Alignment, IncrementSize));
744 // aggregate the two parts
745 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
746 SDValue Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
747 Result = DAG.getNode(ISD::OR, VT, Result, Lo);
749 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
752 SDValue Ops[] = { Result, TF };
753 return DAG.getMergeValues(Ops, 2);
756 /// UnrollVectorOp - We know that the given vector has a legal type, however
757 /// the operation it performs is not legal and is an operation that we have
758 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
759 /// operating on each element individually.
760 SDValue SelectionDAGLegalize::UnrollVectorOp(SDValue Op) {
761 MVT VT = Op.getValueType();
762 assert(isTypeLegal(VT) &&
763 "Caller should expand or promote operands that are not legal!");
764 assert(Op.getNode()->getNumValues() == 1 &&
765 "Can't unroll a vector with multiple results!");
766 unsigned NE = VT.getVectorNumElements();
767 MVT EltVT = VT.getVectorElementType();
769 SmallVector<SDValue, 8> Scalars;
770 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
771 for (unsigned i = 0; i != NE; ++i) {
772 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
773 SDValue Operand = Op.getOperand(j);
774 MVT OperandVT = Operand.getValueType();
775 if (OperandVT.isVector()) {
776 // A vector operand; extract a single element.
777 MVT OperandEltVT = OperandVT.getVectorElementType();
778 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
781 DAG.getConstant(i, MVT::i32));
783 // A scalar operand; just use it as is.
784 Operands[j] = Operand;
787 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT,
788 &Operands[0], Operands.size()));
791 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size());
794 /// GetFPLibCall - Return the right libcall for the given floating point type.
795 static RTLIB::Libcall GetFPLibCall(MVT VT,
796 RTLIB::Libcall Call_F32,
797 RTLIB::Libcall Call_F64,
798 RTLIB::Libcall Call_F80,
799 RTLIB::Libcall Call_PPCF128) {
801 VT == MVT::f32 ? Call_F32 :
802 VT == MVT::f64 ? Call_F64 :
803 VT == MVT::f80 ? Call_F80 :
804 VT == MVT::ppcf128 ? Call_PPCF128 :
805 RTLIB::UNKNOWN_LIBCALL;
808 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
809 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
810 /// is necessary to spill the vector being inserted into to memory, perform
811 /// the insert there, and then read the result back.
812 SDValue SelectionDAGLegalize::
813 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx) {
818 // If the target doesn't support this, we have to spill the input vector
819 // to a temporary stack slot, update the element, then reload it. This is
820 // badness. We could also load the value into a vector register (either
821 // with a "move to register" or "extload into register" instruction, then
822 // permute it into place, if the idx is a constant and if the idx is
823 // supported by the target.
824 MVT VT = Tmp1.getValueType();
825 MVT EltVT = VT.getVectorElementType();
826 MVT IdxVT = Tmp3.getValueType();
827 MVT PtrVT = TLI.getPointerTy();
828 SDValue StackPtr = DAG.CreateStackTemporary(VT);
830 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
833 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr,
834 PseudoSourceValue::getFixedStack(SPFI), 0);
836 // Truncate or zero extend offset to target pointer type.
837 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
838 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
839 // Add the offset to the index.
840 unsigned EltSize = EltVT.getSizeInBits()/8;
841 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
842 SDValue StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
843 // Store the scalar value.
844 Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2,
845 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT);
846 // Load the updated vector.
847 return DAG.getLoad(VT, Ch, StackPtr,
848 PseudoSourceValue::getFixedStack(SPFI), 0);
851 /// LegalizeOp - We know that the specified value has a legal type, and
852 /// that its operands are legal. Now ensure that the operation itself
853 /// is legal, recursively ensuring that the operands' operations remain
855 SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
856 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
859 assert(isTypeLegal(Op.getValueType()) &&
860 "Caller should expand or promote operands that are not legal!");
861 SDNode *Node = Op.getNode();
863 // If this operation defines any values that cannot be represented in a
864 // register on this target, make sure to expand or promote them.
865 if (Node->getNumValues() > 1) {
866 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
867 if (getTypeAction(Node->getValueType(i)) != Legal) {
868 HandleOp(Op.getValue(i));
869 assert(LegalizedNodes.count(Op) &&
870 "Handling didn't add legal operands!");
871 return LegalizedNodes[Op];
875 // Note that LegalizeOp may be reentered even from single-use nodes, which
876 // means that we always must cache transformed nodes.
877 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
878 if (I != LegalizedNodes.end()) return I->second;
880 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
882 bool isCustom = false;
884 switch (Node->getOpcode()) {
885 case ISD::FrameIndex:
886 case ISD::EntryToken:
888 case ISD::BasicBlock:
889 case ISD::TargetFrameIndex:
890 case ISD::TargetJumpTable:
891 case ISD::TargetConstant:
892 case ISD::TargetConstantFP:
893 case ISD::TargetConstantPool:
894 case ISD::TargetGlobalAddress:
895 case ISD::TargetGlobalTLSAddress:
896 case ISD::TargetExternalSymbol:
899 case ISD::MEMOPERAND:
902 // Primitives must all be legal.
903 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
904 "This must be legal!");
907 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
908 // If this is a target node, legalize it by legalizing the operands then
909 // passing it through.
910 SmallVector<SDValue, 8> Ops;
911 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
912 Ops.push_back(LegalizeOp(Node->getOperand(i)));
914 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
916 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
917 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
918 return Result.getValue(Op.getResNo());
920 // Otherwise this is an unhandled builtin node. splat.
922 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
924 assert(0 && "Do not know how to legalize this operator!");
926 case ISD::GLOBAL_OFFSET_TABLE:
927 case ISD::GlobalAddress:
928 case ISD::GlobalTLSAddress:
929 case ISD::ExternalSymbol:
930 case ISD::ConstantPool:
931 case ISD::JumpTable: // Nothing to do.
932 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
933 default: assert(0 && "This action is not supported yet!");
934 case TargetLowering::Custom:
935 Tmp1 = TLI.LowerOperation(Op, DAG);
936 if (Tmp1.getNode()) Result = Tmp1;
937 // FALLTHROUGH if the target doesn't want to lower this op after all.
938 case TargetLowering::Legal:
943 case ISD::RETURNADDR:
944 // The only option for these nodes is to custom lower them. If the target
945 // does not custom lower them, then return zero.
946 Tmp1 = TLI.LowerOperation(Op, DAG);
950 Result = DAG.getConstant(0, TLI.getPointerTy());
952 case ISD::FRAME_TO_ARGS_OFFSET: {
953 MVT VT = Node->getValueType(0);
954 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
955 default: assert(0 && "This action is not supported yet!");
956 case TargetLowering::Custom:
957 Result = TLI.LowerOperation(Op, DAG);
958 if (Result.getNode()) break;
960 case TargetLowering::Legal:
961 Result = DAG.getConstant(0, VT);
966 case ISD::EXCEPTIONADDR: {
967 Tmp1 = LegalizeOp(Node->getOperand(0));
968 MVT VT = Node->getValueType(0);
969 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
970 default: assert(0 && "This action is not supported yet!");
971 case TargetLowering::Expand: {
972 unsigned Reg = TLI.getExceptionAddressRegister();
973 Result = DAG.getCopyFromReg(Tmp1, Reg, VT);
976 case TargetLowering::Custom:
977 Result = TLI.LowerOperation(Op, DAG);
978 if (Result.getNode()) break;
980 case TargetLowering::Legal: {
981 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp1 };
982 Result = DAG.getMergeValues(Ops, 2);
987 if (Result.getNode()->getNumValues() == 1) break;
989 assert(Result.getNode()->getNumValues() == 2 &&
990 "Cannot return more than two values!");
992 // Since we produced two values, make sure to remember that we
993 // legalized both of them.
994 Tmp1 = LegalizeOp(Result);
995 Tmp2 = LegalizeOp(Result.getValue(1));
996 AddLegalizedOperand(Op.getValue(0), Tmp1);
997 AddLegalizedOperand(Op.getValue(1), Tmp2);
998 return Op.getResNo() ? Tmp2 : Tmp1;
999 case ISD::EHSELECTION: {
1000 Tmp1 = LegalizeOp(Node->getOperand(0));
1001 Tmp2 = LegalizeOp(Node->getOperand(1));
1002 MVT VT = Node->getValueType(0);
1003 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1004 default: assert(0 && "This action is not supported yet!");
1005 case TargetLowering::Expand: {
1006 unsigned Reg = TLI.getExceptionSelectorRegister();
1007 Result = DAG.getCopyFromReg(Tmp2, Reg, VT);
1010 case TargetLowering::Custom:
1011 Result = TLI.LowerOperation(Op, DAG);
1012 if (Result.getNode()) break;
1014 case TargetLowering::Legal: {
1015 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp2 };
1016 Result = DAG.getMergeValues(Ops, 2);
1021 if (Result.getNode()->getNumValues() == 1) break;
1023 assert(Result.getNode()->getNumValues() == 2 &&
1024 "Cannot return more than two values!");
1026 // Since we produced two values, make sure to remember that we
1027 // legalized both of them.
1028 Tmp1 = LegalizeOp(Result);
1029 Tmp2 = LegalizeOp(Result.getValue(1));
1030 AddLegalizedOperand(Op.getValue(0), Tmp1);
1031 AddLegalizedOperand(Op.getValue(1), Tmp2);
1032 return Op.getResNo() ? Tmp2 : Tmp1;
1033 case ISD::EH_RETURN: {
1034 MVT VT = Node->getValueType(0);
1035 // The only "good" option for this node is to custom lower it.
1036 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1037 default: assert(0 && "This action is not supported at all!");
1038 case TargetLowering::Custom:
1039 Result = TLI.LowerOperation(Op, DAG);
1040 if (Result.getNode()) break;
1042 case TargetLowering::Legal:
1043 // Target does not know, how to lower this, lower to noop
1044 Result = LegalizeOp(Node->getOperand(0));
1049 case ISD::AssertSext:
1050 case ISD::AssertZext:
1051 Tmp1 = LegalizeOp(Node->getOperand(0));
1052 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1054 case ISD::MERGE_VALUES:
1055 // Legalize eliminates MERGE_VALUES nodes.
1056 Result = Node->getOperand(Op.getResNo());
1058 case ISD::CopyFromReg:
1059 Tmp1 = LegalizeOp(Node->getOperand(0));
1060 Result = Op.getValue(0);
1061 if (Node->getNumValues() == 2) {
1062 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1064 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
1065 if (Node->getNumOperands() == 3) {
1066 Tmp2 = LegalizeOp(Node->getOperand(2));
1067 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1069 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1071 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
1073 // Since CopyFromReg produces two values, make sure to remember that we
1074 // legalized both of them.
1075 AddLegalizedOperand(Op.getValue(0), Result);
1076 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1077 return Result.getValue(Op.getResNo());
1079 MVT VT = Op.getValueType();
1080 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
1081 default: assert(0 && "This action is not supported yet!");
1082 case TargetLowering::Expand:
1084 Result = DAG.getConstant(0, VT);
1085 else if (VT.isFloatingPoint())
1086 Result = DAG.getConstantFP(APFloat(APInt(VT.getSizeInBits(), 0)),
1089 assert(0 && "Unknown value type!");
1091 case TargetLowering::Legal:
1097 case ISD::INTRINSIC_W_CHAIN:
1098 case ISD::INTRINSIC_WO_CHAIN:
1099 case ISD::INTRINSIC_VOID: {
1100 SmallVector<SDValue, 8> Ops;
1101 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1102 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1103 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1105 // Allow the target to custom lower its intrinsics if it wants to.
1106 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
1107 TargetLowering::Custom) {
1108 Tmp3 = TLI.LowerOperation(Result, DAG);
1109 if (Tmp3.getNode()) Result = Tmp3;
1112 if (Result.getNode()->getNumValues() == 1) break;
1114 // Must have return value and chain result.
1115 assert(Result.getNode()->getNumValues() == 2 &&
1116 "Cannot return more than two values!");
1118 // Since loads produce two values, make sure to remember that we
1119 // legalized both of them.
1120 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1121 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1122 return Result.getValue(Op.getResNo());
1125 case ISD::DBG_STOPPOINT:
1126 assert(Node->getNumOperands() == 1 && "Invalid DBG_STOPPOINT node!");
1127 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
1129 switch (TLI.getOperationAction(ISD::DBG_STOPPOINT, MVT::Other)) {
1130 case TargetLowering::Promote:
1131 default: assert(0 && "This action is not supported yet!");
1132 case TargetLowering::Expand: {
1133 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
1134 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
1135 bool useLABEL = TLI.isOperationLegal(ISD::DBG_LABEL, MVT::Other);
1137 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node);
1138 if (MMI && (useDEBUG_LOC || useLABEL)) {
1139 const CompileUnitDesc *CompileUnit = DSP->getCompileUnit();
1140 unsigned SrcFile = MMI->RecordSource(CompileUnit);
1142 unsigned Line = DSP->getLine();
1143 unsigned Col = DSP->getColumn();
1146 SDValue Ops[] = { Tmp1, DAG.getConstant(Line, MVT::i32),
1147 DAG.getConstant(Col, MVT::i32),
1148 DAG.getConstant(SrcFile, MVT::i32) };
1149 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops, 4);
1151 unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile);
1152 Result = DAG.getLabel(ISD::DBG_LABEL, Tmp1, ID);
1155 Result = Tmp1; // chain
1159 case TargetLowering::Legal: {
1160 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1161 if (Action == Legal && Tmp1 == Node->getOperand(0))
1164 SmallVector<SDValue, 8> Ops;
1165 Ops.push_back(Tmp1);
1166 if (Action == Legal) {
1167 Ops.push_back(Node->getOperand(1)); // line # must be legal.
1168 Ops.push_back(Node->getOperand(2)); // col # must be legal.
1170 // Otherwise promote them.
1171 Ops.push_back(PromoteOp(Node->getOperand(1)));
1172 Ops.push_back(PromoteOp(Node->getOperand(2)));
1174 Ops.push_back(Node->getOperand(3)); // filename must be legal.
1175 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
1176 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1183 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!");
1184 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) {
1185 default: assert(0 && "This action is not supported yet!");
1186 case TargetLowering::Legal:
1187 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1188 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1189 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable.
1190 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1192 case TargetLowering::Expand:
1193 Result = LegalizeOp(Node->getOperand(0));
1198 case ISD::DEBUG_LOC:
1199 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
1200 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
1201 default: assert(0 && "This action is not supported yet!");
1202 case TargetLowering::Legal: {
1203 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1204 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1205 if (Action == Legal && Tmp1 == Node->getOperand(0))
1207 if (Action == Legal) {
1208 Tmp2 = Node->getOperand(1);
1209 Tmp3 = Node->getOperand(2);
1210 Tmp4 = Node->getOperand(3);
1212 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1213 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1214 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1216 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1222 case ISD::DBG_LABEL:
1224 assert(Node->getNumOperands() == 1 && "Invalid LABEL node!");
1225 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
1226 default: assert(0 && "This action is not supported yet!");
1227 case TargetLowering::Legal:
1228 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1229 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1231 case TargetLowering::Expand:
1232 Result = LegalizeOp(Node->getOperand(0));
1238 assert(Node->getNumOperands() == 4 && "Invalid Prefetch node!");
1239 switch (TLI.getOperationAction(ISD::PREFETCH, MVT::Other)) {
1240 default: assert(0 && "This action is not supported yet!");
1241 case TargetLowering::Legal:
1242 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1243 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1244 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the rw specifier.
1245 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize locality specifier.
1246 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1248 case TargetLowering::Expand:
1250 Result = LegalizeOp(Node->getOperand(0));
1255 case ISD::MEMBARRIER: {
1256 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!");
1257 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) {
1258 default: assert(0 && "This action is not supported yet!");
1259 case TargetLowering::Legal: {
1261 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1262 for (int x = 1; x < 6; ++x) {
1263 Ops[x] = Node->getOperand(x);
1264 if (!isTypeLegal(Ops[x].getValueType()))
1265 Ops[x] = PromoteOp(Ops[x]);
1267 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6);
1270 case TargetLowering::Expand:
1271 //There is no libgcc call for this op
1272 Result = Node->getOperand(0); // Noop
1278 case ISD::ATOMIC_CMP_SWAP_8:
1279 case ISD::ATOMIC_CMP_SWAP_16:
1280 case ISD::ATOMIC_CMP_SWAP_32:
1281 case ISD::ATOMIC_CMP_SWAP_64: {
1282 unsigned int num_operands = 4;
1283 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1285 for (unsigned int x = 0; x < num_operands; ++x)
1286 Ops[x] = LegalizeOp(Node->getOperand(x));
1287 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1289 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1290 default: assert(0 && "This action is not supported yet!");
1291 case TargetLowering::Custom:
1292 Result = TLI.LowerOperation(Result, DAG);
1294 case TargetLowering::Legal:
1297 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1298 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1299 return Result.getValue(Op.getResNo());
1301 case ISD::ATOMIC_LOAD_ADD_8:
1302 case ISD::ATOMIC_LOAD_SUB_8:
1303 case ISD::ATOMIC_LOAD_AND_8:
1304 case ISD::ATOMIC_LOAD_OR_8:
1305 case ISD::ATOMIC_LOAD_XOR_8:
1306 case ISD::ATOMIC_LOAD_NAND_8:
1307 case ISD::ATOMIC_LOAD_MIN_8:
1308 case ISD::ATOMIC_LOAD_MAX_8:
1309 case ISD::ATOMIC_LOAD_UMIN_8:
1310 case ISD::ATOMIC_LOAD_UMAX_8:
1311 case ISD::ATOMIC_SWAP_8:
1312 case ISD::ATOMIC_LOAD_ADD_16:
1313 case ISD::ATOMIC_LOAD_SUB_16:
1314 case ISD::ATOMIC_LOAD_AND_16:
1315 case ISD::ATOMIC_LOAD_OR_16:
1316 case ISD::ATOMIC_LOAD_XOR_16:
1317 case ISD::ATOMIC_LOAD_NAND_16:
1318 case ISD::ATOMIC_LOAD_MIN_16:
1319 case ISD::ATOMIC_LOAD_MAX_16:
1320 case ISD::ATOMIC_LOAD_UMIN_16:
1321 case ISD::ATOMIC_LOAD_UMAX_16:
1322 case ISD::ATOMIC_SWAP_16:
1323 case ISD::ATOMIC_LOAD_ADD_32:
1324 case ISD::ATOMIC_LOAD_SUB_32:
1325 case ISD::ATOMIC_LOAD_AND_32:
1326 case ISD::ATOMIC_LOAD_OR_32:
1327 case ISD::ATOMIC_LOAD_XOR_32:
1328 case ISD::ATOMIC_LOAD_NAND_32:
1329 case ISD::ATOMIC_LOAD_MIN_32:
1330 case ISD::ATOMIC_LOAD_MAX_32:
1331 case ISD::ATOMIC_LOAD_UMIN_32:
1332 case ISD::ATOMIC_LOAD_UMAX_32:
1333 case ISD::ATOMIC_SWAP_32:
1334 case ISD::ATOMIC_LOAD_ADD_64:
1335 case ISD::ATOMIC_LOAD_SUB_64:
1336 case ISD::ATOMIC_LOAD_AND_64:
1337 case ISD::ATOMIC_LOAD_OR_64:
1338 case ISD::ATOMIC_LOAD_XOR_64:
1339 case ISD::ATOMIC_LOAD_NAND_64:
1340 case ISD::ATOMIC_LOAD_MIN_64:
1341 case ISD::ATOMIC_LOAD_MAX_64:
1342 case ISD::ATOMIC_LOAD_UMIN_64:
1343 case ISD::ATOMIC_LOAD_UMAX_64:
1344 case ISD::ATOMIC_SWAP_64: {
1345 unsigned int num_operands = 3;
1346 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1348 for (unsigned int x = 0; x < num_operands; ++x)
1349 Ops[x] = LegalizeOp(Node->getOperand(x));
1350 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1352 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1353 default: assert(0 && "This action is not supported yet!");
1354 case TargetLowering::Custom:
1355 Result = TLI.LowerOperation(Result, DAG);
1357 case TargetLowering::Legal:
1360 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1361 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1362 return Result.getValue(Op.getResNo());
1364 case ISD::Constant: {
1365 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1367 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1369 // We know we don't need to expand constants here, constants only have one
1370 // value and we check that it is fine above.
1372 if (opAction == TargetLowering::Custom) {
1373 Tmp1 = TLI.LowerOperation(Result, DAG);
1379 case ISD::ConstantFP: {
1380 // Spill FP immediates to the constant pool if the target cannot directly
1381 // codegen them. Targets often have some immediate values that can be
1382 // efficiently generated into an FP register without a load. We explicitly
1383 // leave these constants as ConstantFP nodes for the target to deal with.
1384 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1386 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1387 default: assert(0 && "This action is not supported yet!");
1388 case TargetLowering::Legal:
1390 case TargetLowering::Custom:
1391 Tmp3 = TLI.LowerOperation(Result, DAG);
1392 if (Tmp3.getNode()) {
1397 case TargetLowering::Expand: {
1398 // Check to see if this FP immediate is already legal.
1399 bool isLegal = false;
1400 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1401 E = TLI.legal_fpimm_end(); I != E; ++I) {
1402 if (CFP->isExactlyValue(*I)) {
1407 // If this is a legal constant, turn it into a TargetConstantFP node.
1410 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1415 case ISD::TokenFactor:
1416 if (Node->getNumOperands() == 2) {
1417 Tmp1 = LegalizeOp(Node->getOperand(0));
1418 Tmp2 = LegalizeOp(Node->getOperand(1));
1419 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1420 } else if (Node->getNumOperands() == 3) {
1421 Tmp1 = LegalizeOp(Node->getOperand(0));
1422 Tmp2 = LegalizeOp(Node->getOperand(1));
1423 Tmp3 = LegalizeOp(Node->getOperand(2));
1424 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1426 SmallVector<SDValue, 8> Ops;
1427 // Legalize the operands.
1428 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1429 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1430 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1434 case ISD::FORMAL_ARGUMENTS:
1436 // The only option for this is to custom lower it.
1437 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1438 assert(Tmp3.getNode() && "Target didn't custom lower this node!");
1439 // A call within a calling sequence must be legalized to something
1440 // other than the normal CALLSEQ_END. Violating this gets Legalize
1441 // into an infinite loop.
1442 assert ((!IsLegalizingCall ||
1443 Node->getOpcode() != ISD::CALL ||
1444 Tmp3.getNode()->getOpcode() != ISD::CALLSEQ_END) &&
1445 "Nested CALLSEQ_START..CALLSEQ_END not supported.");
1447 // The number of incoming and outgoing values should match; unless the final
1448 // outgoing value is a flag.
1449 assert((Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() ||
1450 (Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() + 1 &&
1451 Tmp3.getNode()->getValueType(Tmp3.getNode()->getNumValues() - 1) ==
1453 "Lowering call/formal_arguments produced unexpected # results!");
1455 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1456 // remember that we legalized all of them, so it doesn't get relegalized.
1457 for (unsigned i = 0, e = Tmp3.getNode()->getNumValues(); i != e; ++i) {
1458 if (Tmp3.getNode()->getValueType(i) == MVT::Flag)
1460 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1461 if (Op.getResNo() == i)
1463 AddLegalizedOperand(SDValue(Node, i), Tmp1);
1466 case ISD::EXTRACT_SUBREG: {
1467 Tmp1 = LegalizeOp(Node->getOperand(0));
1468 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1469 assert(idx && "Operand must be a constant");
1470 Tmp2 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0));
1471 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1474 case ISD::INSERT_SUBREG: {
1475 Tmp1 = LegalizeOp(Node->getOperand(0));
1476 Tmp2 = LegalizeOp(Node->getOperand(1));
1477 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1478 assert(idx && "Operand must be a constant");
1479 Tmp3 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0));
1480 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1483 case ISD::BUILD_VECTOR:
1484 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1485 default: assert(0 && "This action is not supported yet!");
1486 case TargetLowering::Custom:
1487 Tmp3 = TLI.LowerOperation(Result, DAG);
1488 if (Tmp3.getNode()) {
1493 case TargetLowering::Expand:
1494 Result = ExpandBUILD_VECTOR(Result.getNode());
1498 case ISD::INSERT_VECTOR_ELT:
1499 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1500 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1502 // The type of the value to insert may not be legal, even though the vector
1503 // type is legal. Legalize/Promote accordingly. We do not handle Expand
1505 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1506 default: assert(0 && "Cannot expand insert element operand");
1507 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
1508 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
1510 // FIXME: An alternative would be to check to see if the target is not
1511 // going to custom lower this operation, we could bitcast to half elt
1512 // width and perform two inserts at that width, if that is legal.
1513 Tmp2 = Node->getOperand(1);
1516 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1518 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1519 Node->getValueType(0))) {
1520 default: assert(0 && "This action is not supported yet!");
1521 case TargetLowering::Legal:
1523 case TargetLowering::Custom:
1524 Tmp4 = TLI.LowerOperation(Result, DAG);
1525 if (Tmp4.getNode()) {
1530 case TargetLowering::Promote:
1531 // Fall thru for vector case
1532 case TargetLowering::Expand: {
1533 // If the insert index is a constant, codegen this as a scalar_to_vector,
1534 // then a shuffle that inserts it into the right position in the vector.
1535 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1536 // SCALAR_TO_VECTOR requires that the type of the value being inserted
1537 // match the element type of the vector being created.
1538 if (Tmp2.getValueType() ==
1539 Op.getValueType().getVectorElementType()) {
1540 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
1541 Tmp1.getValueType(), Tmp2);
1543 unsigned NumElts = Tmp1.getValueType().getVectorNumElements();
1545 MVT::getIntVectorWithNumElements(NumElts);
1546 MVT ShufMaskEltVT = ShufMaskVT.getVectorElementType();
1548 // We generate a shuffle of InVec and ScVec, so the shuffle mask
1549 // should be 0,1,2,3,4,5... with the appropriate element replaced with
1550 // elt 0 of the RHS.
1551 SmallVector<SDValue, 8> ShufOps;
1552 for (unsigned i = 0; i != NumElts; ++i) {
1553 if (i != InsertPos->getZExtValue())
1554 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1556 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1558 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1559 &ShufOps[0], ShufOps.size());
1561 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1562 Tmp1, ScVec, ShufMask);
1563 Result = LegalizeOp(Result);
1567 Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3);
1572 case ISD::SCALAR_TO_VECTOR:
1573 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1574 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1578 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1579 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1580 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1581 Node->getValueType(0))) {
1582 default: assert(0 && "This action is not supported yet!");
1583 case TargetLowering::Legal:
1585 case TargetLowering::Custom:
1586 Tmp3 = TLI.LowerOperation(Result, DAG);
1587 if (Tmp3.getNode()) {
1592 case TargetLowering::Expand:
1593 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1597 case ISD::VECTOR_SHUFFLE:
1598 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1599 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1600 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1602 // Allow targets to custom lower the SHUFFLEs they support.
1603 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1604 default: assert(0 && "Unknown operation action!");
1605 case TargetLowering::Legal:
1606 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1607 "vector shuffle should not be created if not legal!");
1609 case TargetLowering::Custom:
1610 Tmp3 = TLI.LowerOperation(Result, DAG);
1611 if (Tmp3.getNode()) {
1616 case TargetLowering::Expand: {
1617 MVT VT = Node->getValueType(0);
1618 MVT EltVT = VT.getVectorElementType();
1619 MVT PtrVT = TLI.getPointerTy();
1620 SDValue Mask = Node->getOperand(2);
1621 unsigned NumElems = Mask.getNumOperands();
1622 SmallVector<SDValue,8> Ops;
1623 for (unsigned i = 0; i != NumElems; ++i) {
1624 SDValue Arg = Mask.getOperand(i);
1625 if (Arg.getOpcode() == ISD::UNDEF) {
1626 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1628 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1629 unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
1631 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1632 DAG.getConstant(Idx, PtrVT)));
1634 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1635 DAG.getConstant(Idx - NumElems, PtrVT)));
1638 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1641 case TargetLowering::Promote: {
1642 // Change base type to a different vector type.
1643 MVT OVT = Node->getValueType(0);
1644 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1646 // Cast the two input vectors.
1647 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1648 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1650 // Convert the shuffle mask to the right # elements.
1651 Tmp3 = SDValue(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1652 assert(Tmp3.getNode() && "Shuffle not legal?");
1653 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1654 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1660 case ISD::EXTRACT_VECTOR_ELT:
1661 Tmp1 = Node->getOperand(0);
1662 Tmp2 = LegalizeOp(Node->getOperand(1));
1663 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1664 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1667 case ISD::EXTRACT_SUBVECTOR:
1668 Tmp1 = Node->getOperand(0);
1669 Tmp2 = LegalizeOp(Node->getOperand(1));
1670 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1671 Result = ExpandEXTRACT_SUBVECTOR(Result);
1674 case ISD::CONCAT_VECTORS: {
1675 // Use extract/insert/build vector for now. We might try to be
1676 // more clever later.
1677 MVT PtrVT = TLI.getPointerTy();
1678 SmallVector<SDValue, 8> Ops;
1679 unsigned NumOperands = Node->getNumOperands();
1680 for (unsigned i=0; i < NumOperands; ++i) {
1681 SDValue SubOp = Node->getOperand(i);
1682 MVT VVT = SubOp.getNode()->getValueType(0);
1683 MVT EltVT = VVT.getVectorElementType();
1684 unsigned NumSubElem = VVT.getVectorNumElements();
1685 for (unsigned j=0; j < NumSubElem; ++j) {
1686 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, SubOp,
1687 DAG.getConstant(j, PtrVT)));
1690 return LegalizeOp(DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0),
1691 &Ops[0], Ops.size()));
1694 case ISD::CALLSEQ_START: {
1695 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1697 // Recursively Legalize all of the inputs of the call end that do not lead
1698 // to this call start. This ensures that any libcalls that need be inserted
1699 // are inserted *before* the CALLSEQ_START.
1700 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1701 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1702 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
1706 // Now that we legalized all of the inputs (which may have inserted
1707 // libcalls) create the new CALLSEQ_START node.
1708 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1710 // Merge in the last call, to ensure that this call start after the last
1712 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1713 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1714 Tmp1 = LegalizeOp(Tmp1);
1717 // Do not try to legalize the target-specific arguments (#1+).
1718 if (Tmp1 != Node->getOperand(0)) {
1719 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1721 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1724 // Remember that the CALLSEQ_START is legalized.
1725 AddLegalizedOperand(Op.getValue(0), Result);
1726 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1727 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1729 // Now that the callseq_start and all of the non-call nodes above this call
1730 // sequence have been legalized, legalize the call itself. During this
1731 // process, no libcalls can/will be inserted, guaranteeing that no calls
1733 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1734 // Note that we are selecting this call!
1735 LastCALLSEQ_END = SDValue(CallEnd, 0);
1736 IsLegalizingCall = true;
1738 // Legalize the call, starting from the CALLSEQ_END.
1739 LegalizeOp(LastCALLSEQ_END);
1740 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1743 case ISD::CALLSEQ_END:
1744 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1745 // will cause this node to be legalized as well as handling libcalls right.
1746 if (LastCALLSEQ_END.getNode() != Node) {
1747 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
1748 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1749 assert(I != LegalizedNodes.end() &&
1750 "Legalizing the call start should have legalized this node!");
1754 // Otherwise, the call start has been legalized and everything is going
1755 // according to plan. Just legalize ourselves normally here.
1756 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1757 // Do not try to legalize the target-specific arguments (#1+), except for
1758 // an optional flag input.
1759 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1760 if (Tmp1 != Node->getOperand(0)) {
1761 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1763 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1766 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1767 if (Tmp1 != Node->getOperand(0) ||
1768 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1769 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1772 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1775 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1776 // This finishes up call legalization.
1777 IsLegalizingCall = false;
1779 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1780 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1781 if (Node->getNumValues() == 2)
1782 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1783 return Result.getValue(Op.getResNo());
1784 case ISD::DYNAMIC_STACKALLOC: {
1785 MVT VT = Node->getValueType(0);
1786 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1787 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1788 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1789 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1791 Tmp1 = Result.getValue(0);
1792 Tmp2 = Result.getValue(1);
1793 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1794 default: assert(0 && "This action is not supported yet!");
1795 case TargetLowering::Expand: {
1796 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1797 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1798 " not tell us which reg is the stack pointer!");
1799 SDValue Chain = Tmp1.getOperand(0);
1801 // Chain the dynamic stack allocation so that it doesn't modify the stack
1802 // pointer when other instructions are using the stack.
1803 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1805 SDValue Size = Tmp2.getOperand(1);
1806 SDValue SP = DAG.getCopyFromReg(Chain, SPReg, VT);
1807 Chain = SP.getValue(1);
1808 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1809 unsigned StackAlign =
1810 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1811 if (Align > StackAlign)
1812 SP = DAG.getNode(ISD::AND, VT, SP,
1813 DAG.getConstant(-(uint64_t)Align, VT));
1814 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value
1815 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
1817 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1818 DAG.getIntPtrConstant(0, true), SDValue());
1820 Tmp1 = LegalizeOp(Tmp1);
1821 Tmp2 = LegalizeOp(Tmp2);
1824 case TargetLowering::Custom:
1825 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1826 if (Tmp3.getNode()) {
1827 Tmp1 = LegalizeOp(Tmp3);
1828 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1831 case TargetLowering::Legal:
1834 // Since this op produce two values, make sure to remember that we
1835 // legalized both of them.
1836 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
1837 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
1838 return Op.getResNo() ? Tmp2 : Tmp1;
1840 case ISD::INLINEASM: {
1841 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1842 bool Changed = false;
1843 // Legalize all of the operands of the inline asm, in case they are nodes
1844 // that need to be expanded or something. Note we skip the asm string and
1845 // all of the TargetConstant flags.
1846 SDValue Op = LegalizeOp(Ops[0]);
1847 Changed = Op != Ops[0];
1850 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1851 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1852 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getZExtValue() >> 3;
1853 for (++i; NumVals; ++i, --NumVals) {
1854 SDValue Op = LegalizeOp(Ops[i]);
1863 Op = LegalizeOp(Ops.back());
1864 Changed |= Op != Ops.back();
1869 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1871 // INLINE asm returns a chain and flag, make sure to add both to the map.
1872 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1873 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1874 return Result.getValue(Op.getResNo());
1877 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1878 // Ensure that libcalls are emitted before a branch.
1879 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1880 Tmp1 = LegalizeOp(Tmp1);
1881 LastCALLSEQ_END = DAG.getEntryNode();
1883 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1886 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1887 // Ensure that libcalls are emitted before a branch.
1888 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1889 Tmp1 = LegalizeOp(Tmp1);
1890 LastCALLSEQ_END = DAG.getEntryNode();
1892 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1893 default: assert(0 && "Indirect target must be legal type (pointer)!");
1895 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1898 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1901 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1902 // Ensure that libcalls are emitted before a branch.
1903 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1904 Tmp1 = LegalizeOp(Tmp1);
1905 LastCALLSEQ_END = DAG.getEntryNode();
1907 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1908 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1910 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1911 default: assert(0 && "This action is not supported yet!");
1912 case TargetLowering::Legal: break;
1913 case TargetLowering::Custom:
1914 Tmp1 = TLI.LowerOperation(Result, DAG);
1915 if (Tmp1.getNode()) Result = Tmp1;
1917 case TargetLowering::Expand: {
1918 SDValue Chain = Result.getOperand(0);
1919 SDValue Table = Result.getOperand(1);
1920 SDValue Index = Result.getOperand(2);
1922 MVT PTy = TLI.getPointerTy();
1923 MachineFunction &MF = DAG.getMachineFunction();
1924 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
1925 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1926 SDValue Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1929 switch (EntrySize) {
1930 default: assert(0 && "Size of jump table not supported yet."); break;
1931 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr,
1932 PseudoSourceValue::getJumpTable(), 0); break;
1933 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr,
1934 PseudoSourceValue::getJumpTable(), 0); break;
1938 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1939 // For PIC, the sequence is:
1940 // BRIND(load(Jumptable + index) + RelocBase)
1941 // RelocBase can be JumpTable, GOT or some sort of global base.
1942 if (PTy != MVT::i32)
1943 Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr);
1944 Addr = DAG.getNode(ISD::ADD, PTy, Addr,
1945 TLI.getPICJumpTableRelocBase(Table, DAG));
1947 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1952 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1953 // Ensure that libcalls are emitted before a return.
1954 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1955 Tmp1 = LegalizeOp(Tmp1);
1956 LastCALLSEQ_END = DAG.getEntryNode();
1958 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1959 case Expand: assert(0 && "It's impossible to expand bools");
1961 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1964 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1966 // The top bits of the promoted condition are not necessarily zero, ensure
1967 // that the value is properly zero extended.
1968 unsigned BitWidth = Tmp2.getValueSizeInBits();
1969 if (!DAG.MaskedValueIsZero(Tmp2,
1970 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
1971 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1976 // Basic block destination (Op#2) is always legal.
1977 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1979 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1980 default: assert(0 && "This action is not supported yet!");
1981 case TargetLowering::Legal: break;
1982 case TargetLowering::Custom:
1983 Tmp1 = TLI.LowerOperation(Result, DAG);
1984 if (Tmp1.getNode()) Result = Tmp1;
1986 case TargetLowering::Expand:
1987 // Expand brcond's setcc into its constituent parts and create a BR_CC
1989 if (Tmp2.getOpcode() == ISD::SETCC) {
1990 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1991 Tmp2.getOperand(0), Tmp2.getOperand(1),
1992 Node->getOperand(2));
1994 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1995 DAG.getCondCode(ISD::SETNE), Tmp2,
1996 DAG.getConstant(0, Tmp2.getValueType()),
1997 Node->getOperand(2));
2003 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2004 // Ensure that libcalls are emitted before a branch.
2005 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2006 Tmp1 = LegalizeOp(Tmp1);
2007 Tmp2 = Node->getOperand(2); // LHS
2008 Tmp3 = Node->getOperand(3); // RHS
2009 Tmp4 = Node->getOperand(1); // CC
2011 LegalizeSetCC(TLI.getSetCCResultType(Tmp2), Tmp2, Tmp3, Tmp4);
2012 LastCALLSEQ_END = DAG.getEntryNode();
2014 // If we didn't get both a LHS and RHS back from LegalizeSetCC,
2015 // the LHS is a legal SETCC itself. In this case, we need to compare
2016 // the result against zero to select between true and false values.
2017 if (Tmp3.getNode() == 0) {
2018 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
2019 Tmp4 = DAG.getCondCode(ISD::SETNE);
2022 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
2023 Node->getOperand(4));
2025 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
2026 default: assert(0 && "Unexpected action for BR_CC!");
2027 case TargetLowering::Legal: break;
2028 case TargetLowering::Custom:
2029 Tmp4 = TLI.LowerOperation(Result, DAG);
2030 if (Tmp4.getNode()) Result = Tmp4;
2035 LoadSDNode *LD = cast<LoadSDNode>(Node);
2036 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
2037 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
2039 ISD::LoadExtType ExtType = LD->getExtensionType();
2040 if (ExtType == ISD::NON_EXTLOAD) {
2041 MVT VT = Node->getValueType(0);
2042 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2043 Tmp3 = Result.getValue(0);
2044 Tmp4 = Result.getValue(1);
2046 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
2047 default: assert(0 && "This action is not supported yet!");
2048 case TargetLowering::Legal:
2049 // If this is an unaligned load and the target doesn't support it,
2051 if (!TLI.allowsUnalignedMemoryAccesses()) {
2052 unsigned ABIAlignment = TLI.getTargetData()->
2053 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
2054 if (LD->getAlignment() < ABIAlignment){
2055 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
2057 Tmp3 = Result.getOperand(0);
2058 Tmp4 = Result.getOperand(1);
2059 Tmp3 = LegalizeOp(Tmp3);
2060 Tmp4 = LegalizeOp(Tmp4);
2064 case TargetLowering::Custom:
2065 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
2066 if (Tmp1.getNode()) {
2067 Tmp3 = LegalizeOp(Tmp1);
2068 Tmp4 = LegalizeOp(Tmp1.getValue(1));
2071 case TargetLowering::Promote: {
2072 // Only promote a load of vector type to another.
2073 assert(VT.isVector() && "Cannot promote this load!");
2074 // Change base type to a different vector type.
2075 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
2077 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
2078 LD->getSrcValueOffset(),
2079 LD->isVolatile(), LD->getAlignment());
2080 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
2081 Tmp4 = LegalizeOp(Tmp1.getValue(1));
2085 // Since loads produce two values, make sure to remember that we
2086 // legalized both of them.
2087 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
2088 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
2089 return Op.getResNo() ? Tmp4 : Tmp3;
2091 MVT SrcVT = LD->getMemoryVT();
2092 unsigned SrcWidth = SrcVT.getSizeInBits();
2093 int SVOffset = LD->getSrcValueOffset();
2094 unsigned Alignment = LD->getAlignment();
2095 bool isVolatile = LD->isVolatile();
2097 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
2098 // Some targets pretend to have an i1 loading operation, and actually
2099 // load an i8. This trick is correct for ZEXTLOAD because the top 7
2100 // bits are guaranteed to be zero; it helps the optimizers understand
2101 // that these bits are zero. It is also useful for EXTLOAD, since it
2102 // tells the optimizers that those bits are undefined. It would be
2103 // nice to have an effective generic way of getting these benefits...
2104 // Until such a way is found, don't insist on promoting i1 here.
2105 (SrcVT != MVT::i1 ||
2106 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
2107 // Promote to a byte-sized load if not loading an integral number of
2108 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
2109 unsigned NewWidth = SrcVT.getStoreSizeInBits();
2110 MVT NVT = MVT::getIntegerVT(NewWidth);
2113 // The extra bits are guaranteed to be zero, since we stored them that
2114 // way. A zext load from NVT thus automatically gives zext from SrcVT.
2116 ISD::LoadExtType NewExtType =
2117 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
2119 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0),
2120 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
2121 NVT, isVolatile, Alignment);
2123 Ch = Result.getValue(1); // The chain.
2125 if (ExtType == ISD::SEXTLOAD)
2126 // Having the top bits zero doesn't help when sign extending.
2127 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2128 Result, DAG.getValueType(SrcVT));
2129 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
2130 // All the top bits are guaranteed to be zero - inform the optimizers.
2131 Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result,
2132 DAG.getValueType(SrcVT));
2134 Tmp1 = LegalizeOp(Result);
2135 Tmp2 = LegalizeOp(Ch);
2136 } else if (SrcWidth & (SrcWidth - 1)) {
2137 // If not loading a power-of-2 number of bits, expand as two loads.
2138 assert(SrcVT.isExtended() && !SrcVT.isVector() &&
2139 "Unsupported extload!");
2140 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
2141 assert(RoundWidth < SrcWidth);
2142 unsigned ExtraWidth = SrcWidth - RoundWidth;
2143 assert(ExtraWidth < RoundWidth);
2144 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2145 "Load size not an integral number of bytes!");
2146 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2147 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2149 unsigned IncrementSize;
2151 if (TLI.isLittleEndian()) {
2152 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
2153 // Load the bottom RoundWidth bits.
2154 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2155 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2158 // Load the remaining ExtraWidth bits.
2159 IncrementSize = RoundWidth / 8;
2160 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2161 DAG.getIntPtrConstant(IncrementSize));
2162 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2163 LD->getSrcValue(), SVOffset + IncrementSize,
2164 ExtraVT, isVolatile,
2165 MinAlign(Alignment, IncrementSize));
2167 // Build a factor node to remember that this load is independent of the
2169 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2172 // Move the top bits to the right place.
2173 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2174 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2176 // Join the hi and lo parts.
2177 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2179 // Big endian - avoid unaligned loads.
2180 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
2181 // Load the top RoundWidth bits.
2182 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2183 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2186 // Load the remaining ExtraWidth bits.
2187 IncrementSize = RoundWidth / 8;
2188 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2189 DAG.getIntPtrConstant(IncrementSize));
2190 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2191 LD->getSrcValue(), SVOffset + IncrementSize,
2192 ExtraVT, isVolatile,
2193 MinAlign(Alignment, IncrementSize));
2195 // Build a factor node to remember that this load is independent of the
2197 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2200 // Move the top bits to the right place.
2201 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2202 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2204 // Join the hi and lo parts.
2205 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2208 Tmp1 = LegalizeOp(Result);
2209 Tmp2 = LegalizeOp(Ch);
2211 switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
2212 default: assert(0 && "This action is not supported yet!");
2213 case TargetLowering::Custom:
2216 case TargetLowering::Legal:
2217 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2218 Tmp1 = Result.getValue(0);
2219 Tmp2 = Result.getValue(1);
2222 Tmp3 = TLI.LowerOperation(Result, DAG);
2223 if (Tmp3.getNode()) {
2224 Tmp1 = LegalizeOp(Tmp3);
2225 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2228 // If this is an unaligned load and the target doesn't support it,
2230 if (!TLI.allowsUnalignedMemoryAccesses()) {
2231 unsigned ABIAlignment = TLI.getTargetData()->
2232 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
2233 if (LD->getAlignment() < ABIAlignment){
2234 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
2236 Tmp1 = Result.getOperand(0);
2237 Tmp2 = Result.getOperand(1);
2238 Tmp1 = LegalizeOp(Tmp1);
2239 Tmp2 = LegalizeOp(Tmp2);
2244 case TargetLowering::Expand:
2245 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
2246 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
2247 SDValue Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
2248 LD->getSrcValueOffset(),
2249 LD->isVolatile(), LD->getAlignment());
2250 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
2251 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
2252 Tmp2 = LegalizeOp(Load.getValue(1));
2255 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
2256 // Turn the unsupported load into an EXTLOAD followed by an explicit
2257 // zero/sign extend inreg.
2258 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2259 Tmp1, Tmp2, LD->getSrcValue(),
2260 LD->getSrcValueOffset(), SrcVT,
2261 LD->isVolatile(), LD->getAlignment());
2263 if (ExtType == ISD::SEXTLOAD)
2264 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2265 Result, DAG.getValueType(SrcVT));
2267 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
2268 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
2269 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
2274 // Since loads produce two values, make sure to remember that we legalized
2276 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2277 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2278 return Op.getResNo() ? Tmp2 : Tmp1;
2281 case ISD::EXTRACT_ELEMENT: {
2282 MVT OpTy = Node->getOperand(0).getValueType();
2283 switch (getTypeAction(OpTy)) {
2284 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
2286 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
2288 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
2289 DAG.getConstant(OpTy.getSizeInBits()/2,
2290 TLI.getShiftAmountTy()));
2291 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
2294 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
2295 Node->getOperand(0));
2299 // Get both the low and high parts.
2300 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2301 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
2302 Result = Tmp2; // 1 -> Hi
2304 Result = Tmp1; // 0 -> Lo
2310 case ISD::CopyToReg:
2311 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2313 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
2314 "Register type must be legal!");
2315 // Legalize the incoming value (must be a legal type).
2316 Tmp2 = LegalizeOp(Node->getOperand(2));
2317 if (Node->getNumValues() == 1) {
2318 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
2320 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
2321 if (Node->getNumOperands() == 4) {
2322 Tmp3 = LegalizeOp(Node->getOperand(3));
2323 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
2326 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
2329 // Since this produces two values, make sure to remember that we legalized
2331 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
2332 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
2338 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2340 // Ensure that libcalls are emitted before a return.
2341 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2342 Tmp1 = LegalizeOp(Tmp1);
2343 LastCALLSEQ_END = DAG.getEntryNode();
2345 switch (Node->getNumOperands()) {
2347 Tmp2 = Node->getOperand(1);
2348 Tmp3 = Node->getOperand(2); // Signness
2349 switch (getTypeAction(Tmp2.getValueType())) {
2351 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
2354 if (!Tmp2.getValueType().isVector()) {
2356 ExpandOp(Tmp2, Lo, Hi);
2358 // Big endian systems want the hi reg first.
2359 if (TLI.isBigEndian())
2363 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2365 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
2366 Result = LegalizeOp(Result);
2368 SDNode *InVal = Tmp2.getNode();
2369 int InIx = Tmp2.getResNo();
2370 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
2371 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
2373 // Figure out if there is a simple type corresponding to this Vector
2374 // type. If so, convert to the vector type.
2375 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2376 if (TLI.isTypeLegal(TVT)) {
2377 // Turn this into a return of the vector type.
2378 Tmp2 = LegalizeOp(Tmp2);
2379 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2380 } else if (NumElems == 1) {
2381 // Turn this into a return of the scalar type.
2382 Tmp2 = ScalarizeVectorOp(Tmp2);
2383 Tmp2 = LegalizeOp(Tmp2);
2384 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2386 // FIXME: Returns of gcc generic vectors smaller than a legal type
2387 // should be returned in integer registers!
2389 // The scalarized value type may not be legal, e.g. it might require
2390 // promotion or expansion. Relegalize the return.
2391 Result = LegalizeOp(Result);
2393 // FIXME: Returns of gcc generic vectors larger than a legal vector
2394 // type should be returned by reference!
2396 SplitVectorOp(Tmp2, Lo, Hi);
2397 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2398 Result = LegalizeOp(Result);
2403 Tmp2 = PromoteOp(Node->getOperand(1));
2404 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2405 Result = LegalizeOp(Result);
2410 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2412 default: { // ret <values>
2413 SmallVector<SDValue, 8> NewValues;
2414 NewValues.push_back(Tmp1);
2415 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
2416 switch (getTypeAction(Node->getOperand(i).getValueType())) {
2418 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
2419 NewValues.push_back(Node->getOperand(i+1));
2423 assert(!Node->getOperand(i).getValueType().isExtended() &&
2424 "FIXME: TODO: implement returning non-legal vector types!");
2425 ExpandOp(Node->getOperand(i), Lo, Hi);
2426 NewValues.push_back(Lo);
2427 NewValues.push_back(Node->getOperand(i+1));
2429 NewValues.push_back(Hi);
2430 NewValues.push_back(Node->getOperand(i+1));
2435 assert(0 && "Can't promote multiple return value yet!");
2438 if (NewValues.size() == Node->getNumOperands())
2439 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
2441 Result = DAG.getNode(ISD::RET, MVT::Other,
2442 &NewValues[0], NewValues.size());
2447 if (Result.getOpcode() == ISD::RET) {
2448 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
2449 default: assert(0 && "This action is not supported yet!");
2450 case TargetLowering::Legal: break;
2451 case TargetLowering::Custom:
2452 Tmp1 = TLI.LowerOperation(Result, DAG);
2453 if (Tmp1.getNode()) Result = Tmp1;
2459 StoreSDNode *ST = cast<StoreSDNode>(Node);
2460 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
2461 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
2462 int SVOffset = ST->getSrcValueOffset();
2463 unsigned Alignment = ST->getAlignment();
2464 bool isVolatile = ST->isVolatile();
2466 if (!ST->isTruncatingStore()) {
2467 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
2468 // FIXME: We shouldn't do this for TargetConstantFP's.
2469 // FIXME: move this to the DAG Combiner! Note that we can't regress due
2470 // to phase ordering between legalized code and the dag combiner. This
2471 // probably means that we need to integrate dag combiner and legalizer
2473 // We generally can't do this one for long doubles.
2474 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
2475 if (CFP->getValueType(0) == MVT::f32 &&
2476 getTypeAction(MVT::i32) == Legal) {
2477 Tmp3 = DAG.getConstant(CFP->getValueAPF().
2478 bitcastToAPInt().zextOrTrunc(32),
2480 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2481 SVOffset, isVolatile, Alignment);
2483 } else if (CFP->getValueType(0) == MVT::f64) {
2484 // If this target supports 64-bit registers, do a single 64-bit store.
2485 if (getTypeAction(MVT::i64) == Legal) {
2486 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
2487 zextOrTrunc(64), MVT::i64);
2488 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2489 SVOffset, isVolatile, Alignment);
2491 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
2492 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
2493 // stores. If the target supports neither 32- nor 64-bits, this
2494 // xform is certainly not worth it.
2495 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
2496 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
2497 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
2498 if (TLI.isBigEndian()) std::swap(Lo, Hi);
2500 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2501 SVOffset, isVolatile, Alignment);
2502 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2503 DAG.getIntPtrConstant(4));
2504 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
2505 isVolatile, MinAlign(Alignment, 4U));
2507 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2513 switch (getTypeAction(ST->getMemoryVT())) {
2515 Tmp3 = LegalizeOp(ST->getValue());
2516 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2519 MVT VT = Tmp3.getValueType();
2520 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2521 default: assert(0 && "This action is not supported yet!");
2522 case TargetLowering::Legal:
2523 // If this is an unaligned store and the target doesn't support it,
2525 if (!TLI.allowsUnalignedMemoryAccesses()) {
2526 unsigned ABIAlignment = TLI.getTargetData()->
2527 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2528 if (ST->getAlignment() < ABIAlignment)
2529 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
2533 case TargetLowering::Custom:
2534 Tmp1 = TLI.LowerOperation(Result, DAG);
2535 if (Tmp1.getNode()) Result = Tmp1;
2537 case TargetLowering::Promote:
2538 assert(VT.isVector() && "Unknown legal promote case!");
2539 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
2540 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2541 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
2542 ST->getSrcValue(), SVOffset, isVolatile,
2549 if (!ST->getMemoryVT().isVector()) {
2550 // Truncate the value and store the result.
2551 Tmp3 = PromoteOp(ST->getValue());
2552 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2553 SVOffset, ST->getMemoryVT(),
2554 isVolatile, Alignment);
2557 // Fall thru to expand for vector
2559 unsigned IncrementSize = 0;
2562 // If this is a vector type, then we have to calculate the increment as
2563 // the product of the element size in bytes, and the number of elements
2564 // in the high half of the vector.
2565 if (ST->getValue().getValueType().isVector()) {
2566 SDNode *InVal = ST->getValue().getNode();
2567 int InIx = ST->getValue().getResNo();
2568 MVT InVT = InVal->getValueType(InIx);
2569 unsigned NumElems = InVT.getVectorNumElements();
2570 MVT EVT = InVT.getVectorElementType();
2572 // Figure out if there is a simple type corresponding to this Vector
2573 // type. If so, convert to the vector type.
2574 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2575 if (TLI.isTypeLegal(TVT)) {
2576 // Turn this into a normal store of the vector type.
2577 Tmp3 = LegalizeOp(ST->getValue());
2578 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2579 SVOffset, isVolatile, Alignment);
2580 Result = LegalizeOp(Result);
2582 } else if (NumElems == 1) {
2583 // Turn this into a normal store of the scalar type.
2584 Tmp3 = ScalarizeVectorOp(ST->getValue());
2585 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2586 SVOffset, isVolatile, Alignment);
2587 // The scalarized value type may not be legal, e.g. it might require
2588 // promotion or expansion. Relegalize the scalar store.
2589 Result = LegalizeOp(Result);
2592 // Check if we have widen this node with another value
2593 std::map<SDValue, SDValue>::iterator I =
2594 WidenNodes.find(ST->getValue());
2595 if (I != WidenNodes.end()) {
2596 Result = StoreWidenVectorOp(ST, Tmp1, Tmp2);
2600 SplitVectorOp(ST->getValue(), Lo, Hi);
2601 IncrementSize = Lo.getNode()->getValueType(0).getVectorNumElements() *
2602 EVT.getSizeInBits()/8;
2606 ExpandOp(ST->getValue(), Lo, Hi);
2607 IncrementSize = Hi.getNode() ? Hi.getValueType().getSizeInBits()/8 : 0;
2609 if (Hi.getNode() && TLI.isBigEndian())
2613 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2614 SVOffset, isVolatile, Alignment);
2616 if (Hi.getNode() == NULL) {
2617 // Must be int <-> float one-to-one expansion.
2622 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2623 DAG.getIntPtrConstant(IncrementSize));
2624 assert(isTypeLegal(Tmp2.getValueType()) &&
2625 "Pointers must be legal!");
2626 SVOffset += IncrementSize;
2627 Alignment = MinAlign(Alignment, IncrementSize);
2628 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2629 SVOffset, isVolatile, Alignment);
2630 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2635 switch (getTypeAction(ST->getValue().getValueType())) {
2637 Tmp3 = LegalizeOp(ST->getValue());
2640 if (!ST->getValue().getValueType().isVector()) {
2641 // We can promote the value, the truncstore will still take care of it.
2642 Tmp3 = PromoteOp(ST->getValue());
2645 // Vector case falls through to expand
2647 // Just store the low part. This may become a non-trunc store, so make
2648 // sure to use getTruncStore, not UpdateNodeOperands below.
2649 ExpandOp(ST->getValue(), Tmp3, Tmp4);
2650 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2651 SVOffset, MVT::i8, isVolatile, Alignment);
2654 MVT StVT = ST->getMemoryVT();
2655 unsigned StWidth = StVT.getSizeInBits();
2657 if (StWidth != StVT.getStoreSizeInBits()) {
2658 // Promote to a byte-sized store with upper bits zero if not
2659 // storing an integral number of bytes. For example, promote
2660 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
2661 MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits());
2662 Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT);
2663 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2664 SVOffset, NVT, isVolatile, Alignment);
2665 } else if (StWidth & (StWidth - 1)) {
2666 // If not storing a power-of-2 number of bits, expand as two stores.
2667 assert(StVT.isExtended() && !StVT.isVector() &&
2668 "Unsupported truncstore!");
2669 unsigned RoundWidth = 1 << Log2_32(StWidth);
2670 assert(RoundWidth < StWidth);
2671 unsigned ExtraWidth = StWidth - RoundWidth;
2672 assert(ExtraWidth < RoundWidth);
2673 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2674 "Store size not an integral number of bytes!");
2675 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2676 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2678 unsigned IncrementSize;
2680 if (TLI.isLittleEndian()) {
2681 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
2682 // Store the bottom RoundWidth bits.
2683 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2685 isVolatile, Alignment);
2687 // Store the remaining ExtraWidth bits.
2688 IncrementSize = RoundWidth / 8;
2689 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2690 DAG.getIntPtrConstant(IncrementSize));
2691 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2692 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2693 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2694 SVOffset + IncrementSize, ExtraVT, isVolatile,
2695 MinAlign(Alignment, IncrementSize));
2697 // Big endian - avoid unaligned stores.
2698 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
2699 // Store the top RoundWidth bits.
2700 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2701 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2702 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset,
2703 RoundVT, isVolatile, Alignment);
2705 // Store the remaining ExtraWidth bits.
2706 IncrementSize = RoundWidth / 8;
2707 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2708 DAG.getIntPtrConstant(IncrementSize));
2709 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2710 SVOffset + IncrementSize, ExtraVT, isVolatile,
2711 MinAlign(Alignment, IncrementSize));
2714 // The order of the stores doesn't matter.
2715 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2717 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2718 Tmp2 != ST->getBasePtr())
2719 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2722 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
2723 default: assert(0 && "This action is not supported yet!");
2724 case TargetLowering::Legal:
2725 // If this is an unaligned store and the target doesn't support it,
2727 if (!TLI.allowsUnalignedMemoryAccesses()) {
2728 unsigned ABIAlignment = TLI.getTargetData()->
2729 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2730 if (ST->getAlignment() < ABIAlignment)
2731 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
2735 case TargetLowering::Custom:
2736 Result = TLI.LowerOperation(Result, DAG);
2739 // TRUNCSTORE:i16 i32 -> STORE i16
2740 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
2741 Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3);
2742 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset,
2743 isVolatile, Alignment);
2751 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2752 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2754 case ISD::STACKSAVE:
2755 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2756 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2757 Tmp1 = Result.getValue(0);
2758 Tmp2 = Result.getValue(1);
2760 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2761 default: assert(0 && "This action is not supported yet!");
2762 case TargetLowering::Legal: break;
2763 case TargetLowering::Custom:
2764 Tmp3 = TLI.LowerOperation(Result, DAG);
2765 if (Tmp3.getNode()) {
2766 Tmp1 = LegalizeOp(Tmp3);
2767 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2770 case TargetLowering::Expand:
2771 // Expand to CopyFromReg if the target set
2772 // StackPointerRegisterToSaveRestore.
2773 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2774 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
2775 Node->getValueType(0));
2776 Tmp2 = Tmp1.getValue(1);
2778 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
2779 Tmp2 = Node->getOperand(0);
2784 // Since stacksave produce two values, make sure to remember that we
2785 // legalized both of them.
2786 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2787 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2788 return Op.getResNo() ? Tmp2 : Tmp1;
2790 case ISD::STACKRESTORE:
2791 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2792 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2793 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2795 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2796 default: assert(0 && "This action is not supported yet!");
2797 case TargetLowering::Legal: break;
2798 case TargetLowering::Custom:
2799 Tmp1 = TLI.LowerOperation(Result, DAG);
2800 if (Tmp1.getNode()) Result = Tmp1;
2802 case TargetLowering::Expand:
2803 // Expand to CopyToReg if the target set
2804 // StackPointerRegisterToSaveRestore.
2805 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2806 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
2814 case ISD::READCYCLECOUNTER:
2815 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2816 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2817 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2818 Node->getValueType(0))) {
2819 default: assert(0 && "This action is not supported yet!");
2820 case TargetLowering::Legal:
2821 Tmp1 = Result.getValue(0);
2822 Tmp2 = Result.getValue(1);
2824 case TargetLowering::Custom:
2825 Result = TLI.LowerOperation(Result, DAG);
2826 Tmp1 = LegalizeOp(Result.getValue(0));
2827 Tmp2 = LegalizeOp(Result.getValue(1));
2831 // Since rdcc produce two values, make sure to remember that we legalized
2833 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2834 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2838 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2839 case Expand: assert(0 && "It's impossible to expand bools");
2841 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2844 assert(!Node->getOperand(0).getValueType().isVector() && "not possible");
2845 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2846 // Make sure the condition is either zero or one.
2847 unsigned BitWidth = Tmp1.getValueSizeInBits();
2848 if (!DAG.MaskedValueIsZero(Tmp1,
2849 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2850 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2854 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2855 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2857 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2859 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2860 default: assert(0 && "This action is not supported yet!");
2861 case TargetLowering::Legal: break;
2862 case TargetLowering::Custom: {
2863 Tmp1 = TLI.LowerOperation(Result, DAG);
2864 if (Tmp1.getNode()) Result = Tmp1;
2867 case TargetLowering::Expand:
2868 if (Tmp1.getOpcode() == ISD::SETCC) {
2869 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2871 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2873 Result = DAG.getSelectCC(Tmp1,
2874 DAG.getConstant(0, Tmp1.getValueType()),
2875 Tmp2, Tmp3, ISD::SETNE);
2878 case TargetLowering::Promote: {
2880 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2881 unsigned ExtOp, TruncOp;
2882 if (Tmp2.getValueType().isVector()) {
2883 ExtOp = ISD::BIT_CONVERT;
2884 TruncOp = ISD::BIT_CONVERT;
2885 } else if (Tmp2.getValueType().isInteger()) {
2886 ExtOp = ISD::ANY_EXTEND;
2887 TruncOp = ISD::TRUNCATE;
2889 ExtOp = ISD::FP_EXTEND;
2890 TruncOp = ISD::FP_ROUND;
2892 // Promote each of the values to the new type.
2893 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2894 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2895 // Perform the larger operation, then round down.
2896 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2897 if (TruncOp != ISD::FP_ROUND)
2898 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2900 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result,
2901 DAG.getIntPtrConstant(0));
2906 case ISD::SELECT_CC: {
2907 Tmp1 = Node->getOperand(0); // LHS
2908 Tmp2 = Node->getOperand(1); // RHS
2909 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2910 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2911 SDValue CC = Node->getOperand(4);
2913 LegalizeSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2, CC);
2915 // If we didn't get both a LHS and RHS back from LegalizeSetCC,
2916 // the LHS is a legal SETCC itself. In this case, we need to compare
2917 // the result against zero to select between true and false values.
2918 if (Tmp2.getNode() == 0) {
2919 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2920 CC = DAG.getCondCode(ISD::SETNE);
2922 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
2924 // Everything is legal, see if we should expand this op or something.
2925 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
2926 default: assert(0 && "This action is not supported yet!");
2927 case TargetLowering::Legal: break;
2928 case TargetLowering::Custom:
2929 Tmp1 = TLI.LowerOperation(Result, DAG);
2930 if (Tmp1.getNode()) Result = Tmp1;
2936 Tmp1 = Node->getOperand(0);
2937 Tmp2 = Node->getOperand(1);
2938 Tmp3 = Node->getOperand(2);
2939 LegalizeSetCC(Node->getValueType(0), Tmp1, Tmp2, Tmp3);
2941 // If we had to Expand the SetCC operands into a SELECT node, then it may
2942 // not always be possible to return a true LHS & RHS. In this case, just
2943 // return the value we legalized, returned in the LHS
2944 if (Tmp2.getNode() == 0) {
2949 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
2950 default: assert(0 && "Cannot handle this action for SETCC yet!");
2951 case TargetLowering::Custom:
2954 case TargetLowering::Legal:
2955 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2957 Tmp4 = TLI.LowerOperation(Result, DAG);
2958 if (Tmp4.getNode()) Result = Tmp4;
2961 case TargetLowering::Promote: {
2962 // First step, figure out the appropriate operation to use.
2963 // Allow SETCC to not be supported for all legal data types
2964 // Mostly this targets FP
2965 MVT NewInTy = Node->getOperand(0).getValueType();
2966 MVT OldVT = NewInTy; OldVT = OldVT;
2968 // Scan for the appropriate larger type to use.
2970 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
2972 assert(NewInTy.isInteger() == OldVT.isInteger() &&
2973 "Fell off of the edge of the integer world");
2974 assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() &&
2975 "Fell off of the edge of the floating point world");
2977 // If the target supports SETCC of this type, use it.
2978 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2981 if (NewInTy.isInteger())
2982 assert(0 && "Cannot promote Legal Integer SETCC yet");
2984 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2985 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2987 Tmp1 = LegalizeOp(Tmp1);
2988 Tmp2 = LegalizeOp(Tmp2);
2989 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2990 Result = LegalizeOp(Result);
2993 case TargetLowering::Expand:
2994 // Expand a setcc node into a select_cc of the same condition, lhs, and
2995 // rhs that selects between const 1 (true) and const 0 (false).
2996 MVT VT = Node->getValueType(0);
2997 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2998 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3004 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3005 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3006 SDValue CC = Node->getOperand(2);
3008 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, CC);
3010 // Everything is legal, see if we should expand this op or something.
3011 switch (TLI.getOperationAction(ISD::VSETCC, Tmp1.getValueType())) {
3012 default: assert(0 && "This action is not supported yet!");
3013 case TargetLowering::Legal: break;
3014 case TargetLowering::Custom:
3015 Tmp1 = TLI.LowerOperation(Result, DAG);
3016 if (Tmp1.getNode()) Result = Tmp1;
3022 case ISD::SHL_PARTS:
3023 case ISD::SRA_PARTS:
3024 case ISD::SRL_PARTS: {
3025 SmallVector<SDValue, 8> Ops;
3026 bool Changed = false;
3027 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
3028 Ops.push_back(LegalizeOp(Node->getOperand(i)));
3029 Changed |= Ops.back() != Node->getOperand(i);
3032 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
3034 switch (TLI.getOperationAction(Node->getOpcode(),
3035 Node->getValueType(0))) {
3036 default: assert(0 && "This action is not supported yet!");
3037 case TargetLowering::Legal: break;
3038 case TargetLowering::Custom:
3039 Tmp1 = TLI.LowerOperation(Result, DAG);
3040 if (Tmp1.getNode()) {
3041 SDValue Tmp2, RetVal(0, 0);
3042 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
3043 Tmp2 = LegalizeOp(Tmp1.getValue(i));
3044 AddLegalizedOperand(SDValue(Node, i), Tmp2);
3045 if (i == Op.getResNo())
3048 assert(RetVal.getNode() && "Illegal result number");
3054 // Since these produce multiple values, make sure to remember that we
3055 // legalized all of them.
3056 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
3057 AddLegalizedOperand(SDValue(Node, i), Result.getValue(i));
3058 return Result.getValue(Op.getResNo());
3080 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3081 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3082 case Expand: assert(0 && "Not possible");
3084 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3087 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3091 if ((Node->getOpcode() == ISD::SHL ||
3092 Node->getOpcode() == ISD::SRL ||
3093 Node->getOpcode() == ISD::SRA) &&
3094 !Node->getValueType(0).isVector()) {
3095 if (TLI.getShiftAmountTy().bitsLT(Tmp2.getValueType()))
3096 Tmp2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Tmp2);
3097 else if (TLI.getShiftAmountTy().bitsGT(Tmp2.getValueType()))
3098 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Tmp2);
3101 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3103 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3104 default: assert(0 && "BinOp legalize operation not supported");
3105 case TargetLowering::Legal: break;
3106 case TargetLowering::Custom:
3107 Tmp1 = TLI.LowerOperation(Result, DAG);
3108 if (Tmp1.getNode()) {
3112 // Fall through if the custom lower can't deal with the operation
3113 case TargetLowering::Expand: {
3114 MVT VT = Op.getValueType();
3116 // See if multiply or divide can be lowered using two-result operations.
3117 SDVTList VTs = DAG.getVTList(VT, VT);
3118 if (Node->getOpcode() == ISD::MUL) {
3119 // We just need the low half of the multiply; try both the signed
3120 // and unsigned forms. If the target supports both SMUL_LOHI and
3121 // UMUL_LOHI, form a preference by checking which forms of plain
3122 // MULH it supports.
3123 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT);
3124 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT);
3125 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT);
3126 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT);
3127 unsigned OpToUse = 0;
3128 if (HasSMUL_LOHI && !HasMULHS) {
3129 OpToUse = ISD::SMUL_LOHI;
3130 } else if (HasUMUL_LOHI && !HasMULHU) {
3131 OpToUse = ISD::UMUL_LOHI;
3132 } else if (HasSMUL_LOHI) {
3133 OpToUse = ISD::SMUL_LOHI;
3134 } else if (HasUMUL_LOHI) {
3135 OpToUse = ISD::UMUL_LOHI;
3138 Result = SDValue(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).getNode(), 0);
3142 if (Node->getOpcode() == ISD::MULHS &&
3143 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) {
3144 Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).getNode(),
3148 if (Node->getOpcode() == ISD::MULHU &&
3149 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) {
3150 Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).getNode(),
3154 if (Node->getOpcode() == ISD::SDIV &&
3155 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3156 Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(),
3160 if (Node->getOpcode() == ISD::UDIV &&
3161 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3162 Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(),
3167 // Check to see if we have a libcall for this operator.
3168 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3169 bool isSigned = false;
3170 switch (Node->getOpcode()) {
3173 if (VT == MVT::i32) {
3174 LC = Node->getOpcode() == ISD::UDIV
3175 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
3176 isSigned = Node->getOpcode() == ISD::SDIV;
3181 LC = RTLIB::MUL_I32;
3184 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
3185 RTLIB::POW_PPCF128);
3189 if (LC != RTLIB::UNKNOWN_LIBCALL) {
3191 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3195 assert(Node->getValueType(0).isVector() &&
3196 "Cannot expand this binary operator!");
3197 // Expand the operation into a bunch of nasty scalar code.
3198 Result = LegalizeOp(UnrollVectorOp(Op));
3201 case TargetLowering::Promote: {
3202 switch (Node->getOpcode()) {
3203 default: assert(0 && "Do not know how to promote this BinOp!");
3207 MVT OVT = Node->getValueType(0);
3208 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3209 assert(OVT.isVector() && "Cannot promote this BinOp!");
3210 // Bit convert each of the values to the new type.
3211 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
3212 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
3213 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3214 // Bit convert the result back the original type.
3215 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
3223 case ISD::SMUL_LOHI:
3224 case ISD::UMUL_LOHI:
3227 // These nodes will only be produced by target-specific lowering, so
3228 // they shouldn't be here if they aren't legal.
3229 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
3230 "This must be legal!");
3232 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3233 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3234 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3237 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
3238 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3239 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3240 case Expand: assert(0 && "Not possible");
3242 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3245 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3249 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3251 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3252 default: assert(0 && "Operation not supported");
3253 case TargetLowering::Custom:
3254 Tmp1 = TLI.LowerOperation(Result, DAG);
3255 if (Tmp1.getNode()) Result = Tmp1;
3257 case TargetLowering::Legal: break;
3258 case TargetLowering::Expand: {
3259 // If this target supports fabs/fneg natively and select is cheap,
3260 // do this efficiently.
3261 if (!TLI.isSelectExpensive() &&
3262 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
3263 TargetLowering::Legal &&
3264 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
3265 TargetLowering::Legal) {
3266 // Get the sign bit of the RHS.
3268 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
3269 SDValue SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
3270 SignBit = DAG.getSetCC(TLI.getSetCCResultType(SignBit),
3271 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
3272 // Get the absolute value of the result.
3273 SDValue AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
3274 // Select between the nabs and abs value based on the sign bit of
3276 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
3277 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
3280 Result = LegalizeOp(Result);
3284 // Otherwise, do bitwise ops!
3286 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
3287 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
3288 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
3289 Result = LegalizeOp(Result);
3297 Tmp1 = LegalizeOp(Node->getOperand(0));
3298 Tmp2 = LegalizeOp(Node->getOperand(1));
3299 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3300 // Since this produces two values, make sure to remember that we legalized
3302 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
3303 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
3308 Tmp1 = LegalizeOp(Node->getOperand(0));
3309 Tmp2 = LegalizeOp(Node->getOperand(1));
3310 Tmp3 = LegalizeOp(Node->getOperand(2));
3311 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3312 // Since this produces two values, make sure to remember that we legalized
3314 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
3315 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
3318 case ISD::BUILD_PAIR: {
3319 MVT PairTy = Node->getValueType(0);
3320 // TODO: handle the case where the Lo and Hi operands are not of legal type
3321 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
3322 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
3323 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
3324 case TargetLowering::Promote:
3325 case TargetLowering::Custom:
3326 assert(0 && "Cannot promote/custom this yet!");
3327 case TargetLowering::Legal:
3328 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
3329 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
3331 case TargetLowering::Expand:
3332 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
3333 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
3334 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
3335 DAG.getConstant(PairTy.getSizeInBits()/2,
3336 TLI.getShiftAmountTy()));
3337 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
3346 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3347 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3349 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3350 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
3351 case TargetLowering::Custom:
3354 case TargetLowering::Legal:
3355 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3357 Tmp1 = TLI.LowerOperation(Result, DAG);
3358 if (Tmp1.getNode()) Result = Tmp1;
3361 case TargetLowering::Expand: {
3362 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
3363 bool isSigned = DivOpc == ISD::SDIV;
3364 MVT VT = Node->getValueType(0);
3366 // See if remainder can be lowered using two-result operations.
3367 SDVTList VTs = DAG.getVTList(VT, VT);
3368 if (Node->getOpcode() == ISD::SREM &&
3369 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3370 Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(), 1);
3373 if (Node->getOpcode() == ISD::UREM &&
3374 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3375 Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(), 1);
3379 if (VT.isInteger()) {
3380 if (TLI.getOperationAction(DivOpc, VT) ==
3381 TargetLowering::Legal) {
3383 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
3384 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
3385 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
3386 } else if (VT.isVector()) {
3387 Result = LegalizeOp(UnrollVectorOp(Op));
3389 assert(VT == MVT::i32 &&
3390 "Cannot expand this binary operator!");
3391 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
3392 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
3394 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3397 assert(VT.isFloatingPoint() &&
3398 "remainder op must have integer or floating-point type");
3399 if (VT.isVector()) {
3400 Result = LegalizeOp(UnrollVectorOp(Op));
3402 // Floating point mod -> fmod libcall.
3403 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
3404 RTLIB::REM_F80, RTLIB::REM_PPCF128);
3406 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3414 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3415 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3417 MVT VT = Node->getValueType(0);
3418 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
3419 default: assert(0 && "This action is not supported yet!");
3420 case TargetLowering::Custom:
3423 case TargetLowering::Legal:
3424 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3425 Result = Result.getValue(0);
3426 Tmp1 = Result.getValue(1);
3429 Tmp2 = TLI.LowerOperation(Result, DAG);
3430 if (Tmp2.getNode()) {
3431 Result = LegalizeOp(Tmp2);
3432 Tmp1 = LegalizeOp(Tmp2.getValue(1));
3436 case TargetLowering::Expand: {
3437 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3438 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
3439 // Increment the pointer, VAList, to the next vaarg
3440 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3441 DAG.getConstant(TLI.getTargetData()->getABITypeSize(VT.getTypeForMVT()),
3442 TLI.getPointerTy()));
3443 // Store the incremented VAList to the legalized pointer
3444 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
3445 // Load the actual argument out of the pointer VAList
3446 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
3447 Tmp1 = LegalizeOp(Result.getValue(1));
3448 Result = LegalizeOp(Result);
3452 // Since VAARG produces two values, make sure to remember that we
3453 // legalized both of them.
3454 AddLegalizedOperand(SDValue(Node, 0), Result);
3455 AddLegalizedOperand(SDValue(Node, 1), Tmp1);
3456 return Op.getResNo() ? Tmp1 : Result;
3460 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3461 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
3462 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
3464 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
3465 default: assert(0 && "This action is not supported yet!");
3466 case TargetLowering::Custom:
3469 case TargetLowering::Legal:
3470 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
3471 Node->getOperand(3), Node->getOperand(4));
3473 Tmp1 = TLI.LowerOperation(Result, DAG);
3474 if (Tmp1.getNode()) Result = Tmp1;
3477 case TargetLowering::Expand:
3478 // This defaults to loading a pointer from the input and storing it to the
3479 // output, returning the chain.
3480 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3481 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3482 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VS, 0);
3483 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VD, 0);
3489 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3490 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3492 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
3493 default: assert(0 && "This action is not supported yet!");
3494 case TargetLowering::Custom:
3497 case TargetLowering::Legal:
3498 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3500 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
3501 if (Tmp1.getNode()) Result = Tmp1;
3504 case TargetLowering::Expand:
3505 Result = Tmp1; // Default to a no-op, return the chain
3511 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3512 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3514 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3516 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
3517 default: assert(0 && "This action is not supported yet!");
3518 case TargetLowering::Legal: break;
3519 case TargetLowering::Custom:
3520 Tmp1 = TLI.LowerOperation(Result, DAG);
3521 if (Tmp1.getNode()) Result = Tmp1;
3528 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3529 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3530 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3531 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3533 assert(0 && "ROTL/ROTR legalize operation not supported");
3535 case TargetLowering::Legal:
3537 case TargetLowering::Custom:
3538 Tmp1 = TLI.LowerOperation(Result, DAG);
3539 if (Tmp1.getNode()) Result = Tmp1;
3541 case TargetLowering::Promote:
3542 assert(0 && "Do not know how to promote ROTL/ROTR");
3544 case TargetLowering::Expand:
3545 assert(0 && "Do not know how to expand ROTL/ROTR");
3551 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3552 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3553 case TargetLowering::Custom:
3554 assert(0 && "Cannot custom legalize this yet!");
3555 case TargetLowering::Legal:
3556 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3558 case TargetLowering::Promote: {
3559 MVT OVT = Tmp1.getValueType();
3560 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3561 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3563 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3564 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3565 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3566 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3569 case TargetLowering::Expand:
3570 Result = ExpandBSWAP(Tmp1);
3578 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3579 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3580 case TargetLowering::Custom:
3581 case TargetLowering::Legal:
3582 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3583 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3584 TargetLowering::Custom) {
3585 Tmp1 = TLI.LowerOperation(Result, DAG);
3586 if (Tmp1.getNode()) {
3591 case TargetLowering::Promote: {
3592 MVT OVT = Tmp1.getValueType();
3593 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3595 // Zero extend the argument.
3596 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3597 // Perform the larger operation, then subtract if needed.
3598 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
3599 switch (Node->getOpcode()) {
3604 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3605 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
3606 DAG.getConstant(NVT.getSizeInBits(), NVT),
3608 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3609 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3612 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3613 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3614 DAG.getConstant(NVT.getSizeInBits() -
3615 OVT.getSizeInBits(), NVT));
3620 case TargetLowering::Expand:
3621 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
3641 case ISD::FNEARBYINT:
3642 Tmp1 = LegalizeOp(Node->getOperand(0));
3643 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3644 case TargetLowering::Promote:
3645 case TargetLowering::Custom:
3648 case TargetLowering::Legal:
3649 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3651 Tmp1 = TLI.LowerOperation(Result, DAG);
3652 if (Tmp1.getNode()) Result = Tmp1;
3655 case TargetLowering::Expand:
3656 switch (Node->getOpcode()) {
3657 default: assert(0 && "Unreachable!");
3659 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3660 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3661 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
3664 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3665 MVT VT = Node->getValueType(0);
3666 Tmp2 = DAG.getConstantFP(0.0, VT);
3667 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
3669 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
3670 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
3685 case ISD::FNEARBYINT: {
3686 MVT VT = Node->getValueType(0);
3688 // Expand unsupported unary vector operators by unrolling them.
3689 if (VT.isVector()) {
3690 Result = LegalizeOp(UnrollVectorOp(Op));
3694 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3695 switch(Node->getOpcode()) {
3697 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3698 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
3701 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
3702 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
3705 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
3706 RTLIB::COS_F80, RTLIB::COS_PPCF128);
3709 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
3710 RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
3713 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3714 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
3717 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3718 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
3721 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
3722 RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
3725 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3726 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
3729 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3730 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
3733 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3734 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128);
3737 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3738 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128);
3741 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64,
3742 RTLIB::RINT_F80, RTLIB::RINT_PPCF128);
3744 case ISD::FNEARBYINT:
3745 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
3746 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
3749 default: assert(0 && "Unreachable!");
3752 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3760 MVT VT = Node->getValueType(0);
3762 // Expand unsupported unary vector operators by unrolling them.
3763 if (VT.isVector()) {
3764 Result = LegalizeOp(UnrollVectorOp(Op));
3768 // We always lower FPOWI into a libcall. No target support for it yet.
3769 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
3770 RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
3772 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3775 case ISD::BIT_CONVERT:
3776 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3777 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3778 Node->getValueType(0));
3779 } else if (Op.getOperand(0).getValueType().isVector()) {
3780 // The input has to be a vector type, we have to either scalarize it, pack
3781 // it, or convert it based on whether the input vector type is legal.
3782 SDNode *InVal = Node->getOperand(0).getNode();
3783 int InIx = Node->getOperand(0).getResNo();
3784 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
3785 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
3787 // Figure out if there is a simple type corresponding to this Vector
3788 // type. If so, convert to the vector type.
3789 MVT TVT = MVT::getVectorVT(EVT, NumElems);
3790 if (TLI.isTypeLegal(TVT)) {
3791 // Turn this into a bit convert of the vector input.
3792 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3793 LegalizeOp(Node->getOperand(0)));
3795 } else if (NumElems == 1) {
3796 // Turn this into a bit convert of the scalar input.
3797 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3798 ScalarizeVectorOp(Node->getOperand(0)));
3801 // FIXME: UNIMP! Store then reload
3802 assert(0 && "Cast from unsupported vector type not implemented yet!");
3805 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3806 Node->getOperand(0).getValueType())) {
3807 default: assert(0 && "Unknown operation action!");
3808 case TargetLowering::Expand:
3809 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3810 Node->getValueType(0));
3812 case TargetLowering::Legal:
3813 Tmp1 = LegalizeOp(Node->getOperand(0));
3814 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3819 case ISD::CONVERT_RNDSAT: {
3820 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
3822 default: assert(0 && "Unknown cvt code!");
3833 SDValue DTyOp = Node->getOperand(1);
3834 SDValue STyOp = Node->getOperand(2);
3835 SDValue RndOp = Node->getOperand(3);
3836 SDValue SatOp = Node->getOperand(4);
3837 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3838 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3840 Tmp1 = LegalizeOp(Node->getOperand(0));
3841 Result = DAG.UpdateNodeOperands(Result, Tmp1, DTyOp, STyOp,
3843 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3844 TargetLowering::Custom) {
3845 Tmp1 = TLI.LowerOperation(Result, DAG);
3846 if (Tmp1.getNode()) Result = Tmp1;
3850 Result = PromoteOp(Node->getOperand(0));
3851 // For FP, make Op1 a i32
3853 Result = DAG.getConvertRndSat(Result.getValueType(), Result,
3854 DTyOp, STyOp, RndOp, SatOp, CvtCode);
3859 } // end switch CvtCode
3862 // Conversion operators. The source and destination have different types.
3863 case ISD::SINT_TO_FP:
3864 case ISD::UINT_TO_FP: {
3865 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
3866 Result = LegalizeINT_TO_FP(Result, isSigned,
3867 Node->getValueType(0), Node->getOperand(0));
3871 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3873 Tmp1 = LegalizeOp(Node->getOperand(0));
3874 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3877 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3879 // Since the result is legal, we should just be able to truncate the low
3880 // part of the source.
3881 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
3884 Result = PromoteOp(Node->getOperand(0));
3885 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
3890 case ISD::FP_TO_SINT:
3891 case ISD::FP_TO_UINT:
3892 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3894 Tmp1 = LegalizeOp(Node->getOperand(0));
3896 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
3897 default: assert(0 && "Unknown operation action!");
3898 case TargetLowering::Custom:
3901 case TargetLowering::Legal:
3902 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3904 Tmp1 = TLI.LowerOperation(Result, DAG);
3905 if (Tmp1.getNode()) Result = Tmp1;
3908 case TargetLowering::Promote:
3909 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
3910 Node->getOpcode() == ISD::FP_TO_SINT);
3912 case TargetLowering::Expand:
3913 if (Node->getOpcode() == ISD::FP_TO_UINT) {
3914 SDValue True, False;
3915 MVT VT = Node->getOperand(0).getValueType();
3916 MVT NVT = Node->getValueType(0);
3917 const uint64_t zero[] = {0, 0};
3918 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero));
3919 APInt x = APInt::getSignBit(NVT.getSizeInBits());
3920 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
3921 Tmp2 = DAG.getConstantFP(apf, VT);
3922 Tmp3 = DAG.getSetCC(TLI.getSetCCResultType(Node->getOperand(0)),
3923 Node->getOperand(0), Tmp2, ISD::SETLT);
3924 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
3925 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
3926 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
3928 False = DAG.getNode(ISD::XOR, NVT, False,
3929 DAG.getConstant(x, NVT));
3930 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
3933 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
3939 MVT VT = Op.getValueType();
3940 MVT OVT = Node->getOperand(0).getValueType();
3941 // Convert ppcf128 to i32
3942 if (OVT == MVT::ppcf128 && VT == MVT::i32) {
3943 if (Node->getOpcode() == ISD::FP_TO_SINT) {
3944 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128,
3945 Node->getOperand(0), DAG.getValueType(MVT::f64));
3946 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result,
3947 DAG.getIntPtrConstant(1));
3948 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result);
3950 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
3951 APFloat apf = APFloat(APInt(128, 2, TwoE31));
3952 Tmp2 = DAG.getConstantFP(apf, OVT);
3953 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
3954 // FIXME: generated code sucks.
3955 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2,
3956 DAG.getNode(ISD::ADD, MVT::i32,
3957 DAG.getNode(ISD::FP_TO_SINT, VT,
3958 DAG.getNode(ISD::FSUB, OVT,
3959 Node->getOperand(0), Tmp2)),
3960 DAG.getConstant(0x80000000, MVT::i32)),
3961 DAG.getNode(ISD::FP_TO_SINT, VT,
3962 Node->getOperand(0)),
3963 DAG.getCondCode(ISD::SETGE));
3967 // Convert f32 / f64 to i32 / i64 / i128.
3968 RTLIB::Libcall LC = (Node->getOpcode() == ISD::FP_TO_SINT) ?
3969 RTLIB::getFPTOSINT(OVT, VT) : RTLIB::getFPTOUINT(OVT, VT);
3970 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpectd fp-to-int conversion!");
3972 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3976 Tmp1 = PromoteOp(Node->getOperand(0));
3977 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
3978 Result = LegalizeOp(Result);
3983 case ISD::FP_EXTEND: {
3984 MVT DstVT = Op.getValueType();
3985 MVT SrcVT = Op.getOperand(0).getValueType();
3986 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3987 // The only other way we can lower this is to turn it into a STORE,
3988 // LOAD pair, targetting a temporary location (a stack slot).
3989 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT);
3992 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3993 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3995 Tmp1 = LegalizeOp(Node->getOperand(0));
3996 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3999 Tmp1 = PromoteOp(Node->getOperand(0));
4000 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1);
4005 case ISD::FP_ROUND: {
4006 MVT DstVT = Op.getValueType();
4007 MVT SrcVT = Op.getOperand(0).getValueType();
4008 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
4009 if (SrcVT == MVT::ppcf128) {
4011 ExpandOp(Node->getOperand(0), Lo, Result);
4012 // Round it the rest of the way (e.g. to f32) if needed.
4013 if (DstVT!=MVT::f64)
4014 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1));
4017 // The only other way we can lower this is to turn it into a STORE,
4018 // LOAD pair, targetting a temporary location (a stack slot).
4019 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT);
4022 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4023 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4025 Tmp1 = LegalizeOp(Node->getOperand(0));
4026 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
4029 Tmp1 = PromoteOp(Node->getOperand(0));
4030 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1,
4031 Node->getOperand(1));
4036 case ISD::ANY_EXTEND:
4037 case ISD::ZERO_EXTEND:
4038 case ISD::SIGN_EXTEND:
4039 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4040 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4042 Tmp1 = LegalizeOp(Node->getOperand(0));
4043 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4044 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
4045 TargetLowering::Custom) {
4046 Tmp1 = TLI.LowerOperation(Result, DAG);
4047 if (Tmp1.getNode()) Result = Tmp1;
4051 switch (Node->getOpcode()) {
4052 case ISD::ANY_EXTEND:
4053 Tmp1 = PromoteOp(Node->getOperand(0));
4054 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
4056 case ISD::ZERO_EXTEND:
4057 Result = PromoteOp(Node->getOperand(0));
4058 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
4059 Result = DAG.getZeroExtendInReg(Result,
4060 Node->getOperand(0).getValueType());
4062 case ISD::SIGN_EXTEND:
4063 Result = PromoteOp(Node->getOperand(0));
4064 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
4065 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
4067 DAG.getValueType(Node->getOperand(0).getValueType()));
4072 case ISD::FP_ROUND_INREG:
4073 case ISD::SIGN_EXTEND_INREG: {
4074 Tmp1 = LegalizeOp(Node->getOperand(0));
4075 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
4077 // If this operation is not supported, convert it to a shl/shr or load/store
4079 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
4080 default: assert(0 && "This action not supported for this op yet!");
4081 case TargetLowering::Legal:
4082 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
4084 case TargetLowering::Expand:
4085 // If this is an integer extend and shifts are supported, do that.
4086 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
4087 // NOTE: we could fall back on load/store here too for targets without
4088 // SAR. However, it is doubtful that any exist.
4089 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() -
4090 ExtraVT.getSizeInBits();
4091 SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
4092 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
4093 Node->getOperand(0), ShiftCst);
4094 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
4096 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
4097 // The only way we can lower this is to turn it into a TRUNCSTORE,
4098 // EXTLOAD pair, targetting a temporary location (a stack slot).
4100 // NOTE: there is a choice here between constantly creating new stack
4101 // slots and always reusing the same one. We currently always create
4102 // new ones, as reuse may inhibit scheduling.
4103 Result = EmitStackConvert(Node->getOperand(0), ExtraVT,
4104 Node->getValueType(0));
4106 assert(0 && "Unknown op");
4112 case ISD::TRAMPOLINE: {
4114 for (unsigned i = 0; i != 6; ++i)
4115 Ops[i] = LegalizeOp(Node->getOperand(i));
4116 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
4117 // The only option for this node is to custom lower it.
4118 Result = TLI.LowerOperation(Result, DAG);
4119 assert(Result.getNode() && "Should always custom lower!");
4121 // Since trampoline produces two values, make sure to remember that we
4122 // legalized both of them.
4123 Tmp1 = LegalizeOp(Result.getValue(1));
4124 Result = LegalizeOp(Result);
4125 AddLegalizedOperand(SDValue(Node, 0), Result);
4126 AddLegalizedOperand(SDValue(Node, 1), Tmp1);
4127 return Op.getResNo() ? Tmp1 : Result;
4129 case ISD::FLT_ROUNDS_: {
4130 MVT VT = Node->getValueType(0);
4131 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4132 default: assert(0 && "This action not supported for this op yet!");
4133 case TargetLowering::Custom:
4134 Result = TLI.LowerOperation(Op, DAG);
4135 if (Result.getNode()) break;
4137 case TargetLowering::Legal:
4138 // If this operation is not supported, lower it to constant 1
4139 Result = DAG.getConstant(1, VT);
4145 MVT VT = Node->getValueType(0);
4146 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4147 default: assert(0 && "This action not supported for this op yet!");
4148 case TargetLowering::Legal:
4149 Tmp1 = LegalizeOp(Node->getOperand(0));
4150 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4152 case TargetLowering::Custom:
4153 Result = TLI.LowerOperation(Op, DAG);
4154 if (Result.getNode()) break;
4156 case TargetLowering::Expand:
4157 // If this operation is not supported, lower it to 'abort()' call
4158 Tmp1 = LegalizeOp(Node->getOperand(0));
4159 TargetLowering::ArgListTy Args;
4160 std::pair<SDValue,SDValue> CallResult =
4161 TLI.LowerCallTo(Tmp1, Type::VoidTy,
4162 false, false, false, false, CallingConv::C, false,
4163 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
4165 Result = CallResult.second;
4172 assert(Result.getValueType() == Op.getValueType() &&
4173 "Bad legalization!");
4175 // Make sure that the generated code is itself legal.
4177 Result = LegalizeOp(Result);
4179 // Note that LegalizeOp may be reentered even from single-use nodes, which
4180 // means that we always must cache transformed nodes.
4181 AddLegalizedOperand(Op, Result);
4185 /// PromoteOp - Given an operation that produces a value in an invalid type,
4186 /// promote it to compute the value into a larger type. The produced value will
4187 /// have the correct bits for the low portion of the register, but no guarantee
4188 /// is made about the top bits: it may be zero, sign-extended, or garbage.
4189 SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) {
4190 MVT VT = Op.getValueType();
4191 MVT NVT = TLI.getTypeToTransformTo(VT);
4192 assert(getTypeAction(VT) == Promote &&
4193 "Caller should expand or legalize operands that are not promotable!");
4194 assert(NVT.bitsGT(VT) && NVT.isInteger() == VT.isInteger() &&
4195 "Cannot promote to smaller type!");
4197 SDValue Tmp1, Tmp2, Tmp3;
4199 SDNode *Node = Op.getNode();
4201 DenseMap<SDValue, SDValue>::iterator I = PromotedNodes.find(Op);
4202 if (I != PromotedNodes.end()) return I->second;
4204 switch (Node->getOpcode()) {
4205 case ISD::CopyFromReg:
4206 assert(0 && "CopyFromReg must be legal!");
4209 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
4211 assert(0 && "Do not know how to promote this operator!");
4214 Result = DAG.getNode(ISD::UNDEF, NVT);
4218 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
4220 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
4221 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
4223 case ISD::ConstantFP:
4224 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
4225 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
4229 assert(isTypeLegal(TLI.getSetCCResultType(Node->getOperand(0)))
4230 && "SetCC type is not legal??");
4231 Result = DAG.getNode(ISD::SETCC,
4232 TLI.getSetCCResultType(Node->getOperand(0)),
4233 Node->getOperand(0), Node->getOperand(1),
4234 Node->getOperand(2));
4238 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4240 Result = LegalizeOp(Node->getOperand(0));
4241 assert(Result.getValueType().bitsGE(NVT) &&
4242 "This truncation doesn't make sense!");
4243 if (Result.getValueType().bitsGT(NVT)) // Truncate to NVT instead of VT
4244 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
4247 // The truncation is not required, because we don't guarantee anything
4248 // about high bits anyway.
4249 Result = PromoteOp(Node->getOperand(0));
4252 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4253 // Truncate the low part of the expanded value to the result type
4254 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
4257 case ISD::SIGN_EXTEND:
4258 case ISD::ZERO_EXTEND:
4259 case ISD::ANY_EXTEND:
4260 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4261 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
4263 // Input is legal? Just do extend all the way to the larger type.
4264 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4267 // Promote the reg if it's smaller.
4268 Result = PromoteOp(Node->getOperand(0));
4269 // The high bits are not guaranteed to be anything. Insert an extend.
4270 if (Node->getOpcode() == ISD::SIGN_EXTEND)
4271 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4272 DAG.getValueType(Node->getOperand(0).getValueType()));
4273 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
4274 Result = DAG.getZeroExtendInReg(Result,
4275 Node->getOperand(0).getValueType());
4279 case ISD::CONVERT_RNDSAT: {
4280 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
4281 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
4282 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
4283 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
4284 "can only promote integers");
4285 Result = DAG.getConvertRndSat(NVT, Node->getOperand(0),
4286 Node->getOperand(1), Node->getOperand(2),
4287 Node->getOperand(3), Node->getOperand(4),
4292 case ISD::BIT_CONVERT:
4293 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
4294 Node->getValueType(0));
4295 Result = PromoteOp(Result);
4298 case ISD::FP_EXTEND:
4299 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
4301 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4302 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
4303 case Promote: assert(0 && "Unreachable with 2 FP types!");
4305 if (Node->getConstantOperandVal(1) == 0) {
4306 // Input is legal? Do an FP_ROUND_INREG.
4307 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
4308 DAG.getValueType(VT));
4310 // Just remove the truncate, it isn't affecting the value.
4311 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0),
4312 Node->getOperand(1));
4317 case ISD::SINT_TO_FP:
4318 case ISD::UINT_TO_FP:
4319 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4321 // No extra round required here.
4322 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4326 Result = PromoteOp(Node->getOperand(0));
4327 if (Node->getOpcode() == ISD::SINT_TO_FP)
4328 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
4330 DAG.getValueType(Node->getOperand(0).getValueType()));
4332 Result = DAG.getZeroExtendInReg(Result,
4333 Node->getOperand(0).getValueType());
4334 // No extra round required here.
4335 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
4338 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
4339 Node->getOperand(0));
4340 // Round if we cannot tolerate excess precision.
4341 if (NoExcessFPPrecision)
4342 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4343 DAG.getValueType(VT));
4348 case ISD::SIGN_EXTEND_INREG:
4349 Result = PromoteOp(Node->getOperand(0));
4350 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4351 Node->getOperand(1));
4353 case ISD::FP_TO_SINT:
4354 case ISD::FP_TO_UINT:
4355 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4358 Tmp1 = Node->getOperand(0);
4361 // The input result is prerounded, so we don't have to do anything
4363 Tmp1 = PromoteOp(Node->getOperand(0));
4366 // If we're promoting a UINT to a larger size, check to see if the new node
4367 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
4368 // we can use that instead. This allows us to generate better code for
4369 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
4370 // legal, such as PowerPC.
4371 if (Node->getOpcode() == ISD::FP_TO_UINT &&
4372 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
4373 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
4374 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
4375 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
4377 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4383 Tmp1 = PromoteOp(Node->getOperand(0));
4384 assert(Tmp1.getValueType() == NVT);
4385 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4386 // NOTE: we do not have to do any extra rounding here for
4387 // NoExcessFPPrecision, because we know the input will have the appropriate
4388 // precision, and these operations don't modify precision at all.
4403 case ISD::FNEARBYINT:
4404 Tmp1 = PromoteOp(Node->getOperand(0));
4405 assert(Tmp1.getValueType() == NVT);
4406 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4407 if (NoExcessFPPrecision)
4408 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4409 DAG.getValueType(VT));
4414 // Promote f32 pow(i) to f64 pow(i). Note that this could insert a libcall
4415 // directly as well, which may be better.
4416 Tmp1 = PromoteOp(Node->getOperand(0));
4417 Tmp2 = Node->getOperand(1);
4418 if (Node->getOpcode() == ISD::FPOW)
4419 Tmp2 = PromoteOp(Tmp2);
4420 assert(Tmp1.getValueType() == NVT);
4421 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4422 if (NoExcessFPPrecision)
4423 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4424 DAG.getValueType(VT));
4428 case ISD::ATOMIC_CMP_SWAP_8:
4429 case ISD::ATOMIC_CMP_SWAP_16:
4430 case ISD::ATOMIC_CMP_SWAP_32:
4431 case ISD::ATOMIC_CMP_SWAP_64: {
4432 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4433 Tmp2 = PromoteOp(Node->getOperand(2));
4434 Tmp3 = PromoteOp(Node->getOperand(3));
4435 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(),
4436 AtomNode->getBasePtr(), Tmp2, Tmp3,
4437 AtomNode->getSrcValue(),
4438 AtomNode->getAlignment());
4439 // Remember that we legalized the chain.
4440 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4443 case ISD::ATOMIC_LOAD_ADD_8:
4444 case ISD::ATOMIC_LOAD_SUB_8:
4445 case ISD::ATOMIC_LOAD_AND_8:
4446 case ISD::ATOMIC_LOAD_OR_8:
4447 case ISD::ATOMIC_LOAD_XOR_8:
4448 case ISD::ATOMIC_LOAD_NAND_8:
4449 case ISD::ATOMIC_LOAD_MIN_8:
4450 case ISD::ATOMIC_LOAD_MAX_8:
4451 case ISD::ATOMIC_LOAD_UMIN_8:
4452 case ISD::ATOMIC_LOAD_UMAX_8:
4453 case ISD::ATOMIC_SWAP_8:
4454 case ISD::ATOMIC_LOAD_ADD_16:
4455 case ISD::ATOMIC_LOAD_SUB_16:
4456 case ISD::ATOMIC_LOAD_AND_16:
4457 case ISD::ATOMIC_LOAD_OR_16:
4458 case ISD::ATOMIC_LOAD_XOR_16:
4459 case ISD::ATOMIC_LOAD_NAND_16:
4460 case ISD::ATOMIC_LOAD_MIN_16:
4461 case ISD::ATOMIC_LOAD_MAX_16:
4462 case ISD::ATOMIC_LOAD_UMIN_16:
4463 case ISD::ATOMIC_LOAD_UMAX_16:
4464 case ISD::ATOMIC_SWAP_16:
4465 case ISD::ATOMIC_LOAD_ADD_32:
4466 case ISD::ATOMIC_LOAD_SUB_32:
4467 case ISD::ATOMIC_LOAD_AND_32:
4468 case ISD::ATOMIC_LOAD_OR_32:
4469 case ISD::ATOMIC_LOAD_XOR_32:
4470 case ISD::ATOMIC_LOAD_NAND_32:
4471 case ISD::ATOMIC_LOAD_MIN_32:
4472 case ISD::ATOMIC_LOAD_MAX_32:
4473 case ISD::ATOMIC_LOAD_UMIN_32:
4474 case ISD::ATOMIC_LOAD_UMAX_32:
4475 case ISD::ATOMIC_SWAP_32:
4476 case ISD::ATOMIC_LOAD_ADD_64:
4477 case ISD::ATOMIC_LOAD_SUB_64:
4478 case ISD::ATOMIC_LOAD_AND_64:
4479 case ISD::ATOMIC_LOAD_OR_64:
4480 case ISD::ATOMIC_LOAD_XOR_64:
4481 case ISD::ATOMIC_LOAD_NAND_64:
4482 case ISD::ATOMIC_LOAD_MIN_64:
4483 case ISD::ATOMIC_LOAD_MAX_64:
4484 case ISD::ATOMIC_LOAD_UMIN_64:
4485 case ISD::ATOMIC_LOAD_UMAX_64:
4486 case ISD::ATOMIC_SWAP_64: {
4487 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4488 Tmp2 = PromoteOp(Node->getOperand(2));
4489 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(),
4490 AtomNode->getBasePtr(), Tmp2,
4491 AtomNode->getSrcValue(),
4492 AtomNode->getAlignment());
4493 // Remember that we legalized the chain.
4494 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4504 // The input may have strange things in the top bits of the registers, but
4505 // these operations don't care. They may have weird bits going out, but
4506 // that too is okay if they are integer operations.
4507 Tmp1 = PromoteOp(Node->getOperand(0));
4508 Tmp2 = PromoteOp(Node->getOperand(1));
4509 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4510 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4515 Tmp1 = PromoteOp(Node->getOperand(0));
4516 Tmp2 = PromoteOp(Node->getOperand(1));
4517 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4518 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4520 // Floating point operations will give excess precision that we may not be
4521 // able to tolerate. If we DO allow excess precision, just leave it,
4522 // otherwise excise it.
4523 // FIXME: Why would we need to round FP ops more than integer ones?
4524 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
4525 if (NoExcessFPPrecision)
4526 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4527 DAG.getValueType(VT));
4532 // These operators require that their input be sign extended.
4533 Tmp1 = PromoteOp(Node->getOperand(0));
4534 Tmp2 = PromoteOp(Node->getOperand(1));
4535 if (NVT.isInteger()) {
4536 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4537 DAG.getValueType(VT));
4538 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4539 DAG.getValueType(VT));
4541 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4543 // Perform FP_ROUND: this is probably overly pessimistic.
4544 if (NVT.isFloatingPoint() && NoExcessFPPrecision)
4545 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4546 DAG.getValueType(VT));
4550 case ISD::FCOPYSIGN:
4551 // These operators require that their input be fp extended.
4552 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4553 case Expand: assert(0 && "not implemented");
4554 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break;
4555 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break;
4557 switch (getTypeAction(Node->getOperand(1).getValueType())) {
4558 case Expand: assert(0 && "not implemented");
4559 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
4560 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
4562 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4564 // Perform FP_ROUND: this is probably overly pessimistic.
4565 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
4566 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4567 DAG.getValueType(VT));
4572 // These operators require that their input be zero extended.
4573 Tmp1 = PromoteOp(Node->getOperand(0));
4574 Tmp2 = PromoteOp(Node->getOperand(1));
4575 assert(NVT.isInteger() && "Operators don't apply to FP!");
4576 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4577 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4578 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4582 Tmp1 = PromoteOp(Node->getOperand(0));
4583 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
4586 // The input value must be properly sign extended.
4587 Tmp1 = PromoteOp(Node->getOperand(0));
4588 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4589 DAG.getValueType(VT));
4590 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
4593 // The input value must be properly zero extended.
4594 Tmp1 = PromoteOp(Node->getOperand(0));
4595 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4596 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
4600 Tmp1 = Node->getOperand(0); // Get the chain.
4601 Tmp2 = Node->getOperand(1); // Get the pointer.
4602 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
4603 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
4604 Result = TLI.LowerOperation(Tmp3, DAG);
4606 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
4607 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
4608 // Increment the pointer, VAList, to the next vaarg
4609 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
4610 DAG.getConstant(VT.getSizeInBits()/8,
4611 TLI.getPointerTy()));
4612 // Store the incremented VAList to the legalized pointer
4613 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
4614 // Load the actual argument out of the pointer VAList
4615 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
4617 // Remember that we legalized the chain.
4618 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4622 LoadSDNode *LD = cast<LoadSDNode>(Node);
4623 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
4624 ? ISD::EXTLOAD : LD->getExtensionType();
4625 Result = DAG.getExtLoad(ExtType, NVT,
4626 LD->getChain(), LD->getBasePtr(),
4627 LD->getSrcValue(), LD->getSrcValueOffset(),
4630 LD->getAlignment());
4631 // Remember that we legalized the chain.
4632 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4636 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
4637 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
4639 MVT VT2 = Tmp2.getValueType();
4640 assert(VT2 == Tmp3.getValueType()
4641 && "PromoteOp SELECT: Operands 2 and 3 ValueTypes don't match");
4642 // Ensure that the resulting node is at least the same size as the operands'
4643 // value types, because we cannot assume that TLI.getSetCCValueType() is
4645 Result = DAG.getNode(ISD::SELECT, VT2, Node->getOperand(0), Tmp2, Tmp3);
4648 case ISD::SELECT_CC:
4649 Tmp2 = PromoteOp(Node->getOperand(2)); // True
4650 Tmp3 = PromoteOp(Node->getOperand(3)); // False
4651 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4652 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
4655 Tmp1 = Node->getOperand(0);
4656 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
4657 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
4658 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
4659 DAG.getConstant(NVT.getSizeInBits() -
4661 TLI.getShiftAmountTy()));
4666 // Zero extend the argument
4667 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4668 // Perform the larger operation, then subtract if needed.
4669 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4670 switch(Node->getOpcode()) {
4675 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
4676 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
4677 DAG.getConstant(NVT.getSizeInBits(), NVT),
4679 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
4680 DAG.getConstant(VT.getSizeInBits(), NVT), Tmp1);
4683 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4684 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
4685 DAG.getConstant(NVT.getSizeInBits() -
4686 VT.getSizeInBits(), NVT));
4690 case ISD::EXTRACT_SUBVECTOR:
4691 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
4693 case ISD::EXTRACT_VECTOR_ELT:
4694 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
4698 assert(Result.getNode() && "Didn't set a result!");
4700 // Make sure the result is itself legal.
4701 Result = LegalizeOp(Result);
4703 // Remember that we promoted this!
4704 AddPromotedOperand(Op, Result);
4708 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
4709 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
4710 /// based on the vector type. The return type of this matches the element type
4711 /// of the vector, which may not be legal for the target.
4712 SDValue SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDValue Op) {
4713 // We know that operand #0 is the Vec vector. If the index is a constant
4714 // or if the invec is a supported hardware type, we can use it. Otherwise,
4715 // lower to a store then an indexed load.
4716 SDValue Vec = Op.getOperand(0);
4717 SDValue Idx = Op.getOperand(1);
4719 MVT TVT = Vec.getValueType();
4720 unsigned NumElems = TVT.getVectorNumElements();
4722 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
4723 default: assert(0 && "This action is not supported yet!");
4724 case TargetLowering::Custom: {
4725 Vec = LegalizeOp(Vec);
4726 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4727 SDValue Tmp3 = TLI.LowerOperation(Op, DAG);
4732 case TargetLowering::Legal:
4733 if (isTypeLegal(TVT)) {
4734 Vec = LegalizeOp(Vec);
4735 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4739 case TargetLowering::Promote:
4740 assert(TVT.isVector() && "not vector type");
4741 // fall thru to expand since vectors are by default are promote
4742 case TargetLowering::Expand:
4746 if (NumElems == 1) {
4747 // This must be an access of the only element. Return it.
4748 Op = ScalarizeVectorOp(Vec);
4749 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
4750 unsigned NumLoElts = 1 << Log2_32(NumElems-1);
4751 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4753 SplitVectorOp(Vec, Lo, Hi);
4754 if (CIdx->getZExtValue() < NumLoElts) {
4758 Idx = DAG.getConstant(CIdx->getZExtValue() - NumLoElts,
4759 Idx.getValueType());
4762 // It's now an extract from the appropriate high or low part. Recurse.
4763 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4764 Op = ExpandEXTRACT_VECTOR_ELT(Op);
4766 // Store the value to a temporary stack slot, then LOAD the scalar
4767 // element back out.
4768 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
4769 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
4771 // Add the offset to the index.
4772 unsigned EltSize = Op.getValueType().getSizeInBits()/8;
4773 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
4774 DAG.getConstant(EltSize, Idx.getValueType()));
4776 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
4777 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx);
4779 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
4781 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
4783 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
4788 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
4789 /// we assume the operation can be split if it is not already legal.
4790 SDValue SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDValue Op) {
4791 // We know that operand #0 is the Vec vector. For now we assume the index
4792 // is a constant and that the extracted result is a supported hardware type.
4793 SDValue Vec = Op.getOperand(0);
4794 SDValue Idx = LegalizeOp(Op.getOperand(1));
4796 unsigned NumElems = Vec.getValueType().getVectorNumElements();
4798 if (NumElems == Op.getValueType().getVectorNumElements()) {
4799 // This must be an access of the desired vector length. Return it.
4803 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4805 SplitVectorOp(Vec, Lo, Hi);
4806 if (CIdx->getZExtValue() < NumElems/2) {
4810 Idx = DAG.getConstant(CIdx->getZExtValue() - NumElems/2,
4811 Idx.getValueType());
4814 // It's now an extract from the appropriate high or low part. Recurse.
4815 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4816 return ExpandEXTRACT_SUBVECTOR(Op);
4819 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
4820 /// with condition CC on the current target. This usually involves legalizing
4821 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
4822 /// there may be no choice but to create a new SetCC node to represent the
4823 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
4824 /// LHS, and the SDValue returned in RHS has a nil SDNode value.
4825 void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS,
4828 SDValue Tmp1, Tmp2, Tmp3, Result;
4830 switch (getTypeAction(LHS.getValueType())) {
4832 Tmp1 = LegalizeOp(LHS); // LHS
4833 Tmp2 = LegalizeOp(RHS); // RHS
4836 Tmp1 = PromoteOp(LHS); // LHS
4837 Tmp2 = PromoteOp(RHS); // RHS
4839 // If this is an FP compare, the operands have already been extended.
4840 if (LHS.getValueType().isInteger()) {
4841 MVT VT = LHS.getValueType();
4842 MVT NVT = TLI.getTypeToTransformTo(VT);
4844 // Otherwise, we have to insert explicit sign or zero extends. Note
4845 // that we could insert sign extends for ALL conditions, but zero extend
4846 // is cheaper on many machines (an AND instead of two shifts), so prefer
4848 switch (cast<CondCodeSDNode>(CC)->get()) {
4849 default: assert(0 && "Unknown integer comparison!");
4856 // ALL of these operations will work if we either sign or zero extend
4857 // the operands (including the unsigned comparisons!). Zero extend is
4858 // usually a simpler/cheaper operation, so prefer it.
4859 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4860 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4866 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4867 DAG.getValueType(VT));
4868 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4869 DAG.getValueType(VT));
4870 Tmp1 = LegalizeOp(Tmp1); // Relegalize new nodes.
4871 Tmp2 = LegalizeOp(Tmp2); // Relegalize new nodes.
4877 MVT VT = LHS.getValueType();
4878 if (VT == MVT::f32 || VT == MVT::f64) {
4879 // Expand into one or more soft-fp libcall(s).
4880 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
4881 switch (cast<CondCodeSDNode>(CC)->get()) {
4884 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4888 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
4892 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4896 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4900 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4904 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4907 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4910 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
4913 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4914 switch (cast<CondCodeSDNode>(CC)->get()) {
4916 // SETONE = SETOLT | SETOGT
4917 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4920 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4923 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4926 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4929 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4932 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4934 default: assert(0 && "Unsupported FP setcc!");
4939 SDValue Ops[2] = { LHS, RHS };
4940 Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2).getNode(),
4941 false /*sign irrelevant*/, Dummy);
4942 Tmp2 = DAG.getConstant(0, MVT::i32);
4943 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
4944 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
4945 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
4947 LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2).getNode(),
4948 false /*sign irrelevant*/, Dummy);
4949 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, Tmp2,
4950 DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
4951 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4954 LHS = LegalizeOp(Tmp1);
4959 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
4960 ExpandOp(LHS, LHSLo, LHSHi);
4961 ExpandOp(RHS, RHSLo, RHSHi);
4962 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
4964 if (VT==MVT::ppcf128) {
4965 // FIXME: This generated code sucks. We want to generate
4966 // FCMPU crN, hi1, hi2
4968 // FCMPU crN, lo1, lo2
4969 // The following can be improved, but not that much.
4970 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4972 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, CCCode);
4973 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4974 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4976 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode);
4977 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4978 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
4987 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
4988 if (RHSCST->isAllOnesValue()) {
4989 // Comparison to -1.
4990 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
4995 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
4996 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
4997 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4998 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
5001 // If this is a comparison of the sign bit, just look at the top part.
5003 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
5004 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
5005 CST->isNullValue()) || // X < 0
5006 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
5007 CST->isAllOnesValue())) { // X > -1
5013 // FIXME: This generated code sucks.
5014 ISD::CondCode LowCC;
5016 default: assert(0 && "Unknown integer setcc!");
5018 case ISD::SETULT: LowCC = ISD::SETULT; break;
5020 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
5022 case ISD::SETULE: LowCC = ISD::SETULE; break;
5024 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
5027 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
5028 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
5029 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
5031 // NOTE: on targets without efficient SELECT of bools, we can always use
5032 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
5033 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
5034 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo,
5035 LowCC, false, DagCombineInfo);
5036 if (!Tmp1.getNode())
5037 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC);
5038 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
5039 CCCode, false, DagCombineInfo);
5040 if (!Tmp2.getNode())
5041 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi,
5044 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
5045 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
5046 if ((Tmp1C && Tmp1C->isNullValue()) ||
5047 (Tmp2C && Tmp2C->isNullValue() &&
5048 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
5049 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
5050 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
5051 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
5052 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
5053 // low part is known false, returns high part.
5054 // For LE / GE, if high part is known false, ignore the low part.
5055 // For LT / GT, if high part is known true, ignore the low part.
5059 Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
5060 ISD::SETEQ, false, DagCombineInfo);
5061 if (!Result.getNode())
5062 Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
5064 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
5065 Result, Tmp1, Tmp2));
5076 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
5077 /// condition code CC on the current target. This routine assumes LHS and rHS
5078 /// have already been legalized by LegalizeSetCCOperands. It expands SETCC with
5079 /// illegal condition code into AND / OR of multiple SETCC values.
5080 void SelectionDAGLegalize::LegalizeSetCCCondCode(MVT VT,
5081 SDValue &LHS, SDValue &RHS,
5083 MVT OpVT = LHS.getValueType();
5084 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
5085 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
5086 default: assert(0 && "Unknown condition code action!");
5087 case TargetLowering::Legal:
5090 case TargetLowering::Expand: {
5091 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
5094 default: assert(0 && "Don't know how to expand this condition!"); abort();
5095 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break;
5096 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break;
5097 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5098 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break;
5099 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5100 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5101 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5102 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5103 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5104 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5105 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5106 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5107 // FIXME: Implement more expansions.
5110 SDValue SetCC1 = DAG.getSetCC(VT, LHS, RHS, CC1);
5111 SDValue SetCC2 = DAG.getSetCC(VT, LHS, RHS, CC2);
5112 LHS = DAG.getNode(Opc, VT, SetCC1, SetCC2);
5120 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
5121 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
5122 /// a load from the stack slot to DestVT, extending it if needed.
5123 /// The resultant code need not be legal.
5124 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
5127 // Create the stack frame object.
5128 unsigned SrcAlign = TLI.getTargetData()->getPrefTypeAlignment(
5129 SrcOp.getValueType().getTypeForMVT());
5130 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
5132 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
5133 int SPFI = StackPtrFI->getIndex();
5135 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
5136 unsigned SlotSize = SlotVT.getSizeInBits();
5137 unsigned DestSize = DestVT.getSizeInBits();
5138 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(
5139 DestVT.getTypeForMVT());
5141 // Emit a store to the stack slot. Use a truncstore if the input value is
5142 // later than DestVT.
5145 if (SrcSize > SlotSize)
5146 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr,
5147 PseudoSourceValue::getFixedStack(SPFI), 0,
5148 SlotVT, false, SrcAlign);
5150 assert(SrcSize == SlotSize && "Invalid store");
5151 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr,
5152 PseudoSourceValue::getFixedStack(SPFI), 0,
5156 // Result is a load from the stack slot.
5157 if (SlotSize == DestSize)
5158 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0, false, DestAlign);
5160 assert(SlotSize < DestSize && "Unknown extension!");
5161 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT,
5165 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
5166 // Create a vector sized/aligned stack slot, store the value to element #0,
5167 // then load the whole vector back out.
5168 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
5170 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
5171 int SPFI = StackPtrFI->getIndex();
5173 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
5174 PseudoSourceValue::getFixedStack(SPFI), 0);
5175 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,
5176 PseudoSourceValue::getFixedStack(SPFI), 0);
5180 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
5181 /// support the operation, but do support the resultant vector type.
5182 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
5184 // If the only non-undef value is the low element, turn this into a
5185 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
5186 unsigned NumElems = Node->getNumOperands();
5187 bool isOnlyLowElement = true;
5188 SDValue SplatValue = Node->getOperand(0);
5190 // FIXME: it would be far nicer to change this into map<SDValue,uint64_t>
5191 // and use a bitmask instead of a list of elements.
5192 std::map<SDValue, std::vector<unsigned> > Values;
5193 Values[SplatValue].push_back(0);
5194 bool isConstant = true;
5195 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
5196 SplatValue.getOpcode() != ISD::UNDEF)
5199 for (unsigned i = 1; i < NumElems; ++i) {
5200 SDValue V = Node->getOperand(i);
5201 Values[V].push_back(i);
5202 if (V.getOpcode() != ISD::UNDEF)
5203 isOnlyLowElement = false;
5204 if (SplatValue != V)
5205 SplatValue = SDValue(0,0);
5207 // If this isn't a constant element or an undef, we can't use a constant
5209 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
5210 V.getOpcode() != ISD::UNDEF)
5214 if (isOnlyLowElement) {
5215 // If the low element is an undef too, then this whole things is an undef.
5216 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
5217 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
5218 // Otherwise, turn this into a scalar_to_vector node.
5219 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
5220 Node->getOperand(0));
5223 // If all elements are constants, create a load from the constant pool.
5225 MVT VT = Node->getValueType(0);
5226 std::vector<Constant*> CV;
5227 for (unsigned i = 0, e = NumElems; i != e; ++i) {
5228 if (ConstantFPSDNode *V =
5229 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
5230 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
5231 } else if (ConstantSDNode *V =
5232 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
5233 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
5235 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
5237 Node->getOperand(0).getValueType().getTypeForMVT();
5238 CV.push_back(UndefValue::get(OpNTy));
5241 Constant *CP = ConstantVector::get(CV);
5242 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
5243 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5244 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
5245 PseudoSourceValue::getConstantPool(), 0,
5249 if (SplatValue.getNode()) { // Splat of one value?
5250 // Build the shuffle constant vector: <0, 0, 0, 0>
5251 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
5252 SDValue Zero = DAG.getConstant(0, MaskVT.getVectorElementType());
5253 std::vector<SDValue> ZeroVec(NumElems, Zero);
5254 SDValue SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
5255 &ZeroVec[0], ZeroVec.size());
5257 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
5258 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
5259 // Get the splatted value into the low element of a vector register.
5261 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
5263 // Return shuffle(LowValVec, undef, <0,0,0,0>)
5264 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
5265 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
5270 // If there are only two unique elements, we may be able to turn this into a
5272 if (Values.size() == 2) {
5273 // Get the two values in deterministic order.
5274 SDValue Val1 = Node->getOperand(1);
5276 std::map<SDValue, std::vector<unsigned> >::iterator MI = Values.begin();
5277 if (MI->first != Val1)
5280 Val2 = (++MI)->first;
5282 // If Val1 is an undef, make sure end ends up as Val2, to ensure that our
5283 // vector shuffle has the undef vector on the RHS.
5284 if (Val1.getOpcode() == ISD::UNDEF)
5285 std::swap(Val1, Val2);
5287 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
5288 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
5289 MVT MaskEltVT = MaskVT.getVectorElementType();
5290 std::vector<SDValue> MaskVec(NumElems);
5292 // Set elements of the shuffle mask for Val1.
5293 std::vector<unsigned> &Val1Elts = Values[Val1];
5294 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i)
5295 MaskVec[Val1Elts[i]] = DAG.getConstant(0, MaskEltVT);
5297 // Set elements of the shuffle mask for Val2.
5298 std::vector<unsigned> &Val2Elts = Values[Val2];
5299 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i)
5300 if (Val2.getOpcode() != ISD::UNDEF)
5301 MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT);
5303 MaskVec[Val2Elts[i]] = DAG.getNode(ISD::UNDEF, MaskEltVT);
5305 SDValue ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
5306 &MaskVec[0], MaskVec.size());
5308 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it.
5309 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
5310 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
5311 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val1);
5312 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val2);
5313 SDValue Ops[] = { Val1, Val2, ShuffleMask };
5315 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
5316 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops, 3);
5320 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
5321 // aligned object on the stack, store each element into it, then load
5322 // the result as a vector.
5323 MVT VT = Node->getValueType(0);
5324 // Create the stack frame object.
5325 SDValue FIPtr = DAG.CreateStackTemporary(VT);
5327 // Emit a store of each element to the stack slot.
5328 SmallVector<SDValue, 8> Stores;
5329 unsigned TypeByteSize = Node->getOperand(0).getValueType().getSizeInBits()/8;
5330 // Store (in the right endianness) the elements to memory.
5331 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5332 // Ignore undef elements.
5333 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
5335 unsigned Offset = TypeByteSize*i;
5337 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
5338 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
5340 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
5345 if (!Stores.empty()) // Not all undef elements?
5346 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
5347 &Stores[0], Stores.size());
5349 StoreChain = DAG.getEntryNode();
5351 // Result is a load from the stack slot.
5352 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
5355 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
5356 SDValue Op, SDValue Amt,
5357 SDValue &Lo, SDValue &Hi) {
5358 // Expand the subcomponents.
5360 ExpandOp(Op, LHSL, LHSH);
5362 SDValue Ops[] = { LHSL, LHSH, Amt };
5363 MVT VT = LHSL.getValueType();
5364 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
5365 Hi = Lo.getValue(1);
5369 /// ExpandShift - Try to find a clever way to expand this shift operation out to
5370 /// smaller elements. If we can't find a way that is more efficient than a
5371 /// libcall on this target, return false. Otherwise, return true with the
5372 /// low-parts expanded into Lo and Hi.
5373 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op,SDValue Amt,
5374 SDValue &Lo, SDValue &Hi) {
5375 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
5376 "This is not a shift!");
5378 MVT NVT = TLI.getTypeToTransformTo(Op.getValueType());
5379 SDValue ShAmt = LegalizeOp(Amt);
5380 MVT ShTy = ShAmt.getValueType();
5381 unsigned ShBits = ShTy.getSizeInBits();
5382 unsigned VTBits = Op.getValueType().getSizeInBits();
5383 unsigned NVTBits = NVT.getSizeInBits();
5385 // Handle the case when Amt is an immediate.
5386 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.getNode())) {
5387 unsigned Cst = CN->getZExtValue();
5388 // Expand the incoming operand to be shifted, so that we have its parts
5390 ExpandOp(Op, InL, InH);
5394 Lo = DAG.getConstant(0, NVT);
5395 Hi = DAG.getConstant(0, NVT);
5396 } else if (Cst > NVTBits) {
5397 Lo = DAG.getConstant(0, NVT);
5398 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
5399 } else if (Cst == NVTBits) {
5400 Lo = DAG.getConstant(0, NVT);
5403 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
5404 Hi = DAG.getNode(ISD::OR, NVT,
5405 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
5406 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
5411 Lo = DAG.getConstant(0, NVT);
5412 Hi = DAG.getConstant(0, NVT);
5413 } else if (Cst > NVTBits) {
5414 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
5415 Hi = DAG.getConstant(0, NVT);
5416 } else if (Cst == NVTBits) {
5418 Hi = DAG.getConstant(0, NVT);
5420 Lo = DAG.getNode(ISD::OR, NVT,
5421 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5422 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5423 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
5428 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
5429 DAG.getConstant(NVTBits-1, ShTy));
5430 } else if (Cst > NVTBits) {
5431 Lo = DAG.getNode(ISD::SRA, NVT, InH,
5432 DAG.getConstant(Cst-NVTBits, ShTy));
5433 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5434 DAG.getConstant(NVTBits-1, ShTy));
5435 } else if (Cst == NVTBits) {
5437 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5438 DAG.getConstant(NVTBits-1, ShTy));
5440 Lo = DAG.getNode(ISD::OR, NVT,
5441 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5442 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5443 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
5449 // Okay, the shift amount isn't constant. However, if we can tell that it is
5450 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
5451 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
5452 APInt KnownZero, KnownOne;
5453 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
5455 // If we know that if any of the high bits of the shift amount are one, then
5456 // we can do this as a couple of simple shifts.
5457 if (KnownOne.intersects(Mask)) {
5458 // Mask out the high bit, which we know is set.
5459 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
5460 DAG.getConstant(~Mask, Amt.getValueType()));
5462 // Expand the incoming operand to be shifted, so that we have its parts
5464 ExpandOp(Op, InL, InH);
5467 Lo = DAG.getConstant(0, NVT); // Low part is zero.
5468 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
5471 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
5472 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
5475 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
5476 DAG.getConstant(NVTBits-1, Amt.getValueType()));
5477 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
5482 // If we know that the high bits of the shift amount are all zero, then we can
5483 // do this as a couple of simple shifts.
5484 if ((KnownZero & Mask) == Mask) {
5486 SDValue Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
5487 DAG.getConstant(NVTBits, Amt.getValueType()),
5490 // Expand the incoming operand to be shifted, so that we have its parts
5492 ExpandOp(Op, InL, InH);
5495 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
5496 Hi = DAG.getNode(ISD::OR, NVT,
5497 DAG.getNode(ISD::SHL, NVT, InH, Amt),
5498 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
5501 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
5502 Lo = DAG.getNode(ISD::OR, NVT,
5503 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5504 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5507 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
5508 Lo = DAG.getNode(ISD::OR, NVT,
5509 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5510 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5519 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
5520 // does not fit into a register, return the lo part and set the hi part to the
5521 // by-reg argument. If it does fit into a single register, return the result
5522 // and leave the Hi part unset.
5523 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
5524 bool isSigned, SDValue &Hi) {
5525 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
5526 // The input chain to this libcall is the entry node of the function.
5527 // Legalizing the call will automatically add the previous call to the
5529 SDValue InChain = DAG.getEntryNode();
5531 TargetLowering::ArgListTy Args;
5532 TargetLowering::ArgListEntry Entry;
5533 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5534 MVT ArgVT = Node->getOperand(i).getValueType();
5535 const Type *ArgTy = ArgVT.getTypeForMVT();
5536 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
5537 Entry.isSExt = isSigned;
5538 Entry.isZExt = !isSigned;
5539 Args.push_back(Entry);
5541 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
5542 TLI.getPointerTy());
5544 // Splice the libcall in wherever FindInputOutputChains tells us to.
5545 const Type *RetTy = Node->getValueType(0).getTypeForMVT();
5546 std::pair<SDValue,SDValue> CallInfo =
5547 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
5548 CallingConv::C, false, Callee, Args, DAG);
5550 // Legalize the call sequence, starting with the chain. This will advance
5551 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
5552 // was added by LowerCallTo (guaranteeing proper serialization of calls).
5553 LegalizeOp(CallInfo.second);
5555 switch (getTypeAction(CallInfo.first.getValueType())) {
5556 default: assert(0 && "Unknown thing");
5558 Result = CallInfo.first;
5561 ExpandOp(CallInfo.first, Result, Hi);
5567 /// LegalizeINT_TO_FP - Legalize a [US]INT_TO_FP operation.
5569 SDValue SelectionDAGLegalize::
5570 LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op) {
5571 bool isCustom = false;
5573 switch (getTypeAction(Op.getValueType())) {
5575 switch (TLI.getOperationAction(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5576 Op.getValueType())) {
5577 default: assert(0 && "Unknown operation action!");
5578 case TargetLowering::Custom:
5581 case TargetLowering::Legal:
5582 Tmp1 = LegalizeOp(Op);
5583 if (Result.getNode())
5584 Result = DAG.UpdateNodeOperands(Result, Tmp1);
5586 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5589 Tmp1 = TLI.LowerOperation(Result, DAG);
5590 if (Tmp1.getNode()) Result = Tmp1;
5593 case TargetLowering::Expand:
5594 Result = ExpandLegalINT_TO_FP(isSigned, LegalizeOp(Op), DestTy);
5596 case TargetLowering::Promote:
5597 Result = PromoteLegalINT_TO_FP(LegalizeOp(Op), DestTy, isSigned);
5602 Result = ExpandIntToFP(isSigned, DestTy, Op);
5605 Tmp1 = PromoteOp(Op);
5607 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
5608 Tmp1, DAG.getValueType(Op.getValueType()));
5610 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
5613 if (Result.getNode())
5614 Result = DAG.UpdateNodeOperands(Result, Tmp1);
5616 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5618 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
5624 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
5626 SDValue SelectionDAGLegalize::
5627 ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source) {
5628 MVT SourceVT = Source.getValueType();
5629 bool ExpandSource = getTypeAction(SourceVT) == Expand;
5631 // Expand unsupported int-to-fp vector casts by unrolling them.
5632 if (DestTy.isVector()) {
5634 return LegalizeOp(UnrollVectorOp(Source));
5635 MVT DestEltTy = DestTy.getVectorElementType();
5636 if (DestTy.getVectorNumElements() == 1) {
5637 SDValue Scalar = ScalarizeVectorOp(Source);
5638 SDValue Result = LegalizeINT_TO_FP(SDValue(), isSigned,
5640 return DAG.getNode(ISD::BUILD_VECTOR, DestTy, Result);
5643 SplitVectorOp(Source, Lo, Hi);
5644 MVT SplitDestTy = MVT::getVectorVT(DestEltTy,
5645 DestTy.getVectorNumElements() / 2);
5646 SDValue LoResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, Lo);
5647 SDValue HiResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, Hi);
5648 return LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, DestTy, LoResult,
5652 // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc.
5653 if (!isSigned && SourceVT != MVT::i32) {
5654 // The integer value loaded will be incorrectly if the 'sign bit' of the
5655 // incoming integer is set. To handle this, we dynamically test to see if
5656 // it is set, and, if so, add a fudge factor.
5660 ExpandOp(Source, Lo, Hi);
5661 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi);
5663 // The comparison for the sign bit will use the entire operand.
5667 // Check to see if the target has a custom way to lower this. If so, use
5668 // it. (Note we've already expanded the operand in this case.)
5669 switch (TLI.getOperationAction(ISD::UINT_TO_FP, SourceVT)) {
5670 default: assert(0 && "This action not implemented for this operation!");
5671 case TargetLowering::Legal:
5672 case TargetLowering::Expand:
5673 break; // This case is handled below.
5674 case TargetLowering::Custom: {
5675 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::UINT_TO_FP, DestTy,
5678 return LegalizeOp(NV);
5679 break; // The target decided this was legal after all
5683 // If this is unsigned, and not supported, first perform the conversion to
5684 // signed, then adjust the result if the sign bit is set.
5685 SDValue SignedConv = ExpandIntToFP(true, DestTy, Source);
5687 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
5688 DAG.getConstant(0, Hi.getValueType()),
5690 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5691 SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5692 SignSet, Four, Zero);
5693 uint64_t FF = 0x5f800000ULL;
5694 if (TLI.isLittleEndian()) FF <<= 32;
5695 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5697 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5698 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5699 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5700 Alignment = std::min(Alignment, 4u);
5702 if (DestTy == MVT::f32)
5703 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5704 PseudoSourceValue::getConstantPool(), 0,
5706 else if (DestTy.bitsGT(MVT::f32))
5707 // FIXME: Avoid the extend by construction the right constantpool?
5708 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
5710 PseudoSourceValue::getConstantPool(), 0,
5711 MVT::f32, false, Alignment);
5713 assert(0 && "Unexpected conversion");
5715 MVT SCVT = SignedConv.getValueType();
5716 if (SCVT != DestTy) {
5717 // Destination type needs to be expanded as well. The FADD now we are
5718 // constructing will be expanded into a libcall.
5719 if (SCVT.getSizeInBits() != DestTy.getSizeInBits()) {
5720 assert(SCVT.getSizeInBits() * 2 == DestTy.getSizeInBits());
5721 SignedConv = DAG.getNode(ISD::BUILD_PAIR, DestTy,
5722 SignedConv, SignedConv.getValue(1));
5724 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
5726 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
5729 // Check to see if the target has a custom way to lower this. If so, use it.
5730 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) {
5731 default: assert(0 && "This action not implemented for this operation!");
5732 case TargetLowering::Legal:
5733 case TargetLowering::Expand:
5734 break; // This case is handled below.
5735 case TargetLowering::Custom: {
5736 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
5739 return LegalizeOp(NV);
5740 break; // The target decided this was legal after all
5744 // Expand the source, then glue it back together for the call. We must expand
5745 // the source in case it is shared (this pass of legalize must traverse it).
5747 SDValue SrcLo, SrcHi;
5748 ExpandOp(Source, SrcLo, SrcHi);
5749 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, SrcLo, SrcHi);
5752 RTLIB::Libcall LC = isSigned ?
5753 RTLIB::getSINTTOFP(SourceVT, DestTy) :
5754 RTLIB::getUINTTOFP(SourceVT, DestTy);
5755 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unknown int value type");
5757 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
5759 SDValue Result = ExpandLibCall(LC, Source.getNode(), isSigned, HiPart);
5760 if (Result.getValueType() != DestTy && HiPart.getNode())
5761 Result = DAG.getNode(ISD::BUILD_PAIR, DestTy, Result, HiPart);
5765 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
5766 /// INT_TO_FP operation of the specified operand when the target requests that
5767 /// we expand it. At this point, we know that the result and operand types are
5768 /// legal for the target.
5769 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
5772 if (Op0.getValueType() == MVT::i32) {
5773 // simple 32-bit [signed|unsigned] integer to float/double expansion
5775 // Get the stack frame index of a 8 byte buffer.
5776 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
5778 // word offset constant for Hi/Lo address computation
5779 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
5780 // set up Hi and Lo (into buffer) address based on endian
5781 SDValue Hi = StackSlot;
5782 SDValue Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
5783 if (TLI.isLittleEndian())
5786 // if signed map to unsigned space
5789 // constant used to invert sign bit (signed to unsigned mapping)
5790 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
5791 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
5795 // store the lo of the constructed double - based on integer input
5796 SDValue Store1 = DAG.getStore(DAG.getEntryNode(),
5797 Op0Mapped, Lo, NULL, 0);
5798 // initial hi portion of constructed double
5799 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
5800 // store the hi of the constructed double - biased exponent
5801 SDValue Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
5802 // load the constructed double
5803 SDValue Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
5804 // FP constant to bias correct the final result
5805 SDValue Bias = DAG.getConstantFP(isSigned ?
5806 BitsToDouble(0x4330000080000000ULL)
5807 : BitsToDouble(0x4330000000000000ULL),
5809 // subtract the bias
5810 SDValue Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
5813 // handle final rounding
5814 if (DestVT == MVT::f64) {
5817 } else if (DestVT.bitsLT(MVT::f64)) {
5818 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub,
5819 DAG.getIntPtrConstant(0));
5820 } else if (DestVT.bitsGT(MVT::f64)) {
5821 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
5825 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
5826 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
5828 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Op0), Op0,
5829 DAG.getConstant(0, Op0.getValueType()),
5831 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5832 SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5833 SignSet, Four, Zero);
5835 // If the sign bit of the integer is set, the large number will be treated
5836 // as a negative number. To counteract this, the dynamic code adds an
5837 // offset depending on the data type.
5839 switch (Op0.getValueType().getSimpleVT()) {
5840 default: assert(0 && "Unsupported integer type!");
5841 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
5842 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
5843 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
5844 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
5846 if (TLI.isLittleEndian()) FF <<= 32;
5847 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5849 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5850 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5851 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5852 Alignment = std::min(Alignment, 4u);
5854 if (DestVT == MVT::f32)
5855 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5856 PseudoSourceValue::getConstantPool(), 0,
5860 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT,
5861 DAG.getEntryNode(), CPIdx,
5862 PseudoSourceValue::getConstantPool(), 0,
5863 MVT::f32, false, Alignment));
5866 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
5869 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
5870 /// *INT_TO_FP operation of the specified operand when the target requests that
5871 /// we promote it. At this point, we know that the result and operand types are
5872 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
5873 /// operation that takes a larger input.
5874 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
5877 // First step, figure out the appropriate *INT_TO_FP operation to use.
5878 MVT NewInTy = LegalOp.getValueType();
5880 unsigned OpToUse = 0;
5882 // Scan for the appropriate larger type to use.
5884 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
5885 assert(NewInTy.isInteger() && "Ran out of possibilities!");
5887 // If the target supports SINT_TO_FP of this type, use it.
5888 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
5890 case TargetLowering::Legal:
5891 if (!TLI.isTypeLegal(NewInTy))
5892 break; // Can't use this datatype.
5894 case TargetLowering::Custom:
5895 OpToUse = ISD::SINT_TO_FP;
5899 if (isSigned) continue;
5901 // If the target supports UINT_TO_FP of this type, use it.
5902 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
5904 case TargetLowering::Legal:
5905 if (!TLI.isTypeLegal(NewInTy))
5906 break; // Can't use this datatype.
5908 case TargetLowering::Custom:
5909 OpToUse = ISD::UINT_TO_FP;
5914 // Otherwise, try a larger type.
5917 // Okay, we found the operation and type to use. Zero extend our input to the
5918 // desired type then run the operation on it.
5919 return DAG.getNode(OpToUse, DestVT,
5920 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
5924 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
5925 /// FP_TO_*INT operation of the specified operand when the target requests that
5926 /// we promote it. At this point, we know that the result and operand types are
5927 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
5928 /// operation that returns a larger result.
5929 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
5932 // First step, figure out the appropriate FP_TO*INT operation to use.
5933 MVT NewOutTy = DestVT;
5935 unsigned OpToUse = 0;
5937 // Scan for the appropriate larger type to use.
5939 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1);
5940 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
5942 // If the target supports FP_TO_SINT returning this type, use it.
5943 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
5945 case TargetLowering::Legal:
5946 if (!TLI.isTypeLegal(NewOutTy))
5947 break; // Can't use this datatype.
5949 case TargetLowering::Custom:
5950 OpToUse = ISD::FP_TO_SINT;
5955 // If the target supports FP_TO_UINT of this type, use it.
5956 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
5958 case TargetLowering::Legal:
5959 if (!TLI.isTypeLegal(NewOutTy))
5960 break; // Can't use this datatype.
5962 case TargetLowering::Custom:
5963 OpToUse = ISD::FP_TO_UINT;
5968 // Otherwise, try a larger type.
5972 // Okay, we found the operation and type to use.
5973 SDValue Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp);
5975 // If the operation produces an invalid type, it must be custom lowered. Use
5976 // the target lowering hooks to expand it. Just keep the low part of the
5977 // expanded operation, we know that we're truncating anyway.
5978 if (getTypeAction(NewOutTy) == Expand) {
5979 Operation = SDValue(TLI.ReplaceNodeResults(Operation.getNode(), DAG), 0);
5980 assert(Operation.getNode() && "Didn't return anything");
5983 // Truncate the result of the extended FP_TO_*INT operation to the desired
5985 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation);
5988 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
5990 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op) {
5991 MVT VT = Op.getValueType();
5992 MVT SHVT = TLI.getShiftAmountTy();
5993 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
5994 switch (VT.getSimpleVT()) {
5995 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
5997 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5998 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5999 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
6001 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
6002 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
6003 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
6004 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
6005 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
6006 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
6007 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
6008 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
6009 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
6011 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
6012 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
6013 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
6014 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
6015 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
6016 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
6017 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
6018 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
6019 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
6020 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
6021 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
6022 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
6023 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
6024 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
6025 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
6026 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
6027 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
6028 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
6029 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
6030 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
6031 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
6035 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
6037 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op) {
6039 default: assert(0 && "Cannot expand this yet!");
6041 static const uint64_t mask[6] = {
6042 0x5555555555555555ULL, 0x3333333333333333ULL,
6043 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
6044 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
6046 MVT VT = Op.getValueType();
6047 MVT ShVT = TLI.getShiftAmountTy();
6048 unsigned len = VT.getSizeInBits();
6049 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
6050 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
6051 SDValue Tmp2 = DAG.getConstant(mask[i], VT);
6052 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
6053 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
6054 DAG.getNode(ISD::AND, VT,
6055 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
6060 // for now, we do this:
6061 // x = x | (x >> 1);
6062 // x = x | (x >> 2);
6064 // x = x | (x >>16);
6065 // x = x | (x >>32); // for 64-bit input
6066 // return popcount(~x);
6068 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
6069 MVT VT = Op.getValueType();
6070 MVT ShVT = TLI.getShiftAmountTy();
6071 unsigned len = VT.getSizeInBits();
6072 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
6073 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
6074 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
6076 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
6077 return DAG.getNode(ISD::CTPOP, VT, Op);
6080 // for now, we use: { return popcount(~x & (x - 1)); }
6081 // unless the target has ctlz but not ctpop, in which case we use:
6082 // { return 32 - nlz(~x & (x-1)); }
6083 // see also http://www.hackersdelight.org/HDcode/ntz.cc
6084 MVT VT = Op.getValueType();
6085 SDValue Tmp2 = DAG.getConstant(~0ULL, VT);
6086 SDValue Tmp3 = DAG.getNode(ISD::AND, VT,
6087 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
6088 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
6089 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
6090 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
6091 TLI.isOperationLegal(ISD::CTLZ, VT))
6092 return DAG.getNode(ISD::SUB, VT,
6093 DAG.getConstant(VT.getSizeInBits(), VT),
6094 DAG.getNode(ISD::CTLZ, VT, Tmp3));
6095 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
6100 /// ExpandOp - Expand the specified SDValue into its two component pieces
6101 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
6102 /// LegalizedNodes map is filled in for any results that are not expanded, the
6103 /// ExpandedNodes map is filled in for any results that are expanded, and the
6104 /// Lo/Hi values are returned.
6105 void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
6106 MVT VT = Op.getValueType();
6107 MVT NVT = TLI.getTypeToTransformTo(VT);
6108 SDNode *Node = Op.getNode();
6109 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
6110 assert(((NVT.isInteger() && NVT.bitsLT(VT)) || VT.isFloatingPoint() ||
6111 VT.isVector()) && "Cannot expand to FP value or to larger int value!");
6113 // See if we already expanded it.
6114 DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator I
6115 = ExpandedNodes.find(Op);
6116 if (I != ExpandedNodes.end()) {
6117 Lo = I->second.first;
6118 Hi = I->second.second;
6122 switch (Node->getOpcode()) {
6123 case ISD::CopyFromReg:
6124 assert(0 && "CopyFromReg must be legal!");
6125 case ISD::FP_ROUND_INREG:
6126 if (VT == MVT::ppcf128 &&
6127 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
6128 TargetLowering::Custom) {
6129 SDValue SrcLo, SrcHi, Src;
6130 ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
6131 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi);
6132 SDValue Result = TLI.LowerOperation(
6133 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG);
6134 assert(Result.getNode()->getOpcode() == ISD::BUILD_PAIR);
6135 Lo = Result.getNode()->getOperand(0);
6136 Hi = Result.getNode()->getOperand(1);
6142 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
6144 assert(0 && "Do not know how to expand this operator!");
6146 case ISD::EXTRACT_ELEMENT:
6147 ExpandOp(Node->getOperand(0), Lo, Hi);
6148 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
6149 return ExpandOp(Hi, Lo, Hi);
6150 return ExpandOp(Lo, Lo, Hi);
6151 case ISD::EXTRACT_VECTOR_ELT:
6152 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types.
6153 Lo = ExpandEXTRACT_VECTOR_ELT(Op);
6154 return ExpandOp(Lo, Lo, Hi);
6156 Lo = DAG.getNode(ISD::UNDEF, NVT);
6157 Hi = DAG.getNode(ISD::UNDEF, NVT);
6159 case ISD::Constant: {
6160 unsigned NVTBits = NVT.getSizeInBits();
6161 const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue();
6162 Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT);
6163 Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT);
6166 case ISD::ConstantFP: {
6167 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
6168 if (CFP->getValueType(0) == MVT::ppcf128) {
6169 APInt api = CFP->getValueAPF().bitcastToAPInt();
6170 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
6172 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
6176 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
6177 if (getTypeAction(Lo.getValueType()) == Expand)
6178 ExpandOp(Lo, Lo, Hi);
6181 case ISD::BUILD_PAIR:
6182 // Return the operands.
6183 Lo = Node->getOperand(0);
6184 Hi = Node->getOperand(1);
6187 case ISD::MERGE_VALUES:
6188 if (Node->getNumValues() == 1) {
6189 ExpandOp(Op.getOperand(0), Lo, Hi);
6192 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y)
6193 assert(Op.getResNo() == 0 && Node->getNumValues() == 2 &&
6194 Op.getValue(1).getValueType() == MVT::Other &&
6195 "unhandled MERGE_VALUES");
6196 ExpandOp(Op.getOperand(0), Lo, Hi);
6197 // Remember that we legalized the chain.
6198 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1)));
6201 case ISD::SIGN_EXTEND_INREG:
6202 ExpandOp(Node->getOperand(0), Lo, Hi);
6203 // sext_inreg the low part if needed.
6204 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
6206 // The high part gets the sign extension from the lo-part. This handles
6207 // things like sextinreg V:i64 from i8.
6208 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6209 DAG.getConstant(NVT.getSizeInBits()-1,
6210 TLI.getShiftAmountTy()));
6214 ExpandOp(Node->getOperand(0), Lo, Hi);
6215 SDValue TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
6216 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
6222 ExpandOp(Node->getOperand(0), Lo, Hi);
6223 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
6224 DAG.getNode(ISD::CTPOP, NVT, Lo),
6225 DAG.getNode(ISD::CTPOP, NVT, Hi));
6226 Hi = DAG.getConstant(0, NVT);
6230 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
6231 ExpandOp(Node->getOperand(0), Lo, Hi);
6232 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
6233 SDValue HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
6234 SDValue TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(HLZ), HLZ, BitsC,
6236 SDValue LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
6237 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
6239 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
6240 Hi = DAG.getConstant(0, NVT);
6245 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
6246 ExpandOp(Node->getOperand(0), Lo, Hi);
6247 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
6248 SDValue LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
6249 SDValue BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(LTZ), LTZ, BitsC,
6251 SDValue HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
6252 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
6254 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
6255 Hi = DAG.getConstant(0, NVT);
6260 SDValue Ch = Node->getOperand(0); // Legalize the chain.
6261 SDValue Ptr = Node->getOperand(1); // Legalize the pointer.
6262 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
6263 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
6265 // Remember that we legalized the chain.
6266 Hi = LegalizeOp(Hi);
6267 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
6268 if (TLI.isBigEndian())
6274 LoadSDNode *LD = cast<LoadSDNode>(Node);
6275 SDValue Ch = LD->getChain(); // Legalize the chain.
6276 SDValue Ptr = LD->getBasePtr(); // Legalize the pointer.
6277 ISD::LoadExtType ExtType = LD->getExtensionType();
6278 const Value *SV = LD->getSrcValue();
6279 int SVOffset = LD->getSrcValueOffset();
6280 unsigned Alignment = LD->getAlignment();
6281 bool isVolatile = LD->isVolatile();
6283 if (ExtType == ISD::NON_EXTLOAD) {
6284 Lo = DAG.getLoad(NVT, Ch, Ptr, SV, SVOffset,
6285 isVolatile, Alignment);
6286 if (VT == MVT::f32 || VT == MVT::f64) {
6287 // f32->i32 or f64->i64 one to one expansion.
6288 // Remember that we legalized the chain.
6289 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
6290 // Recursively expand the new load.
6291 if (getTypeAction(NVT) == Expand)
6292 ExpandOp(Lo, Lo, Hi);
6296 // Increment the pointer to the other half.
6297 unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8;
6298 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
6299 DAG.getIntPtrConstant(IncrementSize));
6300 SVOffset += IncrementSize;
6301 Alignment = MinAlign(Alignment, IncrementSize);
6302 Hi = DAG.getLoad(NVT, Ch, Ptr, SV, SVOffset,
6303 isVolatile, Alignment);
6305 // Build a factor node to remember that this load is independent of the
6307 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
6310 // Remember that we legalized the chain.
6311 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
6312 if (TLI.isBigEndian())
6315 MVT EVT = LD->getMemoryVT();
6317 if ((VT == MVT::f64 && EVT == MVT::f32) ||
6318 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
6319 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
6320 SDValue Load = DAG.getLoad(EVT, Ch, Ptr, SV,
6321 SVOffset, isVolatile, Alignment);
6322 // Remember that we legalized the chain.
6323 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Load.getValue(1)));
6324 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
6329 Lo = DAG.getLoad(NVT, Ch, Ptr, SV,
6330 SVOffset, isVolatile, Alignment);
6332 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, SV,
6333 SVOffset, EVT, isVolatile,
6336 // Remember that we legalized the chain.
6337 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
6339 if (ExtType == ISD::SEXTLOAD) {
6340 // The high part is obtained by SRA'ing all but one of the bits of the
6342 unsigned LoSize = Lo.getValueType().getSizeInBits();
6343 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6344 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6345 } else if (ExtType == ISD::ZEXTLOAD) {
6346 // The high part is just a zero.
6347 Hi = DAG.getConstant(0, NVT);
6348 } else /* if (ExtType == ISD::EXTLOAD) */ {
6349 // The high part is undefined.
6350 Hi = DAG.getNode(ISD::UNDEF, NVT);
6357 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
6358 SDValue LL, LH, RL, RH;
6359 ExpandOp(Node->getOperand(0), LL, LH);
6360 ExpandOp(Node->getOperand(1), RL, RH);
6361 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
6362 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
6366 SDValue LL, LH, RL, RH;
6367 ExpandOp(Node->getOperand(1), LL, LH);
6368 ExpandOp(Node->getOperand(2), RL, RH);
6369 if (getTypeAction(NVT) == Expand)
6370 NVT = TLI.getTypeToExpandTo(NVT);
6371 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
6373 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
6376 case ISD::SELECT_CC: {
6377 SDValue TL, TH, FL, FH;
6378 ExpandOp(Node->getOperand(2), TL, TH);
6379 ExpandOp(Node->getOperand(3), FL, FH);
6380 if (getTypeAction(NVT) == Expand)
6381 NVT = TLI.getTypeToExpandTo(NVT);
6382 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
6383 Node->getOperand(1), TL, FL, Node->getOperand(4));
6385 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
6386 Node->getOperand(1), TH, FH, Node->getOperand(4));
6389 case ISD::ANY_EXTEND:
6390 // The low part is any extension of the input (which degenerates to a copy).
6391 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
6392 // The high part is undefined.
6393 Hi = DAG.getNode(ISD::UNDEF, NVT);
6395 case ISD::SIGN_EXTEND: {
6396 // The low part is just a sign extension of the input (which degenerates to
6398 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
6400 // The high part is obtained by SRA'ing all but one of the bits of the lo
6402 unsigned LoSize = Lo.getValueType().getSizeInBits();
6403 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6404 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6407 case ISD::ZERO_EXTEND:
6408 // The low part is just a zero extension of the input (which degenerates to
6410 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
6412 // The high part is just a zero.
6413 Hi = DAG.getConstant(0, NVT);
6416 case ISD::TRUNCATE: {
6417 // The input value must be larger than this value. Expand *it*.
6419 ExpandOp(Node->getOperand(0), NewLo, Hi);
6421 // The low part is now either the right size, or it is closer. If not the
6422 // right size, make an illegal truncate so we recursively expand it.
6423 if (NewLo.getValueType() != Node->getValueType(0))
6424 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
6425 ExpandOp(NewLo, Lo, Hi);
6429 case ISD::BIT_CONVERT: {
6431 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
6432 // If the target wants to, allow it to lower this itself.
6433 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6434 case Expand: assert(0 && "cannot expand FP!");
6435 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
6436 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
6438 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
6441 // f32 / f64 must be expanded to i32 / i64.
6442 if (VT == MVT::f32 || VT == MVT::f64) {
6443 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6444 if (getTypeAction(NVT) == Expand)
6445 ExpandOp(Lo, Lo, Hi);
6449 // If source operand will be expanded to the same type as VT, i.e.
6450 // i64 <- f64, i32 <- f32, expand the source operand instead.
6451 MVT VT0 = Node->getOperand(0).getValueType();
6452 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
6453 ExpandOp(Node->getOperand(0), Lo, Hi);
6457 // Turn this into a load/store pair by default.
6458 if (Tmp.getNode() == 0)
6459 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT);
6461 ExpandOp(Tmp, Lo, Hi);
6465 case ISD::READCYCLECOUNTER: {
6466 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
6467 TargetLowering::Custom &&
6468 "Must custom expand ReadCycleCounter");
6469 SDValue Tmp = TLI.LowerOperation(Op, DAG);
6470 assert(Tmp.getNode() && "Node must be custom expanded!");
6471 ExpandOp(Tmp.getValue(0), Lo, Hi);
6472 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6473 LegalizeOp(Tmp.getValue(1)));
6477 case ISD::ATOMIC_CMP_SWAP_64: {
6478 // This operation does not need a loop.
6479 SDValue Tmp = TLI.LowerOperation(Op, DAG);
6480 assert(Tmp.getNode() && "Node must be custom expanded!");
6481 ExpandOp(Tmp.getValue(0), Lo, Hi);
6482 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6483 LegalizeOp(Tmp.getValue(1)));
6487 case ISD::ATOMIC_LOAD_ADD_64:
6488 case ISD::ATOMIC_LOAD_SUB_64:
6489 case ISD::ATOMIC_LOAD_AND_64:
6490 case ISD::ATOMIC_LOAD_OR_64:
6491 case ISD::ATOMIC_LOAD_XOR_64:
6492 case ISD::ATOMIC_LOAD_NAND_64:
6493 case ISD::ATOMIC_SWAP_64: {
6494 // These operations require a loop to be generated. We can't do that yet,
6495 // so substitute a target-dependent pseudo and expand that later.
6496 SDValue In2Lo, In2Hi, In2;
6497 ExpandOp(Op.getOperand(2), In2Lo, In2Hi);
6498 In2 = DAG.getNode(ISD::BUILD_PAIR, VT, In2Lo, In2Hi);
6499 AtomicSDNode* Anode = cast<AtomicSDNode>(Node);
6501 DAG.getAtomic(Op.getOpcode(), Op.getOperand(0), Op.getOperand(1), In2,
6502 Anode->getSrcValue(), Anode->getAlignment());
6503 SDValue Result = TLI.LowerOperation(Replace, DAG);
6504 ExpandOp(Result.getValue(0), Lo, Hi);
6505 // Remember that we legalized the chain.
6506 AddLegalizedOperand(SDValue(Node,1), LegalizeOp(Result.getValue(1)));
6510 // These operators cannot be expanded directly, emit them as calls to
6511 // library functions.
6512 case ISD::FP_TO_SINT: {
6513 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
6515 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6516 case Expand: assert(0 && "cannot expand FP!");
6517 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6518 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6521 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
6523 // Now that the custom expander is done, expand the result, which is still
6526 ExpandOp(Op, Lo, Hi);
6531 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Node->getOperand(0).getValueType(),
6533 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected uint-to-fp conversion!");
6534 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6538 case ISD::FP_TO_UINT: {
6539 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
6541 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6542 case Expand: assert(0 && "cannot expand FP!");
6543 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6544 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6547 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
6549 // Now that the custom expander is done, expand the result.
6551 ExpandOp(Op, Lo, Hi);
6556 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Node->getOperand(0).getValueType(),
6558 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
6559 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6564 // If the target wants custom lowering, do so.
6565 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6566 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
6567 SDValue Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
6568 Op = TLI.LowerOperation(Op, DAG);
6570 // Now that the custom expander is done, expand the result, which is
6572 ExpandOp(Op, Lo, Hi);
6577 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
6578 // this X << 1 as X+X.
6579 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
6580 if (ShAmt->getAPIntValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
6581 TLI.isOperationLegal(ISD::ADDE, NVT)) {
6582 SDValue LoOps[2], HiOps[3];
6583 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
6584 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
6585 LoOps[1] = LoOps[0];
6586 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6588 HiOps[1] = HiOps[0];
6589 HiOps[2] = Lo.getValue(1);
6590 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6595 // If we can emit an efficient shift operation, do so now.
6596 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6599 // If this target supports SHL_PARTS, use it.
6600 TargetLowering::LegalizeAction Action =
6601 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
6602 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6603 Action == TargetLowering::Custom) {
6604 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6608 // Otherwise, emit a libcall.
6609 Lo = ExpandLibCall(RTLIB::SHL_I64, Node, false/*left shift=unsigned*/, Hi);
6614 // If the target wants custom lowering, do so.
6615 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6616 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
6617 SDValue Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
6618 Op = TLI.LowerOperation(Op, DAG);
6620 // Now that the custom expander is done, expand the result, which is
6622 ExpandOp(Op, Lo, Hi);
6627 // If we can emit an efficient shift operation, do so now.
6628 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
6631 // If this target supports SRA_PARTS, use it.
6632 TargetLowering::LegalizeAction Action =
6633 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
6634 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6635 Action == TargetLowering::Custom) {
6636 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6640 // Otherwise, emit a libcall.
6641 Lo = ExpandLibCall(RTLIB::SRA_I64, Node, true/*ashr is signed*/, Hi);
6646 // If the target wants custom lowering, do so.
6647 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6648 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
6649 SDValue Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
6650 Op = TLI.LowerOperation(Op, DAG);
6652 // Now that the custom expander is done, expand the result, which is
6654 ExpandOp(Op, Lo, Hi);
6659 // If we can emit an efficient shift operation, do so now.
6660 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6663 // If this target supports SRL_PARTS, use it.
6664 TargetLowering::LegalizeAction Action =
6665 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
6666 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6667 Action == TargetLowering::Custom) {
6668 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6672 // Otherwise, emit a libcall.
6673 Lo = ExpandLibCall(RTLIB::SRL_I64, Node, false/*lshr is unsigned*/, Hi);
6679 // If the target wants to custom expand this, let them.
6680 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
6681 TargetLowering::Custom) {
6682 SDValue Result = TLI.LowerOperation(Op, DAG);
6683 if (Result.getNode()) {
6684 ExpandOp(Result, Lo, Hi);
6688 // Expand the subcomponents.
6689 SDValue LHSL, LHSH, RHSL, RHSH;
6690 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6691 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6692 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6693 SDValue LoOps[2], HiOps[3];
6699 //cascaded check to see if any smaller size has a a carry flag.
6700 unsigned OpV = Node->getOpcode() == ISD::ADD ? ISD::ADDC : ISD::SUBC;
6701 bool hasCarry = false;
6702 for (unsigned BitSize = NVT.getSizeInBits(); BitSize != 0; BitSize /= 2) {
6703 MVT AVT = MVT::getIntegerVT(BitSize);
6704 if (TLI.isOperationLegal(OpV, AVT)) {
6711 if (Node->getOpcode() == ISD::ADD) {
6712 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6713 HiOps[2] = Lo.getValue(1);
6714 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6716 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6717 HiOps[2] = Lo.getValue(1);
6718 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6722 if (Node->getOpcode() == ISD::ADD) {
6723 Lo = DAG.getNode(ISD::ADD, VTList, LoOps, 2);
6724 Hi = DAG.getNode(ISD::ADD, VTList, HiOps, 2);
6725 SDValue Cmp1 = DAG.getSetCC(TLI.getSetCCResultType(Lo),
6726 Lo, LoOps[0], ISD::SETULT);
6727 SDValue Carry1 = DAG.getNode(ISD::SELECT, NVT, Cmp1,
6728 DAG.getConstant(1, NVT),
6729 DAG.getConstant(0, NVT));
6730 SDValue Cmp2 = DAG.getSetCC(TLI.getSetCCResultType(Lo),
6731 Lo, LoOps[1], ISD::SETULT);
6732 SDValue Carry2 = DAG.getNode(ISD::SELECT, NVT, Cmp2,
6733 DAG.getConstant(1, NVT),
6735 Hi = DAG.getNode(ISD::ADD, NVT, Hi, Carry2);
6737 Lo = DAG.getNode(ISD::SUB, VTList, LoOps, 2);
6738 Hi = DAG.getNode(ISD::SUB, VTList, HiOps, 2);
6739 SDValue Cmp = DAG.getSetCC(NVT, LoOps[0], LoOps[1], ISD::SETULT);
6740 SDValue Borrow = DAG.getNode(ISD::SELECT, NVT, Cmp,
6741 DAG.getConstant(1, NVT),
6742 DAG.getConstant(0, NVT));
6743 Hi = DAG.getNode(ISD::SUB, NVT, Hi, Borrow);
6751 // Expand the subcomponents.
6752 SDValue LHSL, LHSH, RHSL, RHSH;
6753 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6754 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6755 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6756 SDValue LoOps[2] = { LHSL, RHSL };
6757 SDValue HiOps[3] = { LHSH, RHSH };
6759 if (Node->getOpcode() == ISD::ADDC) {
6760 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6761 HiOps[2] = Lo.getValue(1);
6762 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6764 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6765 HiOps[2] = Lo.getValue(1);
6766 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6768 // Remember that we legalized the flag.
6769 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6774 // Expand the subcomponents.
6775 SDValue LHSL, LHSH, RHSL, RHSH;
6776 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6777 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6778 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6779 SDValue LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
6780 SDValue HiOps[3] = { LHSH, RHSH };
6782 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
6783 HiOps[2] = Lo.getValue(1);
6784 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
6786 // Remember that we legalized the flag.
6787 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6791 // If the target wants to custom expand this, let them.
6792 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
6793 SDValue New = TLI.LowerOperation(Op, DAG);
6794 if (New.getNode()) {
6795 ExpandOp(New, Lo, Hi);
6800 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
6801 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
6802 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
6803 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
6804 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
6805 SDValue LL, LH, RL, RH;
6806 ExpandOp(Node->getOperand(0), LL, LH);
6807 ExpandOp(Node->getOperand(1), RL, RH);
6808 unsigned OuterBitSize = Op.getValueSizeInBits();
6809 unsigned InnerBitSize = RH.getValueSizeInBits();
6810 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
6811 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
6812 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
6813 if (DAG.MaskedValueIsZero(Node->getOperand(0), HighMask) &&
6814 DAG.MaskedValueIsZero(Node->getOperand(1), HighMask)) {
6815 // The inputs are both zero-extended.
6817 // We can emit a umul_lohi.
6818 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6819 Hi = SDValue(Lo.getNode(), 1);
6823 // We can emit a mulhu+mul.
6824 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6825 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6829 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
6830 // The input values are both sign-extended.
6832 // We can emit a smul_lohi.
6833 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6834 Hi = SDValue(Lo.getNode(), 1);
6838 // We can emit a mulhs+mul.
6839 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6840 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
6845 // Lo,Hi = umul LHS, RHS.
6846 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
6847 DAG.getVTList(NVT, NVT), LL, RL);
6849 Hi = UMulLOHI.getValue(1);
6850 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6851 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6852 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6853 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6857 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6858 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6859 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6860 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6861 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6862 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6867 // If nothing else, we can make a libcall.
6868 Lo = ExpandLibCall(RTLIB::MUL_I64, Node, false/*sign irrelevant*/, Hi);
6872 Lo = ExpandLibCall(RTLIB::SDIV_I64, Node, true, Hi);
6875 Lo = ExpandLibCall(RTLIB::UDIV_I64, Node, true, Hi);
6878 Lo = ExpandLibCall(RTLIB::SREM_I64, Node, true, Hi);
6881 Lo = ExpandLibCall(RTLIB::UREM_I64, Node, true, Hi);
6885 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::ADD_F32,
6888 RTLIB::ADD_PPCF128),
6892 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::SUB_F32,
6895 RTLIB::SUB_PPCF128),
6899 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::MUL_F32,
6902 RTLIB::MUL_PPCF128),
6906 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::DIV_F32,
6909 RTLIB::DIV_PPCF128),
6912 case ISD::FP_EXTEND: {
6913 if (VT == MVT::ppcf128) {
6914 assert(Node->getOperand(0).getValueType()==MVT::f32 ||
6915 Node->getOperand(0).getValueType()==MVT::f64);
6916 const uint64_t zero = 0;
6917 if (Node->getOperand(0).getValueType()==MVT::f32)
6918 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0));
6920 Hi = Node->getOperand(0);
6921 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6924 RTLIB::Libcall LC = RTLIB::getFPEXT(Node->getOperand(0).getValueType(), VT);
6925 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!");
6926 Lo = ExpandLibCall(LC, Node, true, Hi);
6929 case ISD::FP_ROUND: {
6930 RTLIB::Libcall LC = RTLIB::getFPROUND(Node->getOperand(0).getValueType(),
6932 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!");
6933 Lo = ExpandLibCall(LC, Node, true, Hi);
6948 case ISD::FNEARBYINT:
6951 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6952 switch(Node->getOpcode()) {
6954 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
6955 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
6958 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
6959 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
6962 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
6963 RTLIB::COS_F80, RTLIB::COS_PPCF128);
6966 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
6967 RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
6970 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
6971 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
6974 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
6975 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
6978 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
6979 RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
6982 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
6983 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
6986 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
6987 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
6990 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
6991 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128);
6994 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
6995 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128);
6998 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64,
6999 RTLIB::RINT_F80, RTLIB::RINT_PPCF128);
7001 case ISD::FNEARBYINT:
7002 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
7003 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
7006 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
7007 RTLIB::POW_PPCF128);
7010 LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64, RTLIB::POWI_F80,
7011 RTLIB::POWI_PPCF128);
7013 default: assert(0 && "Unreachable!");
7015 Lo = ExpandLibCall(LC, Node, false, Hi);
7019 if (VT == MVT::ppcf128) {
7021 ExpandOp(Node->getOperand(0), Lo, Tmp);
7022 Hi = DAG.getNode(ISD::FABS, NVT, Tmp);
7023 // lo = hi==fabs(hi) ? lo : -lo;
7024 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp,
7025 Lo, DAG.getNode(ISD::FNEG, NVT, Lo),
7026 DAG.getCondCode(ISD::SETEQ));
7029 SDValue Mask = (VT == MVT::f64)
7030 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
7031 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
7032 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
7033 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
7034 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
7035 if (getTypeAction(NVT) == Expand)
7036 ExpandOp(Lo, Lo, Hi);
7040 if (VT == MVT::ppcf128) {
7041 ExpandOp(Node->getOperand(0), Lo, Hi);
7042 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo);
7043 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi);
7046 SDValue Mask = (VT == MVT::f64)
7047 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
7048 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
7049 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
7050 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
7051 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
7052 if (getTypeAction(NVT) == Expand)
7053 ExpandOp(Lo, Lo, Hi);
7056 case ISD::FCOPYSIGN: {
7057 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
7058 if (getTypeAction(NVT) == Expand)
7059 ExpandOp(Lo, Lo, Hi);
7062 case ISD::SINT_TO_FP:
7063 case ISD::UINT_TO_FP: {
7064 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
7065 MVT SrcVT = Node->getOperand(0).getValueType();
7067 // Promote the operand if needed. Do this before checking for
7068 // ppcf128 so conversions of i16 and i8 work.
7069 if (getTypeAction(SrcVT) == Promote) {
7070 SDValue Tmp = PromoteOp(Node->getOperand(0));
7072 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
7073 DAG.getValueType(SrcVT))
7074 : DAG.getZeroExtendInReg(Tmp, SrcVT);
7075 Node = DAG.UpdateNodeOperands(Op, Tmp).getNode();
7076 SrcVT = Node->getOperand(0).getValueType();
7079 if (VT == MVT::ppcf128 && SrcVT == MVT::i32) {
7080 static const uint64_t zero = 0;
7082 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
7083 Node->getOperand(0)));
7084 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7086 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
7087 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
7088 Node->getOperand(0)));
7089 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7090 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
7091 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
7092 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
7093 DAG.getConstant(0, MVT::i32),
7094 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
7096 APFloat(APInt(128, 2, TwoE32)),
7099 DAG.getCondCode(ISD::SETLT)),
7104 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) {
7105 // si64->ppcf128 done by libcall, below
7106 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
7107 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)),
7109 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
7110 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
7111 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
7112 DAG.getConstant(0, MVT::i64),
7113 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
7115 APFloat(APInt(128, 2, TwoE64)),
7118 DAG.getCondCode(ISD::SETLT)),
7123 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
7124 Node->getOperand(0));
7125 if (getTypeAction(Lo.getValueType()) == Expand)
7126 // float to i32 etc. can be 'expanded' to a single node.
7127 ExpandOp(Lo, Lo, Hi);
7132 // Make sure the resultant values have been legalized themselves, unless this
7133 // is a type that requires multi-step expansion.
7134 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
7135 Lo = LegalizeOp(Lo);
7137 // Don't legalize the high part if it is expanded to a single node.
7138 Hi = LegalizeOp(Hi);
7141 // Remember in a map if the values will be reused later.
7143 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
7144 assert(isNew && "Value already expanded?!?");
7147 /// SplitVectorOp - Given an operand of vector type, break it down into
7148 /// two smaller values, still of vector type.
7149 void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
7151 assert(Op.getValueType().isVector() && "Cannot split non-vector type!");
7152 SDNode *Node = Op.getNode();
7153 unsigned NumElements = Op.getValueType().getVectorNumElements();
7154 assert(NumElements > 1 && "Cannot split a single element vector!");
7156 MVT NewEltVT = Op.getValueType().getVectorElementType();
7158 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
7159 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
7161 MVT NewVT_Lo = MVT::getVectorVT(NewEltVT, NewNumElts_Lo);
7162 MVT NewVT_Hi = MVT::getVectorVT(NewEltVT, NewNumElts_Hi);
7164 // See if we already split it.
7165 std::map<SDValue, std::pair<SDValue, SDValue> >::iterator I
7166 = SplitNodes.find(Op);
7167 if (I != SplitNodes.end()) {
7168 Lo = I->second.first;
7169 Hi = I->second.second;
7173 switch (Node->getOpcode()) {
7178 assert(0 && "Unhandled operation in SplitVectorOp!");
7180 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo);
7181 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi);
7183 case ISD::BUILD_PAIR:
7184 Lo = Node->getOperand(0);
7185 Hi = Node->getOperand(1);
7187 case ISD::INSERT_VECTOR_ELT: {
7188 if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) {
7189 SplitVectorOp(Node->getOperand(0), Lo, Hi);
7190 unsigned Index = Idx->getZExtValue();
7191 SDValue ScalarOp = Node->getOperand(1);
7192 if (Index < NewNumElts_Lo)
7193 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp,
7194 DAG.getIntPtrConstant(Index));
7196 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp,
7197 DAG.getIntPtrConstant(Index - NewNumElts_Lo));
7200 SDValue Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0),
7201 Node->getOperand(1),
7202 Node->getOperand(2));
7203 SplitVectorOp(Tmp, Lo, Hi);
7206 case ISD::VECTOR_SHUFFLE: {
7207 // Build the low part.
7208 SDValue Mask = Node->getOperand(2);
7209 SmallVector<SDValue, 8> Ops;
7210 MVT PtrVT = TLI.getPointerTy();
7212 // Insert all of the elements from the input that are needed. We use
7213 // buildvector of extractelement here because the input vectors will have
7214 // to be legalized, so this makes the code simpler.
7215 for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
7216 SDValue IdxNode = Mask.getOperand(i);
7217 if (IdxNode.getOpcode() == ISD::UNDEF) {
7218 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
7221 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
7222 SDValue InVec = Node->getOperand(0);
7223 if (Idx >= NumElements) {
7224 InVec = Node->getOperand(1);
7227 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
7228 DAG.getConstant(Idx, PtrVT)));
7230 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
7233 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
7234 SDValue IdxNode = Mask.getOperand(i);
7235 if (IdxNode.getOpcode() == ISD::UNDEF) {
7236 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
7239 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
7240 SDValue InVec = Node->getOperand(0);
7241 if (Idx >= NumElements) {
7242 InVec = Node->getOperand(1);
7245 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
7246 DAG.getConstant(Idx, PtrVT)));
7248 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &Ops[0], Ops.size());
7251 case ISD::BUILD_VECTOR: {
7252 SmallVector<SDValue, 8> LoOps(Node->op_begin(),
7253 Node->op_begin()+NewNumElts_Lo);
7254 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size());
7256 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
7258 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size());
7261 case ISD::CONCAT_VECTORS: {
7262 // FIXME: Handle non-power-of-two vectors?
7263 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
7264 if (NewNumSubvectors == 1) {
7265 Lo = Node->getOperand(0);
7266 Hi = Node->getOperand(1);
7268 SmallVector<SDValue, 8> LoOps(Node->op_begin(),
7269 Node->op_begin()+NewNumSubvectors);
7270 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size());
7272 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumSubvectors,
7274 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size());
7278 case ISD::EXTRACT_SUBVECTOR: {
7279 SDValue Vec = Op.getOperand(0);
7280 SDValue Idx = Op.getOperand(1);
7281 MVT IdxVT = Idx.getValueType();
7283 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, NewVT_Lo, Vec, Idx);
7284 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx);
7286 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, NewVT_Hi, Vec,
7287 DAG.getConstant(CIdx->getZExtValue() + NewNumElts_Lo,
7290 Idx = DAG.getNode(ISD::ADD, IdxVT, Idx,
7291 DAG.getConstant(NewNumElts_Lo, IdxVT));
7292 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, NewVT_Hi, Vec, Idx);
7297 SDValue Cond = Node->getOperand(0);
7299 SDValue LL, LH, RL, RH;
7300 SplitVectorOp(Node->getOperand(1), LL, LH);
7301 SplitVectorOp(Node->getOperand(2), RL, RH);
7303 if (Cond.getValueType().isVector()) {
7304 // Handle a vector merge.
7306 SplitVectorOp(Cond, CL, CH);
7307 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL);
7308 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH);
7310 // Handle a simple select with vector operands.
7311 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL);
7312 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH);
7316 case ISD::SELECT_CC: {
7317 SDValue CondLHS = Node->getOperand(0);
7318 SDValue CondRHS = Node->getOperand(1);
7319 SDValue CondCode = Node->getOperand(4);
7321 SDValue LL, LH, RL, RH;
7322 SplitVectorOp(Node->getOperand(2), LL, LH);
7323 SplitVectorOp(Node->getOperand(3), RL, RH);
7325 // Handle a simple select with vector operands.
7326 Lo = DAG.getNode(ISD::SELECT_CC, NewVT_Lo, CondLHS, CondRHS,
7328 Hi = DAG.getNode(ISD::SELECT_CC, NewVT_Hi, CondLHS, CondRHS,
7333 SDValue LL, LH, RL, RH;
7334 SplitVectorOp(Node->getOperand(0), LL, LH);
7335 SplitVectorOp(Node->getOperand(1), RL, RH);
7336 Lo = DAG.getNode(ISD::VSETCC, NewVT_Lo, LL, RL, Node->getOperand(2));
7337 Hi = DAG.getNode(ISD::VSETCC, NewVT_Hi, LH, RH, Node->getOperand(2));
7356 SDValue LL, LH, RL, RH;
7357 SplitVectorOp(Node->getOperand(0), LL, LH);
7358 SplitVectorOp(Node->getOperand(1), RL, RH);
7360 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL);
7361 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH);
7367 SplitVectorOp(Node->getOperand(0), L, H);
7369 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1));
7370 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1));
7386 case ISD::FP_TO_SINT:
7387 case ISD::FP_TO_UINT:
7388 case ISD::SINT_TO_FP:
7389 case ISD::UINT_TO_FP:
7391 case ISD::ANY_EXTEND:
7392 case ISD::SIGN_EXTEND:
7393 case ISD::ZERO_EXTEND:
7394 case ISD::FP_EXTEND: {
7396 SplitVectorOp(Node->getOperand(0), L, H);
7398 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L);
7399 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H);
7402 case ISD::CONVERT_RNDSAT: {
7403 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
7405 SplitVectorOp(Node->getOperand(0), L, H);
7406 SDValue DTyOpL = DAG.getValueType(NewVT_Lo);
7407 SDValue DTyOpH = DAG.getValueType(NewVT_Hi);
7408 SDValue STyOpL = DAG.getValueType(L.getValueType());
7409 SDValue STyOpH = DAG.getValueType(H.getValueType());
7411 SDValue RndOp = Node->getOperand(3);
7412 SDValue SatOp = Node->getOperand(4);
7414 Lo = DAG.getConvertRndSat(NewVT_Lo, L, DTyOpL, STyOpL,
7415 RndOp, SatOp, CvtCode);
7416 Hi = DAG.getConvertRndSat(NewVT_Hi, H, DTyOpH, STyOpH,
7417 RndOp, SatOp, CvtCode);
7421 LoadSDNode *LD = cast<LoadSDNode>(Node);
7422 SDValue Ch = LD->getChain();
7423 SDValue Ptr = LD->getBasePtr();
7424 ISD::LoadExtType ExtType = LD->getExtensionType();
7425 const Value *SV = LD->getSrcValue();
7426 int SVOffset = LD->getSrcValueOffset();
7427 MVT MemoryVT = LD->getMemoryVT();
7428 unsigned Alignment = LD->getAlignment();
7429 bool isVolatile = LD->isVolatile();
7431 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
7432 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType());
7434 MVT MemNewEltVT = MemoryVT.getVectorElementType();
7435 MVT MemNewVT_Lo = MVT::getVectorVT(MemNewEltVT, NewNumElts_Lo);
7436 MVT MemNewVT_Hi = MVT::getVectorVT(MemNewEltVT, NewNumElts_Hi);
7438 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType,
7439 NewVT_Lo, Ch, Ptr, Offset,
7440 SV, SVOffset, MemNewVT_Lo, isVolatile, Alignment);
7441 unsigned IncrementSize = NewNumElts_Lo * MemNewEltVT.getSizeInBits()/8;
7442 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
7443 DAG.getIntPtrConstant(IncrementSize));
7444 SVOffset += IncrementSize;
7445 Alignment = MinAlign(Alignment, IncrementSize);
7446 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType,
7447 NewVT_Hi, Ch, Ptr, Offset,
7448 SV, SVOffset, MemNewVT_Hi, isVolatile, Alignment);
7450 // Build a factor node to remember that this load is independent of the
7452 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
7455 // Remember that we legalized the chain.
7456 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
7459 case ISD::BIT_CONVERT: {
7460 // We know the result is a vector. The input may be either a vector or a
7462 SDValue InOp = Node->getOperand(0);
7463 if (!InOp.getValueType().isVector() ||
7464 InOp.getValueType().getVectorNumElements() == 1) {
7465 // The input is a scalar or single-element vector.
7466 // Lower to a store/load so that it can be split.
7467 // FIXME: this could be improved probably.
7468 unsigned LdAlign = TLI.getTargetData()->getPrefTypeAlignment(
7469 Op.getValueType().getTypeForMVT());
7470 SDValue Ptr = DAG.CreateStackTemporary(InOp.getValueType(), LdAlign);
7471 int FI = cast<FrameIndexSDNode>(Ptr.getNode())->getIndex();
7473 SDValue St = DAG.getStore(DAG.getEntryNode(),
7475 PseudoSourceValue::getFixedStack(FI), 0);
7476 InOp = DAG.getLoad(Op.getValueType(), St, Ptr,
7477 PseudoSourceValue::getFixedStack(FI), 0);
7479 // Split the vector and convert each of the pieces now.
7480 SplitVectorOp(InOp, Lo, Hi);
7481 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo);
7482 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi);
7487 // Remember in a map if the values will be reused later.
7489 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
7490 assert(isNew && "Value already split?!?");
7494 /// ScalarizeVectorOp - Given an operand of single-element vector type
7495 /// (e.g. v1f32), convert it into the equivalent operation that returns a
7496 /// scalar (e.g. f32) value.
7497 SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) {
7498 assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!");
7499 SDNode *Node = Op.getNode();
7500 MVT NewVT = Op.getValueType().getVectorElementType();
7501 assert(Op.getValueType().getVectorNumElements() == 1);
7503 // See if we already scalarized it.
7504 std::map<SDValue, SDValue>::iterator I = ScalarizedNodes.find(Op);
7505 if (I != ScalarizedNodes.end()) return I->second;
7508 switch (Node->getOpcode()) {
7511 Node->dump(&DAG); cerr << "\n";
7513 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
7530 Result = DAG.getNode(Node->getOpcode(),
7532 ScalarizeVectorOp(Node->getOperand(0)),
7533 ScalarizeVectorOp(Node->getOperand(1)));
7545 case ISD::FP_TO_SINT:
7546 case ISD::FP_TO_UINT:
7547 case ISD::SINT_TO_FP:
7548 case ISD::UINT_TO_FP:
7549 case ISD::SIGN_EXTEND:
7550 case ISD::ZERO_EXTEND:
7551 case ISD::ANY_EXTEND:
7553 case ISD::FP_EXTEND:
7554 Result = DAG.getNode(Node->getOpcode(),
7556 ScalarizeVectorOp(Node->getOperand(0)));
7558 case ISD::CONVERT_RNDSAT: {
7559 SDValue Op0 = ScalarizeVectorOp(Node->getOperand(0));
7560 Result = DAG.getConvertRndSat(NewVT, Op0,
7561 DAG.getValueType(NewVT),
7562 DAG.getValueType(Op0.getValueType()),
7563 Node->getOperand(3),
7564 Node->getOperand(4),
7565 cast<CvtRndSatSDNode>(Node)->getCvtCode());
7570 Result = DAG.getNode(Node->getOpcode(),
7572 ScalarizeVectorOp(Node->getOperand(0)),
7573 Node->getOperand(1));
7576 LoadSDNode *LD = cast<LoadSDNode>(Node);
7577 SDValue Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
7578 SDValue Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
7579 ISD::LoadExtType ExtType = LD->getExtensionType();
7580 const Value *SV = LD->getSrcValue();
7581 int SVOffset = LD->getSrcValueOffset();
7582 MVT MemoryVT = LD->getMemoryVT();
7583 unsigned Alignment = LD->getAlignment();
7584 bool isVolatile = LD->isVolatile();
7586 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
7587 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType());
7589 Result = DAG.getLoad(ISD::UNINDEXED, ExtType,
7590 NewVT, Ch, Ptr, Offset, SV, SVOffset,
7591 MemoryVT.getVectorElementType(),
7592 isVolatile, Alignment);
7594 // Remember that we legalized the chain.
7595 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
7598 case ISD::BUILD_VECTOR:
7599 Result = Node->getOperand(0);
7601 case ISD::INSERT_VECTOR_ELT:
7602 // Returning the inserted scalar element.
7603 Result = Node->getOperand(1);
7605 case ISD::CONCAT_VECTORS:
7606 assert(Node->getOperand(0).getValueType() == NewVT &&
7607 "Concat of non-legal vectors not yet supported!");
7608 Result = Node->getOperand(0);
7610 case ISD::VECTOR_SHUFFLE: {
7611 // Figure out if the scalar is the LHS or RHS and return it.
7612 SDValue EltNum = Node->getOperand(2).getOperand(0);
7613 if (cast<ConstantSDNode>(EltNum)->getZExtValue())
7614 Result = ScalarizeVectorOp(Node->getOperand(1));
7616 Result = ScalarizeVectorOp(Node->getOperand(0));
7619 case ISD::EXTRACT_SUBVECTOR:
7620 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, Node->getOperand(0),
7621 Node->getOperand(1));
7623 case ISD::BIT_CONVERT: {
7624 SDValue Op0 = Op.getOperand(0);
7625 if (Op0.getValueType().getVectorNumElements() == 1)
7626 Op0 = ScalarizeVectorOp(Op0);
7627 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op0);
7631 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
7632 ScalarizeVectorOp(Op.getOperand(1)),
7633 ScalarizeVectorOp(Op.getOperand(2)));
7635 case ISD::SELECT_CC:
7636 Result = DAG.getNode(ISD::SELECT_CC, NewVT, Node->getOperand(0),
7637 Node->getOperand(1),
7638 ScalarizeVectorOp(Op.getOperand(2)),
7639 ScalarizeVectorOp(Op.getOperand(3)),
7640 Node->getOperand(4));
7643 SDValue Op0 = ScalarizeVectorOp(Op.getOperand(0));
7644 SDValue Op1 = ScalarizeVectorOp(Op.getOperand(1));
7645 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Op0), Op0, Op1,
7647 Result = DAG.getNode(ISD::SELECT, NewVT, Result,
7648 DAG.getConstant(-1ULL, NewVT),
7649 DAG.getConstant(0ULL, NewVT));
7654 if (TLI.isTypeLegal(NewVT))
7655 Result = LegalizeOp(Result);
7656 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
7657 assert(isNew && "Value already scalarized?");
7662 SDValue SelectionDAGLegalize::WidenVectorOp(SDValue Op, MVT WidenVT) {
7663 std::map<SDValue, SDValue>::iterator I = WidenNodes.find(Op);
7664 if (I != WidenNodes.end()) return I->second;
7666 MVT VT = Op.getValueType();
7667 assert(VT.isVector() && "Cannot widen non-vector type!");
7670 SDNode *Node = Op.getNode();
7671 MVT EVT = VT.getVectorElementType();
7673 unsigned NumElts = VT.getVectorNumElements();
7674 unsigned NewNumElts = WidenVT.getVectorNumElements();
7675 assert(NewNumElts > NumElts && "Cannot widen to smaller type!");
7676 assert(NewNumElts < 17);
7678 // When widen is called, it is assumed that it is more efficient to use a
7679 // wide type. The default action is to widen to operation to a wider legal
7680 // vector type and then do the operation if it is legal by calling LegalizeOp
7681 // again. If there is no vector equivalent, we will unroll the operation, do
7682 // it, and rebuild the vector. If most of the operations are vectorizible to
7683 // the legal type, the resulting code will be more efficient. If this is not
7684 // the case, the resulting code will preform badly as we end up generating
7685 // code to pack/unpack the results. It is the function that calls widen
7686 // that is responsible for seeing this doesn't happen.
7687 switch (Node->getOpcode()) {
7692 assert(0 && "Unexpected operation in WidenVectorOp!");
7694 case ISD::CopyFromReg:
7695 assert(0 && "CopyFromReg doesn't need widening!");
7697 case ISD::ConstantFP:
7698 // To build a vector of these elements, clients should call BuildVector
7699 // and with each element instead of creating a node with a vector type
7700 assert(0 && "Unexpected operation in WidenVectorOp!");
7702 // Variable Arguments with vector types doesn't make any sense to me
7703 assert(0 && "Unexpected operation in WidenVectorOp!");
7706 Result = DAG.getNode(ISD::UNDEF, WidenVT);
7708 case ISD::BUILD_VECTOR: {
7709 // Build a vector with undefined for the new nodes
7710 SDValueVector NewOps(Node->op_begin(), Node->op_end());
7711 for (unsigned i = NumElts; i < NewNumElts; ++i) {
7712 NewOps.push_back(DAG.getNode(ISD::UNDEF,EVT));
7714 Result = DAG.getNode(ISD::BUILD_VECTOR, WidenVT, &NewOps[0], NewOps.size());
7717 case ISD::INSERT_VECTOR_ELT: {
7718 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
7719 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, WidenVT, Tmp1,
7720 Node->getOperand(1), Node->getOperand(2));
7723 case ISD::VECTOR_SHUFFLE: {
7724 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
7725 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT);
7726 // VECTOR_SHUFFLE 3rd operand must be a constant build vector that is
7727 // used as permutation array. We build the vector here instead of widening
7728 // because we don't want to legalize and have it turned to something else.
7729 SDValue PermOp = Node->getOperand(2);
7730 SDValueVector NewOps;
7731 MVT PVT = PermOp.getValueType().getVectorElementType();
7732 for (unsigned i = 0; i < NumElts; ++i) {
7733 if (PermOp.getOperand(i).getOpcode() == ISD::UNDEF) {
7734 NewOps.push_back(PermOp.getOperand(i));
7737 cast<ConstantSDNode>(PermOp.getOperand(i))->getZExtValue();
7738 if (Idx < NumElts) {
7739 NewOps.push_back(PermOp.getOperand(i));
7742 NewOps.push_back(DAG.getConstant(Idx + NewNumElts - NumElts,
7743 PermOp.getOperand(i).getValueType()));
7747 for (unsigned i = NumElts; i < NewNumElts; ++i) {
7748 NewOps.push_back(DAG.getNode(ISD::UNDEF,PVT));
7751 SDValue Tmp3 = DAG.getNode(ISD::BUILD_VECTOR,
7752 MVT::getVectorVT(PVT, NewOps.size()),
7753 &NewOps[0], NewOps.size());
7755 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, WidenVT, Tmp1, Tmp2, Tmp3);
7759 // If the load widen returns true, we can use a single load for the
7760 // vector. Otherwise, it is returning a token factor for multiple
7763 if (LoadWidenVectorOp(Result, TFOp, Op, WidenVT))
7764 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TFOp.getValue(1)));
7766 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TFOp.getValue(0)));
7770 case ISD::BIT_CONVERT: {
7771 SDValue Tmp1 = Node->getOperand(0);
7772 // Converts between two different types so we need to determine
7773 // the correct widen type for the input operand.
7774 MVT TVT = Tmp1.getValueType();
7775 assert(TVT.isVector() && "can not widen non vector type");
7776 MVT TEVT = TVT.getVectorElementType();
7777 assert(WidenVT.getSizeInBits() % EVT.getSizeInBits() == 0 &&
7778 "can not widen bit bit convert that are not multiple of element type");
7779 MVT TWidenVT = MVT::getVectorVT(TEVT,
7780 WidenVT.getSizeInBits()/EVT.getSizeInBits());
7781 Tmp1 = WidenVectorOp(Tmp1, TWidenVT);
7782 assert(Tmp1.getValueType().getSizeInBits() == WidenVT.getSizeInBits());
7783 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1);
7785 TargetLowering::LegalizeAction action =
7786 TLI.getOperationAction(Node->getOpcode(), WidenVT);
7788 default: assert(0 && "action not supported");
7789 case TargetLowering::Legal:
7791 case TargetLowering::Promote:
7792 // We defer the promotion to when we legalize the op
7794 case TargetLowering::Expand:
7795 // Expand the operation into a bunch of nasty scalar code.
7796 Result = LegalizeOp(UnrollVectorOp(Result));
7802 case ISD::SINT_TO_FP:
7803 case ISD::UINT_TO_FP:
7804 case ISD::FP_TO_SINT:
7805 case ISD::FP_TO_UINT: {
7806 SDValue Tmp1 = Node->getOperand(0);
7807 // Converts between two different types so we need to determine
7808 // the correct widen type for the input operand.
7809 MVT TVT = Tmp1.getValueType();
7810 assert(TVT.isVector() && "can not widen non vector type");
7811 MVT TEVT = TVT.getVectorElementType();
7812 MVT TWidenVT = MVT::getVectorVT(TEVT, NewNumElts);
7813 Tmp1 = WidenVectorOp(Tmp1, TWidenVT);
7814 assert(Tmp1.getValueType().getVectorNumElements() == NewNumElts);
7815 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1);
7817 TargetLowering::LegalizeAction action =
7818 TLI.getOperationAction(Node->getOpcode(), WidenVT);
7820 default: assert(0 && "action not supported");
7821 case TargetLowering::Legal:
7823 case TargetLowering::Promote:
7824 // We defer the promotion to when we legalize the op
7826 case TargetLowering::Expand:
7827 // Expand the operation into a bunch of nasty scalar code.
7828 Result = LegalizeOp(UnrollVectorOp(Result));
7834 case ISD::FP_EXTEND:
7835 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
7837 case ISD::SIGN_EXTEND:
7838 case ISD::ZERO_EXTEND:
7839 case ISD::ANY_EXTEND:
7841 case ISD::SIGN_EXTEND_INREG:
7850 // Unary op widening
7852 TargetLowering::LegalizeAction action =
7853 TLI.getOperationAction(Node->getOpcode(), WidenVT);
7855 Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
7856 assert(Tmp1.getValueType() == WidenVT);
7857 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1);
7859 default: assert(0 && "action not supported");
7860 case TargetLowering::Legal:
7862 case TargetLowering::Promote:
7863 // We defer the promotion to when we legalize the op
7865 case TargetLowering::Expand:
7866 // Expand the operation into a bunch of nasty scalar code.
7867 Result = LegalizeOp(UnrollVectorOp(Result));
7872 case ISD::CONVERT_RNDSAT: {
7873 SDValue RndOp = Node->getOperand(3);
7874 SDValue SatOp = Node->getOperand(4);
7876 TargetLowering::LegalizeAction action =
7877 TLI.getOperationAction(Node->getOpcode(), WidenVT);
7879 SDValue SrcOp = Node->getOperand(0);
7881 // Converts between two different types so we need to determine
7882 // the correct widen type for the input operand.
7883 MVT SVT = SrcOp.getValueType();
7884 assert(SVT.isVector() && "can not widen non vector type");
7885 MVT SEVT = SVT.getVectorElementType();
7886 MVT SWidenVT = MVT::getVectorVT(SEVT, NewNumElts);
7888 SrcOp = WidenVectorOp(SrcOp, SWidenVT);
7889 assert(SrcOp.getValueType() == WidenVT);
7890 SDValue DTyOp = DAG.getValueType(WidenVT);
7891 SDValue STyOp = DAG.getValueType(SrcOp.getValueType());
7892 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
7894 Result = DAG.getConvertRndSat(WidenVT, SrcOp, DTyOp, STyOp,
7895 RndOp, SatOp, CvtCode);
7897 default: assert(0 && "action not supported");
7898 case TargetLowering::Legal:
7900 case TargetLowering::Promote:
7901 // We defer the promotion to when we legalize the op
7903 case TargetLowering::Expand:
7904 // Expand the operation into a bunch of nasty scalar code.
7905 Result = LegalizeOp(UnrollVectorOp(Result));
7927 case ISD::FCOPYSIGN:
7931 // Binary op widening
7932 TargetLowering::LegalizeAction action =
7933 TLI.getOperationAction(Node->getOpcode(), WidenVT);
7935 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
7936 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT);
7937 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT);
7938 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1, Tmp2);
7940 default: assert(0 && "action not supported");
7941 case TargetLowering::Legal:
7943 case TargetLowering::Promote:
7944 // We defer the promotion to when we legalize the op
7946 case TargetLowering::Expand:
7947 // Expand the operation into a bunch of nasty scalar code by first
7948 // Widening to the right type and then unroll the beast.
7949 Result = LegalizeOp(UnrollVectorOp(Result));
7958 // Binary op with one non vector operand
7959 TargetLowering::LegalizeAction action =
7960 TLI.getOperationAction(Node->getOpcode(), WidenVT);
7962 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
7963 assert(Tmp1.getValueType() == WidenVT);
7964 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1, Node->getOperand(1));
7966 default: assert(0 && "action not supported");
7967 case TargetLowering::Legal:
7969 case TargetLowering::Promote:
7970 // We defer the promotion to when we legalize the op
7972 case TargetLowering::Expand:
7973 // Expand the operation into a bunch of nasty scalar code.
7974 Result = LegalizeOp(UnrollVectorOp(Result));
7979 case ISD::EXTRACT_VECTOR_ELT: {
7980 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
7981 assert(Tmp1.getValueType() == WidenVT);
7982 Result = DAG.getNode(Node->getOpcode(), EVT, Tmp1, Node->getOperand(1));
7985 case ISD::CONCAT_VECTORS: {
7986 // We concurrently support only widen on a multiple of the incoming vector.
7987 // We could widen on a multiple of the incoming operand if necessary.
7988 unsigned NumConcat = NewNumElts / NumElts;
7989 assert(NewNumElts % NumElts == 0 && "Can widen only a multiple of vector");
7990 std::vector<SDValue> UnOps(NumElts, DAG.getNode(ISD::UNDEF,
7991 VT.getVectorElementType()));
7992 SDValue UndefVal = DAG.getNode(ISD::BUILD_VECTOR, VT,
7993 &UnOps[0], UnOps.size());
7994 SmallVector<SDValue, 8> MOps;
7996 for (unsigned i = 1; i != NumConcat; ++i) {
7997 MOps.push_back(UndefVal);
7999 Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, WidenVT,
8000 &MOps[0], MOps.size()));
8003 case ISD::EXTRACT_SUBVECTOR: {
8004 SDValue Tmp1 = Node->getOperand(0);
8005 SDValue Idx = Node->getOperand(1);
8006 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx);
8007 if (CIdx && CIdx->getZExtValue() == 0) {
8008 // Since we are access the start of the vector, the incoming
8009 // vector type might be the proper.
8010 MVT Tmp1VT = Tmp1.getValueType();
8011 if (Tmp1VT == WidenVT)
8014 unsigned Tmp1VTNumElts = Tmp1VT.getVectorNumElements();
8015 if (Tmp1VTNumElts < NewNumElts)
8016 Result = WidenVectorOp(Tmp1, WidenVT);
8018 Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, WidenVT, Tmp1, Idx);
8020 } else if (NewNumElts % NumElts == 0) {
8021 // Widen the extracted subvector.
8022 unsigned NumConcat = NewNumElts / NumElts;
8023 SDValue UndefVal = DAG.getNode(ISD::UNDEF, VT);
8024 SmallVector<SDValue, 8> MOps;
8026 for (unsigned i = 1; i != NumConcat; ++i) {
8027 MOps.push_back(UndefVal);
8029 Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, WidenVT,
8030 &MOps[0], MOps.size()));
8032 assert(0 && "can not widen extract subvector");
8033 // This could be implemented using insert and build vector but I would
8034 // like to see when this happens.
8040 TargetLowering::LegalizeAction action =
8041 TLI.getOperationAction(Node->getOpcode(), WidenVT);
8043 // Determine new condition widen type and widen
8044 SDValue Cond1 = Node->getOperand(0);
8045 MVT CondVT = Cond1.getValueType();
8046 assert(CondVT.isVector() && "can not widen non vector type");
8047 MVT CondEVT = CondVT.getVectorElementType();
8048 MVT CondWidenVT = MVT::getVectorVT(CondEVT, NewNumElts);
8049 Cond1 = WidenVectorOp(Cond1, CondWidenVT);
8050 assert(Cond1.getValueType() == CondWidenVT && "Condition not widen");
8052 SDValue Tmp1 = WidenVectorOp(Node->getOperand(1), WidenVT);
8053 SDValue Tmp2 = WidenVectorOp(Node->getOperand(2), WidenVT);
8054 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT);
8055 Result = DAG.getNode(Node->getOpcode(), WidenVT, Cond1, Tmp1, Tmp2);
8057 default: assert(0 && "action not supported");
8058 case TargetLowering::Legal:
8060 case TargetLowering::Promote:
8061 // We defer the promotion to when we legalize the op
8063 case TargetLowering::Expand:
8064 // Expand the operation into a bunch of nasty scalar code by first
8065 // Widening to the right type and then unroll the beast.
8066 Result = LegalizeOp(UnrollVectorOp(Result));
8072 case ISD::SELECT_CC: {
8073 TargetLowering::LegalizeAction action =
8074 TLI.getOperationAction(Node->getOpcode(), WidenVT);
8076 // Determine new condition widen type and widen
8077 SDValue Cond1 = Node->getOperand(0);
8078 SDValue Cond2 = Node->getOperand(1);
8079 MVT CondVT = Cond1.getValueType();
8080 assert(CondVT.isVector() && "can not widen non vector type");
8081 assert(CondVT == Cond2.getValueType() && "mismatch lhs/rhs");
8082 MVT CondEVT = CondVT.getVectorElementType();
8083 MVT CondWidenVT = MVT::getVectorVT(CondEVT, NewNumElts);
8084 Cond1 = WidenVectorOp(Cond1, CondWidenVT);
8085 Cond2 = WidenVectorOp(Cond2, CondWidenVT);
8086 assert(Cond1.getValueType() == CondWidenVT &&
8087 Cond2.getValueType() == CondWidenVT && "condition not widen");
8089 SDValue Tmp1 = WidenVectorOp(Node->getOperand(2), WidenVT);
8090 SDValue Tmp2 = WidenVectorOp(Node->getOperand(3), WidenVT);
8091 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT &&
8092 "operands not widen");
8093 Result = DAG.getNode(Node->getOpcode(), WidenVT, Cond1, Cond2, Tmp1,
8094 Tmp2, Node->getOperand(4));
8096 default: assert(0 && "action not supported");
8097 case TargetLowering::Legal:
8099 case TargetLowering::Promote:
8100 // We defer the promotion to when we legalize the op
8102 case TargetLowering::Expand:
8103 // Expand the operation into a bunch of nasty scalar code by first
8104 // Widening to the right type and then unroll the beast.
8105 Result = LegalizeOp(UnrollVectorOp(Result));
8111 // Determine widen for the operand
8112 SDValue Tmp1 = Node->getOperand(0);
8113 MVT TmpVT = Tmp1.getValueType();
8114 assert(TmpVT.isVector() && "can not widen non vector type");
8115 MVT TmpEVT = TmpVT.getVectorElementType();
8116 MVT TmpWidenVT = MVT::getVectorVT(TmpEVT, NewNumElts);
8117 Tmp1 = WidenVectorOp(Tmp1, TmpWidenVT);
8118 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), TmpWidenVT);
8119 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1, Tmp2,
8120 Node->getOperand(2));
8123 case ISD::ATOMIC_CMP_SWAP_8:
8124 case ISD::ATOMIC_CMP_SWAP_16:
8125 case ISD::ATOMIC_CMP_SWAP_32:
8126 case ISD::ATOMIC_CMP_SWAP_64:
8127 case ISD::ATOMIC_LOAD_ADD_8:
8128 case ISD::ATOMIC_LOAD_SUB_8:
8129 case ISD::ATOMIC_LOAD_AND_8:
8130 case ISD::ATOMIC_LOAD_OR_8:
8131 case ISD::ATOMIC_LOAD_XOR_8:
8132 case ISD::ATOMIC_LOAD_NAND_8:
8133 case ISD::ATOMIC_LOAD_MIN_8:
8134 case ISD::ATOMIC_LOAD_MAX_8:
8135 case ISD::ATOMIC_LOAD_UMIN_8:
8136 case ISD::ATOMIC_LOAD_UMAX_8:
8137 case ISD::ATOMIC_SWAP_8:
8138 case ISD::ATOMIC_LOAD_ADD_16:
8139 case ISD::ATOMIC_LOAD_SUB_16:
8140 case ISD::ATOMIC_LOAD_AND_16:
8141 case ISD::ATOMIC_LOAD_OR_16:
8142 case ISD::ATOMIC_LOAD_XOR_16:
8143 case ISD::ATOMIC_LOAD_NAND_16:
8144 case ISD::ATOMIC_LOAD_MIN_16:
8145 case ISD::ATOMIC_LOAD_MAX_16:
8146 case ISD::ATOMIC_LOAD_UMIN_16:
8147 case ISD::ATOMIC_LOAD_UMAX_16:
8148 case ISD::ATOMIC_SWAP_16:
8149 case ISD::ATOMIC_LOAD_ADD_32:
8150 case ISD::ATOMIC_LOAD_SUB_32:
8151 case ISD::ATOMIC_LOAD_AND_32:
8152 case ISD::ATOMIC_LOAD_OR_32:
8153 case ISD::ATOMIC_LOAD_XOR_32:
8154 case ISD::ATOMIC_LOAD_NAND_32:
8155 case ISD::ATOMIC_LOAD_MIN_32:
8156 case ISD::ATOMIC_LOAD_MAX_32:
8157 case ISD::ATOMIC_LOAD_UMIN_32:
8158 case ISD::ATOMIC_LOAD_UMAX_32:
8159 case ISD::ATOMIC_SWAP_32:
8160 case ISD::ATOMIC_LOAD_ADD_64:
8161 case ISD::ATOMIC_LOAD_SUB_64:
8162 case ISD::ATOMIC_LOAD_AND_64:
8163 case ISD::ATOMIC_LOAD_OR_64:
8164 case ISD::ATOMIC_LOAD_XOR_64:
8165 case ISD::ATOMIC_LOAD_NAND_64:
8166 case ISD::ATOMIC_LOAD_MIN_64:
8167 case ISD::ATOMIC_LOAD_MAX_64:
8168 case ISD::ATOMIC_LOAD_UMIN_64:
8169 case ISD::ATOMIC_LOAD_UMAX_64:
8170 case ISD::ATOMIC_SWAP_64: {
8171 // For now, we assume that using vectors for these operations don't make
8172 // much sense so we just split it. We return an empty result
8174 SplitVectorOp(Op, X, Y);
8179 } // end switch (Node->getOpcode())
8181 assert(Result.getNode() && "Didn't set a result!");
8183 Result = LegalizeOp(Result);
8185 AddWidenedOperand(Op, Result);
8189 // Utility function to find a legal vector type and its associated element
8190 // type from a preferred width and whose vector type must be the same size
8192 // TLI: Target lowering used to determine legal types
8193 // Width: Preferred width of element type
8194 // VVT: Vector value type whose size we must match.
8195 // Returns VecEVT and EVT - the vector type and its associated element type
8196 static void FindWidenVecType(TargetLowering &TLI, unsigned Width, MVT VVT,
8197 MVT& EVT, MVT& VecEVT) {
8198 // We start with the preferred width, make it a power of 2 and see if
8199 // we can find a vector type of that width. If not, we reduce it by
8200 // another power of 2. If we have widen the type, a vector of bytes should
8202 assert(TLI.isTypeLegal(VVT));
8203 unsigned EWidth = Width + 1;
8206 EWidth = (1 << Log2_32(EWidth-1));
8207 EVT = MVT::getIntegerVT(EWidth);
8208 unsigned NumEVT = VVT.getSizeInBits()/EWidth;
8209 VecEVT = MVT::getVectorVT(EVT, NumEVT);
8210 } while (!TLI.isTypeLegal(VecEVT) ||
8211 VVT.getSizeInBits() != VecEVT.getSizeInBits());
8214 SDValue SelectionDAGLegalize::genWidenVectorLoads(SDValueVector& LdChain,
8223 // We assume that we have good rules to handle loading power of two loads so
8224 // we break down the operations to power of 2 loads. The strategy is to
8225 // load the largest power of 2 that we can easily transform to a legal vector
8226 // and then insert into that vector, and the cast the result into the legal
8227 // vector that we want. This avoids unnecessary stack converts.
8228 // TODO: If the Ldwidth is legal, alignment is the same as the LdWidth, and
8229 // the load is nonvolatile, we an use a wider load for the value.
8230 // Find a vector length we can load a large chunk
8233 FindWidenVecType(TLI, LdWidth, ResType, EVT, VecEVT);
8234 EVTWidth = EVT.getSizeInBits();
8236 SDValue LdOp = DAG.getLoad(EVT, Chain, BasePtr, SV, SVOffset,
8237 isVolatile, Alignment);
8238 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, VecEVT, LdOp);
8239 LdChain.push_back(LdOp.getValue(1));
8241 // Check if we can load the element with one instruction
8242 if (LdWidth == EVTWidth) {
8243 return DAG.getNode(ISD::BIT_CONVERT, ResType, VecOp);
8246 // The vector element order is endianness dependent.
8248 LdWidth -= EVTWidth;
8249 unsigned Offset = 0;
8251 while (LdWidth > 0) {
8252 unsigned Increment = EVTWidth / 8;
8253 Offset += Increment;
8254 BasePtr = DAG.getNode(ISD::ADD, BasePtr.getValueType(), BasePtr,
8255 DAG.getIntPtrConstant(Increment));
8257 if (LdWidth < EVTWidth) {
8258 // Our current type we are using is too large, use a smaller size by
8259 // using a smaller power of 2
8260 unsigned oEVTWidth = EVTWidth;
8261 FindWidenVecType(TLI, LdWidth, ResType, EVT, VecEVT);
8262 EVTWidth = EVT.getSizeInBits();
8263 // Readjust position and vector position based on new load type
8264 Idx = Idx * (oEVTWidth/EVTWidth);
8265 VecOp = DAG.getNode(ISD::BIT_CONVERT, VecEVT, VecOp);
8268 SDValue LdOp = DAG.getLoad(EVT, Chain, BasePtr, SV,
8269 SVOffset+Offset, isVolatile,
8270 MinAlign(Alignment, Offset));
8271 LdChain.push_back(LdOp.getValue(1));
8272 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, VecEVT, VecOp, LdOp,
8273 DAG.getIntPtrConstant(Idx++));
8275 LdWidth -= EVTWidth;
8278 return DAG.getNode(ISD::BIT_CONVERT, ResType, VecOp);
8281 bool SelectionDAGLegalize::LoadWidenVectorOp(SDValue& Result,
8285 // TODO: Add support for ConcatVec and the ability to load many vector
8286 // types (e.g., v4i8). This will not work when a vector register
8287 // to memory mapping is strange (e.g., vector elements are not
8288 // stored in some sequential order).
8290 // It must be true that the widen vector type is bigger than where
8291 // we need to load from.
8292 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
8293 MVT LdVT = LD->getMemoryVT();
8294 assert(LdVT.isVector() && NVT.isVector());
8295 assert(LdVT.getVectorElementType() == NVT.getVectorElementType());
8298 SDValue Chain = LD->getChain();
8299 SDValue BasePtr = LD->getBasePtr();
8300 int SVOffset = LD->getSrcValueOffset();
8301 unsigned Alignment = LD->getAlignment();
8302 bool isVolatile = LD->isVolatile();
8303 const Value *SV = LD->getSrcValue();
8304 unsigned int LdWidth = LdVT.getSizeInBits();
8306 // Load value as a large register
8307 SDValueVector LdChain;
8308 Result = genWidenVectorLoads(LdChain, Chain, BasePtr, SV, SVOffset,
8309 Alignment, isVolatile, LdWidth, NVT);
8311 if (LdChain.size() == 1) {
8316 TFOp=DAG.getNode(ISD::TokenFactor, MVT::Other, &LdChain[0], LdChain.size());
8322 void SelectionDAGLegalize::genWidenVectorStores(SDValueVector& StChain,
8331 // Breaks the stores into a series of power of 2 width stores. For any
8332 // width, we convert the vector to the vector of element size that we
8333 // want to store. This avoids requiring a stack convert.
8335 // Find a width of the element type we can store with
8336 MVT VVT = ValOp.getValueType();
8339 FindWidenVecType(TLI, StWidth, VVT, EVT, VecEVT);
8340 EVTWidth = EVT.getSizeInBits();
8342 SDValue VecOp = DAG.getNode(ISD::BIT_CONVERT, VecEVT, ValOp);
8343 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EVT, VecOp,
8344 DAG.getIntPtrConstant(0));
8345 SDValue StOp = DAG.getStore(Chain, EOp, BasePtr, SV, SVOffset,
8346 isVolatile, Alignment);
8347 StChain.push_back(StOp);
8349 // Check if we are done
8350 if (StWidth == EVTWidth) {
8355 StWidth -= EVTWidth;
8356 unsigned Offset = 0;
8358 while (StWidth > 0) {
8359 unsigned Increment = EVTWidth / 8;
8360 Offset += Increment;
8361 BasePtr = DAG.getNode(ISD::ADD, BasePtr.getValueType(), BasePtr,
8362 DAG.getIntPtrConstant(Increment));
8364 if (StWidth < EVTWidth) {
8365 // Our current type we are using is too large, use a smaller size by
8366 // using a smaller power of 2
8367 unsigned oEVTWidth = EVTWidth;
8368 FindWidenVecType(TLI, StWidth, VVT, EVT, VecEVT);
8369 EVTWidth = EVT.getSizeInBits();
8370 // Readjust position and vector position based on new load type
8371 Idx = Idx * (oEVTWidth/EVTWidth);
8372 VecOp = DAG.getNode(ISD::BIT_CONVERT, VecEVT, VecOp);
8375 EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EVT, VecOp,
8376 DAG.getIntPtrConstant(Idx++));
8377 StChain.push_back(DAG.getStore(Chain, EOp, BasePtr, SV,
8378 SVOffset + Offset, isVolatile,
8379 MinAlign(Alignment, Offset)));
8380 StWidth -= EVTWidth;
8385 SDValue SelectionDAGLegalize::StoreWidenVectorOp(StoreSDNode *ST,
8388 // TODO: It might be cleaner if we can use SplitVector and have more legal
8389 // vector types that can be stored into memory (e.g., v4xi8 can
8390 // be stored as a word). This will not work when a vector register
8391 // to memory mapping is strange (e.g., vector elements are not
8392 // stored in some sequential order).
8394 MVT StVT = ST->getMemoryVT();
8395 SDValue ValOp = ST->getValue();
8397 // Check if we have widen this node with another value
8398 std::map<SDValue, SDValue>::iterator I = WidenNodes.find(ValOp);
8399 if (I != WidenNodes.end())
8402 MVT VVT = ValOp.getValueType();
8404 // It must be true that we the widen vector type is bigger than where
8405 // we need to store.
8406 assert(StVT.isVector() && VVT.isVector());
8407 assert(StVT.getSizeInBits() < VVT.getSizeInBits());
8408 assert(StVT.getVectorElementType() == VVT.getVectorElementType());
8411 SDValueVector StChain;
8412 genWidenVectorStores(StChain, Chain, BasePtr, ST->getSrcValue(),
8413 ST->getSrcValueOffset(), ST->getAlignment(),
8414 ST->isVolatile(), ValOp, StVT.getSizeInBits());
8415 if (StChain.size() == 1)
8418 return DAG.getNode(ISD::TokenFactor, MVT::Other,&StChain[0],StChain.size());
8422 // SelectionDAG::Legalize - This is the entry point for the file.
8424 void SelectionDAG::Legalize() {
8425 /// run - This is the main entry point to this class.
8427 SelectionDAGLegalize(*this).LegalizeDAG();