1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/CodeGen/DwarfWriter.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/CodeGen/PseudoSourceValue.h"
22 #include "llvm/Target/TargetFrameInfo.h"
23 #include "llvm/Target/TargetLowering.h"
24 #include "llvm/Target/TargetData.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Target/TargetSubtarget.h"
28 #include "llvm/CallingConv.h"
29 #include "llvm/Constants.h"
30 #include "llvm/DerivedTypes.h"
31 #include "llvm/Function.h"
32 #include "llvm/GlobalVariable.h"
33 #include "llvm/LLVMContext.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/ADT/DenseMap.h"
40 #include "llvm/ADT/SmallVector.h"
41 #include "llvm/ADT/SmallPtrSet.h"
45 //===----------------------------------------------------------------------===//
46 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
47 /// hacks on it until the target machine can handle it. This involves
48 /// eliminating value sizes the machine cannot handle (promoting small sizes to
49 /// large sizes or splitting up large values into small values) as well as
50 /// eliminating operations the machine cannot handle.
52 /// This code also does a small amount of optimization and recognition of idioms
53 /// as part of its processing. For example, if a target does not support a
54 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
55 /// will attempt merge setcc and brc instructions into brcc's.
58 class SelectionDAGLegalize {
61 CodeGenOpt::Level OptLevel;
63 // Libcall insertion helpers.
65 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
66 /// legalized. We use this to ensure that calls are properly serialized
67 /// against each other, including inserted libcalls.
68 SDValue LastCALLSEQ_END;
70 /// IsLegalizingCall - This member is used *only* for purposes of providing
71 /// helpful assertions that a libcall isn't created while another call is
72 /// being legalized (which could lead to non-serialized call sequences).
73 bool IsLegalizingCall;
76 Legal, // The target natively supports this operation.
77 Promote, // This operation should be executed in a larger type.
78 Expand // Try to expand this to other ops, otherwise use a libcall.
81 /// ValueTypeActions - This is a bitvector that contains two bits for each
82 /// value type, where the two bits correspond to the LegalizeAction enum.
83 /// This can be queried with "getTypeAction(VT)".
84 TargetLowering::ValueTypeActionImpl ValueTypeActions;
86 /// LegalizedNodes - For nodes that are of legal width, and that have more
87 /// than one use, this map indicates what regularized operand to use. This
88 /// allows us to avoid legalizing the same thing more than once.
89 DenseMap<SDValue, SDValue> LegalizedNodes;
91 void AddLegalizedOperand(SDValue From, SDValue To) {
92 LegalizedNodes.insert(std::make_pair(From, To));
93 // If someone requests legalization of the new node, return itself.
95 LegalizedNodes.insert(std::make_pair(To, To));
99 SelectionDAGLegalize(SelectionDAG &DAG, CodeGenOpt::Level ol);
101 /// getTypeAction - Return how we should legalize values of this type, either
102 /// it is already legal or we need to expand it into multiple registers of
103 /// smaller integer type, or we need to promote it to a larger type.
104 LegalizeAction getTypeAction(EVT VT) const {
106 (LegalizeAction)ValueTypeActions.getTypeAction(*DAG.getContext(), VT);
109 /// isTypeLegal - Return true if this type is legal on this target.
111 bool isTypeLegal(EVT VT) const {
112 return getTypeAction(VT) == Legal;
118 /// LegalizeOp - We know that the specified value has a legal type.
119 /// Recursively ensure that the operands have legal types, then return the
121 SDValue LegalizeOp(SDValue O);
123 SDValue OptimizeFloatStore(StoreSDNode *ST);
125 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
126 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
127 /// is necessary to spill the vector being inserted into to memory, perform
128 /// the insert there, and then read the result back.
129 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
130 SDValue Idx, DebugLoc dl);
131 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
132 SDValue Idx, DebugLoc dl);
134 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
135 /// performs the same shuffe in terms of order or result bytes, but on a type
136 /// whose vector element type is narrower than the original shuffle type.
137 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
138 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
139 SDValue N1, SDValue N2,
140 SmallVectorImpl<int> &Mask) const;
142 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
143 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
145 void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
148 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
149 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
150 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
151 RTLIB::Libcall Call_PPCF128);
152 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
153 RTLIB::Libcall Call_I8,
154 RTLIB::Libcall Call_I16,
155 RTLIB::Libcall Call_I32,
156 RTLIB::Libcall Call_I64,
157 RTLIB::Libcall Call_I128);
159 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl);
160 SDValue ExpandBUILD_VECTOR(SDNode *Node);
161 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
162 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
163 SmallVectorImpl<SDValue> &Results);
164 SDValue ExpandFCOPYSIGN(SDNode *Node);
165 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
167 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
169 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
172 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl);
173 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl);
175 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
176 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
178 void ExpandNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
179 void PromoteNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
183 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
184 /// performs the same shuffe in terms of order or result bytes, but on a type
185 /// whose vector element type is narrower than the original shuffle type.
186 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
188 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
189 SDValue N1, SDValue N2,
190 SmallVectorImpl<int> &Mask) const {
191 unsigned NumMaskElts = VT.getVectorNumElements();
192 unsigned NumDestElts = NVT.getVectorNumElements();
193 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
195 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
197 if (NumEltsGrowth == 1)
198 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
200 SmallVector<int, 8> NewMask;
201 for (unsigned i = 0; i != NumMaskElts; ++i) {
203 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
205 NewMask.push_back(-1);
207 NewMask.push_back(Idx * NumEltsGrowth + j);
210 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
211 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
212 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
215 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag,
216 CodeGenOpt::Level ol)
217 : TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol),
218 ValueTypeActions(TLI.getValueTypeActions()) {
219 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
220 "Too many value types for ValueTypeActions to hold!");
223 void SelectionDAGLegalize::LegalizeDAG() {
224 LastCALLSEQ_END = DAG.getEntryNode();
225 IsLegalizingCall = false;
227 // The legalize process is inherently a bottom-up recursive process (users
228 // legalize their uses before themselves). Given infinite stack space, we
229 // could just start legalizing on the root and traverse the whole graph. In
230 // practice however, this causes us to run out of stack space on large basic
231 // blocks. To avoid this problem, compute an ordering of the nodes where each
232 // node is only legalized after all of its operands are legalized.
233 DAG.AssignTopologicalOrder();
234 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
235 E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I)
236 LegalizeOp(SDValue(I, 0));
238 // Finally, it's possible the root changed. Get the new root.
239 SDValue OldRoot = DAG.getRoot();
240 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
241 DAG.setRoot(LegalizedNodes[OldRoot]);
243 LegalizedNodes.clear();
245 // Remove dead nodes now.
246 DAG.RemoveDeadNodes();
250 /// FindCallEndFromCallStart - Given a chained node that is part of a call
251 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
252 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
253 if (Node->getOpcode() == ISD::CALLSEQ_END)
255 if (Node->use_empty())
256 return 0; // No CallSeqEnd
258 // The chain is usually at the end.
259 SDValue TheChain(Node, Node->getNumValues()-1);
260 if (TheChain.getValueType() != MVT::Other) {
261 // Sometimes it's at the beginning.
262 TheChain = SDValue(Node, 0);
263 if (TheChain.getValueType() != MVT::Other) {
264 // Otherwise, hunt for it.
265 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
266 if (Node->getValueType(i) == MVT::Other) {
267 TheChain = SDValue(Node, i);
271 // Otherwise, we walked into a node without a chain.
272 if (TheChain.getValueType() != MVT::Other)
277 for (SDNode::use_iterator UI = Node->use_begin(),
278 E = Node->use_end(); UI != E; ++UI) {
280 // Make sure to only follow users of our token chain.
282 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
283 if (User->getOperand(i) == TheChain)
284 if (SDNode *Result = FindCallEndFromCallStart(User))
290 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
291 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
292 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
293 assert(Node && "Didn't find callseq_start for a call??");
294 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
296 assert(Node->getOperand(0).getValueType() == MVT::Other &&
297 "Node doesn't have a token chain argument!");
298 return FindCallStartFromCallEnd(Node->getOperand(0).getNode());
301 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
302 /// see if any uses can reach Dest. If no dest operands can get to dest,
303 /// legalize them, legalize ourself, and return false, otherwise, return true.
305 /// Keep track of the nodes we fine that actually do lead to Dest in
306 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
308 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
309 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
310 if (N == Dest) return true; // N certainly leads to Dest :)
312 // If we've already processed this node and it does lead to Dest, there is no
313 // need to reprocess it.
314 if (NodesLeadingTo.count(N)) return true;
316 // If the first result of this node has been already legalized, then it cannot
318 if (LegalizedNodes.count(SDValue(N, 0))) return false;
320 // Okay, this node has not already been legalized. Check and legalize all
321 // operands. If none lead to Dest, then we can legalize this node.
322 bool OperandsLeadToDest = false;
323 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
324 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
325 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo);
327 if (OperandsLeadToDest) {
328 NodesLeadingTo.insert(N);
332 // Okay, this node looks safe, legalize it and return false.
333 LegalizeOp(SDValue(N, 0));
337 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
338 /// a load from the constant pool.
339 static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
340 SelectionDAG &DAG, const TargetLowering &TLI) {
342 DebugLoc dl = CFP->getDebugLoc();
344 // If a FP immediate is precise when represented as a float and if the
345 // target can do an extending load from float to double, we put it into
346 // the constant pool as a float, even if it's is statically typed as a
347 // double. This shrinks FP constants and canonicalizes them for targets where
348 // an FP extending load is the same cost as a normal load (such as on the x87
349 // fp stack or PPC FP unit).
350 EVT VT = CFP->getValueType(0);
351 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
353 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
354 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
355 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
360 while (SVT != MVT::f32) {
361 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
362 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
363 // Only do this if the target has a native EXTLOAD instruction from
365 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
366 TLI.ShouldShrinkFPConstant(OrigVT)) {
367 const Type *SType = SVT.getTypeForEVT(*DAG.getContext());
368 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
374 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
375 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
377 return DAG.getExtLoad(ISD::EXTLOAD, dl,
378 OrigVT, DAG.getEntryNode(),
379 CPIdx, PseudoSourceValue::getConstantPool(),
380 0, VT, false, Alignment);
381 return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
382 PseudoSourceValue::getConstantPool(), 0, false, Alignment);
385 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
387 SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
388 const TargetLowering &TLI) {
389 SDValue Chain = ST->getChain();
390 SDValue Ptr = ST->getBasePtr();
391 SDValue Val = ST->getValue();
392 EVT VT = Val.getValueType();
393 int Alignment = ST->getAlignment();
394 int SVOffset = ST->getSrcValueOffset();
395 DebugLoc dl = ST->getDebugLoc();
396 if (ST->getMemoryVT().isFloatingPoint() ||
397 ST->getMemoryVT().isVector()) {
398 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
399 if (TLI.isTypeLegal(intVT)) {
400 // Expand to a bitconvert of the value to the integer type of the
401 // same size, then a (misaligned) int store.
402 // FIXME: Does not handle truncating floating point stores!
403 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, intVT, Val);
404 return DAG.getStore(Chain, dl, Result, Ptr, ST->getSrcValue(),
405 SVOffset, ST->isVolatile(), Alignment);
407 // Do a (aligned) store to a stack slot, then copy from the stack slot
408 // to the final destination using (unaligned) integer loads and stores.
409 EVT StoredVT = ST->getMemoryVT();
411 TLI.getRegisterType(*DAG.getContext(), EVT::getIntegerVT(*DAG.getContext(), StoredVT.getSizeInBits()));
412 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
413 unsigned RegBytes = RegVT.getSizeInBits() / 8;
414 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
416 // Make sure the stack slot is also aligned for the register type.
417 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
419 // Perform the original store, only redirected to the stack slot.
420 SDValue Store = DAG.getTruncStore(Chain, dl,
421 Val, StackPtr, NULL, 0, StoredVT);
422 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
423 SmallVector<SDValue, 8> Stores;
426 // Do all but one copies using the full register width.
427 for (unsigned i = 1; i < NumRegs; i++) {
428 // Load one integer register's worth from the stack slot.
429 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, NULL, 0);
430 // Store it to the final location. Remember the store.
431 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
432 ST->getSrcValue(), SVOffset + Offset,
434 MinAlign(ST->getAlignment(), Offset)));
435 // Increment the pointers.
437 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
439 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
442 // The last store may be partial. Do a truncating store. On big-endian
443 // machines this requires an extending load from the stack slot to ensure
444 // that the bits are in the right place.
445 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), 8 * (StoredBytes - Offset));
447 // Load from the stack slot.
448 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
451 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
452 ST->getSrcValue(), SVOffset + Offset,
453 MemVT, ST->isVolatile(),
454 MinAlign(ST->getAlignment(), Offset)));
455 // The order of the stores doesn't matter - say it with a TokenFactor.
456 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
460 assert(ST->getMemoryVT().isInteger() &&
461 !ST->getMemoryVT().isVector() &&
462 "Unaligned store of unknown type.");
463 // Get the half-size VT
464 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext());
465 int NumBits = NewStoredVT.getSizeInBits();
466 int IncrementSize = NumBits / 8;
468 // Divide the stored value in two parts.
469 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
471 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
473 // Store the two parts
474 SDValue Store1, Store2;
475 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
476 ST->getSrcValue(), SVOffset, NewStoredVT,
477 ST->isVolatile(), Alignment);
478 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
479 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
480 Alignment = MinAlign(Alignment, IncrementSize);
481 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
482 ST->getSrcValue(), SVOffset + IncrementSize,
483 NewStoredVT, ST->isVolatile(), Alignment);
485 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
488 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
490 SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
491 const TargetLowering &TLI) {
492 int SVOffset = LD->getSrcValueOffset();
493 SDValue Chain = LD->getChain();
494 SDValue Ptr = LD->getBasePtr();
495 EVT VT = LD->getValueType(0);
496 EVT LoadedVT = LD->getMemoryVT();
497 DebugLoc dl = LD->getDebugLoc();
498 if (VT.isFloatingPoint() || VT.isVector()) {
499 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
500 if (TLI.isTypeLegal(intVT)) {
501 // Expand to a (misaligned) integer load of the same size,
502 // then bitconvert to floating point or vector.
503 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getSrcValue(),
504 SVOffset, LD->isVolatile(),
506 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, LoadedVT, newLoad);
507 if (VT.isFloatingPoint() && LoadedVT != VT)
508 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result);
510 SDValue Ops[] = { Result, Chain };
511 return DAG.getMergeValues(Ops, 2, dl);
513 // Copy the value to a (aligned) stack slot using (unaligned) integer
514 // loads and stores, then do a (aligned) load from the stack slot.
515 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
516 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
517 unsigned RegBytes = RegVT.getSizeInBits() / 8;
518 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
520 // Make sure the stack slot is also aligned for the register type.
521 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
523 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
524 SmallVector<SDValue, 8> Stores;
525 SDValue StackPtr = StackBase;
528 // Do all but one copies using the full register width.
529 for (unsigned i = 1; i < NumRegs; i++) {
530 // Load one integer register's worth from the original location.
531 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, LD->getSrcValue(),
532 SVOffset + Offset, LD->isVolatile(),
533 MinAlign(LD->getAlignment(), Offset));
534 // Follow the load with a store to the stack slot. Remember the store.
535 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
537 // Increment the pointers.
539 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
540 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
544 // The last copy may be partial. Do an extending load.
545 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), 8 * (LoadedBytes - Offset));
546 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
547 LD->getSrcValue(), SVOffset + Offset,
548 MemVT, LD->isVolatile(),
549 MinAlign(LD->getAlignment(), Offset));
550 // Follow the load with a store to the stack slot. Remember the store.
551 // On big-endian machines this requires a truncating store to ensure
552 // that the bits end up in the right place.
553 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
556 // The order of the stores doesn't matter - say it with a TokenFactor.
557 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
560 // Finally, perform the original load only redirected to the stack slot.
561 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
564 // Callers expect a MERGE_VALUES node.
565 SDValue Ops[] = { Load, TF };
566 return DAG.getMergeValues(Ops, 2, dl);
569 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
570 "Unaligned load of unsupported type.");
572 // Compute the new VT that is half the size of the old one. This is an
574 unsigned NumBits = LoadedVT.getSizeInBits();
576 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
579 unsigned Alignment = LD->getAlignment();
580 unsigned IncrementSize = NumBits / 8;
581 ISD::LoadExtType HiExtType = LD->getExtensionType();
583 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
584 if (HiExtType == ISD::NON_EXTLOAD)
585 HiExtType = ISD::ZEXTLOAD;
587 // Load the value in two parts
589 if (TLI.isLittleEndian()) {
590 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(),
591 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
592 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
593 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
594 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(),
595 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
596 MinAlign(Alignment, IncrementSize));
598 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(),
599 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
600 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
601 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
602 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(),
603 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
604 MinAlign(Alignment, IncrementSize));
607 // aggregate the two parts
608 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
609 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
610 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
612 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
615 SDValue Ops[] = { Result, TF };
616 return DAG.getMergeValues(Ops, 2, dl);
619 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
620 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
621 /// is necessary to spill the vector being inserted into to memory, perform
622 /// the insert there, and then read the result back.
623 SDValue SelectionDAGLegalize::
624 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
630 // If the target doesn't support this, we have to spill the input vector
631 // to a temporary stack slot, update the element, then reload it. This is
632 // badness. We could also load the value into a vector register (either
633 // with a "move to register" or "extload into register" instruction, then
634 // permute it into place, if the idx is a constant and if the idx is
635 // supported by the target.
636 EVT VT = Tmp1.getValueType();
637 EVT EltVT = VT.getVectorElementType();
638 EVT IdxVT = Tmp3.getValueType();
639 EVT PtrVT = TLI.getPointerTy();
640 SDValue StackPtr = DAG.CreateStackTemporary(VT);
642 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
645 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
646 PseudoSourceValue::getFixedStack(SPFI), 0);
648 // Truncate or zero extend offset to target pointer type.
649 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
650 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
651 // Add the offset to the index.
652 unsigned EltSize = EltVT.getSizeInBits()/8;
653 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
654 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
655 // Store the scalar value.
656 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2,
657 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT);
658 // Load the updated vector.
659 return DAG.getLoad(VT, dl, Ch, StackPtr,
660 PseudoSourceValue::getFixedStack(SPFI), 0);
664 SDValue SelectionDAGLegalize::
665 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) {
666 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
667 // SCALAR_TO_VECTOR requires that the type of the value being inserted
668 // match the element type of the vector being created, except for
669 // integers in which case the inserted value can be over width.
670 EVT EltVT = Vec.getValueType().getVectorElementType();
671 if (Val.getValueType() == EltVT ||
672 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
673 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
674 Vec.getValueType(), Val);
676 unsigned NumElts = Vec.getValueType().getVectorNumElements();
677 // We generate a shuffle of InVec and ScVec, so the shuffle mask
678 // should be 0,1,2,3,4,5... with the appropriate element replaced with
680 SmallVector<int, 8> ShufOps;
681 for (unsigned i = 0; i != NumElts; ++i)
682 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
684 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
688 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
691 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
692 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
693 // FIXME: We shouldn't do this for TargetConstantFP's.
694 // FIXME: move this to the DAG Combiner! Note that we can't regress due
695 // to phase ordering between legalized code and the dag combiner. This
696 // probably means that we need to integrate dag combiner and legalizer
698 // We generally can't do this one for long doubles.
699 SDValue Tmp1 = ST->getChain();
700 SDValue Tmp2 = ST->getBasePtr();
702 int SVOffset = ST->getSrcValueOffset();
703 unsigned Alignment = ST->getAlignment();
704 bool isVolatile = ST->isVolatile();
705 DebugLoc dl = ST->getDebugLoc();
706 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
707 if (CFP->getValueType(0) == MVT::f32 &&
708 getTypeAction(MVT::i32) == Legal) {
709 Tmp3 = DAG.getConstant(CFP->getValueAPF().
710 bitcastToAPInt().zextOrTrunc(32),
712 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
713 SVOffset, isVolatile, Alignment);
714 } else if (CFP->getValueType(0) == MVT::f64) {
715 // If this target supports 64-bit registers, do a single 64-bit store.
716 if (getTypeAction(MVT::i64) == Legal) {
717 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
718 zextOrTrunc(64), MVT::i64);
719 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
720 SVOffset, isVolatile, Alignment);
721 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
722 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
723 // stores. If the target supports neither 32- nor 64-bits, this
724 // xform is certainly not worth it.
725 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
726 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
727 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
728 if (TLI.isBigEndian()) std::swap(Lo, Hi);
730 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(),
731 SVOffset, isVolatile, Alignment);
732 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
733 DAG.getIntPtrConstant(4));
734 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
735 isVolatile, MinAlign(Alignment, 4U));
737 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
744 /// LegalizeOp - We know that the specified value has a legal type, and
745 /// that its operands are legal. Now ensure that the operation itself
746 /// is legal, recursively ensuring that the operands' operations remain
748 SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
749 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
752 SDNode *Node = Op.getNode();
753 DebugLoc dl = Node->getDebugLoc();
755 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
756 assert(getTypeAction(Node->getValueType(i)) == Legal &&
757 "Unexpected illegal type!");
759 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
760 assert((isTypeLegal(Node->getOperand(i).getValueType()) ||
761 Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
762 "Unexpected illegal type!");
764 // Note that LegalizeOp may be reentered even from single-use nodes, which
765 // means that we always must cache transformed nodes.
766 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
767 if (I != LegalizedNodes.end()) return I->second;
769 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
771 bool isCustom = false;
773 // Figure out the correct action; the way to query this varies by opcode
774 TargetLowering::LegalizeAction Action;
775 bool SimpleFinishLegalizing = true;
776 switch (Node->getOpcode()) {
777 case ISD::INTRINSIC_W_CHAIN:
778 case ISD::INTRINSIC_WO_CHAIN:
779 case ISD::INTRINSIC_VOID:
782 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
784 case ISD::SINT_TO_FP:
785 case ISD::UINT_TO_FP:
786 case ISD::EXTRACT_VECTOR_ELT:
787 Action = TLI.getOperationAction(Node->getOpcode(),
788 Node->getOperand(0).getValueType());
790 case ISD::FP_ROUND_INREG:
791 case ISD::SIGN_EXTEND_INREG: {
792 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
793 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
799 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
800 Node->getOpcode() == ISD::SETCC ? 2 : 1;
801 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
802 EVT OpVT = Node->getOperand(CompareOperand).getValueType();
803 ISD::CondCode CCCode =
804 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
805 Action = TLI.getCondCodeAction(CCCode, OpVT);
806 if (Action == TargetLowering::Legal) {
807 if (Node->getOpcode() == ISD::SELECT_CC)
808 Action = TLI.getOperationAction(Node->getOpcode(),
809 Node->getValueType(0));
811 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
817 // FIXME: Model these properly. LOAD and STORE are complicated, and
818 // STORE expects the unlegalized operand in some cases.
819 SimpleFinishLegalizing = false;
821 case ISD::CALLSEQ_START:
822 case ISD::CALLSEQ_END:
823 // FIXME: This shouldn't be necessary. These nodes have special properties
824 // dealing with the recursive nature of legalization. Removing this
825 // special case should be done as part of making LegalizeDAG non-recursive.
826 SimpleFinishLegalizing = false;
828 case ISD::EXTRACT_ELEMENT:
829 case ISD::FLT_ROUNDS_:
837 case ISD::MERGE_VALUES:
839 case ISD::FRAME_TO_ARGS_OFFSET:
840 // These operations lie about being legal: when they claim to be legal,
841 // they should actually be expanded.
842 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
843 if (Action == TargetLowering::Legal)
844 Action = TargetLowering::Expand;
846 case ISD::TRAMPOLINE:
848 case ISD::RETURNADDR:
849 // These operations lie about being legal: when they claim to be legal,
850 // they should actually be custom-lowered.
851 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
852 if (Action == TargetLowering::Legal)
853 Action = TargetLowering::Custom;
855 case ISD::BUILD_VECTOR:
856 // A weird case: legalization for BUILD_VECTOR never legalizes the
858 // FIXME: This really sucks... changing it isn't semantically incorrect,
859 // but it massively pessimizes the code for floating-point BUILD_VECTORs
860 // because ConstantFP operands get legalized into constant pool loads
861 // before the BUILD_VECTOR code can see them. It doesn't usually bite,
862 // though, because BUILD_VECTORS usually get lowered into other nodes
863 // which get legalized properly.
864 SimpleFinishLegalizing = false;
867 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
868 Action = TargetLowering::Legal;
870 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
875 if (SimpleFinishLegalizing) {
876 SmallVector<SDValue, 8> Ops, ResultVals;
877 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
878 Ops.push_back(LegalizeOp(Node->getOperand(i)));
879 switch (Node->getOpcode()) {
886 // Branches tweak the chain to include LastCALLSEQ_END
887 Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0],
889 Ops[0] = LegalizeOp(Ops[0]);
890 LastCALLSEQ_END = DAG.getEntryNode();
897 // Legalizing shifts/rotates requires adjusting the shift amount
898 // to the appropriate width.
899 if (!Ops[1].getValueType().isVector())
900 Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[1]));
905 // Legalizing shifts/rotates requires adjusting the shift amount
906 // to the appropriate width.
907 if (!Ops[2].getValueType().isVector())
908 Ops[2] = LegalizeOp(DAG.getShiftAmountOperand(Ops[2]));
912 Result = DAG.UpdateNodeOperands(Result.getValue(0), Ops.data(),
915 case TargetLowering::Legal:
916 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
917 ResultVals.push_back(Result.getValue(i));
919 case TargetLowering::Custom:
920 // FIXME: The handling for custom lowering with multiple results is
922 Tmp1 = TLI.LowerOperation(Result, DAG);
923 if (Tmp1.getNode()) {
924 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
926 ResultVals.push_back(Tmp1);
928 ResultVals.push_back(Tmp1.getValue(i));
934 case TargetLowering::Expand:
935 ExpandNode(Result.getNode(), ResultVals);
937 case TargetLowering::Promote:
938 PromoteNode(Result.getNode(), ResultVals);
941 if (!ResultVals.empty()) {
942 for (unsigned i = 0, e = ResultVals.size(); i != e; ++i) {
943 if (ResultVals[i] != SDValue(Node, i))
944 ResultVals[i] = LegalizeOp(ResultVals[i]);
945 AddLegalizedOperand(SDValue(Node, i), ResultVals[i]);
947 return ResultVals[Op.getResNo()];
951 switch (Node->getOpcode()) {
958 llvm_unreachable("Do not know how to legalize this operator!");
960 case ISD::BUILD_VECTOR:
961 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
962 default: llvm_unreachable("This action is not supported yet!");
963 case TargetLowering::Custom:
964 Tmp3 = TLI.LowerOperation(Result, DAG);
965 if (Tmp3.getNode()) {
970 case TargetLowering::Expand:
971 Result = ExpandBUILD_VECTOR(Result.getNode());
975 case ISD::CALLSEQ_START: {
976 SDNode *CallEnd = FindCallEndFromCallStart(Node);
978 // Recursively Legalize all of the inputs of the call end that do not lead
979 // to this call start. This ensures that any libcalls that need be inserted
980 // are inserted *before* the CALLSEQ_START.
981 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
982 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
983 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
987 // Now that we legalized all of the inputs (which may have inserted
988 // libcalls) create the new CALLSEQ_START node.
989 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
991 // Merge in the last call, to ensure that this call start after the last
993 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
994 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
995 Tmp1, LastCALLSEQ_END);
996 Tmp1 = LegalizeOp(Tmp1);
999 // Do not try to legalize the target-specific arguments (#1+).
1000 if (Tmp1 != Node->getOperand(0)) {
1001 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1003 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1006 // Remember that the CALLSEQ_START is legalized.
1007 AddLegalizedOperand(Op.getValue(0), Result);
1008 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1009 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1011 // Now that the callseq_start and all of the non-call nodes above this call
1012 // sequence have been legalized, legalize the call itself. During this
1013 // process, no libcalls can/will be inserted, guaranteeing that no calls
1015 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1016 // Note that we are selecting this call!
1017 LastCALLSEQ_END = SDValue(CallEnd, 0);
1018 IsLegalizingCall = true;
1020 // Legalize the call, starting from the CALLSEQ_END.
1021 LegalizeOp(LastCALLSEQ_END);
1022 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1025 case ISD::CALLSEQ_END:
1026 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1027 // will cause this node to be legalized as well as handling libcalls right.
1028 if (LastCALLSEQ_END.getNode() != Node) {
1029 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
1030 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1031 assert(I != LegalizedNodes.end() &&
1032 "Legalizing the call start should have legalized this node!");
1036 // Otherwise, the call start has been legalized and everything is going
1037 // according to plan. Just legalize ourselves normally here.
1038 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1039 // Do not try to legalize the target-specific arguments (#1+), except for
1040 // an optional flag input.
1041 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1042 if (Tmp1 != Node->getOperand(0)) {
1043 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1045 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1048 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1049 if (Tmp1 != Node->getOperand(0) ||
1050 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1051 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1054 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1057 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1058 // This finishes up call legalization.
1059 IsLegalizingCall = false;
1061 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1062 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1063 if (Node->getNumValues() == 2)
1064 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1065 return Result.getValue(Op.getResNo());
1067 LoadSDNode *LD = cast<LoadSDNode>(Node);
1068 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1069 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1071 ISD::LoadExtType ExtType = LD->getExtensionType();
1072 if (ExtType == ISD::NON_EXTLOAD) {
1073 EVT VT = Node->getValueType(0);
1074 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1075 Tmp3 = Result.getValue(0);
1076 Tmp4 = Result.getValue(1);
1078 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1079 default: llvm_unreachable("This action is not supported yet!");
1080 case TargetLowering::Legal:
1081 // If this is an unaligned load and the target doesn't support it,
1083 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
1084 const Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1085 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
1086 if (LD->getAlignment() < ABIAlignment){
1087 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
1089 Tmp3 = Result.getOperand(0);
1090 Tmp4 = Result.getOperand(1);
1091 Tmp3 = LegalizeOp(Tmp3);
1092 Tmp4 = LegalizeOp(Tmp4);
1096 case TargetLowering::Custom:
1097 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1098 if (Tmp1.getNode()) {
1099 Tmp3 = LegalizeOp(Tmp1);
1100 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1103 case TargetLowering::Promote: {
1104 // Only promote a load of vector type to another.
1105 assert(VT.isVector() && "Cannot promote this load!");
1106 // Change base type to a different vector type.
1107 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1109 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
1110 LD->getSrcValueOffset(),
1111 LD->isVolatile(), LD->getAlignment());
1112 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp1));
1113 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1117 // Since loads produce two values, make sure to remember that we
1118 // legalized both of them.
1119 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
1120 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
1121 return Op.getResNo() ? Tmp4 : Tmp3;
1123 EVT SrcVT = LD->getMemoryVT();
1124 unsigned SrcWidth = SrcVT.getSizeInBits();
1125 int SVOffset = LD->getSrcValueOffset();
1126 unsigned Alignment = LD->getAlignment();
1127 bool isVolatile = LD->isVolatile();
1129 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
1130 // Some targets pretend to have an i1 loading operation, and actually
1131 // load an i8. This trick is correct for ZEXTLOAD because the top 7
1132 // bits are guaranteed to be zero; it helps the optimizers understand
1133 // that these bits are zero. It is also useful for EXTLOAD, since it
1134 // tells the optimizers that those bits are undefined. It would be
1135 // nice to have an effective generic way of getting these benefits...
1136 // Until such a way is found, don't insist on promoting i1 here.
1137 (SrcVT != MVT::i1 ||
1138 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
1139 // Promote to a byte-sized load if not loading an integral number of
1140 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
1141 unsigned NewWidth = SrcVT.getStoreSizeInBits();
1142 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
1145 // The extra bits are guaranteed to be zero, since we stored them that
1146 // way. A zext load from NVT thus automatically gives zext from SrcVT.
1148 ISD::LoadExtType NewExtType =
1149 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
1151 Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
1152 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
1153 NVT, isVolatile, Alignment);
1155 Ch = Result.getValue(1); // The chain.
1157 if (ExtType == ISD::SEXTLOAD)
1158 // Having the top bits zero doesn't help when sign extending.
1159 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1160 Result.getValueType(),
1161 Result, DAG.getValueType(SrcVT));
1162 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
1163 // All the top bits are guaranteed to be zero - inform the optimizers.
1164 Result = DAG.getNode(ISD::AssertZext, dl,
1165 Result.getValueType(), Result,
1166 DAG.getValueType(SrcVT));
1168 Tmp1 = LegalizeOp(Result);
1169 Tmp2 = LegalizeOp(Ch);
1170 } else if (SrcWidth & (SrcWidth - 1)) {
1171 // If not loading a power-of-2 number of bits, expand as two loads.
1172 assert(!SrcVT.isVector() && "Unsupported extload!");
1173 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
1174 assert(RoundWidth < SrcWidth);
1175 unsigned ExtraWidth = SrcWidth - RoundWidth;
1176 assert(ExtraWidth < RoundWidth);
1177 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1178 "Load size not an integral number of bytes!");
1179 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
1180 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
1182 unsigned IncrementSize;
1184 if (TLI.isLittleEndian()) {
1185 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1186 // Load the bottom RoundWidth bits.
1187 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl,
1188 Node->getValueType(0), Tmp1, Tmp2,
1189 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
1192 // Load the remaining ExtraWidth bits.
1193 IncrementSize = RoundWidth / 8;
1194 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1195 DAG.getIntPtrConstant(IncrementSize));
1196 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
1197 LD->getSrcValue(), SVOffset + IncrementSize,
1198 ExtraVT, isVolatile,
1199 MinAlign(Alignment, IncrementSize));
1201 // Build a factor node to remember that this load is independent of the
1203 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1206 // Move the top bits to the right place.
1207 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1208 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
1210 // Join the hi and lo parts.
1211 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1213 // Big endian - avoid unaligned loads.
1214 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1215 // Load the top RoundWidth bits.
1216 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
1217 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
1220 // Load the remaining ExtraWidth bits.
1221 IncrementSize = RoundWidth / 8;
1222 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1223 DAG.getIntPtrConstant(IncrementSize));
1224 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl,
1225 Node->getValueType(0), Tmp1, Tmp2,
1226 LD->getSrcValue(), SVOffset + IncrementSize,
1227 ExtraVT, isVolatile,
1228 MinAlign(Alignment, IncrementSize));
1230 // Build a factor node to remember that this load is independent of the
1232 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1235 // Move the top bits to the right place.
1236 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1237 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
1239 // Join the hi and lo parts.
1240 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1243 Tmp1 = LegalizeOp(Result);
1244 Tmp2 = LegalizeOp(Ch);
1246 switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
1247 default: llvm_unreachable("This action is not supported yet!");
1248 case TargetLowering::Custom:
1251 case TargetLowering::Legal:
1252 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1253 Tmp1 = Result.getValue(0);
1254 Tmp2 = Result.getValue(1);
1257 Tmp3 = TLI.LowerOperation(Result, DAG);
1258 if (Tmp3.getNode()) {
1259 Tmp1 = LegalizeOp(Tmp3);
1260 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1263 // If this is an unaligned load and the target doesn't support it,
1265 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
1266 const Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1267 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
1268 if (LD->getAlignment() < ABIAlignment){
1269 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
1271 Tmp1 = Result.getOperand(0);
1272 Tmp2 = Result.getOperand(1);
1273 Tmp1 = LegalizeOp(Tmp1);
1274 Tmp2 = LegalizeOp(Tmp2);
1279 case TargetLowering::Expand:
1280 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1281 // f128 = EXTLOAD {f32,f64} too
1282 if ((SrcVT == MVT::f32 && (Node->getValueType(0) == MVT::f64 ||
1283 Node->getValueType(0) == MVT::f128)) ||
1284 (SrcVT == MVT::f64 && Node->getValueType(0) == MVT::f128)) {
1285 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
1286 LD->getSrcValueOffset(),
1287 LD->isVolatile(), LD->getAlignment());
1288 Result = DAG.getNode(ISD::FP_EXTEND, dl,
1289 Node->getValueType(0), Load);
1290 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1291 Tmp2 = LegalizeOp(Load.getValue(1));
1294 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
1295 // Turn the unsupported load into an EXTLOAD followed by an explicit
1296 // zero/sign extend inreg.
1297 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
1298 Tmp1, Tmp2, LD->getSrcValue(),
1299 LD->getSrcValueOffset(), SrcVT,
1300 LD->isVolatile(), LD->getAlignment());
1302 if (ExtType == ISD::SEXTLOAD)
1303 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1304 Result.getValueType(),
1305 Result, DAG.getValueType(SrcVT));
1307 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT);
1308 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1309 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1314 // Since loads produce two values, make sure to remember that we legalized
1316 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
1317 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
1318 return Op.getResNo() ? Tmp2 : Tmp1;
1322 StoreSDNode *ST = cast<StoreSDNode>(Node);
1323 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
1324 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
1325 int SVOffset = ST->getSrcValueOffset();
1326 unsigned Alignment = ST->getAlignment();
1327 bool isVolatile = ST->isVolatile();
1329 if (!ST->isTruncatingStore()) {
1330 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
1331 Result = SDValue(OptStore, 0);
1336 Tmp3 = LegalizeOp(ST->getValue());
1337 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1340 EVT VT = Tmp3.getValueType();
1341 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1342 default: llvm_unreachable("This action is not supported yet!");
1343 case TargetLowering::Legal:
1344 // If this is an unaligned store and the target doesn't support it,
1346 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
1347 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
1348 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
1349 if (ST->getAlignment() < ABIAlignment)
1350 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()),
1354 case TargetLowering::Custom:
1355 Tmp1 = TLI.LowerOperation(Result, DAG);
1356 if (Tmp1.getNode()) Result = Tmp1;
1358 case TargetLowering::Promote:
1359 assert(VT.isVector() && "Unknown legal promote case!");
1360 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, dl,
1361 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
1362 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2,
1363 ST->getSrcValue(), SVOffset, isVolatile,
1370 Tmp3 = LegalizeOp(ST->getValue());
1372 EVT StVT = ST->getMemoryVT();
1373 unsigned StWidth = StVT.getSizeInBits();
1375 if (StWidth != StVT.getStoreSizeInBits()) {
1376 // Promote to a byte-sized store with upper bits zero if not
1377 // storing an integral number of bytes. For example, promote
1378 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
1379 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), StVT.getStoreSizeInBits());
1380 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT);
1381 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1382 SVOffset, NVT, isVolatile, Alignment);
1383 } else if (StWidth & (StWidth - 1)) {
1384 // If not storing a power-of-2 number of bits, expand as two stores.
1385 assert(!StVT.isVector() && "Unsupported truncstore!");
1386 unsigned RoundWidth = 1 << Log2_32(StWidth);
1387 assert(RoundWidth < StWidth);
1388 unsigned ExtraWidth = StWidth - RoundWidth;
1389 assert(ExtraWidth < RoundWidth);
1390 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1391 "Store size not an integral number of bytes!");
1392 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
1393 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
1395 unsigned IncrementSize;
1397 if (TLI.isLittleEndian()) {
1398 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
1399 // Store the bottom RoundWidth bits.
1400 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1402 isVolatile, Alignment);
1404 // Store the remaining ExtraWidth bits.
1405 IncrementSize = RoundWidth / 8;
1406 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1407 DAG.getIntPtrConstant(IncrementSize));
1408 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
1409 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
1410 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
1411 SVOffset + IncrementSize, ExtraVT, isVolatile,
1412 MinAlign(Alignment, IncrementSize));
1414 // Big endian - avoid unaligned stores.
1415 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
1416 // Store the top RoundWidth bits.
1417 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
1418 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
1419 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
1420 SVOffset, RoundVT, isVolatile, Alignment);
1422 // Store the remaining ExtraWidth bits.
1423 IncrementSize = RoundWidth / 8;
1424 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1425 DAG.getIntPtrConstant(IncrementSize));
1426 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1427 SVOffset + IncrementSize, ExtraVT, isVolatile,
1428 MinAlign(Alignment, IncrementSize));
1431 // The order of the stores doesn't matter.
1432 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
1434 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
1435 Tmp2 != ST->getBasePtr())
1436 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1439 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
1440 default: llvm_unreachable("This action is not supported yet!");
1441 case TargetLowering::Legal:
1442 // If this is an unaligned store and the target doesn't support it,
1444 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
1445 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
1446 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
1447 if (ST->getAlignment() < ABIAlignment)
1448 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()),
1452 case TargetLowering::Custom:
1453 Result = TLI.LowerOperation(Result, DAG);
1456 // TRUNCSTORE:i16 i32 -> STORE i16
1457 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
1458 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3);
1459 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1460 SVOffset, isVolatile, Alignment);
1468 assert(Result.getValueType() == Op.getValueType() &&
1469 "Bad legalization!");
1471 // Make sure that the generated code is itself legal.
1473 Result = LegalizeOp(Result);
1475 // Note that LegalizeOp may be reentered even from single-use nodes, which
1476 // means that we always must cache transformed nodes.
1477 AddLegalizedOperand(Op, Result);
1481 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1482 SDValue Vec = Op.getOperand(0);
1483 SDValue Idx = Op.getOperand(1);
1484 DebugLoc dl = Op.getDebugLoc();
1485 // Store the value to a temporary stack slot, then LOAD the returned part.
1486 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1487 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0);
1489 // Add the offset to the index.
1491 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1492 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1493 DAG.getConstant(EltSize, Idx.getValueType()));
1495 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1496 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1498 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1500 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1502 if (Op.getValueType().isVector())
1503 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, NULL, 0);
1505 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
1506 NULL, 0, Vec.getValueType().getVectorElementType());
1509 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1510 // We can't handle this case efficiently. Allocate a sufficiently
1511 // aligned object on the stack, store each element into it, then load
1512 // the result as a vector.
1513 // Create the stack frame object.
1514 EVT VT = Node->getValueType(0);
1515 EVT OpVT = Node->getOperand(0).getValueType();
1516 EVT EltVT = VT.getVectorElementType();
1517 DebugLoc dl = Node->getDebugLoc();
1518 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1519 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1520 const Value *SV = PseudoSourceValue::getFixedStack(FI);
1522 // Emit a store of each element to the stack slot.
1523 SmallVector<SDValue, 8> Stores;
1524 unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1525 // Store (in the right endianness) the elements to memory.
1526 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1527 // Ignore undef elements.
1528 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1530 unsigned Offset = TypeByteSize*i;
1532 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
1533 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1535 // If EltVT smaller than OpVT, only store the bits necessary.
1536 if (EltVT.bitsLT(OpVT))
1537 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1538 Node->getOperand(i), Idx, SV, Offset, EltVT));
1540 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
1541 Node->getOperand(i), Idx, SV, Offset));
1545 if (!Stores.empty()) // Not all undef elements?
1546 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1547 &Stores[0], Stores.size());
1549 StoreChain = DAG.getEntryNode();
1551 // Result is a load from the stack slot.
1552 return DAG.getLoad(VT, dl, StoreChain, FIPtr, SV, 0);
1555 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
1556 DebugLoc dl = Node->getDebugLoc();
1557 SDValue Tmp1 = Node->getOperand(0);
1558 SDValue Tmp2 = Node->getOperand(1);
1559 assert((Tmp2.getValueType() == MVT::f32 ||
1560 Tmp2.getValueType() == MVT::f64) &&
1561 "Ugly special-cased code!");
1562 // Get the sign bit of the RHS.
1564 EVT IVT = Tmp2.getValueType() == MVT::f64 ? MVT::i64 : MVT::i32;
1565 if (isTypeLegal(IVT)) {
1566 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, IVT, Tmp2);
1568 assert(isTypeLegal(TLI.getPointerTy()) &&
1569 (TLI.getPointerTy() == MVT::i32 ||
1570 TLI.getPointerTy() == MVT::i64) &&
1571 "Legal type for load?!");
1572 SDValue StackPtr = DAG.CreateStackTemporary(Tmp2.getValueType());
1573 SDValue StorePtr = StackPtr, LoadPtr = StackPtr;
1575 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StorePtr, NULL, 0);
1576 if (Tmp2.getValueType() == MVT::f64 && TLI.isLittleEndian())
1577 LoadPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(),
1578 LoadPtr, DAG.getIntPtrConstant(4));
1579 SignBit = DAG.getExtLoad(ISD::SEXTLOAD, dl, TLI.getPointerTy(),
1580 Ch, LoadPtr, NULL, 0, MVT::i32);
1583 DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()),
1584 SignBit, DAG.getConstant(0, SignBit.getValueType()),
1586 // Get the absolute value of the result.
1587 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1588 // Select between the nabs and abs value based on the sign bit of
1590 return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit,
1591 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1595 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1596 SmallVectorImpl<SDValue> &Results) {
1597 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1598 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1599 " not tell us which reg is the stack pointer!");
1600 DebugLoc dl = Node->getDebugLoc();
1601 EVT VT = Node->getValueType(0);
1602 SDValue Tmp1 = SDValue(Node, 0);
1603 SDValue Tmp2 = SDValue(Node, 1);
1604 SDValue Tmp3 = Node->getOperand(2);
1605 SDValue Chain = Tmp1.getOperand(0);
1607 // Chain the dynamic stack allocation so that it doesn't modify the stack
1608 // pointer when other instructions are using the stack.
1609 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1611 SDValue Size = Tmp2.getOperand(1);
1612 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1613 Chain = SP.getValue(1);
1614 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1615 unsigned StackAlign =
1616 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1617 if (Align > StackAlign)
1618 SP = DAG.getNode(ISD::AND, dl, VT, SP,
1619 DAG.getConstant(-(uint64_t)Align, VT));
1620 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1621 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1623 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1624 DAG.getIntPtrConstant(0, true), SDValue());
1626 Results.push_back(Tmp1);
1627 Results.push_back(Tmp2);
1630 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
1631 /// condition code CC on the current target. This routine expands SETCC with
1632 /// illegal condition code into AND / OR of multiple SETCC values.
1633 void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1634 SDValue &LHS, SDValue &RHS,
1637 EVT OpVT = LHS.getValueType();
1638 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1639 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1640 default: llvm_unreachable("Unknown condition code action!");
1641 case TargetLowering::Legal:
1644 case TargetLowering::Expand: {
1645 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1648 default: llvm_unreachable("Don't know how to expand this condition!");
1649 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break;
1650 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1651 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1652 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1653 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1654 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1655 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1656 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1657 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1658 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1659 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1660 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1661 // FIXME: Implement more expansions.
1664 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1665 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1666 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1674 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
1675 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1676 /// a load from the stack slot to DestVT, extending it if needed.
1677 /// The resultant code need not be legal.
1678 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
1682 // Create the stack frame object.
1684 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType().
1685 getTypeForEVT(*DAG.getContext()));
1686 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1688 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1689 int SPFI = StackPtrFI->getIndex();
1690 const Value *SV = PseudoSourceValue::getFixedStack(SPFI);
1692 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
1693 unsigned SlotSize = SlotVT.getSizeInBits();
1694 unsigned DestSize = DestVT.getSizeInBits();
1695 unsigned DestAlign =
1696 TLI.getTargetData()->getPrefTypeAlignment(DestVT.getTypeForEVT(*DAG.getContext()));
1698 // Emit a store to the stack slot. Use a truncstore if the input value is
1699 // later than DestVT.
1702 if (SrcSize > SlotSize)
1703 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1704 SV, 0, SlotVT, false, SrcAlign);
1706 assert(SrcSize == SlotSize && "Invalid store");
1707 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1708 SV, 0, false, SrcAlign);
1711 // Result is a load from the stack slot.
1712 if (SlotSize == DestSize)
1713 return DAG.getLoad(DestVT, dl, Store, FIPtr, SV, 0, false, DestAlign);
1715 assert(SlotSize < DestSize && "Unknown extension!");
1716 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, SV, 0, SlotVT,
1720 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1721 DebugLoc dl = Node->getDebugLoc();
1722 // Create a vector sized/aligned stack slot, store the value to element #0,
1723 // then load the whole vector back out.
1724 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1726 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1727 int SPFI = StackPtrFI->getIndex();
1729 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0),
1731 PseudoSourceValue::getFixedStack(SPFI), 0,
1732 Node->getValueType(0).getVectorElementType());
1733 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
1734 PseudoSourceValue::getFixedStack(SPFI), 0);
1738 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
1739 /// support the operation, but do support the resultant vector type.
1740 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1741 unsigned NumElems = Node->getNumOperands();
1742 SDValue Value1, Value2;
1743 DebugLoc dl = Node->getDebugLoc();
1744 EVT VT = Node->getValueType(0);
1745 EVT OpVT = Node->getOperand(0).getValueType();
1746 EVT EltVT = VT.getVectorElementType();
1748 // If the only non-undef value is the low element, turn this into a
1749 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1750 bool isOnlyLowElement = true;
1751 bool MoreThanTwoValues = false;
1752 bool isConstant = true;
1753 for (unsigned i = 0; i < NumElems; ++i) {
1754 SDValue V = Node->getOperand(i);
1755 if (V.getOpcode() == ISD::UNDEF)
1758 isOnlyLowElement = false;
1759 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1762 if (!Value1.getNode()) {
1764 } else if (!Value2.getNode()) {
1767 } else if (V != Value1 && V != Value2) {
1768 MoreThanTwoValues = true;
1772 if (!Value1.getNode())
1773 return DAG.getUNDEF(VT);
1775 if (isOnlyLowElement)
1776 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1778 // If all elements are constants, create a load from the constant pool.
1780 std::vector<Constant*> CV;
1781 for (unsigned i = 0, e = NumElems; i != e; ++i) {
1782 if (ConstantFPSDNode *V =
1783 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1784 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1785 } else if (ConstantSDNode *V =
1786 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1788 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1790 // If OpVT and EltVT don't match, EltVT is not legal and the
1791 // element values have been promoted/truncated earlier. Undo this;
1792 // we don't want a v16i8 to become a v16i32 for example.
1793 const ConstantInt *CI = V->getConstantIntValue();
1794 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
1795 CI->getZExtValue()));
1798 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
1799 const Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
1800 CV.push_back(UndefValue::get(OpNTy));
1803 Constant *CP = ConstantVector::get(CV);
1804 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
1805 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
1806 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
1807 PseudoSourceValue::getConstantPool(), 0,
1811 if (!MoreThanTwoValues) {
1812 SmallVector<int, 8> ShuffleVec(NumElems, -1);
1813 for (unsigned i = 0; i < NumElems; ++i) {
1814 SDValue V = Node->getOperand(i);
1815 if (V.getOpcode() == ISD::UNDEF)
1817 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
1819 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
1820 // Get the splatted value into the low element of a vector register.
1821 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
1823 if (Value2.getNode())
1824 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
1826 Vec2 = DAG.getUNDEF(VT);
1828 // Return shuffle(LowValVec, undef, <0,0,0,0>)
1829 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
1833 // Otherwise, we can't handle this case efficiently.
1834 return ExpandVectorBuildThroughStack(Node);
1837 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
1838 // does not fit into a register, return the lo part and set the hi part to the
1839 // by-reg argument. If it does fit into a single register, return the result
1840 // and leave the Hi part unset.
1841 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
1843 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
1844 // The input chain to this libcall is the entry node of the function.
1845 // Legalizing the call will automatically add the previous call to the
1847 SDValue InChain = DAG.getEntryNode();
1849 TargetLowering::ArgListTy Args;
1850 TargetLowering::ArgListEntry Entry;
1851 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1852 EVT ArgVT = Node->getOperand(i).getValueType();
1853 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1854 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
1855 Entry.isSExt = isSigned;
1856 Entry.isZExt = !isSigned;
1857 Args.push_back(Entry);
1859 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1860 TLI.getPointerTy());
1862 // Splice the libcall in wherever FindInputOutputChains tells us to.
1863 const Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
1864 std::pair<SDValue, SDValue> CallInfo =
1865 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
1866 0, TLI.getLibcallCallingConv(LC), false,
1867 /*isReturnValueUsed=*/true,
1869 Node->getDebugLoc(), DAG.GetOrdering(Node));
1871 // Legalize the call sequence, starting with the chain. This will advance
1872 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
1873 // was added by LowerCallTo (guaranteeing proper serialization of calls).
1874 LegalizeOp(CallInfo.second);
1875 return CallInfo.first;
1878 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
1879 RTLIB::Libcall Call_F32,
1880 RTLIB::Libcall Call_F64,
1881 RTLIB::Libcall Call_F80,
1882 RTLIB::Libcall Call_PPCF128) {
1884 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
1885 default: llvm_unreachable("Unexpected request for libcall!");
1886 case MVT::f32: LC = Call_F32; break;
1887 case MVT::f64: LC = Call_F64; break;
1888 case MVT::f80: LC = Call_F80; break;
1889 case MVT::ppcf128: LC = Call_PPCF128; break;
1891 return ExpandLibCall(LC, Node, false);
1894 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
1895 RTLIB::Libcall Call_I8,
1896 RTLIB::Libcall Call_I16,
1897 RTLIB::Libcall Call_I32,
1898 RTLIB::Libcall Call_I64,
1899 RTLIB::Libcall Call_I128) {
1901 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
1902 default: llvm_unreachable("Unexpected request for libcall!");
1903 case MVT::i8: LC = Call_I8; break;
1904 case MVT::i16: LC = Call_I16; break;
1905 case MVT::i32: LC = Call_I32; break;
1906 case MVT::i64: LC = Call_I64; break;
1907 case MVT::i128: LC = Call_I128; break;
1909 return ExpandLibCall(LC, Node, isSigned);
1912 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
1913 /// INT_TO_FP operation of the specified operand when the target requests that
1914 /// we expand it. At this point, we know that the result and operand types are
1915 /// legal for the target.
1916 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
1920 if (Op0.getValueType() == MVT::i32) {
1921 // simple 32-bit [signed|unsigned] integer to float/double expansion
1923 // Get the stack frame index of a 8 byte buffer.
1924 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
1926 // word offset constant for Hi/Lo address computation
1927 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
1928 // set up Hi and Lo (into buffer) address based on endian
1929 SDValue Hi = StackSlot;
1930 SDValue Lo = DAG.getNode(ISD::ADD, dl,
1931 TLI.getPointerTy(), StackSlot, WordOff);
1932 if (TLI.isLittleEndian())
1935 // if signed map to unsigned space
1938 // constant used to invert sign bit (signed to unsigned mapping)
1939 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
1940 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
1944 // store the lo of the constructed double - based on integer input
1945 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
1946 Op0Mapped, Lo, NULL, 0);
1947 // initial hi portion of constructed double
1948 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
1949 // store the hi of the constructed double - biased exponent
1950 SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0);
1951 // load the constructed double
1952 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0);
1953 // FP constant to bias correct the final result
1954 SDValue Bias = DAG.getConstantFP(isSigned ?
1955 BitsToDouble(0x4330000080000000ULL) :
1956 BitsToDouble(0x4330000000000000ULL),
1958 // subtract the bias
1959 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
1962 // handle final rounding
1963 if (DestVT == MVT::f64) {
1966 } else if (DestVT.bitsLT(MVT::f64)) {
1967 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
1968 DAG.getIntPtrConstant(0));
1969 } else if (DestVT.bitsGT(MVT::f64)) {
1970 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
1974 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
1975 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
1977 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()),
1978 Op0, DAG.getConstant(0, Op0.getValueType()),
1980 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
1981 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
1982 SignSet, Four, Zero);
1984 // If the sign bit of the integer is set, the large number will be treated
1985 // as a negative number. To counteract this, the dynamic code adds an
1986 // offset depending on the data type.
1988 switch (Op0.getValueType().getSimpleVT().SimpleTy) {
1989 default: llvm_unreachable("Unsupported integer type!");
1990 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
1991 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
1992 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
1993 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
1995 if (TLI.isLittleEndian()) FF <<= 32;
1996 Constant *FudgeFactor = ConstantInt::get(
1997 Type::getInt64Ty(*DAG.getContext()), FF);
1999 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
2000 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2001 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
2002 Alignment = std::min(Alignment, 4u);
2004 if (DestVT == MVT::f32)
2005 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2006 PseudoSourceValue::getConstantPool(), 0,
2010 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
2011 DAG.getEntryNode(), CPIdx,
2012 PseudoSourceValue::getConstantPool(), 0,
2013 MVT::f32, false, Alignment));
2016 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2019 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
2020 /// *INT_TO_FP operation of the specified operand when the target requests that
2021 /// we promote it. At this point, we know that the result and operand types are
2022 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2023 /// operation that takes a larger input.
2024 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2028 // First step, figure out the appropriate *INT_TO_FP operation to use.
2029 EVT NewInTy = LegalOp.getValueType();
2031 unsigned OpToUse = 0;
2033 // Scan for the appropriate larger type to use.
2035 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2036 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2038 // If the target supports SINT_TO_FP of this type, use it.
2039 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2040 OpToUse = ISD::SINT_TO_FP;
2043 if (isSigned) continue;
2045 // If the target supports UINT_TO_FP of this type, use it.
2046 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2047 OpToUse = ISD::UINT_TO_FP;
2051 // Otherwise, try a larger type.
2054 // Okay, we found the operation and type to use. Zero extend our input to the
2055 // desired type then run the operation on it.
2056 return DAG.getNode(OpToUse, dl, DestVT,
2057 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2058 dl, NewInTy, LegalOp));
2061 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
2062 /// FP_TO_*INT operation of the specified operand when the target requests that
2063 /// we promote it. At this point, we know that the result and operand types are
2064 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2065 /// operation that returns a larger result.
2066 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2070 // First step, figure out the appropriate FP_TO*INT operation to use.
2071 EVT NewOutTy = DestVT;
2073 unsigned OpToUse = 0;
2075 // Scan for the appropriate larger type to use.
2077 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2078 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2080 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2081 OpToUse = ISD::FP_TO_SINT;
2085 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2086 OpToUse = ISD::FP_TO_UINT;
2090 // Otherwise, try a larger type.
2094 // Okay, we found the operation and type to use.
2095 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2097 // Truncate the result of the extended FP_TO_*INT operation to the desired
2099 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2102 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
2104 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) {
2105 EVT VT = Op.getValueType();
2106 EVT SHVT = TLI.getShiftAmountTy();
2107 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2108 switch (VT.getSimpleVT().SimpleTy) {
2109 default: llvm_unreachable("Unhandled Expand type in BSWAP!");
2111 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2112 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2113 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2115 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2116 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2117 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2118 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2119 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
2120 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
2121 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2122 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2123 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2125 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
2126 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
2127 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2128 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2129 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2130 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2131 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
2132 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
2133 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
2134 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
2135 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
2136 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
2137 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
2138 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
2139 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2140 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2141 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2142 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2143 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2144 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2145 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2149 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
2151 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2154 default: llvm_unreachable("Cannot expand this yet!");
2156 static const uint64_t mask[6] = {
2157 0x5555555555555555ULL, 0x3333333333333333ULL,
2158 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
2159 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
2161 EVT VT = Op.getValueType();
2162 EVT ShVT = TLI.getShiftAmountTy();
2163 unsigned len = VT.getSizeInBits();
2164 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2165 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
2166 unsigned EltSize = VT.isVector() ?
2167 VT.getVectorElementType().getSizeInBits() : len;
2168 SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT);
2169 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2170 Op = DAG.getNode(ISD::ADD, dl, VT,
2171 DAG.getNode(ISD::AND, dl, VT, Op, Tmp2),
2172 DAG.getNode(ISD::AND, dl, VT,
2173 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3),
2179 // for now, we do this:
2180 // x = x | (x >> 1);
2181 // x = x | (x >> 2);
2183 // x = x | (x >>16);
2184 // x = x | (x >>32); // for 64-bit input
2185 // return popcount(~x);
2187 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
2188 EVT VT = Op.getValueType();
2189 EVT ShVT = TLI.getShiftAmountTy();
2190 unsigned len = VT.getSizeInBits();
2191 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2192 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2193 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2194 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2196 Op = DAG.getNOT(dl, Op, VT);
2197 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2200 // for now, we use: { return popcount(~x & (x - 1)); }
2201 // unless the target has ctlz but not ctpop, in which case we use:
2202 // { return 32 - nlz(~x & (x-1)); }
2203 // see also http://www.hackersdelight.org/HDcode/ntz.cc
2204 EVT VT = Op.getValueType();
2205 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2206 DAG.getNOT(dl, Op, VT),
2207 DAG.getNode(ISD::SUB, dl, VT, Op,
2208 DAG.getConstant(1, VT)));
2209 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2210 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2211 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2212 return DAG.getNode(ISD::SUB, dl, VT,
2213 DAG.getConstant(VT.getSizeInBits(), VT),
2214 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2215 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2220 void SelectionDAGLegalize::ExpandNode(SDNode *Node,
2221 SmallVectorImpl<SDValue> &Results) {
2222 DebugLoc dl = Node->getDebugLoc();
2223 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2224 switch (Node->getOpcode()) {
2228 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
2229 Results.push_back(Tmp1);
2232 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2234 case ISD::FRAMEADDR:
2235 case ISD::RETURNADDR:
2236 case ISD::FRAME_TO_ARGS_OFFSET:
2237 Results.push_back(DAG.getConstant(0, Node->getValueType(0)));
2239 case ISD::FLT_ROUNDS_:
2240 Results.push_back(DAG.getConstant(1, Node->getValueType(0)));
2242 case ISD::EH_RETURN:
2245 case ISD::MEMBARRIER:
2247 Results.push_back(Node->getOperand(0));
2249 case ISD::DYNAMIC_STACKALLOC:
2250 ExpandDYNAMIC_STACKALLOC(Node, Results);
2252 case ISD::MERGE_VALUES:
2253 for (unsigned i = 0; i < Node->getNumValues(); i++)
2254 Results.push_back(Node->getOperand(i));
2257 EVT VT = Node->getValueType(0);
2259 Results.push_back(DAG.getConstant(0, VT));
2260 else if (VT.isFloatingPoint())
2261 Results.push_back(DAG.getConstantFP(0, VT));
2263 llvm_unreachable("Unknown value type!");
2267 // If this operation is not supported, lower it to 'abort()' call
2268 TargetLowering::ArgListTy Args;
2269 std::pair<SDValue, SDValue> CallResult =
2270 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()),
2271 false, false, false, false, 0, CallingConv::C, false,
2272 /*isReturnValueUsed=*/true,
2273 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
2274 Args, DAG, dl, DAG.GetOrdering(Node));
2275 Results.push_back(CallResult.second);
2279 case ISD::BIT_CONVERT:
2280 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
2281 Node->getValueType(0), dl);
2282 Results.push_back(Tmp1);
2284 case ISD::FP_EXTEND:
2285 Tmp1 = EmitStackConvert(Node->getOperand(0),
2286 Node->getOperand(0).getValueType(),
2287 Node->getValueType(0), dl);
2288 Results.push_back(Tmp1);
2290 case ISD::SIGN_EXTEND_INREG: {
2291 // NOTE: we could fall back on load/store here too for targets without
2292 // SAR. However, it is doubtful that any exist.
2293 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2294 EVT VT = Node->getValueType(0);
2295 EVT ShiftAmountTy = TLI.getShiftAmountTy();
2298 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
2299 ExtraVT.getScalarType().getSizeInBits();
2300 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy);
2301 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
2302 Node->getOperand(0), ShiftCst);
2303 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
2304 Results.push_back(Tmp1);
2307 case ISD::FP_ROUND_INREG: {
2308 // The only way we can lower this is to turn it into a TRUNCSTORE,
2309 // EXTLOAD pair, targetting a temporary location (a stack slot).
2311 // NOTE: there is a choice here between constantly creating new stack
2312 // slots and always reusing the same one. We currently always create
2313 // new ones, as reuse may inhibit scheduling.
2314 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2315 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
2316 Node->getValueType(0), dl);
2317 Results.push_back(Tmp1);
2320 case ISD::SINT_TO_FP:
2321 case ISD::UINT_TO_FP:
2322 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
2323 Node->getOperand(0), Node->getValueType(0), dl);
2324 Results.push_back(Tmp1);
2326 case ISD::FP_TO_UINT: {
2327 SDValue True, False;
2328 EVT VT = Node->getOperand(0).getValueType();
2329 EVT NVT = Node->getValueType(0);
2330 const uint64_t zero[] = {0, 0};
2331 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero));
2332 APInt x = APInt::getSignBit(NVT.getSizeInBits());
2333 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
2334 Tmp1 = DAG.getConstantFP(apf, VT);
2335 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
2336 Node->getOperand(0),
2338 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
2339 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
2340 DAG.getNode(ISD::FSUB, dl, VT,
2341 Node->getOperand(0), Tmp1));
2342 False = DAG.getNode(ISD::XOR, dl, NVT, False,
2343 DAG.getConstant(x, NVT));
2344 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False);
2345 Results.push_back(Tmp1);
2349 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2350 EVT VT = Node->getValueType(0);
2351 Tmp1 = Node->getOperand(0);
2352 Tmp2 = Node->getOperand(1);
2353 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0);
2354 // Increment the pointer, VAList, to the next vaarg
2355 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
2356 DAG.getConstant(TLI.getTargetData()->
2357 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())),
2358 TLI.getPointerTy()));
2359 // Store the incremented VAList to the legalized pointer
2360 Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0);
2361 // Load the actual argument out of the pointer VAList
2362 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, NULL, 0));
2363 Results.push_back(Results[0].getValue(1));
2367 // This defaults to loading a pointer from the input and storing it to the
2368 // output, returning the chain.
2369 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
2370 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
2371 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0),
2372 Node->getOperand(2), VS, 0);
2373 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1), VD, 0);
2374 Results.push_back(Tmp1);
2377 case ISD::EXTRACT_VECTOR_ELT:
2378 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
2379 // This must be an access of the only element. Return it.
2380 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0),
2381 Node->getOperand(0));
2383 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
2384 Results.push_back(Tmp1);
2386 case ISD::EXTRACT_SUBVECTOR:
2387 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
2389 case ISD::CONCAT_VECTORS: {
2390 Results.push_back(ExpandVectorBuildThroughStack(Node));
2393 case ISD::SCALAR_TO_VECTOR:
2394 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
2396 case ISD::INSERT_VECTOR_ELT:
2397 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
2398 Node->getOperand(1),
2399 Node->getOperand(2), dl));
2401 case ISD::VECTOR_SHUFFLE: {
2402 SmallVector<int, 8> Mask;
2403 cast<ShuffleVectorSDNode>(Node)->getMask(Mask);
2405 EVT VT = Node->getValueType(0);
2406 EVT EltVT = VT.getVectorElementType();
2407 unsigned NumElems = VT.getVectorNumElements();
2408 SmallVector<SDValue, 8> Ops;
2409 for (unsigned i = 0; i != NumElems; ++i) {
2411 Ops.push_back(DAG.getUNDEF(EltVT));
2414 unsigned Idx = Mask[i];
2416 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
2417 Node->getOperand(0),
2418 DAG.getIntPtrConstant(Idx)));
2420 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
2421 Node->getOperand(1),
2422 DAG.getIntPtrConstant(Idx - NumElems)));
2424 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
2425 Results.push_back(Tmp1);
2428 case ISD::EXTRACT_ELEMENT: {
2429 EVT OpTy = Node->getOperand(0).getValueType();
2430 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
2432 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
2433 DAG.getConstant(OpTy.getSizeInBits()/2,
2434 TLI.getShiftAmountTy()));
2435 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
2438 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
2439 Node->getOperand(0));
2441 Results.push_back(Tmp1);
2444 case ISD::STACKSAVE:
2445 // Expand to CopyFromReg if the target set
2446 // StackPointerRegisterToSaveRestore.
2447 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2448 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
2449 Node->getValueType(0)));
2450 Results.push_back(Results[0].getValue(1));
2452 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
2453 Results.push_back(Node->getOperand(0));
2456 case ISD::STACKRESTORE:
2457 // Expand to CopyToReg if the target set
2458 // StackPointerRegisterToSaveRestore.
2459 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2460 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
2461 Node->getOperand(1)));
2463 Results.push_back(Node->getOperand(0));
2466 case ISD::FCOPYSIGN:
2467 Results.push_back(ExpandFCOPYSIGN(Node));
2470 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2471 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2472 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
2473 Node->getOperand(0));
2474 Results.push_back(Tmp1);
2477 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2478 EVT VT = Node->getValueType(0);
2479 Tmp1 = Node->getOperand(0);
2480 Tmp2 = DAG.getConstantFP(0.0, VT);
2481 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
2482 Tmp1, Tmp2, ISD::SETUGT);
2483 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
2484 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3);
2485 Results.push_back(Tmp1);
2489 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
2490 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128));
2493 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
2494 RTLIB::SIN_F80, RTLIB::SIN_PPCF128));
2497 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
2498 RTLIB::COS_F80, RTLIB::COS_PPCF128));
2501 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
2502 RTLIB::LOG_F80, RTLIB::LOG_PPCF128));
2505 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
2506 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128));
2509 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
2510 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128));
2513 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
2514 RTLIB::EXP_F80, RTLIB::EXP_PPCF128));
2517 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
2518 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128));
2521 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
2522 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128));
2525 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
2526 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128));
2529 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
2530 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128));
2533 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
2534 RTLIB::RINT_F80, RTLIB::RINT_PPCF128));
2536 case ISD::FNEARBYINT:
2537 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
2538 RTLIB::NEARBYINT_F64,
2539 RTLIB::NEARBYINT_F80,
2540 RTLIB::NEARBYINT_PPCF128));
2543 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
2544 RTLIB::POWI_F80, RTLIB::POWI_PPCF128));
2547 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
2548 RTLIB::POW_F80, RTLIB::POW_PPCF128));
2551 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
2552 RTLIB::DIV_F80, RTLIB::DIV_PPCF128));
2555 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
2556 RTLIB::REM_F80, RTLIB::REM_PPCF128));
2558 case ISD::ConstantFP: {
2559 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
2560 // Check to see if this FP immediate is already legal.
2561 // If this is a legal constant, turn it into a TargetConstantFP node.
2562 if (TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
2563 Results.push_back(SDValue(Node, 0));
2565 Results.push_back(ExpandConstantFP(CFP, true, DAG, TLI));
2568 case ISD::EHSELECTION: {
2569 unsigned Reg = TLI.getExceptionSelectorRegister();
2570 assert(Reg && "Can't expand to unknown register!");
2571 Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg,
2572 Node->getValueType(0)));
2573 Results.push_back(Results[0].getValue(1));
2576 case ISD::EXCEPTIONADDR: {
2577 unsigned Reg = TLI.getExceptionAddressRegister();
2578 assert(Reg && "Can't expand to unknown register!");
2579 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg,
2580 Node->getValueType(0)));
2581 Results.push_back(Results[0].getValue(1));
2585 EVT VT = Node->getValueType(0);
2586 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
2587 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
2588 "Don't know how to expand this subtraction!");
2589 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
2590 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
2591 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT));
2592 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
2597 EVT VT = Node->getValueType(0);
2598 SDVTList VTs = DAG.getVTList(VT, VT);
2599 bool isSigned = Node->getOpcode() == ISD::SREM;
2600 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
2601 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2602 Tmp2 = Node->getOperand(0);
2603 Tmp3 = Node->getOperand(1);
2604 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) {
2605 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
2606 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
2608 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
2609 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
2610 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
2611 } else if (isSigned) {
2612 Tmp1 = ExpandIntLibCall(Node, true,
2614 RTLIB::SREM_I16, RTLIB::SREM_I32,
2615 RTLIB::SREM_I64, RTLIB::SREM_I128);
2617 Tmp1 = ExpandIntLibCall(Node, false,
2619 RTLIB::UREM_I16, RTLIB::UREM_I32,
2620 RTLIB::UREM_I64, RTLIB::UREM_I128);
2622 Results.push_back(Tmp1);
2627 bool isSigned = Node->getOpcode() == ISD::SDIV;
2628 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2629 EVT VT = Node->getValueType(0);
2630 SDVTList VTs = DAG.getVTList(VT, VT);
2631 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT))
2632 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
2633 Node->getOperand(1));
2635 Tmp1 = ExpandIntLibCall(Node, true,
2637 RTLIB::SDIV_I16, RTLIB::SDIV_I32,
2638 RTLIB::SDIV_I64, RTLIB::SDIV_I128);
2640 Tmp1 = ExpandIntLibCall(Node, false,
2642 RTLIB::UDIV_I16, RTLIB::UDIV_I32,
2643 RTLIB::UDIV_I64, RTLIB::UDIV_I128);
2644 Results.push_back(Tmp1);
2649 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
2651 EVT VT = Node->getValueType(0);
2652 SDVTList VTs = DAG.getVTList(VT, VT);
2653 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
2654 "If this wasn't legal, it shouldn't have been created!");
2655 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
2656 Node->getOperand(1));
2657 Results.push_back(Tmp1.getValue(1));
2661 EVT VT = Node->getValueType(0);
2662 SDVTList VTs = DAG.getVTList(VT, VT);
2663 // See if multiply or divide can be lowered using two-result operations.
2664 // We just need the low half of the multiply; try both the signed
2665 // and unsigned forms. If the target supports both SMUL_LOHI and
2666 // UMUL_LOHI, form a preference by checking which forms of plain
2667 // MULH it supports.
2668 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
2669 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
2670 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
2671 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
2672 unsigned OpToUse = 0;
2673 if (HasSMUL_LOHI && !HasMULHS) {
2674 OpToUse = ISD::SMUL_LOHI;
2675 } else if (HasUMUL_LOHI && !HasMULHU) {
2676 OpToUse = ISD::UMUL_LOHI;
2677 } else if (HasSMUL_LOHI) {
2678 OpToUse = ISD::SMUL_LOHI;
2679 } else if (HasUMUL_LOHI) {
2680 OpToUse = ISD::UMUL_LOHI;
2683 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
2684 Node->getOperand(1)));
2687 Tmp1 = ExpandIntLibCall(Node, false,
2689 RTLIB::MUL_I16, RTLIB::MUL_I32,
2690 RTLIB::MUL_I64, RTLIB::MUL_I128);
2691 Results.push_back(Tmp1);
2696 SDValue LHS = Node->getOperand(0);
2697 SDValue RHS = Node->getOperand(1);
2698 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
2699 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2701 Results.push_back(Sum);
2702 EVT OType = Node->getValueType(1);
2704 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
2706 // LHSSign -> LHS >= 0
2707 // RHSSign -> RHS >= 0
2708 // SumSign -> Sum >= 0
2711 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
2713 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
2715 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
2716 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
2717 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
2718 Node->getOpcode() == ISD::SADDO ?
2719 ISD::SETEQ : ISD::SETNE);
2721 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
2722 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
2724 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
2725 Results.push_back(Cmp);
2730 SDValue LHS = Node->getOperand(0);
2731 SDValue RHS = Node->getOperand(1);
2732 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
2733 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2735 Results.push_back(Sum);
2736 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS,
2737 Node->getOpcode () == ISD::UADDO ?
2738 ISD::SETULT : ISD::SETUGT));
2743 EVT VT = Node->getValueType(0);
2744 SDValue LHS = Node->getOperand(0);
2745 SDValue RHS = Node->getOperand(1);
2748 static const unsigned Ops[2][3] =
2749 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
2750 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
2751 bool isSigned = Node->getOpcode() == ISD::SMULO;
2752 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
2753 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
2754 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
2755 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
2756 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
2758 TopHalf = BottomHalf.getValue(1);
2759 } else if (TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2))) {
2760 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
2761 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
2762 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
2763 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
2764 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
2765 DAG.getIntPtrConstant(0));
2766 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
2767 DAG.getIntPtrConstant(1));
2769 // FIXME: We should be able to fall back to a libcall with an illegal
2770 // type in some cases cases.
2771 // Also, we can fall back to a division in some cases, but that's a big
2772 // performance hit in the general case.
2773 llvm_unreachable("Don't know how to expand this operation yet!");
2776 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1, TLI.getShiftAmountTy());
2777 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
2778 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1,
2781 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf,
2782 DAG.getConstant(0, VT), ISD::SETNE);
2784 Results.push_back(BottomHalf);
2785 Results.push_back(TopHalf);
2788 case ISD::BUILD_PAIR: {
2789 EVT PairTy = Node->getValueType(0);
2790 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
2791 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
2792 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
2793 DAG.getConstant(PairTy.getSizeInBits()/2,
2794 TLI.getShiftAmountTy()));
2795 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
2799 Tmp1 = Node->getOperand(0);
2800 Tmp2 = Node->getOperand(1);
2801 Tmp3 = Node->getOperand(2);
2802 if (Tmp1.getOpcode() == ISD::SETCC) {
2803 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
2805 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2807 Tmp1 = DAG.getSelectCC(dl, Tmp1,
2808 DAG.getConstant(0, Tmp1.getValueType()),
2809 Tmp2, Tmp3, ISD::SETNE);
2811 Results.push_back(Tmp1);
2814 SDValue Chain = Node->getOperand(0);
2815 SDValue Table = Node->getOperand(1);
2816 SDValue Index = Node->getOperand(2);
2818 EVT PTy = TLI.getPointerTy();
2819 MachineFunction &MF = DAG.getMachineFunction();
2820 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
2821 Index= DAG.getNode(ISD::MUL, dl, PTy,
2822 Index, DAG.getConstant(EntrySize, PTy));
2823 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2825 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
2826 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
2827 PseudoSourceValue::getJumpTable(), 0, MemVT);
2829 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2830 // For PIC, the sequence is:
2831 // BRIND(load(Jumptable + index) + RelocBase)
2832 // RelocBase can be JumpTable, GOT or some sort of global base.
2833 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
2834 TLI.getPICJumpTableRelocBase(Table, DAG));
2836 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
2837 Results.push_back(Tmp1);
2841 // Expand brcond's setcc into its constituent parts and create a BR_CC
2843 Tmp1 = Node->getOperand(0);
2844 Tmp2 = Node->getOperand(1);
2845 if (Tmp2.getOpcode() == ISD::SETCC) {
2846 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
2847 Tmp1, Tmp2.getOperand(2),
2848 Tmp2.getOperand(0), Tmp2.getOperand(1),
2849 Node->getOperand(2));
2851 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
2852 DAG.getCondCode(ISD::SETNE), Tmp2,
2853 DAG.getConstant(0, Tmp2.getValueType()),
2854 Node->getOperand(2));
2856 Results.push_back(Tmp1);
2859 Tmp1 = Node->getOperand(0);
2860 Tmp2 = Node->getOperand(1);
2861 Tmp3 = Node->getOperand(2);
2862 LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl);
2864 // If we expanded the SETCC into an AND/OR, return the new node
2865 if (Tmp2.getNode() == 0) {
2866 Results.push_back(Tmp1);
2870 // Otherwise, SETCC for the given comparison type must be completely
2871 // illegal; expand it into a SELECT_CC.
2872 EVT VT = Node->getValueType(0);
2873 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
2874 DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3);
2875 Results.push_back(Tmp1);
2878 case ISD::SELECT_CC: {
2879 Tmp1 = Node->getOperand(0); // LHS
2880 Tmp2 = Node->getOperand(1); // RHS
2881 Tmp3 = Node->getOperand(2); // True
2882 Tmp4 = Node->getOperand(3); // False
2883 SDValue CC = Node->getOperand(4);
2885 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()),
2886 Tmp1, Tmp2, CC, dl);
2888 assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!");
2889 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2890 CC = DAG.getCondCode(ISD::SETNE);
2891 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2,
2893 Results.push_back(Tmp1);
2897 Tmp1 = Node->getOperand(0); // Chain
2898 Tmp2 = Node->getOperand(2); // LHS
2899 Tmp3 = Node->getOperand(3); // RHS
2900 Tmp4 = Node->getOperand(1); // CC
2902 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()),
2903 Tmp2, Tmp3, Tmp4, dl);
2904 LastCALLSEQ_END = DAG.getEntryNode();
2906 assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!");
2907 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
2908 Tmp4 = DAG.getCondCode(ISD::SETNE);
2909 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2,
2910 Tmp3, Node->getOperand(4));
2911 Results.push_back(Tmp1);
2914 case ISD::GLOBAL_OFFSET_TABLE:
2915 case ISD::GlobalAddress:
2916 case ISD::GlobalTLSAddress:
2917 case ISD::ExternalSymbol:
2918 case ISD::ConstantPool:
2919 case ISD::JumpTable:
2920 case ISD::INTRINSIC_W_CHAIN:
2921 case ISD::INTRINSIC_WO_CHAIN:
2922 case ISD::INTRINSIC_VOID:
2923 // FIXME: Custom lowering for these operations shouldn't return null!
2924 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2925 Results.push_back(SDValue(Node, i));
2929 void SelectionDAGLegalize::PromoteNode(SDNode *Node,
2930 SmallVectorImpl<SDValue> &Results) {
2931 EVT OVT = Node->getValueType(0);
2932 if (Node->getOpcode() == ISD::UINT_TO_FP ||
2933 Node->getOpcode() == ISD::SINT_TO_FP ||
2934 Node->getOpcode() == ISD::SETCC) {
2935 OVT = Node->getOperand(0).getValueType();
2937 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2938 DebugLoc dl = Node->getDebugLoc();
2939 SDValue Tmp1, Tmp2, Tmp3;
2940 switch (Node->getOpcode()) {
2944 // Zero extend the argument.
2945 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
2946 // Perform the larger operation.
2947 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
2948 if (Node->getOpcode() == ISD::CTTZ) {
2949 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2950 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
2951 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
2953 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
2954 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
2955 } else if (Node->getOpcode() == ISD::CTLZ) {
2956 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2957 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
2958 DAG.getConstant(NVT.getSizeInBits() -
2959 OVT.getSizeInBits(), NVT));
2961 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
2964 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
2965 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
2966 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
2967 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
2968 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
2969 Results.push_back(Tmp1);
2972 case ISD::FP_TO_UINT:
2973 case ISD::FP_TO_SINT:
2974 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
2975 Node->getOpcode() == ISD::FP_TO_SINT, dl);
2976 Results.push_back(Tmp1);
2978 case ISD::UINT_TO_FP:
2979 case ISD::SINT_TO_FP:
2980 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
2981 Node->getOpcode() == ISD::SINT_TO_FP, dl);
2982 Results.push_back(Tmp1);
2987 unsigned ExtOp, TruncOp;
2988 if (OVT.isVector()) {
2989 ExtOp = ISD::BIT_CONVERT;
2990 TruncOp = ISD::BIT_CONVERT;
2991 } else if (OVT.isInteger()) {
2992 ExtOp = ISD::ANY_EXTEND;
2993 TruncOp = ISD::TRUNCATE;
2995 llvm_report_error("Cannot promote logic operation");
2997 // Promote each of the values to the new type.
2998 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
2999 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3000 // Perform the larger operation, then convert back
3001 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3002 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
3006 unsigned ExtOp, TruncOp;
3007 if (Node->getValueType(0).isVector()) {
3008 ExtOp = ISD::BIT_CONVERT;
3009 TruncOp = ISD::BIT_CONVERT;
3010 } else if (Node->getValueType(0).isInteger()) {
3011 ExtOp = ISD::ANY_EXTEND;
3012 TruncOp = ISD::TRUNCATE;
3014 ExtOp = ISD::FP_EXTEND;
3015 TruncOp = ISD::FP_ROUND;
3017 Tmp1 = Node->getOperand(0);
3018 // Promote each of the values to the new type.
3019 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3020 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
3021 // Perform the larger operation, then round down.
3022 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3);
3023 if (TruncOp != ISD::FP_ROUND)
3024 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
3026 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
3027 DAG.getIntPtrConstant(0));
3028 Results.push_back(Tmp1);
3031 case ISD::VECTOR_SHUFFLE: {
3032 SmallVector<int, 8> Mask;
3033 cast<ShuffleVectorSDNode>(Node)->getMask(Mask);
3035 // Cast the two input vectors.
3036 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
3037 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(1));
3039 // Convert the shuffle mask to the right # elements.
3040 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
3041 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Tmp1);
3042 Results.push_back(Tmp1);
3046 unsigned ExtOp = ISD::FP_EXTEND;
3047 if (NVT.isInteger()) {
3048 ISD::CondCode CCCode =
3049 cast<CondCodeSDNode>(Node->getOperand(2))->get();
3050 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3052 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3053 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3054 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3055 Tmp1, Tmp2, Node->getOperand(2)));
3061 // SelectionDAG::Legalize - This is the entry point for the file.
3063 void SelectionDAG::Legalize(CodeGenOpt::Level OptLevel) {
3064 /// run - This is the main entry point to this class.
3066 SelectionDAGLegalize(*this, OptLevel).LegalizeDAG();