1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/ADT/SmallPtrSet.h"
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/ADT/Triple.h"
18 #include "llvm/CodeGen/Analysis.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineJumpTableInfo.h"
21 #include "llvm/IR/CallingConv.h"
22 #include "llvm/IR/Constants.h"
23 #include "llvm/IR/DataLayout.h"
24 #include "llvm/IR/DebugInfo.h"
25 #include "llvm/IR/DerivedTypes.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/IR/LLVMContext.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/MathExtras.h"
31 #include "llvm/Support/raw_ostream.h"
32 #include "llvm/Target/TargetFrameLowering.h"
33 #include "llvm/Target/TargetLowering.h"
34 #include "llvm/Target/TargetMachine.h"
37 //===----------------------------------------------------------------------===//
38 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
39 /// hacks on it until the target machine can handle it. This involves
40 /// eliminating value sizes the machine cannot handle (promoting small sizes to
41 /// large sizes or splitting up large values into small values) as well as
42 /// eliminating operations the machine cannot handle.
44 /// This code also does a small amount of optimization and recognition of idioms
45 /// as part of its processing. For example, if a target does not support a
46 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
47 /// will attempt merge setcc and brc instructions into brcc's.
50 class SelectionDAGLegalize : public SelectionDAG::DAGUpdateListener {
51 const TargetMachine &TM;
52 const TargetLowering &TLI;
55 /// LegalizePosition - The iterator for walking through the node list.
56 SelectionDAG::allnodes_iterator LegalizePosition;
58 /// LegalizedNodes - The set of nodes which have already been legalized.
59 SmallPtrSet<SDNode *, 16> LegalizedNodes;
61 EVT getSetCCResultType(EVT VT) const {
62 return TLI.getSetCCResultType(*DAG.getContext(), VT);
65 // Libcall insertion helpers.
68 explicit SelectionDAGLegalize(SelectionDAG &DAG);
73 /// LegalizeOp - Legalizes the given operation.
74 void LegalizeOp(SDNode *Node);
76 SDValue OptimizeFloatStore(StoreSDNode *ST);
78 void LegalizeLoadOps(SDNode *Node);
79 void LegalizeStoreOps(SDNode *Node);
81 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
82 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
83 /// is necessary to spill the vector being inserted into to memory, perform
84 /// the insert there, and then read the result back.
85 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
86 SDValue Idx, SDLoc dl);
87 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
88 SDValue Idx, SDLoc dl);
90 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
91 /// performs the same shuffe in terms of order or result bytes, but on a type
92 /// whose vector element type is narrower than the original shuffle type.
93 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
94 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl,
95 SDValue N1, SDValue N2,
96 ArrayRef<int> Mask) const;
98 bool LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
99 bool &NeedInvert, SDLoc dl);
101 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
102 SDValue ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops,
103 unsigned NumOps, bool isSigned, SDLoc dl);
105 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
106 SDNode *Node, bool isSigned);
107 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
108 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
109 RTLIB::Libcall Call_F128,
110 RTLIB::Libcall Call_PPCF128);
111 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
112 RTLIB::Libcall Call_I8,
113 RTLIB::Libcall Call_I16,
114 RTLIB::Libcall Call_I32,
115 RTLIB::Libcall Call_I64,
116 RTLIB::Libcall Call_I128);
117 void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
118 void ExpandSinCosLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
120 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, SDLoc dl);
121 SDValue ExpandBUILD_VECTOR(SDNode *Node);
122 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
123 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
124 SmallVectorImpl<SDValue> &Results);
125 SDValue ExpandFCOPYSIGN(SDNode *Node);
126 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
128 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
130 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
133 SDValue ExpandBSWAP(SDValue Op, SDLoc dl);
134 SDValue ExpandBitCount(unsigned Opc, SDValue Op, SDLoc dl);
136 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
137 SDValue ExpandInsertToVectorThroughStack(SDValue Op);
138 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
140 SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP);
142 std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node);
144 void ExpandNode(SDNode *Node);
145 void PromoteNode(SDNode *Node);
147 void ForgetNode(SDNode *N) {
148 LegalizedNodes.erase(N);
149 if (LegalizePosition == SelectionDAG::allnodes_iterator(N))
154 // DAGUpdateListener implementation.
155 void NodeDeleted(SDNode *N, SDNode *E) override {
158 void NodeUpdated(SDNode *N) override {}
160 // Node replacement helpers
161 void ReplacedNode(SDNode *N) {
162 if (N->use_empty()) {
163 DAG.RemoveDeadNode(N);
168 void ReplaceNode(SDNode *Old, SDNode *New) {
169 DAG.ReplaceAllUsesWith(Old, New);
172 void ReplaceNode(SDValue Old, SDValue New) {
173 DAG.ReplaceAllUsesWith(Old, New);
174 ReplacedNode(Old.getNode());
176 void ReplaceNode(SDNode *Old, const SDValue *New) {
177 DAG.ReplaceAllUsesWith(Old, New);
183 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
184 /// performs the same shuffe in terms of order or result bytes, but on a type
185 /// whose vector element type is narrower than the original shuffle type.
186 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
188 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl,
189 SDValue N1, SDValue N2,
190 ArrayRef<int> Mask) const {
191 unsigned NumMaskElts = VT.getVectorNumElements();
192 unsigned NumDestElts = NVT.getVectorNumElements();
193 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
195 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
197 if (NumEltsGrowth == 1)
198 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
200 SmallVector<int, 8> NewMask;
201 for (unsigned i = 0; i != NumMaskElts; ++i) {
203 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
205 NewMask.push_back(-1);
207 NewMask.push_back(Idx * NumEltsGrowth + j);
210 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
211 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
212 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
215 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
216 : SelectionDAG::DAGUpdateListener(dag),
217 TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()),
221 void SelectionDAGLegalize::LegalizeDAG() {
222 DAG.AssignTopologicalOrder();
224 // Visit all the nodes. We start in topological order, so that we see
225 // nodes with their original operands intact. Legalization can produce
226 // new nodes which may themselves need to be legalized. Iterate until all
227 // nodes have been legalized.
229 bool AnyLegalized = false;
230 for (LegalizePosition = DAG.allnodes_end();
231 LegalizePosition != DAG.allnodes_begin(); ) {
234 SDNode *N = LegalizePosition;
235 if (LegalizedNodes.insert(N)) {
245 // Remove dead nodes now.
246 DAG.RemoveDeadNodes();
249 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
250 /// a load from the constant pool.
252 SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) {
256 // If a FP immediate is precise when represented as a float and if the
257 // target can do an extending load from float to double, we put it into
258 // the constant pool as a float, even if it's is statically typed as a
259 // double. This shrinks FP constants and canonicalizes them for targets where
260 // an FP extending load is the same cost as a normal load (such as on the x87
261 // fp stack or PPC FP unit).
262 EVT VT = CFP->getValueType(0);
263 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
265 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
266 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
267 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
272 while (SVT != MVT::f32) {
273 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
274 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) &&
275 // Only do this if the target has a native EXTLOAD instruction from
277 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
278 TLI.ShouldShrinkFPConstant(OrigVT)) {
279 Type *SType = SVT.getTypeForEVT(*DAG.getContext());
280 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
286 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
287 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
290 DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT,
292 CPIdx, MachinePointerInfo::getConstantPool(),
293 VT, false, false, Alignment);
297 DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
298 MachinePointerInfo::getConstantPool(), false, false, false,
303 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
304 static void ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
305 const TargetLowering &TLI,
306 SelectionDAGLegalize *DAGLegalize) {
307 assert(ST->getAddressingMode() == ISD::UNINDEXED &&
308 "unaligned indexed stores not implemented!");
309 SDValue Chain = ST->getChain();
310 SDValue Ptr = ST->getBasePtr();
311 SDValue Val = ST->getValue();
312 EVT VT = Val.getValueType();
313 int Alignment = ST->getAlignment();
314 unsigned AS = ST->getAddressSpace();
317 if (ST->getMemoryVT().isFloatingPoint() ||
318 ST->getMemoryVT().isVector()) {
319 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
320 if (TLI.isTypeLegal(intVT)) {
321 // Expand to a bitconvert of the value to the integer type of the
322 // same size, then a (misaligned) int store.
323 // FIXME: Does not handle truncating floating point stores!
324 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
325 Result = DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
326 ST->isVolatile(), ST->isNonTemporal(), Alignment);
327 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
330 // Do a (aligned) store to a stack slot, then copy from the stack slot
331 // to the final destination using (unaligned) integer loads and stores.
332 EVT StoredVT = ST->getMemoryVT();
334 TLI.getRegisterType(*DAG.getContext(),
335 EVT::getIntegerVT(*DAG.getContext(),
336 StoredVT.getSizeInBits()));
337 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
338 unsigned RegBytes = RegVT.getSizeInBits() / 8;
339 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
341 // Make sure the stack slot is also aligned for the register type.
342 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
344 // Perform the original store, only redirected to the stack slot.
345 SDValue Store = DAG.getTruncStore(Chain, dl,
346 Val, StackPtr, MachinePointerInfo(),
347 StoredVT, false, false, 0);
348 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy(AS));
349 SmallVector<SDValue, 8> Stores;
352 // Do all but one copies using the full register width.
353 for (unsigned i = 1; i < NumRegs; i++) {
354 // Load one integer register's worth from the stack slot.
355 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr,
356 MachinePointerInfo(),
357 false, false, false, 0);
358 // Store it to the final location. Remember the store.
359 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
360 ST->getPointerInfo().getWithOffset(Offset),
361 ST->isVolatile(), ST->isNonTemporal(),
362 MinAlign(ST->getAlignment(), Offset)));
363 // Increment the pointers.
365 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
367 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
370 // The last store may be partial. Do a truncating store. On big-endian
371 // machines this requires an extending load from the stack slot to ensure
372 // that the bits are in the right place.
373 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
374 8 * (StoredBytes - Offset));
376 // Load from the stack slot.
377 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
378 MachinePointerInfo(),
379 MemVT, false, false, 0);
381 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
383 .getWithOffset(Offset),
384 MemVT, ST->isVolatile(),
386 MinAlign(ST->getAlignment(), Offset),
388 // The order of the stores doesn't matter - say it with a TokenFactor.
390 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
392 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
395 assert(ST->getMemoryVT().isInteger() &&
396 !ST->getMemoryVT().isVector() &&
397 "Unaligned store of unknown type.");
398 // Get the half-size VT
399 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext());
400 int NumBits = NewStoredVT.getSizeInBits();
401 int IncrementSize = NumBits / 8;
403 // Divide the stored value in two parts.
404 SDValue ShiftAmount = DAG.getConstant(NumBits,
405 TLI.getShiftAmountTy(Val.getValueType()));
407 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
409 // Store the two parts
410 SDValue Store1, Store2;
411 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
412 ST->getPointerInfo(), NewStoredVT,
413 ST->isVolatile(), ST->isNonTemporal(), Alignment);
415 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
416 DAG.getConstant(IncrementSize, TLI.getPointerTy(AS)));
417 Alignment = MinAlign(Alignment, IncrementSize);
418 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
419 ST->getPointerInfo().getWithOffset(IncrementSize),
420 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(),
421 Alignment, ST->getTBAAInfo());
424 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
425 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
428 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
430 ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
431 const TargetLowering &TLI,
432 SDValue &ValResult, SDValue &ChainResult) {
433 assert(LD->getAddressingMode() == ISD::UNINDEXED &&
434 "unaligned indexed loads not implemented!");
435 SDValue Chain = LD->getChain();
436 SDValue Ptr = LD->getBasePtr();
437 EVT VT = LD->getValueType(0);
438 EVT LoadedVT = LD->getMemoryVT();
440 if (VT.isFloatingPoint() || VT.isVector()) {
441 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
442 if (TLI.isTypeLegal(intVT) && TLI.isTypeLegal(LoadedVT)) {
443 // Expand to a (misaligned) integer load of the same size,
444 // then bitconvert to floating point or vector.
445 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr,
446 LD->getMemOperand());
447 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad);
449 Result = DAG.getNode(VT.isFloatingPoint() ? ISD::FP_EXTEND :
450 ISD::ANY_EXTEND, dl, VT, Result);
457 // Copy the value to a (aligned) stack slot using (unaligned) integer
458 // loads and stores, then do a (aligned) load from the stack slot.
459 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
460 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
461 unsigned RegBytes = RegVT.getSizeInBits() / 8;
462 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
464 // Make sure the stack slot is also aligned for the register type.
465 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
467 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
468 SmallVector<SDValue, 8> Stores;
469 SDValue StackPtr = StackBase;
472 // Do all but one copies using the full register width.
473 for (unsigned i = 1; i < NumRegs; i++) {
474 // Load one integer register's worth from the original location.
475 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr,
476 LD->getPointerInfo().getWithOffset(Offset),
477 LD->isVolatile(), LD->isNonTemporal(),
479 MinAlign(LD->getAlignment(), Offset),
481 // Follow the load with a store to the stack slot. Remember the store.
482 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
483 MachinePointerInfo(), false, false, 0));
484 // Increment the pointers.
486 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
487 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
491 // The last copy may be partial. Do an extending load.
492 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
493 8 * (LoadedBytes - Offset));
494 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
495 LD->getPointerInfo().getWithOffset(Offset),
496 MemVT, LD->isVolatile(),
498 MinAlign(LD->getAlignment(), Offset),
500 // Follow the load with a store to the stack slot. Remember the store.
501 // On big-endian machines this requires a truncating store to ensure
502 // that the bits end up in the right place.
503 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
504 MachinePointerInfo(), MemVT,
507 // The order of the stores doesn't matter - say it with a TokenFactor.
508 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
511 // Finally, perform the original load only redirected to the stack slot.
512 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
513 MachinePointerInfo(), LoadedVT, false, false, 0);
515 // Callers expect a MERGE_VALUES node.
520 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
521 "Unaligned load of unsupported type.");
523 // Compute the new VT that is half the size of the old one. This is an
525 unsigned NumBits = LoadedVT.getSizeInBits();
527 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
530 unsigned Alignment = LD->getAlignment();
531 unsigned IncrementSize = NumBits / 8;
532 ISD::LoadExtType HiExtType = LD->getExtensionType();
534 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
535 if (HiExtType == ISD::NON_EXTLOAD)
536 HiExtType = ISD::ZEXTLOAD;
538 // Load the value in two parts
540 if (TLI.isLittleEndian()) {
541 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
542 NewLoadedVT, LD->isVolatile(),
543 LD->isNonTemporal(), Alignment, LD->getTBAAInfo());
544 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
545 DAG.getConstant(IncrementSize, Ptr.getValueType()));
546 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr,
547 LD->getPointerInfo().getWithOffset(IncrementSize),
548 NewLoadedVT, LD->isVolatile(),
549 LD->isNonTemporal(), MinAlign(Alignment, IncrementSize),
552 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(),
553 NewLoadedVT, LD->isVolatile(),
554 LD->isNonTemporal(), Alignment, LD->getTBAAInfo());
555 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
556 DAG.getConstant(IncrementSize, Ptr.getValueType()));
557 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
558 LD->getPointerInfo().getWithOffset(IncrementSize),
559 NewLoadedVT, LD->isVolatile(),
560 LD->isNonTemporal(), MinAlign(Alignment, IncrementSize),
564 // aggregate the two parts
565 SDValue ShiftAmount = DAG.getConstant(NumBits,
566 TLI.getShiftAmountTy(Hi.getValueType()));
567 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
568 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
570 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
577 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
578 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
579 /// is necessary to spill the vector being inserted into to memory, perform
580 /// the insert there, and then read the result back.
581 SDValue SelectionDAGLegalize::
582 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
588 // If the target doesn't support this, we have to spill the input vector
589 // to a temporary stack slot, update the element, then reload it. This is
590 // badness. We could also load the value into a vector register (either
591 // with a "move to register" or "extload into register" instruction, then
592 // permute it into place, if the idx is a constant and if the idx is
593 // supported by the target.
594 EVT VT = Tmp1.getValueType();
595 EVT EltVT = VT.getVectorElementType();
596 EVT IdxVT = Tmp3.getValueType();
597 EVT PtrVT = TLI.getPointerTy();
598 SDValue StackPtr = DAG.CreateStackTemporary(VT);
600 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
603 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
604 MachinePointerInfo::getFixedStack(SPFI),
607 // Truncate or zero extend offset to target pointer type.
608 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
609 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
610 // Add the offset to the index.
611 unsigned EltSize = EltVT.getSizeInBits()/8;
612 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
613 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
614 // Store the scalar value.
615 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT,
617 // Load the updated vector.
618 return DAG.getLoad(VT, dl, Ch, StackPtr,
619 MachinePointerInfo::getFixedStack(SPFI), false, false,
624 SDValue SelectionDAGLegalize::
625 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, SDLoc dl) {
626 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
627 // SCALAR_TO_VECTOR requires that the type of the value being inserted
628 // match the element type of the vector being created, except for
629 // integers in which case the inserted value can be over width.
630 EVT EltVT = Vec.getValueType().getVectorElementType();
631 if (Val.getValueType() == EltVT ||
632 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
633 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
634 Vec.getValueType(), Val);
636 unsigned NumElts = Vec.getValueType().getVectorNumElements();
637 // We generate a shuffle of InVec and ScVec, so the shuffle mask
638 // should be 0,1,2,3,4,5... with the appropriate element replaced with
640 SmallVector<int, 8> ShufOps;
641 for (unsigned i = 0; i != NumElts; ++i)
642 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
644 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
648 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
651 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
652 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
653 // FIXME: We shouldn't do this for TargetConstantFP's.
654 // FIXME: move this to the DAG Combiner! Note that we can't regress due
655 // to phase ordering between legalized code and the dag combiner. This
656 // probably means that we need to integrate dag combiner and legalizer
658 // We generally can't do this one for long doubles.
659 SDValue Chain = ST->getChain();
660 SDValue Ptr = ST->getBasePtr();
661 unsigned Alignment = ST->getAlignment();
662 bool isVolatile = ST->isVolatile();
663 bool isNonTemporal = ST->isNonTemporal();
664 const MDNode *TBAAInfo = ST->getTBAAInfo();
666 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
667 if (CFP->getValueType(0) == MVT::f32 &&
668 TLI.isTypeLegal(MVT::i32)) {
669 SDValue Con = DAG.getConstant(CFP->getValueAPF().
670 bitcastToAPInt().zextOrTrunc(32),
672 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
673 isVolatile, isNonTemporal, Alignment, TBAAInfo);
676 if (CFP->getValueType(0) == MVT::f64) {
677 // If this target supports 64-bit registers, do a single 64-bit store.
678 if (TLI.isTypeLegal(MVT::i64)) {
679 SDValue Con = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
680 zextOrTrunc(64), MVT::i64);
681 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
682 isVolatile, isNonTemporal, Alignment, TBAAInfo);
685 if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) {
686 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
687 // stores. If the target supports neither 32- nor 64-bits, this
688 // xform is certainly not worth it.
689 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
690 SDValue Lo = DAG.getConstant(IntVal.trunc(32), MVT::i32);
691 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
692 if (TLI.isBigEndian()) std::swap(Lo, Hi);
694 Lo = DAG.getStore(Chain, dl, Lo, Ptr, ST->getPointerInfo(), isVolatile,
695 isNonTemporal, Alignment, TBAAInfo);
696 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
697 DAG.getConstant(4, Ptr.getValueType()));
698 Hi = DAG.getStore(Chain, dl, Hi, Ptr,
699 ST->getPointerInfo().getWithOffset(4),
700 isVolatile, isNonTemporal, MinAlign(Alignment, 4U),
703 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
707 return SDValue(0, 0);
710 void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
711 StoreSDNode *ST = cast<StoreSDNode>(Node);
712 SDValue Chain = ST->getChain();
713 SDValue Ptr = ST->getBasePtr();
716 unsigned Alignment = ST->getAlignment();
717 bool isVolatile = ST->isVolatile();
718 bool isNonTemporal = ST->isNonTemporal();
719 const MDNode *TBAAInfo = ST->getTBAAInfo();
721 if (!ST->isTruncatingStore()) {
722 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
723 ReplaceNode(ST, OptStore);
728 SDValue Value = ST->getValue();
729 MVT VT = Value.getSimpleValueType();
730 switch (TLI.getOperationAction(ISD::STORE, VT)) {
731 default: llvm_unreachable("This action is not supported yet!");
732 case TargetLowering::Legal: {
733 // If this is an unaligned store and the target doesn't support it,
735 unsigned AS = ST->getAddressSpace();
736 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT(), AS)) {
737 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
738 unsigned ABIAlignment= TLI.getDataLayout()->getABITypeAlignment(Ty);
739 if (ST->getAlignment() < ABIAlignment)
740 ExpandUnalignedStore(cast<StoreSDNode>(Node),
745 case TargetLowering::Custom: {
746 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
748 ReplaceNode(SDValue(Node, 0), Res);
751 case TargetLowering::Promote: {
752 MVT NVT = TLI.getTypeToPromoteTo(ISD::STORE, VT);
753 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
754 "Can only promote stores to same size type");
755 Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value);
757 DAG.getStore(Chain, dl, Value, Ptr,
758 ST->getPointerInfo(), isVolatile,
759 isNonTemporal, Alignment, TBAAInfo);
760 ReplaceNode(SDValue(Node, 0), Result);
767 SDValue Value = ST->getValue();
769 EVT StVT = ST->getMemoryVT();
770 unsigned StWidth = StVT.getSizeInBits();
772 if (StWidth != StVT.getStoreSizeInBits()) {
773 // Promote to a byte-sized store with upper bits zero if not
774 // storing an integral number of bytes. For example, promote
775 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
776 EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
777 StVT.getStoreSizeInBits());
778 Value = DAG.getZeroExtendInReg(Value, dl, StVT);
780 DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
781 NVT, isVolatile, isNonTemporal, Alignment,
783 ReplaceNode(SDValue(Node, 0), Result);
784 } else if (StWidth & (StWidth - 1)) {
785 // If not storing a power-of-2 number of bits, expand as two stores.
786 assert(!StVT.isVector() && "Unsupported truncstore!");
787 unsigned RoundWidth = 1 << Log2_32(StWidth);
788 assert(RoundWidth < StWidth);
789 unsigned ExtraWidth = StWidth - RoundWidth;
790 assert(ExtraWidth < RoundWidth);
791 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
792 "Store size not an integral number of bytes!");
793 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
794 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
796 unsigned IncrementSize;
798 if (TLI.isLittleEndian()) {
799 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
800 // Store the bottom RoundWidth bits.
801 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
803 isVolatile, isNonTemporal, Alignment,
806 // Store the remaining ExtraWidth bits.
807 IncrementSize = RoundWidth / 8;
808 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
809 DAG.getConstant(IncrementSize, Ptr.getValueType()));
810 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
811 DAG.getConstant(RoundWidth,
812 TLI.getShiftAmountTy(Value.getValueType())));
813 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr,
814 ST->getPointerInfo().getWithOffset(IncrementSize),
815 ExtraVT, isVolatile, isNonTemporal,
816 MinAlign(Alignment, IncrementSize), TBAAInfo);
818 // Big endian - avoid unaligned stores.
819 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
820 // Store the top RoundWidth bits.
821 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
822 DAG.getConstant(ExtraWidth,
823 TLI.getShiftAmountTy(Value.getValueType())));
824 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, ST->getPointerInfo(),
825 RoundVT, isVolatile, isNonTemporal, Alignment,
828 // Store the remaining ExtraWidth bits.
829 IncrementSize = RoundWidth / 8;
830 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
831 DAG.getConstant(IncrementSize, Ptr.getValueType()));
832 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr,
833 ST->getPointerInfo().getWithOffset(IncrementSize),
834 ExtraVT, isVolatile, isNonTemporal,
835 MinAlign(Alignment, IncrementSize), TBAAInfo);
838 // The order of the stores doesn't matter.
839 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
840 ReplaceNode(SDValue(Node, 0), Result);
842 switch (TLI.getTruncStoreAction(ST->getValue().getSimpleValueType(),
843 StVT.getSimpleVT())) {
844 default: llvm_unreachable("This action is not supported yet!");
845 case TargetLowering::Legal: {
846 unsigned AS = ST->getAddressSpace();
847 // If this is an unaligned store and the target doesn't support it,
849 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT(), AS)) {
850 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
851 unsigned ABIAlignment= TLI.getDataLayout()->getABITypeAlignment(Ty);
852 if (ST->getAlignment() < ABIAlignment)
853 ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this);
857 case TargetLowering::Custom: {
858 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
860 ReplaceNode(SDValue(Node, 0), Res);
863 case TargetLowering::Expand:
864 assert(!StVT.isVector() &&
865 "Vector Stores are handled in LegalizeVectorOps");
867 // TRUNCSTORE:i16 i32 -> STORE i16
868 assert(TLI.isTypeLegal(StVT) &&
869 "Do not know how to expand this store!");
870 Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value);
872 DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
873 isVolatile, isNonTemporal, Alignment, TBAAInfo);
874 ReplaceNode(SDValue(Node, 0), Result);
881 void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
882 LoadSDNode *LD = cast<LoadSDNode>(Node);
883 SDValue Chain = LD->getChain(); // The chain.
884 SDValue Ptr = LD->getBasePtr(); // The base pointer.
885 SDValue Value; // The value returned by the load op.
888 ISD::LoadExtType ExtType = LD->getExtensionType();
889 if (ExtType == ISD::NON_EXTLOAD) {
890 MVT VT = Node->getSimpleValueType(0);
891 SDValue RVal = SDValue(Node, 0);
892 SDValue RChain = SDValue(Node, 1);
894 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
895 default: llvm_unreachable("This action is not supported yet!");
896 case TargetLowering::Legal: {
897 unsigned AS = LD->getAddressSpace();
898 // If this is an unaligned load and the target doesn't support it,
900 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT(), AS)) {
901 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
902 unsigned ABIAlignment =
903 TLI.getDataLayout()->getABITypeAlignment(Ty);
904 if (LD->getAlignment() < ABIAlignment){
905 ExpandUnalignedLoad(cast<LoadSDNode>(Node), DAG, TLI, RVal, RChain);
910 case TargetLowering::Custom: {
911 SDValue Res = TLI.LowerOperation(RVal, DAG);
914 RChain = Res.getValue(1);
918 case TargetLowering::Promote: {
919 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
920 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
921 "Can only promote loads to same size type");
923 SDValue Res = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getMemOperand());
924 RVal = DAG.getNode(ISD::BITCAST, dl, VT, Res);
925 RChain = Res.getValue(1);
929 if (RChain.getNode() != Node) {
930 assert(RVal.getNode() != Node && "Load must be completely replaced");
931 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), RVal);
932 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), RChain);
938 EVT SrcVT = LD->getMemoryVT();
939 unsigned SrcWidth = SrcVT.getSizeInBits();
940 unsigned Alignment = LD->getAlignment();
941 bool isVolatile = LD->isVolatile();
942 bool isNonTemporal = LD->isNonTemporal();
943 const MDNode *TBAAInfo = LD->getTBAAInfo();
945 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
946 // Some targets pretend to have an i1 loading operation, and actually
947 // load an i8. This trick is correct for ZEXTLOAD because the top 7
948 // bits are guaranteed to be zero; it helps the optimizers understand
949 // that these bits are zero. It is also useful for EXTLOAD, since it
950 // tells the optimizers that those bits are undefined. It would be
951 // nice to have an effective generic way of getting these benefits...
952 // Until such a way is found, don't insist on promoting i1 here.
954 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
955 // Promote to a byte-sized load if not loading an integral number of
956 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
957 unsigned NewWidth = SrcVT.getStoreSizeInBits();
958 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
961 // The extra bits are guaranteed to be zero, since we stored them that
962 // way. A zext load from NVT thus automatically gives zext from SrcVT.
964 ISD::LoadExtType NewExtType =
965 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
968 DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
969 Chain, Ptr, LD->getPointerInfo(),
970 NVT, isVolatile, isNonTemporal, Alignment, TBAAInfo);
972 Ch = Result.getValue(1); // The chain.
974 if (ExtType == ISD::SEXTLOAD)
975 // Having the top bits zero doesn't help when sign extending.
976 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
977 Result.getValueType(),
978 Result, DAG.getValueType(SrcVT));
979 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
980 // All the top bits are guaranteed to be zero - inform the optimizers.
981 Result = DAG.getNode(ISD::AssertZext, dl,
982 Result.getValueType(), Result,
983 DAG.getValueType(SrcVT));
987 } else if (SrcWidth & (SrcWidth - 1)) {
988 // If not loading a power-of-2 number of bits, expand as two loads.
989 assert(!SrcVT.isVector() && "Unsupported extload!");
990 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
991 assert(RoundWidth < SrcWidth);
992 unsigned ExtraWidth = SrcWidth - RoundWidth;
993 assert(ExtraWidth < RoundWidth);
994 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
995 "Load size not an integral number of bytes!");
996 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
997 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
999 unsigned IncrementSize;
1001 if (TLI.isLittleEndian()) {
1002 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1003 // Load the bottom RoundWidth bits.
1004 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0),
1006 LD->getPointerInfo(), RoundVT, isVolatile,
1007 isNonTemporal, Alignment, TBAAInfo);
1009 // Load the remaining ExtraWidth bits.
1010 IncrementSize = RoundWidth / 8;
1011 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1012 DAG.getConstant(IncrementSize, Ptr.getValueType()));
1013 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
1014 LD->getPointerInfo().getWithOffset(IncrementSize),
1015 ExtraVT, isVolatile, isNonTemporal,
1016 MinAlign(Alignment, IncrementSize), TBAAInfo);
1018 // Build a factor node to remember that this load is independent of
1020 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1023 // Move the top bits to the right place.
1024 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1025 DAG.getConstant(RoundWidth,
1026 TLI.getShiftAmountTy(Hi.getValueType())));
1028 // Join the hi and lo parts.
1029 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1031 // Big endian - avoid unaligned loads.
1032 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1033 // Load the top RoundWidth bits.
1034 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
1035 LD->getPointerInfo(), RoundVT, isVolatile,
1036 isNonTemporal, Alignment, TBAAInfo);
1038 // Load the remaining ExtraWidth bits.
1039 IncrementSize = RoundWidth / 8;
1040 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1041 DAG.getConstant(IncrementSize, Ptr.getValueType()));
1042 Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
1043 dl, Node->getValueType(0), Chain, Ptr,
1044 LD->getPointerInfo().getWithOffset(IncrementSize),
1045 ExtraVT, isVolatile, isNonTemporal,
1046 MinAlign(Alignment, IncrementSize), TBAAInfo);
1048 // Build a factor node to remember that this load is independent of
1050 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1053 // Move the top bits to the right place.
1054 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1055 DAG.getConstant(ExtraWidth,
1056 TLI.getShiftAmountTy(Hi.getValueType())));
1058 // Join the hi and lo parts.
1059 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1064 bool isCustom = false;
1065 switch (TLI.getLoadExtAction(ExtType, SrcVT.getSimpleVT())) {
1066 default: llvm_unreachable("This action is not supported yet!");
1067 case TargetLowering::Custom:
1070 case TargetLowering::Legal: {
1071 Value = SDValue(Node, 0);
1072 Chain = SDValue(Node, 1);
1075 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1076 if (Res.getNode()) {
1078 Chain = Res.getValue(1);
1081 // If this is an unaligned load and the target doesn't support
1083 EVT MemVT = LD->getMemoryVT();
1084 unsigned AS = LD->getAddressSpace();
1085 if (!TLI.allowsUnalignedMemoryAccesses(MemVT, AS)) {
1087 LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1088 unsigned ABIAlignment =
1089 TLI.getDataLayout()->getABITypeAlignment(Ty);
1090 if (LD->getAlignment() < ABIAlignment){
1091 ExpandUnalignedLoad(cast<LoadSDNode>(Node),
1092 DAG, TLI, Value, Chain);
1098 case TargetLowering::Expand:
1099 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) &&
1100 TLI.isTypeLegal(SrcVT)) {
1101 SDValue Load = DAG.getLoad(SrcVT, dl, Chain, Ptr,
1102 LD->getMemOperand());
1106 ExtendOp = (SrcVT.isFloatingPoint() ?
1107 ISD::FP_EXTEND : ISD::ANY_EXTEND);
1109 case ISD::SEXTLOAD: ExtendOp = ISD::SIGN_EXTEND; break;
1110 case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break;
1111 default: llvm_unreachable("Unexpected extend load type!");
1113 Value = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
1114 Chain = Load.getValue(1);
1118 assert(!SrcVT.isVector() &&
1119 "Vector Loads are handled in LegalizeVectorOps");
1121 // FIXME: This does not work for vectors on most targets. Sign-
1122 // and zero-extend operations are currently folded into extending
1123 // loads, whether they are legal or not, and then we end up here
1124 // without any support for legalizing them.
1125 assert(ExtType != ISD::EXTLOAD &&
1126 "EXTLOAD should always be supported!");
1127 // Turn the unsupported load into an EXTLOAD followed by an
1128 // explicit zero/sign extend inreg.
1129 SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl,
1130 Node->getValueType(0),
1132 LD->getMemOperand());
1134 if (ExtType == ISD::SEXTLOAD)
1135 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1136 Result.getValueType(),
1137 Result, DAG.getValueType(SrcVT));
1139 ValRes = DAG.getZeroExtendInReg(Result, dl,
1140 SrcVT.getScalarType());
1142 Chain = Result.getValue(1);
1147 // Since loads produce two values, make sure to remember that we legalized
1149 if (Chain.getNode() != Node) {
1150 assert(Value.getNode() != Node && "Load must be completely replaced");
1151 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Value);
1152 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
1157 /// LegalizeOp - Return a legal replacement for the given operation, with
1158 /// all legal operands.
1159 void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
1160 if (Node->getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
1163 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1164 assert(TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) ==
1165 TargetLowering::TypeLegal &&
1166 "Unexpected illegal type!");
1168 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1169 assert((TLI.getTypeAction(*DAG.getContext(),
1170 Node->getOperand(i).getValueType()) ==
1171 TargetLowering::TypeLegal ||
1172 Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
1173 "Unexpected illegal type!");
1175 // Figure out the correct action; the way to query this varies by opcode
1176 TargetLowering::LegalizeAction Action = TargetLowering::Legal;
1177 bool SimpleFinishLegalizing = true;
1178 switch (Node->getOpcode()) {
1179 case ISD::INTRINSIC_W_CHAIN:
1180 case ISD::INTRINSIC_WO_CHAIN:
1181 case ISD::INTRINSIC_VOID:
1182 case ISD::STACKSAVE:
1183 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1186 Action = TLI.getOperationAction(Node->getOpcode(),
1187 Node->getValueType(0));
1188 if (Action != TargetLowering::Promote)
1189 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1191 case ISD::SINT_TO_FP:
1192 case ISD::UINT_TO_FP:
1193 case ISD::EXTRACT_VECTOR_ELT:
1194 Action = TLI.getOperationAction(Node->getOpcode(),
1195 Node->getOperand(0).getValueType());
1197 case ISD::FP_ROUND_INREG:
1198 case ISD::SIGN_EXTEND_INREG: {
1199 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
1200 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
1203 case ISD::ATOMIC_STORE: {
1204 Action = TLI.getOperationAction(Node->getOpcode(),
1205 Node->getOperand(2).getValueType());
1208 case ISD::SELECT_CC:
1211 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
1212 Node->getOpcode() == ISD::SETCC ? 2 : 1;
1213 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
1214 MVT OpVT = Node->getOperand(CompareOperand).getSimpleValueType();
1215 ISD::CondCode CCCode =
1216 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
1217 Action = TLI.getCondCodeAction(CCCode, OpVT);
1218 if (Action == TargetLowering::Legal) {
1219 if (Node->getOpcode() == ISD::SELECT_CC)
1220 Action = TLI.getOperationAction(Node->getOpcode(),
1221 Node->getValueType(0));
1223 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
1229 // FIXME: Model these properly. LOAD and STORE are complicated, and
1230 // STORE expects the unlegalized operand in some cases.
1231 SimpleFinishLegalizing = false;
1233 case ISD::CALLSEQ_START:
1234 case ISD::CALLSEQ_END:
1235 // FIXME: This shouldn't be necessary. These nodes have special properties
1236 // dealing with the recursive nature of legalization. Removing this
1237 // special case should be done as part of making LegalizeDAG non-recursive.
1238 SimpleFinishLegalizing = false;
1240 case ISD::EXTRACT_ELEMENT:
1241 case ISD::FLT_ROUNDS_:
1249 case ISD::MERGE_VALUES:
1250 case ISD::EH_RETURN:
1251 case ISD::FRAME_TO_ARGS_OFFSET:
1252 case ISD::EH_SJLJ_SETJMP:
1253 case ISD::EH_SJLJ_LONGJMP:
1254 // These operations lie about being legal: when they claim to be legal,
1255 // they should actually be expanded.
1256 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1257 if (Action == TargetLowering::Legal)
1258 Action = TargetLowering::Expand;
1260 case ISD::INIT_TRAMPOLINE:
1261 case ISD::ADJUST_TRAMPOLINE:
1262 case ISD::FRAMEADDR:
1263 case ISD::RETURNADDR:
1264 // These operations lie about being legal: when they claim to be legal,
1265 // they should actually be custom-lowered.
1266 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1267 if (Action == TargetLowering::Legal)
1268 Action = TargetLowering::Custom;
1270 case ISD::DEBUGTRAP:
1271 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1272 if (Action == TargetLowering::Expand) {
1273 // replace ISD::DEBUGTRAP with ISD::TRAP
1275 NewVal = DAG.getNode(ISD::TRAP, SDLoc(Node), Node->getVTList(),
1276 Node->getOperand(0));
1277 ReplaceNode(Node, NewVal.getNode());
1278 LegalizeOp(NewVal.getNode());
1284 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1285 Action = TargetLowering::Legal;
1287 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1292 if (SimpleFinishLegalizing) {
1293 SDNode *NewNode = Node;
1294 switch (Node->getOpcode()) {
1301 // Legalizing shifts/rotates requires adjusting the shift amount
1302 // to the appropriate width.
1303 if (!Node->getOperand(1).getValueType().isVector()) {
1305 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1306 Node->getOperand(1));
1307 HandleSDNode Handle(SAO);
1308 LegalizeOp(SAO.getNode());
1309 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1313 case ISD::SRL_PARTS:
1314 case ISD::SRA_PARTS:
1315 case ISD::SHL_PARTS:
1316 // Legalizing shifts/rotates requires adjusting the shift amount
1317 // to the appropriate width.
1318 if (!Node->getOperand(2).getValueType().isVector()) {
1320 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1321 Node->getOperand(2));
1322 HandleSDNode Handle(SAO);
1323 LegalizeOp(SAO.getNode());
1324 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1325 Node->getOperand(1),
1331 if (NewNode != Node) {
1332 DAG.ReplaceAllUsesWith(Node, NewNode);
1333 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1334 DAG.TransferDbgValues(SDValue(Node, i), SDValue(NewNode, i));
1339 case TargetLowering::Legal:
1341 case TargetLowering::Custom: {
1342 // FIXME: The handling for custom lowering with multiple results is
1344 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1345 if (Res.getNode()) {
1346 SmallVector<SDValue, 8> ResultVals;
1347 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
1349 ResultVals.push_back(Res);
1351 ResultVals.push_back(Res.getValue(i));
1353 if (Res.getNode() != Node || Res.getResNo() != 0) {
1354 DAG.ReplaceAllUsesWith(Node, ResultVals.data());
1355 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1356 DAG.TransferDbgValues(SDValue(Node, i), ResultVals[i]);
1363 case TargetLowering::Expand:
1366 case TargetLowering::Promote:
1372 switch (Node->getOpcode()) {
1379 llvm_unreachable("Do not know how to legalize this operator!");
1381 case ISD::CALLSEQ_START:
1382 case ISD::CALLSEQ_END:
1385 return LegalizeLoadOps(Node);
1388 return LegalizeStoreOps(Node);
1393 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1394 SDValue Vec = Op.getOperand(0);
1395 SDValue Idx = Op.getOperand(1);
1398 // Before we generate a new store to a temporary stack slot, see if there is
1399 // already one that we can use. There often is because when we scalarize
1400 // vector operations (using SelectionDAG::UnrollVectorOp for example) a whole
1401 // series of EXTRACT_VECTOR_ELT nodes are generated, one for each element in
1402 // the vector. If all are expanded here, we don't want one store per vector
1404 SDValue StackPtr, Ch;
1405 for (SDNode::use_iterator UI = Vec.getNode()->use_begin(),
1406 UE = Vec.getNode()->use_end(); UI != UE; ++UI) {
1408 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(User)) {
1409 if (ST->isIndexed() || ST->isTruncatingStore() ||
1410 ST->getValue() != Vec)
1413 // Make sure that nothing else could have stored into the destination of
1415 if (!ST->getChain().reachesChainWithoutSideEffects(DAG.getEntryNode()))
1418 StackPtr = ST->getBasePtr();
1419 Ch = SDValue(ST, 0);
1424 if (!Ch.getNode()) {
1425 // Store the value to a temporary stack slot, then LOAD the returned part.
1426 StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1427 Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1428 MachinePointerInfo(), false, false, 0);
1431 // Add the offset to the index.
1433 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1434 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1435 DAG.getConstant(EltSize, Idx.getValueType()));
1437 Idx = DAG.getZExtOrTrunc(Idx, dl, TLI.getPointerTy());
1438 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1440 if (Op.getValueType().isVector())
1441 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,MachinePointerInfo(),
1442 false, false, false, 0);
1443 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
1444 MachinePointerInfo(),
1445 Vec.getValueType().getVectorElementType(),
1449 SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
1450 assert(Op.getValueType().isVector() && "Non-vector insert subvector!");
1452 SDValue Vec = Op.getOperand(0);
1453 SDValue Part = Op.getOperand(1);
1454 SDValue Idx = Op.getOperand(2);
1457 // Store the value to a temporary stack slot, then LOAD the returned part.
1459 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1460 int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1461 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1463 // First store the whole vector.
1464 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo,
1467 // Then store the inserted part.
1469 // Add the offset to the index.
1471 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1473 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1474 DAG.getConstant(EltSize, Idx.getValueType()));
1475 Idx = DAG.getZExtOrTrunc(Idx, dl, TLI.getPointerTy());
1477 SDValue SubStackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
1480 // Store the subvector.
1481 Ch = DAG.getStore(DAG.getEntryNode(), dl, Part, SubStackPtr,
1482 MachinePointerInfo(), false, false, 0);
1484 // Finally, load the updated vector.
1485 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo,
1486 false, false, false, 0);
1489 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1490 // We can't handle this case efficiently. Allocate a sufficiently
1491 // aligned object on the stack, store each element into it, then load
1492 // the result as a vector.
1493 // Create the stack frame object.
1494 EVT VT = Node->getValueType(0);
1495 EVT EltVT = VT.getVectorElementType();
1497 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1498 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1499 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1501 // Emit a store of each element to the stack slot.
1502 SmallVector<SDValue, 8> Stores;
1503 unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1504 // Store (in the right endianness) the elements to memory.
1505 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1506 // Ignore undef elements.
1507 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1509 unsigned Offset = TypeByteSize*i;
1511 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
1512 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1514 // If the destination vector element type is narrower than the source
1515 // element type, only store the bits necessary.
1516 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1517 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1518 Node->getOperand(i), Idx,
1519 PtrInfo.getWithOffset(Offset),
1520 EltVT, false, false, 0));
1522 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
1523 Node->getOperand(i), Idx,
1524 PtrInfo.getWithOffset(Offset),
1529 if (!Stores.empty()) // Not all undef elements?
1530 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1531 &Stores[0], Stores.size());
1533 StoreChain = DAG.getEntryNode();
1535 // Result is a load from the stack slot.
1536 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo,
1537 false, false, false, 0);
1540 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
1542 SDValue Tmp1 = Node->getOperand(0);
1543 SDValue Tmp2 = Node->getOperand(1);
1545 // Get the sign bit of the RHS. First obtain a value that has the same
1546 // sign as the sign bit, i.e. negative if and only if the sign bit is 1.
1548 EVT FloatVT = Tmp2.getValueType();
1549 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits());
1550 if (TLI.isTypeLegal(IVT)) {
1551 // Convert to an integer with the same sign bit.
1552 SignBit = DAG.getNode(ISD::BITCAST, dl, IVT, Tmp2);
1554 // Store the float to memory, then load the sign part out as an integer.
1555 MVT LoadTy = TLI.getPointerTy();
1556 // First create a temporary that is aligned for both the load and store.
1557 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1558 // Then store the float to it.
1560 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, MachinePointerInfo(),
1562 if (TLI.isBigEndian()) {
1563 assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1564 // Load out a legal integer with the same sign bit as the float.
1565 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, MachinePointerInfo(),
1566 false, false, false, 0);
1567 } else { // Little endian
1568 SDValue LoadPtr = StackPtr;
1569 // The float may be wider than the integer we are going to load. Advance
1570 // the pointer so that the loaded integer will contain the sign bit.
1571 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits();
1572 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8;
1573 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(), LoadPtr,
1574 DAG.getConstant(ByteOffset, LoadPtr.getValueType()));
1575 // Load a legal integer containing the sign bit.
1576 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(),
1577 false, false, false, 0);
1578 // Move the sign bit to the top bit of the loaded integer.
1579 unsigned BitShift = LoadTy.getSizeInBits() -
1580 (FloatVT.getSizeInBits() - 8 * ByteOffset);
1581 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?");
1583 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit,
1584 DAG.getConstant(BitShift,
1585 TLI.getShiftAmountTy(SignBit.getValueType())));
1588 // Now get the sign bit proper, by seeing whether the value is negative.
1589 SignBit = DAG.getSetCC(dl, getSetCCResultType(SignBit.getValueType()),
1590 SignBit, DAG.getConstant(0, SignBit.getValueType()),
1592 // Get the absolute value of the result.
1593 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1594 // Select between the nabs and abs value based on the sign bit of
1596 return DAG.getSelect(dl, AbsVal.getValueType(), SignBit,
1597 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1601 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1602 SmallVectorImpl<SDValue> &Results) {
1603 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1604 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1605 " not tell us which reg is the stack pointer!");
1607 EVT VT = Node->getValueType(0);
1608 SDValue Tmp1 = SDValue(Node, 0);
1609 SDValue Tmp2 = SDValue(Node, 1);
1610 SDValue Tmp3 = Node->getOperand(2);
1611 SDValue Chain = Tmp1.getOperand(0);
1613 // Chain the dynamic stack allocation so that it doesn't modify the stack
1614 // pointer when other instructions are using the stack.
1615 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
1618 SDValue Size = Tmp2.getOperand(1);
1619 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1620 Chain = SP.getValue(1);
1621 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1622 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
1623 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1624 if (Align > StackAlign)
1625 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
1626 DAG.getConstant(-(uint64_t)Align, VT));
1627 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1629 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1630 DAG.getIntPtrConstant(0, true), SDValue(),
1633 Results.push_back(Tmp1);
1634 Results.push_back(Tmp2);
1637 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
1638 /// condition code CC on the current target.
1640 /// If the SETCC has been legalized using AND / OR, then the legalized node
1641 /// will be stored in LHS. RHS and CC will be set to SDValue(). NeedInvert
1642 /// will be set to false.
1644 /// If the SETCC has been legalized by using getSetCCSwappedOperands(),
1645 /// then the values of LHS and RHS will be swapped, CC will be set to the
1646 /// new condition, and NeedInvert will be set to false.
1648 /// If the SETCC has been legalized using the inverse condcode, then LHS and
1649 /// RHS will be unchanged, CC will set to the inverted condcode, and NeedInvert
1650 /// will be set to true. The caller must invert the result of the SETCC with
1651 /// SelectionDAG::getNOT() or take equivalent action to swap the effect of a
1652 /// true/false result.
1654 /// \returns true if the SetCC has been legalized, false if it hasn't.
1655 bool SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1656 SDValue &LHS, SDValue &RHS,
1660 MVT OpVT = LHS.getSimpleValueType();
1661 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1663 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1664 default: llvm_unreachable("Unknown condition code action!");
1665 case TargetLowering::Legal:
1668 case TargetLowering::Expand: {
1669 ISD::CondCode InvCC = ISD::getSetCCSwappedOperands(CCCode);
1670 if (TLI.isCondCodeLegal(InvCC, OpVT)) {
1671 std::swap(LHS, RHS);
1672 CC = DAG.getCondCode(InvCC);
1675 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1678 default: llvm_unreachable("Don't know how to expand this condition!");
1680 assert(TLI.getCondCodeAction(ISD::SETOEQ, OpVT)
1681 == TargetLowering::Legal
1682 && "If SETO is expanded, SETOEQ must be legal!");
1683 CC1 = ISD::SETOEQ; CC2 = ISD::SETOEQ; Opc = ISD::AND; break;
1685 assert(TLI.getCondCodeAction(ISD::SETUNE, OpVT)
1686 == TargetLowering::Legal
1687 && "If SETUO is expanded, SETUNE must be legal!");
1688 CC1 = ISD::SETUNE; CC2 = ISD::SETUNE; Opc = ISD::OR; break;
1701 // If we are floating point, assign and break, otherwise fall through.
1702 if (!OpVT.isInteger()) {
1703 // We can use the 4th bit to tell if we are the unordered
1704 // or ordered version of the opcode.
1705 CC2 = ((unsigned)CCCode & 0x8U) ? ISD::SETUO : ISD::SETO;
1706 Opc = ((unsigned)CCCode & 0x8U) ? ISD::OR : ISD::AND;
1707 CC1 = (ISD::CondCode)(((int)CCCode & 0x7) | 0x10);
1710 // Fallthrough if we are unsigned integer.
1715 // We only support using the inverted operation, which is computed above
1716 // and not a different manner of supporting expanding these cases.
1717 llvm_unreachable("Don't know how to expand this condition!");
1720 // Try inverting the result of the inverse condition.
1721 InvCC = CCCode == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ;
1722 if (TLI.isCondCodeLegal(InvCC, OpVT)) {
1723 CC = DAG.getCondCode(InvCC);
1727 // If inverting the condition didn't work then we have no means to expand
1729 llvm_unreachable("Don't know how to expand this condition!");
1732 SDValue SetCC1, SetCC2;
1733 if (CCCode != ISD::SETO && CCCode != ISD::SETUO) {
1734 // If we aren't the ordered or unorder operation,
1735 // then the pattern is (LHS CC1 RHS) Opc (LHS CC2 RHS).
1736 SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1737 SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1739 // Otherwise, the pattern is (LHS CC1 LHS) Opc (RHS CC2 RHS)
1740 SetCC1 = DAG.getSetCC(dl, VT, LHS, LHS, CC1);
1741 SetCC2 = DAG.getSetCC(dl, VT, RHS, RHS, CC2);
1743 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1752 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
1753 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1754 /// a load from the stack slot to DestVT, extending it if needed.
1755 /// The resultant code need not be legal.
1756 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
1760 // Create the stack frame object.
1762 TLI.getDataLayout()->getPrefTypeAlignment(SrcOp.getValueType().
1763 getTypeForEVT(*DAG.getContext()));
1764 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1766 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1767 int SPFI = StackPtrFI->getIndex();
1768 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(SPFI);
1770 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
1771 unsigned SlotSize = SlotVT.getSizeInBits();
1772 unsigned DestSize = DestVT.getSizeInBits();
1773 Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
1774 unsigned DestAlign = TLI.getDataLayout()->getPrefTypeAlignment(DestType);
1776 // Emit a store to the stack slot. Use a truncstore if the input value is
1777 // later than DestVT.
1780 if (SrcSize > SlotSize)
1781 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1782 PtrInfo, SlotVT, false, false, SrcAlign);
1784 assert(SrcSize == SlotSize && "Invalid store");
1785 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1786 PtrInfo, false, false, SrcAlign);
1789 // Result is a load from the stack slot.
1790 if (SlotSize == DestSize)
1791 return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo,
1792 false, false, false, DestAlign);
1794 assert(SlotSize < DestSize && "Unknown extension!");
1795 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr,
1796 PtrInfo, SlotVT, false, false, DestAlign);
1799 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1801 // Create a vector sized/aligned stack slot, store the value to element #0,
1802 // then load the whole vector back out.
1803 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1805 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1806 int SPFI = StackPtrFI->getIndex();
1808 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0),
1810 MachinePointerInfo::getFixedStack(SPFI),
1811 Node->getValueType(0).getVectorElementType(),
1813 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
1814 MachinePointerInfo::getFixedStack(SPFI),
1815 false, false, false, 0);
1819 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
1820 /// support the operation, but do support the resultant vector type.
1821 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1822 unsigned NumElems = Node->getNumOperands();
1823 SDValue Value1, Value2;
1825 EVT VT = Node->getValueType(0);
1826 EVT OpVT = Node->getOperand(0).getValueType();
1827 EVT EltVT = VT.getVectorElementType();
1829 // If the only non-undef value is the low element, turn this into a
1830 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1831 bool isOnlyLowElement = true;
1832 bool MoreThanTwoValues = false;
1833 bool isConstant = true;
1834 for (unsigned i = 0; i < NumElems; ++i) {
1835 SDValue V = Node->getOperand(i);
1836 if (V.getOpcode() == ISD::UNDEF)
1839 isOnlyLowElement = false;
1840 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1843 if (!Value1.getNode()) {
1845 } else if (!Value2.getNode()) {
1848 } else if (V != Value1 && V != Value2) {
1849 MoreThanTwoValues = true;
1853 if (!Value1.getNode())
1854 return DAG.getUNDEF(VT);
1856 if (isOnlyLowElement)
1857 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1859 // If all elements are constants, create a load from the constant pool.
1861 SmallVector<Constant*, 16> CV;
1862 for (unsigned i = 0, e = NumElems; i != e; ++i) {
1863 if (ConstantFPSDNode *V =
1864 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1865 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1866 } else if (ConstantSDNode *V =
1867 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1869 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1871 // If OpVT and EltVT don't match, EltVT is not legal and the
1872 // element values have been promoted/truncated earlier. Undo this;
1873 // we don't want a v16i8 to become a v16i32 for example.
1874 const ConstantInt *CI = V->getConstantIntValue();
1875 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
1876 CI->getZExtValue()));
1879 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
1880 Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
1881 CV.push_back(UndefValue::get(OpNTy));
1884 Constant *CP = ConstantVector::get(CV);
1885 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
1886 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
1887 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
1888 MachinePointerInfo::getConstantPool(),
1889 false, false, false, Alignment);
1892 if (!MoreThanTwoValues) {
1893 SmallVector<int, 8> ShuffleVec(NumElems, -1);
1894 for (unsigned i = 0; i < NumElems; ++i) {
1895 SDValue V = Node->getOperand(i);
1896 if (V.getOpcode() == ISD::UNDEF)
1898 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
1900 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
1901 // Get the splatted value into the low element of a vector register.
1902 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
1904 if (Value2.getNode())
1905 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
1907 Vec2 = DAG.getUNDEF(VT);
1909 // Return shuffle(LowValVec, undef, <0,0,0,0>)
1910 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
1914 // Otherwise, we can't handle this case efficiently.
1915 return ExpandVectorBuildThroughStack(Node);
1918 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
1919 // does not fit into a register, return the lo part and set the hi part to the
1920 // by-reg argument. If it does fit into a single register, return the result
1921 // and leave the Hi part unset.
1922 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
1924 TargetLowering::ArgListTy Args;
1925 TargetLowering::ArgListEntry Entry;
1926 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1927 EVT ArgVT = Node->getOperand(i).getValueType();
1928 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1929 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
1930 Entry.isSExt = isSigned;
1931 Entry.isZExt = !isSigned;
1932 Args.push_back(Entry);
1934 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1935 TLI.getPointerTy());
1937 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
1939 // By default, the input chain to this libcall is the entry node of the
1940 // function. If the libcall is going to be emitted as a tail call then
1941 // TLI.isUsedByReturnOnly will change it to the right chain if the return
1942 // node which is being folded has a non-entry input chain.
1943 SDValue InChain = DAG.getEntryNode();
1945 // isTailCall may be true since the callee does not reference caller stack
1946 // frame. Check if it's in the right position.
1947 SDValue TCChain = InChain;
1948 bool isTailCall = TLI.isInTailCallPosition(DAG, Node, TCChain);
1953 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
1954 0, TLI.getLibcallCallingConv(LC), isTailCall,
1955 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
1956 Callee, Args, DAG, SDLoc(Node));
1957 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
1960 if (!CallInfo.second.getNode())
1961 // It's a tailcall, return the chain (which is the DAG root).
1962 return DAG.getRoot();
1964 return CallInfo.first;
1967 /// ExpandLibCall - Generate a libcall taking the given operands as arguments
1968 /// and returning a result of type RetVT.
1969 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, EVT RetVT,
1970 const SDValue *Ops, unsigned NumOps,
1971 bool isSigned, SDLoc dl) {
1972 TargetLowering::ArgListTy Args;
1973 Args.reserve(NumOps);
1975 TargetLowering::ArgListEntry Entry;
1976 for (unsigned i = 0; i != NumOps; ++i) {
1977 Entry.Node = Ops[i];
1978 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
1979 Entry.isSExt = isSigned;
1980 Entry.isZExt = !isSigned;
1981 Args.push_back(Entry);
1983 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1984 TLI.getPointerTy());
1986 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
1988 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
1989 false, 0, TLI.getLibcallCallingConv(LC),
1990 /*isTailCall=*/false,
1991 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
1992 Callee, Args, DAG, dl);
1993 std::pair<SDValue,SDValue> CallInfo = TLI.LowerCallTo(CLI);
1995 return CallInfo.first;
1998 // ExpandChainLibCall - Expand a node into a call to a libcall. Similar to
1999 // ExpandLibCall except that the first operand is the in-chain.
2000 std::pair<SDValue, SDValue>
2001 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
2004 SDValue InChain = Node->getOperand(0);
2006 TargetLowering::ArgListTy Args;
2007 TargetLowering::ArgListEntry Entry;
2008 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) {
2009 EVT ArgVT = Node->getOperand(i).getValueType();
2010 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2011 Entry.Node = Node->getOperand(i);
2013 Entry.isSExt = isSigned;
2014 Entry.isZExt = !isSigned;
2015 Args.push_back(Entry);
2017 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2018 TLI.getPointerTy());
2020 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2022 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
2023 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
2024 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2025 Callee, Args, DAG, SDLoc(Node));
2026 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2031 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
2032 RTLIB::Libcall Call_F32,
2033 RTLIB::Libcall Call_F64,
2034 RTLIB::Libcall Call_F80,
2035 RTLIB::Libcall Call_F128,
2036 RTLIB::Libcall Call_PPCF128) {
2038 switch (Node->getSimpleValueType(0).SimpleTy) {
2039 default: llvm_unreachable("Unexpected request for libcall!");
2040 case MVT::f32: LC = Call_F32; break;
2041 case MVT::f64: LC = Call_F64; break;
2042 case MVT::f80: LC = Call_F80; break;
2043 case MVT::f128: LC = Call_F128; break;
2044 case MVT::ppcf128: LC = Call_PPCF128; break;
2046 return ExpandLibCall(LC, Node, false);
2049 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
2050 RTLIB::Libcall Call_I8,
2051 RTLIB::Libcall Call_I16,
2052 RTLIB::Libcall Call_I32,
2053 RTLIB::Libcall Call_I64,
2054 RTLIB::Libcall Call_I128) {
2056 switch (Node->getSimpleValueType(0).SimpleTy) {
2057 default: llvm_unreachable("Unexpected request for libcall!");
2058 case MVT::i8: LC = Call_I8; break;
2059 case MVT::i16: LC = Call_I16; break;
2060 case MVT::i32: LC = Call_I32; break;
2061 case MVT::i64: LC = Call_I64; break;
2062 case MVT::i128: LC = Call_I128; break;
2064 return ExpandLibCall(LC, Node, isSigned);
2067 /// isDivRemLibcallAvailable - Return true if divmod libcall is available.
2068 static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
2069 const TargetLowering &TLI) {
2071 switch (Node->getSimpleValueType(0).SimpleTy) {
2072 default: llvm_unreachable("Unexpected request for libcall!");
2073 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2074 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2075 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2076 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2077 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2080 return TLI.getLibcallName(LC) != 0;
2083 /// useDivRem - Only issue divrem libcall if both quotient and remainder are
2085 static bool useDivRem(SDNode *Node, bool isSigned, bool isDIV) {
2086 // The other use might have been replaced with a divrem already.
2087 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2088 unsigned OtherOpcode = 0;
2090 OtherOpcode = isDIV ? ISD::SREM : ISD::SDIV;
2092 OtherOpcode = isDIV ? ISD::UREM : ISD::UDIV;
2094 SDValue Op0 = Node->getOperand(0);
2095 SDValue Op1 = Node->getOperand(1);
2096 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2097 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2101 if ((User->getOpcode() == OtherOpcode || User->getOpcode() == DivRemOpc) &&
2102 User->getOperand(0) == Op0 &&
2103 User->getOperand(1) == Op1)
2109 /// ExpandDivRemLibCall - Issue libcalls to __{u}divmod to compute div / rem
2112 SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
2113 SmallVectorImpl<SDValue> &Results) {
2114 unsigned Opcode = Node->getOpcode();
2115 bool isSigned = Opcode == ISD::SDIVREM;
2118 switch (Node->getSimpleValueType(0).SimpleTy) {
2119 default: llvm_unreachable("Unexpected request for libcall!");
2120 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2121 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2122 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2123 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2124 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2127 // The input chain to this libcall is the entry node of the function.
2128 // Legalizing the call will automatically add the previous call to the
2130 SDValue InChain = DAG.getEntryNode();
2132 EVT RetVT = Node->getValueType(0);
2133 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2135 TargetLowering::ArgListTy Args;
2136 TargetLowering::ArgListEntry Entry;
2137 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2138 EVT ArgVT = Node->getOperand(i).getValueType();
2139 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2140 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
2141 Entry.isSExt = isSigned;
2142 Entry.isZExt = !isSigned;
2143 Args.push_back(Entry);
2146 // Also pass the return address of the remainder.
2147 SDValue FIPtr = DAG.CreateStackTemporary(RetVT);
2149 Entry.Ty = RetTy->getPointerTo();
2150 Entry.isSExt = isSigned;
2151 Entry.isZExt = !isSigned;
2152 Args.push_back(Entry);
2154 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2155 TLI.getPointerTy());
2159 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
2160 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
2161 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2162 Callee, Args, DAG, dl);
2163 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2165 // Remainder is loaded back from the stack frame.
2166 SDValue Rem = DAG.getLoad(RetVT, dl, CallInfo.second, FIPtr,
2167 MachinePointerInfo(), false, false, false, 0);
2168 Results.push_back(CallInfo.first);
2169 Results.push_back(Rem);
2172 /// isSinCosLibcallAvailable - Return true if sincos libcall is available.
2173 static bool isSinCosLibcallAvailable(SDNode *Node, const TargetLowering &TLI) {
2175 switch (Node->getSimpleValueType(0).SimpleTy) {
2176 default: llvm_unreachable("Unexpected request for libcall!");
2177 case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2178 case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2179 case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2180 case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2181 case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2183 return TLI.getLibcallName(LC) != 0;
2186 /// canCombineSinCosLibcall - Return true if sincos libcall is available and
2187 /// can be used to combine sin and cos.
2188 static bool canCombineSinCosLibcall(SDNode *Node, const TargetLowering &TLI,
2189 const TargetMachine &TM) {
2190 if (!isSinCosLibcallAvailable(Node, TLI))
2192 // GNU sin/cos functions set errno while sincos does not. Therefore
2193 // combining sin and cos is only safe if unsafe-fpmath is enabled.
2194 bool isGNU = Triple(TM.getTargetTriple()).getEnvironment() == Triple::GNU;
2195 if (isGNU && !TM.Options.UnsafeFPMath)
2200 /// useSinCos - Only issue sincos libcall if both sin and cos are
2202 static bool useSinCos(SDNode *Node) {
2203 unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN
2204 ? ISD::FCOS : ISD::FSIN;
2206 SDValue Op0 = Node->getOperand(0);
2207 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2208 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2212 // The other user might have been turned into sincos already.
2213 if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS)
2219 /// ExpandSinCosLibCall - Issue libcalls to sincos to compute sin / cos
2222 SelectionDAGLegalize::ExpandSinCosLibCall(SDNode *Node,
2223 SmallVectorImpl<SDValue> &Results) {
2225 switch (Node->getSimpleValueType(0).SimpleTy) {
2226 default: llvm_unreachable("Unexpected request for libcall!");
2227 case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2228 case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2229 case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2230 case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2231 case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2234 // The input chain to this libcall is the entry node of the function.
2235 // Legalizing the call will automatically add the previous call to the
2237 SDValue InChain = DAG.getEntryNode();
2239 EVT RetVT = Node->getValueType(0);
2240 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2242 TargetLowering::ArgListTy Args;
2243 TargetLowering::ArgListEntry Entry;
2245 // Pass the argument.
2246 Entry.Node = Node->getOperand(0);
2248 Entry.isSExt = false;
2249 Entry.isZExt = false;
2250 Args.push_back(Entry);
2252 // Pass the return address of sin.
2253 SDValue SinPtr = DAG.CreateStackTemporary(RetVT);
2254 Entry.Node = SinPtr;
2255 Entry.Ty = RetTy->getPointerTo();
2256 Entry.isSExt = false;
2257 Entry.isZExt = false;
2258 Args.push_back(Entry);
2260 // Also pass the return address of the cos.
2261 SDValue CosPtr = DAG.CreateStackTemporary(RetVT);
2262 Entry.Node = CosPtr;
2263 Entry.Ty = RetTy->getPointerTo();
2264 Entry.isSExt = false;
2265 Entry.isZExt = false;
2266 Args.push_back(Entry);
2268 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2269 TLI.getPointerTy());
2273 CallLoweringInfo CLI(InChain, Type::getVoidTy(*DAG.getContext()),
2274 false, false, false, false,
2275 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
2276 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2277 Callee, Args, DAG, dl);
2278 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2280 Results.push_back(DAG.getLoad(RetVT, dl, CallInfo.second, SinPtr,
2281 MachinePointerInfo(), false, false, false, 0));
2282 Results.push_back(DAG.getLoad(RetVT, dl, CallInfo.second, CosPtr,
2283 MachinePointerInfo(), false, false, false, 0));
2286 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
2287 /// INT_TO_FP operation of the specified operand when the target requests that
2288 /// we expand it. At this point, we know that the result and operand types are
2289 /// legal for the target.
2290 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
2294 if (Op0.getValueType() == MVT::i32 && TLI.isTypeLegal(MVT::f64)) {
2295 // simple 32-bit [signed|unsigned] integer to float/double expansion
2297 // Get the stack frame index of a 8 byte buffer.
2298 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2300 // word offset constant for Hi/Lo address computation
2301 SDValue WordOff = DAG.getConstant(sizeof(int), StackSlot.getValueType());
2302 // set up Hi and Lo (into buffer) address based on endian
2303 SDValue Hi = StackSlot;
2304 SDValue Lo = DAG.getNode(ISD::ADD, dl, StackSlot.getValueType(),
2305 StackSlot, WordOff);
2306 if (TLI.isLittleEndian())
2309 // if signed map to unsigned space
2312 // constant used to invert sign bit (signed to unsigned mapping)
2313 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
2314 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2318 // store the lo of the constructed double - based on integer input
2319 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
2320 Op0Mapped, Lo, MachinePointerInfo(),
2322 // initial hi portion of constructed double
2323 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
2324 // store the hi of the constructed double - biased exponent
2325 SDValue Store2 = DAG.getStore(Store1, dl, InitialHi, Hi,
2326 MachinePointerInfo(),
2328 // load the constructed double
2329 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot,
2330 MachinePointerInfo(), false, false, false, 0);
2331 // FP constant to bias correct the final result
2332 SDValue Bias = DAG.getConstantFP(isSigned ?
2333 BitsToDouble(0x4330000080000000ULL) :
2334 BitsToDouble(0x4330000000000000ULL),
2336 // subtract the bias
2337 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2340 // handle final rounding
2341 if (DestVT == MVT::f64) {
2344 } else if (DestVT.bitsLT(MVT::f64)) {
2345 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2346 DAG.getIntPtrConstant(0));
2347 } else if (DestVT.bitsGT(MVT::f64)) {
2348 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2352 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2353 // Code below here assumes !isSigned without checking again.
2355 // Implementation of unsigned i64 to f64 following the algorithm in
2356 // __floatundidf in compiler_rt. This implementation has the advantage
2357 // of performing rounding correctly, both in the default rounding mode
2358 // and in all alternate rounding modes.
2359 // TODO: Generalize this for use with other types.
2360 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
2362 DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64);
2363 SDValue TwoP84PlusTwoP52 =
2364 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64);
2366 DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64);
2368 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32);
2369 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2370 DAG.getConstant(32, MVT::i64));
2371 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2372 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2373 SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr);
2374 SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr);
2375 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
2377 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
2380 // Implementation of unsigned i64 to f32.
2381 // TODO: Generalize this for use with other types.
2382 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) {
2383 // For unsigned conversions, convert them to signed conversions using the
2384 // algorithm from the x86_64 __floatundidf in compiler_rt.
2386 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0);
2388 SDValue ShiftConst =
2389 DAG.getConstant(1, TLI.getShiftAmountTy(Op0.getValueType()));
2390 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
2391 SDValue AndConst = DAG.getConstant(1, MVT::i64);
2392 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst);
2393 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr);
2395 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or);
2396 SDValue Slow = DAG.getNode(ISD::FADD, dl, MVT::f32, SignCvt, SignCvt);
2398 // TODO: This really should be implemented using a branch rather than a
2399 // select. We happen to get lucky and machinesink does the right
2400 // thing most of the time. This would be a good candidate for a
2401 //pseudo-op, or, even better, for whole-function isel.
2402 SDValue SignBitTest = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
2403 Op0, DAG.getConstant(0, MVT::i64), ISD::SETLT);
2404 return DAG.getSelect(dl, MVT::f32, SignBitTest, Slow, Fast);
2407 // Otherwise, implement the fully general conversion.
2409 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2410 DAG.getConstant(UINT64_C(0xfffffffffffff800), MVT::i64));
2411 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
2412 DAG.getConstant(UINT64_C(0x800), MVT::i64));
2413 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2414 DAG.getConstant(UINT64_C(0x7ff), MVT::i64));
2415 SDValue Ne = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
2416 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE);
2417 SDValue Sel = DAG.getSelect(dl, MVT::i64, Ne, Or, Op0);
2418 SDValue Ge = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
2419 Op0, DAG.getConstant(UINT64_C(0x0020000000000000), MVT::i64),
2421 SDValue Sel2 = DAG.getSelect(dl, MVT::i64, Ge, Sel, Op0);
2422 EVT SHVT = TLI.getShiftAmountTy(Sel2.getValueType());
2424 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2425 DAG.getConstant(32, SHVT));
2426 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh);
2427 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc);
2429 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), MVT::f64);
2430 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt);
2431 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2);
2432 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo);
2433 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2);
2434 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd,
2435 DAG.getIntPtrConstant(0));
2438 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2440 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(Op0.getValueType()),
2441 Op0, DAG.getConstant(0, Op0.getValueType()),
2443 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
2444 SDValue CstOffset = DAG.getSelect(dl, Zero.getValueType(),
2445 SignSet, Four, Zero);
2447 // If the sign bit of the integer is set, the large number will be treated
2448 // as a negative number. To counteract this, the dynamic code adds an
2449 // offset depending on the data type.
2451 switch (Op0.getSimpleValueType().SimpleTy) {
2452 default: llvm_unreachable("Unsupported integer type!");
2453 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2454 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2455 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2456 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2458 if (TLI.isLittleEndian()) FF <<= 32;
2459 Constant *FudgeFactor = ConstantInt::get(
2460 Type::getInt64Ty(*DAG.getContext()), FF);
2462 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
2463 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2464 CPIdx = DAG.getNode(ISD::ADD, dl, CPIdx.getValueType(), CPIdx, CstOffset);
2465 Alignment = std::min(Alignment, 4u);
2467 if (DestVT == MVT::f32)
2468 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2469 MachinePointerInfo::getConstantPool(),
2470 false, false, false, Alignment);
2472 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
2473 DAG.getEntryNode(), CPIdx,
2474 MachinePointerInfo::getConstantPool(),
2475 MVT::f32, false, false, Alignment);
2476 HandleSDNode Handle(Load);
2477 LegalizeOp(Load.getNode());
2478 FudgeInReg = Handle.getValue();
2481 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2484 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
2485 /// *INT_TO_FP operation of the specified operand when the target requests that
2486 /// we promote it. At this point, we know that the result and operand types are
2487 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2488 /// operation that takes a larger input.
2489 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2493 // First step, figure out the appropriate *INT_TO_FP operation to use.
2494 EVT NewInTy = LegalOp.getValueType();
2496 unsigned OpToUse = 0;
2498 // Scan for the appropriate larger type to use.
2500 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2501 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2503 // If the target supports SINT_TO_FP of this type, use it.
2504 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2505 OpToUse = ISD::SINT_TO_FP;
2508 if (isSigned) continue;
2510 // If the target supports UINT_TO_FP of this type, use it.
2511 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2512 OpToUse = ISD::UINT_TO_FP;
2516 // Otherwise, try a larger type.
2519 // Okay, we found the operation and type to use. Zero extend our input to the
2520 // desired type then run the operation on it.
2521 return DAG.getNode(OpToUse, dl, DestVT,
2522 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2523 dl, NewInTy, LegalOp));
2526 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
2527 /// FP_TO_*INT operation of the specified operand when the target requests that
2528 /// we promote it. At this point, we know that the result and operand types are
2529 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2530 /// operation that returns a larger result.
2531 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2535 // First step, figure out the appropriate FP_TO*INT operation to use.
2536 EVT NewOutTy = DestVT;
2538 unsigned OpToUse = 0;
2540 // Scan for the appropriate larger type to use.
2542 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2543 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2545 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2546 OpToUse = ISD::FP_TO_SINT;
2550 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2551 OpToUse = ISD::FP_TO_UINT;
2555 // Otherwise, try a larger type.
2559 // Okay, we found the operation and type to use.
2560 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2562 // Truncate the result of the extended FP_TO_*INT operation to the desired
2564 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2567 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
2569 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, SDLoc dl) {
2570 EVT VT = Op.getValueType();
2571 EVT SHVT = TLI.getShiftAmountTy(VT);
2572 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2573 switch (VT.getSimpleVT().SimpleTy) {
2574 default: llvm_unreachable("Unhandled Expand type in BSWAP!");
2576 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2577 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2578 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2580 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2581 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2582 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2583 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2584 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
2585 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
2586 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2587 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2588 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2590 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
2591 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
2592 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2593 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2594 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2595 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2596 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
2597 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
2598 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
2599 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
2600 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
2601 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
2602 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
2603 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
2604 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2605 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2606 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2607 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2608 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2609 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2610 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2614 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
2616 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2619 default: llvm_unreachable("Cannot expand this yet!");
2621 EVT VT = Op.getValueType();
2622 EVT ShVT = TLI.getShiftAmountTy(VT);
2623 unsigned Len = VT.getSizeInBits();
2625 assert(VT.isInteger() && Len <= 128 && Len % 8 == 0 &&
2626 "CTPOP not implemented for this type.");
2628 // This is the "best" algorithm from
2629 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
2631 SDValue Mask55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)), VT);
2632 SDValue Mask33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)), VT);
2633 SDValue Mask0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)), VT);
2634 SDValue Mask01 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x01)), VT);
2636 // v = v - ((v >> 1) & 0x55555555...)
2637 Op = DAG.getNode(ISD::SUB, dl, VT, Op,
2638 DAG.getNode(ISD::AND, dl, VT,
2639 DAG.getNode(ISD::SRL, dl, VT, Op,
2640 DAG.getConstant(1, ShVT)),
2642 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
2643 Op = DAG.getNode(ISD::ADD, dl, VT,
2644 DAG.getNode(ISD::AND, dl, VT, Op, Mask33),
2645 DAG.getNode(ISD::AND, dl, VT,
2646 DAG.getNode(ISD::SRL, dl, VT, Op,
2647 DAG.getConstant(2, ShVT)),
2649 // v = (v + (v >> 4)) & 0x0F0F0F0F...
2650 Op = DAG.getNode(ISD::AND, dl, VT,
2651 DAG.getNode(ISD::ADD, dl, VT, Op,
2652 DAG.getNode(ISD::SRL, dl, VT, Op,
2653 DAG.getConstant(4, ShVT))),
2655 // v = (v * 0x01010101...) >> (Len - 8)
2656 Op = DAG.getNode(ISD::SRL, dl, VT,
2657 DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
2658 DAG.getConstant(Len - 8, ShVT));
2662 case ISD::CTLZ_ZERO_UNDEF:
2663 // This trivially expands to CTLZ.
2664 return DAG.getNode(ISD::CTLZ, dl, Op.getValueType(), Op);
2666 // for now, we do this:
2667 // x = x | (x >> 1);
2668 // x = x | (x >> 2);
2670 // x = x | (x >>16);
2671 // x = x | (x >>32); // for 64-bit input
2672 // return popcount(~x);
2674 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
2675 EVT VT = Op.getValueType();
2676 EVT ShVT = TLI.getShiftAmountTy(VT);
2677 unsigned len = VT.getSizeInBits();
2678 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2679 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2680 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2681 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2683 Op = DAG.getNOT(dl, Op, VT);
2684 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2686 case ISD::CTTZ_ZERO_UNDEF:
2687 // This trivially expands to CTTZ.
2688 return DAG.getNode(ISD::CTTZ, dl, Op.getValueType(), Op);
2690 // for now, we use: { return popcount(~x & (x - 1)); }
2691 // unless the target has ctlz but not ctpop, in which case we use:
2692 // { return 32 - nlz(~x & (x-1)); }
2693 // see also http://www.hackersdelight.org/HDcode/ntz.cc
2694 EVT VT = Op.getValueType();
2695 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2696 DAG.getNOT(dl, Op, VT),
2697 DAG.getNode(ISD::SUB, dl, VT, Op,
2698 DAG.getConstant(1, VT)));
2699 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2700 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2701 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2702 return DAG.getNode(ISD::SUB, dl, VT,
2703 DAG.getConstant(VT.getSizeInBits(), VT),
2704 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2705 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2710 std::pair <SDValue, SDValue> SelectionDAGLegalize::ExpandAtomic(SDNode *Node) {
2711 unsigned Opc = Node->getOpcode();
2712 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
2717 llvm_unreachable("Unhandled atomic intrinsic Expand!");
2718 case ISD::ATOMIC_SWAP:
2719 switch (VT.SimpleTy) {
2720 default: llvm_unreachable("Unexpected value type for atomic!");
2721 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break;
2722 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
2723 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
2724 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
2725 case MVT::i128:LC = RTLIB::SYNC_LOCK_TEST_AND_SET_16;break;
2728 case ISD::ATOMIC_CMP_SWAP:
2729 switch (VT.SimpleTy) {
2730 default: llvm_unreachable("Unexpected value type for atomic!");
2731 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break;
2732 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;
2733 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;
2734 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
2735 case MVT::i128:LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16;break;
2738 case ISD::ATOMIC_LOAD_ADD:
2739 switch (VT.SimpleTy) {
2740 default: llvm_unreachable("Unexpected value type for atomic!");
2741 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break;
2742 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;
2743 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;
2744 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
2745 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_ADD_16;break;
2748 case ISD::ATOMIC_LOAD_SUB:
2749 switch (VT.SimpleTy) {
2750 default: llvm_unreachable("Unexpected value type for atomic!");
2751 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break;
2752 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;
2753 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;
2754 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
2755 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_SUB_16;break;
2758 case ISD::ATOMIC_LOAD_AND:
2759 switch (VT.SimpleTy) {
2760 default: llvm_unreachable("Unexpected value type for atomic!");
2761 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break;
2762 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;
2763 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;
2764 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
2765 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_AND_16;break;
2768 case ISD::ATOMIC_LOAD_OR:
2769 switch (VT.SimpleTy) {
2770 default: llvm_unreachable("Unexpected value type for atomic!");
2771 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break;
2772 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;
2773 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;
2774 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
2775 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_OR_16;break;
2778 case ISD::ATOMIC_LOAD_XOR:
2779 switch (VT.SimpleTy) {
2780 default: llvm_unreachable("Unexpected value type for atomic!");
2781 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break;
2782 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;
2783 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;
2784 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
2785 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_XOR_16;break;
2788 case ISD::ATOMIC_LOAD_NAND:
2789 switch (VT.SimpleTy) {
2790 default: llvm_unreachable("Unexpected value type for atomic!");
2791 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break;
2792 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;
2793 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;
2794 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
2795 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_NAND_16;break;
2798 case ISD::ATOMIC_LOAD_MAX:
2799 switch (VT.SimpleTy) {
2800 default: llvm_unreachable("Unexpected value type for atomic!");
2801 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_MAX_1; break;
2802 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_MAX_2; break;
2803 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_MAX_4; break;
2804 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_MAX_8; break;
2805 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_MAX_16;break;
2808 case ISD::ATOMIC_LOAD_UMAX:
2809 switch (VT.SimpleTy) {
2810 default: llvm_unreachable("Unexpected value type for atomic!");
2811 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_UMAX_1; break;
2812 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_UMAX_2; break;
2813 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_UMAX_4; break;
2814 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_UMAX_8; break;
2815 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_UMAX_16;break;
2818 case ISD::ATOMIC_LOAD_MIN:
2819 switch (VT.SimpleTy) {
2820 default: llvm_unreachable("Unexpected value type for atomic!");
2821 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_MIN_1; break;
2822 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_MIN_2; break;
2823 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_MIN_4; break;
2824 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_MIN_8; break;
2825 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_MIN_16;break;
2828 case ISD::ATOMIC_LOAD_UMIN:
2829 switch (VT.SimpleTy) {
2830 default: llvm_unreachable("Unexpected value type for atomic!");
2831 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_UMIN_1; break;
2832 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_UMIN_2; break;
2833 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_UMIN_4; break;
2834 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_UMIN_8; break;
2835 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_UMIN_16;break;
2840 return ExpandChainLibCall(LC, Node, false);
2843 void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
2844 SmallVector<SDValue, 8> Results;
2846 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2848 switch (Node->getOpcode()) {
2851 case ISD::CTLZ_ZERO_UNDEF:
2853 case ISD::CTTZ_ZERO_UNDEF:
2854 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
2855 Results.push_back(Tmp1);
2858 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2860 case ISD::FRAMEADDR:
2861 case ISD::RETURNADDR:
2862 case ISD::FRAME_TO_ARGS_OFFSET:
2863 Results.push_back(DAG.getConstant(0, Node->getValueType(0)));
2865 case ISD::FLT_ROUNDS_:
2866 Results.push_back(DAG.getConstant(1, Node->getValueType(0)));
2868 case ISD::EH_RETURN:
2872 case ISD::EH_SJLJ_LONGJMP:
2873 // If the target didn't expand these, there's nothing to do, so just
2874 // preserve the chain and be done.
2875 Results.push_back(Node->getOperand(0));
2877 case ISD::EH_SJLJ_SETJMP:
2878 // If the target didn't expand this, just return 'zero' and preserve the
2880 Results.push_back(DAG.getConstant(0, MVT::i32));
2881 Results.push_back(Node->getOperand(0));
2883 case ISD::ATOMIC_FENCE: {
2884 // If the target didn't lower this, lower it to '__sync_synchronize()' call
2885 // FIXME: handle "fence singlethread" more efficiently.
2886 TargetLowering::ArgListTy Args;
2888 CallLoweringInfo CLI(Node->getOperand(0),
2889 Type::getVoidTy(*DAG.getContext()),
2890 false, false, false, false, 0, CallingConv::C,
2891 /*isTailCall=*/false,
2892 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2893 DAG.getExternalSymbol("__sync_synchronize",
2894 TLI.getPointerTy()),
2896 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
2898 Results.push_back(CallResult.second);
2901 case ISD::ATOMIC_LOAD: {
2902 // There is no libcall for atomic load; fake it with ATOMIC_CMP_SWAP.
2903 SDValue Zero = DAG.getConstant(0, Node->getValueType(0));
2904 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl,
2905 cast<AtomicSDNode>(Node)->getMemoryVT(),
2906 Node->getOperand(0),
2907 Node->getOperand(1), Zero, Zero,
2908 cast<AtomicSDNode>(Node)->getMemOperand(),
2909 cast<AtomicSDNode>(Node)->getOrdering(),
2910 cast<AtomicSDNode>(Node)->getOrdering(),
2911 cast<AtomicSDNode>(Node)->getSynchScope());
2912 Results.push_back(Swap.getValue(0));
2913 Results.push_back(Swap.getValue(1));
2916 case ISD::ATOMIC_STORE: {
2917 // There is no libcall for atomic store; fake it with ATOMIC_SWAP.
2918 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
2919 cast<AtomicSDNode>(Node)->getMemoryVT(),
2920 Node->getOperand(0),
2921 Node->getOperand(1), Node->getOperand(2),
2922 cast<AtomicSDNode>(Node)->getMemOperand(),
2923 cast<AtomicSDNode>(Node)->getOrdering(),
2924 cast<AtomicSDNode>(Node)->getSynchScope());
2925 Results.push_back(Swap.getValue(1));
2928 // By default, atomic intrinsics are marked Legal and lowered. Targets
2929 // which don't support them directly, however, may want libcalls, in which
2930 // case they mark them Expand, and we get here.
2931 case ISD::ATOMIC_SWAP:
2932 case ISD::ATOMIC_LOAD_ADD:
2933 case ISD::ATOMIC_LOAD_SUB:
2934 case ISD::ATOMIC_LOAD_AND:
2935 case ISD::ATOMIC_LOAD_OR:
2936 case ISD::ATOMIC_LOAD_XOR:
2937 case ISD::ATOMIC_LOAD_NAND:
2938 case ISD::ATOMIC_LOAD_MIN:
2939 case ISD::ATOMIC_LOAD_MAX:
2940 case ISD::ATOMIC_LOAD_UMIN:
2941 case ISD::ATOMIC_LOAD_UMAX:
2942 case ISD::ATOMIC_CMP_SWAP: {
2943 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node);
2944 Results.push_back(Tmp.first);
2945 Results.push_back(Tmp.second);
2948 case ISD::DYNAMIC_STACKALLOC:
2949 ExpandDYNAMIC_STACKALLOC(Node, Results);
2951 case ISD::MERGE_VALUES:
2952 for (unsigned i = 0; i < Node->getNumValues(); i++)
2953 Results.push_back(Node->getOperand(i));
2956 EVT VT = Node->getValueType(0);
2958 Results.push_back(DAG.getConstant(0, VT));
2960 assert(VT.isFloatingPoint() && "Unknown value type!");
2961 Results.push_back(DAG.getConstantFP(0, VT));
2966 // If this operation is not supported, lower it to 'abort()' call
2967 TargetLowering::ArgListTy Args;
2969 CallLoweringInfo CLI(Node->getOperand(0),
2970 Type::getVoidTy(*DAG.getContext()),
2971 false, false, false, false, 0, CallingConv::C,
2972 /*isTailCall=*/false,
2973 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2974 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
2976 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
2978 Results.push_back(CallResult.second);
2983 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
2984 Node->getValueType(0), dl);
2985 Results.push_back(Tmp1);
2987 case ISD::FP_EXTEND:
2988 Tmp1 = EmitStackConvert(Node->getOperand(0),
2989 Node->getOperand(0).getValueType(),
2990 Node->getValueType(0), dl);
2991 Results.push_back(Tmp1);
2993 case ISD::SIGN_EXTEND_INREG: {
2994 // NOTE: we could fall back on load/store here too for targets without
2995 // SAR. However, it is doubtful that any exist.
2996 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2997 EVT VT = Node->getValueType(0);
2998 EVT ShiftAmountTy = TLI.getShiftAmountTy(VT);
3001 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
3002 ExtraVT.getScalarType().getSizeInBits();
3003 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy);
3004 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
3005 Node->getOperand(0), ShiftCst);
3006 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
3007 Results.push_back(Tmp1);
3010 case ISD::FP_ROUND_INREG: {
3011 // The only way we can lower this is to turn it into a TRUNCSTORE,
3012 // EXTLOAD pair, targeting a temporary location (a stack slot).
3014 // NOTE: there is a choice here between constantly creating new stack
3015 // slots and always reusing the same one. We currently always create
3016 // new ones, as reuse may inhibit scheduling.
3017 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3018 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
3019 Node->getValueType(0), dl);
3020 Results.push_back(Tmp1);
3023 case ISD::SINT_TO_FP:
3024 case ISD::UINT_TO_FP:
3025 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
3026 Node->getOperand(0), Node->getValueType(0), dl);
3027 Results.push_back(Tmp1);
3029 case ISD::FP_TO_UINT: {
3030 SDValue True, False;
3031 EVT VT = Node->getOperand(0).getValueType();
3032 EVT NVT = Node->getValueType(0);
3033 APFloat apf(DAG.EVTToAPFloatSemantics(VT),
3034 APInt::getNullValue(VT.getSizeInBits()));
3035 APInt x = APInt::getSignBit(NVT.getSizeInBits());
3036 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
3037 Tmp1 = DAG.getConstantFP(apf, VT);
3038 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(VT),
3039 Node->getOperand(0),
3041 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
3042 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
3043 DAG.getNode(ISD::FSUB, dl, VT,
3044 Node->getOperand(0), Tmp1));
3045 False = DAG.getNode(ISD::XOR, dl, NVT, False,
3046 DAG.getConstant(x, NVT));
3047 Tmp1 = DAG.getSelect(dl, NVT, Tmp2, True, False);
3048 Results.push_back(Tmp1);
3052 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3053 EVT VT = Node->getValueType(0);
3054 Tmp1 = Node->getOperand(0);
3055 Tmp2 = Node->getOperand(1);
3056 unsigned Align = Node->getConstantOperandVal(3);
3058 SDValue VAListLoad = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2,
3059 MachinePointerInfo(V),
3060 false, false, false, 0);
3061 SDValue VAList = VAListLoad;
3063 if (Align > TLI.getMinStackArgumentAlignment()) {
3064 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
3066 VAList = DAG.getNode(ISD::ADD, dl, VAList.getValueType(), VAList,
3067 DAG.getConstant(Align - 1,
3068 VAList.getValueType()));
3070 VAList = DAG.getNode(ISD::AND, dl, VAList.getValueType(), VAList,
3071 DAG.getConstant(-(int64_t)Align,
3072 VAList.getValueType()));
3075 // Increment the pointer, VAList, to the next vaarg
3076 Tmp3 = DAG.getNode(ISD::ADD, dl, VAList.getValueType(), VAList,
3077 DAG.getConstant(TLI.getDataLayout()->
3078 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())),
3079 VAList.getValueType()));
3080 // Store the incremented VAList to the legalized pointer
3081 Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2,
3082 MachinePointerInfo(V), false, false, 0);
3083 // Load the actual argument out of the pointer VAList
3084 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(),
3085 false, false, false, 0));
3086 Results.push_back(Results[0].getValue(1));
3090 // This defaults to loading a pointer from the input and storing it to the
3091 // output, returning the chain.
3092 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3093 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3094 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0),
3095 Node->getOperand(2), MachinePointerInfo(VS),
3096 false, false, false, 0);
3097 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1),
3098 MachinePointerInfo(VD), false, false, 0);
3099 Results.push_back(Tmp1);
3102 case ISD::EXTRACT_VECTOR_ELT:
3103 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
3104 // This must be an access of the only element. Return it.
3105 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
3106 Node->getOperand(0));
3108 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
3109 Results.push_back(Tmp1);
3111 case ISD::EXTRACT_SUBVECTOR:
3112 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
3114 case ISD::INSERT_SUBVECTOR:
3115 Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0)));
3117 case ISD::CONCAT_VECTORS: {
3118 Results.push_back(ExpandVectorBuildThroughStack(Node));
3121 case ISD::SCALAR_TO_VECTOR:
3122 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
3124 case ISD::INSERT_VECTOR_ELT:
3125 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
3126 Node->getOperand(1),
3127 Node->getOperand(2), dl));
3129 case ISD::VECTOR_SHUFFLE: {
3130 SmallVector<int, 32> NewMask;
3131 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
3133 EVT VT = Node->getValueType(0);
3134 EVT EltVT = VT.getVectorElementType();
3135 SDValue Op0 = Node->getOperand(0);
3136 SDValue Op1 = Node->getOperand(1);
3137 if (!TLI.isTypeLegal(EltVT)) {
3139 EVT NewEltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
3141 // BUILD_VECTOR operands are allowed to be wider than the element type.
3142 // But if NewEltVT is smaller that EltVT the BUILD_VECTOR does not accept
3144 if (NewEltVT.bitsLT(EltVT)) {
3146 // Convert shuffle node.
3147 // If original node was v4i64 and the new EltVT is i32,
3148 // cast operands to v8i32 and re-build the mask.
3150 // Calculate new VT, the size of the new VT should be equal to original.
3152 EVT::getVectorVT(*DAG.getContext(), NewEltVT,
3153 VT.getSizeInBits() / NewEltVT.getSizeInBits());
3154 assert(NewVT.bitsEq(VT));
3156 // cast operands to new VT
3157 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0);
3158 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1);
3160 // Convert the shuffle mask
3161 unsigned int factor =
3162 NewVT.getVectorNumElements()/VT.getVectorNumElements();
3164 // EltVT gets smaller
3167 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
3169 for (unsigned fi = 0; fi < factor; ++fi)
3170 NewMask.push_back(Mask[i]);
3173 for (unsigned fi = 0; fi < factor; ++fi)
3174 NewMask.push_back(Mask[i]*factor+fi);
3182 unsigned NumElems = VT.getVectorNumElements();
3183 SmallVector<SDValue, 16> Ops;
3184 for (unsigned i = 0; i != NumElems; ++i) {
3186 Ops.push_back(DAG.getUNDEF(EltVT));
3189 unsigned Idx = Mask[i];
3191 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3193 DAG.getConstant(Idx, TLI.getVectorIdxTy())));
3195 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3197 DAG.getConstant(Idx - NumElems,
3198 TLI.getVectorIdxTy())));
3201 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
3202 // We may have changed the BUILD_VECTOR type. Cast it back to the Node type.
3203 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), Tmp1);
3204 Results.push_back(Tmp1);
3207 case ISD::EXTRACT_ELEMENT: {
3208 EVT OpTy = Node->getOperand(0).getValueType();
3209 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
3211 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
3212 DAG.getConstant(OpTy.getSizeInBits()/2,
3213 TLI.getShiftAmountTy(Node->getOperand(0).getValueType())));
3214 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
3217 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
3218 Node->getOperand(0));
3220 Results.push_back(Tmp1);
3223 case ISD::STACKSAVE:
3224 // Expand to CopyFromReg if the target set
3225 // StackPointerRegisterToSaveRestore.
3226 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3227 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
3228 Node->getValueType(0)));
3229 Results.push_back(Results[0].getValue(1));
3231 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
3232 Results.push_back(Node->getOperand(0));
3235 case ISD::STACKRESTORE:
3236 // Expand to CopyToReg if the target set
3237 // StackPointerRegisterToSaveRestore.
3238 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3239 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
3240 Node->getOperand(1)));
3242 Results.push_back(Node->getOperand(0));
3245 case ISD::FCOPYSIGN:
3246 Results.push_back(ExpandFCOPYSIGN(Node));
3249 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3250 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3251 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
3252 Node->getOperand(0));
3253 Results.push_back(Tmp1);
3256 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3257 EVT VT = Node->getValueType(0);
3258 Tmp1 = Node->getOperand(0);
3259 Tmp2 = DAG.getConstantFP(0.0, VT);
3260 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(Tmp1.getValueType()),
3261 Tmp1, Tmp2, ISD::SETUGT);
3262 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
3263 Tmp1 = DAG.getSelect(dl, VT, Tmp2, Tmp1, Tmp3);
3264 Results.push_back(Tmp1);
3268 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3269 RTLIB::SQRT_F80, RTLIB::SQRT_F128,
3270 RTLIB::SQRT_PPCF128));
3274 EVT VT = Node->getValueType(0);
3275 bool isSIN = Node->getOpcode() == ISD::FSIN;
3276 // Turn fsin / fcos into ISD::FSINCOS node if there are a pair of fsin /
3277 // fcos which share the same operand and both are used.
3278 if ((TLI.isOperationLegalOrCustom(ISD::FSINCOS, VT) ||
3279 canCombineSinCosLibcall(Node, TLI, TM))
3280 && useSinCos(Node)) {
3281 SDVTList VTs = DAG.getVTList(VT, VT);
3282 Tmp1 = DAG.getNode(ISD::FSINCOS, dl, VTs, Node->getOperand(0));
3284 Tmp1 = Tmp1.getValue(1);
3285 Results.push_back(Tmp1);
3287 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
3288 RTLIB::SIN_F80, RTLIB::SIN_F128,
3289 RTLIB::SIN_PPCF128));
3291 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
3292 RTLIB::COS_F80, RTLIB::COS_F128,
3293 RTLIB::COS_PPCF128));
3298 // Expand into sincos libcall.
3299 ExpandSinCosLibCall(Node, Results);
3302 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
3303 RTLIB::LOG_F80, RTLIB::LOG_F128,
3304 RTLIB::LOG_PPCF128));
3307 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3308 RTLIB::LOG2_F80, RTLIB::LOG2_F128,
3309 RTLIB::LOG2_PPCF128));
3312 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3313 RTLIB::LOG10_F80, RTLIB::LOG10_F128,
3314 RTLIB::LOG10_PPCF128));
3317 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
3318 RTLIB::EXP_F80, RTLIB::EXP_F128,
3319 RTLIB::EXP_PPCF128));
3322 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3323 RTLIB::EXP2_F80, RTLIB::EXP2_F128,
3324 RTLIB::EXP2_PPCF128));
3327 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3328 RTLIB::TRUNC_F80, RTLIB::TRUNC_F128,
3329 RTLIB::TRUNC_PPCF128));
3332 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3333 RTLIB::FLOOR_F80, RTLIB::FLOOR_F128,
3334 RTLIB::FLOOR_PPCF128));
3337 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3338 RTLIB::CEIL_F80, RTLIB::CEIL_F128,
3339 RTLIB::CEIL_PPCF128));
3342 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
3343 RTLIB::RINT_F80, RTLIB::RINT_F128,
3344 RTLIB::RINT_PPCF128));
3346 case ISD::FNEARBYINT:
3347 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
3348 RTLIB::NEARBYINT_F64,
3349 RTLIB::NEARBYINT_F80,
3350 RTLIB::NEARBYINT_F128,
3351 RTLIB::NEARBYINT_PPCF128));
3354 Results.push_back(ExpandFPLibCall(Node, RTLIB::ROUND_F32,
3358 RTLIB::ROUND_PPCF128));
3361 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
3362 RTLIB::POWI_F80, RTLIB::POWI_F128,
3363 RTLIB::POWI_PPCF128));
3366 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
3367 RTLIB::POW_F80, RTLIB::POW_F128,
3368 RTLIB::POW_PPCF128));
3371 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
3372 RTLIB::DIV_F80, RTLIB::DIV_F128,
3373 RTLIB::DIV_PPCF128));
3376 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
3377 RTLIB::REM_F80, RTLIB::REM_F128,
3378 RTLIB::REM_PPCF128));
3381 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMA_F32, RTLIB::FMA_F64,
3382 RTLIB::FMA_F80, RTLIB::FMA_F128,
3383 RTLIB::FMA_PPCF128));
3385 case ISD::FP16_TO_FP32:
3386 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
3388 case ISD::FP32_TO_FP16:
3389 Results.push_back(ExpandLibCall(RTLIB::FPROUND_F32_F16, Node, false));
3391 case ISD::ConstantFP: {
3392 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
3393 // Check to see if this FP immediate is already legal.
3394 // If this is a legal constant, turn it into a TargetConstantFP node.
3395 if (!TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
3396 Results.push_back(ExpandConstantFP(CFP, true));
3400 EVT VT = Node->getValueType(0);
3401 assert(TLI.isOperationLegalOrCustom(ISD::FADD, VT) &&
3402 TLI.isOperationLegalOrCustom(ISD::FNEG, VT) &&
3403 "Don't know how to expand this FP subtraction!");
3404 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1));
3405 Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1);
3406 Results.push_back(Tmp1);
3410 EVT VT = Node->getValueType(0);
3411 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3412 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3413 "Don't know how to expand this subtraction!");
3414 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3415 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
3416 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, VT));
3417 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3422 EVT VT = Node->getValueType(0);
3423 bool isSigned = Node->getOpcode() == ISD::SREM;
3424 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3425 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3426 Tmp2 = Node->getOperand(0);
3427 Tmp3 = Node->getOperand(1);
3428 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3429 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3430 // If div is legal, it's better to do the normal expansion
3431 !TLI.isOperationLegalOrCustom(DivOpc, Node->getValueType(0)) &&
3432 useDivRem(Node, isSigned, false))) {
3433 SDVTList VTs = DAG.getVTList(VT, VT);
3434 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
3435 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
3437 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
3438 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3439 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3440 } else if (isSigned)
3441 Tmp1 = ExpandIntLibCall(Node, true,
3443 RTLIB::SREM_I16, RTLIB::SREM_I32,
3444 RTLIB::SREM_I64, RTLIB::SREM_I128);
3446 Tmp1 = ExpandIntLibCall(Node, false,
3448 RTLIB::UREM_I16, RTLIB::UREM_I32,
3449 RTLIB::UREM_I64, RTLIB::UREM_I128);
3450 Results.push_back(Tmp1);
3455 bool isSigned = Node->getOpcode() == ISD::SDIV;
3456 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3457 EVT VT = Node->getValueType(0);
3458 SDVTList VTs = DAG.getVTList(VT, VT);
3459 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3460 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3461 useDivRem(Node, isSigned, true)))
3462 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
3463 Node->getOperand(1));
3465 Tmp1 = ExpandIntLibCall(Node, true,
3467 RTLIB::SDIV_I16, RTLIB::SDIV_I32,
3468 RTLIB::SDIV_I64, RTLIB::SDIV_I128);
3470 Tmp1 = ExpandIntLibCall(Node, false,
3472 RTLIB::UDIV_I16, RTLIB::UDIV_I32,
3473 RTLIB::UDIV_I64, RTLIB::UDIV_I128);
3474 Results.push_back(Tmp1);
3479 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
3481 EVT VT = Node->getValueType(0);
3482 SDVTList VTs = DAG.getVTList(VT, VT);
3483 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
3484 "If this wasn't legal, it shouldn't have been created!");
3485 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
3486 Node->getOperand(1));
3487 Results.push_back(Tmp1.getValue(1));
3492 // Expand into divrem libcall
3493 ExpandDivRemLibCall(Node, Results);
3496 EVT VT = Node->getValueType(0);
3497 SDVTList VTs = DAG.getVTList(VT, VT);
3498 // See if multiply or divide can be lowered using two-result operations.
3499 // We just need the low half of the multiply; try both the signed
3500 // and unsigned forms. If the target supports both SMUL_LOHI and
3501 // UMUL_LOHI, form a preference by checking which forms of plain
3502 // MULH it supports.
3503 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3504 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3505 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3506 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3507 unsigned OpToUse = 0;
3508 if (HasSMUL_LOHI && !HasMULHS) {
3509 OpToUse = ISD::SMUL_LOHI;
3510 } else if (HasUMUL_LOHI && !HasMULHU) {
3511 OpToUse = ISD::UMUL_LOHI;
3512 } else if (HasSMUL_LOHI) {
3513 OpToUse = ISD::SMUL_LOHI;
3514 } else if (HasUMUL_LOHI) {
3515 OpToUse = ISD::UMUL_LOHI;
3518 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
3519 Node->getOperand(1)));
3522 Tmp1 = ExpandIntLibCall(Node, false,
3524 RTLIB::MUL_I16, RTLIB::MUL_I32,
3525 RTLIB::MUL_I64, RTLIB::MUL_I128);
3526 Results.push_back(Tmp1);
3531 SDValue LHS = Node->getOperand(0);
3532 SDValue RHS = Node->getOperand(1);
3533 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3534 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3536 Results.push_back(Sum);
3537 EVT OType = Node->getValueType(1);
3539 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
3541 // LHSSign -> LHS >= 0
3542 // RHSSign -> RHS >= 0
3543 // SumSign -> Sum >= 0
3546 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3548 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3550 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3551 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3552 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
3553 Node->getOpcode() == ISD::SADDO ?
3554 ISD::SETEQ : ISD::SETNE);
3556 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3557 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3559 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3560 Results.push_back(Cmp);
3565 SDValue LHS = Node->getOperand(0);
3566 SDValue RHS = Node->getOperand(1);
3567 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
3568 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3570 Results.push_back(Sum);
3571 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS,
3572 Node->getOpcode () == ISD::UADDO ?
3573 ISD::SETULT : ISD::SETUGT));
3578 EVT VT = Node->getValueType(0);
3579 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
3580 SDValue LHS = Node->getOperand(0);
3581 SDValue RHS = Node->getOperand(1);
3584 static const unsigned Ops[2][3] =
3585 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
3586 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
3587 bool isSigned = Node->getOpcode() == ISD::SMULO;
3588 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3589 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3590 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3591 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3592 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3594 TopHalf = BottomHalf.getValue(1);
3595 } else if (TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(),
3596 VT.getSizeInBits() * 2))) {
3597 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
3598 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
3599 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
3600 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3601 DAG.getIntPtrConstant(0));
3602 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3603 DAG.getIntPtrConstant(1));
3605 // We can fall back to a libcall with an illegal type for the MUL if we
3606 // have a libcall big enough.
3607 // Also, we can fall back to a division in some cases, but that's a big
3608 // performance hit in the general case.
3609 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3610 if (WideVT == MVT::i16)
3611 LC = RTLIB::MUL_I16;
3612 else if (WideVT == MVT::i32)
3613 LC = RTLIB::MUL_I32;
3614 else if (WideVT == MVT::i64)
3615 LC = RTLIB::MUL_I64;
3616 else if (WideVT == MVT::i128)
3617 LC = RTLIB::MUL_I128;
3618 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!");
3620 // The high part is obtained by SRA'ing all but one of the bits of low
3622 unsigned LoSize = VT.getSizeInBits();
3623 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, RHS,
3624 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
3625 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, VT, LHS,
3626 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
3628 // Here we're passing the 2 arguments explicitly as 4 arguments that are
3629 // pre-lowered to the correct types. This all depends upon WideVT not
3630 // being a legal type for the architecture and thus has to be split to
3632 SDValue Args[] = { LHS, HiLHS, RHS, HiRHS };
3633 SDValue Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl);
3634 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3635 DAG.getIntPtrConstant(0));
3636 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3637 DAG.getIntPtrConstant(1));
3638 // Ret is a node with an illegal type. Because such things are not
3639 // generally permitted during this phase of legalization, delete the
3640 // node. The above EXTRACT_ELEMENT nodes should have been folded.
3641 DAG.DeleteNode(Ret.getNode());
3645 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1,
3646 TLI.getShiftAmountTy(BottomHalf.getValueType()));
3647 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3648 TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf, Tmp1,
3651 TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf,
3652 DAG.getConstant(0, VT), ISD::SETNE);
3654 Results.push_back(BottomHalf);
3655 Results.push_back(TopHalf);
3658 case ISD::BUILD_PAIR: {
3659 EVT PairTy = Node->getValueType(0);
3660 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3661 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3662 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
3663 DAG.getConstant(PairTy.getSizeInBits()/2,
3664 TLI.getShiftAmountTy(PairTy)));
3665 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3669 Tmp1 = Node->getOperand(0);
3670 Tmp2 = Node->getOperand(1);
3671 Tmp3 = Node->getOperand(2);
3672 if (Tmp1.getOpcode() == ISD::SETCC) {
3673 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3675 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3677 Tmp1 = DAG.getSelectCC(dl, Tmp1,
3678 DAG.getConstant(0, Tmp1.getValueType()),
3679 Tmp2, Tmp3, ISD::SETNE);
3681 Results.push_back(Tmp1);
3684 SDValue Chain = Node->getOperand(0);
3685 SDValue Table = Node->getOperand(1);
3686 SDValue Index = Node->getOperand(2);
3688 EVT PTy = TLI.getPointerTy();
3690 const DataLayout &TD = *TLI.getDataLayout();
3691 unsigned EntrySize =
3692 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
3694 Index = DAG.getNode(ISD::MUL, dl, Index.getValueType(),
3695 Index, DAG.getConstant(EntrySize, Index.getValueType()));
3696 SDValue Addr = DAG.getNode(ISD::ADD, dl, Index.getValueType(),
3699 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
3700 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
3701 MachinePointerInfo::getJumpTable(), MemVT,
3704 if (TM.getRelocationModel() == Reloc::PIC_) {
3705 // For PIC, the sequence is:
3706 // BRIND(load(Jumptable + index) + RelocBase)
3707 // RelocBase can be JumpTable, GOT or some sort of global base.
3708 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3709 TLI.getPICJumpTableRelocBase(Table, DAG));
3711 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
3712 Results.push_back(Tmp1);
3716 // Expand brcond's setcc into its constituent parts and create a BR_CC
3718 Tmp1 = Node->getOperand(0);
3719 Tmp2 = Node->getOperand(1);
3720 if (Tmp2.getOpcode() == ISD::SETCC) {
3721 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3722 Tmp1, Tmp2.getOperand(2),
3723 Tmp2.getOperand(0), Tmp2.getOperand(1),
3724 Node->getOperand(2));
3726 // We test only the i1 bit. Skip the AND if UNDEF.
3727 Tmp3 = (Tmp2.getOpcode() == ISD::UNDEF) ? Tmp2 :
3728 DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2,
3729 DAG.getConstant(1, Tmp2.getValueType()));
3730 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3731 DAG.getCondCode(ISD::SETNE), Tmp3,
3732 DAG.getConstant(0, Tmp3.getValueType()),
3733 Node->getOperand(2));
3735 Results.push_back(Tmp1);
3738 Tmp1 = Node->getOperand(0);
3739 Tmp2 = Node->getOperand(1);
3740 Tmp3 = Node->getOperand(2);
3741 bool Legalized = LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2,
3742 Tmp3, NeedInvert, dl);
3745 // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3746 // condition code, create a new SETCC node.
3748 Tmp1 = DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3751 // If we expanded the SETCC by inverting the condition code, then wrap
3752 // the existing SETCC in a NOT to restore the intended condition.
3754 Tmp1 = DAG.getNOT(dl, Tmp1, Tmp1->getValueType(0));
3756 Results.push_back(Tmp1);
3760 // Otherwise, SETCC for the given comparison type must be completely
3761 // illegal; expand it into a SELECT_CC.
3762 EVT VT = Node->getValueType(0);
3764 switch (TLI.getBooleanContents(VT.isVector())) {
3765 case TargetLowering::ZeroOrOneBooleanContent:
3766 case TargetLowering::UndefinedBooleanContent:
3769 case TargetLowering::ZeroOrNegativeOneBooleanContent:
3773 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3774 DAG.getConstant(TrueValue, VT), DAG.getConstant(0, VT),
3776 Results.push_back(Tmp1);
3779 case ISD::SELECT_CC: {
3780 Tmp1 = Node->getOperand(0); // LHS
3781 Tmp2 = Node->getOperand(1); // RHS
3782 Tmp3 = Node->getOperand(2); // True
3783 Tmp4 = Node->getOperand(3); // False
3784 SDValue CC = Node->getOperand(4);
3786 bool Legalized = false;
3787 // Try to legalize by inverting the condition. This is for targets that
3788 // might support an ordered version of a condition, but not the unordered
3789 // version (or vice versa).
3790 ISD::CondCode InvCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
3791 Tmp1.getValueType().isInteger());
3792 if (TLI.isCondCodeLegal(InvCC, Tmp1.getSimpleValueType())) {
3793 // Use the new condition code and swap true and false
3795 Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp4, Tmp3, InvCC);
3797 // If The inverse is not legal, then try to swap the arguments using
3798 // the inverse condition code.
3799 ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(InvCC);
3800 if (TLI.isCondCodeLegal(SwapInvCC, Tmp1.getSimpleValueType())) {
3801 // The swapped inverse condition is legal, so swap true and false,
3804 Tmp1 = DAG.getSelectCC(dl, Tmp2, Tmp1, Tmp4, Tmp3, SwapInvCC);
3809 Legalized = LegalizeSetCCCondCode(
3810 getSetCCResultType(Tmp1.getValueType()), Tmp1, Tmp2, CC, NeedInvert,
3813 assert(Legalized && "Can't legalize SELECT_CC with legal condition!");
3815 // If we expanded the SETCC by inverting the condition code, then swap
3816 // the True/False operands to match.
3818 std::swap(Tmp3, Tmp4);
3820 // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3821 // condition code, create a new SELECT_CC node.
3823 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0),
3824 Tmp1, Tmp2, Tmp3, Tmp4, CC);
3826 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3827 CC = DAG.getCondCode(ISD::SETNE);
3828 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1,
3829 Tmp2, Tmp3, Tmp4, CC);
3832 Results.push_back(Tmp1);
3836 Tmp1 = Node->getOperand(0); // Chain
3837 Tmp2 = Node->getOperand(2); // LHS
3838 Tmp3 = Node->getOperand(3); // RHS
3839 Tmp4 = Node->getOperand(1); // CC
3841 bool Legalized = LegalizeSetCCCondCode(getSetCCResultType(
3842 Tmp2.getValueType()), Tmp2, Tmp3, Tmp4, NeedInvert, dl);
3844 assert(Legalized && "Can't legalize BR_CC with legal condition!");
3846 // If we expanded the SETCC by inverting the condition code, then wrap
3847 // the existing SETCC in a NOT to restore the intended condition.
3849 Tmp4 = DAG.getNOT(dl, Tmp4, Tmp4->getValueType(0));
3851 // If we expanded the SETCC by swapping LHS and RHS, create a new BR_CC
3853 if (Tmp4.getNode()) {
3854 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1,
3855 Tmp4, Tmp2, Tmp3, Node->getOperand(4));
3857 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
3858 Tmp4 = DAG.getCondCode(ISD::SETNE);
3859 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4,
3860 Tmp2, Tmp3, Node->getOperand(4));
3862 Results.push_back(Tmp1);
3865 case ISD::BUILD_VECTOR:
3866 Results.push_back(ExpandBUILD_VECTOR(Node));
3871 // Scalarize vector SRA/SRL/SHL.
3872 EVT VT = Node->getValueType(0);
3873 assert(VT.isVector() && "Unable to legalize non-vector shift");
3874 assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
3875 unsigned NumElem = VT.getVectorNumElements();
3877 SmallVector<SDValue, 8> Scalars;
3878 for (unsigned Idx = 0; Idx < NumElem; Idx++) {
3879 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3881 Node->getOperand(0), DAG.getConstant(Idx,
3882 TLI.getVectorIdxTy()));
3883 SDValue Sh = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3885 Node->getOperand(1), DAG.getConstant(Idx,
3886 TLI.getVectorIdxTy()));
3887 Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
3888 VT.getScalarType(), Ex, Sh));
3891 DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0),
3892 &Scalars[0], Scalars.size());
3893 ReplaceNode(SDValue(Node, 0), Result);
3896 case ISD::GLOBAL_OFFSET_TABLE:
3897 case ISD::GlobalAddress:
3898 case ISD::GlobalTLSAddress:
3899 case ISD::ExternalSymbol:
3900 case ISD::ConstantPool:
3901 case ISD::JumpTable:
3902 case ISD::INTRINSIC_W_CHAIN:
3903 case ISD::INTRINSIC_WO_CHAIN:
3904 case ISD::INTRINSIC_VOID:
3905 // FIXME: Custom lowering for these operations shouldn't return null!
3909 // Replace the original node with the legalized result.
3910 if (!Results.empty())
3911 ReplaceNode(Node, Results.data());
3914 void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
3915 SmallVector<SDValue, 8> Results;
3916 MVT OVT = Node->getSimpleValueType(0);
3917 if (Node->getOpcode() == ISD::UINT_TO_FP ||
3918 Node->getOpcode() == ISD::SINT_TO_FP ||
3919 Node->getOpcode() == ISD::SETCC) {
3920 OVT = Node->getOperand(0).getSimpleValueType();
3922 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3924 SDValue Tmp1, Tmp2, Tmp3;
3925 switch (Node->getOpcode()) {
3927 case ISD::CTTZ_ZERO_UNDEF:
3929 case ISD::CTLZ_ZERO_UNDEF:
3931 // Zero extend the argument.
3932 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3933 // Perform the larger operation. For CTPOP and CTTZ_ZERO_UNDEF, this is
3934 // already the correct result.
3935 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
3936 if (Node->getOpcode() == ISD::CTTZ) {
3937 // FIXME: This should set a bit in the zero extended value instead.
3938 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT),
3939 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
3941 Tmp1 = DAG.getSelect(dl, NVT, Tmp2,
3942 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3943 } else if (Node->getOpcode() == ISD::CTLZ ||
3944 Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) {
3945 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3946 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
3947 DAG.getConstant(NVT.getSizeInBits() -
3948 OVT.getSizeInBits(), NVT));
3950 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
3953 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3954 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3955 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
3956 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
3957 DAG.getConstant(DiffBits, TLI.getShiftAmountTy(NVT)));
3958 Results.push_back(Tmp1);
3961 case ISD::FP_TO_UINT:
3962 case ISD::FP_TO_SINT:
3963 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
3964 Node->getOpcode() == ISD::FP_TO_SINT, dl);
3965 Results.push_back(Tmp1);
3967 case ISD::UINT_TO_FP:
3968 case ISD::SINT_TO_FP:
3969 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
3970 Node->getOpcode() == ISD::SINT_TO_FP, dl);
3971 Results.push_back(Tmp1);
3974 SDValue Chain = Node->getOperand(0); // Get the chain.
3975 SDValue Ptr = Node->getOperand(1); // Get the pointer.
3978 if (OVT.isVector()) {
3979 TruncOp = ISD::BITCAST;
3981 assert(OVT.isInteger()
3982 && "VAARG promotion is supported only for vectors or integer types");
3983 TruncOp = ISD::TRUNCATE;
3986 // Perform the larger operation, then convert back
3987 Tmp1 = DAG.getVAArg(NVT, dl, Chain, Ptr, Node->getOperand(2),
3988 Node->getConstantOperandVal(3));
3989 Chain = Tmp1.getValue(1);
3991 Tmp2 = DAG.getNode(TruncOp, dl, OVT, Tmp1);
3993 // Modified the chain result - switch anything that used the old chain to
3995 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp2);
3996 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
4003 unsigned ExtOp, TruncOp;
4004 if (OVT.isVector()) {
4005 ExtOp = ISD::BITCAST;
4006 TruncOp = ISD::BITCAST;
4008 assert(OVT.isInteger() && "Cannot promote logic operation");
4009 ExtOp = ISD::ANY_EXTEND;
4010 TruncOp = ISD::TRUNCATE;
4012 // Promote each of the values to the new type.
4013 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4014 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4015 // Perform the larger operation, then convert back
4016 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4017 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
4021 unsigned ExtOp, TruncOp;
4022 if (Node->getValueType(0).isVector() ||
4023 Node->getValueType(0).getSizeInBits() == NVT.getSizeInBits()) {
4024 ExtOp = ISD::BITCAST;
4025 TruncOp = ISD::BITCAST;
4026 } else if (Node->getValueType(0).isInteger()) {
4027 ExtOp = ISD::ANY_EXTEND;
4028 TruncOp = ISD::TRUNCATE;
4030 ExtOp = ISD::FP_EXTEND;
4031 TruncOp = ISD::FP_ROUND;
4033 Tmp1 = Node->getOperand(0);
4034 // Promote each of the values to the new type.
4035 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4036 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
4037 // Perform the larger operation, then round down.
4038 Tmp1 = DAG.getSelect(dl, NVT, Tmp1, Tmp2, Tmp3);
4039 if (TruncOp != ISD::FP_ROUND)
4040 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
4042 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
4043 DAG.getIntPtrConstant(0));
4044 Results.push_back(Tmp1);
4047 case ISD::VECTOR_SHUFFLE: {
4048 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
4050 // Cast the two input vectors.
4051 Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
4052 Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
4054 // Convert the shuffle mask to the right # elements.
4055 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
4056 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
4057 Results.push_back(Tmp1);
4061 unsigned ExtOp = ISD::FP_EXTEND;
4062 if (NVT.isInteger()) {
4063 ISD::CondCode CCCode =
4064 cast<CondCodeSDNode>(Node->getOperand(2))->get();
4065 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4067 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4068 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4069 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
4070 Tmp1, Tmp2, Node->getOperand(2)));
4076 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4077 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
4078 Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4079 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4080 Tmp3, DAG.getIntPtrConstant(0)));
4087 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4088 Tmp2 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4089 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4090 Tmp2, DAG.getIntPtrConstant(0)));
4095 // Replace the original node with the legalized result.
4096 if (!Results.empty())
4097 ReplaceNode(Node, Results.data());
4100 // SelectionDAG::Legalize - This is the entry point for the file.
4102 void SelectionDAG::Legalize() {
4103 /// run - This is the main entry point to this class.
4105 SelectionDAGLegalize(*this).LegalizeDAG();