1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/Analysis/DebugInfo.h"
20 #include "llvm/CodeGen/PseudoSourceValue.h"
21 #include "llvm/Target/TargetFrameInfo.h"
22 #include "llvm/Target/TargetLowering.h"
23 #include "llvm/Target/TargetData.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Target/TargetOptions.h"
26 #include "llvm/CallingConv.h"
27 #include "llvm/Constants.h"
28 #include "llvm/DerivedTypes.h"
29 #include "llvm/Function.h"
30 #include "llvm/GlobalVariable.h"
31 #include "llvm/LLVMContext.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/ADT/DenseMap.h"
37 #include "llvm/ADT/SmallVector.h"
38 #include "llvm/ADT/SmallPtrSet.h"
41 //===----------------------------------------------------------------------===//
42 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
43 /// hacks on it until the target machine can handle it. This involves
44 /// eliminating value sizes the machine cannot handle (promoting small sizes to
45 /// large sizes or splitting up large values into small values) as well as
46 /// eliminating operations the machine cannot handle.
48 /// This code also does a small amount of optimization and recognition of idioms
49 /// as part of its processing. For example, if a target does not support a
50 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
51 /// will attempt merge setcc and brc instructions into brcc's.
54 class SelectionDAGLegalize {
55 const TargetMachine &TM;
56 const TargetLowering &TLI;
58 CodeGenOpt::Level OptLevel;
60 // Libcall insertion helpers.
62 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
63 /// legalized. We use this to ensure that calls are properly serialized
64 /// against each other, including inserted libcalls.
65 SDValue LastCALLSEQ_END;
67 /// IsLegalizingCall - This member is used *only* for purposes of providing
68 /// helpful assertions that a libcall isn't created while another call is
69 /// being legalized (which could lead to non-serialized call sequences).
70 bool IsLegalizingCall;
73 Legal, // The target natively supports this operation.
74 Promote, // This operation should be executed in a larger type.
75 Expand // Try to expand this to other ops, otherwise use a libcall.
78 /// ValueTypeActions - This is a bitvector that contains two bits for each
79 /// value type, where the two bits correspond to the LegalizeAction enum.
80 /// This can be queried with "getTypeAction(VT)".
81 TargetLowering::ValueTypeActionImpl ValueTypeActions;
83 /// LegalizedNodes - For nodes that are of legal width, and that have more
84 /// than one use, this map indicates what regularized operand to use. This
85 /// allows us to avoid legalizing the same thing more than once.
86 DenseMap<SDValue, SDValue> LegalizedNodes;
88 void AddLegalizedOperand(SDValue From, SDValue To) {
89 LegalizedNodes.insert(std::make_pair(From, To));
90 // If someone requests legalization of the new node, return itself.
92 LegalizedNodes.insert(std::make_pair(To, To));
96 SelectionDAGLegalize(SelectionDAG &DAG, CodeGenOpt::Level ol);
98 /// getTypeAction - Return how we should legalize values of this type, either
99 /// it is already legal or we need to expand it into multiple registers of
100 /// smaller integer type, or we need to promote it to a larger type.
101 LegalizeAction getTypeAction(EVT VT) const {
103 (LegalizeAction)ValueTypeActions.getTypeAction(*DAG.getContext(), VT);
106 /// isTypeLegal - Return true if this type is legal on this target.
108 bool isTypeLegal(EVT VT) const {
109 return getTypeAction(VT) == Legal;
115 /// LegalizeOp - We know that the specified value has a legal type.
116 /// Recursively ensure that the operands have legal types, then return the
118 SDValue LegalizeOp(SDValue O);
120 SDValue OptimizeFloatStore(StoreSDNode *ST);
122 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
123 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
124 /// is necessary to spill the vector being inserted into to memory, perform
125 /// the insert there, and then read the result back.
126 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
127 SDValue Idx, DebugLoc dl);
128 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
129 SDValue Idx, DebugLoc dl);
131 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
132 /// performs the same shuffe in terms of order or result bytes, but on a type
133 /// whose vector element type is narrower than the original shuffle type.
134 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
135 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
136 SDValue N1, SDValue N2,
137 SmallVectorImpl<int> &Mask) const;
139 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
140 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
142 void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
145 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
146 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
147 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
148 RTLIB::Libcall Call_PPCF128);
149 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
150 RTLIB::Libcall Call_I8,
151 RTLIB::Libcall Call_I16,
152 RTLIB::Libcall Call_I32,
153 RTLIB::Libcall Call_I64,
154 RTLIB::Libcall Call_I128);
156 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl);
157 SDValue ExpandBUILD_VECTOR(SDNode *Node);
158 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
159 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
160 SmallVectorImpl<SDValue> &Results);
161 SDValue ExpandFCOPYSIGN(SDNode *Node);
162 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
164 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
166 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
169 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl);
170 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl);
172 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
173 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
175 void ExpandNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
176 void PromoteNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
180 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
181 /// performs the same shuffe in terms of order or result bytes, but on a type
182 /// whose vector element type is narrower than the original shuffle type.
183 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
185 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
186 SDValue N1, SDValue N2,
187 SmallVectorImpl<int> &Mask) const {
188 unsigned NumMaskElts = VT.getVectorNumElements();
189 unsigned NumDestElts = NVT.getVectorNumElements();
190 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
192 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
194 if (NumEltsGrowth == 1)
195 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
197 SmallVector<int, 8> NewMask;
198 for (unsigned i = 0; i != NumMaskElts; ++i) {
200 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
202 NewMask.push_back(-1);
204 NewMask.push_back(Idx * NumEltsGrowth + j);
207 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
208 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
209 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
212 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag,
213 CodeGenOpt::Level ol)
214 : TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()),
215 DAG(dag), OptLevel(ol),
216 ValueTypeActions(TLI.getValueTypeActions()) {
217 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
218 "Too many value types for ValueTypeActions to hold!");
221 void SelectionDAGLegalize::LegalizeDAG() {
222 LastCALLSEQ_END = DAG.getEntryNode();
223 IsLegalizingCall = false;
225 // The legalize process is inherently a bottom-up recursive process (users
226 // legalize their uses before themselves). Given infinite stack space, we
227 // could just start legalizing on the root and traverse the whole graph. In
228 // practice however, this causes us to run out of stack space on large basic
229 // blocks. To avoid this problem, compute an ordering of the nodes where each
230 // node is only legalized after all of its operands are legalized.
231 DAG.AssignTopologicalOrder();
232 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
233 E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I)
234 LegalizeOp(SDValue(I, 0));
236 // Finally, it's possible the root changed. Get the new root.
237 SDValue OldRoot = DAG.getRoot();
238 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
239 DAG.setRoot(LegalizedNodes[OldRoot]);
241 LegalizedNodes.clear();
243 // Remove dead nodes now.
244 DAG.RemoveDeadNodes();
248 /// FindCallEndFromCallStart - Given a chained node that is part of a call
249 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
250 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
251 if (Node->getOpcode() == ISD::CALLSEQ_END)
253 if (Node->use_empty())
254 return 0; // No CallSeqEnd
256 // The chain is usually at the end.
257 SDValue TheChain(Node, Node->getNumValues()-1);
258 if (TheChain.getValueType() != MVT::Other) {
259 // Sometimes it's at the beginning.
260 TheChain = SDValue(Node, 0);
261 if (TheChain.getValueType() != MVT::Other) {
262 // Otherwise, hunt for it.
263 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
264 if (Node->getValueType(i) == MVT::Other) {
265 TheChain = SDValue(Node, i);
269 // Otherwise, we walked into a node without a chain.
270 if (TheChain.getValueType() != MVT::Other)
275 for (SDNode::use_iterator UI = Node->use_begin(),
276 E = Node->use_end(); UI != E; ++UI) {
278 // Make sure to only follow users of our token chain.
280 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
281 if (User->getOperand(i) == TheChain)
282 if (SDNode *Result = FindCallEndFromCallStart(User))
288 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
289 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
290 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
291 assert(Node && "Didn't find callseq_start for a call??");
292 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
294 assert(Node->getOperand(0).getValueType() == MVT::Other &&
295 "Node doesn't have a token chain argument!");
296 return FindCallStartFromCallEnd(Node->getOperand(0).getNode());
299 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
300 /// see if any uses can reach Dest. If no dest operands can get to dest,
301 /// legalize them, legalize ourself, and return false, otherwise, return true.
303 /// Keep track of the nodes we fine that actually do lead to Dest in
304 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
306 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
307 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
308 if (N == Dest) return true; // N certainly leads to Dest :)
310 // If we've already processed this node and it does lead to Dest, there is no
311 // need to reprocess it.
312 if (NodesLeadingTo.count(N)) return true;
314 // If the first result of this node has been already legalized, then it cannot
316 if (LegalizedNodes.count(SDValue(N, 0))) return false;
318 // Okay, this node has not already been legalized. Check and legalize all
319 // operands. If none lead to Dest, then we can legalize this node.
320 bool OperandsLeadToDest = false;
321 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
322 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
323 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo);
325 if (OperandsLeadToDest) {
326 NodesLeadingTo.insert(N);
330 // Okay, this node looks safe, legalize it and return false.
331 LegalizeOp(SDValue(N, 0));
335 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
336 /// a load from the constant pool.
337 static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
338 SelectionDAG &DAG, const TargetLowering &TLI) {
340 DebugLoc dl = CFP->getDebugLoc();
342 // If a FP immediate is precise when represented as a float and if the
343 // target can do an extending load from float to double, we put it into
344 // the constant pool as a float, even if it's is statically typed as a
345 // double. This shrinks FP constants and canonicalizes them for targets where
346 // an FP extending load is the same cost as a normal load (such as on the x87
347 // fp stack or PPC FP unit).
348 EVT VT = CFP->getValueType(0);
349 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
351 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
352 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
353 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
358 while (SVT != MVT::f32) {
359 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
360 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
361 // Only do this if the target has a native EXTLOAD instruction from
363 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
364 TLI.ShouldShrinkFPConstant(OrigVT)) {
365 const Type *SType = SVT.getTypeForEVT(*DAG.getContext());
366 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
372 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
373 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
375 return DAG.getExtLoad(ISD::EXTLOAD, dl,
376 OrigVT, DAG.getEntryNode(),
377 CPIdx, PseudoSourceValue::getConstantPool(),
378 0, VT, false, false, Alignment);
379 return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
380 PseudoSourceValue::getConstantPool(), 0, false, false,
384 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
386 SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
387 const TargetLowering &TLI) {
388 SDValue Chain = ST->getChain();
389 SDValue Ptr = ST->getBasePtr();
390 SDValue Val = ST->getValue();
391 EVT VT = Val.getValueType();
392 int Alignment = ST->getAlignment();
393 int SVOffset = ST->getSrcValueOffset();
394 DebugLoc dl = ST->getDebugLoc();
395 if (ST->getMemoryVT().isFloatingPoint() ||
396 ST->getMemoryVT().isVector()) {
397 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
398 if (TLI.isTypeLegal(intVT)) {
399 // Expand to a bitconvert of the value to the integer type of the
400 // same size, then a (misaligned) int store.
401 // FIXME: Does not handle truncating floating point stores!
402 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, intVT, Val);
403 return DAG.getStore(Chain, dl, Result, Ptr, ST->getSrcValue(),
404 SVOffset, ST->isVolatile(), ST->isNonTemporal(),
407 // Do a (aligned) store to a stack slot, then copy from the stack slot
408 // to the final destination using (unaligned) integer loads and stores.
409 EVT StoredVT = ST->getMemoryVT();
411 TLI.getRegisterType(*DAG.getContext(),
412 EVT::getIntegerVT(*DAG.getContext(),
413 StoredVT.getSizeInBits()));
414 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
415 unsigned RegBytes = RegVT.getSizeInBits() / 8;
416 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
418 // Make sure the stack slot is also aligned for the register type.
419 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
421 // Perform the original store, only redirected to the stack slot.
422 SDValue Store = DAG.getTruncStore(Chain, dl,
423 Val, StackPtr, NULL, 0, StoredVT,
425 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
426 SmallVector<SDValue, 8> Stores;
429 // Do all but one copies using the full register width.
430 for (unsigned i = 1; i < NumRegs; i++) {
431 // Load one integer register's worth from the stack slot.
432 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, NULL, 0,
434 // Store it to the final location. Remember the store.
435 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
436 ST->getSrcValue(), SVOffset + Offset,
437 ST->isVolatile(), ST->isNonTemporal(),
438 MinAlign(ST->getAlignment(), Offset)));
439 // Increment the pointers.
441 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
443 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
446 // The last store may be partial. Do a truncating store. On big-endian
447 // machines this requires an extending load from the stack slot to ensure
448 // that the bits are in the right place.
449 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
450 8 * (StoredBytes - Offset));
452 // Load from the stack slot.
453 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
454 NULL, 0, MemVT, false, false, 0);
456 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
457 ST->getSrcValue(), SVOffset + Offset,
458 MemVT, ST->isVolatile(),
460 MinAlign(ST->getAlignment(), Offset)));
461 // The order of the stores doesn't matter - say it with a TokenFactor.
462 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
466 assert(ST->getMemoryVT().isInteger() &&
467 !ST->getMemoryVT().isVector() &&
468 "Unaligned store of unknown type.");
469 // Get the half-size VT
470 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext());
471 int NumBits = NewStoredVT.getSizeInBits();
472 int IncrementSize = NumBits / 8;
474 // Divide the stored value in two parts.
475 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
477 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
479 // Store the two parts
480 SDValue Store1, Store2;
481 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
482 ST->getSrcValue(), SVOffset, NewStoredVT,
483 ST->isVolatile(), ST->isNonTemporal(), Alignment);
484 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
485 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
486 Alignment = MinAlign(Alignment, IncrementSize);
487 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
488 ST->getSrcValue(), SVOffset + IncrementSize,
489 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(),
492 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
495 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
497 SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
498 const TargetLowering &TLI) {
499 int SVOffset = LD->getSrcValueOffset();
500 SDValue Chain = LD->getChain();
501 SDValue Ptr = LD->getBasePtr();
502 EVT VT = LD->getValueType(0);
503 EVT LoadedVT = LD->getMemoryVT();
504 DebugLoc dl = LD->getDebugLoc();
505 if (VT.isFloatingPoint() || VT.isVector()) {
506 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
507 if (TLI.isTypeLegal(intVT)) {
508 // Expand to a (misaligned) integer load of the same size,
509 // then bitconvert to floating point or vector.
510 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getSrcValue(),
511 SVOffset, LD->isVolatile(),
512 LD->isNonTemporal(), LD->getAlignment());
513 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, LoadedVT, newLoad);
514 if (VT.isFloatingPoint() && LoadedVT != VT)
515 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result);
517 SDValue Ops[] = { Result, Chain };
518 return DAG.getMergeValues(Ops, 2, dl);
520 // Copy the value to a (aligned) stack slot using (unaligned) integer
521 // loads and stores, then do a (aligned) load from the stack slot.
522 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
523 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
524 unsigned RegBytes = RegVT.getSizeInBits() / 8;
525 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
527 // Make sure the stack slot is also aligned for the register type.
528 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
530 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
531 SmallVector<SDValue, 8> Stores;
532 SDValue StackPtr = StackBase;
535 // Do all but one copies using the full register width.
536 for (unsigned i = 1; i < NumRegs; i++) {
537 // Load one integer register's worth from the original location.
538 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, LD->getSrcValue(),
539 SVOffset + Offset, LD->isVolatile(),
541 MinAlign(LD->getAlignment(), Offset));
542 // Follow the load with a store to the stack slot. Remember the store.
543 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
544 NULL, 0, false, false, 0));
545 // Increment the pointers.
547 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
548 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
552 // The last copy may be partial. Do an extending load.
553 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
554 8 * (LoadedBytes - Offset));
555 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
556 LD->getSrcValue(), SVOffset + Offset,
557 MemVT, LD->isVolatile(),
559 MinAlign(LD->getAlignment(), Offset));
560 // Follow the load with a store to the stack slot. Remember the store.
561 // On big-endian machines this requires a truncating store to ensure
562 // that the bits end up in the right place.
563 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
564 NULL, 0, MemVT, false, false, 0));
566 // The order of the stores doesn't matter - say it with a TokenFactor.
567 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
570 // Finally, perform the original load only redirected to the stack slot.
571 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
572 NULL, 0, LoadedVT, false, false, 0);
574 // Callers expect a MERGE_VALUES node.
575 SDValue Ops[] = { Load, TF };
576 return DAG.getMergeValues(Ops, 2, dl);
579 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
580 "Unaligned load of unsupported type.");
582 // Compute the new VT that is half the size of the old one. This is an
584 unsigned NumBits = LoadedVT.getSizeInBits();
586 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
589 unsigned Alignment = LD->getAlignment();
590 unsigned IncrementSize = NumBits / 8;
591 ISD::LoadExtType HiExtType = LD->getExtensionType();
593 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
594 if (HiExtType == ISD::NON_EXTLOAD)
595 HiExtType = ISD::ZEXTLOAD;
597 // Load the value in two parts
599 if (TLI.isLittleEndian()) {
600 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(),
601 SVOffset, NewLoadedVT, LD->isVolatile(),
602 LD->isNonTemporal(), Alignment);
603 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
604 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
605 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(),
606 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
607 LD->isNonTemporal(), MinAlign(Alignment, IncrementSize));
609 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(),
610 SVOffset, NewLoadedVT, LD->isVolatile(),
611 LD->isNonTemporal(), Alignment);
612 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
613 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
614 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(),
615 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
616 LD->isNonTemporal(), MinAlign(Alignment, IncrementSize));
619 // aggregate the two parts
620 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
621 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
622 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
624 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
627 SDValue Ops[] = { Result, TF };
628 return DAG.getMergeValues(Ops, 2, dl);
631 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
632 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
633 /// is necessary to spill the vector being inserted into to memory, perform
634 /// the insert there, and then read the result back.
635 SDValue SelectionDAGLegalize::
636 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
642 // If the target doesn't support this, we have to spill the input vector
643 // to a temporary stack slot, update the element, then reload it. This is
644 // badness. We could also load the value into a vector register (either
645 // with a "move to register" or "extload into register" instruction, then
646 // permute it into place, if the idx is a constant and if the idx is
647 // supported by the target.
648 EVT VT = Tmp1.getValueType();
649 EVT EltVT = VT.getVectorElementType();
650 EVT IdxVT = Tmp3.getValueType();
651 EVT PtrVT = TLI.getPointerTy();
652 SDValue StackPtr = DAG.CreateStackTemporary(VT);
654 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
657 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
658 PseudoSourceValue::getFixedStack(SPFI), 0,
661 // Truncate or zero extend offset to target pointer type.
662 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
663 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
664 // Add the offset to the index.
665 unsigned EltSize = EltVT.getSizeInBits()/8;
666 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
667 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
668 // Store the scalar value.
669 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2,
670 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT,
672 // Load the updated vector.
673 return DAG.getLoad(VT, dl, Ch, StackPtr,
674 PseudoSourceValue::getFixedStack(SPFI), 0,
679 SDValue SelectionDAGLegalize::
680 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) {
681 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
682 // SCALAR_TO_VECTOR requires that the type of the value being inserted
683 // match the element type of the vector being created, except for
684 // integers in which case the inserted value can be over width.
685 EVT EltVT = Vec.getValueType().getVectorElementType();
686 if (Val.getValueType() == EltVT ||
687 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
688 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
689 Vec.getValueType(), Val);
691 unsigned NumElts = Vec.getValueType().getVectorNumElements();
692 // We generate a shuffle of InVec and ScVec, so the shuffle mask
693 // should be 0,1,2,3,4,5... with the appropriate element replaced with
695 SmallVector<int, 8> ShufOps;
696 for (unsigned i = 0; i != NumElts; ++i)
697 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
699 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
703 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
706 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
707 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
708 // FIXME: We shouldn't do this for TargetConstantFP's.
709 // FIXME: move this to the DAG Combiner! Note that we can't regress due
710 // to phase ordering between legalized code and the dag combiner. This
711 // probably means that we need to integrate dag combiner and legalizer
713 // We generally can't do this one for long doubles.
714 SDValue Tmp1 = ST->getChain();
715 SDValue Tmp2 = ST->getBasePtr();
717 int SVOffset = ST->getSrcValueOffset();
718 unsigned Alignment = ST->getAlignment();
719 bool isVolatile = ST->isVolatile();
720 bool isNonTemporal = ST->isNonTemporal();
721 DebugLoc dl = ST->getDebugLoc();
722 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
723 if (CFP->getValueType(0) == MVT::f32 &&
724 getTypeAction(MVT::i32) == Legal) {
725 Tmp3 = DAG.getConstant(CFP->getValueAPF().
726 bitcastToAPInt().zextOrTrunc(32),
728 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
729 SVOffset, isVolatile, isNonTemporal, Alignment);
730 } else if (CFP->getValueType(0) == MVT::f64) {
731 // If this target supports 64-bit registers, do a single 64-bit store.
732 if (getTypeAction(MVT::i64) == Legal) {
733 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
734 zextOrTrunc(64), MVT::i64);
735 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
736 SVOffset, isVolatile, isNonTemporal, Alignment);
737 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
738 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
739 // stores. If the target supports neither 32- nor 64-bits, this
740 // xform is certainly not worth it.
741 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
742 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
743 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
744 if (TLI.isBigEndian()) std::swap(Lo, Hi);
746 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(),
747 SVOffset, isVolatile, isNonTemporal, Alignment);
748 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
749 DAG.getIntPtrConstant(4));
750 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
751 isVolatile, isNonTemporal, MinAlign(Alignment, 4U));
753 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
760 /// LegalizeOp - We know that the specified value has a legal type, and
761 /// that its operands are legal. Now ensure that the operation itself
762 /// is legal, recursively ensuring that the operands' operations remain
764 SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
765 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
768 SDNode *Node = Op.getNode();
769 DebugLoc dl = Node->getDebugLoc();
771 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
772 assert(getTypeAction(Node->getValueType(i)) == Legal &&
773 "Unexpected illegal type!");
775 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
776 assert((isTypeLegal(Node->getOperand(i).getValueType()) ||
777 Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
778 "Unexpected illegal type!");
780 // Note that LegalizeOp may be reentered even from single-use nodes, which
781 // means that we always must cache transformed nodes.
782 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
783 if (I != LegalizedNodes.end()) return I->second;
785 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
787 bool isCustom = false;
789 // Figure out the correct action; the way to query this varies by opcode
790 TargetLowering::LegalizeAction Action;
791 bool SimpleFinishLegalizing = true;
792 switch (Node->getOpcode()) {
793 case ISD::INTRINSIC_W_CHAIN:
794 case ISD::INTRINSIC_WO_CHAIN:
795 case ISD::INTRINSIC_VOID:
798 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
800 case ISD::SINT_TO_FP:
801 case ISD::UINT_TO_FP:
802 case ISD::EXTRACT_VECTOR_ELT:
803 Action = TLI.getOperationAction(Node->getOpcode(),
804 Node->getOperand(0).getValueType());
806 case ISD::FP_ROUND_INREG:
807 case ISD::SIGN_EXTEND_INREG: {
808 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
809 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
815 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
816 Node->getOpcode() == ISD::SETCC ? 2 : 1;
817 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
818 EVT OpVT = Node->getOperand(CompareOperand).getValueType();
819 ISD::CondCode CCCode =
820 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
821 Action = TLI.getCondCodeAction(CCCode, OpVT);
822 if (Action == TargetLowering::Legal) {
823 if (Node->getOpcode() == ISD::SELECT_CC)
824 Action = TLI.getOperationAction(Node->getOpcode(),
825 Node->getValueType(0));
827 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
833 // FIXME: Model these properly. LOAD and STORE are complicated, and
834 // STORE expects the unlegalized operand in some cases.
835 SimpleFinishLegalizing = false;
837 case ISD::CALLSEQ_START:
838 case ISD::CALLSEQ_END:
839 // FIXME: This shouldn't be necessary. These nodes have special properties
840 // dealing with the recursive nature of legalization. Removing this
841 // special case should be done as part of making LegalizeDAG non-recursive.
842 SimpleFinishLegalizing = false;
844 case ISD::EXTRACT_ELEMENT:
845 case ISD::FLT_ROUNDS_:
853 case ISD::MERGE_VALUES:
855 case ISD::FRAME_TO_ARGS_OFFSET:
856 // These operations lie about being legal: when they claim to be legal,
857 // they should actually be expanded.
858 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
859 if (Action == TargetLowering::Legal)
860 Action = TargetLowering::Expand;
862 case ISD::TRAMPOLINE:
864 case ISD::RETURNADDR:
865 // These operations lie about being legal: when they claim to be legal,
866 // they should actually be custom-lowered.
867 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
868 if (Action == TargetLowering::Legal)
869 Action = TargetLowering::Custom;
871 case ISD::BUILD_VECTOR:
872 // A weird case: legalization for BUILD_VECTOR never legalizes the
874 // FIXME: This really sucks... changing it isn't semantically incorrect,
875 // but it massively pessimizes the code for floating-point BUILD_VECTORs
876 // because ConstantFP operands get legalized into constant pool loads
877 // before the BUILD_VECTOR code can see them. It doesn't usually bite,
878 // though, because BUILD_VECTORS usually get lowered into other nodes
879 // which get legalized properly.
880 SimpleFinishLegalizing = false;
883 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
884 Action = TargetLowering::Legal;
886 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
891 if (SimpleFinishLegalizing) {
892 SmallVector<SDValue, 8> Ops, ResultVals;
893 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
894 Ops.push_back(LegalizeOp(Node->getOperand(i)));
895 switch (Node->getOpcode()) {
902 // Branches tweak the chain to include LastCALLSEQ_END
903 Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0],
905 Ops[0] = LegalizeOp(Ops[0]);
906 LastCALLSEQ_END = DAG.getEntryNode();
913 // Legalizing shifts/rotates requires adjusting the shift amount
914 // to the appropriate width.
915 if (!Ops[1].getValueType().isVector())
916 Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[1]));
921 // Legalizing shifts/rotates requires adjusting the shift amount
922 // to the appropriate width.
923 if (!Ops[2].getValueType().isVector())
924 Ops[2] = LegalizeOp(DAG.getShiftAmountOperand(Ops[2]));
928 Result = DAG.UpdateNodeOperands(Result.getValue(0), Ops.data(),
931 case TargetLowering::Legal:
932 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
933 ResultVals.push_back(Result.getValue(i));
935 case TargetLowering::Custom:
936 // FIXME: The handling for custom lowering with multiple results is
938 Tmp1 = TLI.LowerOperation(Result, DAG);
939 if (Tmp1.getNode()) {
940 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
942 ResultVals.push_back(Tmp1);
944 ResultVals.push_back(Tmp1.getValue(i));
950 case TargetLowering::Expand:
951 ExpandNode(Result.getNode(), ResultVals);
953 case TargetLowering::Promote:
954 PromoteNode(Result.getNode(), ResultVals);
957 if (!ResultVals.empty()) {
958 for (unsigned i = 0, e = ResultVals.size(); i != e; ++i) {
959 if (ResultVals[i] != SDValue(Node, i))
960 ResultVals[i] = LegalizeOp(ResultVals[i]);
961 AddLegalizedOperand(SDValue(Node, i), ResultVals[i]);
963 return ResultVals[Op.getResNo()];
967 switch (Node->getOpcode()) {
974 assert(0 && "Do not know how to legalize this operator!");
976 case ISD::BUILD_VECTOR:
977 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
978 default: assert(0 && "This action is not supported yet!");
979 case TargetLowering::Custom:
980 Tmp3 = TLI.LowerOperation(Result, DAG);
981 if (Tmp3.getNode()) {
986 case TargetLowering::Expand:
987 Result = ExpandBUILD_VECTOR(Result.getNode());
991 case ISD::CALLSEQ_START: {
992 SDNode *CallEnd = FindCallEndFromCallStart(Node);
994 // Recursively Legalize all of the inputs of the call end that do not lead
995 // to this call start. This ensures that any libcalls that need be inserted
996 // are inserted *before* the CALLSEQ_START.
997 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
998 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
999 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
1003 // Now that we legalized all of the inputs (which may have inserted
1004 // libcalls) create the new CALLSEQ_START node.
1005 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1007 // Merge in the last call, to ensure that this call start after the last
1009 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1010 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1011 Tmp1, LastCALLSEQ_END);
1012 Tmp1 = LegalizeOp(Tmp1);
1015 // Do not try to legalize the target-specific arguments (#1+).
1016 if (Tmp1 != Node->getOperand(0)) {
1017 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1019 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1022 // Remember that the CALLSEQ_START is legalized.
1023 AddLegalizedOperand(Op.getValue(0), Result);
1024 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1025 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1027 // Now that the callseq_start and all of the non-call nodes above this call
1028 // sequence have been legalized, legalize the call itself. During this
1029 // process, no libcalls can/will be inserted, guaranteeing that no calls
1031 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1032 // Note that we are selecting this call!
1033 LastCALLSEQ_END = SDValue(CallEnd, 0);
1034 IsLegalizingCall = true;
1036 // Legalize the call, starting from the CALLSEQ_END.
1037 LegalizeOp(LastCALLSEQ_END);
1038 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1041 case ISD::CALLSEQ_END:
1042 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1043 // will cause this node to be legalized as well as handling libcalls right.
1044 if (LastCALLSEQ_END.getNode() != Node) {
1045 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
1046 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1047 assert(I != LegalizedNodes.end() &&
1048 "Legalizing the call start should have legalized this node!");
1052 // Otherwise, the call start has been legalized and everything is going
1053 // according to plan. Just legalize ourselves normally here.
1054 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1055 // Do not try to legalize the target-specific arguments (#1+), except for
1056 // an optional flag input.
1057 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1058 if (Tmp1 != Node->getOperand(0)) {
1059 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1061 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1064 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1065 if (Tmp1 != Node->getOperand(0) ||
1066 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1067 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1070 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1073 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1074 // This finishes up call legalization.
1075 IsLegalizingCall = false;
1077 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1078 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1079 if (Node->getNumValues() == 2)
1080 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1081 return Result.getValue(Op.getResNo());
1083 LoadSDNode *LD = cast<LoadSDNode>(Node);
1084 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1085 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1087 ISD::LoadExtType ExtType = LD->getExtensionType();
1088 if (ExtType == ISD::NON_EXTLOAD) {
1089 EVT VT = Node->getValueType(0);
1090 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1091 Tmp3 = Result.getValue(0);
1092 Tmp4 = Result.getValue(1);
1094 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1095 default: assert(0 && "This action is not supported yet!");
1096 case TargetLowering::Legal:
1097 // If this is an unaligned load and the target doesn't support it,
1099 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
1100 const Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1101 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
1102 if (LD->getAlignment() < ABIAlignment){
1103 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
1105 Tmp3 = Result.getOperand(0);
1106 Tmp4 = Result.getOperand(1);
1107 Tmp3 = LegalizeOp(Tmp3);
1108 Tmp4 = LegalizeOp(Tmp4);
1112 case TargetLowering::Custom:
1113 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1114 if (Tmp1.getNode()) {
1115 Tmp3 = LegalizeOp(Tmp1);
1116 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1119 case TargetLowering::Promote: {
1120 // Only promote a load of vector type to another.
1121 assert(VT.isVector() && "Cannot promote this load!");
1122 // Change base type to a different vector type.
1123 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1125 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
1126 LD->getSrcValueOffset(),
1127 LD->isVolatile(), LD->isNonTemporal(),
1128 LD->getAlignment());
1129 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp1));
1130 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1134 // Since loads produce two values, make sure to remember that we
1135 // legalized both of them.
1136 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
1137 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
1138 return Op.getResNo() ? Tmp4 : Tmp3;
1140 EVT SrcVT = LD->getMemoryVT();
1141 unsigned SrcWidth = SrcVT.getSizeInBits();
1142 int SVOffset = LD->getSrcValueOffset();
1143 unsigned Alignment = LD->getAlignment();
1144 bool isVolatile = LD->isVolatile();
1145 bool isNonTemporal = LD->isNonTemporal();
1147 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
1148 // Some targets pretend to have an i1 loading operation, and actually
1149 // load an i8. This trick is correct for ZEXTLOAD because the top 7
1150 // bits are guaranteed to be zero; it helps the optimizers understand
1151 // that these bits are zero. It is also useful for EXTLOAD, since it
1152 // tells the optimizers that those bits are undefined. It would be
1153 // nice to have an effective generic way of getting these benefits...
1154 // Until such a way is found, don't insist on promoting i1 here.
1155 (SrcVT != MVT::i1 ||
1156 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
1157 // Promote to a byte-sized load if not loading an integral number of
1158 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
1159 unsigned NewWidth = SrcVT.getStoreSizeInBits();
1160 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
1163 // The extra bits are guaranteed to be zero, since we stored them that
1164 // way. A zext load from NVT thus automatically gives zext from SrcVT.
1166 ISD::LoadExtType NewExtType =
1167 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
1169 Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
1170 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
1171 NVT, isVolatile, isNonTemporal, Alignment);
1173 Ch = Result.getValue(1); // The chain.
1175 if (ExtType == ISD::SEXTLOAD)
1176 // Having the top bits zero doesn't help when sign extending.
1177 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1178 Result.getValueType(),
1179 Result, DAG.getValueType(SrcVT));
1180 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
1181 // All the top bits are guaranteed to be zero - inform the optimizers.
1182 Result = DAG.getNode(ISD::AssertZext, dl,
1183 Result.getValueType(), Result,
1184 DAG.getValueType(SrcVT));
1186 Tmp1 = LegalizeOp(Result);
1187 Tmp2 = LegalizeOp(Ch);
1188 } else if (SrcWidth & (SrcWidth - 1)) {
1189 // If not loading a power-of-2 number of bits, expand as two loads.
1190 assert(!SrcVT.isVector() && "Unsupported extload!");
1191 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
1192 assert(RoundWidth < SrcWidth);
1193 unsigned ExtraWidth = SrcWidth - RoundWidth;
1194 assert(ExtraWidth < RoundWidth);
1195 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1196 "Load size not an integral number of bytes!");
1197 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
1198 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
1200 unsigned IncrementSize;
1202 if (TLI.isLittleEndian()) {
1203 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1204 // Load the bottom RoundWidth bits.
1205 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl,
1206 Node->getValueType(0), Tmp1, Tmp2,
1207 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
1208 isNonTemporal, Alignment);
1210 // Load the remaining ExtraWidth bits.
1211 IncrementSize = RoundWidth / 8;
1212 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1213 DAG.getIntPtrConstant(IncrementSize));
1214 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
1215 LD->getSrcValue(), SVOffset + IncrementSize,
1216 ExtraVT, isVolatile, isNonTemporal,
1217 MinAlign(Alignment, IncrementSize));
1219 // Build a factor node to remember that this load is independent of the
1221 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1224 // Move the top bits to the right place.
1225 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1226 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
1228 // Join the hi and lo parts.
1229 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1231 // Big endian - avoid unaligned loads.
1232 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1233 // Load the top RoundWidth bits.
1234 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
1235 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
1236 isNonTemporal, Alignment);
1238 // Load the remaining ExtraWidth bits.
1239 IncrementSize = RoundWidth / 8;
1240 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1241 DAG.getIntPtrConstant(IncrementSize));
1242 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl,
1243 Node->getValueType(0), Tmp1, Tmp2,
1244 LD->getSrcValue(), SVOffset + IncrementSize,
1245 ExtraVT, isVolatile, isNonTemporal,
1246 MinAlign(Alignment, IncrementSize));
1248 // Build a factor node to remember that this load is independent of the
1250 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1253 // Move the top bits to the right place.
1254 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1255 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
1257 // Join the hi and lo parts.
1258 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1261 Tmp1 = LegalizeOp(Result);
1262 Tmp2 = LegalizeOp(Ch);
1264 switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
1265 default: assert(0 && "This action is not supported yet!");
1266 case TargetLowering::Custom:
1269 case TargetLowering::Legal:
1270 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1271 Tmp1 = Result.getValue(0);
1272 Tmp2 = Result.getValue(1);
1275 Tmp3 = TLI.LowerOperation(Result, DAG);
1276 if (Tmp3.getNode()) {
1277 Tmp1 = LegalizeOp(Tmp3);
1278 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1281 // If this is an unaligned load and the target doesn't support it,
1283 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
1284 const Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1285 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
1286 if (LD->getAlignment() < ABIAlignment){
1287 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
1289 Tmp1 = Result.getOperand(0);
1290 Tmp2 = Result.getOperand(1);
1291 Tmp1 = LegalizeOp(Tmp1);
1292 Tmp2 = LegalizeOp(Tmp2);
1297 case TargetLowering::Expand:
1298 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1299 // f128 = EXTLOAD {f32,f64} too
1300 if ((SrcVT == MVT::f32 && (Node->getValueType(0) == MVT::f64 ||
1301 Node->getValueType(0) == MVT::f128)) ||
1302 (SrcVT == MVT::f64 && Node->getValueType(0) == MVT::f128)) {
1303 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
1304 LD->getSrcValueOffset(),
1305 LD->isVolatile(), LD->isNonTemporal(),
1306 LD->getAlignment());
1307 Result = DAG.getNode(ISD::FP_EXTEND, dl,
1308 Node->getValueType(0), Load);
1309 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1310 Tmp2 = LegalizeOp(Load.getValue(1));
1313 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
1314 // Turn the unsupported load into an EXTLOAD followed by an explicit
1315 // zero/sign extend inreg.
1316 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
1317 Tmp1, Tmp2, LD->getSrcValue(),
1318 LD->getSrcValueOffset(), SrcVT,
1319 LD->isVolatile(), LD->isNonTemporal(),
1320 LD->getAlignment());
1322 if (ExtType == ISD::SEXTLOAD)
1323 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1324 Result.getValueType(),
1325 Result, DAG.getValueType(SrcVT));
1327 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT);
1328 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1329 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1334 // Since loads produce two values, make sure to remember that we legalized
1336 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
1337 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
1338 return Op.getResNo() ? Tmp2 : Tmp1;
1342 StoreSDNode *ST = cast<StoreSDNode>(Node);
1343 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
1344 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
1345 int SVOffset = ST->getSrcValueOffset();
1346 unsigned Alignment = ST->getAlignment();
1347 bool isVolatile = ST->isVolatile();
1348 bool isNonTemporal = ST->isNonTemporal();
1350 if (!ST->isTruncatingStore()) {
1351 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
1352 Result = SDValue(OptStore, 0);
1357 Tmp3 = LegalizeOp(ST->getValue());
1358 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1361 EVT VT = Tmp3.getValueType();
1362 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1363 default: assert(0 && "This action is not supported yet!");
1364 case TargetLowering::Legal:
1365 // If this is an unaligned store and the target doesn't support it,
1367 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
1368 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
1369 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
1370 if (ST->getAlignment() < ABIAlignment)
1371 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()),
1375 case TargetLowering::Custom:
1376 Tmp1 = TLI.LowerOperation(Result, DAG);
1377 if (Tmp1.getNode()) Result = Tmp1;
1379 case TargetLowering::Promote:
1380 assert(VT.isVector() && "Unknown legal promote case!");
1381 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, dl,
1382 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
1383 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2,
1384 ST->getSrcValue(), SVOffset, isVolatile,
1385 isNonTemporal, Alignment);
1391 Tmp3 = LegalizeOp(ST->getValue());
1393 EVT StVT = ST->getMemoryVT();
1394 unsigned StWidth = StVT.getSizeInBits();
1396 if (StWidth != StVT.getStoreSizeInBits()) {
1397 // Promote to a byte-sized store with upper bits zero if not
1398 // storing an integral number of bytes. For example, promote
1399 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
1400 EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
1401 StVT.getStoreSizeInBits());
1402 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT);
1403 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1404 SVOffset, NVT, isVolatile, isNonTemporal,
1406 } else if (StWidth & (StWidth - 1)) {
1407 // If not storing a power-of-2 number of bits, expand as two stores.
1408 assert(!StVT.isVector() && "Unsupported truncstore!");
1409 unsigned RoundWidth = 1 << Log2_32(StWidth);
1410 assert(RoundWidth < StWidth);
1411 unsigned ExtraWidth = StWidth - RoundWidth;
1412 assert(ExtraWidth < RoundWidth);
1413 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1414 "Store size not an integral number of bytes!");
1415 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
1416 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
1418 unsigned IncrementSize;
1420 if (TLI.isLittleEndian()) {
1421 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
1422 // Store the bottom RoundWidth bits.
1423 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1425 isVolatile, isNonTemporal, Alignment);
1427 // Store the remaining ExtraWidth bits.
1428 IncrementSize = RoundWidth / 8;
1429 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1430 DAG.getIntPtrConstant(IncrementSize));
1431 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
1432 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
1433 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
1434 SVOffset + IncrementSize, ExtraVT, isVolatile,
1436 MinAlign(Alignment, IncrementSize));
1438 // Big endian - avoid unaligned stores.
1439 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
1440 // Store the top RoundWidth bits.
1441 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
1442 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
1443 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
1444 SVOffset, RoundVT, isVolatile, isNonTemporal,
1447 // Store the remaining ExtraWidth bits.
1448 IncrementSize = RoundWidth / 8;
1449 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1450 DAG.getIntPtrConstant(IncrementSize));
1451 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1452 SVOffset + IncrementSize, ExtraVT, isVolatile,
1454 MinAlign(Alignment, IncrementSize));
1457 // The order of the stores doesn't matter.
1458 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
1460 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
1461 Tmp2 != ST->getBasePtr())
1462 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1465 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
1466 default: assert(0 && "This action is not supported yet!");
1467 case TargetLowering::Legal:
1468 // If this is an unaligned store and the target doesn't support it,
1470 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
1471 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
1472 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
1473 if (ST->getAlignment() < ABIAlignment)
1474 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()),
1478 case TargetLowering::Custom:
1479 Result = TLI.LowerOperation(Result, DAG);
1482 // TRUNCSTORE:i16 i32 -> STORE i16
1483 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
1484 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3);
1485 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1486 SVOffset, isVolatile, isNonTemporal,
1495 assert(Result.getValueType() == Op.getValueType() &&
1496 "Bad legalization!");
1498 // Make sure that the generated code is itself legal.
1500 Result = LegalizeOp(Result);
1502 // Note that LegalizeOp may be reentered even from single-use nodes, which
1503 // means that we always must cache transformed nodes.
1504 AddLegalizedOperand(Op, Result);
1508 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1509 SDValue Vec = Op.getOperand(0);
1510 SDValue Idx = Op.getOperand(1);
1511 DebugLoc dl = Op.getDebugLoc();
1512 // Store the value to a temporary stack slot, then LOAD the returned part.
1513 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1514 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0,
1517 // Add the offset to the index.
1519 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1520 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1521 DAG.getConstant(EltSize, Idx.getValueType()));
1523 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1524 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1526 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1528 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1530 if (Op.getValueType().isVector())
1531 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, NULL, 0,
1534 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
1535 NULL, 0, Vec.getValueType().getVectorElementType(),
1539 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1540 // We can't handle this case efficiently. Allocate a sufficiently
1541 // aligned object on the stack, store each element into it, then load
1542 // the result as a vector.
1543 // Create the stack frame object.
1544 EVT VT = Node->getValueType(0);
1545 EVT EltVT = VT.getVectorElementType();
1546 DebugLoc dl = Node->getDebugLoc();
1547 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1548 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1549 const Value *SV = PseudoSourceValue::getFixedStack(FI);
1551 // Emit a store of each element to the stack slot.
1552 SmallVector<SDValue, 8> Stores;
1553 unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1554 // Store (in the right endianness) the elements to memory.
1555 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1556 // Ignore undef elements.
1557 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1559 unsigned Offset = TypeByteSize*i;
1561 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
1562 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1564 // If the destination vector element type is narrower than the source
1565 // element type, only store the bits necessary.
1566 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1567 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1568 Node->getOperand(i), Idx, SV, Offset,
1569 EltVT, false, false, 0));
1571 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
1572 Node->getOperand(i), Idx, SV, Offset,
1577 if (!Stores.empty()) // Not all undef elements?
1578 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1579 &Stores[0], Stores.size());
1581 StoreChain = DAG.getEntryNode();
1583 // Result is a load from the stack slot.
1584 return DAG.getLoad(VT, dl, StoreChain, FIPtr, SV, 0, false, false, 0);
1587 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
1588 DebugLoc dl = Node->getDebugLoc();
1589 SDValue Tmp1 = Node->getOperand(0);
1590 SDValue Tmp2 = Node->getOperand(1);
1592 // Get the sign bit of the RHS. First obtain a value that has the same
1593 // sign as the sign bit, i.e. negative if and only if the sign bit is 1.
1595 EVT FloatVT = Tmp2.getValueType();
1596 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits());
1597 if (isTypeLegal(IVT)) {
1598 // Convert to an integer with the same sign bit.
1599 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, IVT, Tmp2);
1601 // Store the float to memory, then load the sign part out as an integer.
1602 MVT LoadTy = TLI.getPointerTy();
1603 // First create a temporary that is aligned for both the load and store.
1604 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1605 // Then store the float to it.
1607 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, NULL, 0,
1609 if (TLI.isBigEndian()) {
1610 assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1611 // Load out a legal integer with the same sign bit as the float.
1612 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, NULL, 0, false, false, 0);
1613 } else { // Little endian
1614 SDValue LoadPtr = StackPtr;
1615 // The float may be wider than the integer we are going to load. Advance
1616 // the pointer so that the loaded integer will contain the sign bit.
1617 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits();
1618 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8;
1619 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(),
1620 LoadPtr, DAG.getIntPtrConstant(ByteOffset));
1621 // Load a legal integer containing the sign bit.
1622 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, NULL, 0, false, false, 0);
1623 // Move the sign bit to the top bit of the loaded integer.
1624 unsigned BitShift = LoadTy.getSizeInBits() -
1625 (FloatVT.getSizeInBits() - 8 * ByteOffset);
1626 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?");
1628 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit,
1629 DAG.getConstant(BitShift,TLI.getShiftAmountTy()));
1632 // Now get the sign bit proper, by seeing whether the value is negative.
1633 SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()),
1634 SignBit, DAG.getConstant(0, SignBit.getValueType()),
1636 // Get the absolute value of the result.
1637 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1638 // Select between the nabs and abs value based on the sign bit of
1640 return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit,
1641 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1645 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1646 SmallVectorImpl<SDValue> &Results) {
1647 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1648 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1649 " not tell us which reg is the stack pointer!");
1650 DebugLoc dl = Node->getDebugLoc();
1651 EVT VT = Node->getValueType(0);
1652 SDValue Tmp1 = SDValue(Node, 0);
1653 SDValue Tmp2 = SDValue(Node, 1);
1654 SDValue Tmp3 = Node->getOperand(2);
1655 SDValue Chain = Tmp1.getOperand(0);
1657 // Chain the dynamic stack allocation so that it doesn't modify the stack
1658 // pointer when other instructions are using the stack.
1659 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1661 SDValue Size = Tmp2.getOperand(1);
1662 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1663 Chain = SP.getValue(1);
1664 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1665 unsigned StackAlign = TM.getFrameInfo()->getStackAlignment();
1666 if (Align > StackAlign)
1667 SP = DAG.getNode(ISD::AND, dl, VT, SP,
1668 DAG.getConstant(-(uint64_t)Align, VT));
1669 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1670 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1672 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1673 DAG.getIntPtrConstant(0, true), SDValue());
1675 Results.push_back(Tmp1);
1676 Results.push_back(Tmp2);
1679 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
1680 /// condition code CC on the current target. This routine expands SETCC with
1681 /// illegal condition code into AND / OR of multiple SETCC values.
1682 void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1683 SDValue &LHS, SDValue &RHS,
1686 EVT OpVT = LHS.getValueType();
1687 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1688 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1689 default: assert(0 && "Unknown condition code action!");
1690 case TargetLowering::Legal:
1693 case TargetLowering::Expand: {
1694 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1697 default: assert(0 && "Don't know how to expand this condition!");
1698 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break;
1699 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1700 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1701 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1702 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1703 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1704 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1705 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1706 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1707 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1708 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1709 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1710 // FIXME: Implement more expansions.
1713 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1714 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1715 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1723 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
1724 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1725 /// a load from the stack slot to DestVT, extending it if needed.
1726 /// The resultant code need not be legal.
1727 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
1731 // Create the stack frame object.
1733 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType().
1734 getTypeForEVT(*DAG.getContext()));
1735 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1737 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1738 int SPFI = StackPtrFI->getIndex();
1739 const Value *SV = PseudoSourceValue::getFixedStack(SPFI);
1741 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
1742 unsigned SlotSize = SlotVT.getSizeInBits();
1743 unsigned DestSize = DestVT.getSizeInBits();
1744 const Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
1745 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(DestType);
1747 // Emit a store to the stack slot. Use a truncstore if the input value is
1748 // later than DestVT.
1751 if (SrcSize > SlotSize)
1752 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1753 SV, 0, SlotVT, false, false, SrcAlign);
1755 assert(SrcSize == SlotSize && "Invalid store");
1756 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1757 SV, 0, false, false, SrcAlign);
1760 // Result is a load from the stack slot.
1761 if (SlotSize == DestSize)
1762 return DAG.getLoad(DestVT, dl, Store, FIPtr, SV, 0, false, false,
1765 assert(SlotSize < DestSize && "Unknown extension!");
1766 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, SV, 0, SlotVT,
1767 false, false, DestAlign);
1770 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1771 DebugLoc dl = Node->getDebugLoc();
1772 // Create a vector sized/aligned stack slot, store the value to element #0,
1773 // then load the whole vector back out.
1774 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1776 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1777 int SPFI = StackPtrFI->getIndex();
1779 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0),
1781 PseudoSourceValue::getFixedStack(SPFI), 0,
1782 Node->getValueType(0).getVectorElementType(),
1784 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
1785 PseudoSourceValue::getFixedStack(SPFI), 0,
1790 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
1791 /// support the operation, but do support the resultant vector type.
1792 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1793 unsigned NumElems = Node->getNumOperands();
1794 SDValue Value1, Value2;
1795 DebugLoc dl = Node->getDebugLoc();
1796 EVT VT = Node->getValueType(0);
1797 EVT OpVT = Node->getOperand(0).getValueType();
1798 EVT EltVT = VT.getVectorElementType();
1800 // If the only non-undef value is the low element, turn this into a
1801 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1802 bool isOnlyLowElement = true;
1803 bool MoreThanTwoValues = false;
1804 bool isConstant = true;
1805 for (unsigned i = 0; i < NumElems; ++i) {
1806 SDValue V = Node->getOperand(i);
1807 if (V.getOpcode() == ISD::UNDEF)
1810 isOnlyLowElement = false;
1811 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1814 if (!Value1.getNode()) {
1816 } else if (!Value2.getNode()) {
1819 } else if (V != Value1 && V != Value2) {
1820 MoreThanTwoValues = true;
1824 if (!Value1.getNode())
1825 return DAG.getUNDEF(VT);
1827 if (isOnlyLowElement)
1828 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1830 // If all elements are constants, create a load from the constant pool.
1832 std::vector<Constant*> CV;
1833 for (unsigned i = 0, e = NumElems; i != e; ++i) {
1834 if (ConstantFPSDNode *V =
1835 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1836 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1837 } else if (ConstantSDNode *V =
1838 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1840 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1842 // If OpVT and EltVT don't match, EltVT is not legal and the
1843 // element values have been promoted/truncated earlier. Undo this;
1844 // we don't want a v16i8 to become a v16i32 for example.
1845 const ConstantInt *CI = V->getConstantIntValue();
1846 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
1847 CI->getZExtValue()));
1850 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
1851 const Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
1852 CV.push_back(UndefValue::get(OpNTy));
1855 Constant *CP = ConstantVector::get(CV);
1856 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
1857 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
1858 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
1859 PseudoSourceValue::getConstantPool(), 0,
1860 false, false, Alignment);
1863 if (!MoreThanTwoValues) {
1864 SmallVector<int, 8> ShuffleVec(NumElems, -1);
1865 for (unsigned i = 0; i < NumElems; ++i) {
1866 SDValue V = Node->getOperand(i);
1867 if (V.getOpcode() == ISD::UNDEF)
1869 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
1871 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
1872 // Get the splatted value into the low element of a vector register.
1873 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
1875 if (Value2.getNode())
1876 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
1878 Vec2 = DAG.getUNDEF(VT);
1880 // Return shuffle(LowValVec, undef, <0,0,0,0>)
1881 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
1885 // Otherwise, we can't handle this case efficiently.
1886 return ExpandVectorBuildThroughStack(Node);
1889 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
1890 // does not fit into a register, return the lo part and set the hi part to the
1891 // by-reg argument. If it does fit into a single register, return the result
1892 // and leave the Hi part unset.
1893 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
1895 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
1896 // The input chain to this libcall is the entry node of the function.
1897 // Legalizing the call will automatically add the previous call to the
1899 SDValue InChain = DAG.getEntryNode();
1901 TargetLowering::ArgListTy Args;
1902 TargetLowering::ArgListEntry Entry;
1903 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1904 EVT ArgVT = Node->getOperand(i).getValueType();
1905 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1906 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
1907 Entry.isSExt = isSigned;
1908 Entry.isZExt = !isSigned;
1909 Args.push_back(Entry);
1911 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1912 TLI.getPointerTy());
1914 // Splice the libcall in wherever FindInputOutputChains tells us to.
1915 const Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
1916 std::pair<SDValue, SDValue> CallInfo =
1917 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
1918 0, TLI.getLibcallCallingConv(LC), false,
1919 /*isReturnValueUsed=*/true,
1920 Callee, Args, DAG, Node->getDebugLoc());
1922 // Legalize the call sequence, starting with the chain. This will advance
1923 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
1924 // was added by LowerCallTo (guaranteeing proper serialization of calls).
1925 LegalizeOp(CallInfo.second);
1926 return CallInfo.first;
1929 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
1930 RTLIB::Libcall Call_F32,
1931 RTLIB::Libcall Call_F64,
1932 RTLIB::Libcall Call_F80,
1933 RTLIB::Libcall Call_PPCF128) {
1935 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
1936 default: assert(0 && "Unexpected request for libcall!");
1937 case MVT::f32: LC = Call_F32; break;
1938 case MVT::f64: LC = Call_F64; break;
1939 case MVT::f80: LC = Call_F80; break;
1940 case MVT::ppcf128: LC = Call_PPCF128; break;
1942 return ExpandLibCall(LC, Node, false);
1945 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
1946 RTLIB::Libcall Call_I8,
1947 RTLIB::Libcall Call_I16,
1948 RTLIB::Libcall Call_I32,
1949 RTLIB::Libcall Call_I64,
1950 RTLIB::Libcall Call_I128) {
1952 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
1953 default: assert(0 && "Unexpected request for libcall!");
1954 case MVT::i8: LC = Call_I8; break;
1955 case MVT::i16: LC = Call_I16; break;
1956 case MVT::i32: LC = Call_I32; break;
1957 case MVT::i64: LC = Call_I64; break;
1958 case MVT::i128: LC = Call_I128; break;
1960 return ExpandLibCall(LC, Node, isSigned);
1963 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
1964 /// INT_TO_FP operation of the specified operand when the target requests that
1965 /// we expand it. At this point, we know that the result and operand types are
1966 /// legal for the target.
1967 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
1971 if (Op0.getValueType() == MVT::i32) {
1972 // simple 32-bit [signed|unsigned] integer to float/double expansion
1974 // Get the stack frame index of a 8 byte buffer.
1975 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
1977 // word offset constant for Hi/Lo address computation
1978 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
1979 // set up Hi and Lo (into buffer) address based on endian
1980 SDValue Hi = StackSlot;
1981 SDValue Lo = DAG.getNode(ISD::ADD, dl,
1982 TLI.getPointerTy(), StackSlot, WordOff);
1983 if (TLI.isLittleEndian())
1986 // if signed map to unsigned space
1989 // constant used to invert sign bit (signed to unsigned mapping)
1990 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
1991 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
1995 // store the lo of the constructed double - based on integer input
1996 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
1997 Op0Mapped, Lo, NULL, 0,
1999 // initial hi portion of constructed double
2000 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
2001 // store the hi of the constructed double - biased exponent
2002 SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0,
2004 // load the constructed double
2005 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0,
2007 // FP constant to bias correct the final result
2008 SDValue Bias = DAG.getConstantFP(isSigned ?
2009 BitsToDouble(0x4330000080000000ULL) :
2010 BitsToDouble(0x4330000000000000ULL),
2012 // subtract the bias
2013 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2016 // handle final rounding
2017 if (DestVT == MVT::f64) {
2020 } else if (DestVT.bitsLT(MVT::f64)) {
2021 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2022 DAG.getIntPtrConstant(0));
2023 } else if (DestVT.bitsGT(MVT::f64)) {
2024 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2028 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2029 // Code below here assumes !isSigned without checking again.
2031 // Implementation of unsigned i64 to f64 following the algorithm in
2032 // __floatundidf in compiler_rt. This implementation has the advantage
2033 // of performing rounding correctly, both in the default rounding mode
2034 // and in all alternate rounding modes.
2035 // TODO: Generalize this for use with other types.
2036 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
2038 DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64);
2039 SDValue TwoP84PlusTwoP52 =
2040 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64);
2042 DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64);
2044 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32);
2045 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2046 DAG.getConstant(32, MVT::i64));
2047 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2048 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2049 SDValue LoFlt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, LoOr);
2050 SDValue HiFlt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, HiOr);
2051 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt, TwoP84PlusTwoP52);
2052 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
2055 // Implementation of unsigned i64 to f32. This implementation has the
2056 // advantage of performing rounding correctly.
2057 // TODO: Generalize this for use with other types.
2058 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) {
2059 EVT SHVT = TLI.getShiftAmountTy();
2061 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2062 DAG.getConstant(UINT64_C(0xfffffffffffff800), MVT::i64));
2063 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
2064 DAG.getConstant(UINT64_C(0x800), MVT::i64));
2065 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2066 DAG.getConstant(UINT64_C(0x7ff), MVT::i64));
2067 SDValue Ne = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2068 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE);
2069 SDValue Sel = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ne, Or, Op0);
2070 SDValue Ge = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2071 Op0, DAG.getConstant(UINT64_C(0x0020000000000000), MVT::i64),
2073 SDValue Sel2 = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ge, Sel, Op0);
2075 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2076 DAG.getConstant(32, SHVT));
2077 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh);
2078 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc);
2080 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), MVT::f64);
2081 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt);
2082 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2);
2083 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo);
2084 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2);
2085 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd,
2086 DAG.getIntPtrConstant(0));
2090 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2092 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()),
2093 Op0, DAG.getConstant(0, Op0.getValueType()),
2095 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
2096 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
2097 SignSet, Four, Zero);
2099 // If the sign bit of the integer is set, the large number will be treated
2100 // as a negative number. To counteract this, the dynamic code adds an
2101 // offset depending on the data type.
2103 switch (Op0.getValueType().getSimpleVT().SimpleTy) {
2104 default: assert(0 && "Unsupported integer type!");
2105 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2106 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2107 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2108 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2110 if (TLI.isLittleEndian()) FF <<= 32;
2111 Constant *FudgeFactor = ConstantInt::get(
2112 Type::getInt64Ty(*DAG.getContext()), FF);
2114 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
2115 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2116 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
2117 Alignment = std::min(Alignment, 4u);
2119 if (DestVT == MVT::f32)
2120 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2121 PseudoSourceValue::getConstantPool(), 0,
2122 false, false, Alignment);
2125 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
2126 DAG.getEntryNode(), CPIdx,
2127 PseudoSourceValue::getConstantPool(), 0,
2128 MVT::f32, false, false, Alignment));
2131 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2134 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
2135 /// *INT_TO_FP operation of the specified operand when the target requests that
2136 /// we promote it. At this point, we know that the result and operand types are
2137 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2138 /// operation that takes a larger input.
2139 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2143 // First step, figure out the appropriate *INT_TO_FP operation to use.
2144 EVT NewInTy = LegalOp.getValueType();
2146 unsigned OpToUse = 0;
2148 // Scan for the appropriate larger type to use.
2150 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2151 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2153 // If the target supports SINT_TO_FP of this type, use it.
2154 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2155 OpToUse = ISD::SINT_TO_FP;
2158 if (isSigned) continue;
2160 // If the target supports UINT_TO_FP of this type, use it.
2161 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2162 OpToUse = ISD::UINT_TO_FP;
2166 // Otherwise, try a larger type.
2169 // Okay, we found the operation and type to use. Zero extend our input to the
2170 // desired type then run the operation on it.
2171 return DAG.getNode(OpToUse, dl, DestVT,
2172 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2173 dl, NewInTy, LegalOp));
2176 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
2177 /// FP_TO_*INT operation of the specified operand when the target requests that
2178 /// we promote it. At this point, we know that the result and operand types are
2179 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2180 /// operation that returns a larger result.
2181 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2185 // First step, figure out the appropriate FP_TO*INT operation to use.
2186 EVT NewOutTy = DestVT;
2188 unsigned OpToUse = 0;
2190 // Scan for the appropriate larger type to use.
2192 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2193 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2195 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2196 OpToUse = ISD::FP_TO_SINT;
2200 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2201 OpToUse = ISD::FP_TO_UINT;
2205 // Otherwise, try a larger type.
2209 // Okay, we found the operation and type to use.
2210 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2212 // Truncate the result of the extended FP_TO_*INT operation to the desired
2214 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2217 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
2219 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) {
2220 EVT VT = Op.getValueType();
2221 EVT SHVT = TLI.getShiftAmountTy();
2222 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2223 switch (VT.getSimpleVT().SimpleTy) {
2224 default: assert(0 && "Unhandled Expand type in BSWAP!");
2226 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2227 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2228 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2230 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2231 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2232 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2233 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2234 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
2235 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
2236 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2237 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2238 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2240 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
2241 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
2242 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2243 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2244 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2245 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2246 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
2247 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
2248 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
2249 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
2250 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
2251 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
2252 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
2253 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
2254 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2255 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2256 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2257 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2258 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2259 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2260 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2264 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
2266 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2269 default: assert(0 && "Cannot expand this yet!");
2271 static const uint64_t mask[6] = {
2272 0x5555555555555555ULL, 0x3333333333333333ULL,
2273 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
2274 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
2276 EVT VT = Op.getValueType();
2277 EVT ShVT = TLI.getShiftAmountTy();
2278 unsigned len = VT.getSizeInBits();
2279 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2280 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
2281 unsigned EltSize = VT.isVector() ?
2282 VT.getVectorElementType().getSizeInBits() : len;
2283 SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT);
2284 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2285 Op = DAG.getNode(ISD::ADD, dl, VT,
2286 DAG.getNode(ISD::AND, dl, VT, Op, Tmp2),
2287 DAG.getNode(ISD::AND, dl, VT,
2288 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3),
2294 // for now, we do this:
2295 // x = x | (x >> 1);
2296 // x = x | (x >> 2);
2298 // x = x | (x >>16);
2299 // x = x | (x >>32); // for 64-bit input
2300 // return popcount(~x);
2302 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
2303 EVT VT = Op.getValueType();
2304 EVT ShVT = TLI.getShiftAmountTy();
2305 unsigned len = VT.getSizeInBits();
2306 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2307 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2308 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2309 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2311 Op = DAG.getNOT(dl, Op, VT);
2312 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2315 // for now, we use: { return popcount(~x & (x - 1)); }
2316 // unless the target has ctlz but not ctpop, in which case we use:
2317 // { return 32 - nlz(~x & (x-1)); }
2318 // see also http://www.hackersdelight.org/HDcode/ntz.cc
2319 EVT VT = Op.getValueType();
2320 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2321 DAG.getNOT(dl, Op, VT),
2322 DAG.getNode(ISD::SUB, dl, VT, Op,
2323 DAG.getConstant(1, VT)));
2324 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2325 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2326 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2327 return DAG.getNode(ISD::SUB, dl, VT,
2328 DAG.getConstant(VT.getSizeInBits(), VT),
2329 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2330 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2335 void SelectionDAGLegalize::ExpandNode(SDNode *Node,
2336 SmallVectorImpl<SDValue> &Results) {
2337 DebugLoc dl = Node->getDebugLoc();
2338 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2339 switch (Node->getOpcode()) {
2343 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
2344 Results.push_back(Tmp1);
2347 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2349 case ISD::FRAMEADDR:
2350 case ISD::RETURNADDR:
2351 case ISD::FRAME_TO_ARGS_OFFSET:
2352 Results.push_back(DAG.getConstant(0, Node->getValueType(0)));
2354 case ISD::FLT_ROUNDS_:
2355 Results.push_back(DAG.getConstant(1, Node->getValueType(0)));
2357 case ISD::EH_RETURN:
2360 case ISD::MEMBARRIER:
2362 Results.push_back(Node->getOperand(0));
2364 case ISD::DYNAMIC_STACKALLOC:
2365 ExpandDYNAMIC_STACKALLOC(Node, Results);
2367 case ISD::MERGE_VALUES:
2368 for (unsigned i = 0; i < Node->getNumValues(); i++)
2369 Results.push_back(Node->getOperand(i));
2372 EVT VT = Node->getValueType(0);
2374 Results.push_back(DAG.getConstant(0, VT));
2376 assert(VT.isFloatingPoint() && "Unknown value type!");
2377 Results.push_back(DAG.getConstantFP(0, VT));
2382 // If this operation is not supported, lower it to 'abort()' call
2383 TargetLowering::ArgListTy Args;
2384 std::pair<SDValue, SDValue> CallResult =
2385 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()),
2386 false, false, false, false, 0, CallingConv::C, false,
2387 /*isReturnValueUsed=*/true,
2388 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
2390 Results.push_back(CallResult.second);
2394 case ISD::BIT_CONVERT:
2395 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
2396 Node->getValueType(0), dl);
2397 Results.push_back(Tmp1);
2399 case ISD::FP_EXTEND:
2400 Tmp1 = EmitStackConvert(Node->getOperand(0),
2401 Node->getOperand(0).getValueType(),
2402 Node->getValueType(0), dl);
2403 Results.push_back(Tmp1);
2405 case ISD::SIGN_EXTEND_INREG: {
2406 // NOTE: we could fall back on load/store here too for targets without
2407 // SAR. However, it is doubtful that any exist.
2408 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2409 EVT VT = Node->getValueType(0);
2410 EVT ShiftAmountTy = TLI.getShiftAmountTy();
2413 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
2414 ExtraVT.getScalarType().getSizeInBits();
2415 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy);
2416 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
2417 Node->getOperand(0), ShiftCst);
2418 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
2419 Results.push_back(Tmp1);
2422 case ISD::FP_ROUND_INREG: {
2423 // The only way we can lower this is to turn it into a TRUNCSTORE,
2424 // EXTLOAD pair, targetting a temporary location (a stack slot).
2426 // NOTE: there is a choice here between constantly creating new stack
2427 // slots and always reusing the same one. We currently always create
2428 // new ones, as reuse may inhibit scheduling.
2429 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2430 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
2431 Node->getValueType(0), dl);
2432 Results.push_back(Tmp1);
2435 case ISD::SINT_TO_FP:
2436 case ISD::UINT_TO_FP:
2437 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
2438 Node->getOperand(0), Node->getValueType(0), dl);
2439 Results.push_back(Tmp1);
2441 case ISD::FP_TO_UINT: {
2442 SDValue True, False;
2443 EVT VT = Node->getOperand(0).getValueType();
2444 EVT NVT = Node->getValueType(0);
2445 const uint64_t zero[] = {0, 0};
2446 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero));
2447 APInt x = APInt::getSignBit(NVT.getSizeInBits());
2448 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
2449 Tmp1 = DAG.getConstantFP(apf, VT);
2450 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
2451 Node->getOperand(0),
2453 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
2454 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
2455 DAG.getNode(ISD::FSUB, dl, VT,
2456 Node->getOperand(0), Tmp1));
2457 False = DAG.getNode(ISD::XOR, dl, NVT, False,
2458 DAG.getConstant(x, NVT));
2459 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False);
2460 Results.push_back(Tmp1);
2464 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2465 EVT VT = Node->getValueType(0);
2466 Tmp1 = Node->getOperand(0);
2467 Tmp2 = Node->getOperand(1);
2468 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0,
2470 // Increment the pointer, VAList, to the next vaarg
2471 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
2472 DAG.getConstant(TLI.getTargetData()->
2473 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())),
2474 TLI.getPointerTy()));
2475 // Store the incremented VAList to the legalized pointer
2476 Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0,
2478 // Load the actual argument out of the pointer VAList
2479 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, NULL, 0,
2481 Results.push_back(Results[0].getValue(1));
2485 // This defaults to loading a pointer from the input and storing it to the
2486 // output, returning the chain.
2487 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
2488 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
2489 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0),
2490 Node->getOperand(2), VS, 0, false, false, 0);
2491 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1), VD, 0,
2493 Results.push_back(Tmp1);
2496 case ISD::EXTRACT_VECTOR_ELT:
2497 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
2498 // This must be an access of the only element. Return it.
2499 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0),
2500 Node->getOperand(0));
2502 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
2503 Results.push_back(Tmp1);
2505 case ISD::EXTRACT_SUBVECTOR:
2506 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
2508 case ISD::CONCAT_VECTORS: {
2509 Results.push_back(ExpandVectorBuildThroughStack(Node));
2512 case ISD::SCALAR_TO_VECTOR:
2513 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
2515 case ISD::INSERT_VECTOR_ELT:
2516 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
2517 Node->getOperand(1),
2518 Node->getOperand(2), dl));
2520 case ISD::VECTOR_SHUFFLE: {
2521 SmallVector<int, 8> Mask;
2522 cast<ShuffleVectorSDNode>(Node)->getMask(Mask);
2524 EVT VT = Node->getValueType(0);
2525 EVT EltVT = VT.getVectorElementType();
2526 if (getTypeAction(EltVT) == Promote)
2527 EltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
2528 unsigned NumElems = VT.getVectorNumElements();
2529 SmallVector<SDValue, 8> Ops;
2530 for (unsigned i = 0; i != NumElems; ++i) {
2532 Ops.push_back(DAG.getUNDEF(EltVT));
2535 unsigned Idx = Mask[i];
2537 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
2538 Node->getOperand(0),
2539 DAG.getIntPtrConstant(Idx)));
2541 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
2542 Node->getOperand(1),
2543 DAG.getIntPtrConstant(Idx - NumElems)));
2545 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
2546 Results.push_back(Tmp1);
2549 case ISD::EXTRACT_ELEMENT: {
2550 EVT OpTy = Node->getOperand(0).getValueType();
2551 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
2553 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
2554 DAG.getConstant(OpTy.getSizeInBits()/2,
2555 TLI.getShiftAmountTy()));
2556 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
2559 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
2560 Node->getOperand(0));
2562 Results.push_back(Tmp1);
2565 case ISD::STACKSAVE:
2566 // Expand to CopyFromReg if the target set
2567 // StackPointerRegisterToSaveRestore.
2568 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2569 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
2570 Node->getValueType(0)));
2571 Results.push_back(Results[0].getValue(1));
2573 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
2574 Results.push_back(Node->getOperand(0));
2577 case ISD::STACKRESTORE:
2578 // Expand to CopyToReg if the target set
2579 // StackPointerRegisterToSaveRestore.
2580 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2581 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
2582 Node->getOperand(1)));
2584 Results.push_back(Node->getOperand(0));
2587 case ISD::FCOPYSIGN:
2588 Results.push_back(ExpandFCOPYSIGN(Node));
2591 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2592 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2593 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
2594 Node->getOperand(0));
2595 Results.push_back(Tmp1);
2598 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2599 EVT VT = Node->getValueType(0);
2600 Tmp1 = Node->getOperand(0);
2601 Tmp2 = DAG.getConstantFP(0.0, VT);
2602 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
2603 Tmp1, Tmp2, ISD::SETUGT);
2604 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
2605 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3);
2606 Results.push_back(Tmp1);
2610 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
2611 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128));
2614 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
2615 RTLIB::SIN_F80, RTLIB::SIN_PPCF128));
2618 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
2619 RTLIB::COS_F80, RTLIB::COS_PPCF128));
2622 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
2623 RTLIB::LOG_F80, RTLIB::LOG_PPCF128));
2626 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
2627 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128));
2630 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
2631 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128));
2634 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
2635 RTLIB::EXP_F80, RTLIB::EXP_PPCF128));
2638 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
2639 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128));
2642 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
2643 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128));
2646 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
2647 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128));
2650 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
2651 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128));
2654 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
2655 RTLIB::RINT_F80, RTLIB::RINT_PPCF128));
2657 case ISD::FNEARBYINT:
2658 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
2659 RTLIB::NEARBYINT_F64,
2660 RTLIB::NEARBYINT_F80,
2661 RTLIB::NEARBYINT_PPCF128));
2664 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
2665 RTLIB::POWI_F80, RTLIB::POWI_PPCF128));
2668 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
2669 RTLIB::POW_F80, RTLIB::POW_PPCF128));
2672 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
2673 RTLIB::DIV_F80, RTLIB::DIV_PPCF128));
2676 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
2677 RTLIB::REM_F80, RTLIB::REM_PPCF128));
2679 case ISD::FP16_TO_FP32:
2680 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
2682 case ISD::FP32_TO_FP16:
2683 Results.push_back(ExpandLibCall(RTLIB::FPROUND_F32_F16, Node, false));
2685 case ISD::ConstantFP: {
2686 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
2687 // Check to see if this FP immediate is already legal.
2688 // If this is a legal constant, turn it into a TargetConstantFP node.
2689 if (TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
2690 Results.push_back(SDValue(Node, 0));
2692 Results.push_back(ExpandConstantFP(CFP, true, DAG, TLI));
2695 case ISD::EHSELECTION: {
2696 unsigned Reg = TLI.getExceptionSelectorRegister();
2697 assert(Reg && "Can't expand to unknown register!");
2698 Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg,
2699 Node->getValueType(0)));
2700 Results.push_back(Results[0].getValue(1));
2703 case ISD::EXCEPTIONADDR: {
2704 unsigned Reg = TLI.getExceptionAddressRegister();
2705 assert(Reg && "Can't expand to unknown register!");
2706 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg,
2707 Node->getValueType(0)));
2708 Results.push_back(Results[0].getValue(1));
2712 EVT VT = Node->getValueType(0);
2713 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
2714 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
2715 "Don't know how to expand this subtraction!");
2716 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
2717 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
2718 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT));
2719 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
2724 EVT VT = Node->getValueType(0);
2725 SDVTList VTs = DAG.getVTList(VT, VT);
2726 bool isSigned = Node->getOpcode() == ISD::SREM;
2727 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
2728 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2729 Tmp2 = Node->getOperand(0);
2730 Tmp3 = Node->getOperand(1);
2731 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) {
2732 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
2733 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
2735 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
2736 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
2737 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
2738 } else if (isSigned) {
2739 Tmp1 = ExpandIntLibCall(Node, true,
2741 RTLIB::SREM_I16, RTLIB::SREM_I32,
2742 RTLIB::SREM_I64, RTLIB::SREM_I128);
2744 Tmp1 = ExpandIntLibCall(Node, false,
2746 RTLIB::UREM_I16, RTLIB::UREM_I32,
2747 RTLIB::UREM_I64, RTLIB::UREM_I128);
2749 Results.push_back(Tmp1);
2754 bool isSigned = Node->getOpcode() == ISD::SDIV;
2755 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2756 EVT VT = Node->getValueType(0);
2757 SDVTList VTs = DAG.getVTList(VT, VT);
2758 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT))
2759 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
2760 Node->getOperand(1));
2762 Tmp1 = ExpandIntLibCall(Node, true,
2764 RTLIB::SDIV_I16, RTLIB::SDIV_I32,
2765 RTLIB::SDIV_I64, RTLIB::SDIV_I128);
2767 Tmp1 = ExpandIntLibCall(Node, false,
2769 RTLIB::UDIV_I16, RTLIB::UDIV_I32,
2770 RTLIB::UDIV_I64, RTLIB::UDIV_I128);
2771 Results.push_back(Tmp1);
2776 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
2778 EVT VT = Node->getValueType(0);
2779 SDVTList VTs = DAG.getVTList(VT, VT);
2780 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
2781 "If this wasn't legal, it shouldn't have been created!");
2782 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
2783 Node->getOperand(1));
2784 Results.push_back(Tmp1.getValue(1));
2788 EVT VT = Node->getValueType(0);
2789 SDVTList VTs = DAG.getVTList(VT, VT);
2790 // See if multiply or divide can be lowered using two-result operations.
2791 // We just need the low half of the multiply; try both the signed
2792 // and unsigned forms. If the target supports both SMUL_LOHI and
2793 // UMUL_LOHI, form a preference by checking which forms of plain
2794 // MULH it supports.
2795 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
2796 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
2797 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
2798 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
2799 unsigned OpToUse = 0;
2800 if (HasSMUL_LOHI && !HasMULHS) {
2801 OpToUse = ISD::SMUL_LOHI;
2802 } else if (HasUMUL_LOHI && !HasMULHU) {
2803 OpToUse = ISD::UMUL_LOHI;
2804 } else if (HasSMUL_LOHI) {
2805 OpToUse = ISD::SMUL_LOHI;
2806 } else if (HasUMUL_LOHI) {
2807 OpToUse = ISD::UMUL_LOHI;
2810 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
2811 Node->getOperand(1)));
2814 Tmp1 = ExpandIntLibCall(Node, false,
2816 RTLIB::MUL_I16, RTLIB::MUL_I32,
2817 RTLIB::MUL_I64, RTLIB::MUL_I128);
2818 Results.push_back(Tmp1);
2823 SDValue LHS = Node->getOperand(0);
2824 SDValue RHS = Node->getOperand(1);
2825 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
2826 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2828 Results.push_back(Sum);
2829 EVT OType = Node->getValueType(1);
2831 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
2833 // LHSSign -> LHS >= 0
2834 // RHSSign -> RHS >= 0
2835 // SumSign -> Sum >= 0
2838 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
2840 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
2842 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
2843 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
2844 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
2845 Node->getOpcode() == ISD::SADDO ?
2846 ISD::SETEQ : ISD::SETNE);
2848 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
2849 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
2851 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
2852 Results.push_back(Cmp);
2857 SDValue LHS = Node->getOperand(0);
2858 SDValue RHS = Node->getOperand(1);
2859 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
2860 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2862 Results.push_back(Sum);
2863 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS,
2864 Node->getOpcode () == ISD::UADDO ?
2865 ISD::SETULT : ISD::SETUGT));
2870 EVT VT = Node->getValueType(0);
2871 SDValue LHS = Node->getOperand(0);
2872 SDValue RHS = Node->getOperand(1);
2875 static const unsigned Ops[2][3] =
2876 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
2877 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
2878 bool isSigned = Node->getOpcode() == ISD::SMULO;
2879 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
2880 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
2881 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
2882 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
2883 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
2885 TopHalf = BottomHalf.getValue(1);
2887 // FIXME: We should be able to fall back to a libcall with an illegal
2888 // type in some cases.
2889 // Also, we can fall back to a division in some cases, but that's a big
2890 // performance hit in the general case.
2891 assert(TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(),
2892 VT.getSizeInBits() * 2)) &&
2893 "Don't know how to expand this operation yet!");
2894 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
2895 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
2896 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
2897 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
2898 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
2899 DAG.getIntPtrConstant(0));
2900 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
2901 DAG.getIntPtrConstant(1));
2904 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1, TLI.getShiftAmountTy());
2905 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
2906 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1,
2909 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf,
2910 DAG.getConstant(0, VT), ISD::SETNE);
2912 Results.push_back(BottomHalf);
2913 Results.push_back(TopHalf);
2916 case ISD::BUILD_PAIR: {
2917 EVT PairTy = Node->getValueType(0);
2918 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
2919 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
2920 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
2921 DAG.getConstant(PairTy.getSizeInBits()/2,
2922 TLI.getShiftAmountTy()));
2923 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
2927 Tmp1 = Node->getOperand(0);
2928 Tmp2 = Node->getOperand(1);
2929 Tmp3 = Node->getOperand(2);
2930 if (Tmp1.getOpcode() == ISD::SETCC) {
2931 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
2933 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2935 Tmp1 = DAG.getSelectCC(dl, Tmp1,
2936 DAG.getConstant(0, Tmp1.getValueType()),
2937 Tmp2, Tmp3, ISD::SETNE);
2939 Results.push_back(Tmp1);
2942 SDValue Chain = Node->getOperand(0);
2943 SDValue Table = Node->getOperand(1);
2944 SDValue Index = Node->getOperand(2);
2946 EVT PTy = TLI.getPointerTy();
2948 const TargetData &TD = *TLI.getTargetData();
2949 unsigned EntrySize =
2950 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
2952 Index = DAG.getNode(ISD::MUL, dl, PTy,
2953 Index, DAG.getConstant(EntrySize, PTy));
2954 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2956 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
2957 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
2958 PseudoSourceValue::getJumpTable(), 0, MemVT,
2961 if (TM.getRelocationModel() == Reloc::PIC_) {
2962 // For PIC, the sequence is:
2963 // BRIND(load(Jumptable + index) + RelocBase)
2964 // RelocBase can be JumpTable, GOT or some sort of global base.
2965 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
2966 TLI.getPICJumpTableRelocBase(Table, DAG));
2968 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
2969 Results.push_back(Tmp1);
2973 // Expand brcond's setcc into its constituent parts and create a BR_CC
2975 Tmp1 = Node->getOperand(0);
2976 Tmp2 = Node->getOperand(1);
2977 if (Tmp2.getOpcode() == ISD::SETCC) {
2978 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
2979 Tmp1, Tmp2.getOperand(2),
2980 Tmp2.getOperand(0), Tmp2.getOperand(1),
2981 Node->getOperand(2));
2983 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
2984 DAG.getCondCode(ISD::SETNE), Tmp2,
2985 DAG.getConstant(0, Tmp2.getValueType()),
2986 Node->getOperand(2));
2988 Results.push_back(Tmp1);
2991 Tmp1 = Node->getOperand(0);
2992 Tmp2 = Node->getOperand(1);
2993 Tmp3 = Node->getOperand(2);
2994 LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl);
2996 // If we expanded the SETCC into an AND/OR, return the new node
2997 if (Tmp2.getNode() == 0) {
2998 Results.push_back(Tmp1);
3002 // Otherwise, SETCC for the given comparison type must be completely
3003 // illegal; expand it into a SELECT_CC.
3004 EVT VT = Node->getValueType(0);
3005 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3006 DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3);
3007 Results.push_back(Tmp1);
3010 case ISD::SELECT_CC: {
3011 Tmp1 = Node->getOperand(0); // LHS
3012 Tmp2 = Node->getOperand(1); // RHS
3013 Tmp3 = Node->getOperand(2); // True
3014 Tmp4 = Node->getOperand(3); // False
3015 SDValue CC = Node->getOperand(4);
3017 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()),
3018 Tmp1, Tmp2, CC, dl);
3020 assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!");
3021 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3022 CC = DAG.getCondCode(ISD::SETNE);
3023 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2,
3025 Results.push_back(Tmp1);
3029 Tmp1 = Node->getOperand(0); // Chain
3030 Tmp2 = Node->getOperand(2); // LHS
3031 Tmp3 = Node->getOperand(3); // RHS
3032 Tmp4 = Node->getOperand(1); // CC
3034 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()),
3035 Tmp2, Tmp3, Tmp4, dl);
3036 LastCALLSEQ_END = DAG.getEntryNode();
3038 assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!");
3039 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
3040 Tmp4 = DAG.getCondCode(ISD::SETNE);
3041 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2,
3042 Tmp3, Node->getOperand(4));
3043 Results.push_back(Tmp1);
3046 case ISD::GLOBAL_OFFSET_TABLE:
3047 case ISD::GlobalAddress:
3048 case ISD::GlobalTLSAddress:
3049 case ISD::ExternalSymbol:
3050 case ISD::ConstantPool:
3051 case ISD::JumpTable:
3052 case ISD::INTRINSIC_W_CHAIN:
3053 case ISD::INTRINSIC_WO_CHAIN:
3054 case ISD::INTRINSIC_VOID:
3055 // FIXME: Custom lowering for these operations shouldn't return null!
3056 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
3057 Results.push_back(SDValue(Node, i));
3061 void SelectionDAGLegalize::PromoteNode(SDNode *Node,
3062 SmallVectorImpl<SDValue> &Results) {
3063 EVT OVT = Node->getValueType(0);
3064 if (Node->getOpcode() == ISD::UINT_TO_FP ||
3065 Node->getOpcode() == ISD::SINT_TO_FP ||
3066 Node->getOpcode() == ISD::SETCC) {
3067 OVT = Node->getOperand(0).getValueType();
3069 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3070 DebugLoc dl = Node->getDebugLoc();
3071 SDValue Tmp1, Tmp2, Tmp3;
3072 switch (Node->getOpcode()) {
3076 // Zero extend the argument.
3077 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3078 // Perform the larger operation.
3079 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
3080 if (Node->getOpcode() == ISD::CTTZ) {
3081 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3082 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
3083 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
3085 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
3086 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3087 } else if (Node->getOpcode() == ISD::CTLZ) {
3088 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3089 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
3090 DAG.getConstant(NVT.getSizeInBits() -
3091 OVT.getSizeInBits(), NVT));
3093 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
3096 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3097 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3098 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
3099 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
3100 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3101 Results.push_back(Tmp1);
3104 case ISD::FP_TO_UINT:
3105 case ISD::FP_TO_SINT:
3106 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
3107 Node->getOpcode() == ISD::FP_TO_SINT, dl);
3108 Results.push_back(Tmp1);
3110 case ISD::UINT_TO_FP:
3111 case ISD::SINT_TO_FP:
3112 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
3113 Node->getOpcode() == ISD::SINT_TO_FP, dl);
3114 Results.push_back(Tmp1);
3119 unsigned ExtOp, TruncOp;
3120 if (OVT.isVector()) {
3121 ExtOp = ISD::BIT_CONVERT;
3122 TruncOp = ISD::BIT_CONVERT;
3124 assert(OVT.isInteger() && "Cannot promote logic operation");
3125 ExtOp = ISD::ANY_EXTEND;
3126 TruncOp = ISD::TRUNCATE;
3128 // Promote each of the values to the new type.
3129 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3130 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3131 // Perform the larger operation, then convert back
3132 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3133 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
3137 unsigned ExtOp, TruncOp;
3138 if (Node->getValueType(0).isVector()) {
3139 ExtOp = ISD::BIT_CONVERT;
3140 TruncOp = ISD::BIT_CONVERT;
3141 } else if (Node->getValueType(0).isInteger()) {
3142 ExtOp = ISD::ANY_EXTEND;
3143 TruncOp = ISD::TRUNCATE;
3145 ExtOp = ISD::FP_EXTEND;
3146 TruncOp = ISD::FP_ROUND;
3148 Tmp1 = Node->getOperand(0);
3149 // Promote each of the values to the new type.
3150 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3151 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
3152 // Perform the larger operation, then round down.
3153 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3);
3154 if (TruncOp != ISD::FP_ROUND)
3155 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
3157 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
3158 DAG.getIntPtrConstant(0));
3159 Results.push_back(Tmp1);
3162 case ISD::VECTOR_SHUFFLE: {
3163 SmallVector<int, 8> Mask;
3164 cast<ShuffleVectorSDNode>(Node)->getMask(Mask);
3166 // Cast the two input vectors.
3167 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
3168 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(1));
3170 // Convert the shuffle mask to the right # elements.
3171 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
3172 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Tmp1);
3173 Results.push_back(Tmp1);
3177 unsigned ExtOp = ISD::FP_EXTEND;
3178 if (NVT.isInteger()) {
3179 ISD::CondCode CCCode =
3180 cast<CondCodeSDNode>(Node->getOperand(2))->get();
3181 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3183 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3184 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3185 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3186 Tmp1, Tmp2, Node->getOperand(2)));
3192 // SelectionDAG::Legalize - This is the entry point for the file.
3194 void SelectionDAG::Legalize(CodeGenOpt::Level OptLevel) {
3195 /// run - This is the main entry point to this class.
3197 SelectionDAGLegalize(*this, OptLevel).LegalizeDAG();