1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/CodeGen/PseudoSourceValue.h"
20 #include "llvm/Target/TargetFrameInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/Target/TargetData.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/Target/TargetSubtarget.h"
26 #include "llvm/CallingConv.h"
27 #include "llvm/Constants.h"
28 #include "llvm/DerivedTypes.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Compiler.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/ADT/DenseMap.h"
33 #include "llvm/ADT/SmallVector.h"
34 #include "llvm/ADT/SmallPtrSet.h"
38 //===----------------------------------------------------------------------===//
39 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
40 /// hacks on it until the target machine can handle it. This involves
41 /// eliminating value sizes the machine cannot handle (promoting small sizes to
42 /// large sizes or splitting up large values into small values) as well as
43 /// eliminating operations the machine cannot handle.
45 /// This code also does a small amount of optimization and recognition of idioms
46 /// as part of its processing. For example, if a target does not support a
47 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
48 /// will attempt merge setcc and brc instructions into brcc's.
51 class VISIBILITY_HIDDEN SelectionDAGLegalize {
55 // Libcall insertion helpers.
57 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
58 /// legalized. We use this to ensure that calls are properly serialized
59 /// against each other, including inserted libcalls.
60 SDValue LastCALLSEQ_END;
62 /// IsLegalizingCall - This member is used *only* for purposes of providing
63 /// helpful assertions that a libcall isn't created while another call is
64 /// being legalized (which could lead to non-serialized call sequences).
65 bool IsLegalizingCall;
68 Legal, // The target natively supports this operation.
69 Promote, // This operation should be executed in a larger type.
70 Expand // Try to expand this to other ops, otherwise use a libcall.
73 /// ValueTypeActions - This is a bitvector that contains two bits for each
74 /// value type, where the two bits correspond to the LegalizeAction enum.
75 /// This can be queried with "getTypeAction(VT)".
76 TargetLowering::ValueTypeActionImpl ValueTypeActions;
78 /// LegalizedNodes - For nodes that are of legal width, and that have more
79 /// than one use, this map indicates what regularized operand to use. This
80 /// allows us to avoid legalizing the same thing more than once.
81 DenseMap<SDValue, SDValue> LegalizedNodes;
83 /// PromotedNodes - For nodes that are below legal width, and that have more
84 /// than one use, this map indicates what promoted value to use. This allows
85 /// us to avoid promoting the same thing more than once.
86 DenseMap<SDValue, SDValue> PromotedNodes;
88 /// ExpandedNodes - For nodes that need to be expanded this map indicates
89 /// which which operands are the expanded version of the input. This allows
90 /// us to avoid expanding the same node more than once.
91 DenseMap<SDValue, std::pair<SDValue, SDValue> > ExpandedNodes;
93 /// SplitNodes - For vector nodes that need to be split, this map indicates
94 /// which which operands are the split version of the input. This allows us
95 /// to avoid splitting the same node more than once.
96 std::map<SDValue, std::pair<SDValue, SDValue> > SplitNodes;
98 /// ScalarizedNodes - For nodes that need to be converted from vector types to
99 /// scalar types, this contains the mapping of ones we have already
100 /// processed to the result.
101 std::map<SDValue, SDValue> ScalarizedNodes;
103 void AddLegalizedOperand(SDValue From, SDValue To) {
104 LegalizedNodes.insert(std::make_pair(From, To));
105 // If someone requests legalization of the new node, return itself.
107 LegalizedNodes.insert(std::make_pair(To, To));
109 void AddPromotedOperand(SDValue From, SDValue To) {
110 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
111 assert(isNew && "Got into the map somehow?");
112 // If someone requests legalization of the new node, return itself.
113 LegalizedNodes.insert(std::make_pair(To, To));
117 explicit SelectionDAGLegalize(SelectionDAG &DAG);
119 /// getTypeAction - Return how we should legalize values of this type, either
120 /// it is already legal or we need to expand it into multiple registers of
121 /// smaller integer type, or we need to promote it to a larger type.
122 LegalizeAction getTypeAction(MVT VT) const {
123 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
126 /// isTypeLegal - Return true if this type is legal on this target.
128 bool isTypeLegal(MVT VT) const {
129 return getTypeAction(VT) == Legal;
135 /// HandleOp - Legalize, Promote, or Expand the specified operand as
136 /// appropriate for its type.
137 void HandleOp(SDValue Op);
139 /// LegalizeOp - We know that the specified value has a legal type.
140 /// Recursively ensure that the operands have legal types, then return the
142 SDValue LegalizeOp(SDValue O);
144 /// UnrollVectorOp - We know that the given vector has a legal type, however
145 /// the operation it performs is not legal and is an operation that we have
146 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
147 /// operating on each element individually.
148 SDValue UnrollVectorOp(SDValue O);
150 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
151 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
152 /// is necessary to spill the vector being inserted into to memory, perform
153 /// the insert there, and then read the result back.
154 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
157 /// PromoteOp - Given an operation that produces a value in an invalid type,
158 /// promote it to compute the value into a larger type. The produced value
159 /// will have the correct bits for the low portion of the register, but no
160 /// guarantee is made about the top bits: it may be zero, sign-extended, or
162 SDValue PromoteOp(SDValue O);
164 /// ExpandOp - Expand the specified SDValue into its two component pieces
165 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
166 /// the LegalizedNodes map is filled in for any results that are not expanded,
167 /// the ExpandedNodes map is filled in for any results that are expanded, and
168 /// the Lo/Hi values are returned. This applies to integer types and Vector
170 void ExpandOp(SDValue O, SDValue &Lo, SDValue &Hi);
172 /// SplitVectorOp - Given an operand of vector type, break it down into
173 /// two smaller values.
174 void SplitVectorOp(SDValue O, SDValue &Lo, SDValue &Hi);
176 /// ScalarizeVectorOp - Given an operand of single-element vector type
177 /// (e.g. v1f32), convert it into the equivalent operation that returns a
178 /// scalar (e.g. f32) value.
179 SDValue ScalarizeVectorOp(SDValue O);
181 /// isShuffleLegal - Return non-null if a vector shuffle is legal with the
182 /// specified mask and type. Targets can specify exactly which masks they
183 /// support and the code generator is tasked with not creating illegal masks.
185 /// Note that this will also return true for shuffles that are promoted to a
188 /// If this is a legal shuffle, this method returns the (possibly promoted)
189 /// build_vector Mask. If it's not a legal shuffle, it returns null.
190 SDNode *isShuffleLegal(MVT VT, SDValue Mask) const;
192 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
193 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
195 void LegalizeSetCCOperands(SDValue &LHS, SDValue &RHS, SDValue &CC);
197 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned,
199 SDValue ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source);
201 SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT);
202 SDValue ExpandBUILD_VECTOR(SDNode *Node);
203 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
204 SDValue LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op);
205 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT);
206 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, bool isSigned);
207 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned);
209 SDValue ExpandBSWAP(SDValue Op);
210 SDValue ExpandBitCount(unsigned Opc, SDValue Op);
211 bool ExpandShift(unsigned Opc, SDValue Op, SDValue Amt,
212 SDValue &Lo, SDValue &Hi);
213 void ExpandShiftParts(unsigned NodeOp, SDValue Op, SDValue Amt,
214 SDValue &Lo, SDValue &Hi);
216 SDValue ExpandEXTRACT_SUBVECTOR(SDValue Op);
217 SDValue ExpandEXTRACT_VECTOR_ELT(SDValue Op);
221 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
222 /// specified mask and type. Targets can specify exactly which masks they
223 /// support and the code generator is tasked with not creating illegal masks.
225 /// Note that this will also return true for shuffles that are promoted to a
227 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDValue Mask) const {
228 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
230 case TargetLowering::Legal:
231 case TargetLowering::Custom:
233 case TargetLowering::Promote: {
234 // If this is promoted to a different type, convert the shuffle mask and
235 // ask if it is legal in the promoted type!
236 MVT NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
237 MVT EltVT = NVT.getVectorElementType();
239 // If we changed # elements, change the shuffle mask.
240 unsigned NumEltsGrowth =
241 NVT.getVectorNumElements() / VT.getVectorNumElements();
242 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
243 if (NumEltsGrowth > 1) {
244 // Renumber the elements.
245 SmallVector<SDValue, 8> Ops;
246 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
247 SDValue InOp = Mask.getOperand(i);
248 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
249 if (InOp.getOpcode() == ISD::UNDEF)
250 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
252 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getZExtValue();
253 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, EltVT));
257 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
263 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.getNode() : 0;
266 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
267 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
268 ValueTypeActions(TLI.getValueTypeActions()) {
269 assert(MVT::LAST_VALUETYPE <= 32 &&
270 "Too many value types for ValueTypeActions to hold!");
273 void SelectionDAGLegalize::LegalizeDAG() {
274 LastCALLSEQ_END = DAG.getEntryNode();
275 IsLegalizingCall = false;
277 // The legalize process is inherently a bottom-up recursive process (users
278 // legalize their uses before themselves). Given infinite stack space, we
279 // could just start legalizing on the root and traverse the whole graph. In
280 // practice however, this causes us to run out of stack space on large basic
281 // blocks. To avoid this problem, compute an ordering of the nodes where each
282 // node is only legalized after all of its operands are legalized.
283 DAG.AssignTopologicalOrder();
284 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
285 E = prior(DAG.allnodes_end()); I != next(E); ++I)
286 HandleOp(SDValue(I, 0));
288 // Finally, it's possible the root changed. Get the new root.
289 SDValue OldRoot = DAG.getRoot();
290 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
291 DAG.setRoot(LegalizedNodes[OldRoot]);
293 ExpandedNodes.clear();
294 LegalizedNodes.clear();
295 PromotedNodes.clear();
297 ScalarizedNodes.clear();
299 // Remove dead nodes now.
300 DAG.RemoveDeadNodes();
304 /// FindCallEndFromCallStart - Given a chained node that is part of a call
305 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
306 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
307 if (Node->getOpcode() == ISD::CALLSEQ_END)
309 if (Node->use_empty())
310 return 0; // No CallSeqEnd
312 // The chain is usually at the end.
313 SDValue TheChain(Node, Node->getNumValues()-1);
314 if (TheChain.getValueType() != MVT::Other) {
315 // Sometimes it's at the beginning.
316 TheChain = SDValue(Node, 0);
317 if (TheChain.getValueType() != MVT::Other) {
318 // Otherwise, hunt for it.
319 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
320 if (Node->getValueType(i) == MVT::Other) {
321 TheChain = SDValue(Node, i);
325 // Otherwise, we walked into a node without a chain.
326 if (TheChain.getValueType() != MVT::Other)
331 for (SDNode::use_iterator UI = Node->use_begin(),
332 E = Node->use_end(); UI != E; ++UI) {
334 // Make sure to only follow users of our token chain.
336 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
337 if (User->getOperand(i) == TheChain)
338 if (SDNode *Result = FindCallEndFromCallStart(User))
344 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
345 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
346 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
347 assert(Node && "Didn't find callseq_start for a call??");
348 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
350 assert(Node->getOperand(0).getValueType() == MVT::Other &&
351 "Node doesn't have a token chain argument!");
352 return FindCallStartFromCallEnd(Node->getOperand(0).getNode());
355 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
356 /// see if any uses can reach Dest. If no dest operands can get to dest,
357 /// legalize them, legalize ourself, and return false, otherwise, return true.
359 /// Keep track of the nodes we fine that actually do lead to Dest in
360 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
362 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
363 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
364 if (N == Dest) return true; // N certainly leads to Dest :)
366 // If we've already processed this node and it does lead to Dest, there is no
367 // need to reprocess it.
368 if (NodesLeadingTo.count(N)) return true;
370 // If the first result of this node has been already legalized, then it cannot
372 switch (getTypeAction(N->getValueType(0))) {
374 if (LegalizedNodes.count(SDValue(N, 0))) return false;
377 if (PromotedNodes.count(SDValue(N, 0))) return false;
380 if (ExpandedNodes.count(SDValue(N, 0))) return false;
384 // Okay, this node has not already been legalized. Check and legalize all
385 // operands. If none lead to Dest, then we can legalize this node.
386 bool OperandsLeadToDest = false;
387 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
388 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
389 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo);
391 if (OperandsLeadToDest) {
392 NodesLeadingTo.insert(N);
396 // Okay, this node looks safe, legalize it and return false.
397 HandleOp(SDValue(N, 0));
401 /// HandleOp - Legalize, Promote, or Expand the specified operand as
402 /// appropriate for its type.
403 void SelectionDAGLegalize::HandleOp(SDValue Op) {
404 MVT VT = Op.getValueType();
405 switch (getTypeAction(VT)) {
406 default: assert(0 && "Bad type action!");
407 case Legal: (void)LegalizeOp(Op); break;
408 case Promote: (void)PromoteOp(Op); break;
410 if (!VT.isVector()) {
411 // If this is an illegal scalar, expand it into its two component
414 if (Op.getOpcode() == ISD::TargetConstant)
415 break; // Allow illegal target nodes.
417 } else if (VT.getVectorNumElements() == 1) {
418 // If this is an illegal single element vector, convert it to a
420 (void)ScalarizeVectorOp(Op);
422 // Otherwise, this is an illegal multiple element vector.
423 // Split it in half and legalize both parts.
425 SplitVectorOp(Op, X, Y);
431 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
432 /// a load from the constant pool.
433 static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
434 SelectionDAG &DAG, TargetLowering &TLI) {
437 // If a FP immediate is precise when represented as a float and if the
438 // target can do an extending load from float to double, we put it into
439 // the constant pool as a float, even if it's is statically typed as a
440 // double. This shrinks FP constants and canonicalizes them for targets where
441 // an FP extending load is the same cost as a normal load (such as on the x87
442 // fp stack or PPC FP unit).
443 MVT VT = CFP->getValueType(0);
444 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
446 if (VT!=MVT::f64 && VT!=MVT::f32)
447 assert(0 && "Invalid type expansion");
448 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
449 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
454 while (SVT != MVT::f32) {
455 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1);
456 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
457 // Only do this if the target has a native EXTLOAD instruction from
459 TLI.isLoadXLegal(ISD::EXTLOAD, SVT) &&
460 TLI.ShouldShrinkFPConstant(OrigVT)) {
461 const Type *SType = SVT.getTypeForMVT();
462 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
468 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
469 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
471 return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, DAG.getEntryNode(),
472 CPIdx, PseudoSourceValue::getConstantPool(),
473 0, VT, false, Alignment);
474 return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx,
475 PseudoSourceValue::getConstantPool(), 0, false, Alignment);
479 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
482 SDValue ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT,
483 SelectionDAG &DAG, TargetLowering &TLI) {
484 MVT VT = Node->getValueType(0);
485 MVT SrcVT = Node->getOperand(1).getValueType();
486 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
487 "fcopysign expansion only supported for f32 and f64");
488 MVT SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
490 // First get the sign bit of second operand.
491 SDValue Mask1 = (SrcVT == MVT::f64)
492 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
493 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
494 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
495 SDValue SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
496 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
497 // Shift right or sign-extend it if the two operands have different types.
498 int SizeDiff = SrcNVT.getSizeInBits() - NVT.getSizeInBits();
500 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
501 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
502 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
503 } else if (SizeDiff < 0) {
504 SignBit = DAG.getNode(ISD::ZERO_EXTEND, NVT, SignBit);
505 SignBit = DAG.getNode(ISD::SHL, NVT, SignBit,
506 DAG.getConstant(-SizeDiff, TLI.getShiftAmountTy()));
509 // Clear the sign bit of first operand.
510 SDValue Mask2 = (VT == MVT::f64)
511 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
512 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
513 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
514 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
515 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
517 // Or the value with the sign bit.
518 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
522 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
524 SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
525 TargetLowering &TLI) {
526 SDValue Chain = ST->getChain();
527 SDValue Ptr = ST->getBasePtr();
528 SDValue Val = ST->getValue();
529 MVT VT = Val.getValueType();
530 int Alignment = ST->getAlignment();
531 int SVOffset = ST->getSrcValueOffset();
532 if (ST->getMemoryVT().isFloatingPoint() ||
533 ST->getMemoryVT().isVector()) {
534 // Expand to a bitconvert of the value to the integer type of the
535 // same size, then a (misaligned) int store.
537 if (VT.is128BitVector() || VT == MVT::ppcf128 || VT == MVT::f128)
539 else if (VT.is64BitVector() || VT==MVT::f64)
541 else if (VT==MVT::f32)
544 assert(0 && "Unaligned store of unsupported type");
546 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val);
547 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(),
548 SVOffset, ST->isVolatile(), Alignment);
550 assert(ST->getMemoryVT().isInteger() &&
551 !ST->getMemoryVT().isVector() &&
552 "Unaligned store of unknown type.");
553 // Get the half-size VT
555 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1);
556 int NumBits = NewStoredVT.getSizeInBits();
557 int IncrementSize = NumBits / 8;
559 // Divide the stored value in two parts.
560 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
562 SDValue Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
564 // Store the two parts
565 SDValue Store1, Store2;
566 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr,
567 ST->getSrcValue(), SVOffset, NewStoredVT,
568 ST->isVolatile(), Alignment);
569 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
570 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
571 Alignment = MinAlign(Alignment, IncrementSize);
572 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr,
573 ST->getSrcValue(), SVOffset + IncrementSize,
574 NewStoredVT, ST->isVolatile(), Alignment);
576 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2);
579 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
581 SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
582 TargetLowering &TLI) {
583 int SVOffset = LD->getSrcValueOffset();
584 SDValue Chain = LD->getChain();
585 SDValue Ptr = LD->getBasePtr();
586 MVT VT = LD->getValueType(0);
587 MVT LoadedVT = LD->getMemoryVT();
588 if (VT.isFloatingPoint() || VT.isVector()) {
589 // Expand to a (misaligned) integer load of the same size,
590 // then bitconvert to floating point or vector.
592 if (LoadedVT.is128BitVector() ||
593 LoadedVT == MVT::ppcf128 || LoadedVT == MVT::f128)
595 else if (LoadedVT.is64BitVector() || LoadedVT == MVT::f64)
597 else if (LoadedVT == MVT::f32)
600 assert(0 && "Unaligned load of unsupported type");
602 SDValue newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(),
603 SVOffset, LD->isVolatile(),
605 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad);
606 if (VT.isFloatingPoint() && LoadedVT != VT)
607 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result);
609 SDValue Ops[] = { Result, Chain };
610 return DAG.getMergeValues(Ops, 2);
612 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
613 "Unaligned load of unsupported type.");
615 // Compute the new VT that is half the size of the old one. This is an
617 unsigned NumBits = LoadedVT.getSizeInBits();
619 NewLoadedVT = MVT::getIntegerVT(NumBits/2);
622 unsigned Alignment = LD->getAlignment();
623 unsigned IncrementSize = NumBits / 8;
624 ISD::LoadExtType HiExtType = LD->getExtensionType();
626 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
627 if (HiExtType == ISD::NON_EXTLOAD)
628 HiExtType = ISD::ZEXTLOAD;
630 // Load the value in two parts
632 if (TLI.isLittleEndian()) {
633 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
634 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
635 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
636 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
637 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(),
638 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
639 MinAlign(Alignment, IncrementSize));
641 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset,
642 NewLoadedVT,LD->isVolatile(), Alignment);
643 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
644 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
645 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
646 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
647 MinAlign(Alignment, IncrementSize));
650 // aggregate the two parts
651 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
652 SDValue Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
653 Result = DAG.getNode(ISD::OR, VT, Result, Lo);
655 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
658 SDValue Ops[] = { Result, TF };
659 return DAG.getMergeValues(Ops, 2);
662 /// UnrollVectorOp - We know that the given vector has a legal type, however
663 /// the operation it performs is not legal and is an operation that we have
664 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
665 /// operating on each element individually.
666 SDValue SelectionDAGLegalize::UnrollVectorOp(SDValue Op) {
667 MVT VT = Op.getValueType();
668 assert(isTypeLegal(VT) &&
669 "Caller should expand or promote operands that are not legal!");
670 assert(Op.getNode()->getNumValues() == 1 &&
671 "Can't unroll a vector with multiple results!");
672 unsigned NE = VT.getVectorNumElements();
673 MVT EltVT = VT.getVectorElementType();
675 SmallVector<SDValue, 8> Scalars;
676 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
677 for (unsigned i = 0; i != NE; ++i) {
678 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
679 SDValue Operand = Op.getOperand(j);
680 MVT OperandVT = Operand.getValueType();
681 if (OperandVT.isVector()) {
682 // A vector operand; extract a single element.
683 MVT OperandEltVT = OperandVT.getVectorElementType();
684 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
687 DAG.getConstant(i, MVT::i32));
689 // A scalar operand; just use it as is.
690 Operands[j] = Operand;
693 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT,
694 &Operands[0], Operands.size()));
697 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size());
700 /// GetFPLibCall - Return the right libcall for the given floating point type.
701 static RTLIB::Libcall GetFPLibCall(MVT VT,
702 RTLIB::Libcall Call_F32,
703 RTLIB::Libcall Call_F64,
704 RTLIB::Libcall Call_F80,
705 RTLIB::Libcall Call_PPCF128) {
707 VT == MVT::f32 ? Call_F32 :
708 VT == MVT::f64 ? Call_F64 :
709 VT == MVT::f80 ? Call_F80 :
710 VT == MVT::ppcf128 ? Call_PPCF128 :
711 RTLIB::UNKNOWN_LIBCALL;
714 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
715 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
716 /// is necessary to spill the vector being inserted into to memory, perform
717 /// the insert there, and then read the result back.
718 SDValue SelectionDAGLegalize::
719 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx) {
724 // If the target doesn't support this, we have to spill the input vector
725 // to a temporary stack slot, update the element, then reload it. This is
726 // badness. We could also load the value into a vector register (either
727 // with a "move to register" or "extload into register" instruction, then
728 // permute it into place, if the idx is a constant and if the idx is
729 // supported by the target.
730 MVT VT = Tmp1.getValueType();
731 MVT EltVT = VT.getVectorElementType();
732 MVT IdxVT = Tmp3.getValueType();
733 MVT PtrVT = TLI.getPointerTy();
734 SDValue StackPtr = DAG.CreateStackTemporary(VT);
736 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
739 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr,
740 PseudoSourceValue::getFixedStack(SPFI), 0);
742 // Truncate or zero extend offset to target pointer type.
743 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
744 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
745 // Add the offset to the index.
746 unsigned EltSize = EltVT.getSizeInBits()/8;
747 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
748 SDValue StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
749 // Store the scalar value.
750 Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2,
751 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT);
752 // Load the updated vector.
753 return DAG.getLoad(VT, Ch, StackPtr,
754 PseudoSourceValue::getFixedStack(SPFI), 0);
757 /// LegalizeOp - We know that the specified value has a legal type, and
758 /// that its operands are legal. Now ensure that the operation itself
759 /// is legal, recursively ensuring that the operands' operations remain
761 SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
762 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
765 assert(isTypeLegal(Op.getValueType()) &&
766 "Caller should expand or promote operands that are not legal!");
767 SDNode *Node = Op.getNode();
769 // If this operation defines any values that cannot be represented in a
770 // register on this target, make sure to expand or promote them.
771 if (Node->getNumValues() > 1) {
772 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
773 if (getTypeAction(Node->getValueType(i)) != Legal) {
774 HandleOp(Op.getValue(i));
775 assert(LegalizedNodes.count(Op) &&
776 "Handling didn't add legal operands!");
777 return LegalizedNodes[Op];
781 // Note that LegalizeOp may be reentered even from single-use nodes, which
782 // means that we always must cache transformed nodes.
783 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
784 if (I != LegalizedNodes.end()) return I->second;
786 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
788 bool isCustom = false;
790 switch (Node->getOpcode()) {
791 case ISD::FrameIndex:
792 case ISD::EntryToken:
794 case ISD::BasicBlock:
795 case ISD::TargetFrameIndex:
796 case ISD::TargetJumpTable:
797 case ISD::TargetConstant:
798 case ISD::TargetConstantFP:
799 case ISD::TargetConstantPool:
800 case ISD::TargetGlobalAddress:
801 case ISD::TargetGlobalTLSAddress:
802 case ISD::TargetExternalSymbol:
805 case ISD::MEMOPERAND:
808 // Primitives must all be legal.
809 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
810 "This must be legal!");
813 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
814 // If this is a target node, legalize it by legalizing the operands then
815 // passing it through.
816 SmallVector<SDValue, 8> Ops;
817 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
818 Ops.push_back(LegalizeOp(Node->getOperand(i)));
820 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
822 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
823 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
824 return Result.getValue(Op.getResNo());
826 // Otherwise this is an unhandled builtin node. splat.
828 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
830 assert(0 && "Do not know how to legalize this operator!");
832 case ISD::GLOBAL_OFFSET_TABLE:
833 case ISD::GlobalAddress:
834 case ISD::GlobalTLSAddress:
835 case ISD::ExternalSymbol:
836 case ISD::ConstantPool:
837 case ISD::JumpTable: // Nothing to do.
838 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
839 default: assert(0 && "This action is not supported yet!");
840 case TargetLowering::Custom:
841 Tmp1 = TLI.LowerOperation(Op, DAG);
842 if (Tmp1.getNode()) Result = Tmp1;
843 // FALLTHROUGH if the target doesn't want to lower this op after all.
844 case TargetLowering::Legal:
849 case ISD::RETURNADDR:
850 // The only option for these nodes is to custom lower them. If the target
851 // does not custom lower them, then return zero.
852 Tmp1 = TLI.LowerOperation(Op, DAG);
856 Result = DAG.getConstant(0, TLI.getPointerTy());
858 case ISD::FRAME_TO_ARGS_OFFSET: {
859 MVT VT = Node->getValueType(0);
860 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
861 default: assert(0 && "This action is not supported yet!");
862 case TargetLowering::Custom:
863 Result = TLI.LowerOperation(Op, DAG);
864 if (Result.getNode()) break;
866 case TargetLowering::Legal:
867 Result = DAG.getConstant(0, VT);
872 case ISD::EXCEPTIONADDR: {
873 Tmp1 = LegalizeOp(Node->getOperand(0));
874 MVT VT = Node->getValueType(0);
875 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
876 default: assert(0 && "This action is not supported yet!");
877 case TargetLowering::Expand: {
878 unsigned Reg = TLI.getExceptionAddressRegister();
879 Result = DAG.getCopyFromReg(Tmp1, Reg, VT);
882 case TargetLowering::Custom:
883 Result = TLI.LowerOperation(Op, DAG);
884 if (Result.getNode()) break;
886 case TargetLowering::Legal: {
887 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp1 };
888 Result = DAG.getMergeValues(Ops, 2);
893 if (Result.getNode()->getNumValues() == 1) break;
895 assert(Result.getNode()->getNumValues() == 2 &&
896 "Cannot return more than two values!");
898 // Since we produced two values, make sure to remember that we
899 // legalized both of them.
900 Tmp1 = LegalizeOp(Result);
901 Tmp2 = LegalizeOp(Result.getValue(1));
902 AddLegalizedOperand(Op.getValue(0), Tmp1);
903 AddLegalizedOperand(Op.getValue(1), Tmp2);
904 return Op.getResNo() ? Tmp2 : Tmp1;
905 case ISD::EHSELECTION: {
906 Tmp1 = LegalizeOp(Node->getOperand(0));
907 Tmp2 = LegalizeOp(Node->getOperand(1));
908 MVT VT = Node->getValueType(0);
909 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
910 default: assert(0 && "This action is not supported yet!");
911 case TargetLowering::Expand: {
912 unsigned Reg = TLI.getExceptionSelectorRegister();
913 Result = DAG.getCopyFromReg(Tmp2, Reg, VT);
916 case TargetLowering::Custom:
917 Result = TLI.LowerOperation(Op, DAG);
918 if (Result.getNode()) break;
920 case TargetLowering::Legal: {
921 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp2 };
922 Result = DAG.getMergeValues(Ops, 2);
927 if (Result.getNode()->getNumValues() == 1) break;
929 assert(Result.getNode()->getNumValues() == 2 &&
930 "Cannot return more than two values!");
932 // Since we produced two values, make sure to remember that we
933 // legalized both of them.
934 Tmp1 = LegalizeOp(Result);
935 Tmp2 = LegalizeOp(Result.getValue(1));
936 AddLegalizedOperand(Op.getValue(0), Tmp1);
937 AddLegalizedOperand(Op.getValue(1), Tmp2);
938 return Op.getResNo() ? Tmp2 : Tmp1;
939 case ISD::EH_RETURN: {
940 MVT VT = Node->getValueType(0);
941 // The only "good" option for this node is to custom lower it.
942 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
943 default: assert(0 && "This action is not supported at all!");
944 case TargetLowering::Custom:
945 Result = TLI.LowerOperation(Op, DAG);
946 if (Result.getNode()) break;
948 case TargetLowering::Legal:
949 // Target does not know, how to lower this, lower to noop
950 Result = LegalizeOp(Node->getOperand(0));
955 case ISD::AssertSext:
956 case ISD::AssertZext:
957 Tmp1 = LegalizeOp(Node->getOperand(0));
958 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
960 case ISD::MERGE_VALUES:
961 // Legalize eliminates MERGE_VALUES nodes.
962 Result = Node->getOperand(Op.getResNo());
964 case ISD::CopyFromReg:
965 Tmp1 = LegalizeOp(Node->getOperand(0));
966 Result = Op.getValue(0);
967 if (Node->getNumValues() == 2) {
968 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
970 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
971 if (Node->getNumOperands() == 3) {
972 Tmp2 = LegalizeOp(Node->getOperand(2));
973 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
975 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
977 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
979 // Since CopyFromReg produces two values, make sure to remember that we
980 // legalized both of them.
981 AddLegalizedOperand(Op.getValue(0), Result);
982 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
983 return Result.getValue(Op.getResNo());
985 MVT VT = Op.getValueType();
986 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
987 default: assert(0 && "This action is not supported yet!");
988 case TargetLowering::Expand:
990 Result = DAG.getConstant(0, VT);
991 else if (VT.isFloatingPoint())
992 Result = DAG.getConstantFP(APFloat(APInt(VT.getSizeInBits(), 0)),
995 assert(0 && "Unknown value type!");
997 case TargetLowering::Legal:
1003 case ISD::INTRINSIC_W_CHAIN:
1004 case ISD::INTRINSIC_WO_CHAIN:
1005 case ISD::INTRINSIC_VOID: {
1006 SmallVector<SDValue, 8> Ops;
1007 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1008 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1009 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1011 // Allow the target to custom lower its intrinsics if it wants to.
1012 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
1013 TargetLowering::Custom) {
1014 Tmp3 = TLI.LowerOperation(Result, DAG);
1015 if (Tmp3.getNode()) Result = Tmp3;
1018 if (Result.getNode()->getNumValues() == 1) break;
1020 // Must have return value and chain result.
1021 assert(Result.getNode()->getNumValues() == 2 &&
1022 "Cannot return more than two values!");
1024 // Since loads produce two values, make sure to remember that we
1025 // legalized both of them.
1026 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1027 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1028 return Result.getValue(Op.getResNo());
1031 case ISD::DBG_STOPPOINT:
1032 assert(Node->getNumOperands() == 1 && "Invalid DBG_STOPPOINT node!");
1033 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
1035 switch (TLI.getOperationAction(ISD::DBG_STOPPOINT, MVT::Other)) {
1036 case TargetLowering::Promote:
1037 default: assert(0 && "This action is not supported yet!");
1038 case TargetLowering::Expand: {
1039 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
1040 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
1041 bool useLABEL = TLI.isOperationLegal(ISD::DBG_LABEL, MVT::Other);
1043 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node);
1044 if (MMI && (useDEBUG_LOC || useLABEL)) {
1045 const CompileUnitDesc *CompileUnit = DSP->getCompileUnit();
1046 unsigned SrcFile = MMI->RecordSource(CompileUnit);
1048 unsigned Line = DSP->getLine();
1049 unsigned Col = DSP->getColumn();
1052 SDValue Ops[] = { Tmp1, DAG.getConstant(Line, MVT::i32),
1053 DAG.getConstant(Col, MVT::i32),
1054 DAG.getConstant(SrcFile, MVT::i32) };
1055 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops, 4);
1057 unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile);
1058 Result = DAG.getLabel(ISD::DBG_LABEL, Tmp1, ID);
1061 Result = Tmp1; // chain
1065 case TargetLowering::Legal: {
1066 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1067 if (Action == Legal && Tmp1 == Node->getOperand(0))
1070 SmallVector<SDValue, 8> Ops;
1071 Ops.push_back(Tmp1);
1072 if (Action == Legal) {
1073 Ops.push_back(Node->getOperand(1)); // line # must be legal.
1074 Ops.push_back(Node->getOperand(2)); // col # must be legal.
1076 // Otherwise promote them.
1077 Ops.push_back(PromoteOp(Node->getOperand(1)));
1078 Ops.push_back(PromoteOp(Node->getOperand(2)));
1080 Ops.push_back(Node->getOperand(3)); // filename must be legal.
1081 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
1082 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1089 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!");
1090 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) {
1091 default: assert(0 && "This action is not supported yet!");
1092 case TargetLowering::Legal:
1093 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1094 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1095 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable.
1096 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1098 case TargetLowering::Expand:
1099 Result = LegalizeOp(Node->getOperand(0));
1104 case ISD::DEBUG_LOC:
1105 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
1106 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
1107 default: assert(0 && "This action is not supported yet!");
1108 case TargetLowering::Legal: {
1109 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1110 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1111 if (Action == Legal && Tmp1 == Node->getOperand(0))
1113 if (Action == Legal) {
1114 Tmp2 = Node->getOperand(1);
1115 Tmp3 = Node->getOperand(2);
1116 Tmp4 = Node->getOperand(3);
1118 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1119 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1120 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1122 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1128 case ISD::DBG_LABEL:
1130 assert(Node->getNumOperands() == 1 && "Invalid LABEL node!");
1131 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
1132 default: assert(0 && "This action is not supported yet!");
1133 case TargetLowering::Legal:
1134 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1135 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1137 case TargetLowering::Expand:
1138 Result = LegalizeOp(Node->getOperand(0));
1144 assert(Node->getNumOperands() == 4 && "Invalid Prefetch node!");
1145 switch (TLI.getOperationAction(ISD::PREFETCH, MVT::Other)) {
1146 default: assert(0 && "This action is not supported yet!");
1147 case TargetLowering::Legal:
1148 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1149 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1150 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the rw specifier.
1151 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize locality specifier.
1152 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1154 case TargetLowering::Expand:
1156 Result = LegalizeOp(Node->getOperand(0));
1161 case ISD::MEMBARRIER: {
1162 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!");
1163 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) {
1164 default: assert(0 && "This action is not supported yet!");
1165 case TargetLowering::Legal: {
1167 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1168 for (int x = 1; x < 6; ++x) {
1169 Ops[x] = Node->getOperand(x);
1170 if (!isTypeLegal(Ops[x].getValueType()))
1171 Ops[x] = PromoteOp(Ops[x]);
1173 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6);
1176 case TargetLowering::Expand:
1177 //There is no libgcc call for this op
1178 Result = Node->getOperand(0); // Noop
1184 case ISD::ATOMIC_CMP_SWAP_8:
1185 case ISD::ATOMIC_CMP_SWAP_16:
1186 case ISD::ATOMIC_CMP_SWAP_32:
1187 case ISD::ATOMIC_CMP_SWAP_64: {
1188 unsigned int num_operands = 4;
1189 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1191 for (unsigned int x = 0; x < num_operands; ++x)
1192 Ops[x] = LegalizeOp(Node->getOperand(x));
1193 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1195 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1196 default: assert(0 && "This action is not supported yet!");
1197 case TargetLowering::Custom:
1198 Result = TLI.LowerOperation(Result, DAG);
1200 case TargetLowering::Legal:
1203 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1204 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1205 return Result.getValue(Op.getResNo());
1207 case ISD::ATOMIC_LOAD_ADD_8:
1208 case ISD::ATOMIC_LOAD_SUB_8:
1209 case ISD::ATOMIC_LOAD_AND_8:
1210 case ISD::ATOMIC_LOAD_OR_8:
1211 case ISD::ATOMIC_LOAD_XOR_8:
1212 case ISD::ATOMIC_LOAD_NAND_8:
1213 case ISD::ATOMIC_LOAD_MIN_8:
1214 case ISD::ATOMIC_LOAD_MAX_8:
1215 case ISD::ATOMIC_LOAD_UMIN_8:
1216 case ISD::ATOMIC_LOAD_UMAX_8:
1217 case ISD::ATOMIC_SWAP_8:
1218 case ISD::ATOMIC_LOAD_ADD_16:
1219 case ISD::ATOMIC_LOAD_SUB_16:
1220 case ISD::ATOMIC_LOAD_AND_16:
1221 case ISD::ATOMIC_LOAD_OR_16:
1222 case ISD::ATOMIC_LOAD_XOR_16:
1223 case ISD::ATOMIC_LOAD_NAND_16:
1224 case ISD::ATOMIC_LOAD_MIN_16:
1225 case ISD::ATOMIC_LOAD_MAX_16:
1226 case ISD::ATOMIC_LOAD_UMIN_16:
1227 case ISD::ATOMIC_LOAD_UMAX_16:
1228 case ISD::ATOMIC_SWAP_16:
1229 case ISD::ATOMIC_LOAD_ADD_32:
1230 case ISD::ATOMIC_LOAD_SUB_32:
1231 case ISD::ATOMIC_LOAD_AND_32:
1232 case ISD::ATOMIC_LOAD_OR_32:
1233 case ISD::ATOMIC_LOAD_XOR_32:
1234 case ISD::ATOMIC_LOAD_NAND_32:
1235 case ISD::ATOMIC_LOAD_MIN_32:
1236 case ISD::ATOMIC_LOAD_MAX_32:
1237 case ISD::ATOMIC_LOAD_UMIN_32:
1238 case ISD::ATOMIC_LOAD_UMAX_32:
1239 case ISD::ATOMIC_SWAP_32:
1240 case ISD::ATOMIC_LOAD_ADD_64:
1241 case ISD::ATOMIC_LOAD_SUB_64:
1242 case ISD::ATOMIC_LOAD_AND_64:
1243 case ISD::ATOMIC_LOAD_OR_64:
1244 case ISD::ATOMIC_LOAD_XOR_64:
1245 case ISD::ATOMIC_LOAD_NAND_64:
1246 case ISD::ATOMIC_LOAD_MIN_64:
1247 case ISD::ATOMIC_LOAD_MAX_64:
1248 case ISD::ATOMIC_LOAD_UMIN_64:
1249 case ISD::ATOMIC_LOAD_UMAX_64:
1250 case ISD::ATOMIC_SWAP_64: {
1251 unsigned int num_operands = 3;
1252 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1254 for (unsigned int x = 0; x < num_operands; ++x)
1255 Ops[x] = LegalizeOp(Node->getOperand(x));
1256 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1258 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1259 default: assert(0 && "This action is not supported yet!");
1260 case TargetLowering::Custom:
1261 Result = TLI.LowerOperation(Result, DAG);
1263 case TargetLowering::Legal:
1266 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1267 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1268 return Result.getValue(Op.getResNo());
1270 case ISD::Constant: {
1271 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1273 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1275 // We know we don't need to expand constants here, constants only have one
1276 // value and we check that it is fine above.
1278 if (opAction == TargetLowering::Custom) {
1279 Tmp1 = TLI.LowerOperation(Result, DAG);
1285 case ISD::ConstantFP: {
1286 // Spill FP immediates to the constant pool if the target cannot directly
1287 // codegen them. Targets often have some immediate values that can be
1288 // efficiently generated into an FP register without a load. We explicitly
1289 // leave these constants as ConstantFP nodes for the target to deal with.
1290 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1292 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1293 default: assert(0 && "This action is not supported yet!");
1294 case TargetLowering::Legal:
1296 case TargetLowering::Custom:
1297 Tmp3 = TLI.LowerOperation(Result, DAG);
1298 if (Tmp3.getNode()) {
1303 case TargetLowering::Expand: {
1304 // Check to see if this FP immediate is already legal.
1305 bool isLegal = false;
1306 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1307 E = TLI.legal_fpimm_end(); I != E; ++I) {
1308 if (CFP->isExactlyValue(*I)) {
1313 // If this is a legal constant, turn it into a TargetConstantFP node.
1316 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1321 case ISD::TokenFactor:
1322 if (Node->getNumOperands() == 2) {
1323 Tmp1 = LegalizeOp(Node->getOperand(0));
1324 Tmp2 = LegalizeOp(Node->getOperand(1));
1325 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1326 } else if (Node->getNumOperands() == 3) {
1327 Tmp1 = LegalizeOp(Node->getOperand(0));
1328 Tmp2 = LegalizeOp(Node->getOperand(1));
1329 Tmp3 = LegalizeOp(Node->getOperand(2));
1330 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1332 SmallVector<SDValue, 8> Ops;
1333 // Legalize the operands.
1334 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1335 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1336 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1340 case ISD::FORMAL_ARGUMENTS:
1342 // The only option for this is to custom lower it.
1343 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1344 assert(Tmp3.getNode() && "Target didn't custom lower this node!");
1345 // A call within a calling sequence must be legalized to something
1346 // other than the normal CALLSEQ_END. Violating this gets Legalize
1347 // into an infinite loop.
1348 assert ((!IsLegalizingCall ||
1349 Node->getOpcode() != ISD::CALL ||
1350 Tmp3.getNode()->getOpcode() != ISD::CALLSEQ_END) &&
1351 "Nested CALLSEQ_START..CALLSEQ_END not supported.");
1353 // The number of incoming and outgoing values should match; unless the final
1354 // outgoing value is a flag.
1355 assert((Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() ||
1356 (Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() + 1 &&
1357 Tmp3.getNode()->getValueType(Tmp3.getNode()->getNumValues() - 1) ==
1359 "Lowering call/formal_arguments produced unexpected # results!");
1361 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1362 // remember that we legalized all of them, so it doesn't get relegalized.
1363 for (unsigned i = 0, e = Tmp3.getNode()->getNumValues(); i != e; ++i) {
1364 if (Tmp3.getNode()->getValueType(i) == MVT::Flag)
1366 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1367 if (Op.getResNo() == i)
1369 AddLegalizedOperand(SDValue(Node, i), Tmp1);
1372 case ISD::EXTRACT_SUBREG: {
1373 Tmp1 = LegalizeOp(Node->getOperand(0));
1374 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1375 assert(idx && "Operand must be a constant");
1376 Tmp2 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0));
1377 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1380 case ISD::INSERT_SUBREG: {
1381 Tmp1 = LegalizeOp(Node->getOperand(0));
1382 Tmp2 = LegalizeOp(Node->getOperand(1));
1383 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1384 assert(idx && "Operand must be a constant");
1385 Tmp3 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0));
1386 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1389 case ISD::BUILD_VECTOR:
1390 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1391 default: assert(0 && "This action is not supported yet!");
1392 case TargetLowering::Custom:
1393 Tmp3 = TLI.LowerOperation(Result, DAG);
1394 if (Tmp3.getNode()) {
1399 case TargetLowering::Expand:
1400 Result = ExpandBUILD_VECTOR(Result.getNode());
1404 case ISD::INSERT_VECTOR_ELT:
1405 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1406 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1408 // The type of the value to insert may not be legal, even though the vector
1409 // type is legal. Legalize/Promote accordingly. We do not handle Expand
1411 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1412 default: assert(0 && "Cannot expand insert element operand");
1413 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
1414 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
1416 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1418 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1419 Node->getValueType(0))) {
1420 default: assert(0 && "This action is not supported yet!");
1421 case TargetLowering::Legal:
1423 case TargetLowering::Custom:
1424 Tmp4 = TLI.LowerOperation(Result, DAG);
1425 if (Tmp4.getNode()) {
1430 case TargetLowering::Expand: {
1431 // If the insert index is a constant, codegen this as a scalar_to_vector,
1432 // then a shuffle that inserts it into the right position in the vector.
1433 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1434 // SCALAR_TO_VECTOR requires that the type of the value being inserted
1435 // match the element type of the vector being created.
1436 if (Tmp2.getValueType() ==
1437 Op.getValueType().getVectorElementType()) {
1438 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
1439 Tmp1.getValueType(), Tmp2);
1441 unsigned NumElts = Tmp1.getValueType().getVectorNumElements();
1443 MVT::getIntVectorWithNumElements(NumElts);
1444 MVT ShufMaskEltVT = ShufMaskVT.getVectorElementType();
1446 // We generate a shuffle of InVec and ScVec, so the shuffle mask
1447 // should be 0,1,2,3,4,5... with the appropriate element replaced with
1448 // elt 0 of the RHS.
1449 SmallVector<SDValue, 8> ShufOps;
1450 for (unsigned i = 0; i != NumElts; ++i) {
1451 if (i != InsertPos->getZExtValue())
1452 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1454 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1456 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1457 &ShufOps[0], ShufOps.size());
1459 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1460 Tmp1, ScVec, ShufMask);
1461 Result = LegalizeOp(Result);
1465 Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3);
1470 case ISD::SCALAR_TO_VECTOR:
1471 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1472 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1476 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1477 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1478 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1479 Node->getValueType(0))) {
1480 default: assert(0 && "This action is not supported yet!");
1481 case TargetLowering::Legal:
1483 case TargetLowering::Custom:
1484 Tmp3 = TLI.LowerOperation(Result, DAG);
1485 if (Tmp3.getNode()) {
1490 case TargetLowering::Expand:
1491 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1495 case ISD::VECTOR_SHUFFLE:
1496 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1497 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1498 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1500 // Allow targets to custom lower the SHUFFLEs they support.
1501 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1502 default: assert(0 && "Unknown operation action!");
1503 case TargetLowering::Legal:
1504 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1505 "vector shuffle should not be created if not legal!");
1507 case TargetLowering::Custom:
1508 Tmp3 = TLI.LowerOperation(Result, DAG);
1509 if (Tmp3.getNode()) {
1514 case TargetLowering::Expand: {
1515 MVT VT = Node->getValueType(0);
1516 MVT EltVT = VT.getVectorElementType();
1517 MVT PtrVT = TLI.getPointerTy();
1518 SDValue Mask = Node->getOperand(2);
1519 unsigned NumElems = Mask.getNumOperands();
1520 SmallVector<SDValue,8> Ops;
1521 for (unsigned i = 0; i != NumElems; ++i) {
1522 SDValue Arg = Mask.getOperand(i);
1523 if (Arg.getOpcode() == ISD::UNDEF) {
1524 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1526 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1527 unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
1529 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1530 DAG.getConstant(Idx, PtrVT)));
1532 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1533 DAG.getConstant(Idx - NumElems, PtrVT)));
1536 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1539 case TargetLowering::Promote: {
1540 // Change base type to a different vector type.
1541 MVT OVT = Node->getValueType(0);
1542 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1544 // Cast the two input vectors.
1545 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1546 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1548 // Convert the shuffle mask to the right # elements.
1549 Tmp3 = SDValue(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1550 assert(Tmp3.getNode() && "Shuffle not legal?");
1551 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1552 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1558 case ISD::EXTRACT_VECTOR_ELT:
1559 Tmp1 = Node->getOperand(0);
1560 Tmp2 = LegalizeOp(Node->getOperand(1));
1561 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1562 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1565 case ISD::EXTRACT_SUBVECTOR:
1566 Tmp1 = Node->getOperand(0);
1567 Tmp2 = LegalizeOp(Node->getOperand(1));
1568 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1569 Result = ExpandEXTRACT_SUBVECTOR(Result);
1572 case ISD::CALLSEQ_START: {
1573 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1575 // Recursively Legalize all of the inputs of the call end that do not lead
1576 // to this call start. This ensures that any libcalls that need be inserted
1577 // are inserted *before* the CALLSEQ_START.
1578 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1579 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1580 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
1584 // Now that we legalized all of the inputs (which may have inserted
1585 // libcalls) create the new CALLSEQ_START node.
1586 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1588 // Merge in the last call, to ensure that this call start after the last
1590 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1591 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1592 Tmp1 = LegalizeOp(Tmp1);
1595 // Do not try to legalize the target-specific arguments (#1+).
1596 if (Tmp1 != Node->getOperand(0)) {
1597 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1599 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1602 // Remember that the CALLSEQ_START is legalized.
1603 AddLegalizedOperand(Op.getValue(0), Result);
1604 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1605 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1607 // Now that the callseq_start and all of the non-call nodes above this call
1608 // sequence have been legalized, legalize the call itself. During this
1609 // process, no libcalls can/will be inserted, guaranteeing that no calls
1611 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1612 // Note that we are selecting this call!
1613 LastCALLSEQ_END = SDValue(CallEnd, 0);
1614 IsLegalizingCall = true;
1616 // Legalize the call, starting from the CALLSEQ_END.
1617 LegalizeOp(LastCALLSEQ_END);
1618 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1621 case ISD::CALLSEQ_END:
1622 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1623 // will cause this node to be legalized as well as handling libcalls right.
1624 if (LastCALLSEQ_END.getNode() != Node) {
1625 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
1626 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1627 assert(I != LegalizedNodes.end() &&
1628 "Legalizing the call start should have legalized this node!");
1632 // Otherwise, the call start has been legalized and everything is going
1633 // according to plan. Just legalize ourselves normally here.
1634 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1635 // Do not try to legalize the target-specific arguments (#1+), except for
1636 // an optional flag input.
1637 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1638 if (Tmp1 != Node->getOperand(0)) {
1639 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1641 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1644 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1645 if (Tmp1 != Node->getOperand(0) ||
1646 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1647 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1650 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1653 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1654 // This finishes up call legalization.
1655 IsLegalizingCall = false;
1657 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1658 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1659 if (Node->getNumValues() == 2)
1660 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1661 return Result.getValue(Op.getResNo());
1662 case ISD::DYNAMIC_STACKALLOC: {
1663 MVT VT = Node->getValueType(0);
1664 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1665 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1666 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1667 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1669 Tmp1 = Result.getValue(0);
1670 Tmp2 = Result.getValue(1);
1671 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1672 default: assert(0 && "This action is not supported yet!");
1673 case TargetLowering::Expand: {
1674 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1675 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1676 " not tell us which reg is the stack pointer!");
1677 SDValue Chain = Tmp1.getOperand(0);
1679 // Chain the dynamic stack allocation so that it doesn't modify the stack
1680 // pointer when other instructions are using the stack.
1681 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1683 SDValue Size = Tmp2.getOperand(1);
1684 SDValue SP = DAG.getCopyFromReg(Chain, SPReg, VT);
1685 Chain = SP.getValue(1);
1686 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1687 unsigned StackAlign =
1688 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1689 if (Align > StackAlign)
1690 SP = DAG.getNode(ISD::AND, VT, SP,
1691 DAG.getConstant(-(uint64_t)Align, VT));
1692 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value
1693 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
1695 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1696 DAG.getIntPtrConstant(0, true), SDValue());
1698 Tmp1 = LegalizeOp(Tmp1);
1699 Tmp2 = LegalizeOp(Tmp2);
1702 case TargetLowering::Custom:
1703 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1704 if (Tmp3.getNode()) {
1705 Tmp1 = LegalizeOp(Tmp3);
1706 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1709 case TargetLowering::Legal:
1712 // Since this op produce two values, make sure to remember that we
1713 // legalized both of them.
1714 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
1715 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
1716 return Op.getResNo() ? Tmp2 : Tmp1;
1718 case ISD::INLINEASM: {
1719 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1720 bool Changed = false;
1721 // Legalize all of the operands of the inline asm, in case they are nodes
1722 // that need to be expanded or something. Note we skip the asm string and
1723 // all of the TargetConstant flags.
1724 SDValue Op = LegalizeOp(Ops[0]);
1725 Changed = Op != Ops[0];
1728 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1729 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1730 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getZExtValue() >> 3;
1731 for (++i; NumVals; ++i, --NumVals) {
1732 SDValue Op = LegalizeOp(Ops[i]);
1741 Op = LegalizeOp(Ops.back());
1742 Changed |= Op != Ops.back();
1747 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1749 // INLINE asm returns a chain and flag, make sure to add both to the map.
1750 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1751 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1752 return Result.getValue(Op.getResNo());
1755 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1756 // Ensure that libcalls are emitted before a branch.
1757 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1758 Tmp1 = LegalizeOp(Tmp1);
1759 LastCALLSEQ_END = DAG.getEntryNode();
1761 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1764 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1765 // Ensure that libcalls are emitted before a branch.
1766 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1767 Tmp1 = LegalizeOp(Tmp1);
1768 LastCALLSEQ_END = DAG.getEntryNode();
1770 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1771 default: assert(0 && "Indirect target must be legal type (pointer)!");
1773 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1776 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1779 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1780 // Ensure that libcalls are emitted before a branch.
1781 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1782 Tmp1 = LegalizeOp(Tmp1);
1783 LastCALLSEQ_END = DAG.getEntryNode();
1785 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1786 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1788 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1789 default: assert(0 && "This action is not supported yet!");
1790 case TargetLowering::Legal: break;
1791 case TargetLowering::Custom:
1792 Tmp1 = TLI.LowerOperation(Result, DAG);
1793 if (Tmp1.getNode()) Result = Tmp1;
1795 case TargetLowering::Expand: {
1796 SDValue Chain = Result.getOperand(0);
1797 SDValue Table = Result.getOperand(1);
1798 SDValue Index = Result.getOperand(2);
1800 MVT PTy = TLI.getPointerTy();
1801 MachineFunction &MF = DAG.getMachineFunction();
1802 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
1803 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1804 SDValue Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1807 switch (EntrySize) {
1808 default: assert(0 && "Size of jump table not supported yet."); break;
1809 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr,
1810 PseudoSourceValue::getJumpTable(), 0); break;
1811 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr,
1812 PseudoSourceValue::getJumpTable(), 0); break;
1816 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1817 // For PIC, the sequence is:
1818 // BRIND(load(Jumptable + index) + RelocBase)
1819 // RelocBase can be JumpTable, GOT or some sort of global base.
1820 if (PTy != MVT::i32)
1821 Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr);
1822 Addr = DAG.getNode(ISD::ADD, PTy, Addr,
1823 TLI.getPICJumpTableRelocBase(Table, DAG));
1825 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1830 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1831 // Ensure that libcalls are emitted before a return.
1832 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1833 Tmp1 = LegalizeOp(Tmp1);
1834 LastCALLSEQ_END = DAG.getEntryNode();
1836 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1837 case Expand: assert(0 && "It's impossible to expand bools");
1839 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1842 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1844 // The top bits of the promoted condition are not necessarily zero, ensure
1845 // that the value is properly zero extended.
1846 unsigned BitWidth = Tmp2.getValueSizeInBits();
1847 if (!DAG.MaskedValueIsZero(Tmp2,
1848 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
1849 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1854 // Basic block destination (Op#2) is always legal.
1855 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1857 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1858 default: assert(0 && "This action is not supported yet!");
1859 case TargetLowering::Legal: break;
1860 case TargetLowering::Custom:
1861 Tmp1 = TLI.LowerOperation(Result, DAG);
1862 if (Tmp1.getNode()) Result = Tmp1;
1864 case TargetLowering::Expand:
1865 // Expand brcond's setcc into its constituent parts and create a BR_CC
1867 if (Tmp2.getOpcode() == ISD::SETCC) {
1868 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1869 Tmp2.getOperand(0), Tmp2.getOperand(1),
1870 Node->getOperand(2));
1872 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1873 DAG.getCondCode(ISD::SETNE), Tmp2,
1874 DAG.getConstant(0, Tmp2.getValueType()),
1875 Node->getOperand(2));
1881 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1882 // Ensure that libcalls are emitted before a branch.
1883 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1884 Tmp1 = LegalizeOp(Tmp1);
1885 Tmp2 = Node->getOperand(2); // LHS
1886 Tmp3 = Node->getOperand(3); // RHS
1887 Tmp4 = Node->getOperand(1); // CC
1889 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1890 LastCALLSEQ_END = DAG.getEntryNode();
1892 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1893 // the LHS is a legal SETCC itself. In this case, we need to compare
1894 // the result against zero to select between true and false values.
1895 if (Tmp3.getNode() == 0) {
1896 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1897 Tmp4 = DAG.getCondCode(ISD::SETNE);
1900 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1901 Node->getOperand(4));
1903 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1904 default: assert(0 && "Unexpected action for BR_CC!");
1905 case TargetLowering::Legal: break;
1906 case TargetLowering::Custom:
1907 Tmp4 = TLI.LowerOperation(Result, DAG);
1908 if (Tmp4.getNode()) Result = Tmp4;
1913 LoadSDNode *LD = cast<LoadSDNode>(Node);
1914 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1915 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1917 ISD::LoadExtType ExtType = LD->getExtensionType();
1918 if (ExtType == ISD::NON_EXTLOAD) {
1919 MVT VT = Node->getValueType(0);
1920 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1921 Tmp3 = Result.getValue(0);
1922 Tmp4 = Result.getValue(1);
1924 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1925 default: assert(0 && "This action is not supported yet!");
1926 case TargetLowering::Legal:
1927 // If this is an unaligned load and the target doesn't support it,
1929 if (!TLI.allowsUnalignedMemoryAccesses()) {
1930 unsigned ABIAlignment = TLI.getTargetData()->
1931 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
1932 if (LD->getAlignment() < ABIAlignment){
1933 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
1935 Tmp3 = Result.getOperand(0);
1936 Tmp4 = Result.getOperand(1);
1937 Tmp3 = LegalizeOp(Tmp3);
1938 Tmp4 = LegalizeOp(Tmp4);
1942 case TargetLowering::Custom:
1943 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1944 if (Tmp1.getNode()) {
1945 Tmp3 = LegalizeOp(Tmp1);
1946 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1949 case TargetLowering::Promote: {
1950 // Only promote a load of vector type to another.
1951 assert(VT.isVector() && "Cannot promote this load!");
1952 // Change base type to a different vector type.
1953 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1955 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1956 LD->getSrcValueOffset(),
1957 LD->isVolatile(), LD->getAlignment());
1958 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1959 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1963 // Since loads produce two values, make sure to remember that we
1964 // legalized both of them.
1965 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
1966 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
1967 return Op.getResNo() ? Tmp4 : Tmp3;
1969 MVT SrcVT = LD->getMemoryVT();
1970 unsigned SrcWidth = SrcVT.getSizeInBits();
1971 int SVOffset = LD->getSrcValueOffset();
1972 unsigned Alignment = LD->getAlignment();
1973 bool isVolatile = LD->isVolatile();
1975 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
1976 // Some targets pretend to have an i1 loading operation, and actually
1977 // load an i8. This trick is correct for ZEXTLOAD because the top 7
1978 // bits are guaranteed to be zero; it helps the optimizers understand
1979 // that these bits are zero. It is also useful for EXTLOAD, since it
1980 // tells the optimizers that those bits are undefined. It would be
1981 // nice to have an effective generic way of getting these benefits...
1982 // Until such a way is found, don't insist on promoting i1 here.
1983 (SrcVT != MVT::i1 ||
1984 TLI.getLoadXAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
1985 // Promote to a byte-sized load if not loading an integral number of
1986 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
1987 unsigned NewWidth = SrcVT.getStoreSizeInBits();
1988 MVT NVT = MVT::getIntegerVT(NewWidth);
1991 // The extra bits are guaranteed to be zero, since we stored them that
1992 // way. A zext load from NVT thus automatically gives zext from SrcVT.
1994 ISD::LoadExtType NewExtType =
1995 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
1997 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0),
1998 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
1999 NVT, isVolatile, Alignment);
2001 Ch = Result.getValue(1); // The chain.
2003 if (ExtType == ISD::SEXTLOAD)
2004 // Having the top bits zero doesn't help when sign extending.
2005 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2006 Result, DAG.getValueType(SrcVT));
2007 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
2008 // All the top bits are guaranteed to be zero - inform the optimizers.
2009 Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result,
2010 DAG.getValueType(SrcVT));
2012 Tmp1 = LegalizeOp(Result);
2013 Tmp2 = LegalizeOp(Ch);
2014 } else if (SrcWidth & (SrcWidth - 1)) {
2015 // If not loading a power-of-2 number of bits, expand as two loads.
2016 assert(SrcVT.isExtended() && !SrcVT.isVector() &&
2017 "Unsupported extload!");
2018 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
2019 assert(RoundWidth < SrcWidth);
2020 unsigned ExtraWidth = SrcWidth - RoundWidth;
2021 assert(ExtraWidth < RoundWidth);
2022 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2023 "Load size not an integral number of bytes!");
2024 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2025 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2027 unsigned IncrementSize;
2029 if (TLI.isLittleEndian()) {
2030 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
2031 // Load the bottom RoundWidth bits.
2032 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2033 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2036 // Load the remaining ExtraWidth bits.
2037 IncrementSize = RoundWidth / 8;
2038 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2039 DAG.getIntPtrConstant(IncrementSize));
2040 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2041 LD->getSrcValue(), SVOffset + IncrementSize,
2042 ExtraVT, isVolatile,
2043 MinAlign(Alignment, IncrementSize));
2045 // Build a factor node to remember that this load is independent of the
2047 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2050 // Move the top bits to the right place.
2051 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2052 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2054 // Join the hi and lo parts.
2055 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2057 // Big endian - avoid unaligned loads.
2058 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
2059 // Load the top RoundWidth bits.
2060 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2061 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2064 // Load the remaining ExtraWidth bits.
2065 IncrementSize = RoundWidth / 8;
2066 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2067 DAG.getIntPtrConstant(IncrementSize));
2068 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2069 LD->getSrcValue(), SVOffset + IncrementSize,
2070 ExtraVT, isVolatile,
2071 MinAlign(Alignment, IncrementSize));
2073 // Build a factor node to remember that this load is independent of the
2075 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2078 // Move the top bits to the right place.
2079 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2080 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2082 // Join the hi and lo parts.
2083 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2086 Tmp1 = LegalizeOp(Result);
2087 Tmp2 = LegalizeOp(Ch);
2089 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
2090 default: assert(0 && "This action is not supported yet!");
2091 case TargetLowering::Custom:
2094 case TargetLowering::Legal:
2095 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2096 Tmp1 = Result.getValue(0);
2097 Tmp2 = Result.getValue(1);
2100 Tmp3 = TLI.LowerOperation(Result, DAG);
2101 if (Tmp3.getNode()) {
2102 Tmp1 = LegalizeOp(Tmp3);
2103 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2106 // If this is an unaligned load and the target doesn't support it,
2108 if (!TLI.allowsUnalignedMemoryAccesses()) {
2109 unsigned ABIAlignment = TLI.getTargetData()->
2110 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
2111 if (LD->getAlignment() < ABIAlignment){
2112 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
2114 Tmp1 = Result.getOperand(0);
2115 Tmp2 = Result.getOperand(1);
2116 Tmp1 = LegalizeOp(Tmp1);
2117 Tmp2 = LegalizeOp(Tmp2);
2122 case TargetLowering::Expand:
2123 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
2124 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
2125 SDValue Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
2126 LD->getSrcValueOffset(),
2127 LD->isVolatile(), LD->getAlignment());
2128 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
2129 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
2130 Tmp2 = LegalizeOp(Load.getValue(1));
2133 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
2134 // Turn the unsupported load into an EXTLOAD followed by an explicit
2135 // zero/sign extend inreg.
2136 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2137 Tmp1, Tmp2, LD->getSrcValue(),
2138 LD->getSrcValueOffset(), SrcVT,
2139 LD->isVolatile(), LD->getAlignment());
2141 if (ExtType == ISD::SEXTLOAD)
2142 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2143 Result, DAG.getValueType(SrcVT));
2145 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
2146 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
2147 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
2152 // Since loads produce two values, make sure to remember that we legalized
2154 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2155 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2156 return Op.getResNo() ? Tmp2 : Tmp1;
2159 case ISD::EXTRACT_ELEMENT: {
2160 MVT OpTy = Node->getOperand(0).getValueType();
2161 switch (getTypeAction(OpTy)) {
2162 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
2164 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
2166 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
2167 DAG.getConstant(OpTy.getSizeInBits()/2,
2168 TLI.getShiftAmountTy()));
2169 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
2172 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
2173 Node->getOperand(0));
2177 // Get both the low and high parts.
2178 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2179 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
2180 Result = Tmp2; // 1 -> Hi
2182 Result = Tmp1; // 0 -> Lo
2188 case ISD::CopyToReg:
2189 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2191 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
2192 "Register type must be legal!");
2193 // Legalize the incoming value (must be a legal type).
2194 Tmp2 = LegalizeOp(Node->getOperand(2));
2195 if (Node->getNumValues() == 1) {
2196 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
2198 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
2199 if (Node->getNumOperands() == 4) {
2200 Tmp3 = LegalizeOp(Node->getOperand(3));
2201 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
2204 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
2207 // Since this produces two values, make sure to remember that we legalized
2209 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
2210 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
2216 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2218 // Ensure that libcalls are emitted before a return.
2219 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2220 Tmp1 = LegalizeOp(Tmp1);
2221 LastCALLSEQ_END = DAG.getEntryNode();
2223 switch (Node->getNumOperands()) {
2225 Tmp2 = Node->getOperand(1);
2226 Tmp3 = Node->getOperand(2); // Signness
2227 switch (getTypeAction(Tmp2.getValueType())) {
2229 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
2232 if (!Tmp2.getValueType().isVector()) {
2234 ExpandOp(Tmp2, Lo, Hi);
2236 // Big endian systems want the hi reg first.
2237 if (TLI.isBigEndian())
2241 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2243 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
2244 Result = LegalizeOp(Result);
2246 SDNode *InVal = Tmp2.getNode();
2247 int InIx = Tmp2.getResNo();
2248 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
2249 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
2251 // Figure out if there is a simple type corresponding to this Vector
2252 // type. If so, convert to the vector type.
2253 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2254 if (TLI.isTypeLegal(TVT)) {
2255 // Turn this into a return of the vector type.
2256 Tmp2 = LegalizeOp(Tmp2);
2257 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2258 } else if (NumElems == 1) {
2259 // Turn this into a return of the scalar type.
2260 Tmp2 = ScalarizeVectorOp(Tmp2);
2261 Tmp2 = LegalizeOp(Tmp2);
2262 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2264 // FIXME: Returns of gcc generic vectors smaller than a legal type
2265 // should be returned in integer registers!
2267 // The scalarized value type may not be legal, e.g. it might require
2268 // promotion or expansion. Relegalize the return.
2269 Result = LegalizeOp(Result);
2271 // FIXME: Returns of gcc generic vectors larger than a legal vector
2272 // type should be returned by reference!
2274 SplitVectorOp(Tmp2, Lo, Hi);
2275 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2276 Result = LegalizeOp(Result);
2281 Tmp2 = PromoteOp(Node->getOperand(1));
2282 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2283 Result = LegalizeOp(Result);
2288 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2290 default: { // ret <values>
2291 SmallVector<SDValue, 8> NewValues;
2292 NewValues.push_back(Tmp1);
2293 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
2294 switch (getTypeAction(Node->getOperand(i).getValueType())) {
2296 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
2297 NewValues.push_back(Node->getOperand(i+1));
2301 assert(!Node->getOperand(i).getValueType().isExtended() &&
2302 "FIXME: TODO: implement returning non-legal vector types!");
2303 ExpandOp(Node->getOperand(i), Lo, Hi);
2304 NewValues.push_back(Lo);
2305 NewValues.push_back(Node->getOperand(i+1));
2307 NewValues.push_back(Hi);
2308 NewValues.push_back(Node->getOperand(i+1));
2313 assert(0 && "Can't promote multiple return value yet!");
2316 if (NewValues.size() == Node->getNumOperands())
2317 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
2319 Result = DAG.getNode(ISD::RET, MVT::Other,
2320 &NewValues[0], NewValues.size());
2325 if (Result.getOpcode() == ISD::RET) {
2326 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
2327 default: assert(0 && "This action is not supported yet!");
2328 case TargetLowering::Legal: break;
2329 case TargetLowering::Custom:
2330 Tmp1 = TLI.LowerOperation(Result, DAG);
2331 if (Tmp1.getNode()) Result = Tmp1;
2337 StoreSDNode *ST = cast<StoreSDNode>(Node);
2338 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
2339 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
2340 int SVOffset = ST->getSrcValueOffset();
2341 unsigned Alignment = ST->getAlignment();
2342 bool isVolatile = ST->isVolatile();
2344 if (!ST->isTruncatingStore()) {
2345 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
2346 // FIXME: We shouldn't do this for TargetConstantFP's.
2347 // FIXME: move this to the DAG Combiner! Note that we can't regress due
2348 // to phase ordering between legalized code and the dag combiner. This
2349 // probably means that we need to integrate dag combiner and legalizer
2351 // We generally can't do this one for long doubles.
2352 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
2353 if (CFP->getValueType(0) == MVT::f32 &&
2354 getTypeAction(MVT::i32) == Legal) {
2355 Tmp3 = DAG.getConstant(CFP->getValueAPF().
2356 bitcastToAPInt().zextOrTrunc(32),
2358 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2359 SVOffset, isVolatile, Alignment);
2361 } else if (CFP->getValueType(0) == MVT::f64) {
2362 // If this target supports 64-bit registers, do a single 64-bit store.
2363 if (getTypeAction(MVT::i64) == Legal) {
2364 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
2365 zextOrTrunc(64), MVT::i64);
2366 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2367 SVOffset, isVolatile, Alignment);
2369 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
2370 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
2371 // stores. If the target supports neither 32- nor 64-bits, this
2372 // xform is certainly not worth it.
2373 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
2374 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
2375 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
2376 if (TLI.isBigEndian()) std::swap(Lo, Hi);
2378 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2379 SVOffset, isVolatile, Alignment);
2380 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2381 DAG.getIntPtrConstant(4));
2382 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
2383 isVolatile, MinAlign(Alignment, 4U));
2385 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2391 switch (getTypeAction(ST->getMemoryVT())) {
2393 Tmp3 = LegalizeOp(ST->getValue());
2394 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2397 MVT VT = Tmp3.getValueType();
2398 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2399 default: assert(0 && "This action is not supported yet!");
2400 case TargetLowering::Legal:
2401 // If this is an unaligned store and the target doesn't support it,
2403 if (!TLI.allowsUnalignedMemoryAccesses()) {
2404 unsigned ABIAlignment = TLI.getTargetData()->
2405 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2406 if (ST->getAlignment() < ABIAlignment)
2407 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
2411 case TargetLowering::Custom:
2412 Tmp1 = TLI.LowerOperation(Result, DAG);
2413 if (Tmp1.getNode()) Result = Tmp1;
2415 case TargetLowering::Promote:
2416 assert(VT.isVector() && "Unknown legal promote case!");
2417 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
2418 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2419 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
2420 ST->getSrcValue(), SVOffset, isVolatile,
2427 // Truncate the value and store the result.
2428 Tmp3 = PromoteOp(ST->getValue());
2429 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2430 SVOffset, ST->getMemoryVT(),
2431 isVolatile, Alignment);
2435 unsigned IncrementSize = 0;
2438 // If this is a vector type, then we have to calculate the increment as
2439 // the product of the element size in bytes, and the number of elements
2440 // in the high half of the vector.
2441 if (ST->getValue().getValueType().isVector()) {
2442 SDNode *InVal = ST->getValue().getNode();
2443 int InIx = ST->getValue().getResNo();
2444 MVT InVT = InVal->getValueType(InIx);
2445 unsigned NumElems = InVT.getVectorNumElements();
2446 MVT EVT = InVT.getVectorElementType();
2448 // Figure out if there is a simple type corresponding to this Vector
2449 // type. If so, convert to the vector type.
2450 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2451 if (TLI.isTypeLegal(TVT)) {
2452 // Turn this into a normal store of the vector type.
2453 Tmp3 = LegalizeOp(ST->getValue());
2454 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2455 SVOffset, isVolatile, Alignment);
2456 Result = LegalizeOp(Result);
2458 } else if (NumElems == 1) {
2459 // Turn this into a normal store of the scalar type.
2460 Tmp3 = ScalarizeVectorOp(ST->getValue());
2461 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2462 SVOffset, isVolatile, Alignment);
2463 // The scalarized value type may not be legal, e.g. it might require
2464 // promotion or expansion. Relegalize the scalar store.
2465 Result = LegalizeOp(Result);
2468 SplitVectorOp(ST->getValue(), Lo, Hi);
2469 IncrementSize = Lo.getNode()->getValueType(0).getVectorNumElements() *
2470 EVT.getSizeInBits()/8;
2473 ExpandOp(ST->getValue(), Lo, Hi);
2474 IncrementSize = Hi.getNode() ? Hi.getValueType().getSizeInBits()/8 : 0;
2476 if (Hi.getNode() && TLI.isBigEndian())
2480 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2481 SVOffset, isVolatile, Alignment);
2483 if (Hi.getNode() == NULL) {
2484 // Must be int <-> float one-to-one expansion.
2489 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2490 DAG.getIntPtrConstant(IncrementSize));
2491 assert(isTypeLegal(Tmp2.getValueType()) &&
2492 "Pointers must be legal!");
2493 SVOffset += IncrementSize;
2494 Alignment = MinAlign(Alignment, IncrementSize);
2495 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2496 SVOffset, isVolatile, Alignment);
2497 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2501 switch (getTypeAction(ST->getValue().getValueType())) {
2503 Tmp3 = LegalizeOp(ST->getValue());
2506 // We can promote the value, the truncstore will still take care of it.
2507 Tmp3 = PromoteOp(ST->getValue());
2510 // Just store the low part. This may become a non-trunc store, so make
2511 // sure to use getTruncStore, not UpdateNodeOperands below.
2512 ExpandOp(ST->getValue(), Tmp3, Tmp4);
2513 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2514 SVOffset, MVT::i8, isVolatile, Alignment);
2517 MVT StVT = ST->getMemoryVT();
2518 unsigned StWidth = StVT.getSizeInBits();
2520 if (StWidth != StVT.getStoreSizeInBits()) {
2521 // Promote to a byte-sized store with upper bits zero if not
2522 // storing an integral number of bytes. For example, promote
2523 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
2524 MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits());
2525 Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT);
2526 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2527 SVOffset, NVT, isVolatile, Alignment);
2528 } else if (StWidth & (StWidth - 1)) {
2529 // If not storing a power-of-2 number of bits, expand as two stores.
2530 assert(StVT.isExtended() && !StVT.isVector() &&
2531 "Unsupported truncstore!");
2532 unsigned RoundWidth = 1 << Log2_32(StWidth);
2533 assert(RoundWidth < StWidth);
2534 unsigned ExtraWidth = StWidth - RoundWidth;
2535 assert(ExtraWidth < RoundWidth);
2536 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2537 "Store size not an integral number of bytes!");
2538 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2539 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2541 unsigned IncrementSize;
2543 if (TLI.isLittleEndian()) {
2544 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
2545 // Store the bottom RoundWidth bits.
2546 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2548 isVolatile, Alignment);
2550 // Store the remaining ExtraWidth bits.
2551 IncrementSize = RoundWidth / 8;
2552 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2553 DAG.getIntPtrConstant(IncrementSize));
2554 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2555 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2556 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2557 SVOffset + IncrementSize, ExtraVT, isVolatile,
2558 MinAlign(Alignment, IncrementSize));
2560 // Big endian - avoid unaligned stores.
2561 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
2562 // Store the top RoundWidth bits.
2563 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2564 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2565 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset,
2566 RoundVT, isVolatile, Alignment);
2568 // Store the remaining ExtraWidth bits.
2569 IncrementSize = RoundWidth / 8;
2570 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2571 DAG.getIntPtrConstant(IncrementSize));
2572 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2573 SVOffset + IncrementSize, ExtraVT, isVolatile,
2574 MinAlign(Alignment, IncrementSize));
2577 // The order of the stores doesn't matter.
2578 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2580 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2581 Tmp2 != ST->getBasePtr())
2582 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2585 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
2586 default: assert(0 && "This action is not supported yet!");
2587 case TargetLowering::Legal:
2588 // If this is an unaligned store and the target doesn't support it,
2590 if (!TLI.allowsUnalignedMemoryAccesses()) {
2591 unsigned ABIAlignment = TLI.getTargetData()->
2592 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2593 if (ST->getAlignment() < ABIAlignment)
2594 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
2598 case TargetLowering::Custom:
2599 Result = TLI.LowerOperation(Result, DAG);
2602 // TRUNCSTORE:i16 i32 -> STORE i16
2603 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
2604 Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3);
2605 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset,
2606 isVolatile, Alignment);
2614 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2615 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2617 case ISD::STACKSAVE:
2618 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2619 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2620 Tmp1 = Result.getValue(0);
2621 Tmp2 = Result.getValue(1);
2623 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2624 default: assert(0 && "This action is not supported yet!");
2625 case TargetLowering::Legal: break;
2626 case TargetLowering::Custom:
2627 Tmp3 = TLI.LowerOperation(Result, DAG);
2628 if (Tmp3.getNode()) {
2629 Tmp1 = LegalizeOp(Tmp3);
2630 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2633 case TargetLowering::Expand:
2634 // Expand to CopyFromReg if the target set
2635 // StackPointerRegisterToSaveRestore.
2636 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2637 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
2638 Node->getValueType(0));
2639 Tmp2 = Tmp1.getValue(1);
2641 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
2642 Tmp2 = Node->getOperand(0);
2647 // Since stacksave produce two values, make sure to remember that we
2648 // legalized both of them.
2649 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2650 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2651 return Op.getResNo() ? Tmp2 : Tmp1;
2653 case ISD::STACKRESTORE:
2654 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2655 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2656 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2658 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2659 default: assert(0 && "This action is not supported yet!");
2660 case TargetLowering::Legal: break;
2661 case TargetLowering::Custom:
2662 Tmp1 = TLI.LowerOperation(Result, DAG);
2663 if (Tmp1.getNode()) Result = Tmp1;
2665 case TargetLowering::Expand:
2666 // Expand to CopyToReg if the target set
2667 // StackPointerRegisterToSaveRestore.
2668 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2669 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
2677 case ISD::READCYCLECOUNTER:
2678 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2679 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2680 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2681 Node->getValueType(0))) {
2682 default: assert(0 && "This action is not supported yet!");
2683 case TargetLowering::Legal:
2684 Tmp1 = Result.getValue(0);
2685 Tmp2 = Result.getValue(1);
2687 case TargetLowering::Custom:
2688 Result = TLI.LowerOperation(Result, DAG);
2689 Tmp1 = LegalizeOp(Result.getValue(0));
2690 Tmp2 = LegalizeOp(Result.getValue(1));
2694 // Since rdcc produce two values, make sure to remember that we legalized
2696 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2697 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2701 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2702 case Expand: assert(0 && "It's impossible to expand bools");
2704 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2707 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2708 // Make sure the condition is either zero or one.
2709 unsigned BitWidth = Tmp1.getValueSizeInBits();
2710 if (!DAG.MaskedValueIsZero(Tmp1,
2711 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2712 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2716 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2717 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2719 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2721 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2722 default: assert(0 && "This action is not supported yet!");
2723 case TargetLowering::Legal: break;
2724 case TargetLowering::Custom: {
2725 Tmp1 = TLI.LowerOperation(Result, DAG);
2726 if (Tmp1.getNode()) Result = Tmp1;
2729 case TargetLowering::Expand:
2730 if (Tmp1.getOpcode() == ISD::SETCC) {
2731 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2733 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2735 Result = DAG.getSelectCC(Tmp1,
2736 DAG.getConstant(0, Tmp1.getValueType()),
2737 Tmp2, Tmp3, ISD::SETNE);
2740 case TargetLowering::Promote: {
2742 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2743 unsigned ExtOp, TruncOp;
2744 if (Tmp2.getValueType().isVector()) {
2745 ExtOp = ISD::BIT_CONVERT;
2746 TruncOp = ISD::BIT_CONVERT;
2747 } else if (Tmp2.getValueType().isInteger()) {
2748 ExtOp = ISD::ANY_EXTEND;
2749 TruncOp = ISD::TRUNCATE;
2751 ExtOp = ISD::FP_EXTEND;
2752 TruncOp = ISD::FP_ROUND;
2754 // Promote each of the values to the new type.
2755 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2756 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2757 // Perform the larger operation, then round down.
2758 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2759 if (TruncOp != ISD::FP_ROUND)
2760 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2762 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result,
2763 DAG.getIntPtrConstant(0));
2768 case ISD::SELECT_CC: {
2769 Tmp1 = Node->getOperand(0); // LHS
2770 Tmp2 = Node->getOperand(1); // RHS
2771 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2772 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2773 SDValue CC = Node->getOperand(4);
2775 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
2777 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
2778 // the LHS is a legal SETCC itself. In this case, we need to compare
2779 // the result against zero to select between true and false values.
2780 if (Tmp2.getNode() == 0) {
2781 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2782 CC = DAG.getCondCode(ISD::SETNE);
2784 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
2786 // Everything is legal, see if we should expand this op or something.
2787 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
2788 default: assert(0 && "This action is not supported yet!");
2789 case TargetLowering::Legal: break;
2790 case TargetLowering::Custom:
2791 Tmp1 = TLI.LowerOperation(Result, DAG);
2792 if (Tmp1.getNode()) Result = Tmp1;
2798 Tmp1 = Node->getOperand(0);
2799 Tmp2 = Node->getOperand(1);
2800 Tmp3 = Node->getOperand(2);
2801 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
2803 // If we had to Expand the SetCC operands into a SELECT node, then it may
2804 // not always be possible to return a true LHS & RHS. In this case, just
2805 // return the value we legalized, returned in the LHS
2806 if (Tmp2.getNode() == 0) {
2811 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
2812 default: assert(0 && "Cannot handle this action for SETCC yet!");
2813 case TargetLowering::Custom:
2816 case TargetLowering::Legal:
2817 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2819 Tmp4 = TLI.LowerOperation(Result, DAG);
2820 if (Tmp4.getNode()) Result = Tmp4;
2823 case TargetLowering::Promote: {
2824 // First step, figure out the appropriate operation to use.
2825 // Allow SETCC to not be supported for all legal data types
2826 // Mostly this targets FP
2827 MVT NewInTy = Node->getOperand(0).getValueType();
2828 MVT OldVT = NewInTy; OldVT = OldVT;
2830 // Scan for the appropriate larger type to use.
2832 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
2834 assert(NewInTy.isInteger() == OldVT.isInteger() &&
2835 "Fell off of the edge of the integer world");
2836 assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() &&
2837 "Fell off of the edge of the floating point world");
2839 // If the target supports SETCC of this type, use it.
2840 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2843 if (NewInTy.isInteger())
2844 assert(0 && "Cannot promote Legal Integer SETCC yet");
2846 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2847 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2849 Tmp1 = LegalizeOp(Tmp1);
2850 Tmp2 = LegalizeOp(Tmp2);
2851 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2852 Result = LegalizeOp(Result);
2855 case TargetLowering::Expand:
2856 // Expand a setcc node into a select_cc of the same condition, lhs, and
2857 // rhs that selects between const 1 (true) and const 0 (false).
2858 MVT VT = Node->getValueType(0);
2859 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2860 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2866 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2867 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2868 SDValue CC = Node->getOperand(2);
2870 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, CC);
2872 // Everything is legal, see if we should expand this op or something.
2873 switch (TLI.getOperationAction(ISD::VSETCC, Tmp1.getValueType())) {
2874 default: assert(0 && "This action is not supported yet!");
2875 case TargetLowering::Legal: break;
2876 case TargetLowering::Custom:
2877 Tmp1 = TLI.LowerOperation(Result, DAG);
2878 if (Tmp1.getNode()) Result = Tmp1;
2884 case ISD::SHL_PARTS:
2885 case ISD::SRA_PARTS:
2886 case ISD::SRL_PARTS: {
2887 SmallVector<SDValue, 8> Ops;
2888 bool Changed = false;
2889 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2890 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2891 Changed |= Ops.back() != Node->getOperand(i);
2894 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2896 switch (TLI.getOperationAction(Node->getOpcode(),
2897 Node->getValueType(0))) {
2898 default: assert(0 && "This action is not supported yet!");
2899 case TargetLowering::Legal: break;
2900 case TargetLowering::Custom:
2901 Tmp1 = TLI.LowerOperation(Result, DAG);
2902 if (Tmp1.getNode()) {
2903 SDValue Tmp2, RetVal(0, 0);
2904 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2905 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2906 AddLegalizedOperand(SDValue(Node, i), Tmp2);
2907 if (i == Op.getResNo())
2910 assert(RetVal.getNode() && "Illegal result number");
2916 // Since these produce multiple values, make sure to remember that we
2917 // legalized all of them.
2918 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2919 AddLegalizedOperand(SDValue(Node, i), Result.getValue(i));
2920 return Result.getValue(Op.getResNo());
2942 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2943 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2944 case Expand: assert(0 && "Not possible");
2946 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2949 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2953 if ((Node->getOpcode() == ISD::SHL ||
2954 Node->getOpcode() == ISD::SRL ||
2955 Node->getOpcode() == ISD::SRA) &&
2956 !Node->getValueType(0).isVector()) {
2957 if (TLI.getShiftAmountTy().bitsLT(Tmp2.getValueType()))
2958 Tmp2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Tmp2);
2959 else if (TLI.getShiftAmountTy().bitsGT(Tmp2.getValueType()))
2960 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Tmp2);
2963 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2965 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2966 default: assert(0 && "BinOp legalize operation not supported");
2967 case TargetLowering::Legal: break;
2968 case TargetLowering::Custom:
2969 Tmp1 = TLI.LowerOperation(Result, DAG);
2970 if (Tmp1.getNode()) {
2974 // Fall through if the custom lower can't deal with the operation
2975 case TargetLowering::Expand: {
2976 MVT VT = Op.getValueType();
2978 // See if multiply or divide can be lowered using two-result operations.
2979 SDVTList VTs = DAG.getVTList(VT, VT);
2980 if (Node->getOpcode() == ISD::MUL) {
2981 // We just need the low half of the multiply; try both the signed
2982 // and unsigned forms. If the target supports both SMUL_LOHI and
2983 // UMUL_LOHI, form a preference by checking which forms of plain
2984 // MULH it supports.
2985 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT);
2986 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT);
2987 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT);
2988 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT);
2989 unsigned OpToUse = 0;
2990 if (HasSMUL_LOHI && !HasMULHS) {
2991 OpToUse = ISD::SMUL_LOHI;
2992 } else if (HasUMUL_LOHI && !HasMULHU) {
2993 OpToUse = ISD::UMUL_LOHI;
2994 } else if (HasSMUL_LOHI) {
2995 OpToUse = ISD::SMUL_LOHI;
2996 } else if (HasUMUL_LOHI) {
2997 OpToUse = ISD::UMUL_LOHI;
3000 Result = SDValue(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).getNode(), 0);
3004 if (Node->getOpcode() == ISD::MULHS &&
3005 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) {
3006 Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).getNode(),
3010 if (Node->getOpcode() == ISD::MULHU &&
3011 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) {
3012 Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).getNode(),
3016 if (Node->getOpcode() == ISD::SDIV &&
3017 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3018 Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(),
3022 if (Node->getOpcode() == ISD::UDIV &&
3023 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3024 Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(),
3029 // Check to see if we have a libcall for this operator.
3030 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3031 bool isSigned = false;
3032 switch (Node->getOpcode()) {
3035 if (VT == MVT::i32) {
3036 LC = Node->getOpcode() == ISD::UDIV
3037 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
3038 isSigned = Node->getOpcode() == ISD::SDIV;
3043 LC = RTLIB::MUL_I32;
3046 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
3047 RTLIB::POW_PPCF128);
3051 if (LC != RTLIB::UNKNOWN_LIBCALL) {
3053 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3057 assert(Node->getValueType(0).isVector() &&
3058 "Cannot expand this binary operator!");
3059 // Expand the operation into a bunch of nasty scalar code.
3060 Result = LegalizeOp(UnrollVectorOp(Op));
3063 case TargetLowering::Promote: {
3064 switch (Node->getOpcode()) {
3065 default: assert(0 && "Do not know how to promote this BinOp!");
3069 MVT OVT = Node->getValueType(0);
3070 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3071 assert(OVT.isVector() && "Cannot promote this BinOp!");
3072 // Bit convert each of the values to the new type.
3073 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
3074 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
3075 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3076 // Bit convert the result back the original type.
3077 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
3085 case ISD::SMUL_LOHI:
3086 case ISD::UMUL_LOHI:
3089 // These nodes will only be produced by target-specific lowering, so
3090 // they shouldn't be here if they aren't legal.
3091 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
3092 "This must be legal!");
3094 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3095 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3096 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3099 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
3100 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3101 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3102 case Expand: assert(0 && "Not possible");
3104 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3107 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3111 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3113 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3114 default: assert(0 && "Operation not supported");
3115 case TargetLowering::Custom:
3116 Tmp1 = TLI.LowerOperation(Result, DAG);
3117 if (Tmp1.getNode()) Result = Tmp1;
3119 case TargetLowering::Legal: break;
3120 case TargetLowering::Expand: {
3121 // If this target supports fabs/fneg natively and select is cheap,
3122 // do this efficiently.
3123 if (!TLI.isSelectExpensive() &&
3124 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
3125 TargetLowering::Legal &&
3126 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
3127 TargetLowering::Legal) {
3128 // Get the sign bit of the RHS.
3130 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
3131 SDValue SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
3132 SignBit = DAG.getSetCC(TLI.getSetCCResultType(SignBit),
3133 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
3134 // Get the absolute value of the result.
3135 SDValue AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
3136 // Select between the nabs and abs value based on the sign bit of
3138 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
3139 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
3142 Result = LegalizeOp(Result);
3146 // Otherwise, do bitwise ops!
3148 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
3149 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
3150 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
3151 Result = LegalizeOp(Result);
3159 Tmp1 = LegalizeOp(Node->getOperand(0));
3160 Tmp2 = LegalizeOp(Node->getOperand(1));
3161 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3162 // Since this produces two values, make sure to remember that we legalized
3164 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
3165 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
3170 Tmp1 = LegalizeOp(Node->getOperand(0));
3171 Tmp2 = LegalizeOp(Node->getOperand(1));
3172 Tmp3 = LegalizeOp(Node->getOperand(2));
3173 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3174 // Since this produces two values, make sure to remember that we legalized
3176 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
3177 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
3180 case ISD::BUILD_PAIR: {
3181 MVT PairTy = Node->getValueType(0);
3182 // TODO: handle the case where the Lo and Hi operands are not of legal type
3183 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
3184 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
3185 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
3186 case TargetLowering::Promote:
3187 case TargetLowering::Custom:
3188 assert(0 && "Cannot promote/custom this yet!");
3189 case TargetLowering::Legal:
3190 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
3191 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
3193 case TargetLowering::Expand:
3194 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
3195 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
3196 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
3197 DAG.getConstant(PairTy.getSizeInBits()/2,
3198 TLI.getShiftAmountTy()));
3199 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
3208 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3209 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3211 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3212 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
3213 case TargetLowering::Custom:
3216 case TargetLowering::Legal:
3217 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3219 Tmp1 = TLI.LowerOperation(Result, DAG);
3220 if (Tmp1.getNode()) Result = Tmp1;
3223 case TargetLowering::Expand: {
3224 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
3225 bool isSigned = DivOpc == ISD::SDIV;
3226 MVT VT = Node->getValueType(0);
3228 // See if remainder can be lowered using two-result operations.
3229 SDVTList VTs = DAG.getVTList(VT, VT);
3230 if (Node->getOpcode() == ISD::SREM &&
3231 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3232 Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(), 1);
3235 if (Node->getOpcode() == ISD::UREM &&
3236 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3237 Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(), 1);
3241 if (VT.isInteger()) {
3242 if (TLI.getOperationAction(DivOpc, VT) ==
3243 TargetLowering::Legal) {
3245 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
3246 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
3247 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
3248 } else if (VT.isVector()) {
3249 Result = LegalizeOp(UnrollVectorOp(Op));
3251 assert(VT == MVT::i32 &&
3252 "Cannot expand this binary operator!");
3253 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
3254 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
3256 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3259 assert(VT.isFloatingPoint() &&
3260 "remainder op must have integer or floating-point type");
3261 if (VT.isVector()) {
3262 Result = LegalizeOp(UnrollVectorOp(Op));
3264 // Floating point mod -> fmod libcall.
3265 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
3266 RTLIB::REM_F80, RTLIB::REM_PPCF128);
3268 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3276 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3277 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3279 MVT VT = Node->getValueType(0);
3280 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
3281 default: assert(0 && "This action is not supported yet!");
3282 case TargetLowering::Custom:
3285 case TargetLowering::Legal:
3286 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3287 Result = Result.getValue(0);
3288 Tmp1 = Result.getValue(1);
3291 Tmp2 = TLI.LowerOperation(Result, DAG);
3292 if (Tmp2.getNode()) {
3293 Result = LegalizeOp(Tmp2);
3294 Tmp1 = LegalizeOp(Tmp2.getValue(1));
3298 case TargetLowering::Expand: {
3299 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3300 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
3301 // Increment the pointer, VAList, to the next vaarg
3302 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3303 DAG.getConstant(VT.getSizeInBits()/8,
3304 TLI.getPointerTy()));
3305 // Store the incremented VAList to the legalized pointer
3306 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
3307 // Load the actual argument out of the pointer VAList
3308 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
3309 Tmp1 = LegalizeOp(Result.getValue(1));
3310 Result = LegalizeOp(Result);
3314 // Since VAARG produces two values, make sure to remember that we
3315 // legalized both of them.
3316 AddLegalizedOperand(SDValue(Node, 0), Result);
3317 AddLegalizedOperand(SDValue(Node, 1), Tmp1);
3318 return Op.getResNo() ? Tmp1 : Result;
3322 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3323 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
3324 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
3326 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
3327 default: assert(0 && "This action is not supported yet!");
3328 case TargetLowering::Custom:
3331 case TargetLowering::Legal:
3332 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
3333 Node->getOperand(3), Node->getOperand(4));
3335 Tmp1 = TLI.LowerOperation(Result, DAG);
3336 if (Tmp1.getNode()) Result = Tmp1;
3339 case TargetLowering::Expand:
3340 // This defaults to loading a pointer from the input and storing it to the
3341 // output, returning the chain.
3342 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3343 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3344 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VS, 0);
3345 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VD, 0);
3351 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3352 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3354 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
3355 default: assert(0 && "This action is not supported yet!");
3356 case TargetLowering::Custom:
3359 case TargetLowering::Legal:
3360 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3362 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
3363 if (Tmp1.getNode()) Result = Tmp1;
3366 case TargetLowering::Expand:
3367 Result = Tmp1; // Default to a no-op, return the chain
3373 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3374 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3376 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3378 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
3379 default: assert(0 && "This action is not supported yet!");
3380 case TargetLowering::Legal: break;
3381 case TargetLowering::Custom:
3382 Tmp1 = TLI.LowerOperation(Result, DAG);
3383 if (Tmp1.getNode()) Result = Tmp1;
3390 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3391 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3392 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3393 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3395 assert(0 && "ROTL/ROTR legalize operation not supported");
3397 case TargetLowering::Legal:
3399 case TargetLowering::Custom:
3400 Tmp1 = TLI.LowerOperation(Result, DAG);
3401 if (Tmp1.getNode()) Result = Tmp1;
3403 case TargetLowering::Promote:
3404 assert(0 && "Do not know how to promote ROTL/ROTR");
3406 case TargetLowering::Expand:
3407 assert(0 && "Do not know how to expand ROTL/ROTR");
3413 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3414 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3415 case TargetLowering::Custom:
3416 assert(0 && "Cannot custom legalize this yet!");
3417 case TargetLowering::Legal:
3418 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3420 case TargetLowering::Promote: {
3421 MVT OVT = Tmp1.getValueType();
3422 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3423 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3425 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3426 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3427 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3428 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3431 case TargetLowering::Expand:
3432 Result = ExpandBSWAP(Tmp1);
3440 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3441 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3442 case TargetLowering::Custom:
3443 case TargetLowering::Legal:
3444 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3445 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3446 TargetLowering::Custom) {
3447 Tmp1 = TLI.LowerOperation(Result, DAG);
3448 if (Tmp1.getNode()) {
3453 case TargetLowering::Promote: {
3454 MVT OVT = Tmp1.getValueType();
3455 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3457 // Zero extend the argument.
3458 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3459 // Perform the larger operation, then subtract if needed.
3460 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
3461 switch (Node->getOpcode()) {
3466 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3467 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
3468 DAG.getConstant(NVT.getSizeInBits(), NVT),
3470 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3471 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3474 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3475 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3476 DAG.getConstant(NVT.getSizeInBits() -
3477 OVT.getSizeInBits(), NVT));
3482 case TargetLowering::Expand:
3483 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
3503 case ISD::FNEARBYINT:
3504 Tmp1 = LegalizeOp(Node->getOperand(0));
3505 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3506 case TargetLowering::Promote:
3507 case TargetLowering::Custom:
3510 case TargetLowering::Legal:
3511 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3513 Tmp1 = TLI.LowerOperation(Result, DAG);
3514 if (Tmp1.getNode()) Result = Tmp1;
3517 case TargetLowering::Expand:
3518 switch (Node->getOpcode()) {
3519 default: assert(0 && "Unreachable!");
3521 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3522 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3523 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
3526 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3527 MVT VT = Node->getValueType(0);
3528 Tmp2 = DAG.getConstantFP(0.0, VT);
3529 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
3531 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
3532 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
3547 case ISD::FNEARBYINT: {
3548 MVT VT = Node->getValueType(0);
3550 // Expand unsupported unary vector operators by unrolling them.
3551 if (VT.isVector()) {
3552 Result = LegalizeOp(UnrollVectorOp(Op));
3556 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3557 switch(Node->getOpcode()) {
3559 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3560 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
3563 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
3564 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
3567 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
3568 RTLIB::COS_F80, RTLIB::COS_PPCF128);
3571 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
3572 RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
3575 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3576 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
3579 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3580 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
3583 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
3584 RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
3587 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3588 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
3591 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3592 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
3595 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3596 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128);
3599 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3600 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128);
3603 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64,
3604 RTLIB::RINT_F80, RTLIB::RINT_PPCF128);
3606 case ISD::FNEARBYINT:
3607 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
3608 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
3611 default: assert(0 && "Unreachable!");
3614 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3622 MVT VT = Node->getValueType(0);
3624 // Expand unsupported unary vector operators by unrolling them.
3625 if (VT.isVector()) {
3626 Result = LegalizeOp(UnrollVectorOp(Op));
3630 // We always lower FPOWI into a libcall. No target support for it yet.
3631 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
3632 RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
3634 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3637 case ISD::BIT_CONVERT:
3638 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3639 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3640 Node->getValueType(0));
3641 } else if (Op.getOperand(0).getValueType().isVector()) {
3642 // The input has to be a vector type, we have to either scalarize it, pack
3643 // it, or convert it based on whether the input vector type is legal.
3644 SDNode *InVal = Node->getOperand(0).getNode();
3645 int InIx = Node->getOperand(0).getResNo();
3646 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
3647 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
3649 // Figure out if there is a simple type corresponding to this Vector
3650 // type. If so, convert to the vector type.
3651 MVT TVT = MVT::getVectorVT(EVT, NumElems);
3652 if (TLI.isTypeLegal(TVT)) {
3653 // Turn this into a bit convert of the vector input.
3654 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3655 LegalizeOp(Node->getOperand(0)));
3657 } else if (NumElems == 1) {
3658 // Turn this into a bit convert of the scalar input.
3659 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3660 ScalarizeVectorOp(Node->getOperand(0)));
3663 // FIXME: UNIMP! Store then reload
3664 assert(0 && "Cast from unsupported vector type not implemented yet!");
3667 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3668 Node->getOperand(0).getValueType())) {
3669 default: assert(0 && "Unknown operation action!");
3670 case TargetLowering::Expand:
3671 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3672 Node->getValueType(0));
3674 case TargetLowering::Legal:
3675 Tmp1 = LegalizeOp(Node->getOperand(0));
3676 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3682 // Conversion operators. The source and destination have different types.
3683 case ISD::SINT_TO_FP:
3684 case ISD::UINT_TO_FP: {
3685 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
3686 Result = LegalizeINT_TO_FP(Result, isSigned,
3687 Node->getValueType(0), Node->getOperand(0));
3691 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3693 Tmp1 = LegalizeOp(Node->getOperand(0));
3694 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3697 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3699 // Since the result is legal, we should just be able to truncate the low
3700 // part of the source.
3701 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
3704 Result = PromoteOp(Node->getOperand(0));
3705 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
3710 case ISD::FP_TO_SINT:
3711 case ISD::FP_TO_UINT:
3712 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3714 Tmp1 = LegalizeOp(Node->getOperand(0));
3716 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
3717 default: assert(0 && "Unknown operation action!");
3718 case TargetLowering::Custom:
3721 case TargetLowering::Legal:
3722 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3724 Tmp1 = TLI.LowerOperation(Result, DAG);
3725 if (Tmp1.getNode()) Result = Tmp1;
3728 case TargetLowering::Promote:
3729 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
3730 Node->getOpcode() == ISD::FP_TO_SINT);
3732 case TargetLowering::Expand:
3733 if (Node->getOpcode() == ISD::FP_TO_UINT) {
3734 SDValue True, False;
3735 MVT VT = Node->getOperand(0).getValueType();
3736 MVT NVT = Node->getValueType(0);
3737 const uint64_t zero[] = {0, 0};
3738 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero));
3739 APInt x = APInt::getSignBit(NVT.getSizeInBits());
3740 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
3741 Tmp2 = DAG.getConstantFP(apf, VT);
3742 Tmp3 = DAG.getSetCC(TLI.getSetCCResultType(Node->getOperand(0)),
3743 Node->getOperand(0), Tmp2, ISD::SETLT);
3744 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
3745 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
3746 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
3748 False = DAG.getNode(ISD::XOR, NVT, False,
3749 DAG.getConstant(x, NVT));
3750 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
3753 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
3759 MVT VT = Op.getValueType();
3760 MVT OVT = Node->getOperand(0).getValueType();
3761 // Convert ppcf128 to i32
3762 if (OVT == MVT::ppcf128 && VT == MVT::i32) {
3763 if (Node->getOpcode() == ISD::FP_TO_SINT) {
3764 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128,
3765 Node->getOperand(0), DAG.getValueType(MVT::f64));
3766 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result,
3767 DAG.getIntPtrConstant(1));
3768 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result);
3770 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
3771 APFloat apf = APFloat(APInt(128, 2, TwoE31));
3772 Tmp2 = DAG.getConstantFP(apf, OVT);
3773 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
3774 // FIXME: generated code sucks.
3775 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2,
3776 DAG.getNode(ISD::ADD, MVT::i32,
3777 DAG.getNode(ISD::FP_TO_SINT, VT,
3778 DAG.getNode(ISD::FSUB, OVT,
3779 Node->getOperand(0), Tmp2)),
3780 DAG.getConstant(0x80000000, MVT::i32)),
3781 DAG.getNode(ISD::FP_TO_SINT, VT,
3782 Node->getOperand(0)),
3783 DAG.getCondCode(ISD::SETGE));
3787 // Convert f32 / f64 to i32 / i64 / i128.
3788 RTLIB::Libcall LC = (Node->getOpcode() == ISD::FP_TO_SINT) ?
3789 RTLIB::getFPTOSINT(OVT, VT) : RTLIB::getFPTOUINT(OVT, VT);
3790 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpectd fp-to-int conversion!");
3792 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3796 Tmp1 = PromoteOp(Node->getOperand(0));
3797 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
3798 Result = LegalizeOp(Result);
3803 case ISD::FP_EXTEND: {
3804 MVT DstVT = Op.getValueType();
3805 MVT SrcVT = Op.getOperand(0).getValueType();
3806 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3807 // The only other way we can lower this is to turn it into a STORE,
3808 // LOAD pair, targetting a temporary location (a stack slot).
3809 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT);
3812 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3813 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3815 Tmp1 = LegalizeOp(Node->getOperand(0));
3816 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3819 Tmp1 = PromoteOp(Node->getOperand(0));
3820 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1);
3825 case ISD::FP_ROUND: {
3826 MVT DstVT = Op.getValueType();
3827 MVT SrcVT = Op.getOperand(0).getValueType();
3828 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3829 if (SrcVT == MVT::ppcf128) {
3831 ExpandOp(Node->getOperand(0), Lo, Result);
3832 // Round it the rest of the way (e.g. to f32) if needed.
3833 if (DstVT!=MVT::f64)
3834 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1));
3837 // The only other way we can lower this is to turn it into a STORE,
3838 // LOAD pair, targetting a temporary location (a stack slot).
3839 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT);
3842 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3843 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3845 Tmp1 = LegalizeOp(Node->getOperand(0));
3846 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3849 Tmp1 = PromoteOp(Node->getOperand(0));
3850 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1,
3851 Node->getOperand(1));
3856 case ISD::ANY_EXTEND:
3857 case ISD::ZERO_EXTEND:
3858 case ISD::SIGN_EXTEND:
3859 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3860 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3862 Tmp1 = LegalizeOp(Node->getOperand(0));
3863 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3864 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3865 TargetLowering::Custom) {
3866 Tmp1 = TLI.LowerOperation(Result, DAG);
3867 if (Tmp1.getNode()) Result = Tmp1;
3871 switch (Node->getOpcode()) {
3872 case ISD::ANY_EXTEND:
3873 Tmp1 = PromoteOp(Node->getOperand(0));
3874 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
3876 case ISD::ZERO_EXTEND:
3877 Result = PromoteOp(Node->getOperand(0));
3878 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3879 Result = DAG.getZeroExtendInReg(Result,
3880 Node->getOperand(0).getValueType());
3882 case ISD::SIGN_EXTEND:
3883 Result = PromoteOp(Node->getOperand(0));
3884 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3885 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3887 DAG.getValueType(Node->getOperand(0).getValueType()));
3892 case ISD::FP_ROUND_INREG:
3893 case ISD::SIGN_EXTEND_INREG: {
3894 Tmp1 = LegalizeOp(Node->getOperand(0));
3895 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3897 // If this operation is not supported, convert it to a shl/shr or load/store
3899 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
3900 default: assert(0 && "This action not supported for this op yet!");
3901 case TargetLowering::Legal:
3902 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3904 case TargetLowering::Expand:
3905 // If this is an integer extend and shifts are supported, do that.
3906 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
3907 // NOTE: we could fall back on load/store here too for targets without
3908 // SAR. However, it is doubtful that any exist.
3909 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() -
3910 ExtraVT.getSizeInBits();
3911 SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
3912 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
3913 Node->getOperand(0), ShiftCst);
3914 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
3916 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
3917 // The only way we can lower this is to turn it into a TRUNCSTORE,
3918 // EXTLOAD pair, targetting a temporary location (a stack slot).
3920 // NOTE: there is a choice here between constantly creating new stack
3921 // slots and always reusing the same one. We currently always create
3922 // new ones, as reuse may inhibit scheduling.
3923 Result = EmitStackConvert(Node->getOperand(0), ExtraVT,
3924 Node->getValueType(0));
3926 assert(0 && "Unknown op");
3932 case ISD::TRAMPOLINE: {
3934 for (unsigned i = 0; i != 6; ++i)
3935 Ops[i] = LegalizeOp(Node->getOperand(i));
3936 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
3937 // The only option for this node is to custom lower it.
3938 Result = TLI.LowerOperation(Result, DAG);
3939 assert(Result.getNode() && "Should always custom lower!");
3941 // Since trampoline produces two values, make sure to remember that we
3942 // legalized both of them.
3943 Tmp1 = LegalizeOp(Result.getValue(1));
3944 Result = LegalizeOp(Result);
3945 AddLegalizedOperand(SDValue(Node, 0), Result);
3946 AddLegalizedOperand(SDValue(Node, 1), Tmp1);
3947 return Op.getResNo() ? Tmp1 : Result;
3949 case ISD::FLT_ROUNDS_: {
3950 MVT VT = Node->getValueType(0);
3951 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
3952 default: assert(0 && "This action not supported for this op yet!");
3953 case TargetLowering::Custom:
3954 Result = TLI.LowerOperation(Op, DAG);
3955 if (Result.getNode()) break;
3957 case TargetLowering::Legal:
3958 // If this operation is not supported, lower it to constant 1
3959 Result = DAG.getConstant(1, VT);
3965 MVT VT = Node->getValueType(0);
3966 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
3967 default: assert(0 && "This action not supported for this op yet!");
3968 case TargetLowering::Legal:
3969 Tmp1 = LegalizeOp(Node->getOperand(0));
3970 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3972 case TargetLowering::Custom:
3973 Result = TLI.LowerOperation(Op, DAG);
3974 if (Result.getNode()) break;
3976 case TargetLowering::Expand:
3977 // If this operation is not supported, lower it to 'abort()' call
3978 Tmp1 = LegalizeOp(Node->getOperand(0));
3979 TargetLowering::ArgListTy Args;
3980 std::pair<SDValue,SDValue> CallResult =
3981 TLI.LowerCallTo(Tmp1, Type::VoidTy,
3982 false, false, false, false, CallingConv::C, false,
3983 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
3985 Result = CallResult.second;
3992 assert(Result.getValueType() == Op.getValueType() &&
3993 "Bad legalization!");
3995 // Make sure that the generated code is itself legal.
3997 Result = LegalizeOp(Result);
3999 // Note that LegalizeOp may be reentered even from single-use nodes, which
4000 // means that we always must cache transformed nodes.
4001 AddLegalizedOperand(Op, Result);
4005 /// PromoteOp - Given an operation that produces a value in an invalid type,
4006 /// promote it to compute the value into a larger type. The produced value will
4007 /// have the correct bits for the low portion of the register, but no guarantee
4008 /// is made about the top bits: it may be zero, sign-extended, or garbage.
4009 SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) {
4010 MVT VT = Op.getValueType();
4011 MVT NVT = TLI.getTypeToTransformTo(VT);
4012 assert(getTypeAction(VT) == Promote &&
4013 "Caller should expand or legalize operands that are not promotable!");
4014 assert(NVT.bitsGT(VT) && NVT.isInteger() == VT.isInteger() &&
4015 "Cannot promote to smaller type!");
4017 SDValue Tmp1, Tmp2, Tmp3;
4019 SDNode *Node = Op.getNode();
4021 DenseMap<SDValue, SDValue>::iterator I = PromotedNodes.find(Op);
4022 if (I != PromotedNodes.end()) return I->second;
4024 switch (Node->getOpcode()) {
4025 case ISD::CopyFromReg:
4026 assert(0 && "CopyFromReg must be legal!");
4029 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
4031 assert(0 && "Do not know how to promote this operator!");
4034 Result = DAG.getNode(ISD::UNDEF, NVT);
4038 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
4040 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
4041 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
4043 case ISD::ConstantFP:
4044 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
4045 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
4049 assert(isTypeLegal(TLI.getSetCCResultType(Node->getOperand(0)))
4050 && "SetCC type is not legal??");
4051 Result = DAG.getNode(ISD::SETCC,
4052 TLI.getSetCCResultType(Node->getOperand(0)),
4053 Node->getOperand(0), Node->getOperand(1),
4054 Node->getOperand(2));
4058 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4060 Result = LegalizeOp(Node->getOperand(0));
4061 assert(Result.getValueType().bitsGE(NVT) &&
4062 "This truncation doesn't make sense!");
4063 if (Result.getValueType().bitsGT(NVT)) // Truncate to NVT instead of VT
4064 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
4067 // The truncation is not required, because we don't guarantee anything
4068 // about high bits anyway.
4069 Result = PromoteOp(Node->getOperand(0));
4072 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4073 // Truncate the low part of the expanded value to the result type
4074 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
4077 case ISD::SIGN_EXTEND:
4078 case ISD::ZERO_EXTEND:
4079 case ISD::ANY_EXTEND:
4080 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4081 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
4083 // Input is legal? Just do extend all the way to the larger type.
4084 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4087 // Promote the reg if it's smaller.
4088 Result = PromoteOp(Node->getOperand(0));
4089 // The high bits are not guaranteed to be anything. Insert an extend.
4090 if (Node->getOpcode() == ISD::SIGN_EXTEND)
4091 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4092 DAG.getValueType(Node->getOperand(0).getValueType()));
4093 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
4094 Result = DAG.getZeroExtendInReg(Result,
4095 Node->getOperand(0).getValueType());
4099 case ISD::BIT_CONVERT:
4100 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
4101 Node->getValueType(0));
4102 Result = PromoteOp(Result);
4105 case ISD::FP_EXTEND:
4106 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
4108 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4109 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
4110 case Promote: assert(0 && "Unreachable with 2 FP types!");
4112 if (Node->getConstantOperandVal(1) == 0) {
4113 // Input is legal? Do an FP_ROUND_INREG.
4114 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
4115 DAG.getValueType(VT));
4117 // Just remove the truncate, it isn't affecting the value.
4118 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0),
4119 Node->getOperand(1));
4124 case ISD::SINT_TO_FP:
4125 case ISD::UINT_TO_FP:
4126 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4128 // No extra round required here.
4129 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4133 Result = PromoteOp(Node->getOperand(0));
4134 if (Node->getOpcode() == ISD::SINT_TO_FP)
4135 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
4137 DAG.getValueType(Node->getOperand(0).getValueType()));
4139 Result = DAG.getZeroExtendInReg(Result,
4140 Node->getOperand(0).getValueType());
4141 // No extra round required here.
4142 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
4145 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
4146 Node->getOperand(0));
4147 // Round if we cannot tolerate excess precision.
4148 if (NoExcessFPPrecision)
4149 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4150 DAG.getValueType(VT));
4155 case ISD::SIGN_EXTEND_INREG:
4156 Result = PromoteOp(Node->getOperand(0));
4157 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4158 Node->getOperand(1));
4160 case ISD::FP_TO_SINT:
4161 case ISD::FP_TO_UINT:
4162 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4165 Tmp1 = Node->getOperand(0);
4168 // The input result is prerounded, so we don't have to do anything
4170 Tmp1 = PromoteOp(Node->getOperand(0));
4173 // If we're promoting a UINT to a larger size, check to see if the new node
4174 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
4175 // we can use that instead. This allows us to generate better code for
4176 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
4177 // legal, such as PowerPC.
4178 if (Node->getOpcode() == ISD::FP_TO_UINT &&
4179 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
4180 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
4181 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
4182 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
4184 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4190 Tmp1 = PromoteOp(Node->getOperand(0));
4191 assert(Tmp1.getValueType() == NVT);
4192 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4193 // NOTE: we do not have to do any extra rounding here for
4194 // NoExcessFPPrecision, because we know the input will have the appropriate
4195 // precision, and these operations don't modify precision at all.
4210 case ISD::FNEARBYINT:
4211 Tmp1 = PromoteOp(Node->getOperand(0));
4212 assert(Tmp1.getValueType() == NVT);
4213 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4214 if (NoExcessFPPrecision)
4215 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4216 DAG.getValueType(VT));
4221 // Promote f32 pow(i) to f64 pow(i). Note that this could insert a libcall
4222 // directly as well, which may be better.
4223 Tmp1 = PromoteOp(Node->getOperand(0));
4224 Tmp2 = Node->getOperand(1);
4225 if (Node->getOpcode() == ISD::FPOW)
4226 Tmp2 = PromoteOp(Tmp2);
4227 assert(Tmp1.getValueType() == NVT);
4228 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4229 if (NoExcessFPPrecision)
4230 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4231 DAG.getValueType(VT));
4235 case ISD::ATOMIC_CMP_SWAP_8:
4236 case ISD::ATOMIC_CMP_SWAP_16:
4237 case ISD::ATOMIC_CMP_SWAP_32:
4238 case ISD::ATOMIC_CMP_SWAP_64: {
4239 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4240 Tmp2 = PromoteOp(Node->getOperand(2));
4241 Tmp3 = PromoteOp(Node->getOperand(3));
4242 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(),
4243 AtomNode->getBasePtr(), Tmp2, Tmp3,
4244 AtomNode->getSrcValue(),
4245 AtomNode->getAlignment());
4246 // Remember that we legalized the chain.
4247 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4250 case ISD::ATOMIC_LOAD_ADD_8:
4251 case ISD::ATOMIC_LOAD_SUB_8:
4252 case ISD::ATOMIC_LOAD_AND_8:
4253 case ISD::ATOMIC_LOAD_OR_8:
4254 case ISD::ATOMIC_LOAD_XOR_8:
4255 case ISD::ATOMIC_LOAD_NAND_8:
4256 case ISD::ATOMIC_LOAD_MIN_8:
4257 case ISD::ATOMIC_LOAD_MAX_8:
4258 case ISD::ATOMIC_LOAD_UMIN_8:
4259 case ISD::ATOMIC_LOAD_UMAX_8:
4260 case ISD::ATOMIC_SWAP_8:
4261 case ISD::ATOMIC_LOAD_ADD_16:
4262 case ISD::ATOMIC_LOAD_SUB_16:
4263 case ISD::ATOMIC_LOAD_AND_16:
4264 case ISD::ATOMIC_LOAD_OR_16:
4265 case ISD::ATOMIC_LOAD_XOR_16:
4266 case ISD::ATOMIC_LOAD_NAND_16:
4267 case ISD::ATOMIC_LOAD_MIN_16:
4268 case ISD::ATOMIC_LOAD_MAX_16:
4269 case ISD::ATOMIC_LOAD_UMIN_16:
4270 case ISD::ATOMIC_LOAD_UMAX_16:
4271 case ISD::ATOMIC_SWAP_16:
4272 case ISD::ATOMIC_LOAD_ADD_32:
4273 case ISD::ATOMIC_LOAD_SUB_32:
4274 case ISD::ATOMIC_LOAD_AND_32:
4275 case ISD::ATOMIC_LOAD_OR_32:
4276 case ISD::ATOMIC_LOAD_XOR_32:
4277 case ISD::ATOMIC_LOAD_NAND_32:
4278 case ISD::ATOMIC_LOAD_MIN_32:
4279 case ISD::ATOMIC_LOAD_MAX_32:
4280 case ISD::ATOMIC_LOAD_UMIN_32:
4281 case ISD::ATOMIC_LOAD_UMAX_32:
4282 case ISD::ATOMIC_SWAP_32:
4283 case ISD::ATOMIC_LOAD_ADD_64:
4284 case ISD::ATOMIC_LOAD_SUB_64:
4285 case ISD::ATOMIC_LOAD_AND_64:
4286 case ISD::ATOMIC_LOAD_OR_64:
4287 case ISD::ATOMIC_LOAD_XOR_64:
4288 case ISD::ATOMIC_LOAD_NAND_64:
4289 case ISD::ATOMIC_LOAD_MIN_64:
4290 case ISD::ATOMIC_LOAD_MAX_64:
4291 case ISD::ATOMIC_LOAD_UMIN_64:
4292 case ISD::ATOMIC_LOAD_UMAX_64:
4293 case ISD::ATOMIC_SWAP_64: {
4294 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4295 Tmp2 = PromoteOp(Node->getOperand(2));
4296 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(),
4297 AtomNode->getBasePtr(), Tmp2,
4298 AtomNode->getSrcValue(),
4299 AtomNode->getAlignment());
4300 // Remember that we legalized the chain.
4301 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4311 // The input may have strange things in the top bits of the registers, but
4312 // these operations don't care. They may have weird bits going out, but
4313 // that too is okay if they are integer operations.
4314 Tmp1 = PromoteOp(Node->getOperand(0));
4315 Tmp2 = PromoteOp(Node->getOperand(1));
4316 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4317 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4322 Tmp1 = PromoteOp(Node->getOperand(0));
4323 Tmp2 = PromoteOp(Node->getOperand(1));
4324 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4325 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4327 // Floating point operations will give excess precision that we may not be
4328 // able to tolerate. If we DO allow excess precision, just leave it,
4329 // otherwise excise it.
4330 // FIXME: Why would we need to round FP ops more than integer ones?
4331 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
4332 if (NoExcessFPPrecision)
4333 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4334 DAG.getValueType(VT));
4339 // These operators require that their input be sign extended.
4340 Tmp1 = PromoteOp(Node->getOperand(0));
4341 Tmp2 = PromoteOp(Node->getOperand(1));
4342 if (NVT.isInteger()) {
4343 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4344 DAG.getValueType(VT));
4345 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4346 DAG.getValueType(VT));
4348 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4350 // Perform FP_ROUND: this is probably overly pessimistic.
4351 if (NVT.isFloatingPoint() && NoExcessFPPrecision)
4352 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4353 DAG.getValueType(VT));
4357 case ISD::FCOPYSIGN:
4358 // These operators require that their input be fp extended.
4359 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4360 case Expand: assert(0 && "not implemented");
4361 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break;
4362 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break;
4364 switch (getTypeAction(Node->getOperand(1).getValueType())) {
4365 case Expand: assert(0 && "not implemented");
4366 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
4367 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
4369 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4371 // Perform FP_ROUND: this is probably overly pessimistic.
4372 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
4373 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4374 DAG.getValueType(VT));
4379 // These operators require that their input be zero extended.
4380 Tmp1 = PromoteOp(Node->getOperand(0));
4381 Tmp2 = PromoteOp(Node->getOperand(1));
4382 assert(NVT.isInteger() && "Operators don't apply to FP!");
4383 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4384 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4385 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4389 Tmp1 = PromoteOp(Node->getOperand(0));
4390 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
4393 // The input value must be properly sign extended.
4394 Tmp1 = PromoteOp(Node->getOperand(0));
4395 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4396 DAG.getValueType(VT));
4397 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
4400 // The input value must be properly zero extended.
4401 Tmp1 = PromoteOp(Node->getOperand(0));
4402 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4403 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
4407 Tmp1 = Node->getOperand(0); // Get the chain.
4408 Tmp2 = Node->getOperand(1); // Get the pointer.
4409 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
4410 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
4411 Result = TLI.LowerOperation(Tmp3, DAG);
4413 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
4414 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
4415 // Increment the pointer, VAList, to the next vaarg
4416 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
4417 DAG.getConstant(VT.getSizeInBits()/8,
4418 TLI.getPointerTy()));
4419 // Store the incremented VAList to the legalized pointer
4420 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
4421 // Load the actual argument out of the pointer VAList
4422 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
4424 // Remember that we legalized the chain.
4425 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4429 LoadSDNode *LD = cast<LoadSDNode>(Node);
4430 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
4431 ? ISD::EXTLOAD : LD->getExtensionType();
4432 Result = DAG.getExtLoad(ExtType, NVT,
4433 LD->getChain(), LD->getBasePtr(),
4434 LD->getSrcValue(), LD->getSrcValueOffset(),
4437 LD->getAlignment());
4438 // Remember that we legalized the chain.
4439 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4443 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
4444 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
4446 MVT VT2 = Tmp2.getValueType();
4447 assert(VT2 == Tmp3.getValueType()
4448 && "PromoteOp SELECT: Operands 2 and 3 ValueTypes don't match");
4449 // Ensure that the resulting node is at least the same size as the operands'
4450 // value types, because we cannot assume that TLI.getSetCCValueType() is
4452 Result = DAG.getNode(ISD::SELECT, VT2, Node->getOperand(0), Tmp2, Tmp3);
4455 case ISD::SELECT_CC:
4456 Tmp2 = PromoteOp(Node->getOperand(2)); // True
4457 Tmp3 = PromoteOp(Node->getOperand(3)); // False
4458 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4459 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
4462 Tmp1 = Node->getOperand(0);
4463 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
4464 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
4465 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
4466 DAG.getConstant(NVT.getSizeInBits() -
4468 TLI.getShiftAmountTy()));
4473 // Zero extend the argument
4474 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4475 // Perform the larger operation, then subtract if needed.
4476 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4477 switch(Node->getOpcode()) {
4482 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
4483 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
4484 DAG.getConstant(NVT.getSizeInBits(), NVT),
4486 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
4487 DAG.getConstant(VT.getSizeInBits(), NVT), Tmp1);
4490 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4491 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
4492 DAG.getConstant(NVT.getSizeInBits() -
4493 VT.getSizeInBits(), NVT));
4497 case ISD::EXTRACT_SUBVECTOR:
4498 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
4500 case ISD::EXTRACT_VECTOR_ELT:
4501 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
4505 assert(Result.getNode() && "Didn't set a result!");
4507 // Make sure the result is itself legal.
4508 Result = LegalizeOp(Result);
4510 // Remember that we promoted this!
4511 AddPromotedOperand(Op, Result);
4515 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
4516 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
4517 /// based on the vector type. The return type of this matches the element type
4518 /// of the vector, which may not be legal for the target.
4519 SDValue SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDValue Op) {
4520 // We know that operand #0 is the Vec vector. If the index is a constant
4521 // or if the invec is a supported hardware type, we can use it. Otherwise,
4522 // lower to a store then an indexed load.
4523 SDValue Vec = Op.getOperand(0);
4524 SDValue Idx = Op.getOperand(1);
4526 MVT TVT = Vec.getValueType();
4527 unsigned NumElems = TVT.getVectorNumElements();
4529 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
4530 default: assert(0 && "This action is not supported yet!");
4531 case TargetLowering::Custom: {
4532 Vec = LegalizeOp(Vec);
4533 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4534 SDValue Tmp3 = TLI.LowerOperation(Op, DAG);
4539 case TargetLowering::Legal:
4540 if (isTypeLegal(TVT)) {
4541 Vec = LegalizeOp(Vec);
4542 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4546 case TargetLowering::Expand:
4550 if (NumElems == 1) {
4551 // This must be an access of the only element. Return it.
4552 Op = ScalarizeVectorOp(Vec);
4553 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
4554 unsigned NumLoElts = 1 << Log2_32(NumElems-1);
4555 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4557 SplitVectorOp(Vec, Lo, Hi);
4558 if (CIdx->getZExtValue() < NumLoElts) {
4562 Idx = DAG.getConstant(CIdx->getZExtValue() - NumLoElts,
4563 Idx.getValueType());
4566 // It's now an extract from the appropriate high or low part. Recurse.
4567 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4568 Op = ExpandEXTRACT_VECTOR_ELT(Op);
4570 // Store the value to a temporary stack slot, then LOAD the scalar
4571 // element back out.
4572 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
4573 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
4575 // Add the offset to the index.
4576 unsigned EltSize = Op.getValueType().getSizeInBits()/8;
4577 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
4578 DAG.getConstant(EltSize, Idx.getValueType()));
4580 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
4581 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx);
4583 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
4585 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
4587 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
4592 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
4593 /// we assume the operation can be split if it is not already legal.
4594 SDValue SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDValue Op) {
4595 // We know that operand #0 is the Vec vector. For now we assume the index
4596 // is a constant and that the extracted result is a supported hardware type.
4597 SDValue Vec = Op.getOperand(0);
4598 SDValue Idx = LegalizeOp(Op.getOperand(1));
4600 unsigned NumElems = Vec.getValueType().getVectorNumElements();
4602 if (NumElems == Op.getValueType().getVectorNumElements()) {
4603 // This must be an access of the desired vector length. Return it.
4607 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4609 SplitVectorOp(Vec, Lo, Hi);
4610 if (CIdx->getZExtValue() < NumElems/2) {
4614 Idx = DAG.getConstant(CIdx->getZExtValue() - NumElems/2,
4615 Idx.getValueType());
4618 // It's now an extract from the appropriate high or low part. Recurse.
4619 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4620 return ExpandEXTRACT_SUBVECTOR(Op);
4623 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
4624 /// with condition CC on the current target. This usually involves legalizing
4625 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
4626 /// there may be no choice but to create a new SetCC node to represent the
4627 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
4628 /// LHS, and the SDValue returned in RHS has a nil SDNode value.
4629 void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS,
4632 SDValue Tmp1, Tmp2, Tmp3, Result;
4634 switch (getTypeAction(LHS.getValueType())) {
4636 Tmp1 = LegalizeOp(LHS); // LHS
4637 Tmp2 = LegalizeOp(RHS); // RHS
4640 Tmp1 = PromoteOp(LHS); // LHS
4641 Tmp2 = PromoteOp(RHS); // RHS
4643 // If this is an FP compare, the operands have already been extended.
4644 if (LHS.getValueType().isInteger()) {
4645 MVT VT = LHS.getValueType();
4646 MVT NVT = TLI.getTypeToTransformTo(VT);
4648 // Otherwise, we have to insert explicit sign or zero extends. Note
4649 // that we could insert sign extends for ALL conditions, but zero extend
4650 // is cheaper on many machines (an AND instead of two shifts), so prefer
4652 switch (cast<CondCodeSDNode>(CC)->get()) {
4653 default: assert(0 && "Unknown integer comparison!");
4660 // ALL of these operations will work if we either sign or zero extend
4661 // the operands (including the unsigned comparisons!). Zero extend is
4662 // usually a simpler/cheaper operation, so prefer it.
4663 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4664 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4670 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4671 DAG.getValueType(VT));
4672 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4673 DAG.getValueType(VT));
4674 Tmp1 = LegalizeOp(Tmp1); // Relegalize new nodes.
4675 Tmp2 = LegalizeOp(Tmp2); // Relegalize new nodes.
4681 MVT VT = LHS.getValueType();
4682 if (VT == MVT::f32 || VT == MVT::f64) {
4683 // Expand into one or more soft-fp libcall(s).
4684 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
4685 switch (cast<CondCodeSDNode>(CC)->get()) {
4688 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4692 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
4696 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4700 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4704 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4708 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4711 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4714 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
4717 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4718 switch (cast<CondCodeSDNode>(CC)->get()) {
4720 // SETONE = SETOLT | SETOGT
4721 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4724 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4727 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4730 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4733 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4736 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4738 default: assert(0 && "Unsupported FP setcc!");
4743 SDValue Ops[2] = { LHS, RHS };
4744 Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2).getNode(),
4745 false /*sign irrelevant*/, Dummy);
4746 Tmp2 = DAG.getConstant(0, MVT::i32);
4747 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
4748 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
4749 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
4751 LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2).getNode(),
4752 false /*sign irrelevant*/, Dummy);
4753 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, Tmp2,
4754 DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
4755 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4758 LHS = LegalizeOp(Tmp1);
4763 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
4764 ExpandOp(LHS, LHSLo, LHSHi);
4765 ExpandOp(RHS, RHSLo, RHSHi);
4766 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
4768 if (VT==MVT::ppcf128) {
4769 // FIXME: This generated code sucks. We want to generate
4770 // FCMPU crN, hi1, hi2
4772 // FCMPU crN, lo1, lo2
4773 // The following can be improved, but not that much.
4774 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4776 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, CCCode);
4777 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4778 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4780 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode);
4781 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4782 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
4791 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
4792 if (RHSCST->isAllOnesValue()) {
4793 // Comparison to -1.
4794 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
4799 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
4800 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
4801 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4802 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
4805 // If this is a comparison of the sign bit, just look at the top part.
4807 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
4808 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
4809 CST->isNullValue()) || // X < 0
4810 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
4811 CST->isAllOnesValue())) { // X > -1
4817 // FIXME: This generated code sucks.
4818 ISD::CondCode LowCC;
4820 default: assert(0 && "Unknown integer setcc!");
4822 case ISD::SETULT: LowCC = ISD::SETULT; break;
4824 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
4826 case ISD::SETULE: LowCC = ISD::SETULE; break;
4828 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
4831 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
4832 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
4833 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
4835 // NOTE: on targets without efficient SELECT of bools, we can always use
4836 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
4837 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
4838 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo,
4839 LowCC, false, DagCombineInfo);
4840 if (!Tmp1.getNode())
4841 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC);
4842 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4843 CCCode, false, DagCombineInfo);
4844 if (!Tmp2.getNode())
4845 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi,
4848 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
4849 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
4850 if ((Tmp1C && Tmp1C->isNullValue()) ||
4851 (Tmp2C && Tmp2C->isNullValue() &&
4852 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
4853 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
4854 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
4855 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
4856 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
4857 // low part is known false, returns high part.
4858 // For LE / GE, if high part is known false, ignore the low part.
4859 // For LT / GT, if high part is known true, ignore the low part.
4863 Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4864 ISD::SETEQ, false, DagCombineInfo);
4865 if (!Result.getNode())
4866 Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4868 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
4869 Result, Tmp1, Tmp2));
4880 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
4881 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
4882 /// a load from the stack slot to DestVT, extending it if needed.
4883 /// The resultant code need not be legal.
4884 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
4887 // Create the stack frame object.
4888 unsigned SrcAlign = TLI.getTargetData()->getPrefTypeAlignment(
4889 SrcOp.getValueType().getTypeForMVT());
4890 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
4892 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
4893 int SPFI = StackPtrFI->getIndex();
4895 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
4896 unsigned SlotSize = SlotVT.getSizeInBits();
4897 unsigned DestSize = DestVT.getSizeInBits();
4898 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(
4899 DestVT.getTypeForMVT());
4901 // Emit a store to the stack slot. Use a truncstore if the input value is
4902 // later than DestVT.
4905 if (SrcSize > SlotSize)
4906 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr,
4907 PseudoSourceValue::getFixedStack(SPFI), 0,
4908 SlotVT, false, SrcAlign);
4910 assert(SrcSize == SlotSize && "Invalid store");
4911 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr,
4912 PseudoSourceValue::getFixedStack(SPFI), 0,
4916 // Result is a load from the stack slot.
4917 if (SlotSize == DestSize)
4918 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0, false, DestAlign);
4920 assert(SlotSize < DestSize && "Unknown extension!");
4921 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT,
4925 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
4926 // Create a vector sized/aligned stack slot, store the value to element #0,
4927 // then load the whole vector back out.
4928 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
4930 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
4931 int SPFI = StackPtrFI->getIndex();
4933 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
4934 PseudoSourceValue::getFixedStack(SPFI), 0);
4935 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,
4936 PseudoSourceValue::getFixedStack(SPFI), 0);
4940 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
4941 /// support the operation, but do support the resultant vector type.
4942 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
4944 // If the only non-undef value is the low element, turn this into a
4945 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
4946 unsigned NumElems = Node->getNumOperands();
4947 bool isOnlyLowElement = true;
4948 SDValue SplatValue = Node->getOperand(0);
4950 // FIXME: it would be far nicer to change this into map<SDValue,uint64_t>
4951 // and use a bitmask instead of a list of elements.
4952 std::map<SDValue, std::vector<unsigned> > Values;
4953 Values[SplatValue].push_back(0);
4954 bool isConstant = true;
4955 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
4956 SplatValue.getOpcode() != ISD::UNDEF)
4959 for (unsigned i = 1; i < NumElems; ++i) {
4960 SDValue V = Node->getOperand(i);
4961 Values[V].push_back(i);
4962 if (V.getOpcode() != ISD::UNDEF)
4963 isOnlyLowElement = false;
4964 if (SplatValue != V)
4965 SplatValue = SDValue(0,0);
4967 // If this isn't a constant element or an undef, we can't use a constant
4969 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
4970 V.getOpcode() != ISD::UNDEF)
4974 if (isOnlyLowElement) {
4975 // If the low element is an undef too, then this whole things is an undef.
4976 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
4977 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
4978 // Otherwise, turn this into a scalar_to_vector node.
4979 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4980 Node->getOperand(0));
4983 // If all elements are constants, create a load from the constant pool.
4985 MVT VT = Node->getValueType(0);
4986 std::vector<Constant*> CV;
4987 for (unsigned i = 0, e = NumElems; i != e; ++i) {
4988 if (ConstantFPSDNode *V =
4989 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
4990 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
4991 } else if (ConstantSDNode *V =
4992 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
4993 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
4995 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
4997 Node->getOperand(0).getValueType().getTypeForMVT();
4998 CV.push_back(UndefValue::get(OpNTy));
5001 Constant *CP = ConstantVector::get(CV);
5002 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
5003 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5004 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
5005 PseudoSourceValue::getConstantPool(), 0,
5009 if (SplatValue.getNode()) { // Splat of one value?
5010 // Build the shuffle constant vector: <0, 0, 0, 0>
5011 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
5012 SDValue Zero = DAG.getConstant(0, MaskVT.getVectorElementType());
5013 std::vector<SDValue> ZeroVec(NumElems, Zero);
5014 SDValue SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
5015 &ZeroVec[0], ZeroVec.size());
5017 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
5018 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
5019 // Get the splatted value into the low element of a vector register.
5021 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
5023 // Return shuffle(LowValVec, undef, <0,0,0,0>)
5024 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
5025 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
5030 // If there are only two unique elements, we may be able to turn this into a
5032 if (Values.size() == 2) {
5033 // Get the two values in deterministic order.
5034 SDValue Val1 = Node->getOperand(1);
5036 std::map<SDValue, std::vector<unsigned> >::iterator MI = Values.begin();
5037 if (MI->first != Val1)
5040 Val2 = (++MI)->first;
5042 // If Val1 is an undef, make sure end ends up as Val2, to ensure that our
5043 // vector shuffle has the undef vector on the RHS.
5044 if (Val1.getOpcode() == ISD::UNDEF)
5045 std::swap(Val1, Val2);
5047 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
5048 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
5049 MVT MaskEltVT = MaskVT.getVectorElementType();
5050 std::vector<SDValue> MaskVec(NumElems);
5052 // Set elements of the shuffle mask for Val1.
5053 std::vector<unsigned> &Val1Elts = Values[Val1];
5054 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i)
5055 MaskVec[Val1Elts[i]] = DAG.getConstant(0, MaskEltVT);
5057 // Set elements of the shuffle mask for Val2.
5058 std::vector<unsigned> &Val2Elts = Values[Val2];
5059 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i)
5060 if (Val2.getOpcode() != ISD::UNDEF)
5061 MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT);
5063 MaskVec[Val2Elts[i]] = DAG.getNode(ISD::UNDEF, MaskEltVT);
5065 SDValue ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
5066 &MaskVec[0], MaskVec.size());
5068 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it.
5069 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
5070 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
5071 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val1);
5072 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val2);
5073 SDValue Ops[] = { Val1, Val2, ShuffleMask };
5075 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
5076 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops, 3);
5080 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
5081 // aligned object on the stack, store each element into it, then load
5082 // the result as a vector.
5083 MVT VT = Node->getValueType(0);
5084 // Create the stack frame object.
5085 SDValue FIPtr = DAG.CreateStackTemporary(VT);
5087 // Emit a store of each element to the stack slot.
5088 SmallVector<SDValue, 8> Stores;
5089 unsigned TypeByteSize = Node->getOperand(0).getValueType().getSizeInBits()/8;
5090 // Store (in the right endianness) the elements to memory.
5091 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5092 // Ignore undef elements.
5093 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
5095 unsigned Offset = TypeByteSize*i;
5097 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
5098 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
5100 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
5105 if (!Stores.empty()) // Not all undef elements?
5106 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
5107 &Stores[0], Stores.size());
5109 StoreChain = DAG.getEntryNode();
5111 // Result is a load from the stack slot.
5112 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
5115 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
5116 SDValue Op, SDValue Amt,
5117 SDValue &Lo, SDValue &Hi) {
5118 // Expand the subcomponents.
5120 ExpandOp(Op, LHSL, LHSH);
5122 SDValue Ops[] = { LHSL, LHSH, Amt };
5123 MVT VT = LHSL.getValueType();
5124 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
5125 Hi = Lo.getValue(1);
5129 /// ExpandShift - Try to find a clever way to expand this shift operation out to
5130 /// smaller elements. If we can't find a way that is more efficient than a
5131 /// libcall on this target, return false. Otherwise, return true with the
5132 /// low-parts expanded into Lo and Hi.
5133 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op,SDValue Amt,
5134 SDValue &Lo, SDValue &Hi) {
5135 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
5136 "This is not a shift!");
5138 MVT NVT = TLI.getTypeToTransformTo(Op.getValueType());
5139 SDValue ShAmt = LegalizeOp(Amt);
5140 MVT ShTy = ShAmt.getValueType();
5141 unsigned ShBits = ShTy.getSizeInBits();
5142 unsigned VTBits = Op.getValueType().getSizeInBits();
5143 unsigned NVTBits = NVT.getSizeInBits();
5145 // Handle the case when Amt is an immediate.
5146 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.getNode())) {
5147 unsigned Cst = CN->getZExtValue();
5148 // Expand the incoming operand to be shifted, so that we have its parts
5150 ExpandOp(Op, InL, InH);
5154 Lo = DAG.getConstant(0, NVT);
5155 Hi = DAG.getConstant(0, NVT);
5156 } else if (Cst > NVTBits) {
5157 Lo = DAG.getConstant(0, NVT);
5158 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
5159 } else if (Cst == NVTBits) {
5160 Lo = DAG.getConstant(0, NVT);
5163 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
5164 Hi = DAG.getNode(ISD::OR, NVT,
5165 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
5166 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
5171 Lo = DAG.getConstant(0, NVT);
5172 Hi = DAG.getConstant(0, NVT);
5173 } else if (Cst > NVTBits) {
5174 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
5175 Hi = DAG.getConstant(0, NVT);
5176 } else if (Cst == NVTBits) {
5178 Hi = DAG.getConstant(0, NVT);
5180 Lo = DAG.getNode(ISD::OR, NVT,
5181 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5182 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5183 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
5188 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
5189 DAG.getConstant(NVTBits-1, ShTy));
5190 } else if (Cst > NVTBits) {
5191 Lo = DAG.getNode(ISD::SRA, NVT, InH,
5192 DAG.getConstant(Cst-NVTBits, ShTy));
5193 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5194 DAG.getConstant(NVTBits-1, ShTy));
5195 } else if (Cst == NVTBits) {
5197 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5198 DAG.getConstant(NVTBits-1, ShTy));
5200 Lo = DAG.getNode(ISD::OR, NVT,
5201 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5202 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5203 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
5209 // Okay, the shift amount isn't constant. However, if we can tell that it is
5210 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
5211 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
5212 APInt KnownZero, KnownOne;
5213 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
5215 // If we know that if any of the high bits of the shift amount are one, then
5216 // we can do this as a couple of simple shifts.
5217 if (KnownOne.intersects(Mask)) {
5218 // Mask out the high bit, which we know is set.
5219 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
5220 DAG.getConstant(~Mask, Amt.getValueType()));
5222 // Expand the incoming operand to be shifted, so that we have its parts
5224 ExpandOp(Op, InL, InH);
5227 Lo = DAG.getConstant(0, NVT); // Low part is zero.
5228 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
5231 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
5232 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
5235 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
5236 DAG.getConstant(NVTBits-1, Amt.getValueType()));
5237 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
5242 // If we know that the high bits of the shift amount are all zero, then we can
5243 // do this as a couple of simple shifts.
5244 if ((KnownZero & Mask) == Mask) {
5246 SDValue Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
5247 DAG.getConstant(NVTBits, Amt.getValueType()),
5250 // Expand the incoming operand to be shifted, so that we have its parts
5252 ExpandOp(Op, InL, InH);
5255 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
5256 Hi = DAG.getNode(ISD::OR, NVT,
5257 DAG.getNode(ISD::SHL, NVT, InH, Amt),
5258 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
5261 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
5262 Lo = DAG.getNode(ISD::OR, NVT,
5263 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5264 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5267 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
5268 Lo = DAG.getNode(ISD::OR, NVT,
5269 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5270 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5279 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
5280 // does not fit into a register, return the lo part and set the hi part to the
5281 // by-reg argument. If it does fit into a single register, return the result
5282 // and leave the Hi part unset.
5283 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
5284 bool isSigned, SDValue &Hi) {
5285 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
5286 // The input chain to this libcall is the entry node of the function.
5287 // Legalizing the call will automatically add the previous call to the
5289 SDValue InChain = DAG.getEntryNode();
5291 TargetLowering::ArgListTy Args;
5292 TargetLowering::ArgListEntry Entry;
5293 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5294 MVT ArgVT = Node->getOperand(i).getValueType();
5295 const Type *ArgTy = ArgVT.getTypeForMVT();
5296 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
5297 Entry.isSExt = isSigned;
5298 Entry.isZExt = !isSigned;
5299 Args.push_back(Entry);
5301 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
5302 TLI.getPointerTy());
5304 // Splice the libcall in wherever FindInputOutputChains tells us to.
5305 const Type *RetTy = Node->getValueType(0).getTypeForMVT();
5306 std::pair<SDValue,SDValue> CallInfo =
5307 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
5308 CallingConv::C, false, Callee, Args, DAG);
5310 // Legalize the call sequence, starting with the chain. This will advance
5311 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
5312 // was added by LowerCallTo (guaranteeing proper serialization of calls).
5313 LegalizeOp(CallInfo.second);
5315 switch (getTypeAction(CallInfo.first.getValueType())) {
5316 default: assert(0 && "Unknown thing");
5318 Result = CallInfo.first;
5321 ExpandOp(CallInfo.first, Result, Hi);
5327 /// LegalizeINT_TO_FP - Legalize a [US]INT_TO_FP operation.
5329 SDValue SelectionDAGLegalize::
5330 LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op) {
5331 bool isCustom = false;
5333 switch (getTypeAction(Op.getValueType())) {
5335 switch (TLI.getOperationAction(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5336 Op.getValueType())) {
5337 default: assert(0 && "Unknown operation action!");
5338 case TargetLowering::Custom:
5341 case TargetLowering::Legal:
5342 Tmp1 = LegalizeOp(Op);
5343 if (Result.getNode())
5344 Result = DAG.UpdateNodeOperands(Result, Tmp1);
5346 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5349 Tmp1 = TLI.LowerOperation(Result, DAG);
5350 if (Tmp1.getNode()) Result = Tmp1;
5353 case TargetLowering::Expand:
5354 Result = ExpandLegalINT_TO_FP(isSigned, LegalizeOp(Op), DestTy);
5356 case TargetLowering::Promote:
5357 Result = PromoteLegalINT_TO_FP(LegalizeOp(Op), DestTy, isSigned);
5362 Result = ExpandIntToFP(isSigned, DestTy, Op);
5365 Tmp1 = PromoteOp(Op);
5367 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
5368 Tmp1, DAG.getValueType(Op.getValueType()));
5370 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
5373 if (Result.getNode())
5374 Result = DAG.UpdateNodeOperands(Result, Tmp1);
5376 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5378 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
5384 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
5386 SDValue SelectionDAGLegalize::
5387 ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source) {
5388 MVT SourceVT = Source.getValueType();
5389 bool ExpandSource = getTypeAction(SourceVT) == Expand;
5391 // Expand unsupported int-to-fp vector casts by unrolling them.
5392 if (DestTy.isVector()) {
5394 return LegalizeOp(UnrollVectorOp(Source));
5395 MVT DestEltTy = DestTy.getVectorElementType();
5396 if (DestTy.getVectorNumElements() == 1) {
5397 SDValue Scalar = ScalarizeVectorOp(Source);
5398 SDValue Result = LegalizeINT_TO_FP(SDValue(), isSigned,
5400 return DAG.getNode(ISD::BUILD_VECTOR, DestTy, Result);
5403 SplitVectorOp(Source, Lo, Hi);
5404 MVT SplitDestTy = MVT::getVectorVT(DestEltTy,
5405 DestTy.getVectorNumElements() / 2);
5406 SDValue LoResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, Lo);
5407 SDValue HiResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, Hi);
5408 return LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, DestTy, LoResult,
5412 // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc.
5413 if (!isSigned && SourceVT != MVT::i32) {
5414 // The integer value loaded will be incorrectly if the 'sign bit' of the
5415 // incoming integer is set. To handle this, we dynamically test to see if
5416 // it is set, and, if so, add a fudge factor.
5420 ExpandOp(Source, Lo, Hi);
5421 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi);
5423 // The comparison for the sign bit will use the entire operand.
5427 // If this is unsigned, and not supported, first perform the conversion to
5428 // signed, then adjust the result if the sign bit is set.
5429 SDValue SignedConv = ExpandIntToFP(true, DestTy, Source);
5431 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
5432 DAG.getConstant(0, Hi.getValueType()),
5434 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5435 SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5436 SignSet, Four, Zero);
5437 uint64_t FF = 0x5f800000ULL;
5438 if (TLI.isLittleEndian()) FF <<= 32;
5439 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5441 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5442 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5443 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5444 Alignment = std::min(Alignment, 4u);
5446 if (DestTy == MVT::f32)
5447 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5448 PseudoSourceValue::getConstantPool(), 0,
5450 else if (DestTy.bitsGT(MVT::f32))
5451 // FIXME: Avoid the extend by construction the right constantpool?
5452 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
5454 PseudoSourceValue::getConstantPool(), 0,
5455 MVT::f32, false, Alignment);
5457 assert(0 && "Unexpected conversion");
5459 MVT SCVT = SignedConv.getValueType();
5460 if (SCVT != DestTy) {
5461 // Destination type needs to be expanded as well. The FADD now we are
5462 // constructing will be expanded into a libcall.
5463 if (SCVT.getSizeInBits() != DestTy.getSizeInBits()) {
5464 assert(SCVT.getSizeInBits() * 2 == DestTy.getSizeInBits());
5465 SignedConv = DAG.getNode(ISD::BUILD_PAIR, DestTy,
5466 SignedConv, SignedConv.getValue(1));
5468 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
5470 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
5473 // Check to see if the target has a custom way to lower this. If so, use it.
5474 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) {
5475 default: assert(0 && "This action not implemented for this operation!");
5476 case TargetLowering::Legal:
5477 case TargetLowering::Expand:
5478 break; // This case is handled below.
5479 case TargetLowering::Custom: {
5480 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
5483 return LegalizeOp(NV);
5484 break; // The target decided this was legal after all
5488 // Expand the source, then glue it back together for the call. We must expand
5489 // the source in case it is shared (this pass of legalize must traverse it).
5491 SDValue SrcLo, SrcHi;
5492 ExpandOp(Source, SrcLo, SrcHi);
5493 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, SrcLo, SrcHi);
5496 RTLIB::Libcall LC = isSigned ?
5497 RTLIB::getSINTTOFP(SourceVT, DestTy) :
5498 RTLIB::getUINTTOFP(SourceVT, DestTy);
5499 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unknown int value type");
5501 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
5503 SDValue Result = ExpandLibCall(LC, Source.getNode(), isSigned, HiPart);
5504 if (Result.getValueType() != DestTy && HiPart.getNode())
5505 Result = DAG.getNode(ISD::BUILD_PAIR, DestTy, Result, HiPart);
5509 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
5510 /// INT_TO_FP operation of the specified operand when the target requests that
5511 /// we expand it. At this point, we know that the result and operand types are
5512 /// legal for the target.
5513 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
5516 if (Op0.getValueType() == MVT::i32) {
5517 // simple 32-bit [signed|unsigned] integer to float/double expansion
5519 // Get the stack frame index of a 8 byte buffer.
5520 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
5522 // word offset constant for Hi/Lo address computation
5523 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
5524 // set up Hi and Lo (into buffer) address based on endian
5525 SDValue Hi = StackSlot;
5526 SDValue Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
5527 if (TLI.isLittleEndian())
5530 // if signed map to unsigned space
5533 // constant used to invert sign bit (signed to unsigned mapping)
5534 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
5535 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
5539 // store the lo of the constructed double - based on integer input
5540 SDValue Store1 = DAG.getStore(DAG.getEntryNode(),
5541 Op0Mapped, Lo, NULL, 0);
5542 // initial hi portion of constructed double
5543 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
5544 // store the hi of the constructed double - biased exponent
5545 SDValue Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
5546 // load the constructed double
5547 SDValue Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
5548 // FP constant to bias correct the final result
5549 SDValue Bias = DAG.getConstantFP(isSigned ?
5550 BitsToDouble(0x4330000080000000ULL)
5551 : BitsToDouble(0x4330000000000000ULL),
5553 // subtract the bias
5554 SDValue Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
5557 // handle final rounding
5558 if (DestVT == MVT::f64) {
5561 } else if (DestVT.bitsLT(MVT::f64)) {
5562 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub,
5563 DAG.getIntPtrConstant(0));
5564 } else if (DestVT.bitsGT(MVT::f64)) {
5565 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
5569 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
5570 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
5572 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Op0), Op0,
5573 DAG.getConstant(0, Op0.getValueType()),
5575 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5576 SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5577 SignSet, Four, Zero);
5579 // If the sign bit of the integer is set, the large number will be treated
5580 // as a negative number. To counteract this, the dynamic code adds an
5581 // offset depending on the data type.
5583 switch (Op0.getValueType().getSimpleVT()) {
5584 default: assert(0 && "Unsupported integer type!");
5585 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
5586 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
5587 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
5588 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
5590 if (TLI.isLittleEndian()) FF <<= 32;
5591 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5593 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5594 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5595 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5596 Alignment = std::min(Alignment, 4u);
5598 if (DestVT == MVT::f32)
5599 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5600 PseudoSourceValue::getConstantPool(), 0,
5604 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT,
5605 DAG.getEntryNode(), CPIdx,
5606 PseudoSourceValue::getConstantPool(), 0,
5607 MVT::f32, false, Alignment));
5610 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
5613 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
5614 /// *INT_TO_FP operation of the specified operand when the target requests that
5615 /// we promote it. At this point, we know that the result and operand types are
5616 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
5617 /// operation that takes a larger input.
5618 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
5621 // First step, figure out the appropriate *INT_TO_FP operation to use.
5622 MVT NewInTy = LegalOp.getValueType();
5624 unsigned OpToUse = 0;
5626 // Scan for the appropriate larger type to use.
5628 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
5629 assert(NewInTy.isInteger() && "Ran out of possibilities!");
5631 // If the target supports SINT_TO_FP of this type, use it.
5632 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
5634 case TargetLowering::Legal:
5635 if (!TLI.isTypeLegal(NewInTy))
5636 break; // Can't use this datatype.
5638 case TargetLowering::Custom:
5639 OpToUse = ISD::SINT_TO_FP;
5643 if (isSigned) continue;
5645 // If the target supports UINT_TO_FP of this type, use it.
5646 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
5648 case TargetLowering::Legal:
5649 if (!TLI.isTypeLegal(NewInTy))
5650 break; // Can't use this datatype.
5652 case TargetLowering::Custom:
5653 OpToUse = ISD::UINT_TO_FP;
5658 // Otherwise, try a larger type.
5661 // Okay, we found the operation and type to use. Zero extend our input to the
5662 // desired type then run the operation on it.
5663 return DAG.getNode(OpToUse, DestVT,
5664 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
5668 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
5669 /// FP_TO_*INT operation of the specified operand when the target requests that
5670 /// we promote it. At this point, we know that the result and operand types are
5671 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
5672 /// operation that returns a larger result.
5673 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
5676 // First step, figure out the appropriate FP_TO*INT operation to use.
5677 MVT NewOutTy = DestVT;
5679 unsigned OpToUse = 0;
5681 // Scan for the appropriate larger type to use.
5683 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1);
5684 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
5686 // If the target supports FP_TO_SINT returning this type, use it.
5687 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
5689 case TargetLowering::Legal:
5690 if (!TLI.isTypeLegal(NewOutTy))
5691 break; // Can't use this datatype.
5693 case TargetLowering::Custom:
5694 OpToUse = ISD::FP_TO_SINT;
5699 // If the target supports FP_TO_UINT of this type, use it.
5700 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
5702 case TargetLowering::Legal:
5703 if (!TLI.isTypeLegal(NewOutTy))
5704 break; // Can't use this datatype.
5706 case TargetLowering::Custom:
5707 OpToUse = ISD::FP_TO_UINT;
5712 // Otherwise, try a larger type.
5716 // Okay, we found the operation and type to use.
5717 SDValue Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp);
5719 // If the operation produces an invalid type, it must be custom lowered. Use
5720 // the target lowering hooks to expand it. Just keep the low part of the
5721 // expanded operation, we know that we're truncating anyway.
5722 if (getTypeAction(NewOutTy) == Expand) {
5723 Operation = SDValue(TLI.ReplaceNodeResults(Operation.getNode(), DAG), 0);
5724 assert(Operation.getNode() && "Didn't return anything");
5727 // Truncate the result of the extended FP_TO_*INT operation to the desired
5729 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation);
5732 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
5734 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op) {
5735 MVT VT = Op.getValueType();
5736 MVT SHVT = TLI.getShiftAmountTy();
5737 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
5738 switch (VT.getSimpleVT()) {
5739 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
5741 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5742 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5743 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
5745 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5746 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5747 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5748 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5749 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
5750 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
5751 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5752 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5753 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5755 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
5756 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
5757 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5758 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5759 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5760 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5761 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
5762 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
5763 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
5764 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
5765 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
5766 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
5767 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
5768 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
5769 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
5770 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
5771 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5772 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5773 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
5774 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5775 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
5779 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
5781 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op) {
5783 default: assert(0 && "Cannot expand this yet!");
5785 static const uint64_t mask[6] = {
5786 0x5555555555555555ULL, 0x3333333333333333ULL,
5787 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
5788 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
5790 MVT VT = Op.getValueType();
5791 MVT ShVT = TLI.getShiftAmountTy();
5792 unsigned len = VT.getSizeInBits();
5793 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5794 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
5795 SDValue Tmp2 = DAG.getConstant(mask[i], VT);
5796 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5797 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
5798 DAG.getNode(ISD::AND, VT,
5799 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
5804 // for now, we do this:
5805 // x = x | (x >> 1);
5806 // x = x | (x >> 2);
5808 // x = x | (x >>16);
5809 // x = x | (x >>32); // for 64-bit input
5810 // return popcount(~x);
5812 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
5813 MVT VT = Op.getValueType();
5814 MVT ShVT = TLI.getShiftAmountTy();
5815 unsigned len = VT.getSizeInBits();
5816 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5817 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5818 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
5820 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
5821 return DAG.getNode(ISD::CTPOP, VT, Op);
5824 // for now, we use: { return popcount(~x & (x - 1)); }
5825 // unless the target has ctlz but not ctpop, in which case we use:
5826 // { return 32 - nlz(~x & (x-1)); }
5827 // see also http://www.hackersdelight.org/HDcode/ntz.cc
5828 MVT VT = Op.getValueType();
5829 SDValue Tmp2 = DAG.getConstant(~0ULL, VT);
5830 SDValue Tmp3 = DAG.getNode(ISD::AND, VT,
5831 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
5832 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
5833 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
5834 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
5835 TLI.isOperationLegal(ISD::CTLZ, VT))
5836 return DAG.getNode(ISD::SUB, VT,
5837 DAG.getConstant(VT.getSizeInBits(), VT),
5838 DAG.getNode(ISD::CTLZ, VT, Tmp3));
5839 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
5844 /// ExpandOp - Expand the specified SDValue into its two component pieces
5845 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
5846 /// LegalizedNodes map is filled in for any results that are not expanded, the
5847 /// ExpandedNodes map is filled in for any results that are expanded, and the
5848 /// Lo/Hi values are returned.
5849 void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
5850 MVT VT = Op.getValueType();
5851 MVT NVT = TLI.getTypeToTransformTo(VT);
5852 SDNode *Node = Op.getNode();
5853 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
5854 assert(((NVT.isInteger() && NVT.bitsLT(VT)) || VT.isFloatingPoint() ||
5855 VT.isVector()) && "Cannot expand to FP value or to larger int value!");
5857 // See if we already expanded it.
5858 DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator I
5859 = ExpandedNodes.find(Op);
5860 if (I != ExpandedNodes.end()) {
5861 Lo = I->second.first;
5862 Hi = I->second.second;
5866 switch (Node->getOpcode()) {
5867 case ISD::CopyFromReg:
5868 assert(0 && "CopyFromReg must be legal!");
5869 case ISD::FP_ROUND_INREG:
5870 if (VT == MVT::ppcf128 &&
5871 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
5872 TargetLowering::Custom) {
5873 SDValue SrcLo, SrcHi, Src;
5874 ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
5875 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi);
5876 SDValue Result = TLI.LowerOperation(
5877 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG);
5878 assert(Result.getNode()->getOpcode() == ISD::BUILD_PAIR);
5879 Lo = Result.getNode()->getOperand(0);
5880 Hi = Result.getNode()->getOperand(1);
5886 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
5888 assert(0 && "Do not know how to expand this operator!");
5890 case ISD::EXTRACT_ELEMENT:
5891 ExpandOp(Node->getOperand(0), Lo, Hi);
5892 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
5893 return ExpandOp(Hi, Lo, Hi);
5894 return ExpandOp(Lo, Lo, Hi);
5895 case ISD::EXTRACT_VECTOR_ELT:
5896 assert(VT==MVT::i64 && "Do not know how to expand this operator!");
5897 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types.
5898 Lo = ExpandEXTRACT_VECTOR_ELT(Op);
5899 return ExpandOp(Lo, Lo, Hi);
5901 Lo = DAG.getNode(ISD::UNDEF, NVT);
5902 Hi = DAG.getNode(ISD::UNDEF, NVT);
5904 case ISD::Constant: {
5905 unsigned NVTBits = NVT.getSizeInBits();
5906 const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue();
5907 Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT);
5908 Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT);
5911 case ISD::ConstantFP: {
5912 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
5913 if (CFP->getValueType(0) == MVT::ppcf128) {
5914 APInt api = CFP->getValueAPF().bitcastToAPInt();
5915 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
5917 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
5921 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
5922 if (getTypeAction(Lo.getValueType()) == Expand)
5923 ExpandOp(Lo, Lo, Hi);
5926 case ISD::BUILD_PAIR:
5927 // Return the operands.
5928 Lo = Node->getOperand(0);
5929 Hi = Node->getOperand(1);
5932 case ISD::MERGE_VALUES:
5933 if (Node->getNumValues() == 1) {
5934 ExpandOp(Op.getOperand(0), Lo, Hi);
5937 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y)
5938 assert(Op.getResNo() == 0 && Node->getNumValues() == 2 &&
5939 Op.getValue(1).getValueType() == MVT::Other &&
5940 "unhandled MERGE_VALUES");
5941 ExpandOp(Op.getOperand(0), Lo, Hi);
5942 // Remember that we legalized the chain.
5943 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1)));
5946 case ISD::SIGN_EXTEND_INREG:
5947 ExpandOp(Node->getOperand(0), Lo, Hi);
5948 // sext_inreg the low part if needed.
5949 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
5951 // The high part gets the sign extension from the lo-part. This handles
5952 // things like sextinreg V:i64 from i8.
5953 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5954 DAG.getConstant(NVT.getSizeInBits()-1,
5955 TLI.getShiftAmountTy()));
5959 ExpandOp(Node->getOperand(0), Lo, Hi);
5960 SDValue TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
5961 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
5967 ExpandOp(Node->getOperand(0), Lo, Hi);
5968 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
5969 DAG.getNode(ISD::CTPOP, NVT, Lo),
5970 DAG.getNode(ISD::CTPOP, NVT, Hi));
5971 Hi = DAG.getConstant(0, NVT);
5975 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
5976 ExpandOp(Node->getOperand(0), Lo, Hi);
5977 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
5978 SDValue HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
5979 SDValue TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(HLZ), HLZ, BitsC,
5981 SDValue LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
5982 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
5984 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
5985 Hi = DAG.getConstant(0, NVT);
5990 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
5991 ExpandOp(Node->getOperand(0), Lo, Hi);
5992 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
5993 SDValue LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
5994 SDValue BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(LTZ), LTZ, BitsC,
5996 SDValue HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
5997 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
5999 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
6000 Hi = DAG.getConstant(0, NVT);
6005 SDValue Ch = Node->getOperand(0); // Legalize the chain.
6006 SDValue Ptr = Node->getOperand(1); // Legalize the pointer.
6007 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
6008 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
6010 // Remember that we legalized the chain.
6011 Hi = LegalizeOp(Hi);
6012 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
6013 if (TLI.isBigEndian())
6019 LoadSDNode *LD = cast<LoadSDNode>(Node);
6020 SDValue Ch = LD->getChain(); // Legalize the chain.
6021 SDValue Ptr = LD->getBasePtr(); // Legalize the pointer.
6022 ISD::LoadExtType ExtType = LD->getExtensionType();
6023 const Value *SV = LD->getSrcValue();
6024 int SVOffset = LD->getSrcValueOffset();
6025 unsigned Alignment = LD->getAlignment();
6026 bool isVolatile = LD->isVolatile();
6028 if (ExtType == ISD::NON_EXTLOAD) {
6029 Lo = DAG.getLoad(NVT, Ch, Ptr, SV, SVOffset,
6030 isVolatile, Alignment);
6031 if (VT == MVT::f32 || VT == MVT::f64) {
6032 // f32->i32 or f64->i64 one to one expansion.
6033 // Remember that we legalized the chain.
6034 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
6035 // Recursively expand the new load.
6036 if (getTypeAction(NVT) == Expand)
6037 ExpandOp(Lo, Lo, Hi);
6041 // Increment the pointer to the other half.
6042 unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8;
6043 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
6044 DAG.getIntPtrConstant(IncrementSize));
6045 SVOffset += IncrementSize;
6046 Alignment = MinAlign(Alignment, IncrementSize);
6047 Hi = DAG.getLoad(NVT, Ch, Ptr, SV, SVOffset,
6048 isVolatile, Alignment);
6050 // Build a factor node to remember that this load is independent of the
6052 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
6055 // Remember that we legalized the chain.
6056 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
6057 if (TLI.isBigEndian())
6060 MVT EVT = LD->getMemoryVT();
6062 if ((VT == MVT::f64 && EVT == MVT::f32) ||
6063 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
6064 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
6065 SDValue Load = DAG.getLoad(EVT, Ch, Ptr, SV,
6066 SVOffset, isVolatile, Alignment);
6067 // Remember that we legalized the chain.
6068 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Load.getValue(1)));
6069 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
6074 Lo = DAG.getLoad(NVT, Ch, Ptr, SV,
6075 SVOffset, isVolatile, Alignment);
6077 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, SV,
6078 SVOffset, EVT, isVolatile,
6081 // Remember that we legalized the chain.
6082 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
6084 if (ExtType == ISD::SEXTLOAD) {
6085 // The high part is obtained by SRA'ing all but one of the bits of the
6087 unsigned LoSize = Lo.getValueType().getSizeInBits();
6088 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6089 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6090 } else if (ExtType == ISD::ZEXTLOAD) {
6091 // The high part is just a zero.
6092 Hi = DAG.getConstant(0, NVT);
6093 } else /* if (ExtType == ISD::EXTLOAD) */ {
6094 // The high part is undefined.
6095 Hi = DAG.getNode(ISD::UNDEF, NVT);
6102 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
6103 SDValue LL, LH, RL, RH;
6104 ExpandOp(Node->getOperand(0), LL, LH);
6105 ExpandOp(Node->getOperand(1), RL, RH);
6106 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
6107 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
6111 SDValue LL, LH, RL, RH;
6112 ExpandOp(Node->getOperand(1), LL, LH);
6113 ExpandOp(Node->getOperand(2), RL, RH);
6114 if (getTypeAction(NVT) == Expand)
6115 NVT = TLI.getTypeToExpandTo(NVT);
6116 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
6118 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
6121 case ISD::SELECT_CC: {
6122 SDValue TL, TH, FL, FH;
6123 ExpandOp(Node->getOperand(2), TL, TH);
6124 ExpandOp(Node->getOperand(3), FL, FH);
6125 if (getTypeAction(NVT) == Expand)
6126 NVT = TLI.getTypeToExpandTo(NVT);
6127 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
6128 Node->getOperand(1), TL, FL, Node->getOperand(4));
6130 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
6131 Node->getOperand(1), TH, FH, Node->getOperand(4));
6134 case ISD::ANY_EXTEND:
6135 // The low part is any extension of the input (which degenerates to a copy).
6136 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
6137 // The high part is undefined.
6138 Hi = DAG.getNode(ISD::UNDEF, NVT);
6140 case ISD::SIGN_EXTEND: {
6141 // The low part is just a sign extension of the input (which degenerates to
6143 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
6145 // The high part is obtained by SRA'ing all but one of the bits of the lo
6147 unsigned LoSize = Lo.getValueType().getSizeInBits();
6148 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6149 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6152 case ISD::ZERO_EXTEND:
6153 // The low part is just a zero extension of the input (which degenerates to
6155 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
6157 // The high part is just a zero.
6158 Hi = DAG.getConstant(0, NVT);
6161 case ISD::TRUNCATE: {
6162 // The input value must be larger than this value. Expand *it*.
6164 ExpandOp(Node->getOperand(0), NewLo, Hi);
6166 // The low part is now either the right size, or it is closer. If not the
6167 // right size, make an illegal truncate so we recursively expand it.
6168 if (NewLo.getValueType() != Node->getValueType(0))
6169 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
6170 ExpandOp(NewLo, Lo, Hi);
6174 case ISD::BIT_CONVERT: {
6176 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
6177 // If the target wants to, allow it to lower this itself.
6178 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6179 case Expand: assert(0 && "cannot expand FP!");
6180 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
6181 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
6183 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
6186 // f32 / f64 must be expanded to i32 / i64.
6187 if (VT == MVT::f32 || VT == MVT::f64) {
6188 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6189 if (getTypeAction(NVT) == Expand)
6190 ExpandOp(Lo, Lo, Hi);
6194 // If source operand will be expanded to the same type as VT, i.e.
6195 // i64 <- f64, i32 <- f32, expand the source operand instead.
6196 MVT VT0 = Node->getOperand(0).getValueType();
6197 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
6198 ExpandOp(Node->getOperand(0), Lo, Hi);
6202 // Turn this into a load/store pair by default.
6203 if (Tmp.getNode() == 0)
6204 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT);
6206 ExpandOp(Tmp, Lo, Hi);
6210 case ISD::READCYCLECOUNTER: {
6211 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
6212 TargetLowering::Custom &&
6213 "Must custom expand ReadCycleCounter");
6214 SDValue Tmp = TLI.LowerOperation(Op, DAG);
6215 assert(Tmp.getNode() && "Node must be custom expanded!");
6216 ExpandOp(Tmp.getValue(0), Lo, Hi);
6217 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6218 LegalizeOp(Tmp.getValue(1)));
6222 case ISD::ATOMIC_CMP_SWAP_64: {
6223 // This operation does not need a loop.
6224 SDValue Tmp = TLI.LowerOperation(Op, DAG);
6225 assert(Tmp.getNode() && "Node must be custom expanded!");
6226 ExpandOp(Tmp.getValue(0), Lo, Hi);
6227 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6228 LegalizeOp(Tmp.getValue(1)));
6232 case ISD::ATOMIC_LOAD_ADD_64:
6233 case ISD::ATOMIC_LOAD_SUB_64:
6234 case ISD::ATOMIC_LOAD_AND_64:
6235 case ISD::ATOMIC_LOAD_OR_64:
6236 case ISD::ATOMIC_LOAD_XOR_64:
6237 case ISD::ATOMIC_LOAD_NAND_64:
6238 case ISD::ATOMIC_SWAP_64: {
6239 // These operations require a loop to be generated. We can't do that yet,
6240 // so substitute a target-dependent pseudo and expand that later.
6241 SDValue In2Lo, In2Hi, In2;
6242 ExpandOp(Op.getOperand(2), In2Lo, In2Hi);
6243 In2 = DAG.getNode(ISD::BUILD_PAIR, VT, In2Lo, In2Hi);
6244 AtomicSDNode* Anode = cast<AtomicSDNode>(Node);
6246 DAG.getAtomic(Op.getOpcode(), Op.getOperand(0), Op.getOperand(1), In2,
6247 Anode->getSrcValue(), Anode->getAlignment());
6248 SDValue Result = TLI.LowerOperation(Replace, DAG);
6249 ExpandOp(Result.getValue(0), Lo, Hi);
6250 // Remember that we legalized the chain.
6251 AddLegalizedOperand(SDValue(Node,1), LegalizeOp(Result.getValue(1)));
6255 // These operators cannot be expanded directly, emit them as calls to
6256 // library functions.
6257 case ISD::FP_TO_SINT: {
6258 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
6260 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6261 case Expand: assert(0 && "cannot expand FP!");
6262 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6263 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6266 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
6268 // Now that the custom expander is done, expand the result, which is still
6271 ExpandOp(Op, Lo, Hi);
6276 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Node->getOperand(0).getValueType(),
6278 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected uint-to-fp conversion!");
6279 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6283 case ISD::FP_TO_UINT: {
6284 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
6286 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6287 case Expand: assert(0 && "cannot expand FP!");
6288 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6289 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6292 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
6294 // Now that the custom expander is done, expand the result.
6296 ExpandOp(Op, Lo, Hi);
6301 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Node->getOperand(0).getValueType(),
6303 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
6304 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6309 // If the target wants custom lowering, do so.
6310 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6311 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
6312 SDValue Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
6313 Op = TLI.LowerOperation(Op, DAG);
6315 // Now that the custom expander is done, expand the result, which is
6317 ExpandOp(Op, Lo, Hi);
6322 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
6323 // this X << 1 as X+X.
6324 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
6325 if (ShAmt->getAPIntValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
6326 TLI.isOperationLegal(ISD::ADDE, NVT)) {
6327 SDValue LoOps[2], HiOps[3];
6328 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
6329 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
6330 LoOps[1] = LoOps[0];
6331 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6333 HiOps[1] = HiOps[0];
6334 HiOps[2] = Lo.getValue(1);
6335 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6340 // If we can emit an efficient shift operation, do so now.
6341 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6344 // If this target supports SHL_PARTS, use it.
6345 TargetLowering::LegalizeAction Action =
6346 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
6347 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6348 Action == TargetLowering::Custom) {
6349 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6353 // Otherwise, emit a libcall.
6354 Lo = ExpandLibCall(RTLIB::SHL_I64, Node, false/*left shift=unsigned*/, Hi);
6359 // If the target wants custom lowering, do so.
6360 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6361 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
6362 SDValue Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
6363 Op = TLI.LowerOperation(Op, DAG);
6365 // Now that the custom expander is done, expand the result, which is
6367 ExpandOp(Op, Lo, Hi);
6372 // If we can emit an efficient shift operation, do so now.
6373 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
6376 // If this target supports SRA_PARTS, use it.
6377 TargetLowering::LegalizeAction Action =
6378 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
6379 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6380 Action == TargetLowering::Custom) {
6381 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6385 // Otherwise, emit a libcall.
6386 Lo = ExpandLibCall(RTLIB::SRA_I64, Node, true/*ashr is signed*/, Hi);
6391 // If the target wants custom lowering, do so.
6392 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6393 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
6394 SDValue Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
6395 Op = TLI.LowerOperation(Op, DAG);
6397 // Now that the custom expander is done, expand the result, which is
6399 ExpandOp(Op, Lo, Hi);
6404 // If we can emit an efficient shift operation, do so now.
6405 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6408 // If this target supports SRL_PARTS, use it.
6409 TargetLowering::LegalizeAction Action =
6410 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
6411 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6412 Action == TargetLowering::Custom) {
6413 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6417 // Otherwise, emit a libcall.
6418 Lo = ExpandLibCall(RTLIB::SRL_I64, Node, false/*lshr is unsigned*/, Hi);
6424 // If the target wants to custom expand this, let them.
6425 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
6426 TargetLowering::Custom) {
6427 SDValue Result = TLI.LowerOperation(Op, DAG);
6428 if (Result.getNode()) {
6429 ExpandOp(Result, Lo, Hi);
6433 // Expand the subcomponents.
6434 SDValue LHSL, LHSH, RHSL, RHSH;
6435 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6436 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6437 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6438 SDValue LoOps[2], HiOps[3];
6444 //cascaded check to see if any smaller size has a a carry flag.
6445 unsigned OpV = Node->getOpcode() == ISD::ADD ? ISD::ADDC : ISD::SUBC;
6446 bool hasCarry = false;
6447 for (unsigned BitSize = NVT.getSizeInBits(); BitSize != 0; BitSize /= 2) {
6448 MVT AVT = MVT::getIntegerVT(BitSize);
6449 if (TLI.isOperationLegal(OpV, AVT)) {
6456 if (Node->getOpcode() == ISD::ADD) {
6457 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6458 HiOps[2] = Lo.getValue(1);
6459 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6461 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6462 HiOps[2] = Lo.getValue(1);
6463 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6467 if (Node->getOpcode() == ISD::ADD) {
6468 Lo = DAG.getNode(ISD::ADD, VTList, LoOps, 2);
6469 Hi = DAG.getNode(ISD::ADD, VTList, HiOps, 2);
6470 SDValue Cmp1 = DAG.getSetCC(TLI.getSetCCResultType(Lo),
6471 Lo, LoOps[0], ISD::SETULT);
6472 SDValue Carry1 = DAG.getNode(ISD::SELECT, NVT, Cmp1,
6473 DAG.getConstant(1, NVT),
6474 DAG.getConstant(0, NVT));
6475 SDValue Cmp2 = DAG.getSetCC(TLI.getSetCCResultType(Lo),
6476 Lo, LoOps[1], ISD::SETULT);
6477 SDValue Carry2 = DAG.getNode(ISD::SELECT, NVT, Cmp2,
6478 DAG.getConstant(1, NVT),
6480 Hi = DAG.getNode(ISD::ADD, NVT, Hi, Carry2);
6482 Lo = DAG.getNode(ISD::SUB, VTList, LoOps, 2);
6483 Hi = DAG.getNode(ISD::SUB, VTList, HiOps, 2);
6484 SDValue Cmp = DAG.getSetCC(NVT, LoOps[0], LoOps[1], ISD::SETULT);
6485 SDValue Borrow = DAG.getNode(ISD::SELECT, NVT, Cmp,
6486 DAG.getConstant(1, NVT),
6487 DAG.getConstant(0, NVT));
6488 Hi = DAG.getNode(ISD::SUB, NVT, Hi, Borrow);
6496 // Expand the subcomponents.
6497 SDValue LHSL, LHSH, RHSL, RHSH;
6498 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6499 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6500 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6501 SDValue LoOps[2] = { LHSL, RHSL };
6502 SDValue HiOps[3] = { LHSH, RHSH };
6504 if (Node->getOpcode() == ISD::ADDC) {
6505 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6506 HiOps[2] = Lo.getValue(1);
6507 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6509 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6510 HiOps[2] = Lo.getValue(1);
6511 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6513 // Remember that we legalized the flag.
6514 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6519 // Expand the subcomponents.
6520 SDValue LHSL, LHSH, RHSL, RHSH;
6521 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6522 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6523 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6524 SDValue LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
6525 SDValue HiOps[3] = { LHSH, RHSH };
6527 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
6528 HiOps[2] = Lo.getValue(1);
6529 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
6531 // Remember that we legalized the flag.
6532 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6536 // If the target wants to custom expand this, let them.
6537 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
6538 SDValue New = TLI.LowerOperation(Op, DAG);
6539 if (New.getNode()) {
6540 ExpandOp(New, Lo, Hi);
6545 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
6546 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
6547 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
6548 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
6549 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
6550 SDValue LL, LH, RL, RH;
6551 ExpandOp(Node->getOperand(0), LL, LH);
6552 ExpandOp(Node->getOperand(1), RL, RH);
6553 unsigned OuterBitSize = Op.getValueSizeInBits();
6554 unsigned InnerBitSize = RH.getValueSizeInBits();
6555 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
6556 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
6557 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
6558 if (DAG.MaskedValueIsZero(Node->getOperand(0), HighMask) &&
6559 DAG.MaskedValueIsZero(Node->getOperand(1), HighMask)) {
6560 // The inputs are both zero-extended.
6562 // We can emit a umul_lohi.
6563 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6564 Hi = SDValue(Lo.getNode(), 1);
6568 // We can emit a mulhu+mul.
6569 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6570 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6574 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
6575 // The input values are both sign-extended.
6577 // We can emit a smul_lohi.
6578 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6579 Hi = SDValue(Lo.getNode(), 1);
6583 // We can emit a mulhs+mul.
6584 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6585 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
6590 // Lo,Hi = umul LHS, RHS.
6591 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
6592 DAG.getVTList(NVT, NVT), LL, RL);
6594 Hi = UMulLOHI.getValue(1);
6595 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6596 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6597 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6598 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6602 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6603 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6604 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6605 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6606 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6607 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6612 // If nothing else, we can make a libcall.
6613 Lo = ExpandLibCall(RTLIB::MUL_I64, Node, false/*sign irrelevant*/, Hi);
6617 Lo = ExpandLibCall(RTLIB::SDIV_I64, Node, true, Hi);
6620 Lo = ExpandLibCall(RTLIB::UDIV_I64, Node, true, Hi);
6623 Lo = ExpandLibCall(RTLIB::SREM_I64, Node, true, Hi);
6626 Lo = ExpandLibCall(RTLIB::UREM_I64, Node, true, Hi);
6630 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::ADD_F32,
6633 RTLIB::ADD_PPCF128),
6637 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::SUB_F32,
6640 RTLIB::SUB_PPCF128),
6644 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::MUL_F32,
6647 RTLIB::MUL_PPCF128),
6651 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::DIV_F32,
6654 RTLIB::DIV_PPCF128),
6657 case ISD::FP_EXTEND: {
6658 if (VT == MVT::ppcf128) {
6659 assert(Node->getOperand(0).getValueType()==MVT::f32 ||
6660 Node->getOperand(0).getValueType()==MVT::f64);
6661 const uint64_t zero = 0;
6662 if (Node->getOperand(0).getValueType()==MVT::f32)
6663 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0));
6665 Hi = Node->getOperand(0);
6666 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6669 RTLIB::Libcall LC = RTLIB::getFPEXT(Node->getOperand(0).getValueType(), VT);
6670 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!");
6671 Lo = ExpandLibCall(LC, Node, true, Hi);
6674 case ISD::FP_ROUND: {
6675 RTLIB::Libcall LC = RTLIB::getFPROUND(Node->getOperand(0).getValueType(),
6677 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!");
6678 Lo = ExpandLibCall(LC, Node, true, Hi);
6693 case ISD::FNEARBYINT:
6696 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6697 switch(Node->getOpcode()) {
6699 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
6700 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
6703 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
6704 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
6707 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
6708 RTLIB::COS_F80, RTLIB::COS_PPCF128);
6711 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
6712 RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
6715 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
6716 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
6719 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
6720 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
6723 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
6724 RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
6727 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
6728 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
6731 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
6732 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
6735 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
6736 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128);
6739 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
6740 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128);
6743 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64,
6744 RTLIB::RINT_F80, RTLIB::RINT_PPCF128);
6746 case ISD::FNEARBYINT:
6747 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
6748 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
6751 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
6752 RTLIB::POW_PPCF128);
6755 LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64, RTLIB::POWI_F80,
6756 RTLIB::POWI_PPCF128);
6758 default: assert(0 && "Unreachable!");
6760 Lo = ExpandLibCall(LC, Node, false, Hi);
6764 if (VT == MVT::ppcf128) {
6766 ExpandOp(Node->getOperand(0), Lo, Tmp);
6767 Hi = DAG.getNode(ISD::FABS, NVT, Tmp);
6768 // lo = hi==fabs(hi) ? lo : -lo;
6769 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp,
6770 Lo, DAG.getNode(ISD::FNEG, NVT, Lo),
6771 DAG.getCondCode(ISD::SETEQ));
6774 SDValue Mask = (VT == MVT::f64)
6775 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
6776 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
6777 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6778 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6779 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
6780 if (getTypeAction(NVT) == Expand)
6781 ExpandOp(Lo, Lo, Hi);
6785 if (VT == MVT::ppcf128) {
6786 ExpandOp(Node->getOperand(0), Lo, Hi);
6787 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo);
6788 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi);
6791 SDValue Mask = (VT == MVT::f64)
6792 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
6793 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
6794 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6795 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6796 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
6797 if (getTypeAction(NVT) == Expand)
6798 ExpandOp(Lo, Lo, Hi);
6801 case ISD::FCOPYSIGN: {
6802 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
6803 if (getTypeAction(NVT) == Expand)
6804 ExpandOp(Lo, Lo, Hi);
6807 case ISD::SINT_TO_FP:
6808 case ISD::UINT_TO_FP: {
6809 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
6810 MVT SrcVT = Node->getOperand(0).getValueType();
6812 // Promote the operand if needed. Do this before checking for
6813 // ppcf128 so conversions of i16 and i8 work.
6814 if (getTypeAction(SrcVT) == Promote) {
6815 SDValue Tmp = PromoteOp(Node->getOperand(0));
6817 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
6818 DAG.getValueType(SrcVT))
6819 : DAG.getZeroExtendInReg(Tmp, SrcVT);
6820 Node = DAG.UpdateNodeOperands(Op, Tmp).getNode();
6821 SrcVT = Node->getOperand(0).getValueType();
6824 if (VT == MVT::ppcf128 && SrcVT == MVT::i32) {
6825 static const uint64_t zero = 0;
6827 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6828 Node->getOperand(0)));
6829 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6831 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
6832 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6833 Node->getOperand(0)));
6834 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6835 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6836 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
6837 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6838 DAG.getConstant(0, MVT::i32),
6839 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6841 APFloat(APInt(128, 2, TwoE32)),
6844 DAG.getCondCode(ISD::SETLT)),
6849 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) {
6850 // si64->ppcf128 done by libcall, below
6851 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
6852 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)),
6854 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6855 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
6856 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6857 DAG.getConstant(0, MVT::i64),
6858 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6860 APFloat(APInt(128, 2, TwoE64)),
6863 DAG.getCondCode(ISD::SETLT)),
6868 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
6869 Node->getOperand(0));
6870 if (getTypeAction(Lo.getValueType()) == Expand)
6871 // float to i32 etc. can be 'expanded' to a single node.
6872 ExpandOp(Lo, Lo, Hi);
6877 // Make sure the resultant values have been legalized themselves, unless this
6878 // is a type that requires multi-step expansion.
6879 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
6880 Lo = LegalizeOp(Lo);
6882 // Don't legalize the high part if it is expanded to a single node.
6883 Hi = LegalizeOp(Hi);
6886 // Remember in a map if the values will be reused later.
6888 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
6889 assert(isNew && "Value already expanded?!?");
6892 /// SplitVectorOp - Given an operand of vector type, break it down into
6893 /// two smaller values, still of vector type.
6894 void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
6896 assert(Op.getValueType().isVector() && "Cannot split non-vector type!");
6897 SDNode *Node = Op.getNode();
6898 unsigned NumElements = Op.getValueType().getVectorNumElements();
6899 assert(NumElements > 1 && "Cannot split a single element vector!");
6901 MVT NewEltVT = Op.getValueType().getVectorElementType();
6903 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
6904 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
6906 MVT NewVT_Lo = MVT::getVectorVT(NewEltVT, NewNumElts_Lo);
6907 MVT NewVT_Hi = MVT::getVectorVT(NewEltVT, NewNumElts_Hi);
6909 // See if we already split it.
6910 std::map<SDValue, std::pair<SDValue, SDValue> >::iterator I
6911 = SplitNodes.find(Op);
6912 if (I != SplitNodes.end()) {
6913 Lo = I->second.first;
6914 Hi = I->second.second;
6918 switch (Node->getOpcode()) {
6923 assert(0 && "Unhandled operation in SplitVectorOp!");
6925 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo);
6926 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi);
6928 case ISD::BUILD_PAIR:
6929 Lo = Node->getOperand(0);
6930 Hi = Node->getOperand(1);
6932 case ISD::INSERT_VECTOR_ELT: {
6933 if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) {
6934 SplitVectorOp(Node->getOperand(0), Lo, Hi);
6935 unsigned Index = Idx->getZExtValue();
6936 SDValue ScalarOp = Node->getOperand(1);
6937 if (Index < NewNumElts_Lo)
6938 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp,
6939 DAG.getIntPtrConstant(Index));
6941 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp,
6942 DAG.getIntPtrConstant(Index - NewNumElts_Lo));
6945 SDValue Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0),
6946 Node->getOperand(1),
6947 Node->getOperand(2));
6948 SplitVectorOp(Tmp, Lo, Hi);
6951 case ISD::VECTOR_SHUFFLE: {
6952 // Build the low part.
6953 SDValue Mask = Node->getOperand(2);
6954 SmallVector<SDValue, 8> Ops;
6955 MVT PtrVT = TLI.getPointerTy();
6957 // Insert all of the elements from the input that are needed. We use
6958 // buildvector of extractelement here because the input vectors will have
6959 // to be legalized, so this makes the code simpler.
6960 for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
6961 SDValue IdxNode = Mask.getOperand(i);
6962 if (IdxNode.getOpcode() == ISD::UNDEF) {
6963 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
6966 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
6967 SDValue InVec = Node->getOperand(0);
6968 if (Idx >= NumElements) {
6969 InVec = Node->getOperand(1);
6972 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6973 DAG.getConstant(Idx, PtrVT)));
6975 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6978 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
6979 SDValue IdxNode = Mask.getOperand(i);
6980 if (IdxNode.getOpcode() == ISD::UNDEF) {
6981 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
6984 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
6985 SDValue InVec = Node->getOperand(0);
6986 if (Idx >= NumElements) {
6987 InVec = Node->getOperand(1);
6990 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6991 DAG.getConstant(Idx, PtrVT)));
6993 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &Ops[0], Ops.size());
6996 case ISD::BUILD_VECTOR: {
6997 SmallVector<SDValue, 8> LoOps(Node->op_begin(),
6998 Node->op_begin()+NewNumElts_Lo);
6999 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size());
7001 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
7003 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size());
7006 case ISD::CONCAT_VECTORS: {
7007 // FIXME: Handle non-power-of-two vectors?
7008 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
7009 if (NewNumSubvectors == 1) {
7010 Lo = Node->getOperand(0);
7011 Hi = Node->getOperand(1);
7013 SmallVector<SDValue, 8> LoOps(Node->op_begin(),
7014 Node->op_begin()+NewNumSubvectors);
7015 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size());
7017 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumSubvectors,
7019 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size());
7024 SDValue Cond = Node->getOperand(0);
7026 SDValue LL, LH, RL, RH;
7027 SplitVectorOp(Node->getOperand(1), LL, LH);
7028 SplitVectorOp(Node->getOperand(2), RL, RH);
7030 if (Cond.getValueType().isVector()) {
7031 // Handle a vector merge.
7033 SplitVectorOp(Cond, CL, CH);
7034 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL);
7035 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH);
7037 // Handle a simple select with vector operands.
7038 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL);
7039 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH);
7043 case ISD::SELECT_CC: {
7044 SDValue CondLHS = Node->getOperand(0);
7045 SDValue CondRHS = Node->getOperand(1);
7046 SDValue CondCode = Node->getOperand(4);
7048 SDValue LL, LH, RL, RH;
7049 SplitVectorOp(Node->getOperand(2), LL, LH);
7050 SplitVectorOp(Node->getOperand(3), RL, RH);
7052 // Handle a simple select with vector operands.
7053 Lo = DAG.getNode(ISD::SELECT_CC, NewVT_Lo, CondLHS, CondRHS,
7055 Hi = DAG.getNode(ISD::SELECT_CC, NewVT_Hi, CondLHS, CondRHS,
7060 SDValue LL, LH, RL, RH;
7061 SplitVectorOp(Node->getOperand(0), LL, LH);
7062 SplitVectorOp(Node->getOperand(1), RL, RH);
7063 Lo = DAG.getNode(ISD::VSETCC, NewVT_Lo, LL, RL, Node->getOperand(2));
7064 Hi = DAG.getNode(ISD::VSETCC, NewVT_Hi, LH, RH, Node->getOperand(2));
7083 SDValue LL, LH, RL, RH;
7084 SplitVectorOp(Node->getOperand(0), LL, LH);
7085 SplitVectorOp(Node->getOperand(1), RL, RH);
7087 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL);
7088 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH);
7094 SplitVectorOp(Node->getOperand(0), L, H);
7096 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1));
7097 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1));
7113 case ISD::FP_TO_SINT:
7114 case ISD::FP_TO_UINT:
7115 case ISD::SINT_TO_FP:
7116 case ISD::UINT_TO_FP:
7118 case ISD::ANY_EXTEND:
7119 case ISD::SIGN_EXTEND:
7120 case ISD::ZERO_EXTEND:
7121 case ISD::FP_EXTEND: {
7123 SplitVectorOp(Node->getOperand(0), L, H);
7125 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L);
7126 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H);
7130 LoadSDNode *LD = cast<LoadSDNode>(Node);
7131 SDValue Ch = LD->getChain();
7132 SDValue Ptr = LD->getBasePtr();
7133 ISD::LoadExtType ExtType = LD->getExtensionType();
7134 const Value *SV = LD->getSrcValue();
7135 int SVOffset = LD->getSrcValueOffset();
7136 MVT MemoryVT = LD->getMemoryVT();
7137 unsigned Alignment = LD->getAlignment();
7138 bool isVolatile = LD->isVolatile();
7140 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
7141 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType());
7143 MVT MemNewEltVT = MemoryVT.getVectorElementType();
7144 MVT MemNewVT_Lo = MVT::getVectorVT(MemNewEltVT, NewNumElts_Lo);
7145 MVT MemNewVT_Hi = MVT::getVectorVT(MemNewEltVT, NewNumElts_Hi);
7147 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType,
7148 NewVT_Lo, Ch, Ptr, Offset,
7149 SV, SVOffset, MemNewVT_Lo, isVolatile, Alignment);
7150 unsigned IncrementSize = NewNumElts_Lo * MemNewEltVT.getSizeInBits()/8;
7151 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
7152 DAG.getIntPtrConstant(IncrementSize));
7153 SVOffset += IncrementSize;
7154 Alignment = MinAlign(Alignment, IncrementSize);
7155 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType,
7156 NewVT_Hi, Ch, Ptr, Offset,
7157 SV, SVOffset, MemNewVT_Hi, isVolatile, Alignment);
7159 // Build a factor node to remember that this load is independent of the
7161 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
7164 // Remember that we legalized the chain.
7165 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
7168 case ISD::BIT_CONVERT: {
7169 // We know the result is a vector. The input may be either a vector or a
7171 SDValue InOp = Node->getOperand(0);
7172 if (!InOp.getValueType().isVector() ||
7173 InOp.getValueType().getVectorNumElements() == 1) {
7174 // The input is a scalar or single-element vector.
7175 // Lower to a store/load so that it can be split.
7176 // FIXME: this could be improved probably.
7177 unsigned LdAlign = TLI.getTargetData()->getPrefTypeAlignment(
7178 Op.getValueType().getTypeForMVT());
7179 SDValue Ptr = DAG.CreateStackTemporary(InOp.getValueType(), LdAlign);
7180 int FI = cast<FrameIndexSDNode>(Ptr.getNode())->getIndex();
7182 SDValue St = DAG.getStore(DAG.getEntryNode(),
7184 PseudoSourceValue::getFixedStack(FI), 0);
7185 InOp = DAG.getLoad(Op.getValueType(), St, Ptr,
7186 PseudoSourceValue::getFixedStack(FI), 0);
7188 // Split the vector and convert each of the pieces now.
7189 SplitVectorOp(InOp, Lo, Hi);
7190 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo);
7191 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi);
7196 // Remember in a map if the values will be reused later.
7198 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
7199 assert(isNew && "Value already split?!?");
7203 /// ScalarizeVectorOp - Given an operand of single-element vector type
7204 /// (e.g. v1f32), convert it into the equivalent operation that returns a
7205 /// scalar (e.g. f32) value.
7206 SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) {
7207 assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!");
7208 SDNode *Node = Op.getNode();
7209 MVT NewVT = Op.getValueType().getVectorElementType();
7210 assert(Op.getValueType().getVectorNumElements() == 1);
7212 // See if we already scalarized it.
7213 std::map<SDValue, SDValue>::iterator I = ScalarizedNodes.find(Op);
7214 if (I != ScalarizedNodes.end()) return I->second;
7217 switch (Node->getOpcode()) {
7220 Node->dump(&DAG); cerr << "\n";
7222 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
7239 Result = DAG.getNode(Node->getOpcode(),
7241 ScalarizeVectorOp(Node->getOperand(0)),
7242 ScalarizeVectorOp(Node->getOperand(1)));
7254 case ISD::FP_TO_SINT:
7255 case ISD::FP_TO_UINT:
7256 case ISD::SINT_TO_FP:
7257 case ISD::UINT_TO_FP:
7258 case ISD::SIGN_EXTEND:
7259 case ISD::ZERO_EXTEND:
7260 case ISD::ANY_EXTEND:
7262 case ISD::FP_EXTEND:
7263 Result = DAG.getNode(Node->getOpcode(),
7265 ScalarizeVectorOp(Node->getOperand(0)));
7269 Result = DAG.getNode(Node->getOpcode(),
7271 ScalarizeVectorOp(Node->getOperand(0)),
7272 Node->getOperand(1));
7275 LoadSDNode *LD = cast<LoadSDNode>(Node);
7276 SDValue Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
7277 SDValue Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
7278 ISD::LoadExtType ExtType = LD->getExtensionType();
7279 const Value *SV = LD->getSrcValue();
7280 int SVOffset = LD->getSrcValueOffset();
7281 MVT MemoryVT = LD->getMemoryVT();
7282 unsigned Alignment = LD->getAlignment();
7283 bool isVolatile = LD->isVolatile();
7285 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
7286 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType());
7288 Result = DAG.getLoad(ISD::UNINDEXED, ExtType,
7289 NewVT, Ch, Ptr, Offset, SV, SVOffset,
7290 MemoryVT.getVectorElementType(),
7291 isVolatile, Alignment);
7293 // Remember that we legalized the chain.
7294 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
7297 case ISD::BUILD_VECTOR:
7298 Result = Node->getOperand(0);
7300 case ISD::INSERT_VECTOR_ELT:
7301 // Returning the inserted scalar element.
7302 Result = Node->getOperand(1);
7304 case ISD::CONCAT_VECTORS:
7305 assert(Node->getOperand(0).getValueType() == NewVT &&
7306 "Concat of non-legal vectors not yet supported!");
7307 Result = Node->getOperand(0);
7309 case ISD::VECTOR_SHUFFLE: {
7310 // Figure out if the scalar is the LHS or RHS and return it.
7311 SDValue EltNum = Node->getOperand(2).getOperand(0);
7312 if (cast<ConstantSDNode>(EltNum)->getZExtValue())
7313 Result = ScalarizeVectorOp(Node->getOperand(1));
7315 Result = ScalarizeVectorOp(Node->getOperand(0));
7318 case ISD::EXTRACT_SUBVECTOR:
7319 Result = Node->getOperand(0);
7320 assert(Result.getValueType() == NewVT);
7322 case ISD::BIT_CONVERT: {
7323 SDValue Op0 = Op.getOperand(0);
7324 if (Op0.getValueType().getVectorNumElements() == 1)
7325 Op0 = ScalarizeVectorOp(Op0);
7326 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op0);
7330 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
7331 ScalarizeVectorOp(Op.getOperand(1)),
7332 ScalarizeVectorOp(Op.getOperand(2)));
7334 case ISD::SELECT_CC:
7335 Result = DAG.getNode(ISD::SELECT_CC, NewVT, Node->getOperand(0),
7336 Node->getOperand(1),
7337 ScalarizeVectorOp(Op.getOperand(2)),
7338 ScalarizeVectorOp(Op.getOperand(3)),
7339 Node->getOperand(4));
7342 SDValue Op0 = ScalarizeVectorOp(Op.getOperand(0));
7343 SDValue Op1 = ScalarizeVectorOp(Op.getOperand(1));
7344 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Op0), Op0, Op1,
7346 Result = DAG.getNode(ISD::SELECT, NewVT, Result,
7347 DAG.getConstant(-1ULL, NewVT),
7348 DAG.getConstant(0ULL, NewVT));
7353 if (TLI.isTypeLegal(NewVT))
7354 Result = LegalizeOp(Result);
7355 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
7356 assert(isNew && "Value already scalarized?");
7361 // SelectionDAG::Legalize - This is the entry point for the file.
7363 void SelectionDAG::Legalize() {
7364 /// run - This is the main entry point to this class.
7366 SelectionDAGLegalize(*this).LegalizeDAG();