1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/CodeGen/PseudoSourceValue.h"
20 #include "llvm/Target/TargetFrameInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/Target/TargetData.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/Target/TargetSubtarget.h"
26 #include "llvm/CallingConv.h"
27 #include "llvm/Constants.h"
28 #include "llvm/DerivedTypes.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Compiler.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/ADT/DenseMap.h"
33 #include "llvm/ADT/SmallVector.h"
34 #include "llvm/ADT/SmallPtrSet.h"
40 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
41 cl::desc("Pop up a window to show dags before legalize"));
43 static const bool ViewLegalizeDAGs = 0;
46 //===----------------------------------------------------------------------===//
47 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
48 /// hacks on it until the target machine can handle it. This involves
49 /// eliminating value sizes the machine cannot handle (promoting small sizes to
50 /// large sizes or splitting up large values into small values) as well as
51 /// eliminating operations the machine cannot handle.
53 /// This code also does a small amount of optimization and recognition of idioms
54 /// as part of its processing. For example, if a target does not support a
55 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
56 /// will attempt merge setcc and brc instructions into brcc's.
59 class VISIBILITY_HIDDEN SelectionDAGLegalize {
63 // Libcall insertion helpers.
65 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
66 /// legalized. We use this to ensure that calls are properly serialized
67 /// against each other, including inserted libcalls.
68 SDOperand LastCALLSEQ_END;
70 /// IsLegalizingCall - This member is used *only* for purposes of providing
71 /// helpful assertions that a libcall isn't created while another call is
72 /// being legalized (which could lead to non-serialized call sequences).
73 bool IsLegalizingCall;
76 Legal, // The target natively supports this operation.
77 Promote, // This operation should be executed in a larger type.
78 Expand // Try to expand this to other ops, otherwise use a libcall.
81 /// ValueTypeActions - This is a bitvector that contains two bits for each
82 /// value type, where the two bits correspond to the LegalizeAction enum.
83 /// This can be queried with "getTypeAction(VT)".
84 TargetLowering::ValueTypeActionImpl ValueTypeActions;
86 /// LegalizedNodes - For nodes that are of legal width, and that have more
87 /// than one use, this map indicates what regularized operand to use. This
88 /// allows us to avoid legalizing the same thing more than once.
89 DenseMap<SDOperand, SDOperand> LegalizedNodes;
91 /// PromotedNodes - For nodes that are below legal width, and that have more
92 /// than one use, this map indicates what promoted value to use. This allows
93 /// us to avoid promoting the same thing more than once.
94 DenseMap<SDOperand, SDOperand> PromotedNodes;
96 /// ExpandedNodes - For nodes that need to be expanded this map indicates
97 /// which which operands are the expanded version of the input. This allows
98 /// us to avoid expanding the same node more than once.
99 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
101 /// SplitNodes - For vector nodes that need to be split, this map indicates
102 /// which which operands are the split version of the input. This allows us
103 /// to avoid splitting the same node more than once.
104 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
106 /// ScalarizedNodes - For nodes that need to be converted from vector types to
107 /// scalar types, this contains the mapping of ones we have already
108 /// processed to the result.
109 std::map<SDOperand, SDOperand> ScalarizedNodes;
111 void AddLegalizedOperand(SDOperand From, SDOperand To) {
112 LegalizedNodes.insert(std::make_pair(From, To));
113 // If someone requests legalization of the new node, return itself.
115 LegalizedNodes.insert(std::make_pair(To, To));
117 void AddPromotedOperand(SDOperand From, SDOperand To) {
118 bool isNew = PromotedNodes.insert(std::make_pair(From, To));
119 assert(isNew && "Got into the map somehow?");
120 // If someone requests legalization of the new node, return itself.
121 LegalizedNodes.insert(std::make_pair(To, To));
126 SelectionDAGLegalize(SelectionDAG &DAG);
128 /// getTypeAction - Return how we should legalize values of this type, either
129 /// it is already legal or we need to expand it into multiple registers of
130 /// smaller integer type, or we need to promote it to a larger type.
131 LegalizeAction getTypeAction(MVT VT) const {
132 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
135 /// isTypeLegal - Return true if this type is legal on this target.
137 bool isTypeLegal(MVT VT) const {
138 return getTypeAction(VT) == Legal;
144 /// HandleOp - Legalize, Promote, or Expand the specified operand as
145 /// appropriate for its type.
146 void HandleOp(SDOperand Op);
148 /// LegalizeOp - We know that the specified value has a legal type.
149 /// Recursively ensure that the operands have legal types, then return the
151 SDOperand LegalizeOp(SDOperand O);
153 /// UnrollVectorOp - We know that the given vector has a legal type, however
154 /// the operation it performs is not legal and is an operation that we have
155 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
156 /// operating on each element individually.
157 SDOperand UnrollVectorOp(SDOperand O);
159 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
160 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
161 /// is necessary to spill the vector being inserted into to memory, perform
162 /// the insert there, and then read the result back.
163 SDOperand PerformInsertVectorEltInMemory(SDOperand Vec, SDOperand Val,
166 /// PromoteOp - Given an operation that produces a value in an invalid type,
167 /// promote it to compute the value into a larger type. The produced value
168 /// will have the correct bits for the low portion of the register, but no
169 /// guarantee is made about the top bits: it may be zero, sign-extended, or
171 SDOperand PromoteOp(SDOperand O);
173 /// ExpandOp - Expand the specified SDOperand into its two component pieces
174 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
175 /// the LegalizeNodes map is filled in for any results that are not expanded,
176 /// the ExpandedNodes map is filled in for any results that are expanded, and
177 /// the Lo/Hi values are returned. This applies to integer types and Vector
179 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
181 /// SplitVectorOp - Given an operand of vector type, break it down into
182 /// two smaller values.
183 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
185 /// ScalarizeVectorOp - Given an operand of single-element vector type
186 /// (e.g. v1f32), convert it into the equivalent operation that returns a
187 /// scalar (e.g. f32) value.
188 SDOperand ScalarizeVectorOp(SDOperand O);
190 /// isShuffleLegal - Return true if a vector shuffle is legal with the
191 /// specified mask and type. Targets can specify exactly which masks they
192 /// support and the code generator is tasked with not creating illegal masks.
194 /// Note that this will also return true for shuffles that are promoted to a
197 /// If this is a legal shuffle, this method returns the (possibly promoted)
198 /// build_vector Mask. If it's not a legal shuffle, it returns null.
199 SDNode *isShuffleLegal(MVT VT, SDOperand Mask) const;
201 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
202 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
204 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
206 SDOperand ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned,
208 SDOperand ExpandIntToFP(bool isSigned, MVT DestTy, SDOperand Source);
210 SDOperand EmitStackConvert(SDOperand SrcOp, MVT SlotVT, MVT DestVT);
211 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
212 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
213 SDOperand ExpandLegalINT_TO_FP(bool isSigned, SDOperand LegalOp, MVT DestVT);
214 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT DestVT, bool isSigned);
215 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT DestVT, bool isSigned);
217 SDOperand ExpandBSWAP(SDOperand Op);
218 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
219 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
220 SDOperand &Lo, SDOperand &Hi);
221 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
222 SDOperand &Lo, SDOperand &Hi);
224 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op);
225 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
229 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
230 /// specified mask and type. Targets can specify exactly which masks they
231 /// support and the code generator is tasked with not creating illegal masks.
233 /// Note that this will also return true for shuffles that are promoted to a
235 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDOperand Mask) const {
236 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
238 case TargetLowering::Legal:
239 case TargetLowering::Custom:
241 case TargetLowering::Promote: {
242 // If this is promoted to a different type, convert the shuffle mask and
243 // ask if it is legal in the promoted type!
244 MVT NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
246 // If we changed # elements, change the shuffle mask.
247 unsigned NumEltsGrowth =
248 NVT.getVectorNumElements() / VT.getVectorNumElements();
249 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
250 if (NumEltsGrowth > 1) {
251 // Renumber the elements.
252 SmallVector<SDOperand, 8> Ops;
253 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
254 SDOperand InOp = Mask.getOperand(i);
255 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
256 if (InOp.getOpcode() == ISD::UNDEF)
257 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
259 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
260 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
264 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
270 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
273 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
274 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
275 ValueTypeActions(TLI.getValueTypeActions()) {
276 assert(MVT::LAST_VALUETYPE <= 32 &&
277 "Too many value types for ValueTypeActions to hold!");
280 /// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order
281 /// contains all of a nodes operands before it contains the node.
282 static void ComputeTopDownOrdering(SelectionDAG &DAG,
283 SmallVector<SDNode*, 64> &Order) {
285 DenseMap<SDNode*, unsigned> Visited;
286 std::vector<SDNode*> Worklist;
287 Worklist.reserve(128);
289 // Compute ordering from all of the leaves in the graphs, those (like the
290 // entry node) that have no operands.
291 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
292 E = DAG.allnodes_end(); I != E; ++I) {
293 if (I->getNumOperands() == 0) {
295 Worklist.push_back(I);
299 while (!Worklist.empty()) {
300 SDNode *N = Worklist.back();
303 if (++Visited[N] != N->getNumOperands())
304 continue; // Haven't visited all operands yet
308 // Now that we have N in, add anything that uses it if all of their operands
310 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
312 Worklist.push_back(UI->getUser());
315 assert(Order.size() == Visited.size() &&
316 Order.size() == DAG.allnodes_size() &&
317 "Error: DAG is cyclic!");
321 void SelectionDAGLegalize::LegalizeDAG() {
322 LastCALLSEQ_END = DAG.getEntryNode();
323 IsLegalizingCall = false;
325 // The legalize process is inherently a bottom-up recursive process (users
326 // legalize their uses before themselves). Given infinite stack space, we
327 // could just start legalizing on the root and traverse the whole graph. In
328 // practice however, this causes us to run out of stack space on large basic
329 // blocks. To avoid this problem, compute an ordering of the nodes where each
330 // node is only legalized after all of its operands are legalized.
331 SmallVector<SDNode*, 64> Order;
332 ComputeTopDownOrdering(DAG, Order);
334 for (unsigned i = 0, e = Order.size(); i != e; ++i)
335 HandleOp(SDOperand(Order[i], 0));
337 // Finally, it's possible the root changed. Get the new root.
338 SDOperand OldRoot = DAG.getRoot();
339 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
340 DAG.setRoot(LegalizedNodes[OldRoot]);
342 ExpandedNodes.clear();
343 LegalizedNodes.clear();
344 PromotedNodes.clear();
346 ScalarizedNodes.clear();
348 // Remove dead nodes now.
349 DAG.RemoveDeadNodes();
353 /// FindCallEndFromCallStart - Given a chained node that is part of a call
354 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
355 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
356 if (Node->getOpcode() == ISD::CALLSEQ_END)
358 if (Node->use_empty())
359 return 0; // No CallSeqEnd
361 // The chain is usually at the end.
362 SDOperand TheChain(Node, Node->getNumValues()-1);
363 if (TheChain.getValueType() != MVT::Other) {
364 // Sometimes it's at the beginning.
365 TheChain = SDOperand(Node, 0);
366 if (TheChain.getValueType() != MVT::Other) {
367 // Otherwise, hunt for it.
368 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
369 if (Node->getValueType(i) == MVT::Other) {
370 TheChain = SDOperand(Node, i);
374 // Otherwise, we walked into a node without a chain.
375 if (TheChain.getValueType() != MVT::Other)
380 for (SDNode::use_iterator UI = Node->use_begin(),
381 E = Node->use_end(); UI != E; ++UI) {
383 // Make sure to only follow users of our token chain.
384 SDNode *User = UI->getUser();
385 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
386 if (User->getOperand(i) == TheChain)
387 if (SDNode *Result = FindCallEndFromCallStart(User))
393 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
394 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
395 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
396 assert(Node && "Didn't find callseq_start for a call??");
397 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
399 assert(Node->getOperand(0).getValueType() == MVT::Other &&
400 "Node doesn't have a token chain argument!");
401 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
404 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
405 /// see if any uses can reach Dest. If no dest operands can get to dest,
406 /// legalize them, legalize ourself, and return false, otherwise, return true.
408 /// Keep track of the nodes we fine that actually do lead to Dest in
409 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
411 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
412 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
413 if (N == Dest) return true; // N certainly leads to Dest :)
415 // If we've already processed this node and it does lead to Dest, there is no
416 // need to reprocess it.
417 if (NodesLeadingTo.count(N)) return true;
419 // If the first result of this node has been already legalized, then it cannot
421 switch (getTypeAction(N->getValueType(0))) {
423 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
426 if (PromotedNodes.count(SDOperand(N, 0))) return false;
429 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
433 // Okay, this node has not already been legalized. Check and legalize all
434 // operands. If none lead to Dest, then we can legalize this node.
435 bool OperandsLeadToDest = false;
436 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
437 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
438 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
440 if (OperandsLeadToDest) {
441 NodesLeadingTo.insert(N);
445 // Okay, this node looks safe, legalize it and return false.
446 HandleOp(SDOperand(N, 0));
450 /// HandleOp - Legalize, Promote, or Expand the specified operand as
451 /// appropriate for its type.
452 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
453 MVT VT = Op.getValueType();
454 switch (getTypeAction(VT)) {
455 default: assert(0 && "Bad type action!");
456 case Legal: (void)LegalizeOp(Op); break;
457 case Promote: (void)PromoteOp(Op); break;
459 if (!VT.isVector()) {
460 // If this is an illegal scalar, expand it into its two component
463 if (Op.getOpcode() == ISD::TargetConstant)
464 break; // Allow illegal target nodes.
466 } else if (VT.getVectorNumElements() == 1) {
467 // If this is an illegal single element vector, convert it to a
469 (void)ScalarizeVectorOp(Op);
471 // Otherwise, this is an illegal multiple element vector.
472 // Split it in half and legalize both parts.
474 SplitVectorOp(Op, X, Y);
480 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
481 /// a load from the constant pool.
482 static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
483 SelectionDAG &DAG, TargetLowering &TLI) {
486 // If a FP immediate is precise when represented as a float and if the
487 // target can do an extending load from float to double, we put it into
488 // the constant pool as a float, even if it's is statically typed as a
489 // double. This shrinks FP constants and canonicalizes them for targets where
490 // an FP extending load is the same cost as a normal load (such as on the x87
491 // fp stack or PPC FP unit).
492 MVT VT = CFP->getValueType(0);
493 ConstantFP *LLVMC = ConstantFP::get(CFP->getValueAPF());
495 if (VT!=MVT::f64 && VT!=MVT::f32)
496 assert(0 && "Invalid type expansion");
497 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt(),
498 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
503 while (SVT != MVT::f32) {
504 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1);
505 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
506 // Only do this if the target has a native EXTLOAD instruction from
508 TLI.isLoadXLegal(ISD::EXTLOAD, SVT) &&
509 TLI.ShouldShrinkFPConstant(OrigVT)) {
510 const Type *SType = SVT.getTypeForMVT();
511 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
517 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
519 return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, DAG.getEntryNode(),
520 CPIdx, PseudoSourceValue::getConstantPool(),
522 return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx,
523 PseudoSourceValue::getConstantPool(), 0);
527 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
530 SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT,
531 SelectionDAG &DAG, TargetLowering &TLI) {
532 MVT VT = Node->getValueType(0);
533 MVT SrcVT = Node->getOperand(1).getValueType();
534 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
535 "fcopysign expansion only supported for f32 and f64");
536 MVT SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
538 // First get the sign bit of second operand.
539 SDOperand Mask1 = (SrcVT == MVT::f64)
540 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
541 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
542 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
543 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
544 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
545 // Shift right or sign-extend it if the two operands have different types.
546 int SizeDiff = SrcNVT.getSizeInBits() - NVT.getSizeInBits();
548 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
549 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
550 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
551 } else if (SizeDiff < 0)
552 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit);
554 // Clear the sign bit of first operand.
555 SDOperand Mask2 = (VT == MVT::f64)
556 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
557 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
558 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
559 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
560 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
562 // Or the value with the sign bit.
563 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
567 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
569 SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
570 TargetLowering &TLI) {
571 SDOperand Chain = ST->getChain();
572 SDOperand Ptr = ST->getBasePtr();
573 SDOperand Val = ST->getValue();
574 MVT VT = Val.getValueType();
575 int Alignment = ST->getAlignment();
576 int SVOffset = ST->getSrcValueOffset();
577 if (ST->getMemoryVT().isFloatingPoint() ||
578 ST->getMemoryVT().isVector()) {
579 // Expand to a bitconvert of the value to the integer type of the
580 // same size, then a (misaligned) int store.
582 if (VT.is128BitVector() || VT == MVT::ppcf128 || VT == MVT::f128)
584 else if (VT.is64BitVector() || VT==MVT::f64)
586 else if (VT==MVT::f32)
589 assert(0 && "Unaligned store of unsupported type");
591 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val);
592 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(),
593 SVOffset, ST->isVolatile(), Alignment);
595 assert(ST->getMemoryVT().isInteger() &&
596 !ST->getMemoryVT().isVector() &&
597 "Unaligned store of unknown type.");
598 // Get the half-size VT
600 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1);
601 int NumBits = NewStoredVT.getSizeInBits();
602 int IncrementSize = NumBits / 8;
604 // Divide the stored value in two parts.
605 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
607 SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
609 // Store the two parts
610 SDOperand Store1, Store2;
611 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr,
612 ST->getSrcValue(), SVOffset, NewStoredVT,
613 ST->isVolatile(), Alignment);
614 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
615 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
616 Alignment = MinAlign(Alignment, IncrementSize);
617 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr,
618 ST->getSrcValue(), SVOffset + IncrementSize,
619 NewStoredVT, ST->isVolatile(), Alignment);
621 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2);
624 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
626 SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
627 TargetLowering &TLI) {
628 int SVOffset = LD->getSrcValueOffset();
629 SDOperand Chain = LD->getChain();
630 SDOperand Ptr = LD->getBasePtr();
631 MVT VT = LD->getValueType(0);
632 MVT LoadedVT = LD->getMemoryVT();
633 if (VT.isFloatingPoint() || VT.isVector()) {
634 // Expand to a (misaligned) integer load of the same size,
635 // then bitconvert to floating point or vector.
637 if (LoadedVT.is128BitVector() ||
638 LoadedVT == MVT::ppcf128 || LoadedVT == MVT::f128)
640 else if (LoadedVT.is64BitVector() || LoadedVT == MVT::f64)
642 else if (LoadedVT == MVT::f32)
645 assert(0 && "Unaligned load of unsupported type");
647 SDOperand newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(),
648 SVOffset, LD->isVolatile(),
650 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad);
651 if (VT.isFloatingPoint() && LoadedVT != VT)
652 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result);
654 SDOperand Ops[] = { Result, Chain };
655 return DAG.getMergeValues(DAG.getVTList(VT, MVT::Other), Ops, 2);
657 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
658 "Unaligned load of unsupported type.");
660 // Compute the new VT that is half the size of the old one. This is an
662 unsigned NumBits = LoadedVT.getSizeInBits();
664 NewLoadedVT = MVT::getIntegerVT(NumBits/2);
667 unsigned Alignment = LD->getAlignment();
668 unsigned IncrementSize = NumBits / 8;
669 ISD::LoadExtType HiExtType = LD->getExtensionType();
671 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
672 if (HiExtType == ISD::NON_EXTLOAD)
673 HiExtType = ISD::ZEXTLOAD;
675 // Load the value in two parts
677 if (TLI.isLittleEndian()) {
678 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
679 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
680 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
681 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
682 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(),
683 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
684 MinAlign(Alignment, IncrementSize));
686 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset,
687 NewLoadedVT,LD->isVolatile(), Alignment);
688 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
689 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
690 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
691 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
692 MinAlign(Alignment, IncrementSize));
695 // aggregate the two parts
696 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
697 SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
698 Result = DAG.getNode(ISD::OR, VT, Result, Lo);
700 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
703 SDOperand Ops[] = { Result, TF };
704 return DAG.getMergeValues(DAG.getVTList(VT, MVT::Other), Ops, 2);
707 /// UnrollVectorOp - We know that the given vector has a legal type, however
708 /// the operation it performs is not legal and is an operation that we have
709 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
710 /// operating on each element individually.
711 SDOperand SelectionDAGLegalize::UnrollVectorOp(SDOperand Op) {
712 MVT VT = Op.getValueType();
713 assert(isTypeLegal(VT) &&
714 "Caller should expand or promote operands that are not legal!");
715 assert(Op.Val->getNumValues() == 1 &&
716 "Can't unroll a vector with multiple results!");
717 unsigned NE = VT.getVectorNumElements();
718 MVT EltVT = VT.getVectorElementType();
720 SmallVector<SDOperand, 8> Scalars;
721 SmallVector<SDOperand, 4> Operands(Op.getNumOperands());
722 for (unsigned i = 0; i != NE; ++i) {
723 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
724 SDOperand Operand = Op.getOperand(j);
725 MVT OperandVT = Operand.getValueType();
726 if (OperandVT.isVector()) {
727 // A vector operand; extract a single element.
728 MVT OperandEltVT = OperandVT.getVectorElementType();
729 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
732 DAG.getConstant(i, MVT::i32));
734 // A scalar operand; just use it as is.
735 Operands[j] = Operand;
738 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT,
739 &Operands[0], Operands.size()));
742 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size());
745 /// GetFPLibCall - Return the right libcall for the given floating point type.
746 static RTLIB::Libcall GetFPLibCall(MVT VT,
747 RTLIB::Libcall Call_F32,
748 RTLIB::Libcall Call_F64,
749 RTLIB::Libcall Call_F80,
750 RTLIB::Libcall Call_PPCF128) {
752 VT == MVT::f32 ? Call_F32 :
753 VT == MVT::f64 ? Call_F64 :
754 VT == MVT::f80 ? Call_F80 :
755 VT == MVT::ppcf128 ? Call_PPCF128 :
756 RTLIB::UNKNOWN_LIBCALL;
759 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
760 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
761 /// is necessary to spill the vector being inserted into to memory, perform
762 /// the insert there, and then read the result back.
763 SDOperand SelectionDAGLegalize::
764 PerformInsertVectorEltInMemory(SDOperand Vec, SDOperand Val, SDOperand Idx) {
765 SDOperand Tmp1 = Vec;
766 SDOperand Tmp2 = Val;
767 SDOperand Tmp3 = Idx;
769 // If the target doesn't support this, we have to spill the input vector
770 // to a temporary stack slot, update the element, then reload it. This is
771 // badness. We could also load the value into a vector register (either
772 // with a "move to register" or "extload into register" instruction, then
773 // permute it into place, if the idx is a constant and if the idx is
774 // supported by the target.
775 MVT VT = Tmp1.getValueType();
776 MVT EltVT = VT.getVectorElementType();
777 MVT IdxVT = Tmp3.getValueType();
778 MVT PtrVT = TLI.getPointerTy();
779 SDOperand StackPtr = DAG.CreateStackTemporary(VT);
781 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr.Val);
782 int SPFI = StackPtrFI->getIndex();
785 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr,
786 PseudoSourceValue::getFixedStack(),
789 // Truncate or zero extend offset to target pointer type.
790 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
791 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
792 // Add the offset to the index.
793 unsigned EltSize = EltVT.getSizeInBits()/8;
794 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
795 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
796 // Store the scalar value.
797 Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2,
798 PseudoSourceValue::getFixedStack(), SPFI, EltVT);
799 // Load the updated vector.
800 return DAG.getLoad(VT, Ch, StackPtr, PseudoSourceValue::getFixedStack(),SPFI);
803 /// LegalizeOp - We know that the specified value has a legal type, and
804 /// that its operands are legal. Now ensure that the operation itself
805 /// is legal, recursively ensuring that the operands' operations remain
807 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
808 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
811 assert(isTypeLegal(Op.getValueType()) &&
812 "Caller should expand or promote operands that are not legal!");
813 SDNode *Node = Op.Val;
815 // If this operation defines any values that cannot be represented in a
816 // register on this target, make sure to expand or promote them.
817 if (Node->getNumValues() > 1) {
818 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
819 if (getTypeAction(Node->getValueType(i)) != Legal) {
820 HandleOp(Op.getValue(i));
821 assert(LegalizedNodes.count(Op) &&
822 "Handling didn't add legal operands!");
823 return LegalizedNodes[Op];
827 // Note that LegalizeOp may be reentered even from single-use nodes, which
828 // means that we always must cache transformed nodes.
829 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
830 if (I != LegalizedNodes.end()) return I->second;
832 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
833 SDOperand Result = Op;
834 bool isCustom = false;
836 switch (Node->getOpcode()) {
837 case ISD::FrameIndex:
838 case ISD::EntryToken:
840 case ISD::BasicBlock:
841 case ISD::TargetFrameIndex:
842 case ISD::TargetJumpTable:
843 case ISD::TargetConstant:
844 case ISD::TargetConstantFP:
845 case ISD::TargetConstantPool:
846 case ISD::TargetGlobalAddress:
847 case ISD::TargetGlobalTLSAddress:
848 case ISD::TargetExternalSymbol:
851 case ISD::MEMOPERAND:
854 // Primitives must all be legal.
855 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
856 "This must be legal!");
859 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
860 // If this is a target node, legalize it by legalizing the operands then
861 // passing it through.
862 SmallVector<SDOperand, 8> Ops;
863 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
864 Ops.push_back(LegalizeOp(Node->getOperand(i)));
866 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
868 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
869 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
870 return Result.getValue(Op.ResNo);
872 // Otherwise this is an unhandled builtin node. splat.
874 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
876 assert(0 && "Do not know how to legalize this operator!");
878 case ISD::GLOBAL_OFFSET_TABLE:
879 case ISD::GlobalAddress:
880 case ISD::GlobalTLSAddress:
881 case ISD::ExternalSymbol:
882 case ISD::ConstantPool:
883 case ISD::JumpTable: // Nothing to do.
884 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
885 default: assert(0 && "This action is not supported yet!");
886 case TargetLowering::Custom:
887 Tmp1 = TLI.LowerOperation(Op, DAG);
888 if (Tmp1.Val) Result = Tmp1;
889 // FALLTHROUGH if the target doesn't want to lower this op after all.
890 case TargetLowering::Legal:
895 case ISD::RETURNADDR:
896 // The only option for these nodes is to custom lower them. If the target
897 // does not custom lower them, then return zero.
898 Tmp1 = TLI.LowerOperation(Op, DAG);
902 Result = DAG.getConstant(0, TLI.getPointerTy());
904 case ISD::FRAME_TO_ARGS_OFFSET: {
905 MVT VT = Node->getValueType(0);
906 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
907 default: assert(0 && "This action is not supported yet!");
908 case TargetLowering::Custom:
909 Result = TLI.LowerOperation(Op, DAG);
910 if (Result.Val) break;
912 case TargetLowering::Legal:
913 Result = DAG.getConstant(0, VT);
918 case ISD::EXCEPTIONADDR: {
919 Tmp1 = LegalizeOp(Node->getOperand(0));
920 MVT VT = Node->getValueType(0);
921 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
922 default: assert(0 && "This action is not supported yet!");
923 case TargetLowering::Expand: {
924 unsigned Reg = TLI.getExceptionAddressRegister();
925 Result = DAG.getCopyFromReg(Tmp1, Reg, VT);
928 case TargetLowering::Custom:
929 Result = TLI.LowerOperation(Op, DAG);
930 if (Result.Val) break;
932 case TargetLowering::Legal: {
933 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 };
934 Result = DAG.getMergeValues(DAG.getVTList(VT, MVT::Other), Ops, 2);
939 if (Result.Val->getNumValues() == 1) break;
941 assert(Result.Val->getNumValues() == 2 &&
942 "Cannot return more than two values!");
944 // Since we produced two values, make sure to remember that we
945 // legalized both of them.
946 Tmp1 = LegalizeOp(Result);
947 Tmp2 = LegalizeOp(Result.getValue(1));
948 AddLegalizedOperand(Op.getValue(0), Tmp1);
949 AddLegalizedOperand(Op.getValue(1), Tmp2);
950 return Op.ResNo ? Tmp2 : Tmp1;
951 case ISD::EHSELECTION: {
952 Tmp1 = LegalizeOp(Node->getOperand(0));
953 Tmp2 = LegalizeOp(Node->getOperand(1));
954 MVT VT = Node->getValueType(0);
955 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
956 default: assert(0 && "This action is not supported yet!");
957 case TargetLowering::Expand: {
958 unsigned Reg = TLI.getExceptionSelectorRegister();
959 Result = DAG.getCopyFromReg(Tmp2, Reg, VT);
962 case TargetLowering::Custom:
963 Result = TLI.LowerOperation(Op, DAG);
964 if (Result.Val) break;
966 case TargetLowering::Legal: {
967 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 };
968 Result = DAG.getMergeValues(DAG.getVTList(VT, MVT::Other), Ops, 2);
973 if (Result.Val->getNumValues() == 1) break;
975 assert(Result.Val->getNumValues() == 2 &&
976 "Cannot return more than two values!");
978 // Since we produced two values, make sure to remember that we
979 // legalized both of them.
980 Tmp1 = LegalizeOp(Result);
981 Tmp2 = LegalizeOp(Result.getValue(1));
982 AddLegalizedOperand(Op.getValue(0), Tmp1);
983 AddLegalizedOperand(Op.getValue(1), Tmp2);
984 return Op.ResNo ? Tmp2 : Tmp1;
985 case ISD::EH_RETURN: {
986 MVT VT = Node->getValueType(0);
987 // The only "good" option for this node is to custom lower it.
988 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
989 default: assert(0 && "This action is not supported at all!");
990 case TargetLowering::Custom:
991 Result = TLI.LowerOperation(Op, DAG);
992 if (Result.Val) break;
994 case TargetLowering::Legal:
995 // Target does not know, how to lower this, lower to noop
996 Result = LegalizeOp(Node->getOperand(0));
1001 case ISD::AssertSext:
1002 case ISD::AssertZext:
1003 Tmp1 = LegalizeOp(Node->getOperand(0));
1004 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1006 case ISD::MERGE_VALUES:
1007 // Legalize eliminates MERGE_VALUES nodes.
1008 Result = Node->getOperand(Op.ResNo);
1010 case ISD::CopyFromReg:
1011 Tmp1 = LegalizeOp(Node->getOperand(0));
1012 Result = Op.getValue(0);
1013 if (Node->getNumValues() == 2) {
1014 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1016 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
1017 if (Node->getNumOperands() == 3) {
1018 Tmp2 = LegalizeOp(Node->getOperand(2));
1019 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1021 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1023 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
1025 // Since CopyFromReg produces two values, make sure to remember that we
1026 // legalized both of them.
1027 AddLegalizedOperand(Op.getValue(0), Result);
1028 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1029 return Result.getValue(Op.ResNo);
1031 MVT VT = Op.getValueType();
1032 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
1033 default: assert(0 && "This action is not supported yet!");
1034 case TargetLowering::Expand:
1036 Result = DAG.getConstant(0, VT);
1037 else if (VT.isFloatingPoint())
1038 Result = DAG.getConstantFP(APFloat(APInt(VT.getSizeInBits(), 0)),
1041 assert(0 && "Unknown value type!");
1043 case TargetLowering::Legal:
1049 case ISD::INTRINSIC_W_CHAIN:
1050 case ISD::INTRINSIC_WO_CHAIN:
1051 case ISD::INTRINSIC_VOID: {
1052 SmallVector<SDOperand, 8> Ops;
1053 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1054 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1055 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1057 // Allow the target to custom lower its intrinsics if it wants to.
1058 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
1059 TargetLowering::Custom) {
1060 Tmp3 = TLI.LowerOperation(Result, DAG);
1061 if (Tmp3.Val) Result = Tmp3;
1064 if (Result.Val->getNumValues() == 1) break;
1066 // Must have return value and chain result.
1067 assert(Result.Val->getNumValues() == 2 &&
1068 "Cannot return more than two values!");
1070 // Since loads produce two values, make sure to remember that we
1071 // legalized both of them.
1072 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1073 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1074 return Result.getValue(Op.ResNo);
1077 case ISD::DBG_STOPPOINT:
1078 assert(Node->getNumOperands() == 1 && "Invalid DBG_STOPPOINT node!");
1079 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
1081 switch (TLI.getOperationAction(ISD::DBG_STOPPOINT, MVT::Other)) {
1082 case TargetLowering::Promote:
1083 default: assert(0 && "This action is not supported yet!");
1084 case TargetLowering::Expand: {
1085 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
1086 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
1087 bool useLABEL = TLI.isOperationLegal(ISD::DBG_LABEL, MVT::Other);
1089 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node);
1090 if (MMI && (useDEBUG_LOC || useLABEL)) {
1091 const CompileUnitDesc *CompileUnit = DSP->getCompileUnit();
1092 unsigned SrcFile = MMI->RecordSource(CompileUnit);
1094 unsigned Line = DSP->getLine();
1095 unsigned Col = DSP->getColumn();
1098 SmallVector<SDOperand, 8> Ops;
1099 Ops.push_back(Tmp1); // chain
1100 Ops.push_back(DAG.getConstant(Line, MVT::i32)); // line #
1101 Ops.push_back(DAG.getConstant(Col, MVT::i32)); // col #
1102 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
1103 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
1105 unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile);
1106 Result = DAG.getLabel(ISD::DBG_LABEL, Tmp1, ID);
1109 Result = Tmp1; // chain
1113 case TargetLowering::Legal:
1114 if (Tmp1 != Node->getOperand(0) ||
1115 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
1116 SmallVector<SDOperand, 8> Ops;
1117 Ops.push_back(Tmp1);
1118 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
1119 Ops.push_back(Node->getOperand(1)); // line # must be legal.
1120 Ops.push_back(Node->getOperand(2)); // col # must be legal.
1122 // Otherwise promote them.
1123 Ops.push_back(PromoteOp(Node->getOperand(1)));
1124 Ops.push_back(PromoteOp(Node->getOperand(2)));
1126 Ops.push_back(Node->getOperand(3)); // filename must be legal.
1127 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
1128 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1135 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!");
1136 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) {
1137 default: assert(0 && "This action is not supported yet!");
1138 case TargetLowering::Legal:
1139 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1140 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1141 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable.
1142 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1144 case TargetLowering::Expand:
1145 Result = LegalizeOp(Node->getOperand(0));
1150 case ISD::DEBUG_LOC:
1151 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
1152 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
1153 default: assert(0 && "This action is not supported yet!");
1154 case TargetLowering::Legal:
1155 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1156 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1157 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1158 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1159 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1164 case ISD::DBG_LABEL:
1166 assert(Node->getNumOperands() == 1 && "Invalid LABEL node!");
1167 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
1168 default: assert(0 && "This action is not supported yet!");
1169 case TargetLowering::Legal:
1170 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1171 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1173 case TargetLowering::Expand:
1174 Result = LegalizeOp(Node->getOperand(0));
1180 assert(Node->getNumOperands() == 4 && "Invalid Prefetch node!");
1181 switch (TLI.getOperationAction(ISD::PREFETCH, MVT::Other)) {
1182 default: assert(0 && "This action is not supported yet!");
1183 case TargetLowering::Legal:
1184 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1185 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1186 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the rw specifier.
1187 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize locality specifier.
1188 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1190 case TargetLowering::Expand:
1192 Result = LegalizeOp(Node->getOperand(0));
1197 case ISD::MEMBARRIER: {
1198 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!");
1199 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) {
1200 default: assert(0 && "This action is not supported yet!");
1201 case TargetLowering::Legal: {
1203 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1204 for (int x = 1; x < 6; ++x) {
1205 Ops[x] = Node->getOperand(x);
1206 if (!isTypeLegal(Ops[x].getValueType()))
1207 Ops[x] = PromoteOp(Ops[x]);
1209 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6);
1212 case TargetLowering::Expand:
1213 //There is no libgcc call for this op
1214 Result = Node->getOperand(0); // Noop
1220 case ISD::ATOMIC_CMP_SWAP: {
1221 unsigned int num_operands = 4;
1222 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1224 for (unsigned int x = 0; x < num_operands; ++x)
1225 Ops[x] = LegalizeOp(Node->getOperand(x));
1226 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1228 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1229 default: assert(0 && "This action is not supported yet!");
1230 case TargetLowering::Custom:
1231 Result = TLI.LowerOperation(Result, DAG);
1233 case TargetLowering::Legal:
1236 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1237 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1238 return Result.getValue(Op.ResNo);
1240 case ISD::ATOMIC_LOAD_ADD:
1241 case ISD::ATOMIC_LOAD_SUB:
1242 case ISD::ATOMIC_LOAD_AND:
1243 case ISD::ATOMIC_LOAD_OR:
1244 case ISD::ATOMIC_LOAD_XOR:
1245 case ISD::ATOMIC_LOAD_NAND:
1246 case ISD::ATOMIC_LOAD_MIN:
1247 case ISD::ATOMIC_LOAD_MAX:
1248 case ISD::ATOMIC_LOAD_UMIN:
1249 case ISD::ATOMIC_LOAD_UMAX:
1250 case ISD::ATOMIC_SWAP: {
1251 unsigned int num_operands = 3;
1252 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1254 for (unsigned int x = 0; x < num_operands; ++x)
1255 Ops[x] = LegalizeOp(Node->getOperand(x));
1256 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1258 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1259 default: assert(0 && "This action is not supported yet!");
1260 case TargetLowering::Custom:
1261 Result = TLI.LowerOperation(Result, DAG);
1263 case TargetLowering::Expand:
1264 Result = SDOperand(TLI.ExpandOperationResult(Op.Val, DAG),0);
1266 case TargetLowering::Legal:
1269 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1270 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1271 return Result.getValue(Op.ResNo);
1273 case ISD::Constant: {
1274 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1276 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1278 // We know we don't need to expand constants here, constants only have one
1279 // value and we check that it is fine above.
1281 if (opAction == TargetLowering::Custom) {
1282 Tmp1 = TLI.LowerOperation(Result, DAG);
1288 case ISD::ConstantFP: {
1289 // Spill FP immediates to the constant pool if the target cannot directly
1290 // codegen them. Targets often have some immediate values that can be
1291 // efficiently generated into an FP register without a load. We explicitly
1292 // leave these constants as ConstantFP nodes for the target to deal with.
1293 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1295 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1296 default: assert(0 && "This action is not supported yet!");
1297 case TargetLowering::Legal:
1299 case TargetLowering::Custom:
1300 Tmp3 = TLI.LowerOperation(Result, DAG);
1306 case TargetLowering::Expand: {
1307 // Check to see if this FP immediate is already legal.
1308 bool isLegal = false;
1309 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1310 E = TLI.legal_fpimm_end(); I != E; ++I) {
1311 if (CFP->isExactlyValue(*I)) {
1316 // If this is a legal constant, turn it into a TargetConstantFP node.
1319 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1324 case ISD::TokenFactor:
1325 if (Node->getNumOperands() == 2) {
1326 Tmp1 = LegalizeOp(Node->getOperand(0));
1327 Tmp2 = LegalizeOp(Node->getOperand(1));
1328 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1329 } else if (Node->getNumOperands() == 3) {
1330 Tmp1 = LegalizeOp(Node->getOperand(0));
1331 Tmp2 = LegalizeOp(Node->getOperand(1));
1332 Tmp3 = LegalizeOp(Node->getOperand(2));
1333 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1335 SmallVector<SDOperand, 8> Ops;
1336 // Legalize the operands.
1337 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1338 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1339 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1343 case ISD::FORMAL_ARGUMENTS:
1345 // The only option for this is to custom lower it.
1346 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1347 assert(Tmp3.Val && "Target didn't custom lower this node!");
1348 // A call within a calling sequence must be legalized to something
1349 // other than the normal CALLSEQ_END. Violating this gets Legalize
1350 // into an infinite loop.
1351 assert ((!IsLegalizingCall ||
1352 Node->getOpcode() != ISD::CALL ||
1353 Tmp3.Val->getOpcode() != ISD::CALLSEQ_END) &&
1354 "Nested CALLSEQ_START..CALLSEQ_END not supported.");
1356 // The number of incoming and outgoing values should match; unless the final
1357 // outgoing value is a flag.
1358 assert((Tmp3.Val->getNumValues() == Result.Val->getNumValues() ||
1359 (Tmp3.Val->getNumValues() == Result.Val->getNumValues() + 1 &&
1360 Tmp3.Val->getValueType(Tmp3.Val->getNumValues() - 1) ==
1362 "Lowering call/formal_arguments produced unexpected # results!");
1364 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1365 // remember that we legalized all of them, so it doesn't get relegalized.
1366 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
1367 if (Tmp3.Val->getValueType(i) == MVT::Flag)
1369 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1372 AddLegalizedOperand(SDOperand(Node, i), Tmp1);
1375 case ISD::EXTRACT_SUBREG: {
1376 Tmp1 = LegalizeOp(Node->getOperand(0));
1377 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1378 assert(idx && "Operand must be a constant");
1379 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1380 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1383 case ISD::INSERT_SUBREG: {
1384 Tmp1 = LegalizeOp(Node->getOperand(0));
1385 Tmp2 = LegalizeOp(Node->getOperand(1));
1386 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1387 assert(idx && "Operand must be a constant");
1388 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1389 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1392 case ISD::BUILD_VECTOR:
1393 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1394 default: assert(0 && "This action is not supported yet!");
1395 case TargetLowering::Custom:
1396 Tmp3 = TLI.LowerOperation(Result, DAG);
1402 case TargetLowering::Expand:
1403 Result = ExpandBUILD_VECTOR(Result.Val);
1407 case ISD::INSERT_VECTOR_ELT:
1408 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1409 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1411 // The type of the value to insert may not be legal, even though the vector
1412 // type is legal. Legalize/Promote accordingly. We do not handle Expand
1414 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1415 default: assert(0 && "Cannot expand insert element operand");
1416 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
1417 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
1419 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1421 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1422 Node->getValueType(0))) {
1423 default: assert(0 && "This action is not supported yet!");
1424 case TargetLowering::Legal:
1426 case TargetLowering::Custom:
1427 Tmp4 = TLI.LowerOperation(Result, DAG);
1433 case TargetLowering::Expand: {
1434 // If the insert index is a constant, codegen this as a scalar_to_vector,
1435 // then a shuffle that inserts it into the right position in the vector.
1436 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1437 // SCALAR_TO_VECTOR requires that the type of the value being inserted
1438 // match the element type of the vector being created.
1439 if (Tmp2.getValueType() ==
1440 Op.getValueType().getVectorElementType()) {
1441 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
1442 Tmp1.getValueType(), Tmp2);
1444 unsigned NumElts = Tmp1.getValueType().getVectorNumElements();
1446 MVT::getIntVectorWithNumElements(NumElts);
1447 MVT ShufMaskEltVT = ShufMaskVT.getVectorElementType();
1449 // We generate a shuffle of InVec and ScVec, so the shuffle mask
1450 // should be 0,1,2,3,4,5... with the appropriate element replaced with
1451 // elt 0 of the RHS.
1452 SmallVector<SDOperand, 8> ShufOps;
1453 for (unsigned i = 0; i != NumElts; ++i) {
1454 if (i != InsertPos->getValue())
1455 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1457 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1459 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1460 &ShufOps[0], ShufOps.size());
1462 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1463 Tmp1, ScVec, ShufMask);
1464 Result = LegalizeOp(Result);
1468 Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3);
1473 case ISD::SCALAR_TO_VECTOR:
1474 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1475 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1479 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1480 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1481 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1482 Node->getValueType(0))) {
1483 default: assert(0 && "This action is not supported yet!");
1484 case TargetLowering::Legal:
1486 case TargetLowering::Custom:
1487 Tmp3 = TLI.LowerOperation(Result, DAG);
1493 case TargetLowering::Expand:
1494 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1498 case ISD::VECTOR_SHUFFLE:
1499 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1500 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1501 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1503 // Allow targets to custom lower the SHUFFLEs they support.
1504 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1505 default: assert(0 && "Unknown operation action!");
1506 case TargetLowering::Legal:
1507 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1508 "vector shuffle should not be created if not legal!");
1510 case TargetLowering::Custom:
1511 Tmp3 = TLI.LowerOperation(Result, DAG);
1517 case TargetLowering::Expand: {
1518 MVT VT = Node->getValueType(0);
1519 MVT EltVT = VT.getVectorElementType();
1520 MVT PtrVT = TLI.getPointerTy();
1521 SDOperand Mask = Node->getOperand(2);
1522 unsigned NumElems = Mask.getNumOperands();
1523 SmallVector<SDOperand,8> Ops;
1524 for (unsigned i = 0; i != NumElems; ++i) {
1525 SDOperand Arg = Mask.getOperand(i);
1526 if (Arg.getOpcode() == ISD::UNDEF) {
1527 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1529 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1530 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
1532 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1533 DAG.getConstant(Idx, PtrVT)));
1535 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1536 DAG.getConstant(Idx - NumElems, PtrVT)));
1539 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1542 case TargetLowering::Promote: {
1543 // Change base type to a different vector type.
1544 MVT OVT = Node->getValueType(0);
1545 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1547 // Cast the two input vectors.
1548 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1549 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1551 // Convert the shuffle mask to the right # elements.
1552 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1553 assert(Tmp3.Val && "Shuffle not legal?");
1554 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1555 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1561 case ISD::EXTRACT_VECTOR_ELT:
1562 Tmp1 = Node->getOperand(0);
1563 Tmp2 = LegalizeOp(Node->getOperand(1));
1564 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1565 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1568 case ISD::EXTRACT_SUBVECTOR:
1569 Tmp1 = Node->getOperand(0);
1570 Tmp2 = LegalizeOp(Node->getOperand(1));
1571 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1572 Result = ExpandEXTRACT_SUBVECTOR(Result);
1575 case ISD::CALLSEQ_START: {
1576 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1578 // Recursively Legalize all of the inputs of the call end that do not lead
1579 // to this call start. This ensures that any libcalls that need be inserted
1580 // are inserted *before* the CALLSEQ_START.
1581 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1582 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1583 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
1587 // Now that we legalized all of the inputs (which may have inserted
1588 // libcalls) create the new CALLSEQ_START node.
1589 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1591 // Merge in the last call, to ensure that this call start after the last
1593 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1594 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1595 Tmp1 = LegalizeOp(Tmp1);
1598 // Do not try to legalize the target-specific arguments (#1+).
1599 if (Tmp1 != Node->getOperand(0)) {
1600 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1602 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1605 // Remember that the CALLSEQ_START is legalized.
1606 AddLegalizedOperand(Op.getValue(0), Result);
1607 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1608 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1610 // Now that the callseq_start and all of the non-call nodes above this call
1611 // sequence have been legalized, legalize the call itself. During this
1612 // process, no libcalls can/will be inserted, guaranteeing that no calls
1614 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1615 // Note that we are selecting this call!
1616 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1617 IsLegalizingCall = true;
1619 // Legalize the call, starting from the CALLSEQ_END.
1620 LegalizeOp(LastCALLSEQ_END);
1621 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1624 case ISD::CALLSEQ_END:
1625 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1626 // will cause this node to be legalized as well as handling libcalls right.
1627 if (LastCALLSEQ_END.Val != Node) {
1628 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1629 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1630 assert(I != LegalizedNodes.end() &&
1631 "Legalizing the call start should have legalized this node!");
1635 // Otherwise, the call start has been legalized and everything is going
1636 // according to plan. Just legalize ourselves normally here.
1637 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1638 // Do not try to legalize the target-specific arguments (#1+), except for
1639 // an optional flag input.
1640 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1641 if (Tmp1 != Node->getOperand(0)) {
1642 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1644 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1647 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1648 if (Tmp1 != Node->getOperand(0) ||
1649 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1650 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1653 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1656 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1657 // This finishes up call legalization.
1658 IsLegalizingCall = false;
1660 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1661 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1662 if (Node->getNumValues() == 2)
1663 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1664 return Result.getValue(Op.ResNo);
1665 case ISD::DYNAMIC_STACKALLOC: {
1666 MVT VT = Node->getValueType(0);
1667 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1668 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1669 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1670 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1672 Tmp1 = Result.getValue(0);
1673 Tmp2 = Result.getValue(1);
1674 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1675 default: assert(0 && "This action is not supported yet!");
1676 case TargetLowering::Expand: {
1677 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1678 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1679 " not tell us which reg is the stack pointer!");
1680 SDOperand Chain = Tmp1.getOperand(0);
1682 // Chain the dynamic stack allocation so that it doesn't modify the stack
1683 // pointer when other instructions are using the stack.
1684 Chain = DAG.getCALLSEQ_START(Chain,
1685 DAG.getConstant(0, TLI.getPointerTy()));
1687 SDOperand Size = Tmp2.getOperand(1);
1688 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT);
1689 Chain = SP.getValue(1);
1690 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue();
1691 unsigned StackAlign =
1692 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1693 if (Align > StackAlign)
1694 SP = DAG.getNode(ISD::AND, VT, SP,
1695 DAG.getConstant(-(uint64_t)Align, VT));
1696 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value
1697 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
1700 DAG.getCALLSEQ_END(Chain,
1701 DAG.getConstant(0, TLI.getPointerTy()),
1702 DAG.getConstant(0, TLI.getPointerTy()),
1705 Tmp1 = LegalizeOp(Tmp1);
1706 Tmp2 = LegalizeOp(Tmp2);
1709 case TargetLowering::Custom:
1710 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1712 Tmp1 = LegalizeOp(Tmp3);
1713 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1716 case TargetLowering::Legal:
1719 // Since this op produce two values, make sure to remember that we
1720 // legalized both of them.
1721 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1722 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1723 return Op.ResNo ? Tmp2 : Tmp1;
1725 case ISD::INLINEASM: {
1726 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1727 bool Changed = false;
1728 // Legalize all of the operands of the inline asm, in case they are nodes
1729 // that need to be expanded or something. Note we skip the asm string and
1730 // all of the TargetConstant flags.
1731 SDOperand Op = LegalizeOp(Ops[0]);
1732 Changed = Op != Ops[0];
1735 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1736 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1737 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1738 for (++i; NumVals; ++i, --NumVals) {
1739 SDOperand Op = LegalizeOp(Ops[i]);
1748 Op = LegalizeOp(Ops.back());
1749 Changed |= Op != Ops.back();
1754 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1756 // INLINE asm returns a chain and flag, make sure to add both to the map.
1757 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1758 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1759 return Result.getValue(Op.ResNo);
1762 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1763 // Ensure that libcalls are emitted before a branch.
1764 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1765 Tmp1 = LegalizeOp(Tmp1);
1766 LastCALLSEQ_END = DAG.getEntryNode();
1768 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1771 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1772 // Ensure that libcalls are emitted before a branch.
1773 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1774 Tmp1 = LegalizeOp(Tmp1);
1775 LastCALLSEQ_END = DAG.getEntryNode();
1777 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1778 default: assert(0 && "Indirect target must be legal type (pointer)!");
1780 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1783 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1786 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1787 // Ensure that libcalls are emitted before a branch.
1788 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1789 Tmp1 = LegalizeOp(Tmp1);
1790 LastCALLSEQ_END = DAG.getEntryNode();
1792 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1793 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1795 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1796 default: assert(0 && "This action is not supported yet!");
1797 case TargetLowering::Legal: break;
1798 case TargetLowering::Custom:
1799 Tmp1 = TLI.LowerOperation(Result, DAG);
1800 if (Tmp1.Val) Result = Tmp1;
1802 case TargetLowering::Expand: {
1803 SDOperand Chain = Result.getOperand(0);
1804 SDOperand Table = Result.getOperand(1);
1805 SDOperand Index = Result.getOperand(2);
1807 MVT PTy = TLI.getPointerTy();
1808 MachineFunction &MF = DAG.getMachineFunction();
1809 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
1810 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1811 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1814 switch (EntrySize) {
1815 default: assert(0 && "Size of jump table not supported yet."); break;
1816 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr,
1817 PseudoSourceValue::getJumpTable(), 0); break;
1818 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr,
1819 PseudoSourceValue::getJumpTable(), 0); break;
1823 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1824 // For PIC, the sequence is:
1825 // BRIND(load(Jumptable + index) + RelocBase)
1826 // RelocBase can be JumpTable, GOT or some sort of global base.
1827 if (PTy != MVT::i32)
1828 Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr);
1829 Addr = DAG.getNode(ISD::ADD, PTy, Addr,
1830 TLI.getPICJumpTableRelocBase(Table, DAG));
1832 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1837 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1838 // Ensure that libcalls are emitted before a return.
1839 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1840 Tmp1 = LegalizeOp(Tmp1);
1841 LastCALLSEQ_END = DAG.getEntryNode();
1843 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1844 case Expand: assert(0 && "It's impossible to expand bools");
1846 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1849 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1851 // The top bits of the promoted condition are not necessarily zero, ensure
1852 // that the value is properly zero extended.
1853 unsigned BitWidth = Tmp2.getValueSizeInBits();
1854 if (!DAG.MaskedValueIsZero(Tmp2,
1855 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
1856 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1861 // Basic block destination (Op#2) is always legal.
1862 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1864 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1865 default: assert(0 && "This action is not supported yet!");
1866 case TargetLowering::Legal: break;
1867 case TargetLowering::Custom:
1868 Tmp1 = TLI.LowerOperation(Result, DAG);
1869 if (Tmp1.Val) Result = Tmp1;
1871 case TargetLowering::Expand:
1872 // Expand brcond's setcc into its constituent parts and create a BR_CC
1874 if (Tmp2.getOpcode() == ISD::SETCC) {
1875 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1876 Tmp2.getOperand(0), Tmp2.getOperand(1),
1877 Node->getOperand(2));
1879 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1880 DAG.getCondCode(ISD::SETNE), Tmp2,
1881 DAG.getConstant(0, Tmp2.getValueType()),
1882 Node->getOperand(2));
1888 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1889 // Ensure that libcalls are emitted before a branch.
1890 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1891 Tmp1 = LegalizeOp(Tmp1);
1892 Tmp2 = Node->getOperand(2); // LHS
1893 Tmp3 = Node->getOperand(3); // RHS
1894 Tmp4 = Node->getOperand(1); // CC
1896 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1897 LastCALLSEQ_END = DAG.getEntryNode();
1899 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1900 // the LHS is a legal SETCC itself. In this case, we need to compare
1901 // the result against zero to select between true and false values.
1902 if (Tmp3.Val == 0) {
1903 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1904 Tmp4 = DAG.getCondCode(ISD::SETNE);
1907 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1908 Node->getOperand(4));
1910 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1911 default: assert(0 && "Unexpected action for BR_CC!");
1912 case TargetLowering::Legal: break;
1913 case TargetLowering::Custom:
1914 Tmp4 = TLI.LowerOperation(Result, DAG);
1915 if (Tmp4.Val) Result = Tmp4;
1920 LoadSDNode *LD = cast<LoadSDNode>(Node);
1921 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1922 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1924 ISD::LoadExtType ExtType = LD->getExtensionType();
1925 if (ExtType == ISD::NON_EXTLOAD) {
1926 MVT VT = Node->getValueType(0);
1927 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1928 Tmp3 = Result.getValue(0);
1929 Tmp4 = Result.getValue(1);
1931 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1932 default: assert(0 && "This action is not supported yet!");
1933 case TargetLowering::Legal:
1934 // If this is an unaligned load and the target doesn't support it,
1936 if (!TLI.allowsUnalignedMemoryAccesses()) {
1937 unsigned ABIAlignment = TLI.getTargetData()->
1938 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
1939 if (LD->getAlignment() < ABIAlignment){
1940 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
1942 Tmp3 = Result.getOperand(0);
1943 Tmp4 = Result.getOperand(1);
1944 Tmp3 = LegalizeOp(Tmp3);
1945 Tmp4 = LegalizeOp(Tmp4);
1949 case TargetLowering::Custom:
1950 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1952 Tmp3 = LegalizeOp(Tmp1);
1953 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1956 case TargetLowering::Promote: {
1957 // Only promote a load of vector type to another.
1958 assert(VT.isVector() && "Cannot promote this load!");
1959 // Change base type to a different vector type.
1960 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1962 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1963 LD->getSrcValueOffset(),
1964 LD->isVolatile(), LD->getAlignment());
1965 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1966 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1970 // Since loads produce two values, make sure to remember that we
1971 // legalized both of them.
1972 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1973 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1974 return Op.ResNo ? Tmp4 : Tmp3;
1976 MVT SrcVT = LD->getMemoryVT();
1977 unsigned SrcWidth = SrcVT.getSizeInBits();
1978 int SVOffset = LD->getSrcValueOffset();
1979 unsigned Alignment = LD->getAlignment();
1980 bool isVolatile = LD->isVolatile();
1982 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
1983 // Some targets pretend to have an i1 loading operation, and actually
1984 // load an i8. This trick is correct for ZEXTLOAD because the top 7
1985 // bits are guaranteed to be zero; it helps the optimizers understand
1986 // that these bits are zero. It is also useful for EXTLOAD, since it
1987 // tells the optimizers that those bits are undefined. It would be
1988 // nice to have an effective generic way of getting these benefits...
1989 // Until such a way is found, don't insist on promoting i1 here.
1990 (SrcVT != MVT::i1 ||
1991 TLI.getLoadXAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
1992 // Promote to a byte-sized load if not loading an integral number of
1993 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
1994 unsigned NewWidth = SrcVT.getStoreSizeInBits();
1995 MVT NVT = MVT::getIntegerVT(NewWidth);
1998 // The extra bits are guaranteed to be zero, since we stored them that
1999 // way. A zext load from NVT thus automatically gives zext from SrcVT.
2001 ISD::LoadExtType NewExtType =
2002 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
2004 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0),
2005 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
2006 NVT, isVolatile, Alignment);
2008 Ch = Result.getValue(1); // The chain.
2010 if (ExtType == ISD::SEXTLOAD)
2011 // Having the top bits zero doesn't help when sign extending.
2012 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2013 Result, DAG.getValueType(SrcVT));
2014 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
2015 // All the top bits are guaranteed to be zero - inform the optimizers.
2016 Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result,
2017 DAG.getValueType(SrcVT));
2019 Tmp1 = LegalizeOp(Result);
2020 Tmp2 = LegalizeOp(Ch);
2021 } else if (SrcWidth & (SrcWidth - 1)) {
2022 // If not loading a power-of-2 number of bits, expand as two loads.
2023 assert(SrcVT.isExtended() && !SrcVT.isVector() &&
2024 "Unsupported extload!");
2025 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
2026 assert(RoundWidth < SrcWidth);
2027 unsigned ExtraWidth = SrcWidth - RoundWidth;
2028 assert(ExtraWidth < RoundWidth);
2029 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2030 "Load size not an integral number of bytes!");
2031 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2032 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2033 SDOperand Lo, Hi, Ch;
2034 unsigned IncrementSize;
2036 if (TLI.isLittleEndian()) {
2037 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
2038 // Load the bottom RoundWidth bits.
2039 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2040 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2043 // Load the remaining ExtraWidth bits.
2044 IncrementSize = RoundWidth / 8;
2045 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2046 DAG.getIntPtrConstant(IncrementSize));
2047 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2048 LD->getSrcValue(), SVOffset + IncrementSize,
2049 ExtraVT, isVolatile,
2050 MinAlign(Alignment, IncrementSize));
2052 // Build a factor node to remember that this load is independent of the
2054 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2057 // Move the top bits to the right place.
2058 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2059 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2061 // Join the hi and lo parts.
2062 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2064 // Big endian - avoid unaligned loads.
2065 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
2066 // Load the top RoundWidth bits.
2067 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2068 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2071 // Load the remaining ExtraWidth bits.
2072 IncrementSize = RoundWidth / 8;
2073 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2074 DAG.getIntPtrConstant(IncrementSize));
2075 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2076 LD->getSrcValue(), SVOffset + IncrementSize,
2077 ExtraVT, isVolatile,
2078 MinAlign(Alignment, IncrementSize));
2080 // Build a factor node to remember that this load is independent of the
2082 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2085 // Move the top bits to the right place.
2086 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2087 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2089 // Join the hi and lo parts.
2090 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2093 Tmp1 = LegalizeOp(Result);
2094 Tmp2 = LegalizeOp(Ch);
2096 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
2097 default: assert(0 && "This action is not supported yet!");
2098 case TargetLowering::Custom:
2101 case TargetLowering::Legal:
2102 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2103 Tmp1 = Result.getValue(0);
2104 Tmp2 = Result.getValue(1);
2107 Tmp3 = TLI.LowerOperation(Result, DAG);
2109 Tmp1 = LegalizeOp(Tmp3);
2110 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2113 // If this is an unaligned load and the target doesn't support it,
2115 if (!TLI.allowsUnalignedMemoryAccesses()) {
2116 unsigned ABIAlignment = TLI.getTargetData()->
2117 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
2118 if (LD->getAlignment() < ABIAlignment){
2119 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
2121 Tmp1 = Result.getOperand(0);
2122 Tmp2 = Result.getOperand(1);
2123 Tmp1 = LegalizeOp(Tmp1);
2124 Tmp2 = LegalizeOp(Tmp2);
2129 case TargetLowering::Expand:
2130 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
2131 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
2132 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
2133 LD->getSrcValueOffset(),
2134 LD->isVolatile(), LD->getAlignment());
2135 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
2136 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
2137 Tmp2 = LegalizeOp(Load.getValue(1));
2140 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
2141 // Turn the unsupported load into an EXTLOAD followed by an explicit
2142 // zero/sign extend inreg.
2143 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2144 Tmp1, Tmp2, LD->getSrcValue(),
2145 LD->getSrcValueOffset(), SrcVT,
2146 LD->isVolatile(), LD->getAlignment());
2148 if (ExtType == ISD::SEXTLOAD)
2149 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2150 Result, DAG.getValueType(SrcVT));
2152 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
2153 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
2154 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
2159 // Since loads produce two values, make sure to remember that we legalized
2161 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2162 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2163 return Op.ResNo ? Tmp2 : Tmp1;
2166 case ISD::EXTRACT_ELEMENT: {
2167 MVT OpTy = Node->getOperand(0).getValueType();
2168 switch (getTypeAction(OpTy)) {
2169 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
2171 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
2173 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
2174 DAG.getConstant(OpTy.getSizeInBits()/2,
2175 TLI.getShiftAmountTy()));
2176 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
2179 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
2180 Node->getOperand(0));
2184 // Get both the low and high parts.
2185 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2186 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
2187 Result = Tmp2; // 1 -> Hi
2189 Result = Tmp1; // 0 -> Lo
2195 case ISD::CopyToReg:
2196 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2198 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
2199 "Register type must be legal!");
2200 // Legalize the incoming value (must be a legal type).
2201 Tmp2 = LegalizeOp(Node->getOperand(2));
2202 if (Node->getNumValues() == 1) {
2203 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
2205 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
2206 if (Node->getNumOperands() == 4) {
2207 Tmp3 = LegalizeOp(Node->getOperand(3));
2208 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
2211 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
2214 // Since this produces two values, make sure to remember that we legalized
2216 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2217 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2223 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2225 // Ensure that libcalls are emitted before a return.
2226 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2227 Tmp1 = LegalizeOp(Tmp1);
2228 LastCALLSEQ_END = DAG.getEntryNode();
2230 switch (Node->getNumOperands()) {
2232 Tmp2 = Node->getOperand(1);
2233 Tmp3 = Node->getOperand(2); // Signness
2234 switch (getTypeAction(Tmp2.getValueType())) {
2236 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
2239 if (!Tmp2.getValueType().isVector()) {
2241 ExpandOp(Tmp2, Lo, Hi);
2243 // Big endian systems want the hi reg first.
2244 if (TLI.isBigEndian())
2248 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2250 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
2251 Result = LegalizeOp(Result);
2253 SDNode *InVal = Tmp2.Val;
2254 int InIx = Tmp2.ResNo;
2255 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
2256 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
2258 // Figure out if there is a simple type corresponding to this Vector
2259 // type. If so, convert to the vector type.
2260 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2261 if (TLI.isTypeLegal(TVT)) {
2262 // Turn this into a return of the vector type.
2263 Tmp2 = LegalizeOp(Tmp2);
2264 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2265 } else if (NumElems == 1) {
2266 // Turn this into a return of the scalar type.
2267 Tmp2 = ScalarizeVectorOp(Tmp2);
2268 Tmp2 = LegalizeOp(Tmp2);
2269 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2271 // FIXME: Returns of gcc generic vectors smaller than a legal type
2272 // should be returned in integer registers!
2274 // The scalarized value type may not be legal, e.g. it might require
2275 // promotion or expansion. Relegalize the return.
2276 Result = LegalizeOp(Result);
2278 // FIXME: Returns of gcc generic vectors larger than a legal vector
2279 // type should be returned by reference!
2281 SplitVectorOp(Tmp2, Lo, Hi);
2282 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2283 Result = LegalizeOp(Result);
2288 Tmp2 = PromoteOp(Node->getOperand(1));
2289 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2290 Result = LegalizeOp(Result);
2295 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2297 default: { // ret <values>
2298 SmallVector<SDOperand, 8> NewValues;
2299 NewValues.push_back(Tmp1);
2300 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
2301 switch (getTypeAction(Node->getOperand(i).getValueType())) {
2303 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
2304 NewValues.push_back(Node->getOperand(i+1));
2308 assert(!Node->getOperand(i).getValueType().isExtended() &&
2309 "FIXME: TODO: implement returning non-legal vector types!");
2310 ExpandOp(Node->getOperand(i), Lo, Hi);
2311 NewValues.push_back(Lo);
2312 NewValues.push_back(Node->getOperand(i+1));
2314 NewValues.push_back(Hi);
2315 NewValues.push_back(Node->getOperand(i+1));
2320 assert(0 && "Can't promote multiple return value yet!");
2323 if (NewValues.size() == Node->getNumOperands())
2324 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
2326 Result = DAG.getNode(ISD::RET, MVT::Other,
2327 &NewValues[0], NewValues.size());
2332 if (Result.getOpcode() == ISD::RET) {
2333 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
2334 default: assert(0 && "This action is not supported yet!");
2335 case TargetLowering::Legal: break;
2336 case TargetLowering::Custom:
2337 Tmp1 = TLI.LowerOperation(Result, DAG);
2338 if (Tmp1.Val) Result = Tmp1;
2344 StoreSDNode *ST = cast<StoreSDNode>(Node);
2345 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
2346 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
2347 int SVOffset = ST->getSrcValueOffset();
2348 unsigned Alignment = ST->getAlignment();
2349 bool isVolatile = ST->isVolatile();
2351 if (!ST->isTruncatingStore()) {
2352 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
2353 // FIXME: We shouldn't do this for TargetConstantFP's.
2354 // FIXME: move this to the DAG Combiner! Note that we can't regress due
2355 // to phase ordering between legalized code and the dag combiner. This
2356 // probably means that we need to integrate dag combiner and legalizer
2358 // We generally can't do this one for long doubles.
2359 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
2360 if (CFP->getValueType(0) == MVT::f32 &&
2361 getTypeAction(MVT::i32) == Legal) {
2362 Tmp3 = DAG.getConstant(CFP->getValueAPF().
2363 convertToAPInt().zextOrTrunc(32),
2365 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2366 SVOffset, isVolatile, Alignment);
2368 } else if (CFP->getValueType(0) == MVT::f64) {
2369 // If this target supports 64-bit registers, do a single 64-bit store.
2370 if (getTypeAction(MVT::i64) == Legal) {
2371 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt().
2372 zextOrTrunc(64), MVT::i64);
2373 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2374 SVOffset, isVolatile, Alignment);
2376 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
2377 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
2378 // stores. If the target supports neither 32- nor 64-bits, this
2379 // xform is certainly not worth it.
2380 const APInt &IntVal =CFP->getValueAPF().convertToAPInt();
2381 SDOperand Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
2382 SDOperand Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
2383 if (TLI.isBigEndian()) std::swap(Lo, Hi);
2385 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2386 SVOffset, isVolatile, Alignment);
2387 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2388 DAG.getIntPtrConstant(4));
2389 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
2390 isVolatile, MinAlign(Alignment, 4U));
2392 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2398 switch (getTypeAction(ST->getMemoryVT())) {
2400 Tmp3 = LegalizeOp(ST->getValue());
2401 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2404 MVT VT = Tmp3.getValueType();
2405 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2406 default: assert(0 && "This action is not supported yet!");
2407 case TargetLowering::Legal:
2408 // If this is an unaligned store and the target doesn't support it,
2410 if (!TLI.allowsUnalignedMemoryAccesses()) {
2411 unsigned ABIAlignment = TLI.getTargetData()->
2412 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2413 if (ST->getAlignment() < ABIAlignment)
2414 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2418 case TargetLowering::Custom:
2419 Tmp1 = TLI.LowerOperation(Result, DAG);
2420 if (Tmp1.Val) Result = Tmp1;
2422 case TargetLowering::Promote:
2423 assert(VT.isVector() && "Unknown legal promote case!");
2424 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
2425 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2426 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
2427 ST->getSrcValue(), SVOffset, isVolatile,
2434 // Truncate the value and store the result.
2435 Tmp3 = PromoteOp(ST->getValue());
2436 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2437 SVOffset, ST->getMemoryVT(),
2438 isVolatile, Alignment);
2442 unsigned IncrementSize = 0;
2445 // If this is a vector type, then we have to calculate the increment as
2446 // the product of the element size in bytes, and the number of elements
2447 // in the high half of the vector.
2448 if (ST->getValue().getValueType().isVector()) {
2449 SDNode *InVal = ST->getValue().Val;
2450 int InIx = ST->getValue().ResNo;
2451 MVT InVT = InVal->getValueType(InIx);
2452 unsigned NumElems = InVT.getVectorNumElements();
2453 MVT EVT = InVT.getVectorElementType();
2455 // Figure out if there is a simple type corresponding to this Vector
2456 // type. If so, convert to the vector type.
2457 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2458 if (TLI.isTypeLegal(TVT)) {
2459 // Turn this into a normal store of the vector type.
2460 Tmp3 = LegalizeOp(ST->getValue());
2461 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2462 SVOffset, isVolatile, Alignment);
2463 Result = LegalizeOp(Result);
2465 } else if (NumElems == 1) {
2466 // Turn this into a normal store of the scalar type.
2467 Tmp3 = ScalarizeVectorOp(ST->getValue());
2468 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2469 SVOffset, isVolatile, Alignment);
2470 // The scalarized value type may not be legal, e.g. it might require
2471 // promotion or expansion. Relegalize the scalar store.
2472 Result = LegalizeOp(Result);
2475 SplitVectorOp(ST->getValue(), Lo, Hi);
2476 IncrementSize = Lo.Val->getValueType(0).getVectorNumElements() *
2477 EVT.getSizeInBits()/8;
2480 ExpandOp(ST->getValue(), Lo, Hi);
2481 IncrementSize = Hi.Val ? Hi.getValueType().getSizeInBits()/8 : 0;
2483 if (TLI.isBigEndian())
2487 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2488 SVOffset, isVolatile, Alignment);
2490 if (Hi.Val == NULL) {
2491 // Must be int <-> float one-to-one expansion.
2496 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2497 DAG.getIntPtrConstant(IncrementSize));
2498 assert(isTypeLegal(Tmp2.getValueType()) &&
2499 "Pointers must be legal!");
2500 SVOffset += IncrementSize;
2501 Alignment = MinAlign(Alignment, IncrementSize);
2502 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2503 SVOffset, isVolatile, Alignment);
2504 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2508 switch (getTypeAction(ST->getValue().getValueType())) {
2510 Tmp3 = LegalizeOp(ST->getValue());
2513 // We can promote the value, the truncstore will still take care of it.
2514 Tmp3 = PromoteOp(ST->getValue());
2517 // Just store the low part. This may become a non-trunc store, so make
2518 // sure to use getTruncStore, not UpdateNodeOperands below.
2519 ExpandOp(ST->getValue(), Tmp3, Tmp4);
2520 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2521 SVOffset, MVT::i8, isVolatile, Alignment);
2524 MVT StVT = ST->getMemoryVT();
2525 unsigned StWidth = StVT.getSizeInBits();
2527 if (StWidth != StVT.getStoreSizeInBits()) {
2528 // Promote to a byte-sized store with upper bits zero if not
2529 // storing an integral number of bytes. For example, promote
2530 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
2531 MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits());
2532 Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT);
2533 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2534 SVOffset, NVT, isVolatile, Alignment);
2535 } else if (StWidth & (StWidth - 1)) {
2536 // If not storing a power-of-2 number of bits, expand as two stores.
2537 assert(StVT.isExtended() && !StVT.isVector() &&
2538 "Unsupported truncstore!");
2539 unsigned RoundWidth = 1 << Log2_32(StWidth);
2540 assert(RoundWidth < StWidth);
2541 unsigned ExtraWidth = StWidth - RoundWidth;
2542 assert(ExtraWidth < RoundWidth);
2543 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2544 "Store size not an integral number of bytes!");
2545 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2546 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2548 unsigned IncrementSize;
2550 if (TLI.isLittleEndian()) {
2551 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
2552 // Store the bottom RoundWidth bits.
2553 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2555 isVolatile, Alignment);
2557 // Store the remaining ExtraWidth bits.
2558 IncrementSize = RoundWidth / 8;
2559 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2560 DAG.getIntPtrConstant(IncrementSize));
2561 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2562 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2563 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2564 SVOffset + IncrementSize, ExtraVT, isVolatile,
2565 MinAlign(Alignment, IncrementSize));
2567 // Big endian - avoid unaligned stores.
2568 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
2569 // Store the top RoundWidth bits.
2570 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2571 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2572 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset,
2573 RoundVT, isVolatile, Alignment);
2575 // Store the remaining ExtraWidth bits.
2576 IncrementSize = RoundWidth / 8;
2577 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2578 DAG.getIntPtrConstant(IncrementSize));
2579 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2580 SVOffset + IncrementSize, ExtraVT, isVolatile,
2581 MinAlign(Alignment, IncrementSize));
2584 // The order of the stores doesn't matter.
2585 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2587 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2588 Tmp2 != ST->getBasePtr())
2589 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2592 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
2593 default: assert(0 && "This action is not supported yet!");
2594 case TargetLowering::Legal:
2595 // If this is an unaligned store and the target doesn't support it,
2597 if (!TLI.allowsUnalignedMemoryAccesses()) {
2598 unsigned ABIAlignment = TLI.getTargetData()->
2599 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2600 if (ST->getAlignment() < ABIAlignment)
2601 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2605 case TargetLowering::Custom:
2606 Result = TLI.LowerOperation(Result, DAG);
2609 // TRUNCSTORE:i16 i32 -> STORE i16
2610 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
2611 Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3);
2612 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset,
2613 isVolatile, Alignment);
2621 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2622 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2624 case ISD::STACKSAVE:
2625 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2626 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2627 Tmp1 = Result.getValue(0);
2628 Tmp2 = Result.getValue(1);
2630 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2631 default: assert(0 && "This action is not supported yet!");
2632 case TargetLowering::Legal: break;
2633 case TargetLowering::Custom:
2634 Tmp3 = TLI.LowerOperation(Result, DAG);
2636 Tmp1 = LegalizeOp(Tmp3);
2637 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2640 case TargetLowering::Expand:
2641 // Expand to CopyFromReg if the target set
2642 // StackPointerRegisterToSaveRestore.
2643 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2644 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
2645 Node->getValueType(0));
2646 Tmp2 = Tmp1.getValue(1);
2648 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
2649 Tmp2 = Node->getOperand(0);
2654 // Since stacksave produce two values, make sure to remember that we
2655 // legalized both of them.
2656 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2657 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2658 return Op.ResNo ? Tmp2 : Tmp1;
2660 case ISD::STACKRESTORE:
2661 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2662 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2663 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2665 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2666 default: assert(0 && "This action is not supported yet!");
2667 case TargetLowering::Legal: break;
2668 case TargetLowering::Custom:
2669 Tmp1 = TLI.LowerOperation(Result, DAG);
2670 if (Tmp1.Val) Result = Tmp1;
2672 case TargetLowering::Expand:
2673 // Expand to CopyToReg if the target set
2674 // StackPointerRegisterToSaveRestore.
2675 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2676 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
2684 case ISD::READCYCLECOUNTER:
2685 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2686 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2687 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2688 Node->getValueType(0))) {
2689 default: assert(0 && "This action is not supported yet!");
2690 case TargetLowering::Legal:
2691 Tmp1 = Result.getValue(0);
2692 Tmp2 = Result.getValue(1);
2694 case TargetLowering::Custom:
2695 Result = TLI.LowerOperation(Result, DAG);
2696 Tmp1 = LegalizeOp(Result.getValue(0));
2697 Tmp2 = LegalizeOp(Result.getValue(1));
2701 // Since rdcc produce two values, make sure to remember that we legalized
2703 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2704 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2708 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2709 case Expand: assert(0 && "It's impossible to expand bools");
2711 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2714 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2715 // Make sure the condition is either zero or one.
2716 unsigned BitWidth = Tmp1.getValueSizeInBits();
2717 if (!DAG.MaskedValueIsZero(Tmp1,
2718 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2719 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2723 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2724 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2726 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2728 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2729 default: assert(0 && "This action is not supported yet!");
2730 case TargetLowering::Legal: break;
2731 case TargetLowering::Custom: {
2732 Tmp1 = TLI.LowerOperation(Result, DAG);
2733 if (Tmp1.Val) Result = Tmp1;
2736 case TargetLowering::Expand:
2737 if (Tmp1.getOpcode() == ISD::SETCC) {
2738 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2740 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2742 Result = DAG.getSelectCC(Tmp1,
2743 DAG.getConstant(0, Tmp1.getValueType()),
2744 Tmp2, Tmp3, ISD::SETNE);
2747 case TargetLowering::Promote: {
2749 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2750 unsigned ExtOp, TruncOp;
2751 if (Tmp2.getValueType().isVector()) {
2752 ExtOp = ISD::BIT_CONVERT;
2753 TruncOp = ISD::BIT_CONVERT;
2754 } else if (Tmp2.getValueType().isInteger()) {
2755 ExtOp = ISD::ANY_EXTEND;
2756 TruncOp = ISD::TRUNCATE;
2758 ExtOp = ISD::FP_EXTEND;
2759 TruncOp = ISD::FP_ROUND;
2761 // Promote each of the values to the new type.
2762 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2763 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2764 // Perform the larger operation, then round down.
2765 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2766 if (TruncOp != ISD::FP_ROUND)
2767 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2769 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result,
2770 DAG.getIntPtrConstant(0));
2775 case ISD::SELECT_CC: {
2776 Tmp1 = Node->getOperand(0); // LHS
2777 Tmp2 = Node->getOperand(1); // RHS
2778 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2779 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2780 SDOperand CC = Node->getOperand(4);
2782 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
2784 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
2785 // the LHS is a legal SETCC itself. In this case, we need to compare
2786 // the result against zero to select between true and false values.
2787 if (Tmp2.Val == 0) {
2788 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2789 CC = DAG.getCondCode(ISD::SETNE);
2791 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
2793 // Everything is legal, see if we should expand this op or something.
2794 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
2795 default: assert(0 && "This action is not supported yet!");
2796 case TargetLowering::Legal: break;
2797 case TargetLowering::Custom:
2798 Tmp1 = TLI.LowerOperation(Result, DAG);
2799 if (Tmp1.Val) Result = Tmp1;
2805 Tmp1 = Node->getOperand(0);
2806 Tmp2 = Node->getOperand(1);
2807 Tmp3 = Node->getOperand(2);
2808 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
2810 // If we had to Expand the SetCC operands into a SELECT node, then it may
2811 // not always be possible to return a true LHS & RHS. In this case, just
2812 // return the value we legalized, returned in the LHS
2813 if (Tmp2.Val == 0) {
2818 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
2819 default: assert(0 && "Cannot handle this action for SETCC yet!");
2820 case TargetLowering::Custom:
2823 case TargetLowering::Legal:
2824 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2826 Tmp4 = TLI.LowerOperation(Result, DAG);
2827 if (Tmp4.Val) Result = Tmp4;
2830 case TargetLowering::Promote: {
2831 // First step, figure out the appropriate operation to use.
2832 // Allow SETCC to not be supported for all legal data types
2833 // Mostly this targets FP
2834 MVT NewInTy = Node->getOperand(0).getValueType();
2835 MVT OldVT = NewInTy; OldVT = OldVT;
2837 // Scan for the appropriate larger type to use.
2839 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
2841 assert(NewInTy.isInteger() == OldVT.isInteger() &&
2842 "Fell off of the edge of the integer world");
2843 assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() &&
2844 "Fell off of the edge of the floating point world");
2846 // If the target supports SETCC of this type, use it.
2847 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2850 if (NewInTy.isInteger())
2851 assert(0 && "Cannot promote Legal Integer SETCC yet");
2853 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2854 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2856 Tmp1 = LegalizeOp(Tmp1);
2857 Tmp2 = LegalizeOp(Tmp2);
2858 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2859 Result = LegalizeOp(Result);
2862 case TargetLowering::Expand:
2863 // Expand a setcc node into a select_cc of the same condition, lhs, and
2864 // rhs that selects between const 1 (true) and const 0 (false).
2865 MVT VT = Node->getValueType(0);
2866 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2867 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2873 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2874 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2875 SDOperand CC = Node->getOperand(2);
2877 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, CC);
2879 // Everything is legal, see if we should expand this op or something.
2880 switch (TLI.getOperationAction(ISD::VSETCC, Tmp1.getValueType())) {
2881 default: assert(0 && "This action is not supported yet!");
2882 case TargetLowering::Legal: break;
2883 case TargetLowering::Custom:
2884 Tmp1 = TLI.LowerOperation(Result, DAG);
2885 if (Tmp1.Val) Result = Tmp1;
2891 case ISD::SHL_PARTS:
2892 case ISD::SRA_PARTS:
2893 case ISD::SRL_PARTS: {
2894 SmallVector<SDOperand, 8> Ops;
2895 bool Changed = false;
2896 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2897 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2898 Changed |= Ops.back() != Node->getOperand(i);
2901 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2903 switch (TLI.getOperationAction(Node->getOpcode(),
2904 Node->getValueType(0))) {
2905 default: assert(0 && "This action is not supported yet!");
2906 case TargetLowering::Legal: break;
2907 case TargetLowering::Custom:
2908 Tmp1 = TLI.LowerOperation(Result, DAG);
2910 SDOperand Tmp2, RetVal(0, 0);
2911 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2912 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2913 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2917 assert(RetVal.Val && "Illegal result number");
2923 // Since these produce multiple values, make sure to remember that we
2924 // legalized all of them.
2925 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2926 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2927 return Result.getValue(Op.ResNo);
2949 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2950 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2951 case Expand: assert(0 && "Not possible");
2953 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2956 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2960 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2962 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2963 default: assert(0 && "BinOp legalize operation not supported");
2964 case TargetLowering::Legal: break;
2965 case TargetLowering::Custom:
2966 Tmp1 = TLI.LowerOperation(Result, DAG);
2967 if (Tmp1.Val) Result = Tmp1;
2969 case TargetLowering::Expand: {
2970 MVT VT = Op.getValueType();
2972 // See if multiply or divide can be lowered using two-result operations.
2973 SDVTList VTs = DAG.getVTList(VT, VT);
2974 if (Node->getOpcode() == ISD::MUL) {
2975 // We just need the low half of the multiply; try both the signed
2976 // and unsigned forms. If the target supports both SMUL_LOHI and
2977 // UMUL_LOHI, form a preference by checking which forms of plain
2978 // MULH it supports.
2979 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT);
2980 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT);
2981 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT);
2982 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT);
2983 unsigned OpToUse = 0;
2984 if (HasSMUL_LOHI && !HasMULHS) {
2985 OpToUse = ISD::SMUL_LOHI;
2986 } else if (HasUMUL_LOHI && !HasMULHU) {
2987 OpToUse = ISD::UMUL_LOHI;
2988 } else if (HasSMUL_LOHI) {
2989 OpToUse = ISD::SMUL_LOHI;
2990 } else if (HasUMUL_LOHI) {
2991 OpToUse = ISD::UMUL_LOHI;
2994 Result = SDOperand(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).Val, 0);
2998 if (Node->getOpcode() == ISD::MULHS &&
2999 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) {
3000 Result = SDOperand(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
3003 if (Node->getOpcode() == ISD::MULHU &&
3004 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) {
3005 Result = SDOperand(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
3008 if (Node->getOpcode() == ISD::SDIV &&
3009 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3010 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 0);
3013 if (Node->getOpcode() == ISD::UDIV &&
3014 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3015 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 0);
3019 // Check to see if we have a libcall for this operator.
3020 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3021 bool isSigned = false;
3022 switch (Node->getOpcode()) {
3025 if (VT == MVT::i32) {
3026 LC = Node->getOpcode() == ISD::UDIV
3027 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
3028 isSigned = Node->getOpcode() == ISD::SDIV;
3032 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
3033 RTLIB::POW_PPCF128);
3037 if (LC != RTLIB::UNKNOWN_LIBCALL) {
3039 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3043 assert(Node->getValueType(0).isVector() &&
3044 "Cannot expand this binary operator!");
3045 // Expand the operation into a bunch of nasty scalar code.
3046 Result = LegalizeOp(UnrollVectorOp(Op));
3049 case TargetLowering::Promote: {
3050 switch (Node->getOpcode()) {
3051 default: assert(0 && "Do not know how to promote this BinOp!");
3055 MVT OVT = Node->getValueType(0);
3056 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3057 assert(OVT.isVector() && "Cannot promote this BinOp!");
3058 // Bit convert each of the values to the new type.
3059 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
3060 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
3061 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3062 // Bit convert the result back the original type.
3063 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
3071 case ISD::SMUL_LOHI:
3072 case ISD::UMUL_LOHI:
3075 // These nodes will only be produced by target-specific lowering, so
3076 // they shouldn't be here if they aren't legal.
3077 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
3078 "This must be legal!");
3080 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3081 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3082 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3085 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
3086 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3087 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3088 case Expand: assert(0 && "Not possible");
3090 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3093 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3097 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3099 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3100 default: assert(0 && "Operation not supported");
3101 case TargetLowering::Custom:
3102 Tmp1 = TLI.LowerOperation(Result, DAG);
3103 if (Tmp1.Val) Result = Tmp1;
3105 case TargetLowering::Legal: break;
3106 case TargetLowering::Expand: {
3107 // If this target supports fabs/fneg natively and select is cheap,
3108 // do this efficiently.
3109 if (!TLI.isSelectExpensive() &&
3110 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
3111 TargetLowering::Legal &&
3112 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
3113 TargetLowering::Legal) {
3114 // Get the sign bit of the RHS.
3116 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
3117 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
3118 SignBit = DAG.getSetCC(TLI.getSetCCResultType(SignBit),
3119 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
3120 // Get the absolute value of the result.
3121 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
3122 // Select between the nabs and abs value based on the sign bit of
3124 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
3125 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
3128 Result = LegalizeOp(Result);
3132 // Otherwise, do bitwise ops!
3134 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
3135 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
3136 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
3137 Result = LegalizeOp(Result);
3145 Tmp1 = LegalizeOp(Node->getOperand(0));
3146 Tmp2 = LegalizeOp(Node->getOperand(1));
3147 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3148 // Since this produces two values, make sure to remember that we legalized
3150 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
3151 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
3156 Tmp1 = LegalizeOp(Node->getOperand(0));
3157 Tmp2 = LegalizeOp(Node->getOperand(1));
3158 Tmp3 = LegalizeOp(Node->getOperand(2));
3159 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3160 // Since this produces two values, make sure to remember that we legalized
3162 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
3163 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
3166 case ISD::BUILD_PAIR: {
3167 MVT PairTy = Node->getValueType(0);
3168 // TODO: handle the case where the Lo and Hi operands are not of legal type
3169 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
3170 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
3171 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
3172 case TargetLowering::Promote:
3173 case TargetLowering::Custom:
3174 assert(0 && "Cannot promote/custom this yet!");
3175 case TargetLowering::Legal:
3176 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
3177 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
3179 case TargetLowering::Expand:
3180 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
3181 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
3182 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
3183 DAG.getConstant(PairTy.getSizeInBits()/2,
3184 TLI.getShiftAmountTy()));
3185 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
3194 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3195 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3197 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3198 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
3199 case TargetLowering::Custom:
3202 case TargetLowering::Legal:
3203 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3205 Tmp1 = TLI.LowerOperation(Result, DAG);
3206 if (Tmp1.Val) Result = Tmp1;
3209 case TargetLowering::Expand: {
3210 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
3211 bool isSigned = DivOpc == ISD::SDIV;
3212 MVT VT = Node->getValueType(0);
3214 // See if remainder can be lowered using two-result operations.
3215 SDVTList VTs = DAG.getVTList(VT, VT);
3216 if (Node->getOpcode() == ISD::SREM &&
3217 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3218 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 1);
3221 if (Node->getOpcode() == ISD::UREM &&
3222 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3223 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 1);
3227 if (VT.isInteger()) {
3228 if (TLI.getOperationAction(DivOpc, VT) ==
3229 TargetLowering::Legal) {
3231 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
3232 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
3233 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
3234 } else if (VT.isVector()) {
3235 Result = LegalizeOp(UnrollVectorOp(Op));
3237 assert(VT == MVT::i32 &&
3238 "Cannot expand this binary operator!");
3239 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
3240 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
3242 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3245 assert(VT.isFloatingPoint() &&
3246 "remainder op must have integer or floating-point type");
3247 if (VT.isVector()) {
3248 Result = LegalizeOp(UnrollVectorOp(Op));
3250 // Floating point mod -> fmod libcall.
3251 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
3252 RTLIB::REM_F80, RTLIB::REM_PPCF128);
3254 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3262 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3263 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3265 MVT VT = Node->getValueType(0);
3266 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
3267 default: assert(0 && "This action is not supported yet!");
3268 case TargetLowering::Custom:
3271 case TargetLowering::Legal:
3272 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3273 Result = Result.getValue(0);
3274 Tmp1 = Result.getValue(1);
3277 Tmp2 = TLI.LowerOperation(Result, DAG);
3279 Result = LegalizeOp(Tmp2);
3280 Tmp1 = LegalizeOp(Tmp2.getValue(1));
3284 case TargetLowering::Expand: {
3285 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3286 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
3287 // Increment the pointer, VAList, to the next vaarg
3288 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3289 DAG.getConstant(VT.getSizeInBits()/8,
3290 TLI.getPointerTy()));
3291 // Store the incremented VAList to the legalized pointer
3292 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
3293 // Load the actual argument out of the pointer VAList
3294 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
3295 Tmp1 = LegalizeOp(Result.getValue(1));
3296 Result = LegalizeOp(Result);
3300 // Since VAARG produces two values, make sure to remember that we
3301 // legalized both of them.
3302 AddLegalizedOperand(SDOperand(Node, 0), Result);
3303 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
3304 return Op.ResNo ? Tmp1 : Result;
3308 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3309 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
3310 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
3312 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
3313 default: assert(0 && "This action is not supported yet!");
3314 case TargetLowering::Custom:
3317 case TargetLowering::Legal:
3318 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
3319 Node->getOperand(3), Node->getOperand(4));
3321 Tmp1 = TLI.LowerOperation(Result, DAG);
3322 if (Tmp1.Val) Result = Tmp1;
3325 case TargetLowering::Expand:
3326 // This defaults to loading a pointer from the input and storing it to the
3327 // output, returning the chain.
3328 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3329 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3330 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VS, 0);
3331 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VD, 0);
3337 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3338 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3340 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
3341 default: assert(0 && "This action is not supported yet!");
3342 case TargetLowering::Custom:
3345 case TargetLowering::Legal:
3346 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3348 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
3349 if (Tmp1.Val) Result = Tmp1;
3352 case TargetLowering::Expand:
3353 Result = Tmp1; // Default to a no-op, return the chain
3359 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3360 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3362 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3364 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
3365 default: assert(0 && "This action is not supported yet!");
3366 case TargetLowering::Legal: break;
3367 case TargetLowering::Custom:
3368 Tmp1 = TLI.LowerOperation(Result, DAG);
3369 if (Tmp1.Val) Result = Tmp1;
3376 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3377 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3378 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3379 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3381 assert(0 && "ROTL/ROTR legalize operation not supported");
3383 case TargetLowering::Legal:
3385 case TargetLowering::Custom:
3386 Tmp1 = TLI.LowerOperation(Result, DAG);
3387 if (Tmp1.Val) Result = Tmp1;
3389 case TargetLowering::Promote:
3390 assert(0 && "Do not know how to promote ROTL/ROTR");
3392 case TargetLowering::Expand:
3393 assert(0 && "Do not know how to expand ROTL/ROTR");
3399 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3400 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3401 case TargetLowering::Custom:
3402 assert(0 && "Cannot custom legalize this yet!");
3403 case TargetLowering::Legal:
3404 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3406 case TargetLowering::Promote: {
3407 MVT OVT = Tmp1.getValueType();
3408 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3409 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3411 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3412 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3413 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3414 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3417 case TargetLowering::Expand:
3418 Result = ExpandBSWAP(Tmp1);
3426 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3427 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3428 case TargetLowering::Custom:
3429 case TargetLowering::Legal:
3430 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3431 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3432 TargetLowering::Custom) {
3433 Tmp1 = TLI.LowerOperation(Result, DAG);
3439 case TargetLowering::Promote: {
3440 MVT OVT = Tmp1.getValueType();
3441 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3443 // Zero extend the argument.
3444 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3445 // Perform the larger operation, then subtract if needed.
3446 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
3447 switch (Node->getOpcode()) {
3452 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3453 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
3454 DAG.getConstant(NVT.getSizeInBits(), NVT),
3456 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3457 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3460 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3461 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3462 DAG.getConstant(NVT.getSizeInBits() -
3463 OVT.getSizeInBits(), NVT));
3468 case TargetLowering::Expand:
3469 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
3480 Tmp1 = LegalizeOp(Node->getOperand(0));
3481 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3482 case TargetLowering::Promote:
3483 case TargetLowering::Custom:
3486 case TargetLowering::Legal:
3487 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3489 Tmp1 = TLI.LowerOperation(Result, DAG);
3490 if (Tmp1.Val) Result = Tmp1;
3493 case TargetLowering::Expand:
3494 switch (Node->getOpcode()) {
3495 default: assert(0 && "Unreachable!");
3497 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3498 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3499 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
3502 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3503 MVT VT = Node->getValueType(0);
3504 Tmp2 = DAG.getConstantFP(0.0, VT);
3505 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
3507 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
3508 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
3514 MVT VT = Node->getValueType(0);
3516 // Expand unsupported unary vector operators by unrolling them.
3517 if (VT.isVector()) {
3518 Result = LegalizeOp(UnrollVectorOp(Op));
3522 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3523 switch(Node->getOpcode()) {
3525 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3526 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
3529 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
3530 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
3533 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
3534 RTLIB::COS_F80, RTLIB::COS_PPCF128);
3536 default: assert(0 && "Unreachable!");
3539 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3547 MVT VT = Node->getValueType(0);
3549 // Expand unsupported unary vector operators by unrolling them.
3550 if (VT.isVector()) {
3551 Result = LegalizeOp(UnrollVectorOp(Op));
3555 // We always lower FPOWI into a libcall. No target support for it yet.
3556 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
3557 RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
3559 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3562 case ISD::BIT_CONVERT:
3563 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3564 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3565 Node->getValueType(0));
3566 } else if (Op.getOperand(0).getValueType().isVector()) {
3567 // The input has to be a vector type, we have to either scalarize it, pack
3568 // it, or convert it based on whether the input vector type is legal.
3569 SDNode *InVal = Node->getOperand(0).Val;
3570 int InIx = Node->getOperand(0).ResNo;
3571 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
3572 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
3574 // Figure out if there is a simple type corresponding to this Vector
3575 // type. If so, convert to the vector type.
3576 MVT TVT = MVT::getVectorVT(EVT, NumElems);
3577 if (TLI.isTypeLegal(TVT)) {
3578 // Turn this into a bit convert of the vector input.
3579 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3580 LegalizeOp(Node->getOperand(0)));
3582 } else if (NumElems == 1) {
3583 // Turn this into a bit convert of the scalar input.
3584 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3585 ScalarizeVectorOp(Node->getOperand(0)));
3588 // FIXME: UNIMP! Store then reload
3589 assert(0 && "Cast from unsupported vector type not implemented yet!");
3592 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3593 Node->getOperand(0).getValueType())) {
3594 default: assert(0 && "Unknown operation action!");
3595 case TargetLowering::Expand:
3596 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3597 Node->getValueType(0));
3599 case TargetLowering::Legal:
3600 Tmp1 = LegalizeOp(Node->getOperand(0));
3601 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3607 // Conversion operators. The source and destination have different types.
3608 case ISD::SINT_TO_FP:
3609 case ISD::UINT_TO_FP: {
3610 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
3611 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3613 switch (TLI.getOperationAction(Node->getOpcode(),
3614 Node->getOperand(0).getValueType())) {
3615 default: assert(0 && "Unknown operation action!");
3616 case TargetLowering::Custom:
3619 case TargetLowering::Legal:
3620 Tmp1 = LegalizeOp(Node->getOperand(0));
3621 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3623 Tmp1 = TLI.LowerOperation(Result, DAG);
3624 if (Tmp1.Val) Result = Tmp1;
3627 case TargetLowering::Expand:
3628 Result = ExpandLegalINT_TO_FP(isSigned,
3629 LegalizeOp(Node->getOperand(0)),
3630 Node->getValueType(0));
3632 case TargetLowering::Promote:
3633 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
3634 Node->getValueType(0),
3640 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
3641 Node->getValueType(0), Node->getOperand(0));
3644 Tmp1 = PromoteOp(Node->getOperand(0));
3646 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
3647 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
3649 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
3650 Node->getOperand(0).getValueType());
3652 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3653 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
3659 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3661 Tmp1 = LegalizeOp(Node->getOperand(0));
3662 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3665 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3667 // Since the result is legal, we should just be able to truncate the low
3668 // part of the source.
3669 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
3672 Result = PromoteOp(Node->getOperand(0));
3673 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
3678 case ISD::FP_TO_SINT:
3679 case ISD::FP_TO_UINT:
3680 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3682 Tmp1 = LegalizeOp(Node->getOperand(0));
3684 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
3685 default: assert(0 && "Unknown operation action!");
3686 case TargetLowering::Custom:
3689 case TargetLowering::Legal:
3690 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3692 Tmp1 = TLI.LowerOperation(Result, DAG);
3693 if (Tmp1.Val) Result = Tmp1;
3696 case TargetLowering::Promote:
3697 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
3698 Node->getOpcode() == ISD::FP_TO_SINT);
3700 case TargetLowering::Expand:
3701 if (Node->getOpcode() == ISD::FP_TO_UINT) {
3702 SDOperand True, False;
3703 MVT VT = Node->getOperand(0).getValueType();
3704 MVT NVT = Node->getValueType(0);
3705 const uint64_t zero[] = {0, 0};
3706 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero));
3707 APInt x = APInt::getSignBit(NVT.getSizeInBits());
3708 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
3709 Tmp2 = DAG.getConstantFP(apf, VT);
3710 Tmp3 = DAG.getSetCC(TLI.getSetCCResultType(Node->getOperand(0)),
3711 Node->getOperand(0), Tmp2, ISD::SETLT);
3712 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
3713 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
3714 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
3716 False = DAG.getNode(ISD::XOR, NVT, False,
3717 DAG.getConstant(x, NVT));
3718 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
3721 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
3727 MVT VT = Op.getValueType();
3728 MVT OVT = Node->getOperand(0).getValueType();
3729 // Convert ppcf128 to i32
3730 if (OVT == MVT::ppcf128 && VT == MVT::i32) {
3731 if (Node->getOpcode() == ISD::FP_TO_SINT) {
3732 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128,
3733 Node->getOperand(0), DAG.getValueType(MVT::f64));
3734 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result,
3735 DAG.getIntPtrConstant(1));
3736 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result);
3738 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
3739 APFloat apf = APFloat(APInt(128, 2, TwoE31));
3740 Tmp2 = DAG.getConstantFP(apf, OVT);
3741 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
3742 // FIXME: generated code sucks.
3743 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2,
3744 DAG.getNode(ISD::ADD, MVT::i32,
3745 DAG.getNode(ISD::FP_TO_SINT, VT,
3746 DAG.getNode(ISD::FSUB, OVT,
3747 Node->getOperand(0), Tmp2)),
3748 DAG.getConstant(0x80000000, MVT::i32)),
3749 DAG.getNode(ISD::FP_TO_SINT, VT,
3750 Node->getOperand(0)),
3751 DAG.getCondCode(ISD::SETGE));
3755 // Convert f32 / f64 to i32 / i64 / i128.
3756 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3757 switch (Node->getOpcode()) {
3758 case ISD::FP_TO_SINT: {
3759 if (VT == MVT::i32) {
3760 if (OVT == MVT::f32)
3761 LC = RTLIB::FPTOSINT_F32_I32;
3762 else if (OVT == MVT::f64)
3763 LC = RTLIB::FPTOSINT_F64_I32;
3765 assert(0 && "Unexpected i32-to-fp conversion!");
3766 } else if (VT == MVT::i64) {
3767 if (OVT == MVT::f32)
3768 LC = RTLIB::FPTOSINT_F32_I64;
3769 else if (OVT == MVT::f64)
3770 LC = RTLIB::FPTOSINT_F64_I64;
3771 else if (OVT == MVT::f80)
3772 LC = RTLIB::FPTOSINT_F80_I64;
3773 else if (OVT == MVT::ppcf128)
3774 LC = RTLIB::FPTOSINT_PPCF128_I64;
3776 assert(0 && "Unexpected i64-to-fp conversion!");
3777 } else if (VT == MVT::i128) {
3778 if (OVT == MVT::f32)
3779 LC = RTLIB::FPTOSINT_F32_I128;
3780 else if (OVT == MVT::f64)
3781 LC = RTLIB::FPTOSINT_F64_I128;
3782 else if (OVT == MVT::f80)
3783 LC = RTLIB::FPTOSINT_F80_I128;
3784 else if (OVT == MVT::ppcf128)
3785 LC = RTLIB::FPTOSINT_PPCF128_I128;
3787 assert(0 && "Unexpected i128-to-fp conversion!");
3789 assert(0 && "Unexpectd int-to-fp conversion!");
3793 case ISD::FP_TO_UINT: {
3794 if (VT == MVT::i32) {
3795 if (OVT == MVT::f32)
3796 LC = RTLIB::FPTOUINT_F32_I32;
3797 else if (OVT == MVT::f64)
3798 LC = RTLIB::FPTOUINT_F64_I32;
3799 else if (OVT == MVT::f80)
3800 LC = RTLIB::FPTOUINT_F80_I32;
3802 assert(0 && "Unexpected i32-to-fp conversion!");
3803 } else if (VT == MVT::i64) {
3804 if (OVT == MVT::f32)
3805 LC = RTLIB::FPTOUINT_F32_I64;
3806 else if (OVT == MVT::f64)
3807 LC = RTLIB::FPTOUINT_F64_I64;
3808 else if (OVT == MVT::f80)
3809 LC = RTLIB::FPTOUINT_F80_I64;
3810 else if (OVT == MVT::ppcf128)
3811 LC = RTLIB::FPTOUINT_PPCF128_I64;
3813 assert(0 && "Unexpected i64-to-fp conversion!");
3814 } else if (VT == MVT::i128) {
3815 if (OVT == MVT::f32)
3816 LC = RTLIB::FPTOUINT_F32_I128;
3817 else if (OVT == MVT::f64)
3818 LC = RTLIB::FPTOUINT_F64_I128;
3819 else if (OVT == MVT::f80)
3820 LC = RTLIB::FPTOUINT_F80_I128;
3821 else if (OVT == MVT::ppcf128)
3822 LC = RTLIB::FPTOUINT_PPCF128_I128;
3824 assert(0 && "Unexpected i128-to-fp conversion!");
3826 assert(0 && "Unexpectd int-to-fp conversion!");
3830 default: assert(0 && "Unreachable!");
3833 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3837 Tmp1 = PromoteOp(Node->getOperand(0));
3838 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
3839 Result = LegalizeOp(Result);
3844 case ISD::FP_EXTEND: {
3845 MVT DstVT = Op.getValueType();
3846 MVT SrcVT = Op.getOperand(0).getValueType();
3847 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3848 // The only other way we can lower this is to turn it into a STORE,
3849 // LOAD pair, targetting a temporary location (a stack slot).
3850 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT);
3853 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3854 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3856 Tmp1 = LegalizeOp(Node->getOperand(0));
3857 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3860 Tmp1 = PromoteOp(Node->getOperand(0));
3861 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1);
3866 case ISD::FP_ROUND: {
3867 MVT DstVT = Op.getValueType();
3868 MVT SrcVT = Op.getOperand(0).getValueType();
3869 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3870 if (SrcVT == MVT::ppcf128) {
3872 ExpandOp(Node->getOperand(0), Lo, Result);
3873 // Round it the rest of the way (e.g. to f32) if needed.
3874 if (DstVT!=MVT::f64)
3875 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1));
3878 // The only other way we can lower this is to turn it into a STORE,
3879 // LOAD pair, targetting a temporary location (a stack slot).
3880 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT);
3883 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3884 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3886 Tmp1 = LegalizeOp(Node->getOperand(0));
3887 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3890 Tmp1 = PromoteOp(Node->getOperand(0));
3891 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1,
3892 Node->getOperand(1));
3897 case ISD::ANY_EXTEND:
3898 case ISD::ZERO_EXTEND:
3899 case ISD::SIGN_EXTEND:
3900 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3901 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3903 Tmp1 = LegalizeOp(Node->getOperand(0));
3904 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3905 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3906 TargetLowering::Custom) {
3907 Tmp1 = TLI.LowerOperation(Result, DAG);
3908 if (Tmp1.Val) Result = Tmp1;
3912 switch (Node->getOpcode()) {
3913 case ISD::ANY_EXTEND:
3914 Tmp1 = PromoteOp(Node->getOperand(0));
3915 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
3917 case ISD::ZERO_EXTEND:
3918 Result = PromoteOp(Node->getOperand(0));
3919 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3920 Result = DAG.getZeroExtendInReg(Result,
3921 Node->getOperand(0).getValueType());
3923 case ISD::SIGN_EXTEND:
3924 Result = PromoteOp(Node->getOperand(0));
3925 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3926 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3928 DAG.getValueType(Node->getOperand(0).getValueType()));
3933 case ISD::FP_ROUND_INREG:
3934 case ISD::SIGN_EXTEND_INREG: {
3935 Tmp1 = LegalizeOp(Node->getOperand(0));
3936 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3938 // If this operation is not supported, convert it to a shl/shr or load/store
3940 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
3941 default: assert(0 && "This action not supported for this op yet!");
3942 case TargetLowering::Legal:
3943 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3945 case TargetLowering::Expand:
3946 // If this is an integer extend and shifts are supported, do that.
3947 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
3948 // NOTE: we could fall back on load/store here too for targets without
3949 // SAR. However, it is doubtful that any exist.
3950 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() -
3951 ExtraVT.getSizeInBits();
3952 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
3953 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
3954 Node->getOperand(0), ShiftCst);
3955 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
3957 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
3958 // The only way we can lower this is to turn it into a TRUNCSTORE,
3959 // EXTLOAD pair, targetting a temporary location (a stack slot).
3961 // NOTE: there is a choice here between constantly creating new stack
3962 // slots and always reusing the same one. We currently always create
3963 // new ones, as reuse may inhibit scheduling.
3964 Result = EmitStackConvert(Node->getOperand(0), ExtraVT,
3965 Node->getValueType(0));
3967 assert(0 && "Unknown op");
3973 case ISD::TRAMPOLINE: {
3975 for (unsigned i = 0; i != 6; ++i)
3976 Ops[i] = LegalizeOp(Node->getOperand(i));
3977 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
3978 // The only option for this node is to custom lower it.
3979 Result = TLI.LowerOperation(Result, DAG);
3980 assert(Result.Val && "Should always custom lower!");
3982 // Since trampoline produces two values, make sure to remember that we
3983 // legalized both of them.
3984 Tmp1 = LegalizeOp(Result.getValue(1));
3985 Result = LegalizeOp(Result);
3986 AddLegalizedOperand(SDOperand(Node, 0), Result);
3987 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
3988 return Op.ResNo ? Tmp1 : Result;
3990 case ISD::FLT_ROUNDS_: {
3991 MVT VT = Node->getValueType(0);
3992 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
3993 default: assert(0 && "This action not supported for this op yet!");
3994 case TargetLowering::Custom:
3995 Result = TLI.LowerOperation(Op, DAG);
3996 if (Result.Val) break;
3998 case TargetLowering::Legal:
3999 // If this operation is not supported, lower it to constant 1
4000 Result = DAG.getConstant(1, VT);
4006 MVT VT = Node->getValueType(0);
4007 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4008 default: assert(0 && "This action not supported for this op yet!");
4009 case TargetLowering::Legal:
4010 Tmp1 = LegalizeOp(Node->getOperand(0));
4011 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4013 case TargetLowering::Custom:
4014 Result = TLI.LowerOperation(Op, DAG);
4015 if (Result.Val) break;
4017 case TargetLowering::Expand:
4018 // If this operation is not supported, lower it to 'abort()' call
4019 Tmp1 = LegalizeOp(Node->getOperand(0));
4020 TargetLowering::ArgListTy Args;
4021 std::pair<SDOperand,SDOperand> CallResult =
4022 TLI.LowerCallTo(Tmp1, Type::VoidTy,
4023 false, false, false, CallingConv::C, false,
4024 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
4026 Result = CallResult.second;
4033 assert(Result.getValueType() == Op.getValueType() &&
4034 "Bad legalization!");
4036 // Make sure that the generated code is itself legal.
4038 Result = LegalizeOp(Result);
4040 // Note that LegalizeOp may be reentered even from single-use nodes, which
4041 // means that we always must cache transformed nodes.
4042 AddLegalizedOperand(Op, Result);
4046 /// PromoteOp - Given an operation that produces a value in an invalid type,
4047 /// promote it to compute the value into a larger type. The produced value will
4048 /// have the correct bits for the low portion of the register, but no guarantee
4049 /// is made about the top bits: it may be zero, sign-extended, or garbage.
4050 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
4051 MVT VT = Op.getValueType();
4052 MVT NVT = TLI.getTypeToTransformTo(VT);
4053 assert(getTypeAction(VT) == Promote &&
4054 "Caller should expand or legalize operands that are not promotable!");
4055 assert(NVT.bitsGT(VT) && NVT.isInteger() == VT.isInteger() &&
4056 "Cannot promote to smaller type!");
4058 SDOperand Tmp1, Tmp2, Tmp3;
4060 SDNode *Node = Op.Val;
4062 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
4063 if (I != PromotedNodes.end()) return I->second;
4065 switch (Node->getOpcode()) {
4066 case ISD::CopyFromReg:
4067 assert(0 && "CopyFromReg must be legal!");
4070 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
4072 assert(0 && "Do not know how to promote this operator!");
4075 Result = DAG.getNode(ISD::UNDEF, NVT);
4079 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
4081 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
4082 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
4084 case ISD::ConstantFP:
4085 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
4086 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
4090 assert(isTypeLegal(TLI.getSetCCResultType(Node->getOperand(0)))
4091 && "SetCC type is not legal??");
4092 Result = DAG.getNode(ISD::SETCC,
4093 TLI.getSetCCResultType(Node->getOperand(0)),
4094 Node->getOperand(0), Node->getOperand(1),
4095 Node->getOperand(2));
4099 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4101 Result = LegalizeOp(Node->getOperand(0));
4102 assert(Result.getValueType().bitsGE(NVT) &&
4103 "This truncation doesn't make sense!");
4104 if (Result.getValueType().bitsGT(NVT)) // Truncate to NVT instead of VT
4105 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
4108 // The truncation is not required, because we don't guarantee anything
4109 // about high bits anyway.
4110 Result = PromoteOp(Node->getOperand(0));
4113 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4114 // Truncate the low part of the expanded value to the result type
4115 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
4118 case ISD::SIGN_EXTEND:
4119 case ISD::ZERO_EXTEND:
4120 case ISD::ANY_EXTEND:
4121 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4122 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
4124 // Input is legal? Just do extend all the way to the larger type.
4125 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4128 // Promote the reg if it's smaller.
4129 Result = PromoteOp(Node->getOperand(0));
4130 // The high bits are not guaranteed to be anything. Insert an extend.
4131 if (Node->getOpcode() == ISD::SIGN_EXTEND)
4132 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4133 DAG.getValueType(Node->getOperand(0).getValueType()));
4134 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
4135 Result = DAG.getZeroExtendInReg(Result,
4136 Node->getOperand(0).getValueType());
4140 case ISD::BIT_CONVERT:
4141 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
4142 Node->getValueType(0));
4143 Result = PromoteOp(Result);
4146 case ISD::FP_EXTEND:
4147 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
4149 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4150 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
4151 case Promote: assert(0 && "Unreachable with 2 FP types!");
4153 if (Node->getConstantOperandVal(1) == 0) {
4154 // Input is legal? Do an FP_ROUND_INREG.
4155 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
4156 DAG.getValueType(VT));
4158 // Just remove the truncate, it isn't affecting the value.
4159 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0),
4160 Node->getOperand(1));
4165 case ISD::SINT_TO_FP:
4166 case ISD::UINT_TO_FP:
4167 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4169 // No extra round required here.
4170 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4174 Result = PromoteOp(Node->getOperand(0));
4175 if (Node->getOpcode() == ISD::SINT_TO_FP)
4176 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
4178 DAG.getValueType(Node->getOperand(0).getValueType()));
4180 Result = DAG.getZeroExtendInReg(Result,
4181 Node->getOperand(0).getValueType());
4182 // No extra round required here.
4183 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
4186 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
4187 Node->getOperand(0));
4188 // Round if we cannot tolerate excess precision.
4189 if (NoExcessFPPrecision)
4190 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4191 DAG.getValueType(VT));
4196 case ISD::SIGN_EXTEND_INREG:
4197 Result = PromoteOp(Node->getOperand(0));
4198 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4199 Node->getOperand(1));
4201 case ISD::FP_TO_SINT:
4202 case ISD::FP_TO_UINT:
4203 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4206 Tmp1 = Node->getOperand(0);
4209 // The input result is prerounded, so we don't have to do anything
4211 Tmp1 = PromoteOp(Node->getOperand(0));
4214 // If we're promoting a UINT to a larger size, check to see if the new node
4215 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
4216 // we can use that instead. This allows us to generate better code for
4217 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
4218 // legal, such as PowerPC.
4219 if (Node->getOpcode() == ISD::FP_TO_UINT &&
4220 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
4221 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
4222 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
4223 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
4225 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4231 Tmp1 = PromoteOp(Node->getOperand(0));
4232 assert(Tmp1.getValueType() == NVT);
4233 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4234 // NOTE: we do not have to do any extra rounding here for
4235 // NoExcessFPPrecision, because we know the input will have the appropriate
4236 // precision, and these operations don't modify precision at all.
4242 Tmp1 = PromoteOp(Node->getOperand(0));
4243 assert(Tmp1.getValueType() == NVT);
4244 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4245 if (NoExcessFPPrecision)
4246 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4247 DAG.getValueType(VT));
4251 // Promote f32 powi to f64 powi. Note that this could insert a libcall
4252 // directly as well, which may be better.
4253 Tmp1 = PromoteOp(Node->getOperand(0));
4254 assert(Tmp1.getValueType() == NVT);
4255 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1));
4256 if (NoExcessFPPrecision)
4257 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4258 DAG.getValueType(VT));
4262 case ISD::ATOMIC_CMP_SWAP: {
4263 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4264 Tmp2 = PromoteOp(Node->getOperand(2));
4265 Tmp3 = PromoteOp(Node->getOperand(3));
4266 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(),
4267 AtomNode->getBasePtr(), Tmp2, Tmp3,
4268 AtomNode->getSrcValue(),
4269 AtomNode->getAlignment());
4270 // Remember that we legalized the chain.
4271 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4274 case ISD::ATOMIC_LOAD_ADD:
4275 case ISD::ATOMIC_LOAD_SUB:
4276 case ISD::ATOMIC_LOAD_AND:
4277 case ISD::ATOMIC_LOAD_OR:
4278 case ISD::ATOMIC_LOAD_XOR:
4279 case ISD::ATOMIC_LOAD_NAND:
4280 case ISD::ATOMIC_LOAD_MIN:
4281 case ISD::ATOMIC_LOAD_MAX:
4282 case ISD::ATOMIC_LOAD_UMIN:
4283 case ISD::ATOMIC_LOAD_UMAX:
4284 case ISD::ATOMIC_SWAP: {
4285 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4286 Tmp2 = PromoteOp(Node->getOperand(2));
4287 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(),
4288 AtomNode->getBasePtr(), Tmp2,
4289 AtomNode->getSrcValue(),
4290 AtomNode->getAlignment());
4291 // Remember that we legalized the chain.
4292 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4302 // The input may have strange things in the top bits of the registers, but
4303 // these operations don't care. They may have weird bits going out, but
4304 // that too is okay if they are integer operations.
4305 Tmp1 = PromoteOp(Node->getOperand(0));
4306 Tmp2 = PromoteOp(Node->getOperand(1));
4307 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4308 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4313 Tmp1 = PromoteOp(Node->getOperand(0));
4314 Tmp2 = PromoteOp(Node->getOperand(1));
4315 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4316 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4318 // Floating point operations will give excess precision that we may not be
4319 // able to tolerate. If we DO allow excess precision, just leave it,
4320 // otherwise excise it.
4321 // FIXME: Why would we need to round FP ops more than integer ones?
4322 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
4323 if (NoExcessFPPrecision)
4324 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4325 DAG.getValueType(VT));
4330 // These operators require that their input be sign extended.
4331 Tmp1 = PromoteOp(Node->getOperand(0));
4332 Tmp2 = PromoteOp(Node->getOperand(1));
4333 if (NVT.isInteger()) {
4334 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4335 DAG.getValueType(VT));
4336 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4337 DAG.getValueType(VT));
4339 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4341 // Perform FP_ROUND: this is probably overly pessimistic.
4342 if (NVT.isFloatingPoint() && NoExcessFPPrecision)
4343 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4344 DAG.getValueType(VT));
4348 case ISD::FCOPYSIGN:
4349 // These operators require that their input be fp extended.
4350 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4351 case Expand: assert(0 && "not implemented");
4352 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break;
4353 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break;
4355 switch (getTypeAction(Node->getOperand(1).getValueType())) {
4356 case Expand: assert(0 && "not implemented");
4357 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
4358 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
4360 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4362 // Perform FP_ROUND: this is probably overly pessimistic.
4363 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
4364 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4365 DAG.getValueType(VT));
4370 // These operators require that their input be zero extended.
4371 Tmp1 = PromoteOp(Node->getOperand(0));
4372 Tmp2 = PromoteOp(Node->getOperand(1));
4373 assert(NVT.isInteger() && "Operators don't apply to FP!");
4374 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4375 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4376 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4380 Tmp1 = PromoteOp(Node->getOperand(0));
4381 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
4384 // The input value must be properly sign extended.
4385 Tmp1 = PromoteOp(Node->getOperand(0));
4386 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4387 DAG.getValueType(VT));
4388 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
4391 // The input value must be properly zero extended.
4392 Tmp1 = PromoteOp(Node->getOperand(0));
4393 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4394 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
4398 Tmp1 = Node->getOperand(0); // Get the chain.
4399 Tmp2 = Node->getOperand(1); // Get the pointer.
4400 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
4401 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
4402 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
4404 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
4405 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
4406 // Increment the pointer, VAList, to the next vaarg
4407 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
4408 DAG.getConstant(VT.getSizeInBits()/8,
4409 TLI.getPointerTy()));
4410 // Store the incremented VAList to the legalized pointer
4411 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
4412 // Load the actual argument out of the pointer VAList
4413 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
4415 // Remember that we legalized the chain.
4416 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4420 LoadSDNode *LD = cast<LoadSDNode>(Node);
4421 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
4422 ? ISD::EXTLOAD : LD->getExtensionType();
4423 Result = DAG.getExtLoad(ExtType, NVT,
4424 LD->getChain(), LD->getBasePtr(),
4425 LD->getSrcValue(), LD->getSrcValueOffset(),
4428 LD->getAlignment());
4429 // Remember that we legalized the chain.
4430 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4434 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
4435 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
4437 MVT VT2 = Tmp2.getValueType();
4438 assert(VT2 == Tmp3.getValueType()
4439 && "PromoteOp SELECT: Operands 2 and 3 ValueTypes don't match");
4440 // Ensure that the resulting node is at least the same size as the operands'
4441 // value types, because we cannot assume that TLI.getSetCCValueType() is
4443 Result = DAG.getNode(ISD::SELECT, VT2, Node->getOperand(0), Tmp2, Tmp3);
4446 case ISD::SELECT_CC:
4447 Tmp2 = PromoteOp(Node->getOperand(2)); // True
4448 Tmp3 = PromoteOp(Node->getOperand(3)); // False
4449 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4450 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
4453 Tmp1 = Node->getOperand(0);
4454 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
4455 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
4456 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
4457 DAG.getConstant(NVT.getSizeInBits() -
4459 TLI.getShiftAmountTy()));
4464 // Zero extend the argument
4465 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4466 // Perform the larger operation, then subtract if needed.
4467 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4468 switch(Node->getOpcode()) {
4473 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
4474 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
4475 DAG.getConstant(NVT.getSizeInBits(), NVT),
4477 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
4478 DAG.getConstant(VT.getSizeInBits(), NVT), Tmp1);
4481 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4482 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
4483 DAG.getConstant(NVT.getSizeInBits() -
4484 VT.getSizeInBits(), NVT));
4488 case ISD::EXTRACT_SUBVECTOR:
4489 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
4491 case ISD::EXTRACT_VECTOR_ELT:
4492 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
4496 assert(Result.Val && "Didn't set a result!");
4498 // Make sure the result is itself legal.
4499 Result = LegalizeOp(Result);
4501 // Remember that we promoted this!
4502 AddPromotedOperand(Op, Result);
4506 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
4507 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
4508 /// based on the vector type. The return type of this matches the element type
4509 /// of the vector, which may not be legal for the target.
4510 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
4511 // We know that operand #0 is the Vec vector. If the index is a constant
4512 // or if the invec is a supported hardware type, we can use it. Otherwise,
4513 // lower to a store then an indexed load.
4514 SDOperand Vec = Op.getOperand(0);
4515 SDOperand Idx = Op.getOperand(1);
4517 MVT TVT = Vec.getValueType();
4518 unsigned NumElems = TVT.getVectorNumElements();
4520 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
4521 default: assert(0 && "This action is not supported yet!");
4522 case TargetLowering::Custom: {
4523 Vec = LegalizeOp(Vec);
4524 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4525 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG);
4530 case TargetLowering::Legal:
4531 if (isTypeLegal(TVT)) {
4532 Vec = LegalizeOp(Vec);
4533 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4537 case TargetLowering::Expand:
4541 if (NumElems == 1) {
4542 // This must be an access of the only element. Return it.
4543 Op = ScalarizeVectorOp(Vec);
4544 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
4545 unsigned NumLoElts = 1 << Log2_32(NumElems-1);
4546 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4548 SplitVectorOp(Vec, Lo, Hi);
4549 if (CIdx->getValue() < NumLoElts) {
4553 Idx = DAG.getConstant(CIdx->getValue() - NumLoElts,
4554 Idx.getValueType());
4557 // It's now an extract from the appropriate high or low part. Recurse.
4558 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4559 Op = ExpandEXTRACT_VECTOR_ELT(Op);
4561 // Store the value to a temporary stack slot, then LOAD the scalar
4562 // element back out.
4563 SDOperand StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
4564 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
4566 // Add the offset to the index.
4567 unsigned EltSize = Op.getValueType().getSizeInBits()/8;
4568 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
4569 DAG.getConstant(EltSize, Idx.getValueType()));
4571 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
4572 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx);
4574 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
4576 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
4578 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
4583 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
4584 /// we assume the operation can be split if it is not already legal.
4585 SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) {
4586 // We know that operand #0 is the Vec vector. For now we assume the index
4587 // is a constant and that the extracted result is a supported hardware type.
4588 SDOperand Vec = Op.getOperand(0);
4589 SDOperand Idx = LegalizeOp(Op.getOperand(1));
4591 unsigned NumElems = Vec.getValueType().getVectorNumElements();
4593 if (NumElems == Op.getValueType().getVectorNumElements()) {
4594 // This must be an access of the desired vector length. Return it.
4598 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4600 SplitVectorOp(Vec, Lo, Hi);
4601 if (CIdx->getValue() < NumElems/2) {
4605 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
4608 // It's now an extract from the appropriate high or low part. Recurse.
4609 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4610 return ExpandEXTRACT_SUBVECTOR(Op);
4613 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
4614 /// with condition CC on the current target. This usually involves legalizing
4615 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
4616 /// there may be no choice but to create a new SetCC node to represent the
4617 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
4618 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
4619 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
4622 SDOperand Tmp1, Tmp2, Tmp3, Result;
4624 switch (getTypeAction(LHS.getValueType())) {
4626 Tmp1 = LegalizeOp(LHS); // LHS
4627 Tmp2 = LegalizeOp(RHS); // RHS
4630 Tmp1 = PromoteOp(LHS); // LHS
4631 Tmp2 = PromoteOp(RHS); // RHS
4633 // If this is an FP compare, the operands have already been extended.
4634 if (LHS.getValueType().isInteger()) {
4635 MVT VT = LHS.getValueType();
4636 MVT NVT = TLI.getTypeToTransformTo(VT);
4638 // Otherwise, we have to insert explicit sign or zero extends. Note
4639 // that we could insert sign extends for ALL conditions, but zero extend
4640 // is cheaper on many machines (an AND instead of two shifts), so prefer
4642 switch (cast<CondCodeSDNode>(CC)->get()) {
4643 default: assert(0 && "Unknown integer comparison!");
4650 // ALL of these operations will work if we either sign or zero extend
4651 // the operands (including the unsigned comparisons!). Zero extend is
4652 // usually a simpler/cheaper operation, so prefer it.
4653 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4654 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4660 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4661 DAG.getValueType(VT));
4662 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4663 DAG.getValueType(VT));
4669 MVT VT = LHS.getValueType();
4670 if (VT == MVT::f32 || VT == MVT::f64) {
4671 // Expand into one or more soft-fp libcall(s).
4672 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
4673 switch (cast<CondCodeSDNode>(CC)->get()) {
4676 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4680 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
4684 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4688 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4692 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4696 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4699 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4702 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
4705 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4706 switch (cast<CondCodeSDNode>(CC)->get()) {
4708 // SETONE = SETOLT | SETOGT
4709 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4712 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4715 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4718 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4721 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4724 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4726 default: assert(0 && "Unsupported FP setcc!");
4731 Tmp1 = ExpandLibCall(LC1,
4732 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4733 false /*sign irrelevant*/, Dummy);
4734 Tmp2 = DAG.getConstant(0, MVT::i32);
4735 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
4736 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
4737 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
4739 LHS = ExpandLibCall(LC2,
4740 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4741 false /*sign irrelevant*/, Dummy);
4742 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, Tmp2,
4743 DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
4744 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4752 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
4753 ExpandOp(LHS, LHSLo, LHSHi);
4754 ExpandOp(RHS, RHSLo, RHSHi);
4755 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
4757 if (VT==MVT::ppcf128) {
4758 // FIXME: This generated code sucks. We want to generate
4759 // FCMP crN, hi1, hi2
4761 // FCMP crN, lo1, lo2
4762 // The following can be improved, but not that much.
4763 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETEQ);
4764 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, CCCode);
4765 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4766 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETNE);
4767 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode);
4768 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4769 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
4778 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
4779 if (RHSCST->isAllOnesValue()) {
4780 // Comparison to -1.
4781 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
4786 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
4787 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
4788 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4789 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
4792 // If this is a comparison of the sign bit, just look at the top part.
4794 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
4795 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
4796 CST->isNullValue()) || // X < 0
4797 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
4798 CST->isAllOnesValue())) { // X > -1
4804 // FIXME: This generated code sucks.
4805 ISD::CondCode LowCC;
4807 default: assert(0 && "Unknown integer setcc!");
4809 case ISD::SETULT: LowCC = ISD::SETULT; break;
4811 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
4813 case ISD::SETULE: LowCC = ISD::SETULE; break;
4815 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
4818 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
4819 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
4820 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
4822 // NOTE: on targets without efficient SELECT of bools, we can always use
4823 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
4824 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
4825 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo,
4826 LowCC, false, DagCombineInfo);
4828 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC);
4829 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4830 CCCode, false, DagCombineInfo);
4832 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi,
4835 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
4836 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
4837 if ((Tmp1C && Tmp1C->isNullValue()) ||
4838 (Tmp2C && Tmp2C->isNullValue() &&
4839 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
4840 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
4841 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
4842 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
4843 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
4844 // low part is known false, returns high part.
4845 // For LE / GE, if high part is known false, ignore the low part.
4846 // For LT / GT, if high part is known true, ignore the low part.
4850 Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4851 ISD::SETEQ, false, DagCombineInfo);
4853 Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4855 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
4856 Result, Tmp1, Tmp2));
4867 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
4868 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
4869 /// a load from the stack slot to DestVT, extending it if needed.
4870 /// The resultant code need not be legal.
4871 SDOperand SelectionDAGLegalize::EmitStackConvert(SDOperand SrcOp,
4874 // Create the stack frame object.
4875 SDOperand FIPtr = DAG.CreateStackTemporary(SlotVT);
4877 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
4878 int SPFI = StackPtrFI->getIndex();
4880 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
4881 unsigned SlotSize = SlotVT.getSizeInBits();
4882 unsigned DestSize = DestVT.getSizeInBits();
4884 // Emit a store to the stack slot. Use a truncstore if the input value is
4885 // later than DestVT.
4887 if (SrcSize > SlotSize)
4888 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr,
4889 PseudoSourceValue::getFixedStack(),
4892 assert(SrcSize == SlotSize && "Invalid store");
4893 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr,
4894 PseudoSourceValue::getFixedStack(),
4898 // Result is a load from the stack slot.
4899 if (SlotSize == DestSize)
4900 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0);
4902 assert(SlotSize < DestSize && "Unknown extension!");
4903 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT);
4906 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
4907 // Create a vector sized/aligned stack slot, store the value to element #0,
4908 // then load the whole vector back out.
4909 SDOperand StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
4911 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
4912 int SPFI = StackPtrFI->getIndex();
4914 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
4915 PseudoSourceValue::getFixedStack(), SPFI);
4916 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,
4917 PseudoSourceValue::getFixedStack(), SPFI);
4921 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
4922 /// support the operation, but do support the resultant vector type.
4923 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
4925 // If the only non-undef value is the low element, turn this into a
4926 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
4927 unsigned NumElems = Node->getNumOperands();
4928 bool isOnlyLowElement = true;
4929 SDOperand SplatValue = Node->getOperand(0);
4931 // FIXME: it would be far nicer to change this into map<SDOperand,uint64_t>
4932 // and use a bitmask instead of a list of elements.
4933 std::map<SDOperand, std::vector<unsigned> > Values;
4934 Values[SplatValue].push_back(0);
4935 bool isConstant = true;
4936 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
4937 SplatValue.getOpcode() != ISD::UNDEF)
4940 for (unsigned i = 1; i < NumElems; ++i) {
4941 SDOperand V = Node->getOperand(i);
4942 Values[V].push_back(i);
4943 if (V.getOpcode() != ISD::UNDEF)
4944 isOnlyLowElement = false;
4945 if (SplatValue != V)
4946 SplatValue = SDOperand(0,0);
4948 // If this isn't a constant element or an undef, we can't use a constant
4950 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
4951 V.getOpcode() != ISD::UNDEF)
4955 if (isOnlyLowElement) {
4956 // If the low element is an undef too, then this whole things is an undef.
4957 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
4958 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
4959 // Otherwise, turn this into a scalar_to_vector node.
4960 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4961 Node->getOperand(0));
4964 // If all elements are constants, create a load from the constant pool.
4966 MVT VT = Node->getValueType(0);
4967 std::vector<Constant*> CV;
4968 for (unsigned i = 0, e = NumElems; i != e; ++i) {
4969 if (ConstantFPSDNode *V =
4970 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
4971 CV.push_back(ConstantFP::get(V->getValueAPF()));
4972 } else if (ConstantSDNode *V =
4973 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
4974 CV.push_back(ConstantInt::get(V->getAPIntValue()));
4976 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
4978 Node->getOperand(0).getValueType().getTypeForMVT();
4979 CV.push_back(UndefValue::get(OpNTy));
4982 Constant *CP = ConstantVector::get(CV);
4983 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
4984 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4985 PseudoSourceValue::getConstantPool(), 0);
4988 if (SplatValue.Val) { // Splat of one value?
4989 // Build the shuffle constant vector: <0, 0, 0, 0>
4990 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
4991 SDOperand Zero = DAG.getConstant(0, MaskVT.getVectorElementType());
4992 std::vector<SDOperand> ZeroVec(NumElems, Zero);
4993 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4994 &ZeroVec[0], ZeroVec.size());
4996 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4997 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
4998 // Get the splatted value into the low element of a vector register.
4999 SDOperand LowValVec =
5000 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
5002 // Return shuffle(LowValVec, undef, <0,0,0,0>)
5003 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
5004 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
5009 // If there are only two unique elements, we may be able to turn this into a
5011 if (Values.size() == 2) {
5012 // Get the two values in deterministic order.
5013 SDOperand Val1 = Node->getOperand(1);
5015 std::map<SDOperand, std::vector<unsigned> >::iterator MI = Values.begin();
5016 if (MI->first != Val1)
5019 Val2 = (++MI)->first;
5021 // If Val1 is an undef, make sure end ends up as Val2, to ensure that our
5022 // vector shuffle has the undef vector on the RHS.
5023 if (Val1.getOpcode() == ISD::UNDEF)
5024 std::swap(Val1, Val2);
5026 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
5027 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
5028 MVT MaskEltVT = MaskVT.getVectorElementType();
5029 std::vector<SDOperand> MaskVec(NumElems);
5031 // Set elements of the shuffle mask for Val1.
5032 std::vector<unsigned> &Val1Elts = Values[Val1];
5033 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i)
5034 MaskVec[Val1Elts[i]] = DAG.getConstant(0, MaskEltVT);
5036 // Set elements of the shuffle mask for Val2.
5037 std::vector<unsigned> &Val2Elts = Values[Val2];
5038 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i)
5039 if (Val2.getOpcode() != ISD::UNDEF)
5040 MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT);
5042 MaskVec[Val2Elts[i]] = DAG.getNode(ISD::UNDEF, MaskEltVT);
5044 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
5045 &MaskVec[0], MaskVec.size());
5047 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it.
5048 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
5049 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
5050 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val1);
5051 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val2);
5052 SDOperand Ops[] = { Val1, Val2, ShuffleMask };
5054 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
5055 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops, 3);
5059 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
5060 // aligned object on the stack, store each element into it, then load
5061 // the result as a vector.
5062 MVT VT = Node->getValueType(0);
5063 // Create the stack frame object.
5064 SDOperand FIPtr = DAG.CreateStackTemporary(VT);
5066 // Emit a store of each element to the stack slot.
5067 SmallVector<SDOperand, 8> Stores;
5068 unsigned TypeByteSize = Node->getOperand(0).getValueType().getSizeInBits()/8;
5069 // Store (in the right endianness) the elements to memory.
5070 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5071 // Ignore undef elements.
5072 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
5074 unsigned Offset = TypeByteSize*i;
5076 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
5077 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
5079 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
5083 SDOperand StoreChain;
5084 if (!Stores.empty()) // Not all undef elements?
5085 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
5086 &Stores[0], Stores.size());
5088 StoreChain = DAG.getEntryNode();
5090 // Result is a load from the stack slot.
5091 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
5094 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
5095 SDOperand Op, SDOperand Amt,
5096 SDOperand &Lo, SDOperand &Hi) {
5097 // Expand the subcomponents.
5098 SDOperand LHSL, LHSH;
5099 ExpandOp(Op, LHSL, LHSH);
5101 SDOperand Ops[] = { LHSL, LHSH, Amt };
5102 MVT VT = LHSL.getValueType();
5103 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
5104 Hi = Lo.getValue(1);
5108 /// ExpandShift - Try to find a clever way to expand this shift operation out to
5109 /// smaller elements. If we can't find a way that is more efficient than a
5110 /// libcall on this target, return false. Otherwise, return true with the
5111 /// low-parts expanded into Lo and Hi.
5112 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
5113 SDOperand &Lo, SDOperand &Hi) {
5114 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
5115 "This is not a shift!");
5117 MVT NVT = TLI.getTypeToTransformTo(Op.getValueType());
5118 SDOperand ShAmt = LegalizeOp(Amt);
5119 MVT ShTy = ShAmt.getValueType();
5120 unsigned ShBits = ShTy.getSizeInBits();
5121 unsigned VTBits = Op.getValueType().getSizeInBits();
5122 unsigned NVTBits = NVT.getSizeInBits();
5124 // Handle the case when Amt is an immediate.
5125 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
5126 unsigned Cst = CN->getValue();
5127 // Expand the incoming operand to be shifted, so that we have its parts
5129 ExpandOp(Op, InL, InH);
5133 Lo = DAG.getConstant(0, NVT);
5134 Hi = DAG.getConstant(0, NVT);
5135 } else if (Cst > NVTBits) {
5136 Lo = DAG.getConstant(0, NVT);
5137 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
5138 } else if (Cst == NVTBits) {
5139 Lo = DAG.getConstant(0, NVT);
5142 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
5143 Hi = DAG.getNode(ISD::OR, NVT,
5144 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
5145 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
5150 Lo = DAG.getConstant(0, NVT);
5151 Hi = DAG.getConstant(0, NVT);
5152 } else if (Cst > NVTBits) {
5153 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
5154 Hi = DAG.getConstant(0, NVT);
5155 } else if (Cst == NVTBits) {
5157 Hi = DAG.getConstant(0, NVT);
5159 Lo = DAG.getNode(ISD::OR, NVT,
5160 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5161 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5162 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
5167 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
5168 DAG.getConstant(NVTBits-1, ShTy));
5169 } else if (Cst > NVTBits) {
5170 Lo = DAG.getNode(ISD::SRA, NVT, InH,
5171 DAG.getConstant(Cst-NVTBits, ShTy));
5172 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5173 DAG.getConstant(NVTBits-1, ShTy));
5174 } else if (Cst == NVTBits) {
5176 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5177 DAG.getConstant(NVTBits-1, ShTy));
5179 Lo = DAG.getNode(ISD::OR, NVT,
5180 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5181 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5182 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
5188 // Okay, the shift amount isn't constant. However, if we can tell that it is
5189 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
5190 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
5191 APInt KnownZero, KnownOne;
5192 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
5194 // If we know that if any of the high bits of the shift amount are one, then
5195 // we can do this as a couple of simple shifts.
5196 if (KnownOne.intersects(Mask)) {
5197 // Mask out the high bit, which we know is set.
5198 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
5199 DAG.getConstant(~Mask, Amt.getValueType()));
5201 // Expand the incoming operand to be shifted, so that we have its parts
5203 ExpandOp(Op, InL, InH);
5206 Lo = DAG.getConstant(0, NVT); // Low part is zero.
5207 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
5210 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
5211 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
5214 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
5215 DAG.getConstant(NVTBits-1, Amt.getValueType()));
5216 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
5221 // If we know that the high bits of the shift amount are all zero, then we can
5222 // do this as a couple of simple shifts.
5223 if ((KnownZero & Mask) == Mask) {
5225 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
5226 DAG.getConstant(NVTBits, Amt.getValueType()),
5229 // Expand the incoming operand to be shifted, so that we have its parts
5231 ExpandOp(Op, InL, InH);
5234 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
5235 Hi = DAG.getNode(ISD::OR, NVT,
5236 DAG.getNode(ISD::SHL, NVT, InH, Amt),
5237 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
5240 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
5241 Lo = DAG.getNode(ISD::OR, NVT,
5242 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5243 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5246 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
5247 Lo = DAG.getNode(ISD::OR, NVT,
5248 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5249 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5258 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
5259 // does not fit into a register, return the lo part and set the hi part to the
5260 // by-reg argument. If it does fit into a single register, return the result
5261 // and leave the Hi part unset.
5262 SDOperand SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
5263 bool isSigned, SDOperand &Hi) {
5264 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
5265 // The input chain to this libcall is the entry node of the function.
5266 // Legalizing the call will automatically add the previous call to the
5268 SDOperand InChain = DAG.getEntryNode();
5270 TargetLowering::ArgListTy Args;
5271 TargetLowering::ArgListEntry Entry;
5272 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5273 MVT ArgVT = Node->getOperand(i).getValueType();
5274 const Type *ArgTy = ArgVT.getTypeForMVT();
5275 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
5276 Entry.isSExt = isSigned;
5277 Entry.isZExt = !isSigned;
5278 Args.push_back(Entry);
5280 SDOperand Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
5281 TLI.getPointerTy());
5283 // Splice the libcall in wherever FindInputOutputChains tells us to.
5284 const Type *RetTy = Node->getValueType(0).getTypeForMVT();
5285 std::pair<SDOperand,SDOperand> CallInfo =
5286 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, CallingConv::C,
5287 false, Callee, Args, DAG);
5289 // Legalize the call sequence, starting with the chain. This will advance
5290 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
5291 // was added by LowerCallTo (guaranteeing proper serialization of calls).
5292 LegalizeOp(CallInfo.second);
5294 switch (getTypeAction(CallInfo.first.getValueType())) {
5295 default: assert(0 && "Unknown thing");
5297 Result = CallInfo.first;
5300 ExpandOp(CallInfo.first, Result, Hi);
5307 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
5309 SDOperand SelectionDAGLegalize::
5310 ExpandIntToFP(bool isSigned, MVT DestTy, SDOperand Source) {
5311 MVT SourceVT = Source.getValueType();
5312 bool ExpandSource = getTypeAction(SourceVT) == Expand;
5314 // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc.
5315 if (!isSigned && SourceVT != MVT::i32) {
5316 // The integer value loaded will be incorrectly if the 'sign bit' of the
5317 // incoming integer is set. To handle this, we dynamically test to see if
5318 // it is set, and, if so, add a fudge factor.
5322 ExpandOp(Source, Lo, Hi);
5323 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi);
5325 // The comparison for the sign bit will use the entire operand.
5329 // If this is unsigned, and not supported, first perform the conversion to
5330 // signed, then adjust the result if the sign bit is set.
5331 SDOperand SignedConv = ExpandIntToFP(true, DestTy, Source);
5333 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
5334 DAG.getConstant(0, Hi.getValueType()),
5336 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5337 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5338 SignSet, Four, Zero);
5339 uint64_t FF = 0x5f800000ULL;
5340 if (TLI.isLittleEndian()) FF <<= 32;
5341 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5343 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5344 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5345 SDOperand FudgeInReg;
5346 if (DestTy == MVT::f32)
5347 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5348 PseudoSourceValue::getConstantPool(), 0);
5349 else if (DestTy.bitsGT(MVT::f32))
5350 // FIXME: Avoid the extend by construction the right constantpool?
5351 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
5353 PseudoSourceValue::getConstantPool(), 0,
5356 assert(0 && "Unexpected conversion");
5358 MVT SCVT = SignedConv.getValueType();
5359 if (SCVT != DestTy) {
5360 // Destination type needs to be expanded as well. The FADD now we are
5361 // constructing will be expanded into a libcall.
5362 if (SCVT.getSizeInBits() != DestTy.getSizeInBits()) {
5363 assert(SCVT.getSizeInBits() * 2 == DestTy.getSizeInBits());
5364 SignedConv = DAG.getNode(ISD::BUILD_PAIR, DestTy,
5365 SignedConv, SignedConv.getValue(1));
5367 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
5369 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
5372 // Check to see if the target has a custom way to lower this. If so, use it.
5373 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) {
5374 default: assert(0 && "This action not implemented for this operation!");
5375 case TargetLowering::Legal:
5376 case TargetLowering::Expand:
5377 break; // This case is handled below.
5378 case TargetLowering::Custom: {
5379 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
5382 return LegalizeOp(NV);
5383 break; // The target decided this was legal after all
5387 // Expand the source, then glue it back together for the call. We must expand
5388 // the source in case it is shared (this pass of legalize must traverse it).
5390 SDOperand SrcLo, SrcHi;
5391 ExpandOp(Source, SrcLo, SrcHi);
5392 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, SrcLo, SrcHi);
5396 if (SourceVT == MVT::i32) {
5397 if (DestTy == MVT::f32)
5398 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32;
5400 assert(DestTy == MVT::f64 && "Unknown fp value type!");
5401 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64;
5403 } else if (SourceVT == MVT::i64) {
5404 if (DestTy == MVT::f32)
5405 LC = RTLIB::SINTTOFP_I64_F32;
5406 else if (DestTy == MVT::f64)
5407 LC = RTLIB::SINTTOFP_I64_F64;
5408 else if (DestTy == MVT::f80)
5409 LC = RTLIB::SINTTOFP_I64_F80;
5411 assert(DestTy == MVT::ppcf128 && "Unknown fp value type!");
5412 LC = RTLIB::SINTTOFP_I64_PPCF128;
5414 } else if (SourceVT == MVT::i128) {
5415 if (DestTy == MVT::f32)
5416 LC = RTLIB::SINTTOFP_I128_F32;
5417 else if (DestTy == MVT::f64)
5418 LC = RTLIB::SINTTOFP_I128_F64;
5419 else if (DestTy == MVT::f80)
5420 LC = RTLIB::SINTTOFP_I128_F80;
5422 assert(DestTy == MVT::ppcf128 && "Unknown fp value type!");
5423 LC = RTLIB::SINTTOFP_I128_PPCF128;
5426 assert(0 && "Unknown int value type");
5429 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!");
5430 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
5432 SDOperand Result = ExpandLibCall(LC, Source.Val, isSigned, HiPart);
5433 if (Result.getValueType() != DestTy && HiPart.Val)
5434 Result = DAG.getNode(ISD::BUILD_PAIR, DestTy, Result, HiPart);
5438 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
5439 /// INT_TO_FP operation of the specified operand when the target requests that
5440 /// we expand it. At this point, we know that the result and operand types are
5441 /// legal for the target.
5442 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
5445 if (Op0.getValueType() == MVT::i32) {
5446 // simple 32-bit [signed|unsigned] integer to float/double expansion
5448 // Get the stack frame index of a 8 byte buffer.
5449 SDOperand StackSlot = DAG.CreateStackTemporary(MVT::f64);
5451 // word offset constant for Hi/Lo address computation
5452 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
5453 // set up Hi and Lo (into buffer) address based on endian
5454 SDOperand Hi = StackSlot;
5455 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
5456 if (TLI.isLittleEndian())
5459 // if signed map to unsigned space
5460 SDOperand Op0Mapped;
5462 // constant used to invert sign bit (signed to unsigned mapping)
5463 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
5464 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
5468 // store the lo of the constructed double - based on integer input
5469 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(),
5470 Op0Mapped, Lo, NULL, 0);
5471 // initial hi portion of constructed double
5472 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
5473 // store the hi of the constructed double - biased exponent
5474 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
5475 // load the constructed double
5476 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
5477 // FP constant to bias correct the final result
5478 SDOperand Bias = DAG.getConstantFP(isSigned ?
5479 BitsToDouble(0x4330000080000000ULL)
5480 : BitsToDouble(0x4330000000000000ULL),
5482 // subtract the bias
5483 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
5486 // handle final rounding
5487 if (DestVT == MVT::f64) {
5490 } else if (DestVT.bitsLT(MVT::f64)) {
5491 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub,
5492 DAG.getIntPtrConstant(0));
5493 } else if (DestVT.bitsGT(MVT::f64)) {
5494 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
5498 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
5499 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
5501 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Op0), Op0,
5502 DAG.getConstant(0, Op0.getValueType()),
5504 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5505 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5506 SignSet, Four, Zero);
5508 // If the sign bit of the integer is set, the large number will be treated
5509 // as a negative number. To counteract this, the dynamic code adds an
5510 // offset depending on the data type.
5512 switch (Op0.getValueType().getSimpleVT()) {
5513 default: assert(0 && "Unsupported integer type!");
5514 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
5515 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
5516 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
5517 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
5519 if (TLI.isLittleEndian()) FF <<= 32;
5520 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5522 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5523 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5524 SDOperand FudgeInReg;
5525 if (DestVT == MVT::f32)
5526 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5527 PseudoSourceValue::getConstantPool(), 0);
5530 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT,
5531 DAG.getEntryNode(), CPIdx,
5532 PseudoSourceValue::getConstantPool(), 0,
5536 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
5539 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
5540 /// *INT_TO_FP operation of the specified operand when the target requests that
5541 /// we promote it. At this point, we know that the result and operand types are
5542 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
5543 /// operation that takes a larger input.
5544 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
5547 // First step, figure out the appropriate *INT_TO_FP operation to use.
5548 MVT NewInTy = LegalOp.getValueType();
5550 unsigned OpToUse = 0;
5552 // Scan for the appropriate larger type to use.
5554 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
5555 assert(NewInTy.isInteger() && "Ran out of possibilities!");
5557 // If the target supports SINT_TO_FP of this type, use it.
5558 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
5560 case TargetLowering::Legal:
5561 if (!TLI.isTypeLegal(NewInTy))
5562 break; // Can't use this datatype.
5564 case TargetLowering::Custom:
5565 OpToUse = ISD::SINT_TO_FP;
5569 if (isSigned) continue;
5571 // If the target supports UINT_TO_FP of this type, use it.
5572 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
5574 case TargetLowering::Legal:
5575 if (!TLI.isTypeLegal(NewInTy))
5576 break; // Can't use this datatype.
5578 case TargetLowering::Custom:
5579 OpToUse = ISD::UINT_TO_FP;
5584 // Otherwise, try a larger type.
5587 // Okay, we found the operation and type to use. Zero extend our input to the
5588 // desired type then run the operation on it.
5589 return DAG.getNode(OpToUse, DestVT,
5590 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
5594 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
5595 /// FP_TO_*INT operation of the specified operand when the target requests that
5596 /// we promote it. At this point, we know that the result and operand types are
5597 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
5598 /// operation that returns a larger result.
5599 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
5602 // First step, figure out the appropriate FP_TO*INT operation to use.
5603 MVT NewOutTy = DestVT;
5605 unsigned OpToUse = 0;
5607 // Scan for the appropriate larger type to use.
5609 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1);
5610 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
5612 // If the target supports FP_TO_SINT returning this type, use it.
5613 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
5615 case TargetLowering::Legal:
5616 if (!TLI.isTypeLegal(NewOutTy))
5617 break; // Can't use this datatype.
5619 case TargetLowering::Custom:
5620 OpToUse = ISD::FP_TO_SINT;
5625 // If the target supports FP_TO_UINT of this type, use it.
5626 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
5628 case TargetLowering::Legal:
5629 if (!TLI.isTypeLegal(NewOutTy))
5630 break; // Can't use this datatype.
5632 case TargetLowering::Custom:
5633 OpToUse = ISD::FP_TO_UINT;
5638 // Otherwise, try a larger type.
5642 // Okay, we found the operation and type to use.
5643 SDOperand Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp);
5645 // If the operation produces an invalid type, it must be custom lowered. Use
5646 // the target lowering hooks to expand it. Just keep the low part of the
5647 // expanded operation, we know that we're truncating anyway.
5648 if (getTypeAction(NewOutTy) == Expand) {
5649 Operation = SDOperand(TLI.ExpandOperationResult(Operation.Val, DAG), 0);
5650 assert(Operation.Val && "Didn't return anything");
5653 // Truncate the result of the extended FP_TO_*INT operation to the desired
5655 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation);
5658 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
5660 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
5661 MVT VT = Op.getValueType();
5662 MVT SHVT = TLI.getShiftAmountTy();
5663 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
5664 switch (VT.getSimpleVT()) {
5665 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
5667 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5668 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5669 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
5671 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5672 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5673 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5674 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5675 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
5676 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
5677 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5678 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5679 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5681 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
5682 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
5683 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5684 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5685 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5686 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5687 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
5688 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
5689 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
5690 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
5691 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
5692 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
5693 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
5694 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
5695 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
5696 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
5697 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5698 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5699 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
5700 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5701 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
5705 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
5707 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
5709 default: assert(0 && "Cannot expand this yet!");
5711 static const uint64_t mask[6] = {
5712 0x5555555555555555ULL, 0x3333333333333333ULL,
5713 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
5714 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
5716 MVT VT = Op.getValueType();
5717 MVT ShVT = TLI.getShiftAmountTy();
5718 unsigned len = VT.getSizeInBits();
5719 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5720 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
5721 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
5722 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5723 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
5724 DAG.getNode(ISD::AND, VT,
5725 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
5730 // for now, we do this:
5731 // x = x | (x >> 1);
5732 // x = x | (x >> 2);
5734 // x = x | (x >>16);
5735 // x = x | (x >>32); // for 64-bit input
5736 // return popcount(~x);
5738 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
5739 MVT VT = Op.getValueType();
5740 MVT ShVT = TLI.getShiftAmountTy();
5741 unsigned len = VT.getSizeInBits();
5742 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5743 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5744 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
5746 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
5747 return DAG.getNode(ISD::CTPOP, VT, Op);
5750 // for now, we use: { return popcount(~x & (x - 1)); }
5751 // unless the target has ctlz but not ctpop, in which case we use:
5752 // { return 32 - nlz(~x & (x-1)); }
5753 // see also http://www.hackersdelight.org/HDcode/ntz.cc
5754 MVT VT = Op.getValueType();
5755 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
5756 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
5757 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
5758 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
5759 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
5760 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
5761 TLI.isOperationLegal(ISD::CTLZ, VT))
5762 return DAG.getNode(ISD::SUB, VT,
5763 DAG.getConstant(VT.getSizeInBits(), VT),
5764 DAG.getNode(ISD::CTLZ, VT, Tmp3));
5765 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
5770 /// ExpandOp - Expand the specified SDOperand into its two component pieces
5771 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
5772 /// LegalizeNodes map is filled in for any results that are not expanded, the
5773 /// ExpandedNodes map is filled in for any results that are expanded, and the
5774 /// Lo/Hi values are returned.
5775 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
5776 MVT VT = Op.getValueType();
5777 MVT NVT = TLI.getTypeToTransformTo(VT);
5778 SDNode *Node = Op.Val;
5779 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
5780 assert(((NVT.isInteger() && NVT.bitsLT(VT)) || VT.isFloatingPoint() ||
5781 VT.isVector()) && "Cannot expand to FP value or to larger int value!");
5783 // See if we already expanded it.
5784 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
5785 = ExpandedNodes.find(Op);
5786 if (I != ExpandedNodes.end()) {
5787 Lo = I->second.first;
5788 Hi = I->second.second;
5792 switch (Node->getOpcode()) {
5793 case ISD::CopyFromReg:
5794 assert(0 && "CopyFromReg must be legal!");
5795 case ISD::FP_ROUND_INREG:
5796 if (VT == MVT::ppcf128 &&
5797 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
5798 TargetLowering::Custom) {
5799 SDOperand SrcLo, SrcHi, Src;
5800 ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
5801 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi);
5802 SDOperand Result = TLI.LowerOperation(
5803 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG);
5804 assert(Result.Val->getOpcode() == ISD::BUILD_PAIR);
5805 Lo = Result.Val->getOperand(0);
5806 Hi = Result.Val->getOperand(1);
5812 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
5814 assert(0 && "Do not know how to expand this operator!");
5816 case ISD::EXTRACT_ELEMENT:
5817 ExpandOp(Node->getOperand(0), Lo, Hi);
5818 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
5819 return ExpandOp(Hi, Lo, Hi);
5820 return ExpandOp(Lo, Lo, Hi);
5821 case ISD::EXTRACT_VECTOR_ELT:
5822 assert(VT==MVT::i64 && "Do not know how to expand this operator!");
5823 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types.
5824 Lo = ExpandEXTRACT_VECTOR_ELT(Op);
5825 return ExpandOp(Lo, Lo, Hi);
5827 Lo = DAG.getNode(ISD::UNDEF, NVT);
5828 Hi = DAG.getNode(ISD::UNDEF, NVT);
5830 case ISD::Constant: {
5831 unsigned NVTBits = NVT.getSizeInBits();
5832 const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue();
5833 Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT);
5834 Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT);
5837 case ISD::ConstantFP: {
5838 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
5839 if (CFP->getValueType(0) == MVT::ppcf128) {
5840 APInt api = CFP->getValueAPF().convertToAPInt();
5841 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
5843 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
5847 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
5848 if (getTypeAction(Lo.getValueType()) == Expand)
5849 ExpandOp(Lo, Lo, Hi);
5852 case ISD::BUILD_PAIR:
5853 // Return the operands.
5854 Lo = Node->getOperand(0);
5855 Hi = Node->getOperand(1);
5858 case ISD::MERGE_VALUES:
5859 if (Node->getNumValues() == 1) {
5860 ExpandOp(Op.getOperand(0), Lo, Hi);
5863 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y)
5864 assert(Op.ResNo == 0 && Node->getNumValues() == 2 &&
5865 Op.getValue(1).getValueType() == MVT::Other &&
5866 "unhandled MERGE_VALUES");
5867 ExpandOp(Op.getOperand(0), Lo, Hi);
5868 // Remember that we legalized the chain.
5869 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1)));
5872 case ISD::SIGN_EXTEND_INREG:
5873 ExpandOp(Node->getOperand(0), Lo, Hi);
5874 // sext_inreg the low part if needed.
5875 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
5877 // The high part gets the sign extension from the lo-part. This handles
5878 // things like sextinreg V:i64 from i8.
5879 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5880 DAG.getConstant(NVT.getSizeInBits()-1,
5881 TLI.getShiftAmountTy()));
5885 ExpandOp(Node->getOperand(0), Lo, Hi);
5886 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
5887 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
5893 ExpandOp(Node->getOperand(0), Lo, Hi);
5894 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
5895 DAG.getNode(ISD::CTPOP, NVT, Lo),
5896 DAG.getNode(ISD::CTPOP, NVT, Hi));
5897 Hi = DAG.getConstant(0, NVT);
5901 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
5902 ExpandOp(Node->getOperand(0), Lo, Hi);
5903 SDOperand BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
5904 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
5905 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(HLZ), HLZ, BitsC,
5907 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
5908 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
5910 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
5911 Hi = DAG.getConstant(0, NVT);
5916 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
5917 ExpandOp(Node->getOperand(0), Lo, Hi);
5918 SDOperand BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
5919 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
5920 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(LTZ), LTZ, BitsC,
5922 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
5923 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
5925 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
5926 Hi = DAG.getConstant(0, NVT);
5931 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
5932 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
5933 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
5934 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
5936 // Remember that we legalized the chain.
5937 Hi = LegalizeOp(Hi);
5938 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
5939 if (TLI.isBigEndian())
5945 LoadSDNode *LD = cast<LoadSDNode>(Node);
5946 SDOperand Ch = LD->getChain(); // Legalize the chain.
5947 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer.
5948 ISD::LoadExtType ExtType = LD->getExtensionType();
5949 int SVOffset = LD->getSrcValueOffset();
5950 unsigned Alignment = LD->getAlignment();
5951 bool isVolatile = LD->isVolatile();
5953 if (ExtType == ISD::NON_EXTLOAD) {
5954 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5955 isVolatile, Alignment);
5956 if (VT == MVT::f32 || VT == MVT::f64) {
5957 // f32->i32 or f64->i64 one to one expansion.
5958 // Remember that we legalized the chain.
5959 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5960 // Recursively expand the new load.
5961 if (getTypeAction(NVT) == Expand)
5962 ExpandOp(Lo, Lo, Hi);
5966 // Increment the pointer to the other half.
5967 unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8;
5968 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
5969 DAG.getIntPtrConstant(IncrementSize));
5970 SVOffset += IncrementSize;
5971 Alignment = MinAlign(Alignment, IncrementSize);
5972 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5973 isVolatile, Alignment);
5975 // Build a factor node to remember that this load is independent of the
5977 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
5980 // Remember that we legalized the chain.
5981 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
5982 if (TLI.isBigEndian())
5985 MVT EVT = LD->getMemoryVT();
5987 if ((VT == MVT::f64 && EVT == MVT::f32) ||
5988 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
5989 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
5990 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(),
5991 SVOffset, isVolatile, Alignment);
5992 // Remember that we legalized the chain.
5993 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1)));
5994 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
5999 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),
6000 SVOffset, isVolatile, Alignment);
6002 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(),
6003 SVOffset, EVT, isVolatile,
6006 // Remember that we legalized the chain.
6007 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
6009 if (ExtType == ISD::SEXTLOAD) {
6010 // The high part is obtained by SRA'ing all but one of the bits of the
6012 unsigned LoSize = Lo.getValueType().getSizeInBits();
6013 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6014 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6015 } else if (ExtType == ISD::ZEXTLOAD) {
6016 // The high part is just a zero.
6017 Hi = DAG.getConstant(0, NVT);
6018 } else /* if (ExtType == ISD::EXTLOAD) */ {
6019 // The high part is undefined.
6020 Hi = DAG.getNode(ISD::UNDEF, NVT);
6027 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
6028 SDOperand LL, LH, RL, RH;
6029 ExpandOp(Node->getOperand(0), LL, LH);
6030 ExpandOp(Node->getOperand(1), RL, RH);
6031 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
6032 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
6036 SDOperand LL, LH, RL, RH;
6037 ExpandOp(Node->getOperand(1), LL, LH);
6038 ExpandOp(Node->getOperand(2), RL, RH);
6039 if (getTypeAction(NVT) == Expand)
6040 NVT = TLI.getTypeToExpandTo(NVT);
6041 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
6043 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
6046 case ISD::SELECT_CC: {
6047 SDOperand TL, TH, FL, FH;
6048 ExpandOp(Node->getOperand(2), TL, TH);
6049 ExpandOp(Node->getOperand(3), FL, FH);
6050 if (getTypeAction(NVT) == Expand)
6051 NVT = TLI.getTypeToExpandTo(NVT);
6052 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
6053 Node->getOperand(1), TL, FL, Node->getOperand(4));
6055 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
6056 Node->getOperand(1), TH, FH, Node->getOperand(4));
6059 case ISD::ANY_EXTEND:
6060 // The low part is any extension of the input (which degenerates to a copy).
6061 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
6062 // The high part is undefined.
6063 Hi = DAG.getNode(ISD::UNDEF, NVT);
6065 case ISD::SIGN_EXTEND: {
6066 // The low part is just a sign extension of the input (which degenerates to
6068 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
6070 // The high part is obtained by SRA'ing all but one of the bits of the lo
6072 unsigned LoSize = Lo.getValueType().getSizeInBits();
6073 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6074 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6077 case ISD::ZERO_EXTEND:
6078 // The low part is just a zero extension of the input (which degenerates to
6080 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
6082 // The high part is just a zero.
6083 Hi = DAG.getConstant(0, NVT);
6086 case ISD::TRUNCATE: {
6087 // The input value must be larger than this value. Expand *it*.
6089 ExpandOp(Node->getOperand(0), NewLo, Hi);
6091 // The low part is now either the right size, or it is closer. If not the
6092 // right size, make an illegal truncate so we recursively expand it.
6093 if (NewLo.getValueType() != Node->getValueType(0))
6094 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
6095 ExpandOp(NewLo, Lo, Hi);
6099 case ISD::BIT_CONVERT: {
6101 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
6102 // If the target wants to, allow it to lower this itself.
6103 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6104 case Expand: assert(0 && "cannot expand FP!");
6105 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
6106 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
6108 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
6111 // f32 / f64 must be expanded to i32 / i64.
6112 if (VT == MVT::f32 || VT == MVT::f64) {
6113 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6114 if (getTypeAction(NVT) == Expand)
6115 ExpandOp(Lo, Lo, Hi);
6119 // If source operand will be expanded to the same type as VT, i.e.
6120 // i64 <- f64, i32 <- f32, expand the source operand instead.
6121 MVT VT0 = Node->getOperand(0).getValueType();
6122 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
6123 ExpandOp(Node->getOperand(0), Lo, Hi);
6127 // Turn this into a load/store pair by default.
6129 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT);
6131 ExpandOp(Tmp, Lo, Hi);
6135 case ISD::READCYCLECOUNTER: {
6136 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
6137 TargetLowering::Custom &&
6138 "Must custom expand ReadCycleCounter");
6139 SDOperand Tmp = TLI.LowerOperation(Op, DAG);
6140 assert(Tmp.Val && "Node must be custom expanded!");
6141 ExpandOp(Tmp.getValue(0), Lo, Hi);
6142 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
6143 LegalizeOp(Tmp.getValue(1)));
6147 case ISD::ATOMIC_CMP_SWAP: {
6148 SDOperand Tmp = TLI.LowerOperation(Op, DAG);
6149 assert(Tmp.Val && "Node must be custom expanded!");
6150 ExpandOp(Tmp.getValue(0), Lo, Hi);
6151 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
6152 LegalizeOp(Tmp.getValue(1)));
6158 // These operators cannot be expanded directly, emit them as calls to
6159 // library functions.
6160 case ISD::FP_TO_SINT: {
6161 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
6163 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6164 case Expand: assert(0 && "cannot expand FP!");
6165 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6166 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6169 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
6171 // Now that the custom expander is done, expand the result, which is still
6174 ExpandOp(Op, Lo, Hi);
6179 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6180 if (VT == MVT::i64) {
6181 if (Node->getOperand(0).getValueType() == MVT::f32)
6182 LC = RTLIB::FPTOSINT_F32_I64;
6183 else if (Node->getOperand(0).getValueType() == MVT::f64)
6184 LC = RTLIB::FPTOSINT_F64_I64;
6185 else if (Node->getOperand(0).getValueType() == MVT::f80)
6186 LC = RTLIB::FPTOSINT_F80_I64;
6187 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
6188 LC = RTLIB::FPTOSINT_PPCF128_I64;
6189 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6190 } else if (VT == MVT::i128) {
6191 if (Node->getOperand(0).getValueType() == MVT::f32)
6192 LC = RTLIB::FPTOSINT_F32_I128;
6193 else if (Node->getOperand(0).getValueType() == MVT::f64)
6194 LC = RTLIB::FPTOSINT_F64_I128;
6195 else if (Node->getOperand(0).getValueType() == MVT::f80)
6196 LC = RTLIB::FPTOSINT_F80_I128;
6197 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
6198 LC = RTLIB::FPTOSINT_PPCF128_I128;
6199 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6201 assert(0 && "Unexpected uint-to-fp conversion!");
6206 case ISD::FP_TO_UINT: {
6207 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
6209 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6210 case Expand: assert(0 && "cannot expand FP!");
6211 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6212 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6215 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
6217 // Now that the custom expander is done, expand the result.
6219 ExpandOp(Op, Lo, Hi);
6224 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6225 if (VT == MVT::i64) {
6226 if (Node->getOperand(0).getValueType() == MVT::f32)
6227 LC = RTLIB::FPTOUINT_F32_I64;
6228 else if (Node->getOperand(0).getValueType() == MVT::f64)
6229 LC = RTLIB::FPTOUINT_F64_I64;
6230 else if (Node->getOperand(0).getValueType() == MVT::f80)
6231 LC = RTLIB::FPTOUINT_F80_I64;
6232 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
6233 LC = RTLIB::FPTOUINT_PPCF128_I64;
6234 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6235 } else if (VT == MVT::i128) {
6236 if (Node->getOperand(0).getValueType() == MVT::f32)
6237 LC = RTLIB::FPTOUINT_F32_I128;
6238 else if (Node->getOperand(0).getValueType() == MVT::f64)
6239 LC = RTLIB::FPTOUINT_F64_I128;
6240 else if (Node->getOperand(0).getValueType() == MVT::f80)
6241 LC = RTLIB::FPTOUINT_F80_I128;
6242 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
6243 LC = RTLIB::FPTOUINT_PPCF128_I128;
6244 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6246 assert(0 && "Unexpected uint-to-fp conversion!");
6252 // If the target wants custom lowering, do so.
6253 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6254 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
6255 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
6256 Op = TLI.LowerOperation(Op, DAG);
6258 // Now that the custom expander is done, expand the result, which is
6260 ExpandOp(Op, Lo, Hi);
6265 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
6266 // this X << 1 as X+X.
6267 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
6268 if (ShAmt->getAPIntValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
6269 TLI.isOperationLegal(ISD::ADDE, NVT)) {
6270 SDOperand LoOps[2], HiOps[3];
6271 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
6272 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
6273 LoOps[1] = LoOps[0];
6274 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6276 HiOps[1] = HiOps[0];
6277 HiOps[2] = Lo.getValue(1);
6278 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6283 // If we can emit an efficient shift operation, do so now.
6284 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6287 // If this target supports SHL_PARTS, use it.
6288 TargetLowering::LegalizeAction Action =
6289 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
6290 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6291 Action == TargetLowering::Custom) {
6292 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6296 // Otherwise, emit a libcall.
6297 Lo = ExpandLibCall(RTLIB::SHL_I64, Node, false/*left shift=unsigned*/, Hi);
6302 // If the target wants custom lowering, do so.
6303 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6304 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
6305 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
6306 Op = TLI.LowerOperation(Op, DAG);
6308 // Now that the custom expander is done, expand the result, which is
6310 ExpandOp(Op, Lo, Hi);
6315 // If we can emit an efficient shift operation, do so now.
6316 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
6319 // If this target supports SRA_PARTS, use it.
6320 TargetLowering::LegalizeAction Action =
6321 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
6322 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6323 Action == TargetLowering::Custom) {
6324 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6328 // Otherwise, emit a libcall.
6329 Lo = ExpandLibCall(RTLIB::SRA_I64, Node, true/*ashr is signed*/, Hi);
6334 // If the target wants custom lowering, do so.
6335 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6336 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
6337 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
6338 Op = TLI.LowerOperation(Op, DAG);
6340 // Now that the custom expander is done, expand the result, which is
6342 ExpandOp(Op, Lo, Hi);
6347 // If we can emit an efficient shift operation, do so now.
6348 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6351 // If this target supports SRL_PARTS, use it.
6352 TargetLowering::LegalizeAction Action =
6353 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
6354 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6355 Action == TargetLowering::Custom) {
6356 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6360 // Otherwise, emit a libcall.
6361 Lo = ExpandLibCall(RTLIB::SRL_I64, Node, false/*lshr is unsigned*/, Hi);
6367 // If the target wants to custom expand this, let them.
6368 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
6369 TargetLowering::Custom) {
6370 SDOperand Result = TLI.LowerOperation(Op, DAG);
6372 ExpandOp(Result, Lo, Hi);
6377 // Expand the subcomponents.
6378 SDOperand LHSL, LHSH, RHSL, RHSH;
6379 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6380 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6381 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6382 SDOperand LoOps[2], HiOps[3];
6387 if (Node->getOpcode() == ISD::ADD) {
6388 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6389 HiOps[2] = Lo.getValue(1);
6390 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6392 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6393 HiOps[2] = Lo.getValue(1);
6394 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6401 // Expand the subcomponents.
6402 SDOperand LHSL, LHSH, RHSL, RHSH;
6403 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6404 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6405 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6406 SDOperand LoOps[2] = { LHSL, RHSL };
6407 SDOperand HiOps[3] = { LHSH, RHSH };
6409 if (Node->getOpcode() == ISD::ADDC) {
6410 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6411 HiOps[2] = Lo.getValue(1);
6412 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6414 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6415 HiOps[2] = Lo.getValue(1);
6416 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6418 // Remember that we legalized the flag.
6419 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6424 // Expand the subcomponents.
6425 SDOperand LHSL, LHSH, RHSL, RHSH;
6426 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6427 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6428 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6429 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
6430 SDOperand HiOps[3] = { LHSH, RHSH };
6432 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
6433 HiOps[2] = Lo.getValue(1);
6434 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
6436 // Remember that we legalized the flag.
6437 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6441 // If the target wants to custom expand this, let them.
6442 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
6443 SDOperand New = TLI.LowerOperation(Op, DAG);
6445 ExpandOp(New, Lo, Hi);
6450 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
6451 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
6452 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
6453 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
6454 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
6455 SDOperand LL, LH, RL, RH;
6456 ExpandOp(Node->getOperand(0), LL, LH);
6457 ExpandOp(Node->getOperand(1), RL, RH);
6458 unsigned OuterBitSize = Op.getValueSizeInBits();
6459 unsigned InnerBitSize = RH.getValueSizeInBits();
6460 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
6461 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
6462 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
6463 if (DAG.MaskedValueIsZero(Node->getOperand(0), HighMask) &&
6464 DAG.MaskedValueIsZero(Node->getOperand(1), HighMask)) {
6465 // The inputs are both zero-extended.
6467 // We can emit a umul_lohi.
6468 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6469 Hi = SDOperand(Lo.Val, 1);
6473 // We can emit a mulhu+mul.
6474 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6475 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6479 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
6480 // The input values are both sign-extended.
6482 // We can emit a smul_lohi.
6483 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6484 Hi = SDOperand(Lo.Val, 1);
6488 // We can emit a mulhs+mul.
6489 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6490 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
6495 // Lo,Hi = umul LHS, RHS.
6496 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
6497 DAG.getVTList(NVT, NVT), LL, RL);
6499 Hi = UMulLOHI.getValue(1);
6500 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6501 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6502 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6503 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6507 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6508 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6509 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6510 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6511 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6512 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6517 // If nothing else, we can make a libcall.
6518 Lo = ExpandLibCall(RTLIB::MUL_I64, Node, false/*sign irrelevant*/, Hi);
6522 Lo = ExpandLibCall(RTLIB::SDIV_I64, Node, true, Hi);
6525 Lo = ExpandLibCall(RTLIB::UDIV_I64, Node, true, Hi);
6528 Lo = ExpandLibCall(RTLIB::SREM_I64, Node, true, Hi);
6531 Lo = ExpandLibCall(RTLIB::UREM_I64, Node, true, Hi);
6535 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::ADD_F32,
6538 RTLIB::ADD_PPCF128),
6542 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::SUB_F32,
6545 RTLIB::SUB_PPCF128),
6549 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::MUL_F32,
6552 RTLIB::MUL_PPCF128),
6556 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::DIV_F32,
6559 RTLIB::DIV_PPCF128),
6562 case ISD::FP_EXTEND:
6563 if (VT == MVT::ppcf128) {
6564 assert(Node->getOperand(0).getValueType()==MVT::f32 ||
6565 Node->getOperand(0).getValueType()==MVT::f64);
6566 const uint64_t zero = 0;
6567 if (Node->getOperand(0).getValueType()==MVT::f32)
6568 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0));
6570 Hi = Node->getOperand(0);
6571 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6574 Lo = ExpandLibCall(RTLIB::FPEXT_F32_F64, Node, true, Hi);
6577 Lo = ExpandLibCall(RTLIB::FPROUND_F64_F32, Node, true, Hi);
6580 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::POWI_F32,
6583 RTLIB::POWI_PPCF128),
6589 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6590 switch(Node->getOpcode()) {
6592 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
6593 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
6596 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
6597 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
6600 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
6601 RTLIB::COS_F80, RTLIB::COS_PPCF128);
6603 default: assert(0 && "Unreachable!");
6605 Lo = ExpandLibCall(LC, Node, false, Hi);
6609 if (VT == MVT::ppcf128) {
6611 ExpandOp(Node->getOperand(0), Lo, Tmp);
6612 Hi = DAG.getNode(ISD::FABS, NVT, Tmp);
6613 // lo = hi==fabs(hi) ? lo : -lo;
6614 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp,
6615 Lo, DAG.getNode(ISD::FNEG, NVT, Lo),
6616 DAG.getCondCode(ISD::SETEQ));
6619 SDOperand Mask = (VT == MVT::f64)
6620 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
6621 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
6622 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6623 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6624 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
6625 if (getTypeAction(NVT) == Expand)
6626 ExpandOp(Lo, Lo, Hi);
6630 if (VT == MVT::ppcf128) {
6631 ExpandOp(Node->getOperand(0), Lo, Hi);
6632 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo);
6633 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi);
6636 SDOperand Mask = (VT == MVT::f64)
6637 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
6638 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
6639 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6640 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6641 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
6642 if (getTypeAction(NVT) == Expand)
6643 ExpandOp(Lo, Lo, Hi);
6646 case ISD::FCOPYSIGN: {
6647 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
6648 if (getTypeAction(NVT) == Expand)
6649 ExpandOp(Lo, Lo, Hi);
6652 case ISD::SINT_TO_FP:
6653 case ISD::UINT_TO_FP: {
6654 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
6655 MVT SrcVT = Node->getOperand(0).getValueType();
6657 // Promote the operand if needed. Do this before checking for
6658 // ppcf128 so conversions of i16 and i8 work.
6659 if (getTypeAction(SrcVT) == Promote) {
6660 SDOperand Tmp = PromoteOp(Node->getOperand(0));
6662 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
6663 DAG.getValueType(SrcVT))
6664 : DAG.getZeroExtendInReg(Tmp, SrcVT);
6665 Node = DAG.UpdateNodeOperands(Op, Tmp).Val;
6666 SrcVT = Node->getOperand(0).getValueType();
6669 if (VT == MVT::ppcf128 && SrcVT == MVT::i32) {
6670 static const uint64_t zero = 0;
6672 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6673 Node->getOperand(0)));
6674 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6676 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
6677 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6678 Node->getOperand(0)));
6679 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6680 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6681 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
6682 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6683 DAG.getConstant(0, MVT::i32),
6684 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6686 APFloat(APInt(128, 2, TwoE32)),
6689 DAG.getCondCode(ISD::SETLT)),
6694 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) {
6695 // si64->ppcf128 done by libcall, below
6696 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
6697 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)),
6699 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6700 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
6701 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6702 DAG.getConstant(0, MVT::i64),
6703 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6705 APFloat(APInt(128, 2, TwoE64)),
6708 DAG.getCondCode(ISD::SETLT)),
6713 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
6714 Node->getOperand(0));
6715 if (getTypeAction(Lo.getValueType()) == Expand)
6716 // float to i32 etc. can be 'expanded' to a single node.
6717 ExpandOp(Lo, Lo, Hi);
6722 // Make sure the resultant values have been legalized themselves, unless this
6723 // is a type that requires multi-step expansion.
6724 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
6725 Lo = LegalizeOp(Lo);
6727 // Don't legalize the high part if it is expanded to a single node.
6728 Hi = LegalizeOp(Hi);
6731 // Remember in a map if the values will be reused later.
6732 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi)));
6733 assert(isNew && "Value already expanded?!?");
6736 /// SplitVectorOp - Given an operand of vector type, break it down into
6737 /// two smaller values, still of vector type.
6738 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
6740 assert(Op.getValueType().isVector() && "Cannot split non-vector type!");
6741 SDNode *Node = Op.Val;
6742 unsigned NumElements = Op.getValueType().getVectorNumElements();
6743 assert(NumElements > 1 && "Cannot split a single element vector!");
6745 MVT NewEltVT = Op.getValueType().getVectorElementType();
6747 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
6748 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
6750 MVT NewVT_Lo = MVT::getVectorVT(NewEltVT, NewNumElts_Lo);
6751 MVT NewVT_Hi = MVT::getVectorVT(NewEltVT, NewNumElts_Hi);
6753 // See if we already split it.
6754 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
6755 = SplitNodes.find(Op);
6756 if (I != SplitNodes.end()) {
6757 Lo = I->second.first;
6758 Hi = I->second.second;
6762 switch (Node->getOpcode()) {
6767 assert(0 && "Unhandled operation in SplitVectorOp!");
6769 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo);
6770 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi);
6772 case ISD::BUILD_PAIR:
6773 Lo = Node->getOperand(0);
6774 Hi = Node->getOperand(1);
6776 case ISD::INSERT_VECTOR_ELT: {
6777 if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) {
6778 SplitVectorOp(Node->getOperand(0), Lo, Hi);
6779 unsigned Index = Idx->getValue();
6780 SDOperand ScalarOp = Node->getOperand(1);
6781 if (Index < NewNumElts_Lo)
6782 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp,
6783 DAG.getIntPtrConstant(Index));
6785 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp,
6786 DAG.getIntPtrConstant(Index - NewNumElts_Lo));
6789 SDOperand Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0),
6790 Node->getOperand(1),
6791 Node->getOperand(2));
6792 SplitVectorOp(Tmp, Lo, Hi);
6795 case ISD::VECTOR_SHUFFLE: {
6796 // Build the low part.
6797 SDOperand Mask = Node->getOperand(2);
6798 SmallVector<SDOperand, 8> Ops;
6799 MVT PtrVT = TLI.getPointerTy();
6801 // Insert all of the elements from the input that are needed. We use
6802 // buildvector of extractelement here because the input vectors will have
6803 // to be legalized, so this makes the code simpler.
6804 for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
6805 SDOperand IdxNode = Mask.getOperand(i);
6806 if (IdxNode.getOpcode() == ISD::UNDEF) {
6807 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
6810 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getValue();
6811 SDOperand InVec = Node->getOperand(0);
6812 if (Idx >= NumElements) {
6813 InVec = Node->getOperand(1);
6816 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6817 DAG.getConstant(Idx, PtrVT)));
6819 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6822 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
6823 SDOperand IdxNode = Mask.getOperand(i);
6824 if (IdxNode.getOpcode() == ISD::UNDEF) {
6825 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
6828 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getValue();
6829 SDOperand InVec = Node->getOperand(0);
6830 if (Idx >= NumElements) {
6831 InVec = Node->getOperand(1);
6834 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6835 DAG.getConstant(Idx, PtrVT)));
6837 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6840 case ISD::BUILD_VECTOR: {
6841 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
6842 Node->op_begin()+NewNumElts_Lo);
6843 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size());
6845 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
6847 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size());
6850 case ISD::CONCAT_VECTORS: {
6851 // FIXME: Handle non-power-of-two vectors?
6852 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
6853 if (NewNumSubvectors == 1) {
6854 Lo = Node->getOperand(0);
6855 Hi = Node->getOperand(1);
6857 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
6858 Node->op_begin()+NewNumSubvectors);
6859 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size());
6861 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors,
6863 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size());
6868 SDOperand Cond = Node->getOperand(0);
6870 SDOperand LL, LH, RL, RH;
6871 SplitVectorOp(Node->getOperand(1), LL, LH);
6872 SplitVectorOp(Node->getOperand(2), RL, RH);
6874 if (Cond.getValueType().isVector()) {
6875 // Handle a vector merge.
6877 SplitVectorOp(Cond, CL, CH);
6878 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL);
6879 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH);
6881 // Handle a simple select with vector operands.
6882 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL);
6883 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH);
6887 case ISD::SELECT_CC: {
6888 SDOperand CondLHS = Node->getOperand(0);
6889 SDOperand CondRHS = Node->getOperand(1);
6890 SDOperand CondCode = Node->getOperand(4);
6892 SDOperand LL, LH, RL, RH;
6893 SplitVectorOp(Node->getOperand(2), LL, LH);
6894 SplitVectorOp(Node->getOperand(3), RL, RH);
6896 // Handle a simple select with vector operands.
6897 Lo = DAG.getNode(ISD::SELECT_CC, NewVT_Lo, CondLHS, CondRHS,
6899 Hi = DAG.getNode(ISD::SELECT_CC, NewVT_Hi, CondLHS, CondRHS,
6904 SDOperand LL, LH, RL, RH;
6905 SplitVectorOp(Node->getOperand(0), LL, LH);
6906 SplitVectorOp(Node->getOperand(1), RL, RH);
6907 Lo = DAG.getNode(ISD::VSETCC, NewVT_Lo, LL, RL, Node->getOperand(2));
6908 Hi = DAG.getNode(ISD::VSETCC, NewVT_Hi, LH, RH, Node->getOperand(2));
6927 SDOperand LL, LH, RL, RH;
6928 SplitVectorOp(Node->getOperand(0), LL, LH);
6929 SplitVectorOp(Node->getOperand(1), RL, RH);
6931 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL);
6932 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH);
6937 SplitVectorOp(Node->getOperand(0), L, H);
6939 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1));
6940 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1));
6951 case ISD::FP_TO_SINT:
6952 case ISD::FP_TO_UINT:
6953 case ISD::SINT_TO_FP:
6954 case ISD::UINT_TO_FP: {
6956 SplitVectorOp(Node->getOperand(0), L, H);
6958 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L);
6959 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H);
6963 LoadSDNode *LD = cast<LoadSDNode>(Node);
6964 SDOperand Ch = LD->getChain();
6965 SDOperand Ptr = LD->getBasePtr();
6966 const Value *SV = LD->getSrcValue();
6967 int SVOffset = LD->getSrcValueOffset();
6968 unsigned Alignment = LD->getAlignment();
6969 bool isVolatile = LD->isVolatile();
6971 Lo = DAG.getLoad(NewVT_Lo, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
6972 unsigned IncrementSize = NewNumElts_Lo * NewEltVT.getSizeInBits()/8;
6973 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
6974 DAG.getIntPtrConstant(IncrementSize));
6975 SVOffset += IncrementSize;
6976 Alignment = MinAlign(Alignment, IncrementSize);
6977 Hi = DAG.getLoad(NewVT_Hi, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
6979 // Build a factor node to remember that this load is independent of the
6981 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
6984 // Remember that we legalized the chain.
6985 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
6988 case ISD::BIT_CONVERT: {
6989 // We know the result is a vector. The input may be either a vector or a
6991 SDOperand InOp = Node->getOperand(0);
6992 if (!InOp.getValueType().isVector() ||
6993 InOp.getValueType().getVectorNumElements() == 1) {
6994 // The input is a scalar or single-element vector.
6995 // Lower to a store/load so that it can be split.
6996 // FIXME: this could be improved probably.
6997 SDOperand Ptr = DAG.CreateStackTemporary(InOp.getValueType());
6998 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(Ptr.Val);
7000 SDOperand St = DAG.getStore(DAG.getEntryNode(),
7002 PseudoSourceValue::getFixedStack(),
7004 InOp = DAG.getLoad(Op.getValueType(), St, Ptr,
7005 PseudoSourceValue::getFixedStack(),
7008 // Split the vector and convert each of the pieces now.
7009 SplitVectorOp(InOp, Lo, Hi);
7010 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo);
7011 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi);
7016 // Remember in a map if the values will be reused later.
7018 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
7019 assert(isNew && "Value already split?!?");
7023 /// ScalarizeVectorOp - Given an operand of single-element vector type
7024 /// (e.g. v1f32), convert it into the equivalent operation that returns a
7025 /// scalar (e.g. f32) value.
7026 SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) {
7027 assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!");
7028 SDNode *Node = Op.Val;
7029 MVT NewVT = Op.getValueType().getVectorElementType();
7030 assert(Op.getValueType().getVectorNumElements() == 1);
7032 // See if we already scalarized it.
7033 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op);
7034 if (I != ScalarizedNodes.end()) return I->second;
7037 switch (Node->getOpcode()) {
7040 Node->dump(&DAG); cerr << "\n";
7042 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
7059 Result = DAG.getNode(Node->getOpcode(),
7061 ScalarizeVectorOp(Node->getOperand(0)),
7062 ScalarizeVectorOp(Node->getOperand(1)));
7069 Result = DAG.getNode(Node->getOpcode(),
7071 ScalarizeVectorOp(Node->getOperand(0)));
7074 Result = DAG.getNode(Node->getOpcode(),
7076 ScalarizeVectorOp(Node->getOperand(0)),
7077 Node->getOperand(1));
7080 LoadSDNode *LD = cast<LoadSDNode>(Node);
7081 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
7082 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
7084 const Value *SV = LD->getSrcValue();
7085 int SVOffset = LD->getSrcValueOffset();
7086 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset,
7087 LD->isVolatile(), LD->getAlignment());
7089 // Remember that we legalized the chain.
7090 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
7093 case ISD::BUILD_VECTOR:
7094 Result = Node->getOperand(0);
7096 case ISD::INSERT_VECTOR_ELT:
7097 // Returning the inserted scalar element.
7098 Result = Node->getOperand(1);
7100 case ISD::CONCAT_VECTORS:
7101 assert(Node->getOperand(0).getValueType() == NewVT &&
7102 "Concat of non-legal vectors not yet supported!");
7103 Result = Node->getOperand(0);
7105 case ISD::VECTOR_SHUFFLE: {
7106 // Figure out if the scalar is the LHS or RHS and return it.
7107 SDOperand EltNum = Node->getOperand(2).getOperand(0);
7108 if (cast<ConstantSDNode>(EltNum)->getValue())
7109 Result = ScalarizeVectorOp(Node->getOperand(1));
7111 Result = ScalarizeVectorOp(Node->getOperand(0));
7114 case ISD::EXTRACT_SUBVECTOR:
7115 Result = Node->getOperand(0);
7116 assert(Result.getValueType() == NewVT);
7118 case ISD::BIT_CONVERT: {
7119 SDOperand Op0 = Op.getOperand(0);
7120 if (Op0.getValueType().getVectorNumElements() == 1)
7121 Op0 = ScalarizeVectorOp(Op0);
7122 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op0);
7126 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
7127 ScalarizeVectorOp(Op.getOperand(1)),
7128 ScalarizeVectorOp(Op.getOperand(2)));
7130 case ISD::SELECT_CC:
7131 Result = DAG.getNode(ISD::SELECT_CC, NewVT, Node->getOperand(0),
7132 Node->getOperand(1),
7133 ScalarizeVectorOp(Op.getOperand(2)),
7134 ScalarizeVectorOp(Op.getOperand(3)),
7135 Node->getOperand(4));
7138 SDOperand Op0 = ScalarizeVectorOp(Op.getOperand(0));
7139 SDOperand Op1 = ScalarizeVectorOp(Op.getOperand(1));
7140 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Op0), Op0, Op1,
7142 Result = DAG.getNode(ISD::SELECT, NewVT, Result,
7143 DAG.getConstant(-1ULL, NewVT),
7144 DAG.getConstant(0ULL, NewVT));
7149 if (TLI.isTypeLegal(NewVT))
7150 Result = LegalizeOp(Result);
7151 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
7152 assert(isNew && "Value already scalarized?");
7157 // SelectionDAG::Legalize - This is the entry point for the file.
7159 void SelectionDAG::Legalize() {
7160 if (ViewLegalizeDAGs) viewGraph();
7162 /// run - This is the main entry point to this class.
7164 SelectionDAGLegalize(*this).LegalizeDAG();