1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/Analysis/DebugInfo.h"
20 #include "llvm/CodeGen/PseudoSourceValue.h"
21 #include "llvm/Target/TargetFrameInfo.h"
22 #include "llvm/Target/TargetLowering.h"
23 #include "llvm/Target/TargetData.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Target/TargetOptions.h"
26 #include "llvm/CallingConv.h"
27 #include "llvm/Constants.h"
28 #include "llvm/DerivedTypes.h"
29 #include "llvm/Function.h"
30 #include "llvm/GlobalVariable.h"
31 #include "llvm/LLVMContext.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/Support/raw_ostream.h"
37 #include "llvm/ADT/DenseMap.h"
38 #include "llvm/ADT/SmallVector.h"
39 #include "llvm/ADT/SmallPtrSet.h"
42 //===----------------------------------------------------------------------===//
43 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
44 /// hacks on it until the target machine can handle it. This involves
45 /// eliminating value sizes the machine cannot handle (promoting small sizes to
46 /// large sizes or splitting up large values into small values) as well as
47 /// eliminating operations the machine cannot handle.
49 /// This code also does a small amount of optimization and recognition of idioms
50 /// as part of its processing. For example, if a target does not support a
51 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
52 /// will attempt merge setcc and brc instructions into brcc's.
55 class SelectionDAGLegalize {
56 const TargetMachine &TM;
57 const TargetLowering &TLI;
59 CodeGenOpt::Level OptLevel;
61 // Libcall insertion helpers.
63 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
64 /// legalized. We use this to ensure that calls are properly serialized
65 /// against each other, including inserted libcalls.
66 SDValue LastCALLSEQ_END;
68 /// IsLegalizingCall - This member is used *only* for purposes of providing
69 /// helpful assertions that a libcall isn't created while another call is
70 /// being legalized (which could lead to non-serialized call sequences).
71 bool IsLegalizingCall;
74 Legal, // The target natively supports this operation.
75 Promote, // This operation should be executed in a larger type.
76 Expand // Try to expand this to other ops, otherwise use a libcall.
79 /// ValueTypeActions - This is a bitvector that contains two bits for each
80 /// value type, where the two bits correspond to the LegalizeAction enum.
81 /// This can be queried with "getTypeAction(VT)".
82 TargetLowering::ValueTypeActionImpl ValueTypeActions;
84 /// LegalizedNodes - For nodes that are of legal width, and that have more
85 /// than one use, this map indicates what regularized operand to use. This
86 /// allows us to avoid legalizing the same thing more than once.
87 DenseMap<SDValue, SDValue> LegalizedNodes;
89 void AddLegalizedOperand(SDValue From, SDValue To) {
90 LegalizedNodes.insert(std::make_pair(From, To));
91 // If someone requests legalization of the new node, return itself.
93 LegalizedNodes.insert(std::make_pair(To, To));
97 SelectionDAGLegalize(SelectionDAG &DAG, CodeGenOpt::Level ol);
99 /// getTypeAction - Return how we should legalize values of this type, either
100 /// it is already legal or we need to expand it into multiple registers of
101 /// smaller integer type, or we need to promote it to a larger type.
102 LegalizeAction getTypeAction(EVT VT) const {
103 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
106 /// isTypeLegal - Return true if this type is legal on this target.
108 bool isTypeLegal(EVT VT) const {
109 return getTypeAction(VT) == Legal;
115 /// LegalizeOp - We know that the specified value has a legal type.
116 /// Recursively ensure that the operands have legal types, then return the
118 SDValue LegalizeOp(SDValue O);
120 SDValue OptimizeFloatStore(StoreSDNode *ST);
122 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
123 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
124 /// is necessary to spill the vector being inserted into to memory, perform
125 /// the insert there, and then read the result back.
126 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
127 SDValue Idx, DebugLoc dl);
128 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
129 SDValue Idx, DebugLoc dl);
131 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
132 /// performs the same shuffe in terms of order or result bytes, but on a type
133 /// whose vector element type is narrower than the original shuffle type.
134 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
135 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
136 SDValue N1, SDValue N2,
137 SmallVectorImpl<int> &Mask) const;
139 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
140 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
142 void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
145 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
146 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
147 SDNode *Node, bool isSigned);
148 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
149 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
150 RTLIB::Libcall Call_PPCF128);
151 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
152 RTLIB::Libcall Call_I8,
153 RTLIB::Libcall Call_I16,
154 RTLIB::Libcall Call_I32,
155 RTLIB::Libcall Call_I64,
156 RTLIB::Libcall Call_I128);
158 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl);
159 SDValue ExpandBUILD_VECTOR(SDNode *Node);
160 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
161 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
162 SmallVectorImpl<SDValue> &Results);
163 SDValue ExpandFCOPYSIGN(SDNode *Node);
164 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
166 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
168 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
171 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl);
172 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl);
174 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
175 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
177 std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node);
179 void ExpandNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
180 void PromoteNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
184 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
185 /// performs the same shuffe in terms of order or result bytes, but on a type
186 /// whose vector element type is narrower than the original shuffle type.
187 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
189 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
190 SDValue N1, SDValue N2,
191 SmallVectorImpl<int> &Mask) const {
192 unsigned NumMaskElts = VT.getVectorNumElements();
193 unsigned NumDestElts = NVT.getVectorNumElements();
194 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
196 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
198 if (NumEltsGrowth == 1)
199 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
201 SmallVector<int, 8> NewMask;
202 for (unsigned i = 0; i != NumMaskElts; ++i) {
204 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
206 NewMask.push_back(-1);
208 NewMask.push_back(Idx * NumEltsGrowth + j);
211 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
212 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
213 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
216 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag,
217 CodeGenOpt::Level ol)
218 : TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()),
219 DAG(dag), OptLevel(ol),
220 ValueTypeActions(TLI.getValueTypeActions()) {
221 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
222 "Too many value types for ValueTypeActions to hold!");
225 void SelectionDAGLegalize::LegalizeDAG() {
226 LastCALLSEQ_END = DAG.getEntryNode();
227 IsLegalizingCall = false;
229 // The legalize process is inherently a bottom-up recursive process (users
230 // legalize their uses before themselves). Given infinite stack space, we
231 // could just start legalizing on the root and traverse the whole graph. In
232 // practice however, this causes us to run out of stack space on large basic
233 // blocks. To avoid this problem, compute an ordering of the nodes where each
234 // node is only legalized after all of its operands are legalized.
235 DAG.AssignTopologicalOrder();
236 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
237 E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I)
238 LegalizeOp(SDValue(I, 0));
240 // Finally, it's possible the root changed. Get the new root.
241 SDValue OldRoot = DAG.getRoot();
242 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
243 DAG.setRoot(LegalizedNodes[OldRoot]);
245 LegalizedNodes.clear();
247 // Remove dead nodes now.
248 DAG.RemoveDeadNodes();
252 /// FindCallEndFromCallStart - Given a chained node that is part of a call
253 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
254 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
255 if (Node->getOpcode() == ISD::CALLSEQ_END)
257 if (Node->use_empty())
258 return 0; // No CallSeqEnd
260 // The chain is usually at the end.
261 SDValue TheChain(Node, Node->getNumValues()-1);
262 if (TheChain.getValueType() != MVT::Other) {
263 // Sometimes it's at the beginning.
264 TheChain = SDValue(Node, 0);
265 if (TheChain.getValueType() != MVT::Other) {
266 // Otherwise, hunt for it.
267 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
268 if (Node->getValueType(i) == MVT::Other) {
269 TheChain = SDValue(Node, i);
273 // Otherwise, we walked into a node without a chain.
274 if (TheChain.getValueType() != MVT::Other)
279 for (SDNode::use_iterator UI = Node->use_begin(),
280 E = Node->use_end(); UI != E; ++UI) {
282 // Make sure to only follow users of our token chain.
284 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
285 if (User->getOperand(i) == TheChain)
286 if (SDNode *Result = FindCallEndFromCallStart(User))
292 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
293 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
294 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
295 assert(Node && "Didn't find callseq_start for a call??");
296 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
298 assert(Node->getOperand(0).getValueType() == MVT::Other &&
299 "Node doesn't have a token chain argument!");
300 return FindCallStartFromCallEnd(Node->getOperand(0).getNode());
303 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
304 /// see if any uses can reach Dest. If no dest operands can get to dest,
305 /// legalize them, legalize ourself, and return false, otherwise, return true.
307 /// Keep track of the nodes we fine that actually do lead to Dest in
308 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
310 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
311 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
312 if (N == Dest) return true; // N certainly leads to Dest :)
314 // If we've already processed this node and it does lead to Dest, there is no
315 // need to reprocess it.
316 if (NodesLeadingTo.count(N)) return true;
318 // If the first result of this node has been already legalized, then it cannot
320 if (LegalizedNodes.count(SDValue(N, 0))) return false;
322 // Okay, this node has not already been legalized. Check and legalize all
323 // operands. If none lead to Dest, then we can legalize this node.
324 bool OperandsLeadToDest = false;
325 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
326 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
327 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest,
330 if (OperandsLeadToDest) {
331 NodesLeadingTo.insert(N);
335 // Okay, this node looks safe, legalize it and return false.
336 LegalizeOp(SDValue(N, 0));
340 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
341 /// a load from the constant pool.
342 static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
343 SelectionDAG &DAG, const TargetLowering &TLI) {
345 DebugLoc dl = CFP->getDebugLoc();
347 // If a FP immediate is precise when represented as a float and if the
348 // target can do an extending load from float to double, we put it into
349 // the constant pool as a float, even if it's is statically typed as a
350 // double. This shrinks FP constants and canonicalizes them for targets where
351 // an FP extending load is the same cost as a normal load (such as on the x87
352 // fp stack or PPC FP unit).
353 EVT VT = CFP->getValueType(0);
354 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
356 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
357 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
358 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
363 while (SVT != MVT::f32) {
364 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
365 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) &&
366 // Only do this if the target has a native EXTLOAD instruction from
368 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
369 TLI.ShouldShrinkFPConstant(OrigVT)) {
370 const Type *SType = SVT.getTypeForEVT(*DAG.getContext());
371 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
377 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
378 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
380 return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, dl,
382 CPIdx, PseudoSourceValue::getConstantPool(),
383 0, VT, false, false, Alignment);
384 return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
385 PseudoSourceValue::getConstantPool(), 0, false, false,
389 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
391 SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
392 const TargetLowering &TLI) {
393 SDValue Chain = ST->getChain();
394 SDValue Ptr = ST->getBasePtr();
395 SDValue Val = ST->getValue();
396 EVT VT = Val.getValueType();
397 int Alignment = ST->getAlignment();
398 int SVOffset = ST->getSrcValueOffset();
399 DebugLoc dl = ST->getDebugLoc();
400 if (ST->getMemoryVT().isFloatingPoint() ||
401 ST->getMemoryVT().isVector()) {
402 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
403 if (TLI.isTypeLegal(intVT)) {
404 // Expand to a bitconvert of the value to the integer type of the
405 // same size, then a (misaligned) int store.
406 // FIXME: Does not handle truncating floating point stores!
407 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, intVT, Val);
408 return DAG.getStore(Chain, dl, Result, Ptr, ST->getSrcValue(),
409 SVOffset, ST->isVolatile(), ST->isNonTemporal(),
412 // Do a (aligned) store to a stack slot, then copy from the stack slot
413 // to the final destination using (unaligned) integer loads and stores.
414 EVT StoredVT = ST->getMemoryVT();
416 TLI.getRegisterType(*DAG.getContext(),
417 EVT::getIntegerVT(*DAG.getContext(),
418 StoredVT.getSizeInBits()));
419 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
420 unsigned RegBytes = RegVT.getSizeInBits() / 8;
421 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
423 // Make sure the stack slot is also aligned for the register type.
424 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
426 // Perform the original store, only redirected to the stack slot.
427 SDValue Store = DAG.getTruncStore(Chain, dl,
428 Val, StackPtr, NULL, 0, StoredVT,
430 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
431 SmallVector<SDValue, 8> Stores;
434 // Do all but one copies using the full register width.
435 for (unsigned i = 1; i < NumRegs; i++) {
436 // Load one integer register's worth from the stack slot.
437 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, NULL, 0,
439 // Store it to the final location. Remember the store.
440 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
441 ST->getSrcValue(), SVOffset + Offset,
442 ST->isVolatile(), ST->isNonTemporal(),
443 MinAlign(ST->getAlignment(), Offset)));
444 // Increment the pointers.
446 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
448 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
451 // The last store may be partial. Do a truncating store. On big-endian
452 // machines this requires an extending load from the stack slot to ensure
453 // that the bits are in the right place.
454 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
455 8 * (StoredBytes - Offset));
457 // Load from the stack slot.
458 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, RegVT, dl, Store, StackPtr,
459 NULL, 0, MemVT, false, false, 0);
461 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
462 ST->getSrcValue(), SVOffset + Offset,
463 MemVT, ST->isVolatile(),
465 MinAlign(ST->getAlignment(), Offset)));
466 // The order of the stores doesn't matter - say it with a TokenFactor.
467 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
471 assert(ST->getMemoryVT().isInteger() &&
472 !ST->getMemoryVT().isVector() &&
473 "Unaligned store of unknown type.");
474 // Get the half-size VT
475 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext());
476 int NumBits = NewStoredVT.getSizeInBits();
477 int IncrementSize = NumBits / 8;
479 // Divide the stored value in two parts.
480 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
482 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
484 // Store the two parts
485 SDValue Store1, Store2;
486 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
487 ST->getSrcValue(), SVOffset, NewStoredVT,
488 ST->isVolatile(), ST->isNonTemporal(), Alignment);
489 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
490 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
491 Alignment = MinAlign(Alignment, IncrementSize);
492 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
493 ST->getSrcValue(), SVOffset + IncrementSize,
494 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(),
497 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
500 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
502 SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
503 const TargetLowering &TLI) {
504 int SVOffset = LD->getSrcValueOffset();
505 SDValue Chain = LD->getChain();
506 SDValue Ptr = LD->getBasePtr();
507 EVT VT = LD->getValueType(0);
508 EVT LoadedVT = LD->getMemoryVT();
509 DebugLoc dl = LD->getDebugLoc();
510 if (VT.isFloatingPoint() || VT.isVector()) {
511 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
512 if (TLI.isTypeLegal(intVT)) {
513 // Expand to a (misaligned) integer load of the same size,
514 // then bitconvert to floating point or vector.
515 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getSrcValue(),
516 SVOffset, LD->isVolatile(),
517 LD->isNonTemporal(), LD->getAlignment());
518 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, LoadedVT, newLoad);
519 if (VT.isFloatingPoint() && LoadedVT != VT)
520 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result);
522 SDValue Ops[] = { Result, Chain };
523 return DAG.getMergeValues(Ops, 2, dl);
525 // Copy the value to a (aligned) stack slot using (unaligned) integer
526 // loads and stores, then do a (aligned) load from the stack slot.
527 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
528 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
529 unsigned RegBytes = RegVT.getSizeInBits() / 8;
530 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
532 // Make sure the stack slot is also aligned for the register type.
533 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
535 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
536 SmallVector<SDValue, 8> Stores;
537 SDValue StackPtr = StackBase;
540 // Do all but one copies using the full register width.
541 for (unsigned i = 1; i < NumRegs; i++) {
542 // Load one integer register's worth from the original location.
543 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, LD->getSrcValue(),
544 SVOffset + Offset, LD->isVolatile(),
546 MinAlign(LD->getAlignment(), Offset));
547 // Follow the load with a store to the stack slot. Remember the store.
548 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
549 NULL, 0, false, false, 0));
550 // Increment the pointers.
552 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
553 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
557 // The last copy may be partial. Do an extending load.
558 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
559 8 * (LoadedBytes - Offset));
560 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, RegVT, dl, Chain, Ptr,
561 LD->getSrcValue(), SVOffset + Offset,
562 MemVT, LD->isVolatile(),
564 MinAlign(LD->getAlignment(), Offset));
565 // Follow the load with a store to the stack slot. Remember the store.
566 // On big-endian machines this requires a truncating store to ensure
567 // that the bits end up in the right place.
568 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
569 NULL, 0, MemVT, false, false, 0));
571 // The order of the stores doesn't matter - say it with a TokenFactor.
572 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
575 // Finally, perform the original load only redirected to the stack slot.
576 Load = DAG.getExtLoad(LD->getExtensionType(), VT, dl, TF, StackBase,
577 NULL, 0, LoadedVT, false, false, 0);
579 // Callers expect a MERGE_VALUES node.
580 SDValue Ops[] = { Load, TF };
581 return DAG.getMergeValues(Ops, 2, dl);
584 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
585 "Unaligned load of unsupported type.");
587 // Compute the new VT that is half the size of the old one. This is an
589 unsigned NumBits = LoadedVT.getSizeInBits();
591 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
594 unsigned Alignment = LD->getAlignment();
595 unsigned IncrementSize = NumBits / 8;
596 ISD::LoadExtType HiExtType = LD->getExtensionType();
598 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
599 if (HiExtType == ISD::NON_EXTLOAD)
600 HiExtType = ISD::ZEXTLOAD;
602 // Load the value in two parts
604 if (TLI.isLittleEndian()) {
605 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, dl, Chain, Ptr, LD->getSrcValue(),
606 SVOffset, NewLoadedVT, LD->isVolatile(),
607 LD->isNonTemporal(), Alignment);
608 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
609 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
610 Hi = DAG.getExtLoad(HiExtType, VT, dl, Chain, Ptr, LD->getSrcValue(),
611 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
612 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
614 Hi = DAG.getExtLoad(HiExtType, VT, dl, Chain, Ptr, LD->getSrcValue(),
615 SVOffset, NewLoadedVT, LD->isVolatile(),
616 LD->isNonTemporal(), Alignment);
617 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
618 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
619 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, dl, Chain, Ptr, LD->getSrcValue(),
620 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
621 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
624 // aggregate the two parts
625 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
626 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
627 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
629 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
632 SDValue Ops[] = { Result, TF };
633 return DAG.getMergeValues(Ops, 2, dl);
636 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
637 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
638 /// is necessary to spill the vector being inserted into to memory, perform
639 /// the insert there, and then read the result back.
640 SDValue SelectionDAGLegalize::
641 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
647 // If the target doesn't support this, we have to spill the input vector
648 // to a temporary stack slot, update the element, then reload it. This is
649 // badness. We could also load the value into a vector register (either
650 // with a "move to register" or "extload into register" instruction, then
651 // permute it into place, if the idx is a constant and if the idx is
652 // supported by the target.
653 EVT VT = Tmp1.getValueType();
654 EVT EltVT = VT.getVectorElementType();
655 EVT IdxVT = Tmp3.getValueType();
656 EVT PtrVT = TLI.getPointerTy();
657 SDValue StackPtr = DAG.CreateStackTemporary(VT);
659 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
662 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
663 PseudoSourceValue::getFixedStack(SPFI), 0,
666 // Truncate or zero extend offset to target pointer type.
667 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
668 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
669 // Add the offset to the index.
670 unsigned EltSize = EltVT.getSizeInBits()/8;
671 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
672 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
673 // Store the scalar value.
674 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2,
675 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT,
677 // Load the updated vector.
678 return DAG.getLoad(VT, dl, Ch, StackPtr,
679 PseudoSourceValue::getFixedStack(SPFI), 0,
684 SDValue SelectionDAGLegalize::
685 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) {
686 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
687 // SCALAR_TO_VECTOR requires that the type of the value being inserted
688 // match the element type of the vector being created, except for
689 // integers in which case the inserted value can be over width.
690 EVT EltVT = Vec.getValueType().getVectorElementType();
691 if (Val.getValueType() == EltVT ||
692 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
693 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
694 Vec.getValueType(), Val);
696 unsigned NumElts = Vec.getValueType().getVectorNumElements();
697 // We generate a shuffle of InVec and ScVec, so the shuffle mask
698 // should be 0,1,2,3,4,5... with the appropriate element replaced with
700 SmallVector<int, 8> ShufOps;
701 for (unsigned i = 0; i != NumElts; ++i)
702 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
704 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
708 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
711 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
712 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
713 // FIXME: We shouldn't do this for TargetConstantFP's.
714 // FIXME: move this to the DAG Combiner! Note that we can't regress due
715 // to phase ordering between legalized code and the dag combiner. This
716 // probably means that we need to integrate dag combiner and legalizer
718 // We generally can't do this one for long doubles.
719 SDValue Tmp1 = ST->getChain();
720 SDValue Tmp2 = ST->getBasePtr();
722 int SVOffset = ST->getSrcValueOffset();
723 unsigned Alignment = ST->getAlignment();
724 bool isVolatile = ST->isVolatile();
725 bool isNonTemporal = ST->isNonTemporal();
726 DebugLoc dl = ST->getDebugLoc();
727 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
728 if (CFP->getValueType(0) == MVT::f32 &&
729 getTypeAction(MVT::i32) == Legal) {
730 Tmp3 = DAG.getConstant(CFP->getValueAPF().
731 bitcastToAPInt().zextOrTrunc(32),
733 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
734 SVOffset, isVolatile, isNonTemporal, Alignment);
735 } else if (CFP->getValueType(0) == MVT::f64) {
736 // If this target supports 64-bit registers, do a single 64-bit store.
737 if (getTypeAction(MVT::i64) == Legal) {
738 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
739 zextOrTrunc(64), MVT::i64);
740 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
741 SVOffset, isVolatile, isNonTemporal, Alignment);
742 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
743 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
744 // stores. If the target supports neither 32- nor 64-bits, this
745 // xform is certainly not worth it.
746 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
747 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
748 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
749 if (TLI.isBigEndian()) std::swap(Lo, Hi);
751 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(),
752 SVOffset, isVolatile, isNonTemporal, Alignment);
753 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
754 DAG.getIntPtrConstant(4));
755 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
756 isVolatile, isNonTemporal, MinAlign(Alignment, 4U));
758 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
765 /// LegalizeOp - We know that the specified value has a legal type, and
766 /// that its operands are legal. Now ensure that the operation itself
767 /// is legal, recursively ensuring that the operands' operations remain
769 SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
770 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
773 SDNode *Node = Op.getNode();
774 DebugLoc dl = Node->getDebugLoc();
776 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
777 assert(getTypeAction(Node->getValueType(i)) == Legal &&
778 "Unexpected illegal type!");
780 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
781 assert((isTypeLegal(Node->getOperand(i).getValueType()) ||
782 Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
783 "Unexpected illegal type!");
785 // Note that LegalizeOp may be reentered even from single-use nodes, which
786 // means that we always must cache transformed nodes.
787 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
788 if (I != LegalizedNodes.end()) return I->second;
790 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
792 bool isCustom = false;
794 // Figure out the correct action; the way to query this varies by opcode
795 TargetLowering::LegalizeAction Action;
796 bool SimpleFinishLegalizing = true;
797 switch (Node->getOpcode()) {
798 case ISD::INTRINSIC_W_CHAIN:
799 case ISD::INTRINSIC_WO_CHAIN:
800 case ISD::INTRINSIC_VOID:
803 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
805 case ISD::SINT_TO_FP:
806 case ISD::UINT_TO_FP:
807 case ISD::EXTRACT_VECTOR_ELT:
808 Action = TLI.getOperationAction(Node->getOpcode(),
809 Node->getOperand(0).getValueType());
811 case ISD::FP_ROUND_INREG:
812 case ISD::SIGN_EXTEND_INREG: {
813 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
814 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
820 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
821 Node->getOpcode() == ISD::SETCC ? 2 : 1;
822 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
823 EVT OpVT = Node->getOperand(CompareOperand).getValueType();
824 ISD::CondCode CCCode =
825 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
826 Action = TLI.getCondCodeAction(CCCode, OpVT);
827 if (Action == TargetLowering::Legal) {
828 if (Node->getOpcode() == ISD::SELECT_CC)
829 Action = TLI.getOperationAction(Node->getOpcode(),
830 Node->getValueType(0));
832 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
838 // FIXME: Model these properly. LOAD and STORE are complicated, and
839 // STORE expects the unlegalized operand in some cases.
840 SimpleFinishLegalizing = false;
842 case ISD::CALLSEQ_START:
843 case ISD::CALLSEQ_END:
844 // FIXME: This shouldn't be necessary. These nodes have special properties
845 // dealing with the recursive nature of legalization. Removing this
846 // special case should be done as part of making LegalizeDAG non-recursive.
847 SimpleFinishLegalizing = false;
849 case ISD::EXTRACT_ELEMENT:
850 case ISD::FLT_ROUNDS_:
858 case ISD::MERGE_VALUES:
860 case ISD::FRAME_TO_ARGS_OFFSET:
861 case ISD::EH_SJLJ_SETJMP:
862 case ISD::EH_SJLJ_LONGJMP:
863 // These operations lie about being legal: when they claim to be legal,
864 // they should actually be expanded.
865 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
866 if (Action == TargetLowering::Legal)
867 Action = TargetLowering::Expand;
869 case ISD::TRAMPOLINE:
871 case ISD::RETURNADDR:
872 // These operations lie about being legal: when they claim to be legal,
873 // they should actually be custom-lowered.
874 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
875 if (Action == TargetLowering::Legal)
876 Action = TargetLowering::Custom;
878 case ISD::BUILD_VECTOR:
879 // A weird case: legalization for BUILD_VECTOR never legalizes the
881 // FIXME: This really sucks... changing it isn't semantically incorrect,
882 // but it massively pessimizes the code for floating-point BUILD_VECTORs
883 // because ConstantFP operands get legalized into constant pool loads
884 // before the BUILD_VECTOR code can see them. It doesn't usually bite,
885 // though, because BUILD_VECTORS usually get lowered into other nodes
886 // which get legalized properly.
887 SimpleFinishLegalizing = false;
890 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
891 Action = TargetLowering::Legal;
893 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
898 if (SimpleFinishLegalizing) {
899 SmallVector<SDValue, 8> Ops, ResultVals;
900 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
901 Ops.push_back(LegalizeOp(Node->getOperand(i)));
902 switch (Node->getOpcode()) {
909 // Branches tweak the chain to include LastCALLSEQ_END
910 Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0],
912 Ops[0] = LegalizeOp(Ops[0]);
913 LastCALLSEQ_END = DAG.getEntryNode();
920 // Legalizing shifts/rotates requires adjusting the shift amount
921 // to the appropriate width.
922 if (!Ops[1].getValueType().isVector())
923 Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[1]));
928 // Legalizing shifts/rotates requires adjusting the shift amount
929 // to the appropriate width.
930 if (!Ops[2].getValueType().isVector())
931 Ops[2] = LegalizeOp(DAG.getShiftAmountOperand(Ops[2]));
935 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), Ops.data(),
938 case TargetLowering::Legal:
939 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
940 ResultVals.push_back(Result.getValue(i));
942 case TargetLowering::Custom:
943 // FIXME: The handling for custom lowering with multiple results is
945 Tmp1 = TLI.LowerOperation(Result, DAG);
946 if (Tmp1.getNode()) {
947 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
949 ResultVals.push_back(Tmp1);
951 ResultVals.push_back(Tmp1.getValue(i));
957 case TargetLowering::Expand:
958 ExpandNode(Result.getNode(), ResultVals);
960 case TargetLowering::Promote:
961 PromoteNode(Result.getNode(), ResultVals);
964 if (!ResultVals.empty()) {
965 for (unsigned i = 0, e = ResultVals.size(); i != e; ++i) {
966 if (ResultVals[i] != SDValue(Node, i))
967 ResultVals[i] = LegalizeOp(ResultVals[i]);
968 AddLegalizedOperand(SDValue(Node, i), ResultVals[i]);
970 return ResultVals[Op.getResNo()];
974 switch (Node->getOpcode()) {
981 assert(0 && "Do not know how to legalize this operator!");
983 case ISD::BUILD_VECTOR:
984 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
985 default: assert(0 && "This action is not supported yet!");
986 case TargetLowering::Custom:
987 Tmp3 = TLI.LowerOperation(Result, DAG);
988 if (Tmp3.getNode()) {
993 case TargetLowering::Expand:
994 Result = ExpandBUILD_VECTOR(Result.getNode());
998 case ISD::CALLSEQ_START: {
999 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1001 // Recursively Legalize all of the inputs of the call end that do not lead
1002 // to this call start. This ensures that any libcalls that need be inserted
1003 // are inserted *before* the CALLSEQ_START.
1004 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1005 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1006 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
1010 // Now that we have legalized all of the inputs (which may have inserted
1011 // libcalls), create the new CALLSEQ_START node.
1012 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1014 // Merge in the last call to ensure that this call starts after the last
1016 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1017 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1018 Tmp1, LastCALLSEQ_END);
1019 Tmp1 = LegalizeOp(Tmp1);
1022 // Do not try to legalize the target-specific arguments (#1+).
1023 if (Tmp1 != Node->getOperand(0)) {
1024 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1026 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), &Ops[0],
1027 Ops.size()), Result.getResNo());
1030 // Remember that the CALLSEQ_START is legalized.
1031 AddLegalizedOperand(Op.getValue(0), Result);
1032 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1033 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1035 // Now that the callseq_start and all of the non-call nodes above this call
1036 // sequence have been legalized, legalize the call itself. During this
1037 // process, no libcalls can/will be inserted, guaranteeing that no calls
1039 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1040 // Note that we are selecting this call!
1041 LastCALLSEQ_END = SDValue(CallEnd, 0);
1042 IsLegalizingCall = true;
1044 // Legalize the call, starting from the CALLSEQ_END.
1045 LegalizeOp(LastCALLSEQ_END);
1046 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1049 case ISD::CALLSEQ_END:
1050 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1051 // will cause this node to be legalized as well as handling libcalls right.
1052 if (LastCALLSEQ_END.getNode() != Node) {
1053 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
1054 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1055 assert(I != LegalizedNodes.end() &&
1056 "Legalizing the call start should have legalized this node!");
1060 // Otherwise, the call start has been legalized and everything is going
1061 // according to plan. Just legalize ourselves normally here.
1062 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1063 // Do not try to legalize the target-specific arguments (#1+), except for
1064 // an optional flag input.
1065 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1066 if (Tmp1 != Node->getOperand(0)) {
1067 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1069 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1070 &Ops[0], Ops.size()),
1074 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1075 if (Tmp1 != Node->getOperand(0) ||
1076 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1077 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1080 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1081 &Ops[0], Ops.size()),
1085 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1086 // This finishes up call legalization.
1087 IsLegalizingCall = false;
1089 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1090 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1091 if (Node->getNumValues() == 2)
1092 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1093 return Result.getValue(Op.getResNo());
1095 LoadSDNode *LD = cast<LoadSDNode>(Node);
1096 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1097 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1099 ISD::LoadExtType ExtType = LD->getExtensionType();
1100 if (ExtType == ISD::NON_EXTLOAD) {
1101 EVT VT = Node->getValueType(0);
1102 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1103 Tmp1, Tmp2, LD->getOffset()),
1105 Tmp3 = Result.getValue(0);
1106 Tmp4 = Result.getValue(1);
1108 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1109 default: assert(0 && "This action is not supported yet!");
1110 case TargetLowering::Legal:
1111 // If this is an unaligned load and the target doesn't support it,
1113 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
1114 const Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1115 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
1116 if (LD->getAlignment() < ABIAlignment){
1117 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
1119 Tmp3 = Result.getOperand(0);
1120 Tmp4 = Result.getOperand(1);
1121 Tmp3 = LegalizeOp(Tmp3);
1122 Tmp4 = LegalizeOp(Tmp4);
1126 case TargetLowering::Custom:
1127 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1128 if (Tmp1.getNode()) {
1129 Tmp3 = LegalizeOp(Tmp1);
1130 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1133 case TargetLowering::Promote: {
1134 // Only promote a load of vector type to another.
1135 assert(VT.isVector() && "Cannot promote this load!");
1136 // Change base type to a different vector type.
1137 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1139 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
1140 LD->getSrcValueOffset(),
1141 LD->isVolatile(), LD->isNonTemporal(),
1142 LD->getAlignment());
1143 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp1));
1144 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1148 // Since loads produce two values, make sure to remember that we
1149 // legalized both of them.
1150 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
1151 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
1152 return Op.getResNo() ? Tmp4 : Tmp3;
1154 EVT SrcVT = LD->getMemoryVT();
1155 unsigned SrcWidth = SrcVT.getSizeInBits();
1156 int SVOffset = LD->getSrcValueOffset();
1157 unsigned Alignment = LD->getAlignment();
1158 bool isVolatile = LD->isVolatile();
1159 bool isNonTemporal = LD->isNonTemporal();
1161 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
1162 // Some targets pretend to have an i1 loading operation, and actually
1163 // load an i8. This trick is correct for ZEXTLOAD because the top 7
1164 // bits are guaranteed to be zero; it helps the optimizers understand
1165 // that these bits are zero. It is also useful for EXTLOAD, since it
1166 // tells the optimizers that those bits are undefined. It would be
1167 // nice to have an effective generic way of getting these benefits...
1168 // Until such a way is found, don't insist on promoting i1 here.
1169 (SrcVT != MVT::i1 ||
1170 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
1171 // Promote to a byte-sized load if not loading an integral number of
1172 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
1173 unsigned NewWidth = SrcVT.getStoreSizeInBits();
1174 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
1177 // The extra bits are guaranteed to be zero, since we stored them that
1178 // way. A zext load from NVT thus automatically gives zext from SrcVT.
1180 ISD::LoadExtType NewExtType =
1181 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
1183 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0), dl,
1184 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
1185 NVT, isVolatile, isNonTemporal, Alignment);
1187 Ch = Result.getValue(1); // The chain.
1189 if (ExtType == ISD::SEXTLOAD)
1190 // Having the top bits zero doesn't help when sign extending.
1191 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1192 Result.getValueType(),
1193 Result, DAG.getValueType(SrcVT));
1194 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
1195 // All the top bits are guaranteed to be zero - inform the optimizers.
1196 Result = DAG.getNode(ISD::AssertZext, dl,
1197 Result.getValueType(), Result,
1198 DAG.getValueType(SrcVT));
1200 Tmp1 = LegalizeOp(Result);
1201 Tmp2 = LegalizeOp(Ch);
1202 } else if (SrcWidth & (SrcWidth - 1)) {
1203 // If not loading a power-of-2 number of bits, expand as two loads.
1204 assert(!SrcVT.isVector() && "Unsupported extload!");
1205 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
1206 assert(RoundWidth < SrcWidth);
1207 unsigned ExtraWidth = SrcWidth - RoundWidth;
1208 assert(ExtraWidth < RoundWidth);
1209 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1210 "Load size not an integral number of bytes!");
1211 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
1212 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
1214 unsigned IncrementSize;
1216 if (TLI.isLittleEndian()) {
1217 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1218 // Load the bottom RoundWidth bits.
1219 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), dl,
1221 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
1222 isNonTemporal, Alignment);
1224 // Load the remaining ExtraWidth bits.
1225 IncrementSize = RoundWidth / 8;
1226 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1227 DAG.getIntPtrConstant(IncrementSize));
1228 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), dl, Tmp1, Tmp2,
1229 LD->getSrcValue(), SVOffset + IncrementSize,
1230 ExtraVT, isVolatile, isNonTemporal,
1231 MinAlign(Alignment, IncrementSize));
1233 // Build a factor node to remember that this load is independent of
1235 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1238 // Move the top bits to the right place.
1239 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1240 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
1242 // Join the hi and lo parts.
1243 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1245 // Big endian - avoid unaligned loads.
1246 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1247 // Load the top RoundWidth bits.
1248 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), dl, Tmp1, Tmp2,
1249 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
1250 isNonTemporal, Alignment);
1252 // Load the remaining ExtraWidth bits.
1253 IncrementSize = RoundWidth / 8;
1254 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1255 DAG.getIntPtrConstant(IncrementSize));
1256 Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
1257 Node->getValueType(0), dl, Tmp1, Tmp2,
1258 LD->getSrcValue(), SVOffset + IncrementSize,
1259 ExtraVT, isVolatile, isNonTemporal,
1260 MinAlign(Alignment, IncrementSize));
1262 // Build a factor node to remember that this load is independent of
1264 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1267 // Move the top bits to the right place.
1268 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1269 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
1271 // Join the hi and lo parts.
1272 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1275 Tmp1 = LegalizeOp(Result);
1276 Tmp2 = LegalizeOp(Ch);
1278 switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
1279 default: assert(0 && "This action is not supported yet!");
1280 case TargetLowering::Custom:
1283 case TargetLowering::Legal:
1284 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1285 Tmp1, Tmp2, LD->getOffset()),
1287 Tmp1 = Result.getValue(0);
1288 Tmp2 = Result.getValue(1);
1291 Tmp3 = TLI.LowerOperation(Result, DAG);
1292 if (Tmp3.getNode()) {
1293 Tmp1 = LegalizeOp(Tmp3);
1294 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1297 // If this is an unaligned load and the target doesn't support it,
1299 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
1301 LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1302 unsigned ABIAlignment =
1303 TLI.getTargetData()->getABITypeAlignment(Ty);
1304 if (LD->getAlignment() < ABIAlignment){
1305 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
1307 Tmp1 = Result.getOperand(0);
1308 Tmp2 = Result.getOperand(1);
1309 Tmp1 = LegalizeOp(Tmp1);
1310 Tmp2 = LegalizeOp(Tmp2);
1315 case TargetLowering::Expand:
1316 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT)) {
1317 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
1318 LD->getSrcValueOffset(),
1319 LD->isVolatile(), LD->isNonTemporal(),
1320 LD->getAlignment());
1324 ExtendOp = (SrcVT.isFloatingPoint() ?
1325 ISD::FP_EXTEND : ISD::ANY_EXTEND);
1327 case ISD::SEXTLOAD: ExtendOp = ISD::SIGN_EXTEND; break;
1328 case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break;
1329 default: llvm_unreachable("Unexpected extend load type!");
1331 Result = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
1332 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1333 Tmp2 = LegalizeOp(Load.getValue(1));
1336 assert(ExtType != ISD::EXTLOAD &&
1337 "EXTLOAD should always be supported!");
1338 // Turn the unsupported load into an EXTLOAD followed by an explicit
1339 // zero/sign extend inreg.
1340 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), dl,
1341 Tmp1, Tmp2, LD->getSrcValue(),
1342 LD->getSrcValueOffset(), SrcVT,
1343 LD->isVolatile(), LD->isNonTemporal(),
1344 LD->getAlignment());
1346 if (ExtType == ISD::SEXTLOAD)
1347 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1348 Result.getValueType(),
1349 Result, DAG.getValueType(SrcVT));
1351 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT);
1352 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1353 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1358 // Since loads produce two values, make sure to remember that we legalized
1360 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
1361 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
1362 return Op.getResNo() ? Tmp2 : Tmp1;
1366 StoreSDNode *ST = cast<StoreSDNode>(Node);
1367 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
1368 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
1369 int SVOffset = ST->getSrcValueOffset();
1370 unsigned Alignment = ST->getAlignment();
1371 bool isVolatile = ST->isVolatile();
1372 bool isNonTemporal = ST->isNonTemporal();
1374 if (!ST->isTruncatingStore()) {
1375 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
1376 Result = SDValue(OptStore, 0);
1381 Tmp3 = LegalizeOp(ST->getValue());
1382 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1387 EVT VT = Tmp3.getValueType();
1388 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1389 default: assert(0 && "This action is not supported yet!");
1390 case TargetLowering::Legal:
1391 // If this is an unaligned store and the target doesn't support it,
1393 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
1394 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
1395 unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty);
1396 if (ST->getAlignment() < ABIAlignment)
1397 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()),
1401 case TargetLowering::Custom:
1402 Tmp1 = TLI.LowerOperation(Result, DAG);
1403 if (Tmp1.getNode()) Result = Tmp1;
1405 case TargetLowering::Promote:
1406 assert(VT.isVector() && "Unknown legal promote case!");
1407 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, dl,
1408 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
1409 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2,
1410 ST->getSrcValue(), SVOffset, isVolatile,
1411 isNonTemporal, Alignment);
1417 Tmp3 = LegalizeOp(ST->getValue());
1419 EVT StVT = ST->getMemoryVT();
1420 unsigned StWidth = StVT.getSizeInBits();
1422 if (StWidth != StVT.getStoreSizeInBits()) {
1423 // Promote to a byte-sized store with upper bits zero if not
1424 // storing an integral number of bytes. For example, promote
1425 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
1426 EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
1427 StVT.getStoreSizeInBits());
1428 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT);
1429 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1430 SVOffset, NVT, isVolatile, isNonTemporal,
1432 } else if (StWidth & (StWidth - 1)) {
1433 // If not storing a power-of-2 number of bits, expand as two stores.
1434 assert(!StVT.isVector() && "Unsupported truncstore!");
1435 unsigned RoundWidth = 1 << Log2_32(StWidth);
1436 assert(RoundWidth < StWidth);
1437 unsigned ExtraWidth = StWidth - RoundWidth;
1438 assert(ExtraWidth < RoundWidth);
1439 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1440 "Store size not an integral number of bytes!");
1441 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
1442 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
1444 unsigned IncrementSize;
1446 if (TLI.isLittleEndian()) {
1447 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
1448 // Store the bottom RoundWidth bits.
1449 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1451 isVolatile, isNonTemporal, Alignment);
1453 // Store the remaining ExtraWidth bits.
1454 IncrementSize = RoundWidth / 8;
1455 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1456 DAG.getIntPtrConstant(IncrementSize));
1457 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
1458 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
1459 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
1460 SVOffset + IncrementSize, ExtraVT, isVolatile,
1462 MinAlign(Alignment, IncrementSize));
1464 // Big endian - avoid unaligned stores.
1465 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
1466 // Store the top RoundWidth bits.
1467 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
1468 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
1469 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
1470 SVOffset, RoundVT, isVolatile, isNonTemporal,
1473 // Store the remaining ExtraWidth bits.
1474 IncrementSize = RoundWidth / 8;
1475 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1476 DAG.getIntPtrConstant(IncrementSize));
1477 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1478 SVOffset + IncrementSize, ExtraVT, isVolatile,
1480 MinAlign(Alignment, IncrementSize));
1483 // The order of the stores doesn't matter.
1484 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
1486 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
1487 Tmp2 != ST->getBasePtr())
1488 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1493 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
1494 default: assert(0 && "This action is not supported yet!");
1495 case TargetLowering::Legal:
1496 // If this is an unaligned store and the target doesn't support it,
1498 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
1499 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
1500 unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty);
1501 if (ST->getAlignment() < ABIAlignment)
1502 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()),
1506 case TargetLowering::Custom:
1507 Result = TLI.LowerOperation(Result, DAG);
1510 // TRUNCSTORE:i16 i32 -> STORE i16
1511 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
1512 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3);
1513 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1514 SVOffset, isVolatile, isNonTemporal,
1523 assert(Result.getValueType() == Op.getValueType() &&
1524 "Bad legalization!");
1526 // Make sure that the generated code is itself legal.
1528 Result = LegalizeOp(Result);
1530 // Note that LegalizeOp may be reentered even from single-use nodes, which
1531 // means that we always must cache transformed nodes.
1532 AddLegalizedOperand(Op, Result);
1536 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1537 SDValue Vec = Op.getOperand(0);
1538 SDValue Idx = Op.getOperand(1);
1539 DebugLoc dl = Op.getDebugLoc();
1540 // Store the value to a temporary stack slot, then LOAD the returned part.
1541 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1542 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0,
1545 // Add the offset to the index.
1547 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1548 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1549 DAG.getConstant(EltSize, Idx.getValueType()));
1551 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1552 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1554 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1556 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1558 if (Op.getValueType().isVector())
1559 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, NULL, 0,
1562 return DAG.getExtLoad(ISD::EXTLOAD, Op.getValueType(), dl, Ch, StackPtr,
1563 NULL, 0, Vec.getValueType().getVectorElementType(),
1567 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1568 // We can't handle this case efficiently. Allocate a sufficiently
1569 // aligned object on the stack, store each element into it, then load
1570 // the result as a vector.
1571 // Create the stack frame object.
1572 EVT VT = Node->getValueType(0);
1573 EVT EltVT = VT.getVectorElementType();
1574 DebugLoc dl = Node->getDebugLoc();
1575 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1576 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1577 const Value *SV = PseudoSourceValue::getFixedStack(FI);
1579 // Emit a store of each element to the stack slot.
1580 SmallVector<SDValue, 8> Stores;
1581 unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1582 // Store (in the right endianness) the elements to memory.
1583 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1584 // Ignore undef elements.
1585 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1587 unsigned Offset = TypeByteSize*i;
1589 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
1590 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1592 // If the destination vector element type is narrower than the source
1593 // element type, only store the bits necessary.
1594 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1595 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1596 Node->getOperand(i), Idx, SV, Offset,
1597 EltVT, false, false, 0));
1599 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
1600 Node->getOperand(i), Idx, SV, Offset,
1605 if (!Stores.empty()) // Not all undef elements?
1606 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1607 &Stores[0], Stores.size());
1609 StoreChain = DAG.getEntryNode();
1611 // Result is a load from the stack slot.
1612 return DAG.getLoad(VT, dl, StoreChain, FIPtr, SV, 0, false, false, 0);
1615 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
1616 DebugLoc dl = Node->getDebugLoc();
1617 SDValue Tmp1 = Node->getOperand(0);
1618 SDValue Tmp2 = Node->getOperand(1);
1620 // Get the sign bit of the RHS. First obtain a value that has the same
1621 // sign as the sign bit, i.e. negative if and only if the sign bit is 1.
1623 EVT FloatVT = Tmp2.getValueType();
1624 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits());
1625 if (isTypeLegal(IVT)) {
1626 // Convert to an integer with the same sign bit.
1627 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, IVT, Tmp2);
1629 // Store the float to memory, then load the sign part out as an integer.
1630 MVT LoadTy = TLI.getPointerTy();
1631 // First create a temporary that is aligned for both the load and store.
1632 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1633 // Then store the float to it.
1635 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, NULL, 0,
1637 if (TLI.isBigEndian()) {
1638 assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1639 // Load out a legal integer with the same sign bit as the float.
1640 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, NULL, 0, false, false, 0);
1641 } else { // Little endian
1642 SDValue LoadPtr = StackPtr;
1643 // The float may be wider than the integer we are going to load. Advance
1644 // the pointer so that the loaded integer will contain the sign bit.
1645 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits();
1646 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8;
1647 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(),
1648 LoadPtr, DAG.getIntPtrConstant(ByteOffset));
1649 // Load a legal integer containing the sign bit.
1650 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, NULL, 0, false, false, 0);
1651 // Move the sign bit to the top bit of the loaded integer.
1652 unsigned BitShift = LoadTy.getSizeInBits() -
1653 (FloatVT.getSizeInBits() - 8 * ByteOffset);
1654 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?");
1656 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit,
1657 DAG.getConstant(BitShift,TLI.getShiftAmountTy()));
1660 // Now get the sign bit proper, by seeing whether the value is negative.
1661 SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()),
1662 SignBit, DAG.getConstant(0, SignBit.getValueType()),
1664 // Get the absolute value of the result.
1665 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1666 // Select between the nabs and abs value based on the sign bit of
1668 return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit,
1669 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1673 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1674 SmallVectorImpl<SDValue> &Results) {
1675 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1676 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1677 " not tell us which reg is the stack pointer!");
1678 DebugLoc dl = Node->getDebugLoc();
1679 EVT VT = Node->getValueType(0);
1680 SDValue Tmp1 = SDValue(Node, 0);
1681 SDValue Tmp2 = SDValue(Node, 1);
1682 SDValue Tmp3 = Node->getOperand(2);
1683 SDValue Chain = Tmp1.getOperand(0);
1685 // Chain the dynamic stack allocation so that it doesn't modify the stack
1686 // pointer when other instructions are using the stack.
1687 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1689 SDValue Size = Tmp2.getOperand(1);
1690 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1691 Chain = SP.getValue(1);
1692 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1693 unsigned StackAlign = TM.getFrameInfo()->getStackAlignment();
1694 if (Align > StackAlign)
1695 SP = DAG.getNode(ISD::AND, dl, VT, SP,
1696 DAG.getConstant(-(uint64_t)Align, VT));
1697 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1698 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1700 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1701 DAG.getIntPtrConstant(0, true), SDValue());
1703 Results.push_back(Tmp1);
1704 Results.push_back(Tmp2);
1707 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
1708 /// condition code CC on the current target. This routine expands SETCC with
1709 /// illegal condition code into AND / OR of multiple SETCC values.
1710 void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1711 SDValue &LHS, SDValue &RHS,
1714 EVT OpVT = LHS.getValueType();
1715 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1716 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1717 default: assert(0 && "Unknown condition code action!");
1718 case TargetLowering::Legal:
1721 case TargetLowering::Expand: {
1722 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1725 default: assert(0 && "Don't know how to expand this condition!");
1726 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break;
1727 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1728 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1729 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1730 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1731 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1732 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1733 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1734 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1735 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1736 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1737 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1738 // FIXME: Implement more expansions.
1741 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1742 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1743 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1751 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
1752 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1753 /// a load from the stack slot to DestVT, extending it if needed.
1754 /// The resultant code need not be legal.
1755 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
1759 // Create the stack frame object.
1761 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType().
1762 getTypeForEVT(*DAG.getContext()));
1763 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1765 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1766 int SPFI = StackPtrFI->getIndex();
1767 const Value *SV = PseudoSourceValue::getFixedStack(SPFI);
1769 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
1770 unsigned SlotSize = SlotVT.getSizeInBits();
1771 unsigned DestSize = DestVT.getSizeInBits();
1772 const Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
1773 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(DestType);
1775 // Emit a store to the stack slot. Use a truncstore if the input value is
1776 // later than DestVT.
1779 if (SrcSize > SlotSize)
1780 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1781 SV, 0, SlotVT, false, false, SrcAlign);
1783 assert(SrcSize == SlotSize && "Invalid store");
1784 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1785 SV, 0, false, false, SrcAlign);
1788 // Result is a load from the stack slot.
1789 if (SlotSize == DestSize)
1790 return DAG.getLoad(DestVT, dl, Store, FIPtr, SV, 0, false, false,
1793 assert(SlotSize < DestSize && "Unknown extension!");
1794 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, dl, Store, FIPtr, SV, 0, SlotVT,
1795 false, false, DestAlign);
1798 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1799 DebugLoc dl = Node->getDebugLoc();
1800 // Create a vector sized/aligned stack slot, store the value to element #0,
1801 // then load the whole vector back out.
1802 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1804 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1805 int SPFI = StackPtrFI->getIndex();
1807 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0),
1809 PseudoSourceValue::getFixedStack(SPFI), 0,
1810 Node->getValueType(0).getVectorElementType(),
1812 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
1813 PseudoSourceValue::getFixedStack(SPFI), 0,
1818 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
1819 /// support the operation, but do support the resultant vector type.
1820 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1821 unsigned NumElems = Node->getNumOperands();
1822 SDValue Value1, Value2;
1823 DebugLoc dl = Node->getDebugLoc();
1824 EVT VT = Node->getValueType(0);
1825 EVT OpVT = Node->getOperand(0).getValueType();
1826 EVT EltVT = VT.getVectorElementType();
1828 // If the only non-undef value is the low element, turn this into a
1829 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1830 bool isOnlyLowElement = true;
1831 bool MoreThanTwoValues = false;
1832 bool isConstant = true;
1833 for (unsigned i = 0; i < NumElems; ++i) {
1834 SDValue V = Node->getOperand(i);
1835 if (V.getOpcode() == ISD::UNDEF)
1838 isOnlyLowElement = false;
1839 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1842 if (!Value1.getNode()) {
1844 } else if (!Value2.getNode()) {
1847 } else if (V != Value1 && V != Value2) {
1848 MoreThanTwoValues = true;
1852 if (!Value1.getNode())
1853 return DAG.getUNDEF(VT);
1855 if (isOnlyLowElement)
1856 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1858 // If all elements are constants, create a load from the constant pool.
1860 std::vector<Constant*> CV;
1861 for (unsigned i = 0, e = NumElems; i != e; ++i) {
1862 if (ConstantFPSDNode *V =
1863 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1864 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1865 } else if (ConstantSDNode *V =
1866 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1868 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1870 // If OpVT and EltVT don't match, EltVT is not legal and the
1871 // element values have been promoted/truncated earlier. Undo this;
1872 // we don't want a v16i8 to become a v16i32 for example.
1873 const ConstantInt *CI = V->getConstantIntValue();
1874 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
1875 CI->getZExtValue()));
1878 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
1879 const Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
1880 CV.push_back(UndefValue::get(OpNTy));
1883 Constant *CP = ConstantVector::get(CV);
1884 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
1885 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
1886 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
1887 PseudoSourceValue::getConstantPool(), 0,
1888 false, false, Alignment);
1891 if (!MoreThanTwoValues) {
1892 SmallVector<int, 8> ShuffleVec(NumElems, -1);
1893 for (unsigned i = 0; i < NumElems; ++i) {
1894 SDValue V = Node->getOperand(i);
1895 if (V.getOpcode() == ISD::UNDEF)
1897 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
1899 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
1900 // Get the splatted value into the low element of a vector register.
1901 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
1903 if (Value2.getNode())
1904 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
1906 Vec2 = DAG.getUNDEF(VT);
1908 // Return shuffle(LowValVec, undef, <0,0,0,0>)
1909 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
1913 // Otherwise, we can't handle this case efficiently.
1914 return ExpandVectorBuildThroughStack(Node);
1917 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
1918 // does not fit into a register, return the lo part and set the hi part to the
1919 // by-reg argument. If it does fit into a single register, return the result
1920 // and leave the Hi part unset.
1921 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
1923 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
1924 // The input chain to this libcall is the entry node of the function.
1925 // Legalizing the call will automatically add the previous call to the
1927 SDValue InChain = DAG.getEntryNode();
1929 TargetLowering::ArgListTy Args;
1930 TargetLowering::ArgListEntry Entry;
1931 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1932 EVT ArgVT = Node->getOperand(i).getValueType();
1933 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1934 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
1935 Entry.isSExt = isSigned;
1936 Entry.isZExt = !isSigned;
1937 Args.push_back(Entry);
1939 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1940 TLI.getPointerTy());
1942 // Splice the libcall in wherever FindInputOutputChains tells us to.
1943 const Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
1944 std::pair<SDValue, SDValue> CallInfo =
1945 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
1946 0, TLI.getLibcallCallingConv(LC), false,
1947 /*isReturnValueUsed=*/true,
1948 Callee, Args, DAG, Node->getDebugLoc());
1950 // Legalize the call sequence, starting with the chain. This will advance
1951 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
1952 // was added by LowerCallTo (guaranteeing proper serialization of calls).
1953 LegalizeOp(CallInfo.second);
1954 return CallInfo.first;
1957 // ExpandChainLibCall - Expand a node into a call to a libcall. Similar to
1958 // ExpandLibCall except that the first operand is the in-chain.
1959 std::pair<SDValue, SDValue>
1960 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
1963 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
1964 SDValue InChain = Node->getOperand(0);
1966 TargetLowering::ArgListTy Args;
1967 TargetLowering::ArgListEntry Entry;
1968 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) {
1969 EVT ArgVT = Node->getOperand(i).getValueType();
1970 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1971 Entry.Node = Node->getOperand(i);
1973 Entry.isSExt = isSigned;
1974 Entry.isZExt = !isSigned;
1975 Args.push_back(Entry);
1977 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1978 TLI.getPointerTy());
1980 // Splice the libcall in wherever FindInputOutputChains tells us to.
1981 const Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
1982 std::pair<SDValue, SDValue> CallInfo =
1983 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
1984 0, TLI.getLibcallCallingConv(LC), false,
1985 /*isReturnValueUsed=*/true,
1986 Callee, Args, DAG, Node->getDebugLoc());
1988 // Legalize the call sequence, starting with the chain. This will advance
1989 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
1990 // was added by LowerCallTo (guaranteeing proper serialization of calls).
1991 LegalizeOp(CallInfo.second);
1995 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
1996 RTLIB::Libcall Call_F32,
1997 RTLIB::Libcall Call_F64,
1998 RTLIB::Libcall Call_F80,
1999 RTLIB::Libcall Call_PPCF128) {
2001 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
2002 default: assert(0 && "Unexpected request for libcall!");
2003 case MVT::f32: LC = Call_F32; break;
2004 case MVT::f64: LC = Call_F64; break;
2005 case MVT::f80: LC = Call_F80; break;
2006 case MVT::ppcf128: LC = Call_PPCF128; break;
2008 return ExpandLibCall(LC, Node, false);
2011 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
2012 RTLIB::Libcall Call_I8,
2013 RTLIB::Libcall Call_I16,
2014 RTLIB::Libcall Call_I32,
2015 RTLIB::Libcall Call_I64,
2016 RTLIB::Libcall Call_I128) {
2018 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
2019 default: assert(0 && "Unexpected request for libcall!");
2020 case MVT::i8: LC = Call_I8; break;
2021 case MVT::i16: LC = Call_I16; break;
2022 case MVT::i32: LC = Call_I32; break;
2023 case MVT::i64: LC = Call_I64; break;
2024 case MVT::i128: LC = Call_I128; break;
2026 return ExpandLibCall(LC, Node, isSigned);
2029 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
2030 /// INT_TO_FP operation of the specified operand when the target requests that
2031 /// we expand it. At this point, we know that the result and operand types are
2032 /// legal for the target.
2033 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
2037 if (Op0.getValueType() == MVT::i32) {
2038 // simple 32-bit [signed|unsigned] integer to float/double expansion
2040 // Get the stack frame index of a 8 byte buffer.
2041 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2043 // word offset constant for Hi/Lo address computation
2044 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
2045 // set up Hi and Lo (into buffer) address based on endian
2046 SDValue Hi = StackSlot;
2047 SDValue Lo = DAG.getNode(ISD::ADD, dl,
2048 TLI.getPointerTy(), StackSlot, WordOff);
2049 if (TLI.isLittleEndian())
2052 // if signed map to unsigned space
2055 // constant used to invert sign bit (signed to unsigned mapping)
2056 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
2057 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2061 // store the lo of the constructed double - based on integer input
2062 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
2063 Op0Mapped, Lo, NULL, 0,
2065 // initial hi portion of constructed double
2066 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
2067 // store the hi of the constructed double - biased exponent
2068 SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0,
2070 // load the constructed double
2071 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0,
2073 // FP constant to bias correct the final result
2074 SDValue Bias = DAG.getConstantFP(isSigned ?
2075 BitsToDouble(0x4330000080000000ULL) :
2076 BitsToDouble(0x4330000000000000ULL),
2078 // subtract the bias
2079 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2082 // handle final rounding
2083 if (DestVT == MVT::f64) {
2086 } else if (DestVT.bitsLT(MVT::f64)) {
2087 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2088 DAG.getIntPtrConstant(0));
2089 } else if (DestVT.bitsGT(MVT::f64)) {
2090 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2094 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2095 // Code below here assumes !isSigned without checking again.
2097 // Implementation of unsigned i64 to f64 following the algorithm in
2098 // __floatundidf in compiler_rt. This implementation has the advantage
2099 // of performing rounding correctly, both in the default rounding mode
2100 // and in all alternate rounding modes.
2101 // TODO: Generalize this for use with other types.
2102 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
2104 DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64);
2105 SDValue TwoP84PlusTwoP52 =
2106 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64);
2108 DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64);
2110 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32);
2111 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2112 DAG.getConstant(32, MVT::i64));
2113 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2114 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2115 SDValue LoFlt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, LoOr);
2116 SDValue HiFlt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, HiOr);
2117 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
2119 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
2122 // Implementation of unsigned i64 to f32. This implementation has the
2123 // advantage of performing rounding correctly.
2124 // TODO: Generalize this for use with other types.
2125 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) {
2126 EVT SHVT = TLI.getShiftAmountTy();
2128 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2129 DAG.getConstant(UINT64_C(0xfffffffffffff800), MVT::i64));
2130 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
2131 DAG.getConstant(UINT64_C(0x800), MVT::i64));
2132 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2133 DAG.getConstant(UINT64_C(0x7ff), MVT::i64));
2134 SDValue Ne = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2135 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE);
2136 SDValue Sel = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ne, Or, Op0);
2137 SDValue Ge = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2138 Op0, DAG.getConstant(UINT64_C(0x0020000000000000), MVT::i64),
2140 SDValue Sel2 = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ge, Sel, Op0);
2142 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2143 DAG.getConstant(32, SHVT));
2144 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh);
2145 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc);
2147 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), MVT::f64);
2148 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt);
2149 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2);
2150 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo);
2151 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2);
2152 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd,
2153 DAG.getIntPtrConstant(0));
2157 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2159 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()),
2160 Op0, DAG.getConstant(0, Op0.getValueType()),
2162 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
2163 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
2164 SignSet, Four, Zero);
2166 // If the sign bit of the integer is set, the large number will be treated
2167 // as a negative number. To counteract this, the dynamic code adds an
2168 // offset depending on the data type.
2170 switch (Op0.getValueType().getSimpleVT().SimpleTy) {
2171 default: assert(0 && "Unsupported integer type!");
2172 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2173 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2174 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2175 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2177 if (TLI.isLittleEndian()) FF <<= 32;
2178 Constant *FudgeFactor = ConstantInt::get(
2179 Type::getInt64Ty(*DAG.getContext()), FF);
2181 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
2182 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2183 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
2184 Alignment = std::min(Alignment, 4u);
2186 if (DestVT == MVT::f32)
2187 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2188 PseudoSourceValue::getConstantPool(), 0,
2189 false, false, Alignment);
2192 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT, dl,
2193 DAG.getEntryNode(), CPIdx,
2194 PseudoSourceValue::getConstantPool(), 0,
2195 MVT::f32, false, false, Alignment));
2198 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2201 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
2202 /// *INT_TO_FP operation of the specified operand when the target requests that
2203 /// we promote it. At this point, we know that the result and operand types are
2204 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2205 /// operation that takes a larger input.
2206 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2210 // First step, figure out the appropriate *INT_TO_FP operation to use.
2211 EVT NewInTy = LegalOp.getValueType();
2213 unsigned OpToUse = 0;
2215 // Scan for the appropriate larger type to use.
2217 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2218 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2220 // If the target supports SINT_TO_FP of this type, use it.
2221 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2222 OpToUse = ISD::SINT_TO_FP;
2225 if (isSigned) continue;
2227 // If the target supports UINT_TO_FP of this type, use it.
2228 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2229 OpToUse = ISD::UINT_TO_FP;
2233 // Otherwise, try a larger type.
2236 // Okay, we found the operation and type to use. Zero extend our input to the
2237 // desired type then run the operation on it.
2238 return DAG.getNode(OpToUse, dl, DestVT,
2239 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2240 dl, NewInTy, LegalOp));
2243 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
2244 /// FP_TO_*INT operation of the specified operand when the target requests that
2245 /// we promote it. At this point, we know that the result and operand types are
2246 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2247 /// operation that returns a larger result.
2248 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2252 // First step, figure out the appropriate FP_TO*INT operation to use.
2253 EVT NewOutTy = DestVT;
2255 unsigned OpToUse = 0;
2257 // Scan for the appropriate larger type to use.
2259 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2260 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2262 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2263 OpToUse = ISD::FP_TO_SINT;
2267 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2268 OpToUse = ISD::FP_TO_UINT;
2272 // Otherwise, try a larger type.
2276 // Okay, we found the operation and type to use.
2277 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2279 // Truncate the result of the extended FP_TO_*INT operation to the desired
2281 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2284 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
2286 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) {
2287 EVT VT = Op.getValueType();
2288 EVT SHVT = TLI.getShiftAmountTy();
2289 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2290 switch (VT.getSimpleVT().SimpleTy) {
2291 default: assert(0 && "Unhandled Expand type in BSWAP!");
2293 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2294 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2295 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2297 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2298 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2299 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2300 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2301 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
2302 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
2303 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2304 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2305 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2307 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
2308 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
2309 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2310 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2311 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2312 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2313 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
2314 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
2315 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
2316 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
2317 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
2318 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
2319 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
2320 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
2321 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2322 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2323 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2324 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2325 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2326 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2327 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2331 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
2333 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2336 default: assert(0 && "Cannot expand this yet!");
2338 static const uint64_t mask[6] = {
2339 0x5555555555555555ULL, 0x3333333333333333ULL,
2340 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
2341 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
2343 EVT VT = Op.getValueType();
2344 EVT ShVT = TLI.getShiftAmountTy();
2345 unsigned len = VT.getSizeInBits();
2346 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2347 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
2348 unsigned EltSize = VT.isVector() ?
2349 VT.getVectorElementType().getSizeInBits() : len;
2350 SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT);
2351 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2352 Op = DAG.getNode(ISD::ADD, dl, VT,
2353 DAG.getNode(ISD::AND, dl, VT, Op, Tmp2),
2354 DAG.getNode(ISD::AND, dl, VT,
2355 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3),
2361 // for now, we do this:
2362 // x = x | (x >> 1);
2363 // x = x | (x >> 2);
2365 // x = x | (x >>16);
2366 // x = x | (x >>32); // for 64-bit input
2367 // return popcount(~x);
2369 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
2370 EVT VT = Op.getValueType();
2371 EVT ShVT = TLI.getShiftAmountTy();
2372 unsigned len = VT.getSizeInBits();
2373 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2374 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2375 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2376 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2378 Op = DAG.getNOT(dl, Op, VT);
2379 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2382 // for now, we use: { return popcount(~x & (x - 1)); }
2383 // unless the target has ctlz but not ctpop, in which case we use:
2384 // { return 32 - nlz(~x & (x-1)); }
2385 // see also http://www.hackersdelight.org/HDcode/ntz.cc
2386 EVT VT = Op.getValueType();
2387 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2388 DAG.getNOT(dl, Op, VT),
2389 DAG.getNode(ISD::SUB, dl, VT, Op,
2390 DAG.getConstant(1, VT)));
2391 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2392 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2393 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2394 return DAG.getNode(ISD::SUB, dl, VT,
2395 DAG.getConstant(VT.getSizeInBits(), VT),
2396 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2397 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2402 std::pair <SDValue, SDValue> SelectionDAGLegalize::ExpandAtomic(SDNode *Node) {
2403 unsigned Opc = Node->getOpcode();
2404 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
2409 llvm_unreachable("Unhandled atomic intrinsic Expand!");
2411 case ISD::ATOMIC_SWAP:
2412 switch (VT.SimpleTy) {
2413 default: llvm_unreachable("Unexpected value type for atomic!");
2414 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break;
2415 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
2416 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
2417 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
2420 case ISD::ATOMIC_CMP_SWAP:
2421 switch (VT.SimpleTy) {
2422 default: llvm_unreachable("Unexpected value type for atomic!");
2423 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break;
2424 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;
2425 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;
2426 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
2429 case ISD::ATOMIC_LOAD_ADD:
2430 switch (VT.SimpleTy) {
2431 default: llvm_unreachable("Unexpected value type for atomic!");
2432 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break;
2433 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;
2434 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;
2435 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
2438 case ISD::ATOMIC_LOAD_SUB:
2439 switch (VT.SimpleTy) {
2440 default: llvm_unreachable("Unexpected value type for atomic!");
2441 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break;
2442 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;
2443 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;
2444 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
2447 case ISD::ATOMIC_LOAD_AND:
2448 switch (VT.SimpleTy) {
2449 default: llvm_unreachable("Unexpected value type for atomic!");
2450 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break;
2451 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;
2452 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;
2453 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
2456 case ISD::ATOMIC_LOAD_OR:
2457 switch (VT.SimpleTy) {
2458 default: llvm_unreachable("Unexpected value type for atomic!");
2459 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break;
2460 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;
2461 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;
2462 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
2465 case ISD::ATOMIC_LOAD_XOR:
2466 switch (VT.SimpleTy) {
2467 default: llvm_unreachable("Unexpected value type for atomic!");
2468 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break;
2469 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;
2470 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;
2471 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
2474 case ISD::ATOMIC_LOAD_NAND:
2475 switch (VT.SimpleTy) {
2476 default: llvm_unreachable("Unexpected value type for atomic!");
2477 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break;
2478 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;
2479 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;
2480 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
2485 return ExpandChainLibCall(LC, Node, false);
2488 void SelectionDAGLegalize::ExpandNode(SDNode *Node,
2489 SmallVectorImpl<SDValue> &Results) {
2490 DebugLoc dl = Node->getDebugLoc();
2491 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2492 switch (Node->getOpcode()) {
2496 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
2497 Results.push_back(Tmp1);
2500 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2502 case ISD::FRAMEADDR:
2503 case ISD::RETURNADDR:
2504 case ISD::FRAME_TO_ARGS_OFFSET:
2505 Results.push_back(DAG.getConstant(0, Node->getValueType(0)));
2507 case ISD::FLT_ROUNDS_:
2508 Results.push_back(DAG.getConstant(1, Node->getValueType(0)));
2510 case ISD::EH_RETURN:
2514 case ISD::EH_SJLJ_LONGJMP:
2515 Results.push_back(Node->getOperand(0));
2517 case ISD::EH_SJLJ_SETJMP:
2518 Results.push_back(DAG.getConstant(0, MVT::i32));
2519 Results.push_back(Node->getOperand(0));
2521 case ISD::MEMBARRIER: {
2522 // If the target didn't lower this, lower it to '__sync_synchronize()' call
2523 TargetLowering::ArgListTy Args;
2524 std::pair<SDValue, SDValue> CallResult =
2525 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()),
2526 false, false, false, false, 0, CallingConv::C, false,
2527 /*isReturnValueUsed=*/true,
2528 DAG.getExternalSymbol("__sync_synchronize",
2529 TLI.getPointerTy()),
2531 Results.push_back(CallResult.second);
2534 // By default, atomic intrinsics are marked Legal and lowered. Targets
2535 // which don't support them directly, however, may want libcalls, in which
2536 // case they mark them Expand, and we get here.
2537 // FIXME: Unimplemented for now. Add libcalls.
2538 case ISD::ATOMIC_SWAP:
2539 case ISD::ATOMIC_LOAD_ADD:
2540 case ISD::ATOMIC_LOAD_SUB:
2541 case ISD::ATOMIC_LOAD_AND:
2542 case ISD::ATOMIC_LOAD_OR:
2543 case ISD::ATOMIC_LOAD_XOR:
2544 case ISD::ATOMIC_LOAD_NAND:
2545 case ISD::ATOMIC_LOAD_MIN:
2546 case ISD::ATOMIC_LOAD_MAX:
2547 case ISD::ATOMIC_LOAD_UMIN:
2548 case ISD::ATOMIC_LOAD_UMAX:
2549 case ISD::ATOMIC_CMP_SWAP: {
2550 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node);
2551 Results.push_back(Tmp.first);
2552 Results.push_back(Tmp.second);
2555 case ISD::DYNAMIC_STACKALLOC:
2556 ExpandDYNAMIC_STACKALLOC(Node, Results);
2558 case ISD::MERGE_VALUES:
2559 for (unsigned i = 0; i < Node->getNumValues(); i++)
2560 Results.push_back(Node->getOperand(i));
2563 EVT VT = Node->getValueType(0);
2565 Results.push_back(DAG.getConstant(0, VT));
2567 assert(VT.isFloatingPoint() && "Unknown value type!");
2568 Results.push_back(DAG.getConstantFP(0, VT));
2573 // If this operation is not supported, lower it to 'abort()' call
2574 TargetLowering::ArgListTy Args;
2575 std::pair<SDValue, SDValue> CallResult =
2576 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()),
2577 false, false, false, false, 0, CallingConv::C, false,
2578 /*isReturnValueUsed=*/true,
2579 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
2581 Results.push_back(CallResult.second);
2585 case ISD::BIT_CONVERT:
2586 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
2587 Node->getValueType(0), dl);
2588 Results.push_back(Tmp1);
2590 case ISD::FP_EXTEND:
2591 Tmp1 = EmitStackConvert(Node->getOperand(0),
2592 Node->getOperand(0).getValueType(),
2593 Node->getValueType(0), dl);
2594 Results.push_back(Tmp1);
2596 case ISD::SIGN_EXTEND_INREG: {
2597 // NOTE: we could fall back on load/store here too for targets without
2598 // SAR. However, it is doubtful that any exist.
2599 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2600 EVT VT = Node->getValueType(0);
2601 EVT ShiftAmountTy = TLI.getShiftAmountTy();
2604 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
2605 ExtraVT.getScalarType().getSizeInBits();
2606 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy);
2607 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
2608 Node->getOperand(0), ShiftCst);
2609 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
2610 Results.push_back(Tmp1);
2613 case ISD::FP_ROUND_INREG: {
2614 // The only way we can lower this is to turn it into a TRUNCSTORE,
2615 // EXTLOAD pair, targetting a temporary location (a stack slot).
2617 // NOTE: there is a choice here between constantly creating new stack
2618 // slots and always reusing the same one. We currently always create
2619 // new ones, as reuse may inhibit scheduling.
2620 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2621 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
2622 Node->getValueType(0), dl);
2623 Results.push_back(Tmp1);
2626 case ISD::SINT_TO_FP:
2627 case ISD::UINT_TO_FP:
2628 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
2629 Node->getOperand(0), Node->getValueType(0), dl);
2630 Results.push_back(Tmp1);
2632 case ISD::FP_TO_UINT: {
2633 SDValue True, False;
2634 EVT VT = Node->getOperand(0).getValueType();
2635 EVT NVT = Node->getValueType(0);
2636 const uint64_t zero[] = {0, 0};
2637 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero));
2638 APInt x = APInt::getSignBit(NVT.getSizeInBits());
2639 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
2640 Tmp1 = DAG.getConstantFP(apf, VT);
2641 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
2642 Node->getOperand(0),
2644 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
2645 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
2646 DAG.getNode(ISD::FSUB, dl, VT,
2647 Node->getOperand(0), Tmp1));
2648 False = DAG.getNode(ISD::XOR, dl, NVT, False,
2649 DAG.getConstant(x, NVT));
2650 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False);
2651 Results.push_back(Tmp1);
2655 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2656 EVT VT = Node->getValueType(0);
2657 Tmp1 = Node->getOperand(0);
2658 Tmp2 = Node->getOperand(1);
2659 unsigned Align = Node->getConstantOperandVal(3);
2661 SDValue VAListLoad = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0,
2663 SDValue VAList = VAListLoad;
2665 if (Align > TLI.getMinStackArgumentAlignment()) {
2666 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
2668 VAList = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
2669 DAG.getConstant(Align - 1,
2670 TLI.getPointerTy()));
2672 VAList = DAG.getNode(ISD::AND, dl, TLI.getPointerTy(), VAList,
2673 DAG.getConstant(-Align,
2674 TLI.getPointerTy()));
2677 // Increment the pointer, VAList, to the next vaarg
2678 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
2679 DAG.getConstant(TLI.getTargetData()->
2680 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())),
2681 TLI.getPointerTy()));
2682 // Store the incremented VAList to the legalized pointer
2683 Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2, V, 0,
2685 // Load the actual argument out of the pointer VAList
2686 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, NULL, 0,
2688 Results.push_back(Results[0].getValue(1));
2692 // This defaults to loading a pointer from the input and storing it to the
2693 // output, returning the chain.
2694 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
2695 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
2696 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0),
2697 Node->getOperand(2), VS, 0, false, false, 0);
2698 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1), VD, 0,
2700 Results.push_back(Tmp1);
2703 case ISD::EXTRACT_VECTOR_ELT:
2704 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
2705 // This must be an access of the only element. Return it.
2706 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0),
2707 Node->getOperand(0));
2709 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
2710 Results.push_back(Tmp1);
2712 case ISD::EXTRACT_SUBVECTOR:
2713 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
2715 case ISD::CONCAT_VECTORS: {
2716 Results.push_back(ExpandVectorBuildThroughStack(Node));
2719 case ISD::SCALAR_TO_VECTOR:
2720 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
2722 case ISD::INSERT_VECTOR_ELT:
2723 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
2724 Node->getOperand(1),
2725 Node->getOperand(2), dl));
2727 case ISD::VECTOR_SHUFFLE: {
2728 SmallVector<int, 8> Mask;
2729 cast<ShuffleVectorSDNode>(Node)->getMask(Mask);
2731 EVT VT = Node->getValueType(0);
2732 EVT EltVT = VT.getVectorElementType();
2733 if (getTypeAction(EltVT) == Promote)
2734 EltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
2735 unsigned NumElems = VT.getVectorNumElements();
2736 SmallVector<SDValue, 8> Ops;
2737 for (unsigned i = 0; i != NumElems; ++i) {
2739 Ops.push_back(DAG.getUNDEF(EltVT));
2742 unsigned Idx = Mask[i];
2744 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
2745 Node->getOperand(0),
2746 DAG.getIntPtrConstant(Idx)));
2748 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
2749 Node->getOperand(1),
2750 DAG.getIntPtrConstant(Idx - NumElems)));
2752 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
2753 Results.push_back(Tmp1);
2756 case ISD::EXTRACT_ELEMENT: {
2757 EVT OpTy = Node->getOperand(0).getValueType();
2758 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
2760 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
2761 DAG.getConstant(OpTy.getSizeInBits()/2,
2762 TLI.getShiftAmountTy()));
2763 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
2766 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
2767 Node->getOperand(0));
2769 Results.push_back(Tmp1);
2772 case ISD::STACKSAVE:
2773 // Expand to CopyFromReg if the target set
2774 // StackPointerRegisterToSaveRestore.
2775 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2776 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
2777 Node->getValueType(0)));
2778 Results.push_back(Results[0].getValue(1));
2780 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
2781 Results.push_back(Node->getOperand(0));
2784 case ISD::STACKRESTORE:
2785 // Expand to CopyToReg if the target set
2786 // StackPointerRegisterToSaveRestore.
2787 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2788 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
2789 Node->getOperand(1)));
2791 Results.push_back(Node->getOperand(0));
2794 case ISD::FCOPYSIGN:
2795 Results.push_back(ExpandFCOPYSIGN(Node));
2798 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2799 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2800 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
2801 Node->getOperand(0));
2802 Results.push_back(Tmp1);
2805 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2806 EVT VT = Node->getValueType(0);
2807 Tmp1 = Node->getOperand(0);
2808 Tmp2 = DAG.getConstantFP(0.0, VT);
2809 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
2810 Tmp1, Tmp2, ISD::SETUGT);
2811 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
2812 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3);
2813 Results.push_back(Tmp1);
2817 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
2818 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128));
2821 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
2822 RTLIB::SIN_F80, RTLIB::SIN_PPCF128));
2825 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
2826 RTLIB::COS_F80, RTLIB::COS_PPCF128));
2829 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
2830 RTLIB::LOG_F80, RTLIB::LOG_PPCF128));
2833 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
2834 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128));
2837 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
2838 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128));
2841 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
2842 RTLIB::EXP_F80, RTLIB::EXP_PPCF128));
2845 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
2846 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128));
2849 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
2850 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128));
2853 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
2854 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128));
2857 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
2858 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128));
2861 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
2862 RTLIB::RINT_F80, RTLIB::RINT_PPCF128));
2864 case ISD::FNEARBYINT:
2865 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
2866 RTLIB::NEARBYINT_F64,
2867 RTLIB::NEARBYINT_F80,
2868 RTLIB::NEARBYINT_PPCF128));
2871 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
2872 RTLIB::POWI_F80, RTLIB::POWI_PPCF128));
2875 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
2876 RTLIB::POW_F80, RTLIB::POW_PPCF128));
2879 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
2880 RTLIB::DIV_F80, RTLIB::DIV_PPCF128));
2883 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
2884 RTLIB::REM_F80, RTLIB::REM_PPCF128));
2886 case ISD::FP16_TO_FP32:
2887 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
2889 case ISD::FP32_TO_FP16:
2890 Results.push_back(ExpandLibCall(RTLIB::FPROUND_F32_F16, Node, false));
2892 case ISD::ConstantFP: {
2893 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
2894 // Check to see if this FP immediate is already legal.
2895 // If this is a legal constant, turn it into a TargetConstantFP node.
2896 if (TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
2897 Results.push_back(SDValue(Node, 0));
2899 Results.push_back(ExpandConstantFP(CFP, true, DAG, TLI));
2902 case ISD::EHSELECTION: {
2903 unsigned Reg = TLI.getExceptionSelectorRegister();
2904 assert(Reg && "Can't expand to unknown register!");
2905 Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg,
2906 Node->getValueType(0)));
2907 Results.push_back(Results[0].getValue(1));
2910 case ISD::EXCEPTIONADDR: {
2911 unsigned Reg = TLI.getExceptionAddressRegister();
2912 assert(Reg && "Can't expand to unknown register!");
2913 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg,
2914 Node->getValueType(0)));
2915 Results.push_back(Results[0].getValue(1));
2919 EVT VT = Node->getValueType(0);
2920 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
2921 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
2922 "Don't know how to expand this subtraction!");
2923 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
2924 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
2925 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT));
2926 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
2931 EVT VT = Node->getValueType(0);
2932 SDVTList VTs = DAG.getVTList(VT, VT);
2933 bool isSigned = Node->getOpcode() == ISD::SREM;
2934 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
2935 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2936 Tmp2 = Node->getOperand(0);
2937 Tmp3 = Node->getOperand(1);
2938 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) {
2939 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
2940 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
2942 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
2943 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
2944 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
2945 } else if (isSigned) {
2946 Tmp1 = ExpandIntLibCall(Node, true,
2948 RTLIB::SREM_I16, RTLIB::SREM_I32,
2949 RTLIB::SREM_I64, RTLIB::SREM_I128);
2951 Tmp1 = ExpandIntLibCall(Node, false,
2953 RTLIB::UREM_I16, RTLIB::UREM_I32,
2954 RTLIB::UREM_I64, RTLIB::UREM_I128);
2956 Results.push_back(Tmp1);
2961 bool isSigned = Node->getOpcode() == ISD::SDIV;
2962 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2963 EVT VT = Node->getValueType(0);
2964 SDVTList VTs = DAG.getVTList(VT, VT);
2965 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT))
2966 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
2967 Node->getOperand(1));
2969 Tmp1 = ExpandIntLibCall(Node, true,
2971 RTLIB::SDIV_I16, RTLIB::SDIV_I32,
2972 RTLIB::SDIV_I64, RTLIB::SDIV_I128);
2974 Tmp1 = ExpandIntLibCall(Node, false,
2976 RTLIB::UDIV_I16, RTLIB::UDIV_I32,
2977 RTLIB::UDIV_I64, RTLIB::UDIV_I128);
2978 Results.push_back(Tmp1);
2983 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
2985 EVT VT = Node->getValueType(0);
2986 SDVTList VTs = DAG.getVTList(VT, VT);
2987 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
2988 "If this wasn't legal, it shouldn't have been created!");
2989 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
2990 Node->getOperand(1));
2991 Results.push_back(Tmp1.getValue(1));
2995 EVT VT = Node->getValueType(0);
2996 SDVTList VTs = DAG.getVTList(VT, VT);
2997 // See if multiply or divide can be lowered using two-result operations.
2998 // We just need the low half of the multiply; try both the signed
2999 // and unsigned forms. If the target supports both SMUL_LOHI and
3000 // UMUL_LOHI, form a preference by checking which forms of plain
3001 // MULH it supports.
3002 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3003 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3004 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3005 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3006 unsigned OpToUse = 0;
3007 if (HasSMUL_LOHI && !HasMULHS) {
3008 OpToUse = ISD::SMUL_LOHI;
3009 } else if (HasUMUL_LOHI && !HasMULHU) {
3010 OpToUse = ISD::UMUL_LOHI;
3011 } else if (HasSMUL_LOHI) {
3012 OpToUse = ISD::SMUL_LOHI;
3013 } else if (HasUMUL_LOHI) {
3014 OpToUse = ISD::UMUL_LOHI;
3017 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
3018 Node->getOperand(1)));
3021 Tmp1 = ExpandIntLibCall(Node, false,
3023 RTLIB::MUL_I16, RTLIB::MUL_I32,
3024 RTLIB::MUL_I64, RTLIB::MUL_I128);
3025 Results.push_back(Tmp1);
3030 SDValue LHS = Node->getOperand(0);
3031 SDValue RHS = Node->getOperand(1);
3032 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3033 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3035 Results.push_back(Sum);
3036 EVT OType = Node->getValueType(1);
3038 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
3040 // LHSSign -> LHS >= 0
3041 // RHSSign -> RHS >= 0
3042 // SumSign -> Sum >= 0
3045 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3047 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3049 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3050 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3051 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
3052 Node->getOpcode() == ISD::SADDO ?
3053 ISD::SETEQ : ISD::SETNE);
3055 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3056 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3058 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3059 Results.push_back(Cmp);
3064 SDValue LHS = Node->getOperand(0);
3065 SDValue RHS = Node->getOperand(1);
3066 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
3067 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3069 Results.push_back(Sum);
3070 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS,
3071 Node->getOpcode () == ISD::UADDO ?
3072 ISD::SETULT : ISD::SETUGT));
3077 EVT VT = Node->getValueType(0);
3078 SDValue LHS = Node->getOperand(0);
3079 SDValue RHS = Node->getOperand(1);
3082 static const unsigned Ops[2][3] =
3083 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
3084 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
3085 bool isSigned = Node->getOpcode() == ISD::SMULO;
3086 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3087 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3088 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3089 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3090 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3092 TopHalf = BottomHalf.getValue(1);
3094 // FIXME: We should be able to fall back to a libcall with an illegal
3095 // type in some cases.
3096 // Also, we can fall back to a division in some cases, but that's a big
3097 // performance hit in the general case.
3098 assert(TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(),
3099 VT.getSizeInBits() * 2)) &&
3100 "Don't know how to expand this operation yet!");
3101 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
3102 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
3103 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
3104 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
3105 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3106 DAG.getIntPtrConstant(0));
3107 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3108 DAG.getIntPtrConstant(1));
3111 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1, TLI.getShiftAmountTy());
3112 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3113 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1,
3116 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf,
3117 DAG.getConstant(0, VT), ISD::SETNE);
3119 Results.push_back(BottomHalf);
3120 Results.push_back(TopHalf);
3123 case ISD::BUILD_PAIR: {
3124 EVT PairTy = Node->getValueType(0);
3125 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3126 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3127 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
3128 DAG.getConstant(PairTy.getSizeInBits()/2,
3129 TLI.getShiftAmountTy()));
3130 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3134 Tmp1 = Node->getOperand(0);
3135 Tmp2 = Node->getOperand(1);
3136 Tmp3 = Node->getOperand(2);
3137 if (Tmp1.getOpcode() == ISD::SETCC) {
3138 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3140 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3142 Tmp1 = DAG.getSelectCC(dl, Tmp1,
3143 DAG.getConstant(0, Tmp1.getValueType()),
3144 Tmp2, Tmp3, ISD::SETNE);
3146 Results.push_back(Tmp1);
3149 SDValue Chain = Node->getOperand(0);
3150 SDValue Table = Node->getOperand(1);
3151 SDValue Index = Node->getOperand(2);
3153 EVT PTy = TLI.getPointerTy();
3155 const TargetData &TD = *TLI.getTargetData();
3156 unsigned EntrySize =
3157 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
3159 Index = DAG.getNode(ISD::MUL, dl, PTy,
3160 Index, DAG.getConstant(EntrySize, PTy));
3161 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
3163 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
3164 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, PTy, dl, Chain, Addr,
3165 PseudoSourceValue::getJumpTable(), 0, MemVT,
3168 if (TM.getRelocationModel() == Reloc::PIC_) {
3169 // For PIC, the sequence is:
3170 // BRIND(load(Jumptable + index) + RelocBase)
3171 // RelocBase can be JumpTable, GOT or some sort of global base.
3172 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3173 TLI.getPICJumpTableRelocBase(Table, DAG));
3175 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
3176 Results.push_back(Tmp1);
3180 // Expand brcond's setcc into its constituent parts and create a BR_CC
3182 Tmp1 = Node->getOperand(0);
3183 Tmp2 = Node->getOperand(1);
3184 if (Tmp2.getOpcode() == ISD::SETCC) {
3185 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3186 Tmp1, Tmp2.getOperand(2),
3187 Tmp2.getOperand(0), Tmp2.getOperand(1),
3188 Node->getOperand(2));
3190 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3191 DAG.getCondCode(ISD::SETNE), Tmp2,
3192 DAG.getConstant(0, Tmp2.getValueType()),
3193 Node->getOperand(2));
3195 Results.push_back(Tmp1);
3198 Tmp1 = Node->getOperand(0);
3199 Tmp2 = Node->getOperand(1);
3200 Tmp3 = Node->getOperand(2);
3201 LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl);
3203 // If we expanded the SETCC into an AND/OR, return the new node
3204 if (Tmp2.getNode() == 0) {
3205 Results.push_back(Tmp1);
3209 // Otherwise, SETCC for the given comparison type must be completely
3210 // illegal; expand it into a SELECT_CC.
3211 EVT VT = Node->getValueType(0);
3212 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3213 DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3);
3214 Results.push_back(Tmp1);
3217 case ISD::SELECT_CC: {
3218 Tmp1 = Node->getOperand(0); // LHS
3219 Tmp2 = Node->getOperand(1); // RHS
3220 Tmp3 = Node->getOperand(2); // True
3221 Tmp4 = Node->getOperand(3); // False
3222 SDValue CC = Node->getOperand(4);
3224 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()),
3225 Tmp1, Tmp2, CC, dl);
3227 assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!");
3228 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3229 CC = DAG.getCondCode(ISD::SETNE);
3230 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2,
3232 Results.push_back(Tmp1);
3236 Tmp1 = Node->getOperand(0); // Chain
3237 Tmp2 = Node->getOperand(2); // LHS
3238 Tmp3 = Node->getOperand(3); // RHS
3239 Tmp4 = Node->getOperand(1); // CC
3241 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()),
3242 Tmp2, Tmp3, Tmp4, dl);
3243 LastCALLSEQ_END = DAG.getEntryNode();
3245 assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!");
3246 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
3247 Tmp4 = DAG.getCondCode(ISD::SETNE);
3248 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2,
3249 Tmp3, Node->getOperand(4));
3250 Results.push_back(Tmp1);
3253 case ISD::GLOBAL_OFFSET_TABLE:
3254 case ISD::GlobalAddress:
3255 case ISD::GlobalTLSAddress:
3256 case ISD::ExternalSymbol:
3257 case ISD::ConstantPool:
3258 case ISD::JumpTable:
3259 case ISD::INTRINSIC_W_CHAIN:
3260 case ISD::INTRINSIC_WO_CHAIN:
3261 case ISD::INTRINSIC_VOID:
3262 // FIXME: Custom lowering for these operations shouldn't return null!
3263 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
3264 Results.push_back(SDValue(Node, i));
3268 void SelectionDAGLegalize::PromoteNode(SDNode *Node,
3269 SmallVectorImpl<SDValue> &Results) {
3270 EVT OVT = Node->getValueType(0);
3271 if (Node->getOpcode() == ISD::UINT_TO_FP ||
3272 Node->getOpcode() == ISD::SINT_TO_FP ||
3273 Node->getOpcode() == ISD::SETCC) {
3274 OVT = Node->getOperand(0).getValueType();
3276 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3277 DebugLoc dl = Node->getDebugLoc();
3278 SDValue Tmp1, Tmp2, Tmp3;
3279 switch (Node->getOpcode()) {
3283 // Zero extend the argument.
3284 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3285 // Perform the larger operation.
3286 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
3287 if (Node->getOpcode() == ISD::CTTZ) {
3288 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3289 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
3290 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
3292 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
3293 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3294 } else if (Node->getOpcode() == ISD::CTLZ) {
3295 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3296 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
3297 DAG.getConstant(NVT.getSizeInBits() -
3298 OVT.getSizeInBits(), NVT));
3300 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
3303 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3304 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3305 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
3306 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
3307 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3308 Results.push_back(Tmp1);
3311 case ISD::FP_TO_UINT:
3312 case ISD::FP_TO_SINT:
3313 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
3314 Node->getOpcode() == ISD::FP_TO_SINT, dl);
3315 Results.push_back(Tmp1);
3317 case ISD::UINT_TO_FP:
3318 case ISD::SINT_TO_FP:
3319 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
3320 Node->getOpcode() == ISD::SINT_TO_FP, dl);
3321 Results.push_back(Tmp1);
3326 unsigned ExtOp, TruncOp;
3327 if (OVT.isVector()) {
3328 ExtOp = ISD::BIT_CONVERT;
3329 TruncOp = ISD::BIT_CONVERT;
3331 assert(OVT.isInteger() && "Cannot promote logic operation");
3332 ExtOp = ISD::ANY_EXTEND;
3333 TruncOp = ISD::TRUNCATE;
3335 // Promote each of the values to the new type.
3336 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3337 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3338 // Perform the larger operation, then convert back
3339 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3340 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
3344 unsigned ExtOp, TruncOp;
3345 if (Node->getValueType(0).isVector()) {
3346 ExtOp = ISD::BIT_CONVERT;
3347 TruncOp = ISD::BIT_CONVERT;
3348 } else if (Node->getValueType(0).isInteger()) {
3349 ExtOp = ISD::ANY_EXTEND;
3350 TruncOp = ISD::TRUNCATE;
3352 ExtOp = ISD::FP_EXTEND;
3353 TruncOp = ISD::FP_ROUND;
3355 Tmp1 = Node->getOperand(0);
3356 // Promote each of the values to the new type.
3357 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3358 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
3359 // Perform the larger operation, then round down.
3360 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3);
3361 if (TruncOp != ISD::FP_ROUND)
3362 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
3364 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
3365 DAG.getIntPtrConstant(0));
3366 Results.push_back(Tmp1);
3369 case ISD::VECTOR_SHUFFLE: {
3370 SmallVector<int, 8> Mask;
3371 cast<ShuffleVectorSDNode>(Node)->getMask(Mask);
3373 // Cast the two input vectors.
3374 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
3375 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(1));
3377 // Convert the shuffle mask to the right # elements.
3378 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
3379 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Tmp1);
3380 Results.push_back(Tmp1);
3384 unsigned ExtOp = ISD::FP_EXTEND;
3385 if (NVT.isInteger()) {
3386 ISD::CondCode CCCode =
3387 cast<CondCodeSDNode>(Node->getOperand(2))->get();
3388 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3390 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3391 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3392 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3393 Tmp1, Tmp2, Node->getOperand(2)));
3399 // SelectionDAG::Legalize - This is the entry point for the file.
3401 void SelectionDAG::Legalize(CodeGenOpt::Level OptLevel) {
3402 /// run - This is the main entry point to this class.
3404 SelectionDAGLegalize(*this, OptLevel).LegalizeDAG();