1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/Target/TargetLowering.h"
19 #include "llvm/Target/TargetData.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetOptions.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Support/MathExtras.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/Compiler.h"
28 #include "llvm/ADT/DenseMap.h"
29 #include "llvm/ADT/SmallVector.h"
30 #include "llvm/ADT/SmallPtrSet.h"
36 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
37 cl::desc("Pop up a window to show dags before legalize"));
39 static const bool ViewLegalizeDAGs = 0;
44 struct DenseMapKeyInfo<SDOperand> {
45 static inline SDOperand getEmptyKey() { return SDOperand((SDNode*)-1, -1U); }
46 static inline SDOperand getTombstoneKey() { return SDOperand((SDNode*)-1, 0);}
47 static unsigned getHashValue(const SDOperand &Val) {
48 return DenseMapKeyInfo<void*>::getHashValue(Val.Val) + Val.ResNo;
50 static bool isPod() { return true; }
54 //===----------------------------------------------------------------------===//
55 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
56 /// hacks on it until the target machine can handle it. This involves
57 /// eliminating value sizes the machine cannot handle (promoting small sizes to
58 /// large sizes or splitting up large values into small values) as well as
59 /// eliminating operations the machine cannot handle.
61 /// This code also does a small amount of optimization and recognition of idioms
62 /// as part of its processing. For example, if a target does not support a
63 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
64 /// will attempt merge setcc and brc instructions into brcc's.
67 class VISIBILITY_HIDDEN SelectionDAGLegalize {
71 // Libcall insertion helpers.
73 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
74 /// legalized. We use this to ensure that calls are properly serialized
75 /// against each other, including inserted libcalls.
76 SDOperand LastCALLSEQ_END;
78 /// IsLegalizingCall - This member is used *only* for purposes of providing
79 /// helpful assertions that a libcall isn't created while another call is
80 /// being legalized (which could lead to non-serialized call sequences).
81 bool IsLegalizingCall;
84 Legal, // The target natively supports this operation.
85 Promote, // This operation should be executed in a larger type.
86 Expand // Try to expand this to other ops, otherwise use a libcall.
89 /// ValueTypeActions - This is a bitvector that contains two bits for each
90 /// value type, where the two bits correspond to the LegalizeAction enum.
91 /// This can be queried with "getTypeAction(VT)".
92 TargetLowering::ValueTypeActionImpl ValueTypeActions;
94 /// LegalizedNodes - For nodes that are of legal width, and that have more
95 /// than one use, this map indicates what regularized operand to use. This
96 /// allows us to avoid legalizing the same thing more than once.
97 DenseMap<SDOperand, SDOperand> LegalizedNodes;
99 /// PromotedNodes - For nodes that are below legal width, and that have more
100 /// than one use, this map indicates what promoted value to use. This allows
101 /// us to avoid promoting the same thing more than once.
102 DenseMap<SDOperand, SDOperand> PromotedNodes;
104 /// ExpandedNodes - For nodes that need to be expanded this map indicates
105 /// which which operands are the expanded version of the input. This allows
106 /// us to avoid expanding the same node more than once.
107 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
109 /// SplitNodes - For vector nodes that need to be split, this map indicates
110 /// which which operands are the split version of the input. This allows us
111 /// to avoid splitting the same node more than once.
112 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
114 /// PackedNodes - For nodes that need to be packed from MVT::Vector types to
115 /// concrete vector types, this contains the mapping of ones we have already
116 /// processed to the result.
117 std::map<SDOperand, SDOperand> PackedNodes;
119 void AddLegalizedOperand(SDOperand From, SDOperand To) {
120 LegalizedNodes.insert(std::make_pair(From, To));
121 // If someone requests legalization of the new node, return itself.
123 LegalizedNodes.insert(std::make_pair(To, To));
125 void AddPromotedOperand(SDOperand From, SDOperand To) {
126 bool isNew = PromotedNodes.insert(std::make_pair(From, To));
127 assert(isNew && "Got into the map somehow?");
128 // If someone requests legalization of the new node, return itself.
129 LegalizedNodes.insert(std::make_pair(To, To));
134 SelectionDAGLegalize(SelectionDAG &DAG);
136 /// getTypeAction - Return how we should legalize values of this type, either
137 /// it is already legal or we need to expand it into multiple registers of
138 /// smaller integer type, or we need to promote it to a larger type.
139 LegalizeAction getTypeAction(MVT::ValueType VT) const {
140 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
143 /// isTypeLegal - Return true if this type is legal on this target.
145 bool isTypeLegal(MVT::ValueType VT) const {
146 return getTypeAction(VT) == Legal;
152 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as
153 /// appropriate for its type.
154 void HandleOp(SDOperand Op);
156 /// LegalizeOp - We know that the specified value has a legal type.
157 /// Recursively ensure that the operands have legal types, then return the
159 SDOperand LegalizeOp(SDOperand O);
161 /// PromoteOp - Given an operation that produces a value in an invalid type,
162 /// promote it to compute the value into a larger type. The produced value
163 /// will have the correct bits for the low portion of the register, but no
164 /// guarantee is made about the top bits: it may be zero, sign-extended, or
166 SDOperand PromoteOp(SDOperand O);
168 /// ExpandOp - Expand the specified SDOperand into its two component pieces
169 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
170 /// the LegalizeNodes map is filled in for any results that are not expanded,
171 /// the ExpandedNodes map is filled in for any results that are expanded, and
172 /// the Lo/Hi values are returned. This applies to integer types and Vector
174 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
176 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into
177 /// two smaller values of MVT::Vector type.
178 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
180 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the
181 /// equivalent operation that returns a packed value (e.g. MVT::V4F32). When
182 /// this is called, we know that PackedVT is the right type for the result and
183 /// we know that this type is legal for the target.
184 SDOperand PackVectorOp(SDOperand O, MVT::ValueType PackedVT);
186 /// isShuffleLegal - Return true if a vector shuffle is legal with the
187 /// specified mask and type. Targets can specify exactly which masks they
188 /// support and the code generator is tasked with not creating illegal masks.
190 /// Note that this will also return true for shuffles that are promoted to a
193 /// If this is a legal shuffle, this method returns the (possibly promoted)
194 /// build_vector Mask. If it's not a legal shuffle, it returns null.
195 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
197 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
198 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
200 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
202 SDOperand CreateStackTemporary(MVT::ValueType VT);
204 SDOperand ExpandLibCall(const char *Name, SDNode *Node, bool isSigned,
206 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
209 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp);
210 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
211 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
212 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
214 MVT::ValueType DestVT);
215 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
217 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
220 SDOperand ExpandBSWAP(SDOperand Op);
221 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
222 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
223 SDOperand &Lo, SDOperand &Hi);
224 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
225 SDOperand &Lo, SDOperand &Hi);
227 SDOperand LowerVEXTRACT_VECTOR_ELT(SDOperand Op);
228 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
230 SDOperand getIntPtrConstant(uint64_t Val) {
231 return DAG.getConstant(Val, TLI.getPointerTy());
236 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
237 /// specified mask and type. Targets can specify exactly which masks they
238 /// support and the code generator is tasked with not creating illegal masks.
240 /// Note that this will also return true for shuffles that are promoted to a
242 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
243 SDOperand Mask) const {
244 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
246 case TargetLowering::Legal:
247 case TargetLowering::Custom:
249 case TargetLowering::Promote: {
250 // If this is promoted to a different type, convert the shuffle mask and
251 // ask if it is legal in the promoted type!
252 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
254 // If we changed # elements, change the shuffle mask.
255 unsigned NumEltsGrowth =
256 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
257 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
258 if (NumEltsGrowth > 1) {
259 // Renumber the elements.
260 SmallVector<SDOperand, 8> Ops;
261 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
262 SDOperand InOp = Mask.getOperand(i);
263 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
264 if (InOp.getOpcode() == ISD::UNDEF)
265 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
267 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
268 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
272 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
278 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
281 /// getScalarizedOpcode - Return the scalar opcode that corresponds to the
282 /// specified vector opcode.
283 static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) {
285 default: assert(0 && "Don't know how to scalarize this opcode!");
286 case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD;
287 case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB;
288 case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL;
289 case ISD::VSDIV: return MVT::isInteger(VT) ? ISD::SDIV: ISD::FDIV;
290 case ISD::VUDIV: return MVT::isInteger(VT) ? ISD::UDIV: ISD::FDIV;
291 case ISD::VAND: return MVT::isInteger(VT) ? ISD::AND : 0;
292 case ISD::VOR: return MVT::isInteger(VT) ? ISD::OR : 0;
293 case ISD::VXOR: return MVT::isInteger(VT) ? ISD::XOR : 0;
297 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
298 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
299 ValueTypeActions(TLI.getValueTypeActions()) {
300 assert(MVT::LAST_VALUETYPE <= 32 &&
301 "Too many value types for ValueTypeActions to hold!");
304 /// ComputeTopDownOrdering - Add the specified node to the Order list if it has
305 /// not been visited yet and if all of its operands have already been visited.
306 static void ComputeTopDownOrdering(SDNode *N, SmallVector<SDNode*, 64> &Order,
307 DenseMap<SDNode*, unsigned> &Visited) {
308 if (++Visited[N] != N->getNumOperands())
309 return; // Haven't visited all operands yet
313 if (N->hasOneUse()) { // Tail recurse in common case.
314 ComputeTopDownOrdering(*N->use_begin(), Order, Visited);
318 // Now that we have N in, add anything that uses it if all of their operands
320 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI)
321 ComputeTopDownOrdering(*UI, Order, Visited);
325 void SelectionDAGLegalize::LegalizeDAG() {
326 LastCALLSEQ_END = DAG.getEntryNode();
327 IsLegalizingCall = false;
329 // The legalize process is inherently a bottom-up recursive process (users
330 // legalize their uses before themselves). Given infinite stack space, we
331 // could just start legalizing on the root and traverse the whole graph. In
332 // practice however, this causes us to run out of stack space on large basic
333 // blocks. To avoid this problem, compute an ordering of the nodes where each
334 // node is only legalized after all of its operands are legalized.
335 DenseMap<SDNode*, unsigned> Visited;
336 SmallVector<SDNode*, 64> Order;
338 // Compute ordering from all of the leaves in the graphs, those (like the
339 // entry node) that have no operands.
340 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
341 E = DAG.allnodes_end(); I != E; ++I) {
342 if (I->getNumOperands() == 0) {
344 ComputeTopDownOrdering(I, Order, Visited);
348 assert(Order.size() == Visited.size() &&
350 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
351 "Error: DAG is cyclic!");
354 for (unsigned i = 0, e = Order.size(); i != e; ++i)
355 HandleOp(SDOperand(Order[i], 0));
357 // Finally, it's possible the root changed. Get the new root.
358 SDOperand OldRoot = DAG.getRoot();
359 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
360 DAG.setRoot(LegalizedNodes[OldRoot]);
362 ExpandedNodes.clear();
363 LegalizedNodes.clear();
364 PromotedNodes.clear();
368 // Remove dead nodes now.
369 DAG.RemoveDeadNodes();
373 /// FindCallEndFromCallStart - Given a chained node that is part of a call
374 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
375 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
376 if (Node->getOpcode() == ISD::CALLSEQ_END)
378 if (Node->use_empty())
379 return 0; // No CallSeqEnd
381 // The chain is usually at the end.
382 SDOperand TheChain(Node, Node->getNumValues()-1);
383 if (TheChain.getValueType() != MVT::Other) {
384 // Sometimes it's at the beginning.
385 TheChain = SDOperand(Node, 0);
386 if (TheChain.getValueType() != MVT::Other) {
387 // Otherwise, hunt for it.
388 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
389 if (Node->getValueType(i) == MVT::Other) {
390 TheChain = SDOperand(Node, i);
394 // Otherwise, we walked into a node without a chain.
395 if (TheChain.getValueType() != MVT::Other)
400 for (SDNode::use_iterator UI = Node->use_begin(),
401 E = Node->use_end(); UI != E; ++UI) {
403 // Make sure to only follow users of our token chain.
405 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
406 if (User->getOperand(i) == TheChain)
407 if (SDNode *Result = FindCallEndFromCallStart(User))
413 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
414 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
415 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
416 assert(Node && "Didn't find callseq_start for a call??");
417 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
419 assert(Node->getOperand(0).getValueType() == MVT::Other &&
420 "Node doesn't have a token chain argument!");
421 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
424 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
425 /// see if any uses can reach Dest. If no dest operands can get to dest,
426 /// legalize them, legalize ourself, and return false, otherwise, return true.
428 /// Keep track of the nodes we fine that actually do lead to Dest in
429 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
431 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
432 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
433 if (N == Dest) return true; // N certainly leads to Dest :)
435 // If we've already processed this node and it does lead to Dest, there is no
436 // need to reprocess it.
437 if (NodesLeadingTo.count(N)) return true;
439 // If the first result of this node has been already legalized, then it cannot
441 switch (getTypeAction(N->getValueType(0))) {
443 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
446 if (PromotedNodes.count(SDOperand(N, 0))) return false;
449 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
453 // Okay, this node has not already been legalized. Check and legalize all
454 // operands. If none lead to Dest, then we can legalize this node.
455 bool OperandsLeadToDest = false;
456 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
457 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
458 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
460 if (OperandsLeadToDest) {
461 NodesLeadingTo.insert(N);
465 // Okay, this node looks safe, legalize it and return false.
466 HandleOp(SDOperand(N, 0));
470 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as
471 /// appropriate for its type.
472 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
473 switch (getTypeAction(Op.getValueType())) {
474 default: assert(0 && "Bad type action!");
475 case Legal: LegalizeOp(Op); break;
476 case Promote: PromoteOp(Op); break;
478 if (Op.getValueType() != MVT::Vector) {
483 unsigned NumOps = N->getNumOperands();
484 unsigned NumElements =
485 cast<ConstantSDNode>(N->getOperand(NumOps-2))->getValue();
486 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(NumOps-1))->getVT();
487 MVT::ValueType PackedVT = MVT::getVectorType(EVT, NumElements);
488 if (PackedVT != MVT::Other && TLI.isTypeLegal(PackedVT)) {
489 // In the common case, this is a legal vector type, convert it to the
490 // packed operation and type now.
491 PackVectorOp(Op, PackedVT);
492 } else if (NumElements == 1) {
493 // Otherwise, if this is a single element vector, convert it to a
495 PackVectorOp(Op, EVT);
497 // Otherwise, this is a multiple element vector that isn't supported.
498 // Split it in half and legalize both parts.
500 SplitVectorOp(Op, X, Y);
507 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
508 /// a load from the constant pool.
509 static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
510 SelectionDAG &DAG, TargetLowering &TLI) {
513 // If a FP immediate is precise when represented as a float and if the
514 // target can do an extending load from float to double, we put it into
515 // the constant pool as a float, even if it's is statically typed as a
517 MVT::ValueType VT = CFP->getValueType(0);
518 bool isDouble = VT == MVT::f64;
519 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy :
520 Type::FloatTy, CFP->getValue());
522 double Val = LLVMC->getValue();
524 ? DAG.getConstant(DoubleToBits(Val), MVT::i64)
525 : DAG.getConstant(FloatToBits(Val), MVT::i32);
528 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) &&
529 // Only do this if the target has a native EXTLOAD instruction from f32.
530 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) {
531 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC,Type::FloatTy));
536 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
538 return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
539 CPIdx, NULL, 0, MVT::f32);
541 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
546 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
549 SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT,
550 SelectionDAG &DAG, TargetLowering &TLI) {
551 MVT::ValueType VT = Node->getValueType(0);
552 MVT::ValueType SrcVT = Node->getOperand(1).getValueType();
553 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
555 // First get the sign bit of second operand.
556 SDOperand Mask1 = (SrcVT == MVT::f64)
557 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
558 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
559 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
560 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
561 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
562 // Shift right or sign-extend it if the two operands have different types.
563 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT);
565 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
566 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
567 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
568 } else if (SizeDiff < 0)
569 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit);
571 // Clear the sign bit of first operand.
572 SDOperand Mask2 = (VT == MVT::f64)
573 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
574 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
575 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
576 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
577 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
579 // Or the value with the sign bit.
580 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
585 /// LegalizeOp - We know that the specified value has a legal type.
586 /// Recursively ensure that the operands have legal types, then return the
588 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
589 assert(isTypeLegal(Op.getValueType()) &&
590 "Caller should expand or promote operands that are not legal!");
591 SDNode *Node = Op.Val;
593 // If this operation defines any values that cannot be represented in a
594 // register on this target, make sure to expand or promote them.
595 if (Node->getNumValues() > 1) {
596 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
597 if (getTypeAction(Node->getValueType(i)) != Legal) {
598 HandleOp(Op.getValue(i));
599 assert(LegalizedNodes.count(Op) &&
600 "Handling didn't add legal operands!");
601 return LegalizedNodes[Op];
605 // Note that LegalizeOp may be reentered even from single-use nodes, which
606 // means that we always must cache transformed nodes.
607 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
608 if (I != LegalizedNodes.end()) return I->second;
610 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
611 SDOperand Result = Op;
612 bool isCustom = false;
614 switch (Node->getOpcode()) {
615 case ISD::FrameIndex:
616 case ISD::EntryToken:
618 case ISD::BasicBlock:
619 case ISD::TargetFrameIndex:
620 case ISD::TargetJumpTable:
621 case ISD::TargetConstant:
622 case ISD::TargetConstantFP:
623 case ISD::TargetConstantPool:
624 case ISD::TargetGlobalAddress:
625 case ISD::TargetExternalSymbol:
630 case ISD::GLOBAL_OFFSET_TABLE:
631 // Primitives must all be legal.
632 assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) &&
633 "This must be legal!");
636 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
637 // If this is a target node, legalize it by legalizing the operands then
638 // passing it through.
639 SmallVector<SDOperand, 8> Ops;
640 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
641 Ops.push_back(LegalizeOp(Node->getOperand(i)));
643 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
645 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
646 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
647 return Result.getValue(Op.ResNo);
649 // Otherwise this is an unhandled builtin node. splat.
651 cerr << "NODE: "; Node->dump(); cerr << "\n";
653 assert(0 && "Do not know how to legalize this operator!");
655 case ISD::GlobalAddress:
656 case ISD::ExternalSymbol:
657 case ISD::ConstantPool:
658 case ISD::JumpTable: // Nothing to do.
659 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
660 default: assert(0 && "This action is not supported yet!");
661 case TargetLowering::Custom:
662 Tmp1 = TLI.LowerOperation(Op, DAG);
663 if (Tmp1.Val) Result = Tmp1;
664 // FALLTHROUGH if the target doesn't want to lower this op after all.
665 case TargetLowering::Legal:
670 case ISD::RETURNADDR:
671 // The only option for these nodes is to custom lower them. If the target
672 // does not custom lower them, then return zero.
673 Tmp1 = TLI.LowerOperation(Op, DAG);
677 Result = DAG.getConstant(0, TLI.getPointerTy());
679 case ISD::EXCEPTIONADDR: {
680 Tmp1 = LegalizeOp(Node->getOperand(0));
681 MVT::ValueType VT = Node->getValueType(0);
682 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
683 default: assert(0 && "This action is not supported yet!");
684 case TargetLowering::Expand: {
685 unsigned Reg = TLI.getExceptionAddressRegister();
686 Result = DAG.getCopyFromReg(Tmp1, Reg, VT).getValue(Op.ResNo);
689 case TargetLowering::Custom:
690 Result = TLI.LowerOperation(Op, DAG);
691 if (Result.Val) break;
693 case TargetLowering::Legal:
694 Result = DAG.getNode(ISD::MERGE_VALUES, VT, DAG.getConstant(0, VT), Tmp1).
700 case ISD::EHSELECTION: {
701 Tmp1 = LegalizeOp(Node->getOperand(0));
702 Tmp2 = LegalizeOp(Node->getOperand(1));
703 MVT::ValueType VT = Node->getValueType(0);
704 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
705 default: assert(0 && "This action is not supported yet!");
706 case TargetLowering::Expand: {
707 unsigned Reg = TLI.getExceptionSelectorRegister();
708 Result = DAG.getCopyFromReg(Tmp2, Reg, VT).getValue(Op.ResNo);
711 case TargetLowering::Custom:
712 Result = TLI.LowerOperation(Op, DAG);
713 if (Result.Val) break;
715 case TargetLowering::Legal:
716 Result = DAG.getNode(ISD::MERGE_VALUES, VT, DAG.getConstant(0, VT), Tmp2).
722 case ISD::AssertSext:
723 case ISD::AssertZext:
724 Tmp1 = LegalizeOp(Node->getOperand(0));
725 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
727 case ISD::MERGE_VALUES:
728 // Legalize eliminates MERGE_VALUES nodes.
729 Result = Node->getOperand(Op.ResNo);
731 case ISD::CopyFromReg:
732 Tmp1 = LegalizeOp(Node->getOperand(0));
733 Result = Op.getValue(0);
734 if (Node->getNumValues() == 2) {
735 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
737 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
738 if (Node->getNumOperands() == 3) {
739 Tmp2 = LegalizeOp(Node->getOperand(2));
740 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
742 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
744 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
746 // Since CopyFromReg produces two values, make sure to remember that we
747 // legalized both of them.
748 AddLegalizedOperand(Op.getValue(0), Result);
749 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
750 return Result.getValue(Op.ResNo);
752 MVT::ValueType VT = Op.getValueType();
753 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
754 default: assert(0 && "This action is not supported yet!");
755 case TargetLowering::Expand:
756 if (MVT::isInteger(VT))
757 Result = DAG.getConstant(0, VT);
758 else if (MVT::isFloatingPoint(VT))
759 Result = DAG.getConstantFP(0, VT);
761 assert(0 && "Unknown value type!");
763 case TargetLowering::Legal:
769 case ISD::INTRINSIC_W_CHAIN:
770 case ISD::INTRINSIC_WO_CHAIN:
771 case ISD::INTRINSIC_VOID: {
772 SmallVector<SDOperand, 8> Ops;
773 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
774 Ops.push_back(LegalizeOp(Node->getOperand(i)));
775 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
777 // Allow the target to custom lower its intrinsics if it wants to.
778 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
779 TargetLowering::Custom) {
780 Tmp3 = TLI.LowerOperation(Result, DAG);
781 if (Tmp3.Val) Result = Tmp3;
784 if (Result.Val->getNumValues() == 1) break;
786 // Must have return value and chain result.
787 assert(Result.Val->getNumValues() == 2 &&
788 "Cannot return more than two values!");
790 // Since loads produce two values, make sure to remember that we
791 // legalized both of them.
792 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
793 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
794 return Result.getValue(Op.ResNo);
798 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
799 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
801 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
802 case TargetLowering::Promote:
803 default: assert(0 && "This action is not supported yet!");
804 case TargetLowering::Expand: {
805 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
806 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
807 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other);
809 if (MMI && (useDEBUG_LOC || useLABEL)) {
810 const std::string &FName =
811 cast<StringSDNode>(Node->getOperand(3))->getValue();
812 const std::string &DirName =
813 cast<StringSDNode>(Node->getOperand(4))->getValue();
814 unsigned SrcFile = MMI->RecordSource(DirName, FName);
816 SmallVector<SDOperand, 8> Ops;
817 Ops.push_back(Tmp1); // chain
818 SDOperand LineOp = Node->getOperand(1);
819 SDOperand ColOp = Node->getOperand(2);
822 Ops.push_back(LineOp); // line #
823 Ops.push_back(ColOp); // col #
824 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
825 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
827 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
828 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
829 unsigned ID = MMI->RecordLabel(Line, Col, SrcFile);
830 Ops.push_back(DAG.getConstant(ID, MVT::i32));
831 Result = DAG.getNode(ISD::LABEL, MVT::Other,&Ops[0],Ops.size());
834 Result = Tmp1; // chain
838 case TargetLowering::Legal:
839 if (Tmp1 != Node->getOperand(0) ||
840 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
841 SmallVector<SDOperand, 8> Ops;
843 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
844 Ops.push_back(Node->getOperand(1)); // line # must be legal.
845 Ops.push_back(Node->getOperand(2)); // col # must be legal.
847 // Otherwise promote them.
848 Ops.push_back(PromoteOp(Node->getOperand(1)));
849 Ops.push_back(PromoteOp(Node->getOperand(2)));
851 Ops.push_back(Node->getOperand(3)); // filename must be legal.
852 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
853 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
860 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
861 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
862 default: assert(0 && "This action is not supported yet!");
863 case TargetLowering::Legal:
864 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
865 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
866 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
867 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
868 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
874 assert(Node->getNumOperands() == 2 && "Invalid LABEL node!");
875 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) {
876 default: assert(0 && "This action is not supported yet!");
877 case TargetLowering::Legal:
878 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
879 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
880 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
882 case TargetLowering::Expand:
883 Result = LegalizeOp(Node->getOperand(0));
889 // We know we don't need to expand constants here, constants only have one
890 // value and we check that it is fine above.
892 // FIXME: Maybe we should handle things like targets that don't support full
893 // 32-bit immediates?
895 case ISD::ConstantFP: {
896 // Spill FP immediates to the constant pool if the target cannot directly
897 // codegen them. Targets often have some immediate values that can be
898 // efficiently generated into an FP register without a load. We explicitly
899 // leave these constants as ConstantFP nodes for the target to deal with.
900 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
902 // Check to see if this FP immediate is already legal.
903 bool isLegal = false;
904 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
905 E = TLI.legal_fpimm_end(); I != E; ++I)
906 if (CFP->isExactlyValue(*I)) {
911 // If this is a legal constant, turn it into a TargetConstantFP node.
913 Result = DAG.getTargetConstantFP(CFP->getValue(), CFP->getValueType(0));
917 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
918 default: assert(0 && "This action is not supported yet!");
919 case TargetLowering::Custom:
920 Tmp3 = TLI.LowerOperation(Result, DAG);
926 case TargetLowering::Expand:
927 Result = ExpandConstantFP(CFP, true, DAG, TLI);
931 case ISD::TokenFactor:
932 if (Node->getNumOperands() == 2) {
933 Tmp1 = LegalizeOp(Node->getOperand(0));
934 Tmp2 = LegalizeOp(Node->getOperand(1));
935 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
936 } else if (Node->getNumOperands() == 3) {
937 Tmp1 = LegalizeOp(Node->getOperand(0));
938 Tmp2 = LegalizeOp(Node->getOperand(1));
939 Tmp3 = LegalizeOp(Node->getOperand(2));
940 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
942 SmallVector<SDOperand, 8> Ops;
943 // Legalize the operands.
944 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
945 Ops.push_back(LegalizeOp(Node->getOperand(i)));
946 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
950 case ISD::FORMAL_ARGUMENTS:
952 // The only option for this is to custom lower it.
953 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
954 assert(Tmp3.Val && "Target didn't custom lower this node!");
955 assert(Tmp3.Val->getNumValues() == Result.Val->getNumValues() &&
956 "Lowering call/formal_arguments produced unexpected # results!");
958 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
959 // remember that we legalized all of them, so it doesn't get relegalized.
960 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
961 Tmp1 = LegalizeOp(Tmp3.getValue(i));
964 AddLegalizedOperand(SDOperand(Node, i), Tmp1);
968 case ISD::BUILD_VECTOR:
969 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
970 default: assert(0 && "This action is not supported yet!");
971 case TargetLowering::Custom:
972 Tmp3 = TLI.LowerOperation(Result, DAG);
978 case TargetLowering::Expand:
979 Result = ExpandBUILD_VECTOR(Result.Val);
983 case ISD::INSERT_VECTOR_ELT:
984 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
985 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal
986 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
987 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
989 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
990 Node->getValueType(0))) {
991 default: assert(0 && "This action is not supported yet!");
992 case TargetLowering::Legal:
994 case TargetLowering::Custom:
995 Tmp3 = TLI.LowerOperation(Result, DAG);
1001 case TargetLowering::Expand: {
1002 // If the insert index is a constant, codegen this as a scalar_to_vector,
1003 // then a shuffle that inserts it into the right position in the vector.
1004 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1005 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
1006 Tmp1.getValueType(), Tmp2);
1008 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
1009 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
1010 MVT::ValueType ShufMaskEltVT = MVT::getVectorBaseType(ShufMaskVT);
1012 // We generate a shuffle of InVec and ScVec, so the shuffle mask should
1013 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of
1015 SmallVector<SDOperand, 8> ShufOps;
1016 for (unsigned i = 0; i != NumElts; ++i) {
1017 if (i != InsertPos->getValue())
1018 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1020 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1022 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1023 &ShufOps[0], ShufOps.size());
1025 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1026 Tmp1, ScVec, ShufMask);
1027 Result = LegalizeOp(Result);
1031 // If the target doesn't support this, we have to spill the input vector
1032 // to a temporary stack slot, update the element, then reload it. This is
1033 // badness. We could also load the value into a vector register (either
1034 // with a "move to register" or "extload into register" instruction, then
1035 // permute it into place, if the idx is a constant and if the idx is
1036 // supported by the target.
1037 MVT::ValueType VT = Tmp1.getValueType();
1038 MVT::ValueType EltVT = Tmp2.getValueType();
1039 MVT::ValueType IdxVT = Tmp3.getValueType();
1040 MVT::ValueType PtrVT = TLI.getPointerTy();
1041 SDOperand StackPtr = CreateStackTemporary(VT);
1042 // Store the vector.
1043 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, NULL, 0);
1045 // Truncate or zero extend offset to target pointer type.
1046 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
1047 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
1048 // Add the offset to the index.
1049 unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
1050 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
1051 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
1052 // Store the scalar value.
1053 Ch = DAG.getStore(Ch, Tmp2, StackPtr2, NULL, 0);
1054 // Load the updated vector.
1055 Result = DAG.getLoad(VT, Ch, StackPtr, NULL, 0);
1060 case ISD::SCALAR_TO_VECTOR:
1061 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1062 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1066 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1067 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1068 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1069 Node->getValueType(0))) {
1070 default: assert(0 && "This action is not supported yet!");
1071 case TargetLowering::Legal:
1073 case TargetLowering::Custom:
1074 Tmp3 = TLI.LowerOperation(Result, DAG);
1080 case TargetLowering::Expand:
1081 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1085 case ISD::VECTOR_SHUFFLE:
1086 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1087 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1088 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1090 // Allow targets to custom lower the SHUFFLEs they support.
1091 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1092 default: assert(0 && "Unknown operation action!");
1093 case TargetLowering::Legal:
1094 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1095 "vector shuffle should not be created if not legal!");
1097 case TargetLowering::Custom:
1098 Tmp3 = TLI.LowerOperation(Result, DAG);
1104 case TargetLowering::Expand: {
1105 MVT::ValueType VT = Node->getValueType(0);
1106 MVT::ValueType EltVT = MVT::getVectorBaseType(VT);
1107 MVT::ValueType PtrVT = TLI.getPointerTy();
1108 SDOperand Mask = Node->getOperand(2);
1109 unsigned NumElems = Mask.getNumOperands();
1110 SmallVector<SDOperand,8> Ops;
1111 for (unsigned i = 0; i != NumElems; ++i) {
1112 SDOperand Arg = Mask.getOperand(i);
1113 if (Arg.getOpcode() == ISD::UNDEF) {
1114 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1116 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1117 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
1119 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1120 DAG.getConstant(Idx, PtrVT)));
1122 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1123 DAG.getConstant(Idx - NumElems, PtrVT)));
1126 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1129 case TargetLowering::Promote: {
1130 // Change base type to a different vector type.
1131 MVT::ValueType OVT = Node->getValueType(0);
1132 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1134 // Cast the two input vectors.
1135 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1136 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1138 // Convert the shuffle mask to the right # elements.
1139 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1140 assert(Tmp3.Val && "Shuffle not legal?");
1141 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1142 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1148 case ISD::EXTRACT_VECTOR_ELT:
1149 Tmp1 = LegalizeOp(Node->getOperand(0));
1150 Tmp2 = LegalizeOp(Node->getOperand(1));
1151 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1153 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT,
1154 Tmp1.getValueType())) {
1155 default: assert(0 && "This action is not supported yet!");
1156 case TargetLowering::Legal:
1158 case TargetLowering::Custom:
1159 Tmp3 = TLI.LowerOperation(Result, DAG);
1165 case TargetLowering::Expand:
1166 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1171 case ISD::VEXTRACT_VECTOR_ELT:
1172 Result = LegalizeOp(LowerVEXTRACT_VECTOR_ELT(Op));
1175 case ISD::CALLSEQ_START: {
1176 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1178 // Recursively Legalize all of the inputs of the call end that do not lead
1179 // to this call start. This ensures that any libcalls that need be inserted
1180 // are inserted *before* the CALLSEQ_START.
1181 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1182 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1183 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
1187 // Now that we legalized all of the inputs (which may have inserted
1188 // libcalls) create the new CALLSEQ_START node.
1189 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1191 // Merge in the last call, to ensure that this call start after the last
1193 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1194 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1195 Tmp1 = LegalizeOp(Tmp1);
1198 // Do not try to legalize the target-specific arguments (#1+).
1199 if (Tmp1 != Node->getOperand(0)) {
1200 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1202 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1205 // Remember that the CALLSEQ_START is legalized.
1206 AddLegalizedOperand(Op.getValue(0), Result);
1207 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1208 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1210 // Now that the callseq_start and all of the non-call nodes above this call
1211 // sequence have been legalized, legalize the call itself. During this
1212 // process, no libcalls can/will be inserted, guaranteeing that no calls
1214 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1215 SDOperand InCallSEQ = LastCALLSEQ_END;
1216 // Note that we are selecting this call!
1217 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1218 IsLegalizingCall = true;
1220 // Legalize the call, starting from the CALLSEQ_END.
1221 LegalizeOp(LastCALLSEQ_END);
1222 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1225 case ISD::CALLSEQ_END:
1226 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1227 // will cause this node to be legalized as well as handling libcalls right.
1228 if (LastCALLSEQ_END.Val != Node) {
1229 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1230 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1231 assert(I != LegalizedNodes.end() &&
1232 "Legalizing the call start should have legalized this node!");
1236 // Otherwise, the call start has been legalized and everything is going
1237 // according to plan. Just legalize ourselves normally here.
1238 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1239 // Do not try to legalize the target-specific arguments (#1+), except for
1240 // an optional flag input.
1241 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1242 if (Tmp1 != Node->getOperand(0)) {
1243 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1245 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1248 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1249 if (Tmp1 != Node->getOperand(0) ||
1250 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1251 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1254 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1257 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1258 // This finishes up call legalization.
1259 IsLegalizingCall = false;
1261 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1262 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1263 if (Node->getNumValues() == 2)
1264 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1265 return Result.getValue(Op.ResNo);
1266 case ISD::DYNAMIC_STACKALLOC: {
1267 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1268 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1269 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1270 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1272 Tmp1 = Result.getValue(0);
1273 Tmp2 = Result.getValue(1);
1274 switch (TLI.getOperationAction(Node->getOpcode(),
1275 Node->getValueType(0))) {
1276 default: assert(0 && "This action is not supported yet!");
1277 case TargetLowering::Expand: {
1278 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1279 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1280 " not tell us which reg is the stack pointer!");
1281 SDOperand Chain = Tmp1.getOperand(0);
1282 SDOperand Size = Tmp2.getOperand(1);
1283 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, Node->getValueType(0));
1284 Tmp1 = DAG.getNode(ISD::SUB, Node->getValueType(0), SP, Size); // Value
1285 Tmp2 = DAG.getCopyToReg(SP.getValue(1), SPReg, Tmp1); // Output chain
1286 Tmp1 = LegalizeOp(Tmp1);
1287 Tmp2 = LegalizeOp(Tmp2);
1290 case TargetLowering::Custom:
1291 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1293 Tmp1 = LegalizeOp(Tmp3);
1294 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1297 case TargetLowering::Legal:
1300 // Since this op produce two values, make sure to remember that we
1301 // legalized both of them.
1302 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1303 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1304 return Op.ResNo ? Tmp2 : Tmp1;
1306 case ISD::INLINEASM: {
1307 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1308 bool Changed = false;
1309 // Legalize all of the operands of the inline asm, in case they are nodes
1310 // that need to be expanded or something. Note we skip the asm string and
1311 // all of the TargetConstant flags.
1312 SDOperand Op = LegalizeOp(Ops[0]);
1313 Changed = Op != Ops[0];
1316 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1317 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1318 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1319 for (++i; NumVals; ++i, --NumVals) {
1320 SDOperand Op = LegalizeOp(Ops[i]);
1329 Op = LegalizeOp(Ops.back());
1330 Changed |= Op != Ops.back();
1335 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1337 // INLINE asm returns a chain and flag, make sure to add both to the map.
1338 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1339 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1340 return Result.getValue(Op.ResNo);
1343 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1344 // Ensure that libcalls are emitted before a branch.
1345 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1346 Tmp1 = LegalizeOp(Tmp1);
1347 LastCALLSEQ_END = DAG.getEntryNode();
1349 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1352 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1353 // Ensure that libcalls are emitted before a branch.
1354 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1355 Tmp1 = LegalizeOp(Tmp1);
1356 LastCALLSEQ_END = DAG.getEntryNode();
1358 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1359 default: assert(0 && "Indirect target must be legal type (pointer)!");
1361 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1364 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1367 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1368 // Ensure that libcalls are emitted before a branch.
1369 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1370 Tmp1 = LegalizeOp(Tmp1);
1371 LastCALLSEQ_END = DAG.getEntryNode();
1373 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1374 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1376 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1377 default: assert(0 && "This action is not supported yet!");
1378 case TargetLowering::Legal: break;
1379 case TargetLowering::Custom:
1380 Tmp1 = TLI.LowerOperation(Result, DAG);
1381 if (Tmp1.Val) Result = Tmp1;
1383 case TargetLowering::Expand: {
1384 SDOperand Chain = Result.getOperand(0);
1385 SDOperand Table = Result.getOperand(1);
1386 SDOperand Index = Result.getOperand(2);
1388 MVT::ValueType PTy = TLI.getPointerTy();
1389 MachineFunction &MF = DAG.getMachineFunction();
1390 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
1391 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1392 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1395 switch (EntrySize) {
1396 default: assert(0 && "Size of jump table not supported yet."); break;
1397 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, NULL, 0); break;
1398 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, NULL, 0); break;
1401 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1402 // For PIC, the sequence is:
1403 // BRIND(load(Jumptable + index) + RelocBase)
1404 // RelocBase is the JumpTable on PPC and X86, GOT on Alpha
1406 if (TLI.usesGlobalOffsetTable())
1407 Reloc = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PTy);
1410 Addr = (PTy != MVT::i32) ? DAG.getNode(ISD::SIGN_EXTEND, PTy, LD) : LD;
1411 Addr = DAG.getNode(ISD::ADD, PTy, Addr, Reloc);
1412 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1414 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), LD);
1420 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1421 // Ensure that libcalls are emitted before a return.
1422 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1423 Tmp1 = LegalizeOp(Tmp1);
1424 LastCALLSEQ_END = DAG.getEntryNode();
1426 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1427 case Expand: assert(0 && "It's impossible to expand bools");
1429 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1432 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1434 // The top bits of the promoted condition are not necessarily zero, ensure
1435 // that the value is properly zero extended.
1436 if (!TLI.MaskedValueIsZero(Tmp2,
1437 MVT::getIntVTBitMask(Tmp2.getValueType())^1))
1438 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1442 // Basic block destination (Op#2) is always legal.
1443 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1445 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1446 default: assert(0 && "This action is not supported yet!");
1447 case TargetLowering::Legal: break;
1448 case TargetLowering::Custom:
1449 Tmp1 = TLI.LowerOperation(Result, DAG);
1450 if (Tmp1.Val) Result = Tmp1;
1452 case TargetLowering::Expand:
1453 // Expand brcond's setcc into its constituent parts and create a BR_CC
1455 if (Tmp2.getOpcode() == ISD::SETCC) {
1456 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1457 Tmp2.getOperand(0), Tmp2.getOperand(1),
1458 Node->getOperand(2));
1460 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1461 DAG.getCondCode(ISD::SETNE), Tmp2,
1462 DAG.getConstant(0, Tmp2.getValueType()),
1463 Node->getOperand(2));
1469 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1470 // Ensure that libcalls are emitted before a branch.
1471 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1472 Tmp1 = LegalizeOp(Tmp1);
1473 Tmp2 = Node->getOperand(2); // LHS
1474 Tmp3 = Node->getOperand(3); // RHS
1475 Tmp4 = Node->getOperand(1); // CC
1477 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1478 LastCALLSEQ_END = DAG.getEntryNode();
1480 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1481 // the LHS is a legal SETCC itself. In this case, we need to compare
1482 // the result against zero to select between true and false values.
1483 if (Tmp3.Val == 0) {
1484 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1485 Tmp4 = DAG.getCondCode(ISD::SETNE);
1488 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1489 Node->getOperand(4));
1491 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1492 default: assert(0 && "Unexpected action for BR_CC!");
1493 case TargetLowering::Legal: break;
1494 case TargetLowering::Custom:
1495 Tmp4 = TLI.LowerOperation(Result, DAG);
1496 if (Tmp4.Val) Result = Tmp4;
1501 LoadSDNode *LD = cast<LoadSDNode>(Node);
1502 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1503 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1505 ISD::LoadExtType ExtType = LD->getExtensionType();
1506 if (ExtType == ISD::NON_EXTLOAD) {
1507 MVT::ValueType VT = Node->getValueType(0);
1508 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1509 Tmp3 = Result.getValue(0);
1510 Tmp4 = Result.getValue(1);
1512 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1513 default: assert(0 && "This action is not supported yet!");
1514 case TargetLowering::Legal: break;
1515 case TargetLowering::Custom:
1516 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1518 Tmp3 = LegalizeOp(Tmp1);
1519 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1522 case TargetLowering::Promote: {
1523 // Only promote a load of vector type to another.
1524 assert(MVT::isVector(VT) && "Cannot promote this load!");
1525 // Change base type to a different vector type.
1526 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1528 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1529 LD->getSrcValueOffset());
1530 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1531 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1535 // Since loads produce two values, make sure to remember that we
1536 // legalized both of them.
1537 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1538 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1539 return Op.ResNo ? Tmp4 : Tmp3;
1541 MVT::ValueType SrcVT = LD->getLoadedVT();
1542 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
1543 default: assert(0 && "This action is not supported yet!");
1544 case TargetLowering::Promote:
1545 assert(SrcVT == MVT::i1 &&
1546 "Can only promote extending LOAD from i1 -> i8!");
1547 Result = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
1548 LD->getSrcValue(), LD->getSrcValueOffset(),
1550 Tmp1 = Result.getValue(0);
1551 Tmp2 = Result.getValue(1);
1553 case TargetLowering::Custom:
1556 case TargetLowering::Legal:
1557 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1558 Tmp1 = Result.getValue(0);
1559 Tmp2 = Result.getValue(1);
1562 Tmp3 = TLI.LowerOperation(Result, DAG);
1564 Tmp1 = LegalizeOp(Tmp3);
1565 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1569 case TargetLowering::Expand:
1570 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1571 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1572 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
1573 LD->getSrcValueOffset());
1574 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
1575 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1576 Tmp2 = LegalizeOp(Load.getValue(1));
1579 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
1580 // Turn the unsupported load into an EXTLOAD followed by an explicit
1581 // zero/sign extend inreg.
1582 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
1583 Tmp1, Tmp2, LD->getSrcValue(),
1584 LD->getSrcValueOffset(), SrcVT);
1586 if (ExtType == ISD::SEXTLOAD)
1587 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1588 Result, DAG.getValueType(SrcVT));
1590 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
1591 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1592 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1595 // Since loads produce two values, make sure to remember that we legalized
1597 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1598 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1599 return Op.ResNo ? Tmp2 : Tmp1;
1602 case ISD::EXTRACT_ELEMENT: {
1603 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
1604 switch (getTypeAction(OpTy)) {
1605 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
1607 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
1609 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
1610 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
1611 TLI.getShiftAmountTy()));
1612 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
1615 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
1616 Node->getOperand(0));
1620 // Get both the low and high parts.
1621 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1622 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
1623 Result = Tmp2; // 1 -> Hi
1625 Result = Tmp1; // 0 -> Lo
1631 case ISD::CopyToReg:
1632 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1634 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
1635 "Register type must be legal!");
1636 // Legalize the incoming value (must be a legal type).
1637 Tmp2 = LegalizeOp(Node->getOperand(2));
1638 if (Node->getNumValues() == 1) {
1639 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
1641 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
1642 if (Node->getNumOperands() == 4) {
1643 Tmp3 = LegalizeOp(Node->getOperand(3));
1644 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
1647 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1650 // Since this produces two values, make sure to remember that we legalized
1652 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1653 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1659 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1661 // Ensure that libcalls are emitted before a return.
1662 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1663 Tmp1 = LegalizeOp(Tmp1);
1664 LastCALLSEQ_END = DAG.getEntryNode();
1666 switch (Node->getNumOperands()) {
1668 Tmp2 = Node->getOperand(1);
1669 Tmp3 = Node->getOperand(2); // Signness
1670 switch (getTypeAction(Tmp2.getValueType())) {
1672 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
1675 if (Tmp2.getValueType() != MVT::Vector) {
1677 ExpandOp(Tmp2, Lo, Hi);
1679 // Big endian systems want the hi reg first.
1680 if (!TLI.isLittleEndian())
1684 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
1686 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
1687 Result = LegalizeOp(Result);
1689 SDNode *InVal = Tmp2.Val;
1691 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
1692 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
1694 // Figure out if there is a Packed type corresponding to this Vector
1695 // type. If so, convert to the vector type.
1696 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1697 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
1698 // Turn this into a return of the vector type.
1699 Tmp2 = PackVectorOp(Tmp2, TVT);
1700 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1701 } else if (NumElems == 1) {
1702 // Turn this into a return of the scalar type.
1703 Tmp2 = PackVectorOp(Tmp2, EVT);
1704 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1706 // FIXME: Returns of gcc generic vectors smaller than a legal type
1707 // should be returned in integer registers!
1709 // The scalarized value type may not be legal, e.g. it might require
1710 // promotion or expansion. Relegalize the return.
1711 Result = LegalizeOp(Result);
1713 // FIXME: Returns of gcc generic vectors larger than a legal vector
1714 // type should be returned by reference!
1716 SplitVectorOp(Tmp2, Lo, Hi);
1717 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
1718 Result = LegalizeOp(Result);
1723 Tmp2 = PromoteOp(Node->getOperand(1));
1724 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1725 Result = LegalizeOp(Result);
1730 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1732 default: { // ret <values>
1733 SmallVector<SDOperand, 8> NewValues;
1734 NewValues.push_back(Tmp1);
1735 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
1736 switch (getTypeAction(Node->getOperand(i).getValueType())) {
1738 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
1739 NewValues.push_back(Node->getOperand(i+1));
1743 assert(Node->getOperand(i).getValueType() != MVT::Vector &&
1744 "FIXME: TODO: implement returning non-legal vector types!");
1745 ExpandOp(Node->getOperand(i), Lo, Hi);
1746 NewValues.push_back(Lo);
1747 NewValues.push_back(Node->getOperand(i+1));
1749 NewValues.push_back(Hi);
1750 NewValues.push_back(Node->getOperand(i+1));
1755 assert(0 && "Can't promote multiple return value yet!");
1758 if (NewValues.size() == Node->getNumOperands())
1759 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
1761 Result = DAG.getNode(ISD::RET, MVT::Other,
1762 &NewValues[0], NewValues.size());
1767 if (Result.getOpcode() == ISD::RET) {
1768 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
1769 default: assert(0 && "This action is not supported yet!");
1770 case TargetLowering::Legal: break;
1771 case TargetLowering::Custom:
1772 Tmp1 = TLI.LowerOperation(Result, DAG);
1773 if (Tmp1.Val) Result = Tmp1;
1779 StoreSDNode *ST = cast<StoreSDNode>(Node);
1780 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
1781 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
1783 if (!ST->isTruncatingStore()) {
1784 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
1785 // FIXME: We shouldn't do this for TargetConstantFP's.
1786 // FIXME: move this to the DAG Combiner! Note that we can't regress due
1787 // to phase ordering between legalized code and the dag combiner. This
1788 // probably means that we need to integrate dag combiner and legalizer
1790 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
1791 if (CFP->getValueType(0) == MVT::f32) {
1792 Tmp3 = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32);
1794 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
1795 Tmp3 = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64);
1797 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1798 ST->getSrcValueOffset());
1802 switch (getTypeAction(ST->getStoredVT())) {
1804 Tmp3 = LegalizeOp(ST->getValue());
1805 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1808 MVT::ValueType VT = Tmp3.getValueType();
1809 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1810 default: assert(0 && "This action is not supported yet!");
1811 case TargetLowering::Legal: break;
1812 case TargetLowering::Custom:
1813 Tmp1 = TLI.LowerOperation(Result, DAG);
1814 if (Tmp1.Val) Result = Tmp1;
1816 case TargetLowering::Promote:
1817 assert(MVT::isVector(VT) && "Unknown legal promote case!");
1818 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
1819 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
1820 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
1821 ST->getSrcValue(), ST->getSrcValueOffset());
1827 // Truncate the value and store the result.
1828 Tmp3 = PromoteOp(ST->getValue());
1829 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1830 ST->getSrcValueOffset(), ST->getStoredVT());
1834 unsigned IncrementSize = 0;
1837 // If this is a vector type, then we have to calculate the increment as
1838 // the product of the element size in bytes, and the number of elements
1839 // in the high half of the vector.
1840 if (ST->getValue().getValueType() == MVT::Vector) {
1841 SDNode *InVal = ST->getValue().Val;
1843 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
1844 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
1846 // Figure out if there is a Packed type corresponding to this Vector
1847 // type. If so, convert to the vector type.
1848 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1849 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
1850 // Turn this into a normal store of the vector type.
1851 Tmp3 = PackVectorOp(Node->getOperand(1), TVT);
1852 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1853 ST->getSrcValueOffset());
1854 Result = LegalizeOp(Result);
1856 } else if (NumElems == 1) {
1857 // Turn this into a normal store of the scalar type.
1858 Tmp3 = PackVectorOp(Node->getOperand(1), EVT);
1859 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1860 ST->getSrcValueOffset());
1861 // The scalarized value type may not be legal, e.g. it might require
1862 // promotion or expansion. Relegalize the scalar store.
1863 Result = LegalizeOp(Result);
1866 SplitVectorOp(Node->getOperand(1), Lo, Hi);
1867 IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8;
1870 ExpandOp(Node->getOperand(1), Lo, Hi);
1871 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0;
1873 if (!TLI.isLittleEndian())
1877 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
1878 ST->getSrcValueOffset());
1880 if (Hi.Val == NULL) {
1881 // Must be int <-> float one-to-one expansion.
1886 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1887 getIntPtrConstant(IncrementSize));
1888 assert(isTypeLegal(Tmp2.getValueType()) &&
1889 "Pointers must be legal!");
1890 // FIXME: This sets the srcvalue of both halves to be the same, which is
1892 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
1893 ST->getSrcValueOffset());
1894 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
1899 assert(isTypeLegal(ST->getValue().getValueType()) &&
1900 "Cannot handle illegal TRUNCSTORE yet!");
1901 Tmp3 = LegalizeOp(ST->getValue());
1903 // The only promote case we handle is TRUNCSTORE:i1 X into
1904 // -> TRUNCSTORE:i8 (and X, 1)
1905 if (ST->getStoredVT() == MVT::i1 &&
1906 TLI.getStoreXAction(MVT::i1) == TargetLowering::Promote) {
1907 // Promote the bool to a mask then store.
1908 Tmp3 = DAG.getNode(ISD::AND, Tmp3.getValueType(), Tmp3,
1909 DAG.getConstant(1, Tmp3.getValueType()));
1910 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1911 ST->getSrcValueOffset(), MVT::i8);
1912 } else if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
1913 Tmp2 != ST->getBasePtr()) {
1914 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1918 MVT::ValueType StVT = cast<StoreSDNode>(Result.Val)->getStoredVT();
1919 switch (TLI.getStoreXAction(StVT)) {
1920 default: assert(0 && "This action is not supported yet!");
1921 case TargetLowering::Legal: break;
1922 case TargetLowering::Custom:
1923 Tmp1 = TLI.LowerOperation(Result, DAG);
1924 if (Tmp1.Val) Result = Tmp1;
1931 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1932 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1934 case ISD::STACKSAVE:
1935 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1936 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1937 Tmp1 = Result.getValue(0);
1938 Tmp2 = Result.getValue(1);
1940 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
1941 default: assert(0 && "This action is not supported yet!");
1942 case TargetLowering::Legal: break;
1943 case TargetLowering::Custom:
1944 Tmp3 = TLI.LowerOperation(Result, DAG);
1946 Tmp1 = LegalizeOp(Tmp3);
1947 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1950 case TargetLowering::Expand:
1951 // Expand to CopyFromReg if the target set
1952 // StackPointerRegisterToSaveRestore.
1953 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
1954 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
1955 Node->getValueType(0));
1956 Tmp2 = Tmp1.getValue(1);
1958 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
1959 Tmp2 = Node->getOperand(0);
1964 // Since stacksave produce two values, make sure to remember that we
1965 // legalized both of them.
1966 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1967 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1968 return Op.ResNo ? Tmp2 : Tmp1;
1970 case ISD::STACKRESTORE:
1971 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1972 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1973 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1975 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
1976 default: assert(0 && "This action is not supported yet!");
1977 case TargetLowering::Legal: break;
1978 case TargetLowering::Custom:
1979 Tmp1 = TLI.LowerOperation(Result, DAG);
1980 if (Tmp1.Val) Result = Tmp1;
1982 case TargetLowering::Expand:
1983 // Expand to CopyToReg if the target set
1984 // StackPointerRegisterToSaveRestore.
1985 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
1986 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
1994 case ISD::READCYCLECOUNTER:
1995 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
1996 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1997 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
1998 Node->getValueType(0))) {
1999 default: assert(0 && "This action is not supported yet!");
2000 case TargetLowering::Legal:
2001 Tmp1 = Result.getValue(0);
2002 Tmp2 = Result.getValue(1);
2004 case TargetLowering::Custom:
2005 Result = TLI.LowerOperation(Result, DAG);
2006 Tmp1 = LegalizeOp(Result.getValue(0));
2007 Tmp2 = LegalizeOp(Result.getValue(1));
2011 // Since rdcc produce two values, make sure to remember that we legalized
2013 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2014 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2018 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2019 case Expand: assert(0 && "It's impossible to expand bools");
2021 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2024 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2025 // Make sure the condition is either zero or one.
2026 if (!TLI.MaskedValueIsZero(Tmp1,
2027 MVT::getIntVTBitMask(Tmp1.getValueType())^1))
2028 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2031 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2032 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2034 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2036 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2037 default: assert(0 && "This action is not supported yet!");
2038 case TargetLowering::Legal: break;
2039 case TargetLowering::Custom: {
2040 Tmp1 = TLI.LowerOperation(Result, DAG);
2041 if (Tmp1.Val) Result = Tmp1;
2044 case TargetLowering::Expand:
2045 if (Tmp1.getOpcode() == ISD::SETCC) {
2046 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2048 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2050 Result = DAG.getSelectCC(Tmp1,
2051 DAG.getConstant(0, Tmp1.getValueType()),
2052 Tmp2, Tmp3, ISD::SETNE);
2055 case TargetLowering::Promote: {
2056 MVT::ValueType NVT =
2057 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2058 unsigned ExtOp, TruncOp;
2059 if (MVT::isVector(Tmp2.getValueType())) {
2060 ExtOp = ISD::BIT_CONVERT;
2061 TruncOp = ISD::BIT_CONVERT;
2062 } else if (MVT::isInteger(Tmp2.getValueType())) {
2063 ExtOp = ISD::ANY_EXTEND;
2064 TruncOp = ISD::TRUNCATE;
2066 ExtOp = ISD::FP_EXTEND;
2067 TruncOp = ISD::FP_ROUND;
2069 // Promote each of the values to the new type.
2070 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2071 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2072 // Perform the larger operation, then round down.
2073 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2074 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2079 case ISD::SELECT_CC: {
2080 Tmp1 = Node->getOperand(0); // LHS
2081 Tmp2 = Node->getOperand(1); // RHS
2082 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2083 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2084 SDOperand CC = Node->getOperand(4);
2086 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
2088 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
2089 // the LHS is a legal SETCC itself. In this case, we need to compare
2090 // the result against zero to select between true and false values.
2091 if (Tmp2.Val == 0) {
2092 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2093 CC = DAG.getCondCode(ISD::SETNE);
2095 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
2097 // Everything is legal, see if we should expand this op or something.
2098 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
2099 default: assert(0 && "This action is not supported yet!");
2100 case TargetLowering::Legal: break;
2101 case TargetLowering::Custom:
2102 Tmp1 = TLI.LowerOperation(Result, DAG);
2103 if (Tmp1.Val) Result = Tmp1;
2109 Tmp1 = Node->getOperand(0);
2110 Tmp2 = Node->getOperand(1);
2111 Tmp3 = Node->getOperand(2);
2112 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
2114 // If we had to Expand the SetCC operands into a SELECT node, then it may
2115 // not always be possible to return a true LHS & RHS. In this case, just
2116 // return the value we legalized, returned in the LHS
2117 if (Tmp2.Val == 0) {
2122 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
2123 default: assert(0 && "Cannot handle this action for SETCC yet!");
2124 case TargetLowering::Custom:
2127 case TargetLowering::Legal:
2128 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2130 Tmp4 = TLI.LowerOperation(Result, DAG);
2131 if (Tmp4.Val) Result = Tmp4;
2134 case TargetLowering::Promote: {
2135 // First step, figure out the appropriate operation to use.
2136 // Allow SETCC to not be supported for all legal data types
2137 // Mostly this targets FP
2138 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
2139 MVT::ValueType OldVT = NewInTy; OldVT = OldVT;
2141 // Scan for the appropriate larger type to use.
2143 NewInTy = (MVT::ValueType)(NewInTy+1);
2145 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
2146 "Fell off of the edge of the integer world");
2147 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
2148 "Fell off of the edge of the floating point world");
2150 // If the target supports SETCC of this type, use it.
2151 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2154 if (MVT::isInteger(NewInTy))
2155 assert(0 && "Cannot promote Legal Integer SETCC yet");
2157 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2158 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2160 Tmp1 = LegalizeOp(Tmp1);
2161 Tmp2 = LegalizeOp(Tmp2);
2162 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2163 Result = LegalizeOp(Result);
2166 case TargetLowering::Expand:
2167 // Expand a setcc node into a select_cc of the same condition, lhs, and
2168 // rhs that selects between const 1 (true) and const 0 (false).
2169 MVT::ValueType VT = Node->getValueType(0);
2170 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2171 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2178 case ISD::MEMMOVE: {
2179 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
2180 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
2182 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
2183 switch (getTypeAction(Node->getOperand(2).getValueType())) {
2184 case Expand: assert(0 && "Cannot expand a byte!");
2186 Tmp3 = LegalizeOp(Node->getOperand(2));
2189 Tmp3 = PromoteOp(Node->getOperand(2));
2193 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
2197 switch (getTypeAction(Node->getOperand(3).getValueType())) {
2199 // Length is too big, just take the lo-part of the length.
2201 ExpandOp(Node->getOperand(3), Tmp4, HiPart);
2205 Tmp4 = LegalizeOp(Node->getOperand(3));
2208 Tmp4 = PromoteOp(Node->getOperand(3));
2213 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
2214 case Expand: assert(0 && "Cannot expand this yet!");
2216 Tmp5 = LegalizeOp(Node->getOperand(4));
2219 Tmp5 = PromoteOp(Node->getOperand(4));
2223 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2224 default: assert(0 && "This action not implemented for this operation!");
2225 case TargetLowering::Custom:
2228 case TargetLowering::Legal:
2229 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, Tmp5);
2231 Tmp1 = TLI.LowerOperation(Result, DAG);
2232 if (Tmp1.Val) Result = Tmp1;
2235 case TargetLowering::Expand: {
2236 // Otherwise, the target does not support this operation. Lower the
2237 // operation to an explicit libcall as appropriate.
2238 MVT::ValueType IntPtr = TLI.getPointerTy();
2239 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType();
2240 TargetLowering::ArgListTy Args;
2241 TargetLowering::ArgListEntry Entry;
2243 const char *FnName = 0;
2244 if (Node->getOpcode() == ISD::MEMSET) {
2245 Entry.Node = Tmp2; Entry.Ty = IntPtrTy;
2246 Args.push_back(Entry);
2247 // Extend the (previously legalized) ubyte argument to be an int value
2249 if (Tmp3.getValueType() > MVT::i32)
2250 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
2252 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
2253 Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSExt = true;
2254 Args.push_back(Entry);
2255 Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSExt = false;
2256 Args.push_back(Entry);
2259 } else if (Node->getOpcode() == ISD::MEMCPY ||
2260 Node->getOpcode() == ISD::MEMMOVE) {
2261 Entry.Ty = IntPtrTy;
2262 Entry.Node = Tmp2; Args.push_back(Entry);
2263 Entry.Node = Tmp3; Args.push_back(Entry);
2264 Entry.Node = Tmp4; Args.push_back(Entry);
2265 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
2267 assert(0 && "Unknown op!");
2270 std::pair<SDOperand,SDOperand> CallResult =
2271 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, CallingConv::C, false,
2272 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
2273 Result = CallResult.second;
2280 case ISD::SHL_PARTS:
2281 case ISD::SRA_PARTS:
2282 case ISD::SRL_PARTS: {
2283 SmallVector<SDOperand, 8> Ops;
2284 bool Changed = false;
2285 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2286 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2287 Changed |= Ops.back() != Node->getOperand(i);
2290 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2292 switch (TLI.getOperationAction(Node->getOpcode(),
2293 Node->getValueType(0))) {
2294 default: assert(0 && "This action is not supported yet!");
2295 case TargetLowering::Legal: break;
2296 case TargetLowering::Custom:
2297 Tmp1 = TLI.LowerOperation(Result, DAG);
2299 SDOperand Tmp2, RetVal(0, 0);
2300 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2301 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2302 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2306 assert(RetVal.Val && "Illegal result number");
2312 // Since these produce multiple values, make sure to remember that we
2313 // legalized all of them.
2314 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2315 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2316 return Result.getValue(Op.ResNo);
2337 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2338 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2339 case Expand: assert(0 && "Not possible");
2341 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2344 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2348 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2350 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2351 default: assert(0 && "BinOp legalize operation not supported");
2352 case TargetLowering::Legal: break;
2353 case TargetLowering::Custom:
2354 Tmp1 = TLI.LowerOperation(Result, DAG);
2355 if (Tmp1.Val) Result = Tmp1;
2357 case TargetLowering::Expand: {
2358 if (Node->getValueType(0) == MVT::i32) {
2359 switch (Node->getOpcode()) {
2360 default: assert(0 && "Do not know how to expand this integer BinOp!");
2363 RTLIB::Libcall LC = Node->getOpcode() == ISD::UDIV
2364 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
2366 bool isSigned = Node->getOpcode() == ISD::SDIV;
2367 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
2372 assert(MVT::isVector(Node->getValueType(0)) &&
2373 "Cannot expand this binary operator!");
2374 // Expand the operation into a bunch of nasty scalar code.
2375 SmallVector<SDOperand, 8> Ops;
2376 MVT::ValueType EltVT = MVT::getVectorBaseType(Node->getValueType(0));
2377 MVT::ValueType PtrVT = TLI.getPointerTy();
2378 for (unsigned i = 0, e = MVT::getVectorNumElements(Node->getValueType(0));
2380 SDOperand Idx = DAG.getConstant(i, PtrVT);
2381 SDOperand LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, Idx);
2382 SDOperand RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, Idx);
2383 Ops.push_back(DAG.getNode(Node->getOpcode(), EltVT, LHS, RHS));
2385 Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0),
2386 &Ops[0], Ops.size());
2389 case TargetLowering::Promote: {
2390 switch (Node->getOpcode()) {
2391 default: assert(0 && "Do not know how to promote this BinOp!");
2395 MVT::ValueType OVT = Node->getValueType(0);
2396 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2397 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
2398 // Bit convert each of the values to the new type.
2399 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
2400 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
2401 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2402 // Bit convert the result back the original type.
2403 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
2411 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
2412 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2413 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2414 case Expand: assert(0 && "Not possible");
2416 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2419 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2423 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2425 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2426 default: assert(0 && "Operation not supported");
2427 case TargetLowering::Custom:
2428 Tmp1 = TLI.LowerOperation(Result, DAG);
2429 if (Tmp1.Val) Result = Tmp1;
2431 case TargetLowering::Legal: break;
2432 case TargetLowering::Expand: {
2433 // If this target supports fabs/fneg natively and select is cheap,
2434 // do this efficiently.
2435 if (!TLI.isSelectExpensive() &&
2436 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
2437 TargetLowering::Legal &&
2438 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
2439 TargetLowering::Legal) {
2440 // Get the sign bit of the RHS.
2441 MVT::ValueType IVT =
2442 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
2443 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
2444 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
2445 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
2446 // Get the absolute value of the result.
2447 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
2448 // Select between the nabs and abs value based on the sign bit of
2450 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
2451 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
2454 Result = LegalizeOp(Result);
2458 // Otherwise, do bitwise ops!
2459 MVT::ValueType NVT =
2460 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
2461 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
2462 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
2463 Result = LegalizeOp(Result);
2471 Tmp1 = LegalizeOp(Node->getOperand(0));
2472 Tmp2 = LegalizeOp(Node->getOperand(1));
2473 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2474 // Since this produces two values, make sure to remember that we legalized
2476 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2477 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2482 Tmp1 = LegalizeOp(Node->getOperand(0));
2483 Tmp2 = LegalizeOp(Node->getOperand(1));
2484 Tmp3 = LegalizeOp(Node->getOperand(2));
2485 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2486 // Since this produces two values, make sure to remember that we legalized
2488 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2489 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2492 case ISD::BUILD_PAIR: {
2493 MVT::ValueType PairTy = Node->getValueType(0);
2494 // TODO: handle the case where the Lo and Hi operands are not of legal type
2495 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
2496 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
2497 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
2498 case TargetLowering::Promote:
2499 case TargetLowering::Custom:
2500 assert(0 && "Cannot promote/custom this yet!");
2501 case TargetLowering::Legal:
2502 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
2503 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
2505 case TargetLowering::Expand:
2506 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
2507 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
2508 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
2509 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
2510 TLI.getShiftAmountTy()));
2511 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
2520 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2521 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2523 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2524 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
2525 case TargetLowering::Custom:
2528 case TargetLowering::Legal:
2529 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2531 Tmp1 = TLI.LowerOperation(Result, DAG);
2532 if (Tmp1.Val) Result = Tmp1;
2535 case TargetLowering::Expand:
2536 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
2537 bool isSigned = DivOpc == ISD::SDIV;
2538 if (MVT::isInteger(Node->getValueType(0))) {
2539 if (TLI.getOperationAction(DivOpc, Node->getValueType(0)) ==
2540 TargetLowering::Legal) {
2542 MVT::ValueType VT = Node->getValueType(0);
2543 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
2544 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
2545 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
2547 assert(Node->getValueType(0) == MVT::i32 &&
2548 "Cannot expand this binary operator!");
2549 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
2550 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
2552 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
2555 // Floating point mod -> fmod libcall.
2556 RTLIB::Libcall LC = Node->getValueType(0) == MVT::f32
2557 ? RTLIB::REM_F32 : RTLIB::REM_F64;
2559 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
2560 false/*sign irrelevant*/, Dummy);
2566 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2567 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2569 MVT::ValueType VT = Node->getValueType(0);
2570 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2571 default: assert(0 && "This action is not supported yet!");
2572 case TargetLowering::Custom:
2575 case TargetLowering::Legal:
2576 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2577 Result = Result.getValue(0);
2578 Tmp1 = Result.getValue(1);
2581 Tmp2 = TLI.LowerOperation(Result, DAG);
2583 Result = LegalizeOp(Tmp2);
2584 Tmp1 = LegalizeOp(Tmp2.getValue(1));
2588 case TargetLowering::Expand: {
2589 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
2590 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
2591 SV->getValue(), SV->getOffset());
2592 // Increment the pointer, VAList, to the next vaarg
2593 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
2594 DAG.getConstant(MVT::getSizeInBits(VT)/8,
2595 TLI.getPointerTy()));
2596 // Store the incremented VAList to the legalized pointer
2597 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
2599 // Load the actual argument out of the pointer VAList
2600 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
2601 Tmp1 = LegalizeOp(Result.getValue(1));
2602 Result = LegalizeOp(Result);
2606 // Since VAARG produces two values, make sure to remember that we
2607 // legalized both of them.
2608 AddLegalizedOperand(SDOperand(Node, 0), Result);
2609 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
2610 return Op.ResNo ? Tmp1 : Result;
2614 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2615 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
2616 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
2618 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
2619 default: assert(0 && "This action is not supported yet!");
2620 case TargetLowering::Custom:
2623 case TargetLowering::Legal:
2624 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
2625 Node->getOperand(3), Node->getOperand(4));
2627 Tmp1 = TLI.LowerOperation(Result, DAG);
2628 if (Tmp1.Val) Result = Tmp1;
2631 case TargetLowering::Expand:
2632 // This defaults to loading a pointer from the input and storing it to the
2633 // output, returning the chain.
2634 SrcValueSDNode *SVD = cast<SrcValueSDNode>(Node->getOperand(3));
2635 SrcValueSDNode *SVS = cast<SrcValueSDNode>(Node->getOperand(4));
2636 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD->getValue(),
2638 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, SVS->getValue(),
2645 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2646 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2648 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
2649 default: assert(0 && "This action is not supported yet!");
2650 case TargetLowering::Custom:
2653 case TargetLowering::Legal:
2654 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2656 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
2657 if (Tmp1.Val) Result = Tmp1;
2660 case TargetLowering::Expand:
2661 Result = Tmp1; // Default to a no-op, return the chain
2667 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2668 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2670 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2672 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
2673 default: assert(0 && "This action is not supported yet!");
2674 case TargetLowering::Legal: break;
2675 case TargetLowering::Custom:
2676 Tmp1 = TLI.LowerOperation(Result, DAG);
2677 if (Tmp1.Val) Result = Tmp1;
2684 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2685 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2687 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
2688 "Cannot handle this yet!");
2689 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2693 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2694 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2695 case TargetLowering::Custom:
2696 assert(0 && "Cannot custom legalize this yet!");
2697 case TargetLowering::Legal:
2698 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2700 case TargetLowering::Promote: {
2701 MVT::ValueType OVT = Tmp1.getValueType();
2702 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2703 unsigned DiffBits = getSizeInBits(NVT) - getSizeInBits(OVT);
2705 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2706 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
2707 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
2708 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
2711 case TargetLowering::Expand:
2712 Result = ExpandBSWAP(Tmp1);
2720 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2721 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2722 case TargetLowering::Custom: assert(0 && "Cannot custom handle this yet!");
2723 case TargetLowering::Legal:
2724 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2726 case TargetLowering::Promote: {
2727 MVT::ValueType OVT = Tmp1.getValueType();
2728 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2730 // Zero extend the argument.
2731 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2732 // Perform the larger operation, then subtract if needed.
2733 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2734 switch (Node->getOpcode()) {
2739 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2740 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
2741 DAG.getConstant(getSizeInBits(NVT), NVT),
2743 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
2744 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1);
2747 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2748 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
2749 DAG.getConstant(getSizeInBits(NVT) -
2750 getSizeInBits(OVT), NVT));
2755 case TargetLowering::Expand:
2756 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
2767 Tmp1 = LegalizeOp(Node->getOperand(0));
2768 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2769 case TargetLowering::Promote:
2770 case TargetLowering::Custom:
2773 case TargetLowering::Legal:
2774 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2776 Tmp1 = TLI.LowerOperation(Result, DAG);
2777 if (Tmp1.Val) Result = Tmp1;
2780 case TargetLowering::Expand:
2781 switch (Node->getOpcode()) {
2782 default: assert(0 && "Unreachable!");
2784 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2785 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2786 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
2789 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2790 MVT::ValueType VT = Node->getValueType(0);
2791 Tmp2 = DAG.getConstantFP(0.0, VT);
2792 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
2793 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
2794 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
2800 MVT::ValueType VT = Node->getValueType(0);
2801 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2802 switch(Node->getOpcode()) {
2804 LC = VT == MVT::f32 ? RTLIB::SQRT_F32 : RTLIB::SQRT_F64;
2807 LC = VT == MVT::f32 ? RTLIB::SIN_F32 : RTLIB::SIN_F64;
2810 LC = VT == MVT::f32 ? RTLIB::COS_F32 : RTLIB::COS_F64;
2812 default: assert(0 && "Unreachable!");
2815 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
2816 false/*sign irrelevant*/, Dummy);
2824 // We always lower FPOWI into a libcall. No target support it yet.
2825 RTLIB::Libcall LC = Node->getValueType(0) == MVT::f32
2826 ? RTLIB::POWI_F32 : RTLIB::POWI_F64;
2828 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
2829 false/*sign irrelevant*/, Dummy);
2832 case ISD::BIT_CONVERT:
2833 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
2834 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2836 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
2837 Node->getOperand(0).getValueType())) {
2838 default: assert(0 && "Unknown operation action!");
2839 case TargetLowering::Expand:
2840 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2842 case TargetLowering::Legal:
2843 Tmp1 = LegalizeOp(Node->getOperand(0));
2844 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2849 case ISD::VBIT_CONVERT: {
2850 assert(Op.getOperand(0).getValueType() == MVT::Vector &&
2851 "Can only have VBIT_CONVERT where input or output is MVT::Vector!");
2853 // The input has to be a vector type, we have to either scalarize it, pack
2854 // it, or convert it based on whether the input vector type is legal.
2855 SDNode *InVal = Node->getOperand(0).Val;
2857 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
2858 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
2860 // Figure out if there is a Packed type corresponding to this Vector
2861 // type. If so, convert to the vector type.
2862 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2863 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
2864 // Turn this into a bit convert of the packed input.
2865 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
2866 PackVectorOp(Node->getOperand(0), TVT));
2868 } else if (NumElems == 1) {
2869 // Turn this into a bit convert of the scalar input.
2870 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
2871 PackVectorOp(Node->getOperand(0), EVT));
2874 // FIXME: UNIMP! Store then reload
2875 assert(0 && "Cast from unsupported vector type not implemented yet!");
2879 // Conversion operators. The source and destination have different types.
2880 case ISD::SINT_TO_FP:
2881 case ISD::UINT_TO_FP: {
2882 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
2883 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2885 switch (TLI.getOperationAction(Node->getOpcode(),
2886 Node->getOperand(0).getValueType())) {
2887 default: assert(0 && "Unknown operation action!");
2888 case TargetLowering::Custom:
2891 case TargetLowering::Legal:
2892 Tmp1 = LegalizeOp(Node->getOperand(0));
2893 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2895 Tmp1 = TLI.LowerOperation(Result, DAG);
2896 if (Tmp1.Val) Result = Tmp1;
2899 case TargetLowering::Expand:
2900 Result = ExpandLegalINT_TO_FP(isSigned,
2901 LegalizeOp(Node->getOperand(0)),
2902 Node->getValueType(0));
2904 case TargetLowering::Promote:
2905 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
2906 Node->getValueType(0),
2912 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
2913 Node->getValueType(0), Node->getOperand(0));
2916 Tmp1 = PromoteOp(Node->getOperand(0));
2918 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
2919 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
2921 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
2922 Node->getOperand(0).getValueType());
2924 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2925 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
2931 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2933 Tmp1 = LegalizeOp(Node->getOperand(0));
2934 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2937 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2939 // Since the result is legal, we should just be able to truncate the low
2940 // part of the source.
2941 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
2944 Result = PromoteOp(Node->getOperand(0));
2945 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
2950 case ISD::FP_TO_SINT:
2951 case ISD::FP_TO_UINT:
2952 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2954 Tmp1 = LegalizeOp(Node->getOperand(0));
2956 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
2957 default: assert(0 && "Unknown operation action!");
2958 case TargetLowering::Custom:
2961 case TargetLowering::Legal:
2962 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2964 Tmp1 = TLI.LowerOperation(Result, DAG);
2965 if (Tmp1.Val) Result = Tmp1;
2968 case TargetLowering::Promote:
2969 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
2970 Node->getOpcode() == ISD::FP_TO_SINT);
2972 case TargetLowering::Expand:
2973 if (Node->getOpcode() == ISD::FP_TO_UINT) {
2974 SDOperand True, False;
2975 MVT::ValueType VT = Node->getOperand(0).getValueType();
2976 MVT::ValueType NVT = Node->getValueType(0);
2977 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1;
2978 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT);
2979 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
2980 Node->getOperand(0), Tmp2, ISD::SETLT);
2981 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
2982 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
2983 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
2985 False = DAG.getNode(ISD::XOR, NVT, False,
2986 DAG.getConstant(1ULL << ShiftAmt, NVT));
2987 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
2990 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
2996 // Convert f32 / f64 to i32 / i64.
2997 MVT::ValueType VT = Op.getValueType();
2998 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2999 switch (Node->getOpcode()) {
3000 case ISD::FP_TO_SINT:
3001 if (Node->getOperand(0).getValueType() == MVT::f32)
3002 LC = (VT == MVT::i32)
3003 ? RTLIB::FPTOSINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3005 LC = (VT == MVT::i32)
3006 ? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3008 case ISD::FP_TO_UINT:
3009 if (Node->getOperand(0).getValueType() == MVT::f32)
3010 LC = (VT == MVT::i32)
3011 ? RTLIB::FPTOUINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3013 LC = (VT == MVT::i32)
3014 ? RTLIB::FPTOUINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3016 default: assert(0 && "Unreachable!");
3019 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3020 false/*sign irrelevant*/, Dummy);
3024 Tmp1 = PromoteOp(Node->getOperand(0));
3025 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
3026 Result = LegalizeOp(Result);
3031 case ISD::ANY_EXTEND:
3032 case ISD::ZERO_EXTEND:
3033 case ISD::SIGN_EXTEND:
3034 case ISD::FP_EXTEND:
3036 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3037 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3039 Tmp1 = LegalizeOp(Node->getOperand(0));
3040 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3043 switch (Node->getOpcode()) {
3044 case ISD::ANY_EXTEND:
3045 Tmp1 = PromoteOp(Node->getOperand(0));
3046 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
3048 case ISD::ZERO_EXTEND:
3049 Result = PromoteOp(Node->getOperand(0));
3050 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3051 Result = DAG.getZeroExtendInReg(Result,
3052 Node->getOperand(0).getValueType());
3054 case ISD::SIGN_EXTEND:
3055 Result = PromoteOp(Node->getOperand(0));
3056 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3057 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3059 DAG.getValueType(Node->getOperand(0).getValueType()));
3061 case ISD::FP_EXTEND:
3062 Result = PromoteOp(Node->getOperand(0));
3063 if (Result.getValueType() != Op.getValueType())
3064 // Dynamically dead while we have only 2 FP types.
3065 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result);
3068 Result = PromoteOp(Node->getOperand(0));
3069 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
3074 case ISD::FP_ROUND_INREG:
3075 case ISD::SIGN_EXTEND_INREG: {
3076 Tmp1 = LegalizeOp(Node->getOperand(0));
3077 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3079 // If this operation is not supported, convert it to a shl/shr or load/store
3081 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
3082 default: assert(0 && "This action not supported for this op yet!");
3083 case TargetLowering::Legal:
3084 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3086 case TargetLowering::Expand:
3087 // If this is an integer extend and shifts are supported, do that.
3088 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
3089 // NOTE: we could fall back on load/store here too for targets without
3090 // SAR. However, it is doubtful that any exist.
3091 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
3092 MVT::getSizeInBits(ExtraVT);
3093 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
3094 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
3095 Node->getOperand(0), ShiftCst);
3096 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
3098 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
3099 // The only way we can lower this is to turn it into a TRUNCSTORE,
3100 // EXTLOAD pair, targetting a temporary location (a stack slot).
3102 // NOTE: there is a choice here between constantly creating new stack
3103 // slots and always reusing the same one. We currently always create
3104 // new ones, as reuse may inhibit scheduling.
3105 const Type *Ty = MVT::getTypeForValueType(ExtraVT);
3106 unsigned TySize = (unsigned)TLI.getTargetData()->getTypeSize(Ty);
3107 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
3108 MachineFunction &MF = DAG.getMachineFunction();
3110 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
3111 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3112 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0),
3113 StackSlot, NULL, 0, ExtraVT);
3114 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
3115 Result, StackSlot, NULL, 0, ExtraVT);
3117 assert(0 && "Unknown op");
3125 assert(Result.getValueType() == Op.getValueType() &&
3126 "Bad legalization!");
3128 // Make sure that the generated code is itself legal.
3130 Result = LegalizeOp(Result);
3132 // Note that LegalizeOp may be reentered even from single-use nodes, which
3133 // means that we always must cache transformed nodes.
3134 AddLegalizedOperand(Op, Result);
3138 /// PromoteOp - Given an operation that produces a value in an invalid type,
3139 /// promote it to compute the value into a larger type. The produced value will
3140 /// have the correct bits for the low portion of the register, but no guarantee
3141 /// is made about the top bits: it may be zero, sign-extended, or garbage.
3142 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
3143 MVT::ValueType VT = Op.getValueType();
3144 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3145 assert(getTypeAction(VT) == Promote &&
3146 "Caller should expand or legalize operands that are not promotable!");
3147 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
3148 "Cannot promote to smaller type!");
3150 SDOperand Tmp1, Tmp2, Tmp3;
3152 SDNode *Node = Op.Val;
3154 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
3155 if (I != PromotedNodes.end()) return I->second;
3157 switch (Node->getOpcode()) {
3158 case ISD::CopyFromReg:
3159 assert(0 && "CopyFromReg must be legal!");
3162 cerr << "NODE: "; Node->dump(); cerr << "\n";
3164 assert(0 && "Do not know how to promote this operator!");
3167 Result = DAG.getNode(ISD::UNDEF, NVT);
3171 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
3173 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
3174 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
3176 case ISD::ConstantFP:
3177 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
3178 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
3182 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
3183 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
3184 Node->getOperand(1), Node->getOperand(2));
3188 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3190 Result = LegalizeOp(Node->getOperand(0));
3191 assert(Result.getValueType() >= NVT &&
3192 "This truncation doesn't make sense!");
3193 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
3194 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
3197 // The truncation is not required, because we don't guarantee anything
3198 // about high bits anyway.
3199 Result = PromoteOp(Node->getOperand(0));
3202 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3203 // Truncate the low part of the expanded value to the result type
3204 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
3207 case ISD::SIGN_EXTEND:
3208 case ISD::ZERO_EXTEND:
3209 case ISD::ANY_EXTEND:
3210 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3211 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
3213 // Input is legal? Just do extend all the way to the larger type.
3214 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
3217 // Promote the reg if it's smaller.
3218 Result = PromoteOp(Node->getOperand(0));
3219 // The high bits are not guaranteed to be anything. Insert an extend.
3220 if (Node->getOpcode() == ISD::SIGN_EXTEND)
3221 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3222 DAG.getValueType(Node->getOperand(0).getValueType()));
3223 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
3224 Result = DAG.getZeroExtendInReg(Result,
3225 Node->getOperand(0).getValueType());
3229 case ISD::BIT_CONVERT:
3230 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
3231 Result = PromoteOp(Result);
3234 case ISD::FP_EXTEND:
3235 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
3237 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3238 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
3239 case Promote: assert(0 && "Unreachable with 2 FP types!");
3241 // Input is legal? Do an FP_ROUND_INREG.
3242 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
3243 DAG.getValueType(VT));
3248 case ISD::SINT_TO_FP:
3249 case ISD::UINT_TO_FP:
3250 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3252 // No extra round required here.
3253 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
3257 Result = PromoteOp(Node->getOperand(0));
3258 if (Node->getOpcode() == ISD::SINT_TO_FP)
3259 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3261 DAG.getValueType(Node->getOperand(0).getValueType()));
3263 Result = DAG.getZeroExtendInReg(Result,
3264 Node->getOperand(0).getValueType());
3265 // No extra round required here.
3266 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
3269 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
3270 Node->getOperand(0));
3271 // Round if we cannot tolerate excess precision.
3272 if (NoExcessFPPrecision)
3273 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3274 DAG.getValueType(VT));
3279 case ISD::SIGN_EXTEND_INREG:
3280 Result = PromoteOp(Node->getOperand(0));
3281 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3282 Node->getOperand(1));
3284 case ISD::FP_TO_SINT:
3285 case ISD::FP_TO_UINT:
3286 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3289 Tmp1 = Node->getOperand(0);
3292 // The input result is prerounded, so we don't have to do anything
3294 Tmp1 = PromoteOp(Node->getOperand(0));
3297 // If we're promoting a UINT to a larger size, check to see if the new node
3298 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
3299 // we can use that instead. This allows us to generate better code for
3300 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
3301 // legal, such as PowerPC.
3302 if (Node->getOpcode() == ISD::FP_TO_UINT &&
3303 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
3304 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
3305 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
3306 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
3308 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3314 Tmp1 = PromoteOp(Node->getOperand(0));
3315 assert(Tmp1.getValueType() == NVT);
3316 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3317 // NOTE: we do not have to do any extra rounding here for
3318 // NoExcessFPPrecision, because we know the input will have the appropriate
3319 // precision, and these operations don't modify precision at all.
3325 Tmp1 = PromoteOp(Node->getOperand(0));
3326 assert(Tmp1.getValueType() == NVT);
3327 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3328 if (NoExcessFPPrecision)
3329 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3330 DAG.getValueType(VT));
3334 // Promote f32 powi to f64 powi. Note that this could insert a libcall
3335 // directly as well, which may be better.
3336 Tmp1 = PromoteOp(Node->getOperand(0));
3337 assert(Tmp1.getValueType() == NVT);
3338 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1));
3339 if (NoExcessFPPrecision)
3340 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3341 DAG.getValueType(VT));
3351 // The input may have strange things in the top bits of the registers, but
3352 // these operations don't care. They may have weird bits going out, but
3353 // that too is okay if they are integer operations.
3354 Tmp1 = PromoteOp(Node->getOperand(0));
3355 Tmp2 = PromoteOp(Node->getOperand(1));
3356 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3357 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3362 Tmp1 = PromoteOp(Node->getOperand(0));
3363 Tmp2 = PromoteOp(Node->getOperand(1));
3364 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3365 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3367 // Floating point operations will give excess precision that we may not be
3368 // able to tolerate. If we DO allow excess precision, just leave it,
3369 // otherwise excise it.
3370 // FIXME: Why would we need to round FP ops more than integer ones?
3371 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
3372 if (NoExcessFPPrecision)
3373 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3374 DAG.getValueType(VT));
3379 // These operators require that their input be sign extended.
3380 Tmp1 = PromoteOp(Node->getOperand(0));
3381 Tmp2 = PromoteOp(Node->getOperand(1));
3382 if (MVT::isInteger(NVT)) {
3383 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3384 DAG.getValueType(VT));
3385 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3386 DAG.getValueType(VT));
3388 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3390 // Perform FP_ROUND: this is probably overly pessimistic.
3391 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
3392 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3393 DAG.getValueType(VT));
3397 case ISD::FCOPYSIGN:
3398 // These operators require that their input be fp extended.
3399 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3401 Tmp1 = LegalizeOp(Node->getOperand(0));
3404 Tmp1 = PromoteOp(Node->getOperand(0));
3407 assert(0 && "not implemented");
3409 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3411 Tmp2 = LegalizeOp(Node->getOperand(1));
3414 Tmp2 = PromoteOp(Node->getOperand(1));
3417 assert(0 && "not implemented");
3419 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3421 // Perform FP_ROUND: this is probably overly pessimistic.
3422 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
3423 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3424 DAG.getValueType(VT));
3429 // These operators require that their input be zero extended.
3430 Tmp1 = PromoteOp(Node->getOperand(0));
3431 Tmp2 = PromoteOp(Node->getOperand(1));
3432 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
3433 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3434 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3435 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3439 Tmp1 = PromoteOp(Node->getOperand(0));
3440 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
3443 // The input value must be properly sign extended.
3444 Tmp1 = PromoteOp(Node->getOperand(0));
3445 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3446 DAG.getValueType(VT));
3447 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
3450 // The input value must be properly zero extended.
3451 Tmp1 = PromoteOp(Node->getOperand(0));
3452 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3453 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
3457 Tmp1 = Node->getOperand(0); // Get the chain.
3458 Tmp2 = Node->getOperand(1); // Get the pointer.
3459 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
3460 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
3461 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
3463 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
3464 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
3465 SV->getValue(), SV->getOffset());
3466 // Increment the pointer, VAList, to the next vaarg
3467 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3468 DAG.getConstant(MVT::getSizeInBits(VT)/8,
3469 TLI.getPointerTy()));
3470 // Store the incremented VAList to the legalized pointer
3471 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
3473 // Load the actual argument out of the pointer VAList
3474 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
3476 // Remember that we legalized the chain.
3477 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3481 LoadSDNode *LD = cast<LoadSDNode>(Node);
3482 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
3483 ? ISD::EXTLOAD : LD->getExtensionType();
3484 Result = DAG.getExtLoad(ExtType, NVT,
3485 LD->getChain(), LD->getBasePtr(),
3486 LD->getSrcValue(), LD->getSrcValueOffset(),
3488 // Remember that we legalized the chain.
3489 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3493 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
3494 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
3495 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
3497 case ISD::SELECT_CC:
3498 Tmp2 = PromoteOp(Node->getOperand(2)); // True
3499 Tmp3 = PromoteOp(Node->getOperand(3)); // False
3500 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3501 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
3504 Tmp1 = Node->getOperand(0);
3505 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3506 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3507 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3508 DAG.getConstant(getSizeInBits(NVT) - getSizeInBits(VT),
3509 TLI.getShiftAmountTy()));
3514 // Zero extend the argument
3515 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
3516 // Perform the larger operation, then subtract if needed.
3517 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3518 switch(Node->getOpcode()) {
3523 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3524 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
3525 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ);
3526 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3527 DAG.getConstant(getSizeInBits(VT), NVT), Tmp1);
3530 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3531 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3532 DAG.getConstant(getSizeInBits(NVT) -
3533 getSizeInBits(VT), NVT));
3537 case ISD::VEXTRACT_VECTOR_ELT:
3538 Result = PromoteOp(LowerVEXTRACT_VECTOR_ELT(Op));
3540 case ISD::EXTRACT_VECTOR_ELT:
3541 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
3545 assert(Result.Val && "Didn't set a result!");
3547 // Make sure the result is itself legal.
3548 Result = LegalizeOp(Result);
3550 // Remember that we promoted this!
3551 AddPromotedOperand(Op, Result);
3555 /// LowerVEXTRACT_VECTOR_ELT - Lower a VEXTRACT_VECTOR_ELT operation into a
3556 /// EXTRACT_VECTOR_ELT operation, to memory operations, or to scalar code based
3557 /// on the vector type. The return type of this matches the element type of the
3558 /// vector, which may not be legal for the target.
3559 SDOperand SelectionDAGLegalize::LowerVEXTRACT_VECTOR_ELT(SDOperand Op) {
3560 // We know that operand #0 is the Vec vector. If the index is a constant
3561 // or if the invec is a supported hardware type, we can use it. Otherwise,
3562 // lower to a store then an indexed load.
3563 SDOperand Vec = Op.getOperand(0);
3564 SDOperand Idx = LegalizeOp(Op.getOperand(1));
3566 SDNode *InVal = Vec.Val;
3567 unsigned NumElems = cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
3568 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
3570 // Figure out if there is a Packed type corresponding to this Vector
3571 // type. If so, convert to the vector type.
3572 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
3573 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
3574 // Turn this into a packed extract_vector_elt operation.
3575 Vec = PackVectorOp(Vec, TVT);
3576 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Op.getValueType(), Vec, Idx);
3577 } else if (NumElems == 1) {
3578 // This must be an access of the only element. Return it.
3579 return PackVectorOp(Vec, EVT);
3580 } else if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
3582 SplitVectorOp(Vec, Lo, Hi);
3583 if (CIdx->getValue() < NumElems/2) {
3587 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
3590 // It's now an extract from the appropriate high or low part. Recurse.
3591 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3592 return LowerVEXTRACT_VECTOR_ELT(Op);
3594 // Variable index case for extract element.
3595 // FIXME: IMPLEMENT STORE/LOAD lowering. Need alignment of stack slot!!
3596 assert(0 && "unimp!");
3601 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
3603 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
3604 SDOperand Vector = Op.getOperand(0);
3605 SDOperand Idx = Op.getOperand(1);
3607 // If the target doesn't support this, store the value to a temporary
3608 // stack slot, then LOAD the scalar element back out.
3609 SDOperand StackPtr = CreateStackTemporary(Vector.getValueType());
3610 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vector, StackPtr, NULL, 0);
3612 // Add the offset to the index.
3613 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
3614 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
3615 DAG.getConstant(EltSize, Idx.getValueType()));
3616 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
3618 return DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
3622 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
3623 /// with condition CC on the current target. This usually involves legalizing
3624 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
3625 /// there may be no choice but to create a new SetCC node to represent the
3626 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
3627 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
3628 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
3631 SDOperand Tmp1, Tmp2, Result;
3633 switch (getTypeAction(LHS.getValueType())) {
3635 Tmp1 = LegalizeOp(LHS); // LHS
3636 Tmp2 = LegalizeOp(RHS); // RHS
3639 Tmp1 = PromoteOp(LHS); // LHS
3640 Tmp2 = PromoteOp(RHS); // RHS
3642 // If this is an FP compare, the operands have already been extended.
3643 if (MVT::isInteger(LHS.getValueType())) {
3644 MVT::ValueType VT = LHS.getValueType();
3645 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3647 // Otherwise, we have to insert explicit sign or zero extends. Note
3648 // that we could insert sign extends for ALL conditions, but zero extend
3649 // is cheaper on many machines (an AND instead of two shifts), so prefer
3651 switch (cast<CondCodeSDNode>(CC)->get()) {
3652 default: assert(0 && "Unknown integer comparison!");
3659 // ALL of these operations will work if we either sign or zero extend
3660 // the operands (including the unsigned comparisons!). Zero extend is
3661 // usually a simpler/cheaper operation, so prefer it.
3662 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3663 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3669 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3670 DAG.getValueType(VT));
3671 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3672 DAG.getValueType(VT));
3678 MVT::ValueType VT = LHS.getValueType();
3679 if (VT == MVT::f32 || VT == MVT::f64) {
3680 // Expand into one or more soft-fp libcall(s).
3681 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL;
3682 switch (cast<CondCodeSDNode>(CC)->get()) {
3685 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
3689 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
3693 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
3697 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
3701 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
3705 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
3708 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
3711 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
3714 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
3715 switch (cast<CondCodeSDNode>(CC)->get()) {
3717 // SETONE = SETOLT | SETOGT
3718 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
3721 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
3724 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
3727 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
3730 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
3733 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
3735 default: assert(0 && "Unsupported FP setcc!");
3740 Tmp1 = ExpandLibCall(TLI.getLibcallName(LC1),
3741 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
3742 false /*sign irrelevant*/, Dummy);
3743 Tmp2 = DAG.getConstant(0, MVT::i32);
3744 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
3745 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
3746 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC);
3747 LHS = ExpandLibCall(TLI.getLibcallName(LC2),
3748 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
3749 false /*sign irrelevant*/, Dummy);
3750 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2,
3751 DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
3752 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
3760 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
3761 ExpandOp(LHS, LHSLo, LHSHi);
3762 ExpandOp(RHS, RHSLo, RHSHi);
3763 switch (cast<CondCodeSDNode>(CC)->get()) {
3767 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
3768 if (RHSCST->isAllOnesValue()) {
3769 // Comparison to -1.
3770 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
3775 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
3776 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
3777 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
3778 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3781 // If this is a comparison of the sign bit, just look at the top part.
3783 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
3784 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
3785 CST->getValue() == 0) || // X < 0
3786 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
3787 CST->isAllOnesValue())) { // X > -1
3793 // FIXME: This generated code sucks.
3794 ISD::CondCode LowCC;
3795 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
3797 default: assert(0 && "Unknown integer setcc!");
3799 case ISD::SETULT: LowCC = ISD::SETULT; break;
3801 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
3803 case ISD::SETULE: LowCC = ISD::SETULE; break;
3805 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
3808 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
3809 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
3810 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
3812 // NOTE: on targets without efficient SELECT of bools, we can always use
3813 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
3814 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
3815 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC,
3816 false, DagCombineInfo);
3818 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
3819 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
3820 CCCode, false, DagCombineInfo);
3822 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi, CC);
3824 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
3825 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
3826 if ((Tmp1C && Tmp1C->getValue() == 0) ||
3827 (Tmp2C && Tmp2C->getValue() == 0 &&
3828 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
3829 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
3830 (Tmp2C && Tmp2C->getValue() == 1 &&
3831 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
3832 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
3833 // low part is known false, returns high part.
3834 // For LE / GE, if high part is known false, ignore the low part.
3835 // For LT / GT, if high part is known true, ignore the low part.
3839 Result = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
3840 ISD::SETEQ, false, DagCombineInfo);
3842 Result=DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
3843 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
3844 Result, Tmp1, Tmp2));
3855 /// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination.
3856 /// The resultant code need not be legal. Note that SrcOp is the input operand
3857 /// to the BIT_CONVERT, not the BIT_CONVERT node itself.
3858 SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT,
3860 // Create the stack frame object.
3861 SDOperand FIPtr = CreateStackTemporary(DestVT);
3863 // Emit a store to the stack slot.
3864 SDOperand Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0);
3865 // Result is a load from the stack slot.
3866 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0);
3869 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
3870 // Create a vector sized/aligned stack slot, store the value to element #0,
3871 // then load the whole vector back out.
3872 SDOperand StackPtr = CreateStackTemporary(Node->getValueType(0));
3873 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
3875 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, NULL, 0);
3879 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
3880 /// support the operation, but do support the resultant packed vector type.
3881 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
3883 // If the only non-undef value is the low element, turn this into a
3884 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
3885 unsigned NumElems = Node->getNumOperands();
3886 bool isOnlyLowElement = true;
3887 SDOperand SplatValue = Node->getOperand(0);
3888 std::map<SDOperand, std::vector<unsigned> > Values;
3889 Values[SplatValue].push_back(0);
3890 bool isConstant = true;
3891 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
3892 SplatValue.getOpcode() != ISD::UNDEF)
3895 for (unsigned i = 1; i < NumElems; ++i) {
3896 SDOperand V = Node->getOperand(i);
3897 Values[V].push_back(i);
3898 if (V.getOpcode() != ISD::UNDEF)
3899 isOnlyLowElement = false;
3900 if (SplatValue != V)
3901 SplatValue = SDOperand(0,0);
3903 // If this isn't a constant element or an undef, we can't use a constant
3905 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
3906 V.getOpcode() != ISD::UNDEF)
3910 if (isOnlyLowElement) {
3911 // If the low element is an undef too, then this whole things is an undef.
3912 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
3913 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
3914 // Otherwise, turn this into a scalar_to_vector node.
3915 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
3916 Node->getOperand(0));
3919 // If all elements are constants, create a load from the constant pool.
3921 MVT::ValueType VT = Node->getValueType(0);
3923 MVT::getTypeForValueType(Node->getOperand(0).getValueType());
3924 std::vector<Constant*> CV;
3925 for (unsigned i = 0, e = NumElems; i != e; ++i) {
3926 if (ConstantFPSDNode *V =
3927 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
3928 CV.push_back(ConstantFP::get(OpNTy, V->getValue()));
3929 } else if (ConstantSDNode *V =
3930 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
3931 CV.push_back(ConstantInt::get(OpNTy, V->getValue()));
3933 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
3934 CV.push_back(UndefValue::get(OpNTy));
3937 Constant *CP = ConstantVector::get(CV);
3938 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
3939 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
3942 if (SplatValue.Val) { // Splat of one value?
3943 // Build the shuffle constant vector: <0, 0, 0, 0>
3944 MVT::ValueType MaskVT =
3945 MVT::getIntVectorWithNumElements(NumElems);
3946 SDOperand Zero = DAG.getConstant(0, MVT::getVectorBaseType(MaskVT));
3947 std::vector<SDOperand> ZeroVec(NumElems, Zero);
3948 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3949 &ZeroVec[0], ZeroVec.size());
3951 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
3952 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
3953 // Get the splatted value into the low element of a vector register.
3954 SDOperand LowValVec =
3955 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
3957 // Return shuffle(LowValVec, undef, <0,0,0,0>)
3958 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
3959 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
3964 // If there are only two unique elements, we may be able to turn this into a
3966 if (Values.size() == 2) {
3967 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
3968 MVT::ValueType MaskVT =
3969 MVT::getIntVectorWithNumElements(NumElems);
3970 std::vector<SDOperand> MaskVec(NumElems);
3972 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
3973 E = Values.end(); I != E; ++I) {
3974 for (std::vector<unsigned>::iterator II = I->second.begin(),
3975 EE = I->second.end(); II != EE; ++II)
3976 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorBaseType(MaskVT));
3979 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3980 &MaskVec[0], MaskVec.size());
3982 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
3983 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
3984 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
3985 SmallVector<SDOperand, 8> Ops;
3986 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
3987 E = Values.end(); I != E; ++I) {
3988 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
3992 Ops.push_back(ShuffleMask);
3994 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
3995 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0),
3996 &Ops[0], Ops.size());
4000 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
4001 // aligned object on the stack, store each element into it, then load
4002 // the result as a vector.
4003 MVT::ValueType VT = Node->getValueType(0);
4004 // Create the stack frame object.
4005 SDOperand FIPtr = CreateStackTemporary(VT);
4007 // Emit a store of each element to the stack slot.
4008 SmallVector<SDOperand, 8> Stores;
4009 unsigned TypeByteSize =
4010 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
4011 // Store (in the right endianness) the elements to memory.
4012 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
4013 // Ignore undef elements.
4014 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
4016 unsigned Offset = TypeByteSize*i;
4018 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
4019 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
4021 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
4025 SDOperand StoreChain;
4026 if (!Stores.empty()) // Not all undef elements?
4027 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4028 &Stores[0], Stores.size());
4030 StoreChain = DAG.getEntryNode();
4032 // Result is a load from the stack slot.
4033 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
4036 /// CreateStackTemporary - Create a stack temporary, suitable for holding the
4037 /// specified value type.
4038 SDOperand SelectionDAGLegalize::CreateStackTemporary(MVT::ValueType VT) {
4039 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
4040 unsigned ByteSize = MVT::getSizeInBits(VT)/8;
4041 const Type *Ty = MVT::getTypeForValueType(VT);
4042 unsigned StackAlign = (unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty);
4043 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign);
4044 return DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
4047 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
4048 SDOperand Op, SDOperand Amt,
4049 SDOperand &Lo, SDOperand &Hi) {
4050 // Expand the subcomponents.
4051 SDOperand LHSL, LHSH;
4052 ExpandOp(Op, LHSL, LHSH);
4054 SDOperand Ops[] = { LHSL, LHSH, Amt };
4055 MVT::ValueType VT = LHSL.getValueType();
4056 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
4057 Hi = Lo.getValue(1);
4061 /// ExpandShift - Try to find a clever way to expand this shift operation out to
4062 /// smaller elements. If we can't find a way that is more efficient than a
4063 /// libcall on this target, return false. Otherwise, return true with the
4064 /// low-parts expanded into Lo and Hi.
4065 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
4066 SDOperand &Lo, SDOperand &Hi) {
4067 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
4068 "This is not a shift!");
4070 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
4071 SDOperand ShAmt = LegalizeOp(Amt);
4072 MVT::ValueType ShTy = ShAmt.getValueType();
4073 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
4074 unsigned NVTBits = MVT::getSizeInBits(NVT);
4076 // Handle the case when Amt is an immediate. Other cases are currently broken
4077 // and are disabled.
4078 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
4079 unsigned Cst = CN->getValue();
4080 // Expand the incoming operand to be shifted, so that we have its parts
4082 ExpandOp(Op, InL, InH);
4086 Lo = DAG.getConstant(0, NVT);
4087 Hi = DAG.getConstant(0, NVT);
4088 } else if (Cst > NVTBits) {
4089 Lo = DAG.getConstant(0, NVT);
4090 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
4091 } else if (Cst == NVTBits) {
4092 Lo = DAG.getConstant(0, NVT);
4095 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
4096 Hi = DAG.getNode(ISD::OR, NVT,
4097 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
4098 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
4103 Lo = DAG.getConstant(0, NVT);
4104 Hi = DAG.getConstant(0, NVT);
4105 } else if (Cst > NVTBits) {
4106 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
4107 Hi = DAG.getConstant(0, NVT);
4108 } else if (Cst == NVTBits) {
4110 Hi = DAG.getConstant(0, NVT);
4112 Lo = DAG.getNode(ISD::OR, NVT,
4113 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
4114 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
4115 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
4120 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
4121 DAG.getConstant(NVTBits-1, ShTy));
4122 } else if (Cst > NVTBits) {
4123 Lo = DAG.getNode(ISD::SRA, NVT, InH,
4124 DAG.getConstant(Cst-NVTBits, ShTy));
4125 Hi = DAG.getNode(ISD::SRA, NVT, InH,
4126 DAG.getConstant(NVTBits-1, ShTy));
4127 } else if (Cst == NVTBits) {
4129 Hi = DAG.getNode(ISD::SRA, NVT, InH,
4130 DAG.getConstant(NVTBits-1, ShTy));
4132 Lo = DAG.getNode(ISD::OR, NVT,
4133 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
4134 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
4135 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
4141 // Okay, the shift amount isn't constant. However, if we can tell that it is
4142 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
4143 uint64_t Mask = NVTBits, KnownZero, KnownOne;
4144 TLI.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
4146 // If we know that the high bit of the shift amount is one, then we can do
4147 // this as a couple of simple shifts.
4148 if (KnownOne & Mask) {
4149 // Mask out the high bit, which we know is set.
4150 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
4151 DAG.getConstant(NVTBits-1, Amt.getValueType()));
4153 // Expand the incoming operand to be shifted, so that we have its parts
4155 ExpandOp(Op, InL, InH);
4158 Lo = DAG.getConstant(0, NVT); // Low part is zero.
4159 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
4162 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
4163 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
4166 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
4167 DAG.getConstant(NVTBits-1, Amt.getValueType()));
4168 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
4173 // If we know that the high bit of the shift amount is zero, then we can do
4174 // this as a couple of simple shifts.
4175 if (KnownZero & Mask) {
4177 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
4178 DAG.getConstant(NVTBits, Amt.getValueType()),
4181 // Expand the incoming operand to be shifted, so that we have its parts
4183 ExpandOp(Op, InL, InH);
4186 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
4187 Hi = DAG.getNode(ISD::OR, NVT,
4188 DAG.getNode(ISD::SHL, NVT, InH, Amt),
4189 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
4192 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
4193 Lo = DAG.getNode(ISD::OR, NVT,
4194 DAG.getNode(ISD::SRL, NVT, InL, Amt),
4195 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
4198 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
4199 Lo = DAG.getNode(ISD::OR, NVT,
4200 DAG.getNode(ISD::SRL, NVT, InL, Amt),
4201 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
4210 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
4211 // does not fit into a register, return the lo part and set the hi part to the
4212 // by-reg argument. If it does fit into a single register, return the result
4213 // and leave the Hi part unset.
4214 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
4215 bool isSigned, SDOperand &Hi) {
4216 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
4217 // The input chain to this libcall is the entry node of the function.
4218 // Legalizing the call will automatically add the previous call to the
4220 SDOperand InChain = DAG.getEntryNode();
4222 TargetLowering::ArgListTy Args;
4223 TargetLowering::ArgListEntry Entry;
4224 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
4225 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
4226 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
4227 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
4228 Entry.isSExt = isSigned;
4229 Args.push_back(Entry);
4231 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
4233 // Splice the libcall in wherever FindInputOutputChains tells us to.
4234 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
4235 std::pair<SDOperand,SDOperand> CallInfo =
4236 TLI.LowerCallTo(InChain, RetTy, isSigned, false, CallingConv::C, false,
4239 // Legalize the call sequence, starting with the chain. This will advance
4240 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
4241 // was added by LowerCallTo (guaranteeing proper serialization of calls).
4242 LegalizeOp(CallInfo.second);
4244 switch (getTypeAction(CallInfo.first.getValueType())) {
4245 default: assert(0 && "Unknown thing");
4247 Result = CallInfo.first;
4250 ExpandOp(CallInfo.first, Result, Hi);
4257 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the
4258 /// destination type is legal.
4259 SDOperand SelectionDAGLegalize::
4260 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
4261 assert(isTypeLegal(DestTy) && "Destination type is not legal!");
4262 assert(getTypeAction(Source.getValueType()) == Expand &&
4263 "This is not an expansion!");
4264 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
4267 assert(Source.getValueType() == MVT::i64 &&
4268 "This only works for 64-bit -> FP");
4269 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
4270 // incoming integer is set. To handle this, we dynamically test to see if
4271 // it is set, and, if so, add a fudge factor.
4273 ExpandOp(Source, Lo, Hi);
4275 // If this is unsigned, and not supported, first perform the conversion to
4276 // signed, then adjust the result if the sign bit is set.
4277 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
4278 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
4280 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
4281 DAG.getConstant(0, Hi.getValueType()),
4283 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
4284 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
4285 SignSet, Four, Zero);
4286 uint64_t FF = 0x5f800000ULL;
4287 if (TLI.isLittleEndian()) FF <<= 32;
4288 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
4290 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
4291 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
4292 SDOperand FudgeInReg;
4293 if (DestTy == MVT::f32)
4294 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
4296 assert(DestTy == MVT::f64 && "Unexpected conversion");
4297 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
4298 CPIdx, NULL, 0, MVT::f32);
4300 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
4303 // Check to see if the target has a custom way to lower this. If so, use it.
4304 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
4305 default: assert(0 && "This action not implemented for this operation!");
4306 case TargetLowering::Legal:
4307 case TargetLowering::Expand:
4308 break; // This case is handled below.
4309 case TargetLowering::Custom: {
4310 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
4313 return LegalizeOp(NV);
4314 break; // The target decided this was legal after all
4318 // Expand the source, then glue it back together for the call. We must expand
4319 // the source in case it is shared (this pass of legalize must traverse it).
4320 SDOperand SrcLo, SrcHi;
4321 ExpandOp(Source, SrcLo, SrcHi);
4322 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
4325 if (DestTy == MVT::f32)
4326 LC = RTLIB::SINTTOFP_I64_F32;
4328 assert(DestTy == MVT::f64 && "Unknown fp value type!");
4329 LC = RTLIB::SINTTOFP_I64_F64;
4332 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
4333 SDOperand UnusedHiPart;
4334 return ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned,
4338 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
4339 /// INT_TO_FP operation of the specified operand when the target requests that
4340 /// we expand it. At this point, we know that the result and operand types are
4341 /// legal for the target.
4342 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
4344 MVT::ValueType DestVT) {
4345 if (Op0.getValueType() == MVT::i32) {
4346 // simple 32-bit [signed|unsigned] integer to float/double expansion
4348 // get the stack frame index of a 8 byte buffer, pessimistically aligned
4349 MachineFunction &MF = DAG.getMachineFunction();
4350 const Type *F64Type = MVT::getTypeForValueType(MVT::f64);
4351 unsigned StackAlign =
4352 (unsigned)TLI.getTargetData()->getPrefTypeAlignment(F64Type);
4353 int SSFI = MF.getFrameInfo()->CreateStackObject(8, StackAlign);
4354 // get address of 8 byte buffer
4355 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
4356 // word offset constant for Hi/Lo address computation
4357 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
4358 // set up Hi and Lo (into buffer) address based on endian
4359 SDOperand Hi = StackSlot;
4360 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
4361 if (TLI.isLittleEndian())
4364 // if signed map to unsigned space
4365 SDOperand Op0Mapped;
4367 // constant used to invert sign bit (signed to unsigned mapping)
4368 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
4369 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
4373 // store the lo of the constructed double - based on integer input
4374 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(),
4375 Op0Mapped, Lo, NULL, 0);
4376 // initial hi portion of constructed double
4377 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
4378 // store the hi of the constructed double - biased exponent
4379 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
4380 // load the constructed double
4381 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
4382 // FP constant to bias correct the final result
4383 SDOperand Bias = DAG.getConstantFP(isSigned ?
4384 BitsToDouble(0x4330000080000000ULL)
4385 : BitsToDouble(0x4330000000000000ULL),
4387 // subtract the bias
4388 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
4391 // handle final rounding
4392 if (DestVT == MVT::f64) {
4396 // if f32 then cast to f32
4397 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub);
4401 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
4402 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
4404 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
4405 DAG.getConstant(0, Op0.getValueType()),
4407 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
4408 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
4409 SignSet, Four, Zero);
4411 // If the sign bit of the integer is set, the large number will be treated
4412 // as a negative number. To counteract this, the dynamic code adds an
4413 // offset depending on the data type.
4415 switch (Op0.getValueType()) {
4416 default: assert(0 && "Unsupported integer type!");
4417 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
4418 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
4419 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
4420 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
4422 if (TLI.isLittleEndian()) FF <<= 32;
4423 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
4425 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
4426 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
4427 SDOperand FudgeInReg;
4428 if (DestVT == MVT::f32)
4429 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
4431 assert(DestVT == MVT::f64 && "Unexpected conversion");
4432 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64,
4433 DAG.getEntryNode(), CPIdx,
4434 NULL, 0, MVT::f32));
4437 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
4440 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
4441 /// *INT_TO_FP operation of the specified operand when the target requests that
4442 /// we promote it. At this point, we know that the result and operand types are
4443 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
4444 /// operation that takes a larger input.
4445 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
4446 MVT::ValueType DestVT,
4448 // First step, figure out the appropriate *INT_TO_FP operation to use.
4449 MVT::ValueType NewInTy = LegalOp.getValueType();
4451 unsigned OpToUse = 0;
4453 // Scan for the appropriate larger type to use.
4455 NewInTy = (MVT::ValueType)(NewInTy+1);
4456 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
4458 // If the target supports SINT_TO_FP of this type, use it.
4459 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
4461 case TargetLowering::Legal:
4462 if (!TLI.isTypeLegal(NewInTy))
4463 break; // Can't use this datatype.
4465 case TargetLowering::Custom:
4466 OpToUse = ISD::SINT_TO_FP;
4470 if (isSigned) continue;
4472 // If the target supports UINT_TO_FP of this type, use it.
4473 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
4475 case TargetLowering::Legal:
4476 if (!TLI.isTypeLegal(NewInTy))
4477 break; // Can't use this datatype.
4479 case TargetLowering::Custom:
4480 OpToUse = ISD::UINT_TO_FP;
4485 // Otherwise, try a larger type.
4488 // Okay, we found the operation and type to use. Zero extend our input to the
4489 // desired type then run the operation on it.
4490 return DAG.getNode(OpToUse, DestVT,
4491 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
4495 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
4496 /// FP_TO_*INT operation of the specified operand when the target requests that
4497 /// we promote it. At this point, we know that the result and operand types are
4498 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
4499 /// operation that returns a larger result.
4500 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
4501 MVT::ValueType DestVT,
4503 // First step, figure out the appropriate FP_TO*INT operation to use.
4504 MVT::ValueType NewOutTy = DestVT;
4506 unsigned OpToUse = 0;
4508 // Scan for the appropriate larger type to use.
4510 NewOutTy = (MVT::ValueType)(NewOutTy+1);
4511 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
4513 // If the target supports FP_TO_SINT returning this type, use it.
4514 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
4516 case TargetLowering::Legal:
4517 if (!TLI.isTypeLegal(NewOutTy))
4518 break; // Can't use this datatype.
4520 case TargetLowering::Custom:
4521 OpToUse = ISD::FP_TO_SINT;
4526 // If the target supports FP_TO_UINT of this type, use it.
4527 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
4529 case TargetLowering::Legal:
4530 if (!TLI.isTypeLegal(NewOutTy))
4531 break; // Can't use this datatype.
4533 case TargetLowering::Custom:
4534 OpToUse = ISD::FP_TO_UINT;
4539 // Otherwise, try a larger type.
4542 // Okay, we found the operation and type to use. Truncate the result of the
4543 // extended FP_TO_*INT operation to the desired size.
4544 return DAG.getNode(ISD::TRUNCATE, DestVT,
4545 DAG.getNode(OpToUse, NewOutTy, LegalOp));
4548 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
4550 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
4551 MVT::ValueType VT = Op.getValueType();
4552 MVT::ValueType SHVT = TLI.getShiftAmountTy();
4553 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
4555 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
4557 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4558 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4559 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
4561 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4562 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4563 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4564 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4565 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
4566 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
4567 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4568 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4569 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4571 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
4572 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
4573 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4574 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4575 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4576 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4577 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
4578 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
4579 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
4580 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
4581 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
4582 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
4583 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
4584 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
4585 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
4586 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
4587 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4588 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4589 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
4590 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4591 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
4595 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
4597 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
4599 default: assert(0 && "Cannot expand this yet!");
4601 static const uint64_t mask[6] = {
4602 0x5555555555555555ULL, 0x3333333333333333ULL,
4603 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
4604 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
4606 MVT::ValueType VT = Op.getValueType();
4607 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4608 unsigned len = getSizeInBits(VT);
4609 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4610 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
4611 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
4612 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4613 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
4614 DAG.getNode(ISD::AND, VT,
4615 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
4620 // for now, we do this:
4621 // x = x | (x >> 1);
4622 // x = x | (x >> 2);
4624 // x = x | (x >>16);
4625 // x = x | (x >>32); // for 64-bit input
4626 // return popcount(~x);
4628 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
4629 MVT::ValueType VT = Op.getValueType();
4630 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4631 unsigned len = getSizeInBits(VT);
4632 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4633 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4634 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
4636 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
4637 return DAG.getNode(ISD::CTPOP, VT, Op);
4640 // for now, we use: { return popcount(~x & (x - 1)); }
4641 // unless the target has ctlz but not ctpop, in which case we use:
4642 // { return 32 - nlz(~x & (x-1)); }
4643 // see also http://www.hackersdelight.org/HDcode/ntz.cc
4644 MVT::ValueType VT = Op.getValueType();
4645 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
4646 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
4647 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
4648 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
4649 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
4650 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
4651 TLI.isOperationLegal(ISD::CTLZ, VT))
4652 return DAG.getNode(ISD::SUB, VT,
4653 DAG.getConstant(getSizeInBits(VT), VT),
4654 DAG.getNode(ISD::CTLZ, VT, Tmp3));
4655 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
4660 /// ExpandOp - Expand the specified SDOperand into its two component pieces
4661 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
4662 /// LegalizeNodes map is filled in for any results that are not expanded, the
4663 /// ExpandedNodes map is filled in for any results that are expanded, and the
4664 /// Lo/Hi values are returned.
4665 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
4666 MVT::ValueType VT = Op.getValueType();
4667 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4668 SDNode *Node = Op.Val;
4669 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
4670 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) ||
4671 VT == MVT::Vector) &&
4672 "Cannot expand to FP value or to larger int value!");
4674 // See if we already expanded it.
4675 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
4676 = ExpandedNodes.find(Op);
4677 if (I != ExpandedNodes.end()) {
4678 Lo = I->second.first;
4679 Hi = I->second.second;
4683 switch (Node->getOpcode()) {
4684 case ISD::CopyFromReg:
4685 assert(0 && "CopyFromReg must be legal!");
4688 cerr << "NODE: "; Node->dump(); cerr << "\n";
4690 assert(0 && "Do not know how to expand this operator!");
4693 NVT = TLI.getTypeToExpandTo(VT);
4694 Lo = DAG.getNode(ISD::UNDEF, NVT);
4695 Hi = DAG.getNode(ISD::UNDEF, NVT);
4697 case ISD::Constant: {
4698 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
4699 Lo = DAG.getConstant(Cst, NVT);
4700 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
4703 case ISD::ConstantFP: {
4704 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
4705 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
4706 if (getTypeAction(Lo.getValueType()) == Expand)
4707 ExpandOp(Lo, Lo, Hi);
4710 case ISD::BUILD_PAIR:
4711 // Return the operands.
4712 Lo = Node->getOperand(0);
4713 Hi = Node->getOperand(1);
4716 case ISD::SIGN_EXTEND_INREG:
4717 ExpandOp(Node->getOperand(0), Lo, Hi);
4718 // sext_inreg the low part if needed.
4719 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
4721 // The high part gets the sign extension from the lo-part. This handles
4722 // things like sextinreg V:i64 from i8.
4723 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4724 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
4725 TLI.getShiftAmountTy()));
4729 ExpandOp(Node->getOperand(0), Lo, Hi);
4730 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
4731 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
4737 ExpandOp(Node->getOperand(0), Lo, Hi);
4738 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
4739 DAG.getNode(ISD::CTPOP, NVT, Lo),
4740 DAG.getNode(ISD::CTPOP, NVT, Hi));
4741 Hi = DAG.getConstant(0, NVT);
4745 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
4746 ExpandOp(Node->getOperand(0), Lo, Hi);
4747 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
4748 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
4749 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
4751 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
4752 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
4754 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
4755 Hi = DAG.getConstant(0, NVT);
4760 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
4761 ExpandOp(Node->getOperand(0), Lo, Hi);
4762 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
4763 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
4764 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
4766 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
4767 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
4769 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
4770 Hi = DAG.getConstant(0, NVT);
4775 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
4776 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
4777 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
4778 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
4780 // Remember that we legalized the chain.
4781 Hi = LegalizeOp(Hi);
4782 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
4783 if (!TLI.isLittleEndian())
4789 LoadSDNode *LD = cast<LoadSDNode>(Node);
4790 SDOperand Ch = LD->getChain(); // Legalize the chain.
4791 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer.
4792 ISD::LoadExtType ExtType = LD->getExtensionType();
4794 if (ExtType == ISD::NON_EXTLOAD) {
4795 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),LD->getSrcValueOffset());
4796 if (VT == MVT::f32 || VT == MVT::f64) {
4797 // f32->i32 or f64->i64 one to one expansion.
4798 // Remember that we legalized the chain.
4799 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
4800 // Recursively expand the new load.
4801 if (getTypeAction(NVT) == Expand)
4802 ExpandOp(Lo, Lo, Hi);
4806 // Increment the pointer to the other half.
4807 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
4808 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
4809 getIntPtrConstant(IncrementSize));
4810 // FIXME: This creates a bogus srcvalue!
4811 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),LD->getSrcValueOffset());
4813 // Build a factor node to remember that this load is independent of the
4815 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
4818 // Remember that we legalized the chain.
4819 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
4820 if (!TLI.isLittleEndian())
4823 MVT::ValueType EVT = LD->getLoadedVT();
4825 if (VT == MVT::f64 && EVT == MVT::f32) {
4826 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
4827 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(),
4828 LD->getSrcValueOffset());
4829 // Remember that we legalized the chain.
4830 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1)));
4831 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
4836 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),
4837 LD->getSrcValueOffset());
4839 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(),
4840 LD->getSrcValueOffset(), EVT);
4842 // Remember that we legalized the chain.
4843 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
4845 if (ExtType == ISD::SEXTLOAD) {
4846 // The high part is obtained by SRA'ing all but one of the bits of the
4848 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
4849 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4850 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
4851 } else if (ExtType == ISD::ZEXTLOAD) {
4852 // The high part is just a zero.
4853 Hi = DAG.getConstant(0, NVT);
4854 } else /* if (ExtType == ISD::EXTLOAD) */ {
4855 // The high part is undefined.
4856 Hi = DAG.getNode(ISD::UNDEF, NVT);
4863 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
4864 SDOperand LL, LH, RL, RH;
4865 ExpandOp(Node->getOperand(0), LL, LH);
4866 ExpandOp(Node->getOperand(1), RL, RH);
4867 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
4868 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
4872 SDOperand LL, LH, RL, RH;
4873 ExpandOp(Node->getOperand(1), LL, LH);
4874 ExpandOp(Node->getOperand(2), RL, RH);
4875 if (getTypeAction(NVT) == Expand)
4876 NVT = TLI.getTypeToExpandTo(NVT);
4877 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
4879 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
4882 case ISD::SELECT_CC: {
4883 SDOperand TL, TH, FL, FH;
4884 ExpandOp(Node->getOperand(2), TL, TH);
4885 ExpandOp(Node->getOperand(3), FL, FH);
4886 if (getTypeAction(NVT) == Expand)
4887 NVT = TLI.getTypeToExpandTo(NVT);
4888 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4889 Node->getOperand(1), TL, FL, Node->getOperand(4));
4891 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4892 Node->getOperand(1), TH, FH, Node->getOperand(4));
4895 case ISD::ANY_EXTEND:
4896 // The low part is any extension of the input (which degenerates to a copy).
4897 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
4898 // The high part is undefined.
4899 Hi = DAG.getNode(ISD::UNDEF, NVT);
4901 case ISD::SIGN_EXTEND: {
4902 // The low part is just a sign extension of the input (which degenerates to
4904 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
4906 // The high part is obtained by SRA'ing all but one of the bits of the lo
4908 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
4909 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4910 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
4913 case ISD::ZERO_EXTEND:
4914 // The low part is just a zero extension of the input (which degenerates to
4916 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4918 // The high part is just a zero.
4919 Hi = DAG.getConstant(0, NVT);
4922 case ISD::TRUNCATE: {
4923 // The input value must be larger than this value. Expand *it*.
4925 ExpandOp(Node->getOperand(0), NewLo, Hi);
4927 // The low part is now either the right size, or it is closer. If not the
4928 // right size, make an illegal truncate so we recursively expand it.
4929 if (NewLo.getValueType() != Node->getValueType(0))
4930 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
4931 ExpandOp(NewLo, Lo, Hi);
4935 case ISD::BIT_CONVERT: {
4937 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
4938 // If the target wants to, allow it to lower this itself.
4939 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4940 case Expand: assert(0 && "cannot expand FP!");
4941 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
4942 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
4944 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
4947 // f32 / f64 must be expanded to i32 / i64.
4948 if (VT == MVT::f32 || VT == MVT::f64) {
4949 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
4950 if (getTypeAction(NVT) == Expand)
4951 ExpandOp(Lo, Lo, Hi);
4955 // If source operand will be expanded to the same type as VT, i.e.
4956 // i64 <- f64, i32 <- f32, expand the source operand instead.
4957 MVT::ValueType VT0 = Node->getOperand(0).getValueType();
4958 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
4959 ExpandOp(Node->getOperand(0), Lo, Hi);
4963 // Turn this into a load/store pair by default.
4965 Tmp = ExpandBIT_CONVERT(VT, Node->getOperand(0));
4967 ExpandOp(Tmp, Lo, Hi);
4971 case ISD::READCYCLECOUNTER:
4972 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
4973 TargetLowering::Custom &&
4974 "Must custom expand ReadCycleCounter");
4975 Lo = TLI.LowerOperation(Op, DAG);
4976 assert(Lo.Val && "Node must be custom expanded!");
4977 Hi = Lo.getValue(1);
4978 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
4979 LegalizeOp(Lo.getValue(2)));
4982 // These operators cannot be expanded directly, emit them as calls to
4983 // library functions.
4984 case ISD::FP_TO_SINT: {
4985 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
4987 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4988 case Expand: assert(0 && "cannot expand FP!");
4989 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
4990 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
4993 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
4995 // Now that the custom expander is done, expand the result, which is still
4998 ExpandOp(Op, Lo, Hi);
5004 if (Node->getOperand(0).getValueType() == MVT::f32)
5005 LC = RTLIB::FPTOSINT_F32_I64;
5007 LC = RTLIB::FPTOSINT_F64_I64;
5008 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
5009 false/*sign irrelevant*/, Hi);
5013 case ISD::FP_TO_UINT: {
5014 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
5016 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5017 case Expand: assert(0 && "cannot expand FP!");
5018 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
5019 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
5022 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
5024 // Now that the custom expander is done, expand the result.
5026 ExpandOp(Op, Lo, Hi);
5032 if (Node->getOperand(0).getValueType() == MVT::f32)
5033 LC = RTLIB::FPTOUINT_F32_I64;
5035 LC = RTLIB::FPTOUINT_F64_I64;
5036 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
5037 false/*sign irrelevant*/, Hi);
5042 // If the target wants custom lowering, do so.
5043 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5044 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
5045 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
5046 Op = TLI.LowerOperation(Op, DAG);
5048 // Now that the custom expander is done, expand the result, which is
5050 ExpandOp(Op, Lo, Hi);
5055 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
5056 // this X << 1 as X+X.
5057 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
5058 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
5059 TLI.isOperationLegal(ISD::ADDE, NVT)) {
5060 SDOperand LoOps[2], HiOps[3];
5061 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
5062 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
5063 LoOps[1] = LoOps[0];
5064 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5066 HiOps[1] = HiOps[0];
5067 HiOps[2] = Lo.getValue(1);
5068 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5073 // If we can emit an efficient shift operation, do so now.
5074 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
5077 // If this target supports SHL_PARTS, use it.
5078 TargetLowering::LegalizeAction Action =
5079 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
5080 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5081 Action == TargetLowering::Custom) {
5082 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5086 // Otherwise, emit a libcall.
5087 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SHL_I64), Node,
5088 false/*left shift=unsigned*/, Hi);
5093 // If the target wants custom lowering, do so.
5094 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5095 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
5096 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
5097 Op = TLI.LowerOperation(Op, DAG);
5099 // Now that the custom expander is done, expand the result, which is
5101 ExpandOp(Op, Lo, Hi);
5106 // If we can emit an efficient shift operation, do so now.
5107 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
5110 // If this target supports SRA_PARTS, use it.
5111 TargetLowering::LegalizeAction Action =
5112 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
5113 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5114 Action == TargetLowering::Custom) {
5115 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5119 // Otherwise, emit a libcall.
5120 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRA_I64), Node,
5121 true/*ashr is signed*/, Hi);
5126 // If the target wants custom lowering, do so.
5127 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5128 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
5129 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
5130 Op = TLI.LowerOperation(Op, DAG);
5132 // Now that the custom expander is done, expand the result, which is
5134 ExpandOp(Op, Lo, Hi);
5139 // If we can emit an efficient shift operation, do so now.
5140 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
5143 // If this target supports SRL_PARTS, use it.
5144 TargetLowering::LegalizeAction Action =
5145 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
5146 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5147 Action == TargetLowering::Custom) {
5148 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5152 // Otherwise, emit a libcall.
5153 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), Node,
5154 false/*lshr is unsigned*/, Hi);
5160 // If the target wants to custom expand this, let them.
5161 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
5162 TargetLowering::Custom) {
5163 Op = TLI.LowerOperation(Op, DAG);
5165 ExpandOp(Op, Lo, Hi);
5170 // Expand the subcomponents.
5171 SDOperand LHSL, LHSH, RHSL, RHSH;
5172 ExpandOp(Node->getOperand(0), LHSL, LHSH);
5173 ExpandOp(Node->getOperand(1), RHSL, RHSH);
5174 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
5175 SDOperand LoOps[2], HiOps[3];
5180 if (Node->getOpcode() == ISD::ADD) {
5181 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5182 HiOps[2] = Lo.getValue(1);
5183 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5185 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
5186 HiOps[2] = Lo.getValue(1);
5187 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
5192 // If the target wants to custom expand this, let them.
5193 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
5194 SDOperand New = TLI.LowerOperation(Op, DAG);
5196 ExpandOp(New, Lo, Hi);
5201 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
5202 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
5203 if (HasMULHS || HasMULHU) {
5204 SDOperand LL, LH, RL, RH;
5205 ExpandOp(Node->getOperand(0), LL, LH);
5206 ExpandOp(Node->getOperand(1), RL, RH);
5207 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1;
5208 // FIXME: Move this to the dag combiner.
5209 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp
5210 // extended the sign bit of the low half through the upper half, and if so
5211 // emit a MULHS instead of the alternate sequence that is valid for any
5212 // i64 x i64 multiply.
5214 // is RH an extension of the sign bit of RL?
5215 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL &&
5216 RH.getOperand(1).getOpcode() == ISD::Constant &&
5217 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH &&
5218 // is LH an extension of the sign bit of LL?
5219 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL &&
5220 LH.getOperand(1).getOpcode() == ISD::Constant &&
5221 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) {
5223 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
5225 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
5227 } else if (HasMULHU) {
5229 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
5232 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
5233 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
5234 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
5235 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
5236 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
5241 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), Node,
5242 false/*sign irrelevant*/, Hi);
5246 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SDIV_I64), Node, true, Hi);
5249 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UDIV_I64), Node, true, Hi);
5252 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SREM_I64), Node, true, Hi);
5255 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UREM_I64), Node, true, Hi);
5259 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5260 ? RTLIB::ADD_F32 : RTLIB::ADD_F64),
5264 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5265 ? RTLIB::SUB_F32 : RTLIB::SUB_F64),
5269 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5270 ? RTLIB::MUL_F32 : RTLIB::MUL_F64),
5274 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5275 ? RTLIB::DIV_F32 : RTLIB::DIV_F64),
5278 case ISD::FP_EXTEND:
5279 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPEXT_F32_F64), Node, true,Hi);
5282 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi);
5287 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
5288 switch(Node->getOpcode()) {
5290 LC = (VT == MVT::f32) ? RTLIB::SQRT_F32 : RTLIB::SQRT_F64;
5293 LC = (VT == MVT::f32) ? RTLIB::SIN_F32 : RTLIB::SIN_F64;
5296 LC = (VT == MVT::f32) ? RTLIB::COS_F32 : RTLIB::COS_F64;
5298 default: assert(0 && "Unreachable!");
5300 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false, Hi);
5304 SDOperand Mask = (VT == MVT::f64)
5305 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
5306 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
5307 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
5308 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
5309 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
5310 if (getTypeAction(NVT) == Expand)
5311 ExpandOp(Lo, Lo, Hi);
5315 SDOperand Mask = (VT == MVT::f64)
5316 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
5317 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
5318 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
5319 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
5320 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
5321 if (getTypeAction(NVT) == Expand)
5322 ExpandOp(Lo, Lo, Hi);
5325 case ISD::FCOPYSIGN: {
5326 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
5327 if (getTypeAction(NVT) == Expand)
5328 ExpandOp(Lo, Lo, Hi);
5331 case ISD::SINT_TO_FP:
5332 case ISD::UINT_TO_FP: {
5333 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
5334 MVT::ValueType SrcVT = Node->getOperand(0).getValueType();
5336 if (Node->getOperand(0).getValueType() == MVT::i64) {
5338 LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32;
5340 LC = isSigned ? RTLIB::SINTTOFP_I64_F64 : RTLIB::UINTTOFP_I64_F64;
5343 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32;
5345 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64;
5348 // Promote the operand if needed.
5349 if (getTypeAction(SrcVT) == Promote) {
5350 SDOperand Tmp = PromoteOp(Node->getOperand(0));
5352 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
5353 DAG.getValueType(SrcVT))
5354 : DAG.getZeroExtendInReg(Tmp, SrcVT);
5355 Node = DAG.UpdateNodeOperands(Op, Tmp).Val;
5357 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Hi);
5362 // Make sure the resultant values have been legalized themselves, unless this
5363 // is a type that requires multi-step expansion.
5364 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
5365 Lo = LegalizeOp(Lo);
5367 // Don't legalize the high part if it is expanded to a single node.
5368 Hi = LegalizeOp(Hi);
5371 // Remember in a map if the values will be reused later.
5372 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi)));
5373 assert(isNew && "Value already expanded?!?");
5376 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into
5377 /// two smaller values of MVT::Vector type.
5378 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
5380 assert(Op.getValueType() == MVT::Vector && "Cannot split non-vector type!");
5381 SDNode *Node = Op.Val;
5382 unsigned NumElements = cast<ConstantSDNode>(*(Node->op_end()-2))->getValue();
5383 assert(NumElements > 1 && "Cannot split a single element vector!");
5384 unsigned NewNumElts = NumElements/2;
5385 SDOperand NewNumEltsNode = DAG.getConstant(NewNumElts, MVT::i32);
5386 SDOperand TypeNode = *(Node->op_end()-1);
5388 // See if we already split it.
5389 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
5390 = SplitNodes.find(Op);
5391 if (I != SplitNodes.end()) {
5392 Lo = I->second.first;
5393 Hi = I->second.second;
5397 switch (Node->getOpcode()) {
5402 assert(0 && "Unhandled operation in SplitVectorOp!");
5403 case ISD::VBUILD_VECTOR: {
5404 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
5405 Node->op_begin()+NewNumElts);
5406 LoOps.push_back(NewNumEltsNode);
5407 LoOps.push_back(TypeNode);
5408 Lo = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &LoOps[0], LoOps.size());
5410 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts,
5412 HiOps.push_back(NewNumEltsNode);
5413 HiOps.push_back(TypeNode);
5414 Hi = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &HiOps[0], HiOps.size());
5425 SDOperand LL, LH, RL, RH;
5426 SplitVectorOp(Node->getOperand(0), LL, LH);
5427 SplitVectorOp(Node->getOperand(1), RL, RH);
5429 Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL,
5430 NewNumEltsNode, TypeNode);
5431 Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH,
5432 NewNumEltsNode, TypeNode);
5436 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
5437 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
5438 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT();
5440 Lo = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2));
5441 unsigned IncrementSize = NewNumElts * MVT::getSizeInBits(EVT)/8;
5442 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
5443 getIntPtrConstant(IncrementSize));
5444 // FIXME: This creates a bogus srcvalue!
5445 Hi = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2));
5447 // Build a factor node to remember that this load is independent of the
5449 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
5452 // Remember that we legalized the chain.
5453 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
5456 case ISD::VBIT_CONVERT: {
5457 // We know the result is a vector. The input may be either a vector or a
5459 if (Op.getOperand(0).getValueType() != MVT::Vector) {
5460 // Lower to a store/load. FIXME: this could be improved probably.
5461 SDOperand Ptr = CreateStackTemporary(Op.getOperand(0).getValueType());
5463 SDOperand St = DAG.getStore(DAG.getEntryNode(),
5464 Op.getOperand(0), Ptr, NULL, 0);
5465 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT();
5466 St = DAG.getVecLoad(NumElements, EVT, St, Ptr, DAG.getSrcValue(0));
5467 SplitVectorOp(St, Lo, Hi);
5469 // If the input is a vector type, we have to either scalarize it, pack it
5470 // or convert it based on whether the input vector type is legal.
5471 SDNode *InVal = Node->getOperand(0).Val;
5473 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
5474 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
5476 // If the input is from a single element vector, scalarize the vector,
5477 // then treat like a scalar.
5478 if (NumElems == 1) {
5479 SDOperand Scalar = PackVectorOp(Op.getOperand(0), EVT);
5480 Scalar = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Scalar,
5481 Op.getOperand(1), Op.getOperand(2));
5482 SplitVectorOp(Scalar, Lo, Hi);
5484 // Split the input vector.
5485 SplitVectorOp(Op.getOperand(0), Lo, Hi);
5487 // Convert each of the pieces now.
5488 Lo = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Lo,
5489 NewNumEltsNode, TypeNode);
5490 Hi = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Hi,
5491 NewNumEltsNode, TypeNode);
5498 // Remember in a map if the values will be reused later.
5500 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
5501 assert(isNew && "Value already expanded?!?");
5505 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the
5506 /// equivalent operation that returns a scalar (e.g. F32) or packed value
5507 /// (e.g. MVT::V4F32). When this is called, we know that PackedVT is the right
5508 /// type for the result.
5509 SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op,
5510 MVT::ValueType NewVT) {
5511 assert(Op.getValueType() == MVT::Vector && "Bad PackVectorOp invocation!");
5512 SDNode *Node = Op.Val;
5514 // See if we already packed it.
5515 std::map<SDOperand, SDOperand>::iterator I = PackedNodes.find(Op);
5516 if (I != PackedNodes.end()) return I->second;
5519 switch (Node->getOpcode()) {
5522 Node->dump(); cerr << "\n";
5524 assert(0 && "Unknown vector operation in PackVectorOp!");
5533 Result = DAG.getNode(getScalarizedOpcode(Node->getOpcode(), NewVT),
5535 PackVectorOp(Node->getOperand(0), NewVT),
5536 PackVectorOp(Node->getOperand(1), NewVT));
5539 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
5540 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
5542 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
5543 Result = DAG.getLoad(NewVT, Ch, Ptr, SV->getValue(), SV->getOffset());
5545 // Remember that we legalized the chain.
5546 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
5549 case ISD::VBUILD_VECTOR:
5550 if (Node->getOperand(0).getValueType() == NewVT) {
5551 // Returning a scalar?
5552 Result = Node->getOperand(0);
5554 // Returning a BUILD_VECTOR?
5556 // If all elements of the build_vector are undefs, return an undef.
5557 bool AllUndef = true;
5558 for (unsigned i = 0, e = Node->getNumOperands()-2; i != e; ++i)
5559 if (Node->getOperand(i).getOpcode() != ISD::UNDEF) {
5564 Result = DAG.getNode(ISD::UNDEF, NewVT);
5566 Result = DAG.getNode(ISD::BUILD_VECTOR, NewVT, Node->op_begin(),
5567 Node->getNumOperands()-2);
5571 case ISD::VINSERT_VECTOR_ELT:
5572 if (!MVT::isVector(NewVT)) {
5573 // Returning a scalar? Must be the inserted element.
5574 Result = Node->getOperand(1);
5576 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT,
5577 PackVectorOp(Node->getOperand(0), NewVT),
5578 Node->getOperand(1), Node->getOperand(2));
5581 case ISD::VVECTOR_SHUFFLE:
5582 if (!MVT::isVector(NewVT)) {
5583 // Returning a scalar? Figure out if it is the LHS or RHS and return it.
5584 SDOperand EltNum = Node->getOperand(2).getOperand(0);
5585 if (cast<ConstantSDNode>(EltNum)->getValue())
5586 Result = PackVectorOp(Node->getOperand(1), NewVT);
5588 Result = PackVectorOp(Node->getOperand(0), NewVT);
5590 // Otherwise, return a VECTOR_SHUFFLE node. First convert the index
5591 // vector from a VBUILD_VECTOR to a BUILD_VECTOR.
5592 std::vector<SDOperand> BuildVecIdx(Node->getOperand(2).Val->op_begin(),
5593 Node->getOperand(2).Val->op_end()-2);
5594 MVT::ValueType BVT = MVT::getIntVectorWithNumElements(BuildVecIdx.size());
5595 SDOperand BV = DAG.getNode(ISD::BUILD_VECTOR, BVT,
5596 Node->getOperand(2).Val->op_begin(),
5597 Node->getOperand(2).Val->getNumOperands()-2);
5599 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT,
5600 PackVectorOp(Node->getOperand(0), NewVT),
5601 PackVectorOp(Node->getOperand(1), NewVT), BV);
5604 case ISD::VBIT_CONVERT:
5605 if (Op.getOperand(0).getValueType() != MVT::Vector)
5606 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));
5608 // If the input is a vector type, we have to either scalarize it, pack it
5609 // or convert it based on whether the input vector type is legal.
5610 SDNode *InVal = Node->getOperand(0).Val;
5612 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
5613 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
5615 // Figure out if there is a Packed type corresponding to this Vector
5616 // type. If so, convert to the vector type.
5617 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
5618 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
5619 // Turn this into a bit convert of the packed input.
5620 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT,
5621 PackVectorOp(Node->getOperand(0), TVT));
5623 } else if (NumElems == 1) {
5624 // Turn this into a bit convert of the scalar input.
5625 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT,
5626 PackVectorOp(Node->getOperand(0), EVT));
5630 assert(0 && "Cast from unsupported vector type not implemented yet!");
5635 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
5636 PackVectorOp(Op.getOperand(1), NewVT),
5637 PackVectorOp(Op.getOperand(2), NewVT));
5641 if (TLI.isTypeLegal(NewVT))
5642 Result = LegalizeOp(Result);
5643 bool isNew = PackedNodes.insert(std::make_pair(Op, Result)).second;
5644 assert(isNew && "Value already packed?");
5649 // SelectionDAG::Legalize - This is the entry point for the file.
5651 void SelectionDAG::Legalize() {
5652 if (ViewLegalizeDAGs) viewGraph();
5654 /// run - This is the main entry point to this class.
5656 SelectionDAGLegalize(*this).LegalizeDAG();