1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/Target/TargetFrameInfo.h"
20 #include "llvm/Target/TargetLowering.h"
21 #include "llvm/Target/TargetData.h"
22 #include "llvm/Target/TargetMachine.h"
23 #include "llvm/Target/TargetOptions.h"
24 #include "llvm/CallingConv.h"
25 #include "llvm/Constants.h"
26 #include "llvm/DerivedTypes.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/Compiler.h"
29 #include "llvm/Support/MathExtras.h"
30 #include "llvm/ADT/DenseMap.h"
31 #include "llvm/ADT/SmallVector.h"
32 #include "llvm/ADT/SmallPtrSet.h"
38 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
39 cl::desc("Pop up a window to show dags before legalize"));
41 static const bool ViewLegalizeDAGs = 0;
44 //===----------------------------------------------------------------------===//
45 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
46 /// hacks on it until the target machine can handle it. This involves
47 /// eliminating value sizes the machine cannot handle (promoting small sizes to
48 /// large sizes or splitting up large values into small values) as well as
49 /// eliminating operations the machine cannot handle.
51 /// This code also does a small amount of optimization and recognition of idioms
52 /// as part of its processing. For example, if a target does not support a
53 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
54 /// will attempt merge setcc and brc instructions into brcc's.
57 class VISIBILITY_HIDDEN SelectionDAGLegalize {
61 // Libcall insertion helpers.
63 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
64 /// legalized. We use this to ensure that calls are properly serialized
65 /// against each other, including inserted libcalls.
66 SDOperand LastCALLSEQ_END;
68 /// IsLegalizingCall - This member is used *only* for purposes of providing
69 /// helpful assertions that a libcall isn't created while another call is
70 /// being legalized (which could lead to non-serialized call sequences).
71 bool IsLegalizingCall;
74 Legal, // The target natively supports this operation.
75 Promote, // This operation should be executed in a larger type.
76 Expand // Try to expand this to other ops, otherwise use a libcall.
79 /// ValueTypeActions - This is a bitvector that contains two bits for each
80 /// value type, where the two bits correspond to the LegalizeAction enum.
81 /// This can be queried with "getTypeAction(VT)".
82 TargetLowering::ValueTypeActionImpl ValueTypeActions;
84 /// LegalizedNodes - For nodes that are of legal width, and that have more
85 /// than one use, this map indicates what regularized operand to use. This
86 /// allows us to avoid legalizing the same thing more than once.
87 DenseMap<SDOperand, SDOperand> LegalizedNodes;
89 /// PromotedNodes - For nodes that are below legal width, and that have more
90 /// than one use, this map indicates what promoted value to use. This allows
91 /// us to avoid promoting the same thing more than once.
92 DenseMap<SDOperand, SDOperand> PromotedNodes;
94 /// ExpandedNodes - For nodes that need to be expanded this map indicates
95 /// which which operands are the expanded version of the input. This allows
96 /// us to avoid expanding the same node more than once.
97 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
99 /// SplitNodes - For vector nodes that need to be split, this map indicates
100 /// which which operands are the split version of the input. This allows us
101 /// to avoid splitting the same node more than once.
102 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
104 /// ScalarizedNodes - For nodes that need to be converted from vector types to
105 /// scalar types, this contains the mapping of ones we have already
106 /// processed to the result.
107 std::map<SDOperand, SDOperand> ScalarizedNodes;
109 void AddLegalizedOperand(SDOperand From, SDOperand To) {
110 LegalizedNodes.insert(std::make_pair(From, To));
111 // If someone requests legalization of the new node, return itself.
113 LegalizedNodes.insert(std::make_pair(To, To));
115 void AddPromotedOperand(SDOperand From, SDOperand To) {
116 bool isNew = PromotedNodes.insert(std::make_pair(From, To));
117 assert(isNew && "Got into the map somehow?");
118 // If someone requests legalization of the new node, return itself.
119 LegalizedNodes.insert(std::make_pair(To, To));
124 SelectionDAGLegalize(SelectionDAG &DAG);
126 /// getTypeAction - Return how we should legalize values of this type, either
127 /// it is already legal or we need to expand it into multiple registers of
128 /// smaller integer type, or we need to promote it to a larger type.
129 LegalizeAction getTypeAction(MVT::ValueType VT) const {
130 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
133 /// isTypeLegal - Return true if this type is legal on this target.
135 bool isTypeLegal(MVT::ValueType VT) const {
136 return getTypeAction(VT) == Legal;
142 /// HandleOp - Legalize, Promote, or Expand the specified operand as
143 /// appropriate for its type.
144 void HandleOp(SDOperand Op);
146 /// LegalizeOp - We know that the specified value has a legal type.
147 /// Recursively ensure that the operands have legal types, then return the
149 SDOperand LegalizeOp(SDOperand O);
151 /// UnrollVectorOp - We know that the given vector has a legal type, however
152 /// the operation it performs is not legal and is an operation that we have
153 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
154 /// operating on each element individually.
155 SDOperand UnrollVectorOp(SDOperand O);
157 /// PromoteOp - Given an operation that produces a value in an invalid type,
158 /// promote it to compute the value into a larger type. The produced value
159 /// will have the correct bits for the low portion of the register, but no
160 /// guarantee is made about the top bits: it may be zero, sign-extended, or
162 SDOperand PromoteOp(SDOperand O);
164 /// ExpandOp - Expand the specified SDOperand into its two component pieces
165 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
166 /// the LegalizeNodes map is filled in for any results that are not expanded,
167 /// the ExpandedNodes map is filled in for any results that are expanded, and
168 /// the Lo/Hi values are returned. This applies to integer types and Vector
170 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
172 /// SplitVectorOp - Given an operand of vector type, break it down into
173 /// two smaller values.
174 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
176 /// ScalarizeVectorOp - Given an operand of single-element vector type
177 /// (e.g. v1f32), convert it into the equivalent operation that returns a
178 /// scalar (e.g. f32) value.
179 SDOperand ScalarizeVectorOp(SDOperand O);
181 /// isShuffleLegal - Return true if a vector shuffle is legal with the
182 /// specified mask and type. Targets can specify exactly which masks they
183 /// support and the code generator is tasked with not creating illegal masks.
185 /// Note that this will also return true for shuffles that are promoted to a
188 /// If this is a legal shuffle, this method returns the (possibly promoted)
189 /// build_vector Mask. If it's not a legal shuffle, it returns null.
190 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
192 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
193 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
195 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
197 SDOperand ExpandLibCall(const char *Name, SDNode *Node, bool isSigned,
199 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
202 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp);
203 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
204 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
205 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
207 MVT::ValueType DestVT);
208 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
210 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
213 SDOperand ExpandBSWAP(SDOperand Op);
214 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
215 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
216 SDOperand &Lo, SDOperand &Hi);
217 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
218 SDOperand &Lo, SDOperand &Hi);
220 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op);
221 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
223 SDOperand getIntPtrConstant(uint64_t Val) {
224 return DAG.getConstant(Val, TLI.getPointerTy());
229 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
230 /// specified mask and type. Targets can specify exactly which masks they
231 /// support and the code generator is tasked with not creating illegal masks.
233 /// Note that this will also return true for shuffles that are promoted to a
235 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
236 SDOperand Mask) const {
237 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
239 case TargetLowering::Legal:
240 case TargetLowering::Custom:
242 case TargetLowering::Promote: {
243 // If this is promoted to a different type, convert the shuffle mask and
244 // ask if it is legal in the promoted type!
245 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
247 // If we changed # elements, change the shuffle mask.
248 unsigned NumEltsGrowth =
249 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
250 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
251 if (NumEltsGrowth > 1) {
252 // Renumber the elements.
253 SmallVector<SDOperand, 8> Ops;
254 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
255 SDOperand InOp = Mask.getOperand(i);
256 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
257 if (InOp.getOpcode() == ISD::UNDEF)
258 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
260 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
261 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
265 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
271 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
274 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
275 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
276 ValueTypeActions(TLI.getValueTypeActions()) {
277 assert(MVT::LAST_VALUETYPE <= 32 &&
278 "Too many value types for ValueTypeActions to hold!");
281 /// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order
282 /// contains all of a nodes operands before it contains the node.
283 static void ComputeTopDownOrdering(SelectionDAG &DAG,
284 SmallVector<SDNode*, 64> &Order) {
286 DenseMap<SDNode*, unsigned> Visited;
287 std::vector<SDNode*> Worklist;
288 Worklist.reserve(128);
290 // Compute ordering from all of the leaves in the graphs, those (like the
291 // entry node) that have no operands.
292 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
293 E = DAG.allnodes_end(); I != E; ++I) {
294 if (I->getNumOperands() == 0) {
296 Worklist.push_back(I);
300 while (!Worklist.empty()) {
301 SDNode *N = Worklist.back();
304 if (++Visited[N] != N->getNumOperands())
305 continue; // Haven't visited all operands yet
309 // Now that we have N in, add anything that uses it if all of their operands
311 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
313 Worklist.push_back(*UI);
316 assert(Order.size() == Visited.size() &&
318 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
319 "Error: DAG is cyclic!");
323 void SelectionDAGLegalize::LegalizeDAG() {
324 LastCALLSEQ_END = DAG.getEntryNode();
325 IsLegalizingCall = false;
327 // The legalize process is inherently a bottom-up recursive process (users
328 // legalize their uses before themselves). Given infinite stack space, we
329 // could just start legalizing on the root and traverse the whole graph. In
330 // practice however, this causes us to run out of stack space on large basic
331 // blocks. To avoid this problem, compute an ordering of the nodes where each
332 // node is only legalized after all of its operands are legalized.
333 SmallVector<SDNode*, 64> Order;
334 ComputeTopDownOrdering(DAG, Order);
336 for (unsigned i = 0, e = Order.size(); i != e; ++i)
337 HandleOp(SDOperand(Order[i], 0));
339 // Finally, it's possible the root changed. Get the new root.
340 SDOperand OldRoot = DAG.getRoot();
341 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
342 DAG.setRoot(LegalizedNodes[OldRoot]);
344 ExpandedNodes.clear();
345 LegalizedNodes.clear();
346 PromotedNodes.clear();
348 ScalarizedNodes.clear();
350 // Remove dead nodes now.
351 DAG.RemoveDeadNodes();
355 /// FindCallEndFromCallStart - Given a chained node that is part of a call
356 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
357 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
358 if (Node->getOpcode() == ISD::CALLSEQ_END)
360 if (Node->use_empty())
361 return 0; // No CallSeqEnd
363 // The chain is usually at the end.
364 SDOperand TheChain(Node, Node->getNumValues()-1);
365 if (TheChain.getValueType() != MVT::Other) {
366 // Sometimes it's at the beginning.
367 TheChain = SDOperand(Node, 0);
368 if (TheChain.getValueType() != MVT::Other) {
369 // Otherwise, hunt for it.
370 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
371 if (Node->getValueType(i) == MVT::Other) {
372 TheChain = SDOperand(Node, i);
376 // Otherwise, we walked into a node without a chain.
377 if (TheChain.getValueType() != MVT::Other)
382 for (SDNode::use_iterator UI = Node->use_begin(),
383 E = Node->use_end(); UI != E; ++UI) {
385 // Make sure to only follow users of our token chain.
387 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
388 if (User->getOperand(i) == TheChain)
389 if (SDNode *Result = FindCallEndFromCallStart(User))
395 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
396 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
397 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
398 assert(Node && "Didn't find callseq_start for a call??");
399 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
401 assert(Node->getOperand(0).getValueType() == MVT::Other &&
402 "Node doesn't have a token chain argument!");
403 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
406 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
407 /// see if any uses can reach Dest. If no dest operands can get to dest,
408 /// legalize them, legalize ourself, and return false, otherwise, return true.
410 /// Keep track of the nodes we fine that actually do lead to Dest in
411 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
413 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
414 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
415 if (N == Dest) return true; // N certainly leads to Dest :)
417 // If we've already processed this node and it does lead to Dest, there is no
418 // need to reprocess it.
419 if (NodesLeadingTo.count(N)) return true;
421 // If the first result of this node has been already legalized, then it cannot
423 switch (getTypeAction(N->getValueType(0))) {
425 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
428 if (PromotedNodes.count(SDOperand(N, 0))) return false;
431 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
435 // Okay, this node has not already been legalized. Check and legalize all
436 // operands. If none lead to Dest, then we can legalize this node.
437 bool OperandsLeadToDest = false;
438 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
439 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
440 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
442 if (OperandsLeadToDest) {
443 NodesLeadingTo.insert(N);
447 // Okay, this node looks safe, legalize it and return false.
448 HandleOp(SDOperand(N, 0));
452 /// HandleOp - Legalize, Promote, or Expand the specified operand as
453 /// appropriate for its type.
454 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
455 MVT::ValueType VT = Op.getValueType();
456 switch (getTypeAction(VT)) {
457 default: assert(0 && "Bad type action!");
458 case Legal: (void)LegalizeOp(Op); break;
459 case Promote: (void)PromoteOp(Op); break;
461 if (!MVT::isVector(VT)) {
462 // If this is an illegal scalar, expand it into its two component
465 if (Op.getOpcode() == ISD::TargetConstant)
466 break; // Allow illegal target nodes.
468 } else if (MVT::getVectorNumElements(VT) == 1) {
469 // If this is an illegal single element vector, convert it to a
471 (void)ScalarizeVectorOp(Op);
473 // Otherwise, this is an illegal multiple element vector.
474 // Split it in half and legalize both parts.
476 SplitVectorOp(Op, X, Y);
482 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
483 /// a load from the constant pool.
484 static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
485 SelectionDAG &DAG, TargetLowering &TLI) {
488 // If a FP immediate is precise when represented as a float and if the
489 // target can do an extending load from float to double, we put it into
490 // the constant pool as a float, even if it's is statically typed as a
492 MVT::ValueType VT = CFP->getValueType(0);
493 bool isDouble = VT == MVT::f64;
494 ConstantFP *LLVMC = ConstantFP::get(MVT::getTypeForValueType(VT),
497 if (VT!=MVT::f64 && VT!=MVT::f32)
498 assert(0 && "Invalid type expansion");
499 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt().getZExtValue(),
500 isDouble ? MVT::i64 : MVT::i32);
503 if (isDouble && CFP->isValueValidForType(MVT::f32, CFP->getValueAPF()) &&
504 // Only do this if the target has a native EXTLOAD instruction from f32.
505 // Do not try to be clever about long doubles (so far)
506 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) {
507 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC,Type::FloatTy));
512 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
514 return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
515 CPIdx, NULL, 0, MVT::f32);
517 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
522 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
525 SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT,
526 SelectionDAG &DAG, TargetLowering &TLI) {
527 MVT::ValueType VT = Node->getValueType(0);
528 MVT::ValueType SrcVT = Node->getOperand(1).getValueType();
529 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
530 "fcopysign expansion only supported for f32 and f64");
531 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
533 // First get the sign bit of second operand.
534 SDOperand Mask1 = (SrcVT == MVT::f64)
535 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
536 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
537 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
538 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
539 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
540 // Shift right or sign-extend it if the two operands have different types.
541 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT);
543 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
544 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
545 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
546 } else if (SizeDiff < 0)
547 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit);
549 // Clear the sign bit of first operand.
550 SDOperand Mask2 = (VT == MVT::f64)
551 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
552 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
553 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
554 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
555 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
557 // Or the value with the sign bit.
558 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
562 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
564 SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
565 TargetLowering &TLI) {
566 SDOperand Chain = ST->getChain();
567 SDOperand Ptr = ST->getBasePtr();
568 SDOperand Val = ST->getValue();
569 MVT::ValueType VT = Val.getValueType();
570 int Alignment = ST->getAlignment();
571 int SVOffset = ST->getSrcValueOffset();
572 if (MVT::isFloatingPoint(ST->getStoredVT())) {
573 // Expand to a bitconvert of the value to the integer type of the
574 // same size, then a (misaligned) int store.
575 MVT::ValueType intVT;
578 else if (VT==MVT::f32)
581 assert(0 && "Unaligned load of unsupported floating point type");
583 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val);
584 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(),
585 SVOffset, ST->isVolatile(), Alignment);
587 assert(MVT::isInteger(ST->getStoredVT()) &&
588 "Unaligned store of unknown type.");
589 // Get the half-size VT
590 MVT::ValueType NewStoredVT = ST->getStoredVT() - 1;
591 int NumBits = MVT::getSizeInBits(NewStoredVT);
592 int IncrementSize = NumBits / 8;
594 // Divide the stored value in two parts.
595 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
597 SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
599 // Store the two parts
600 SDOperand Store1, Store2;
601 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr,
602 ST->getSrcValue(), SVOffset, NewStoredVT,
603 ST->isVolatile(), Alignment);
604 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
605 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
606 Alignment = MinAlign(Alignment, IncrementSize);
607 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr,
608 ST->getSrcValue(), SVOffset + IncrementSize,
609 NewStoredVT, ST->isVolatile(), Alignment);
611 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2);
614 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
616 SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
617 TargetLowering &TLI) {
618 int SVOffset = LD->getSrcValueOffset();
619 SDOperand Chain = LD->getChain();
620 SDOperand Ptr = LD->getBasePtr();
621 MVT::ValueType VT = LD->getValueType(0);
622 MVT::ValueType LoadedVT = LD->getLoadedVT();
623 if (MVT::isFloatingPoint(VT) && !MVT::isVector(VT)) {
624 // Expand to a (misaligned) integer load of the same size,
625 // then bitconvert to floating point.
626 MVT::ValueType intVT;
627 if (LoadedVT == MVT::f64)
629 else if (LoadedVT == MVT::f32)
632 assert(0 && "Unaligned load of unsupported floating point type");
634 SDOperand newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(),
635 SVOffset, LD->isVolatile(),
637 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad);
639 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result);
641 SDOperand Ops[] = { Result, Chain };
642 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
645 assert((MVT::isInteger(LoadedVT) || MVT::isVector(LoadedVT)) &&
646 "Unaligned load of unsupported type.");
648 // Compute the new VT that is half the size of the old one. We either have an
649 // integer MVT or we have a vector MVT.
650 unsigned NumBits = MVT::getSizeInBits(LoadedVT);
651 MVT::ValueType NewLoadedVT;
652 if (!MVT::isVector(LoadedVT)) {
653 NewLoadedVT = MVT::getIntegerType(NumBits/2);
655 // FIXME: This is not right for <1 x anything> it is also not right for
656 // non-power-of-two vectors.
657 NewLoadedVT = MVT::getVectorType(MVT::getVectorElementType(LoadedVT),
658 MVT::getVectorNumElements(LoadedVT)/2);
662 unsigned Alignment = LD->getAlignment();
663 unsigned IncrementSize = NumBits / 8;
664 ISD::LoadExtType HiExtType = LD->getExtensionType();
666 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
667 if (HiExtType == ISD::NON_EXTLOAD)
668 HiExtType = ISD::ZEXTLOAD;
670 // Load the value in two parts
672 if (TLI.isLittleEndian()) {
673 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
674 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
675 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
676 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
677 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(),
678 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
679 MinAlign(Alignment, IncrementSize));
681 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset,
682 NewLoadedVT,LD->isVolatile(), Alignment);
683 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
684 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
685 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
686 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
687 MinAlign(Alignment, IncrementSize));
690 // aggregate the two parts
691 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
692 SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
693 Result = DAG.getNode(ISD::OR, VT, Result, Lo);
695 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
698 SDOperand Ops[] = { Result, TF };
699 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2);
702 /// UnrollVectorOp - We know that the given vector has a legal type, however
703 /// the operation it performs is not legal and is an operation that we have
704 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
705 /// operating on each element individually.
706 SDOperand SelectionDAGLegalize::UnrollVectorOp(SDOperand Op) {
707 MVT::ValueType VT = Op.getValueType();
708 assert(isTypeLegal(VT) &&
709 "Caller should expand or promote operands that are not legal!");
710 assert(Op.Val->getNumValues() == 1 &&
711 "Can't unroll a vector with multiple results!");
712 unsigned NE = MVT::getVectorNumElements(VT);
713 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
715 SmallVector<SDOperand, 8> Scalars;
716 SmallVector<SDOperand, 4> Operands(Op.getNumOperands());
717 for (unsigned i = 0; i != NE; ++i) {
718 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
719 SDOperand Operand = Op.getOperand(j);
720 MVT::ValueType OperandVT = Operand.getValueType();
721 if (MVT::isVector(OperandVT)) {
722 // A vector operand; extract a single element.
723 MVT::ValueType OperandEltVT = MVT::getVectorElementType(OperandVT);
724 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
727 DAG.getConstant(i, MVT::i32));
729 // A scalar operand; just use it as is.
730 Operands[j] = Operand;
733 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT,
734 &Operands[0], Operands.size()));
737 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size());
740 /// GetFPLibCall - Return the right libcall for the given floating point type.
741 static RTLIB::Libcall GetFPLibCall(MVT::ValueType VT,
742 RTLIB::Libcall Call_F32,
743 RTLIB::Libcall Call_F64,
744 RTLIB::Libcall Call_F80,
745 RTLIB::Libcall Call_PPCF128) {
747 VT == MVT::f32 ? Call_F32 :
748 VT == MVT::f64 ? Call_F64 :
749 VT == MVT::f80 ? Call_F80 :
750 VT == MVT::ppcf128 ? Call_PPCF128 :
751 RTLIB::UNKNOWN_LIBCALL;
754 /// LegalizeOp - We know that the specified value has a legal type, and
755 /// that its operands are legal. Now ensure that the operation itself
756 /// is legal, recursively ensuring that the operands' operations remain
758 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
759 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
762 assert(isTypeLegal(Op.getValueType()) &&
763 "Caller should expand or promote operands that are not legal!");
764 SDNode *Node = Op.Val;
766 // If this operation defines any values that cannot be represented in a
767 // register on this target, make sure to expand or promote them.
768 if (Node->getNumValues() > 1) {
769 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
770 if (getTypeAction(Node->getValueType(i)) != Legal) {
771 HandleOp(Op.getValue(i));
772 assert(LegalizedNodes.count(Op) &&
773 "Handling didn't add legal operands!");
774 return LegalizedNodes[Op];
778 // Note that LegalizeOp may be reentered even from single-use nodes, which
779 // means that we always must cache transformed nodes.
780 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
781 if (I != LegalizedNodes.end()) return I->second;
783 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
784 SDOperand Result = Op;
785 bool isCustom = false;
787 switch (Node->getOpcode()) {
788 case ISD::FrameIndex:
789 case ISD::EntryToken:
791 case ISD::BasicBlock:
792 case ISD::TargetFrameIndex:
793 case ISD::TargetJumpTable:
794 case ISD::TargetConstant:
795 case ISD::TargetConstantFP:
796 case ISD::TargetConstantPool:
797 case ISD::TargetGlobalAddress:
798 case ISD::TargetGlobalTLSAddress:
799 case ISD::TargetExternalSymbol:
804 // Primitives must all be legal.
805 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
806 "This must be legal!");
809 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
810 // If this is a target node, legalize it by legalizing the operands then
811 // passing it through.
812 SmallVector<SDOperand, 8> Ops;
813 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
814 Ops.push_back(LegalizeOp(Node->getOperand(i)));
816 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
818 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
819 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
820 return Result.getValue(Op.ResNo);
822 // Otherwise this is an unhandled builtin node. splat.
824 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
826 assert(0 && "Do not know how to legalize this operator!");
828 case ISD::GLOBAL_OFFSET_TABLE:
829 case ISD::GlobalAddress:
830 case ISD::GlobalTLSAddress:
831 case ISD::ExternalSymbol:
832 case ISD::ConstantPool:
833 case ISD::JumpTable: // Nothing to do.
834 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
835 default: assert(0 && "This action is not supported yet!");
836 case TargetLowering::Custom:
837 Tmp1 = TLI.LowerOperation(Op, DAG);
838 if (Tmp1.Val) Result = Tmp1;
839 // FALLTHROUGH if the target doesn't want to lower this op after all.
840 case TargetLowering::Legal:
845 case ISD::RETURNADDR:
846 // The only option for these nodes is to custom lower them. If the target
847 // does not custom lower them, then return zero.
848 Tmp1 = TLI.LowerOperation(Op, DAG);
852 Result = DAG.getConstant(0, TLI.getPointerTy());
854 case ISD::FRAME_TO_ARGS_OFFSET: {
855 MVT::ValueType VT = Node->getValueType(0);
856 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
857 default: assert(0 && "This action is not supported yet!");
858 case TargetLowering::Custom:
859 Result = TLI.LowerOperation(Op, DAG);
860 if (Result.Val) break;
862 case TargetLowering::Legal:
863 Result = DAG.getConstant(0, VT);
868 case ISD::EXCEPTIONADDR: {
869 Tmp1 = LegalizeOp(Node->getOperand(0));
870 MVT::ValueType VT = Node->getValueType(0);
871 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
872 default: assert(0 && "This action is not supported yet!");
873 case TargetLowering::Expand: {
874 unsigned Reg = TLI.getExceptionAddressRegister();
875 Result = DAG.getCopyFromReg(Tmp1, Reg, VT);
878 case TargetLowering::Custom:
879 Result = TLI.LowerOperation(Op, DAG);
880 if (Result.Val) break;
882 case TargetLowering::Legal: {
883 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 };
884 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
890 if (Result.Val->getNumValues() == 1) break;
892 assert(Result.Val->getNumValues() == 2 &&
893 "Cannot return more than two values!");
895 // Since we produced two values, make sure to remember that we
896 // legalized both of them.
897 Tmp1 = LegalizeOp(Result);
898 Tmp2 = LegalizeOp(Result.getValue(1));
899 AddLegalizedOperand(Op.getValue(0), Tmp1);
900 AddLegalizedOperand(Op.getValue(1), Tmp2);
901 return Op.ResNo ? Tmp2 : Tmp1;
902 case ISD::EHSELECTION: {
903 Tmp1 = LegalizeOp(Node->getOperand(0));
904 Tmp2 = LegalizeOp(Node->getOperand(1));
905 MVT::ValueType VT = Node->getValueType(0);
906 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
907 default: assert(0 && "This action is not supported yet!");
908 case TargetLowering::Expand: {
909 unsigned Reg = TLI.getExceptionSelectorRegister();
910 Result = DAG.getCopyFromReg(Tmp2, Reg, VT);
913 case TargetLowering::Custom:
914 Result = TLI.LowerOperation(Op, DAG);
915 if (Result.Val) break;
917 case TargetLowering::Legal: {
918 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 };
919 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
925 if (Result.Val->getNumValues() == 1) break;
927 assert(Result.Val->getNumValues() == 2 &&
928 "Cannot return more than two values!");
930 // Since we produced two values, make sure to remember that we
931 // legalized both of them.
932 Tmp1 = LegalizeOp(Result);
933 Tmp2 = LegalizeOp(Result.getValue(1));
934 AddLegalizedOperand(Op.getValue(0), Tmp1);
935 AddLegalizedOperand(Op.getValue(1), Tmp2);
936 return Op.ResNo ? Tmp2 : Tmp1;
937 case ISD::EH_RETURN: {
938 MVT::ValueType VT = Node->getValueType(0);
939 // The only "good" option for this node is to custom lower it.
940 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
941 default: assert(0 && "This action is not supported at all!");
942 case TargetLowering::Custom:
943 Result = TLI.LowerOperation(Op, DAG);
944 if (Result.Val) break;
946 case TargetLowering::Legal:
947 // Target does not know, how to lower this, lower to noop
948 Result = LegalizeOp(Node->getOperand(0));
953 case ISD::AssertSext:
954 case ISD::AssertZext:
955 Tmp1 = LegalizeOp(Node->getOperand(0));
956 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
958 case ISD::MERGE_VALUES:
959 // Legalize eliminates MERGE_VALUES nodes.
960 Result = Node->getOperand(Op.ResNo);
962 case ISD::CopyFromReg:
963 Tmp1 = LegalizeOp(Node->getOperand(0));
964 Result = Op.getValue(0);
965 if (Node->getNumValues() == 2) {
966 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
968 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
969 if (Node->getNumOperands() == 3) {
970 Tmp2 = LegalizeOp(Node->getOperand(2));
971 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
973 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
975 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
977 // Since CopyFromReg produces two values, make sure to remember that we
978 // legalized both of them.
979 AddLegalizedOperand(Op.getValue(0), Result);
980 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
981 return Result.getValue(Op.ResNo);
983 MVT::ValueType VT = Op.getValueType();
984 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
985 default: assert(0 && "This action is not supported yet!");
986 case TargetLowering::Expand:
987 if (MVT::isInteger(VT))
988 Result = DAG.getConstant(0, VT);
989 else if (MVT::isFloatingPoint(VT))
990 Result = DAG.getConstantFP(APFloat(APInt(MVT::getSizeInBits(VT), 0)),
993 assert(0 && "Unknown value type!");
995 case TargetLowering::Legal:
1001 case ISD::INTRINSIC_W_CHAIN:
1002 case ISD::INTRINSIC_WO_CHAIN:
1003 case ISD::INTRINSIC_VOID: {
1004 SmallVector<SDOperand, 8> Ops;
1005 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1006 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1007 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1009 // Allow the target to custom lower its intrinsics if it wants to.
1010 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
1011 TargetLowering::Custom) {
1012 Tmp3 = TLI.LowerOperation(Result, DAG);
1013 if (Tmp3.Val) Result = Tmp3;
1016 if (Result.Val->getNumValues() == 1) break;
1018 // Must have return value and chain result.
1019 assert(Result.Val->getNumValues() == 2 &&
1020 "Cannot return more than two values!");
1022 // Since loads produce two values, make sure to remember that we
1023 // legalized both of them.
1024 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1025 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1026 return Result.getValue(Op.ResNo);
1030 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
1031 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
1033 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
1034 case TargetLowering::Promote:
1035 default: assert(0 && "This action is not supported yet!");
1036 case TargetLowering::Expand: {
1037 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
1038 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
1039 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other);
1041 if (MMI && (useDEBUG_LOC || useLABEL)) {
1042 const std::string &FName =
1043 cast<StringSDNode>(Node->getOperand(3))->getValue();
1044 const std::string &DirName =
1045 cast<StringSDNode>(Node->getOperand(4))->getValue();
1046 unsigned SrcFile = MMI->RecordSource(DirName, FName);
1048 SmallVector<SDOperand, 8> Ops;
1049 Ops.push_back(Tmp1); // chain
1050 SDOperand LineOp = Node->getOperand(1);
1051 SDOperand ColOp = Node->getOperand(2);
1054 Ops.push_back(LineOp); // line #
1055 Ops.push_back(ColOp); // col #
1056 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
1057 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
1059 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
1060 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
1061 unsigned ID = MMI->RecordLabel(Line, Col, SrcFile);
1062 Ops.push_back(DAG.getConstant(ID, MVT::i32));
1063 Result = DAG.getNode(ISD::LABEL, MVT::Other,&Ops[0],Ops.size());
1066 Result = Tmp1; // chain
1070 case TargetLowering::Legal:
1071 if (Tmp1 != Node->getOperand(0) ||
1072 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
1073 SmallVector<SDOperand, 8> Ops;
1074 Ops.push_back(Tmp1);
1075 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
1076 Ops.push_back(Node->getOperand(1)); // line # must be legal.
1077 Ops.push_back(Node->getOperand(2)); // col # must be legal.
1079 // Otherwise promote them.
1080 Ops.push_back(PromoteOp(Node->getOperand(1)));
1081 Ops.push_back(PromoteOp(Node->getOperand(2)));
1083 Ops.push_back(Node->getOperand(3)); // filename must be legal.
1084 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
1085 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1091 case ISD::DEBUG_LOC:
1092 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
1093 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
1094 default: assert(0 && "This action is not supported yet!");
1095 case TargetLowering::Legal:
1096 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1097 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1098 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1099 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1100 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1106 assert(Node->getNumOperands() == 2 && "Invalid LABEL node!");
1107 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) {
1108 default: assert(0 && "This action is not supported yet!");
1109 case TargetLowering::Legal:
1110 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1111 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
1112 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1114 case TargetLowering::Expand:
1115 Result = LegalizeOp(Node->getOperand(0));
1120 case ISD::Constant: {
1121 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1123 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1125 // We know we don't need to expand constants here, constants only have one
1126 // value and we check that it is fine above.
1128 if (opAction == TargetLowering::Custom) {
1129 Tmp1 = TLI.LowerOperation(Result, DAG);
1135 case ISD::ConstantFP: {
1136 // Spill FP immediates to the constant pool if the target cannot directly
1137 // codegen them. Targets often have some immediate values that can be
1138 // efficiently generated into an FP register without a load. We explicitly
1139 // leave these constants as ConstantFP nodes for the target to deal with.
1140 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1142 // Check to see if this FP immediate is already legal.
1143 bool isLegal = false;
1144 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1145 E = TLI.legal_fpimm_end(); I != E; ++I)
1146 if (CFP->isExactlyValue(*I)) {
1151 // If this is a legal constant, turn it into a TargetConstantFP node.
1153 Result = DAG.getTargetConstantFP(CFP->getValueAPF(),
1154 CFP->getValueType(0));
1158 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1159 default: assert(0 && "This action is not supported yet!");
1160 case TargetLowering::Custom:
1161 Tmp3 = TLI.LowerOperation(Result, DAG);
1167 case TargetLowering::Expand:
1168 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1172 case ISD::TokenFactor:
1173 if (Node->getNumOperands() == 2) {
1174 Tmp1 = LegalizeOp(Node->getOperand(0));
1175 Tmp2 = LegalizeOp(Node->getOperand(1));
1176 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1177 } else if (Node->getNumOperands() == 3) {
1178 Tmp1 = LegalizeOp(Node->getOperand(0));
1179 Tmp2 = LegalizeOp(Node->getOperand(1));
1180 Tmp3 = LegalizeOp(Node->getOperand(2));
1181 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1183 SmallVector<SDOperand, 8> Ops;
1184 // Legalize the operands.
1185 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1186 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1187 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1191 case ISD::FORMAL_ARGUMENTS:
1193 // The only option for this is to custom lower it.
1194 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1195 assert(Tmp3.Val && "Target didn't custom lower this node!");
1197 // The number of incoming and outgoing values should match; unless the final
1198 // outgoing value is a flag.
1199 assert((Tmp3.Val->getNumValues() == Result.Val->getNumValues() ||
1200 (Tmp3.Val->getNumValues() == Result.Val->getNumValues() + 1 &&
1201 Tmp3.Val->getValueType(Tmp3.Val->getNumValues() - 1) ==
1203 "Lowering call/formal_arguments produced unexpected # results!");
1205 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1206 // remember that we legalized all of them, so it doesn't get relegalized.
1207 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
1208 if (Tmp3.Val->getValueType(i) == MVT::Flag)
1210 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1213 AddLegalizedOperand(SDOperand(Node, i), Tmp1);
1216 case ISD::EXTRACT_SUBREG: {
1217 Tmp1 = LegalizeOp(Node->getOperand(0));
1218 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1219 assert(idx && "Operand must be a constant");
1220 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1221 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1224 case ISD::INSERT_SUBREG: {
1225 Tmp1 = LegalizeOp(Node->getOperand(0));
1226 Tmp2 = LegalizeOp(Node->getOperand(1));
1227 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1228 assert(idx && "Operand must be a constant");
1229 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1230 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1233 case ISD::BUILD_VECTOR:
1234 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1235 default: assert(0 && "This action is not supported yet!");
1236 case TargetLowering::Custom:
1237 Tmp3 = TLI.LowerOperation(Result, DAG);
1243 case TargetLowering::Expand:
1244 Result = ExpandBUILD_VECTOR(Result.Val);
1248 case ISD::INSERT_VECTOR_ELT:
1249 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1250 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal
1251 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1252 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1254 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1255 Node->getValueType(0))) {
1256 default: assert(0 && "This action is not supported yet!");
1257 case TargetLowering::Legal:
1259 case TargetLowering::Custom:
1260 Tmp4 = TLI.LowerOperation(Result, DAG);
1266 case TargetLowering::Expand: {
1267 // If the insert index is a constant, codegen this as a scalar_to_vector,
1268 // then a shuffle that inserts it into the right position in the vector.
1269 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1270 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
1271 Tmp1.getValueType(), Tmp2);
1273 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
1274 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
1275 MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT);
1277 // We generate a shuffle of InVec and ScVec, so the shuffle mask should
1278 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of
1280 SmallVector<SDOperand, 8> ShufOps;
1281 for (unsigned i = 0; i != NumElts; ++i) {
1282 if (i != InsertPos->getValue())
1283 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1285 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1287 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1288 &ShufOps[0], ShufOps.size());
1290 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1291 Tmp1, ScVec, ShufMask);
1292 Result = LegalizeOp(Result);
1296 // If the target doesn't support this, we have to spill the input vector
1297 // to a temporary stack slot, update the element, then reload it. This is
1298 // badness. We could also load the value into a vector register (either
1299 // with a "move to register" or "extload into register" instruction, then
1300 // permute it into place, if the idx is a constant and if the idx is
1301 // supported by the target.
1302 MVT::ValueType VT = Tmp1.getValueType();
1303 MVT::ValueType EltVT = Tmp2.getValueType();
1304 MVT::ValueType IdxVT = Tmp3.getValueType();
1305 MVT::ValueType PtrVT = TLI.getPointerTy();
1306 SDOperand StackPtr = DAG.CreateStackTemporary(VT);
1307 // Store the vector.
1308 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, NULL, 0);
1310 // Truncate or zero extend offset to target pointer type.
1311 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
1312 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
1313 // Add the offset to the index.
1314 unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
1315 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
1316 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
1317 // Store the scalar value.
1318 Ch = DAG.getStore(Ch, Tmp2, StackPtr2, NULL, 0);
1319 // Load the updated vector.
1320 Result = DAG.getLoad(VT, Ch, StackPtr, NULL, 0);
1325 case ISD::SCALAR_TO_VECTOR:
1326 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1327 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1331 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1332 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1333 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1334 Node->getValueType(0))) {
1335 default: assert(0 && "This action is not supported yet!");
1336 case TargetLowering::Legal:
1338 case TargetLowering::Custom:
1339 Tmp3 = TLI.LowerOperation(Result, DAG);
1345 case TargetLowering::Expand:
1346 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1350 case ISD::VECTOR_SHUFFLE:
1351 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1352 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1353 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1355 // Allow targets to custom lower the SHUFFLEs they support.
1356 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1357 default: assert(0 && "Unknown operation action!");
1358 case TargetLowering::Legal:
1359 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1360 "vector shuffle should not be created if not legal!");
1362 case TargetLowering::Custom:
1363 Tmp3 = TLI.LowerOperation(Result, DAG);
1369 case TargetLowering::Expand: {
1370 MVT::ValueType VT = Node->getValueType(0);
1371 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
1372 MVT::ValueType PtrVT = TLI.getPointerTy();
1373 SDOperand Mask = Node->getOperand(2);
1374 unsigned NumElems = Mask.getNumOperands();
1375 SmallVector<SDOperand,8> Ops;
1376 for (unsigned i = 0; i != NumElems; ++i) {
1377 SDOperand Arg = Mask.getOperand(i);
1378 if (Arg.getOpcode() == ISD::UNDEF) {
1379 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1381 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1382 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
1384 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1385 DAG.getConstant(Idx, PtrVT)));
1387 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1388 DAG.getConstant(Idx - NumElems, PtrVT)));
1391 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1394 case TargetLowering::Promote: {
1395 // Change base type to a different vector type.
1396 MVT::ValueType OVT = Node->getValueType(0);
1397 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1399 // Cast the two input vectors.
1400 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1401 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1403 // Convert the shuffle mask to the right # elements.
1404 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1405 assert(Tmp3.Val && "Shuffle not legal?");
1406 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1407 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1413 case ISD::EXTRACT_VECTOR_ELT:
1414 Tmp1 = Node->getOperand(0);
1415 Tmp2 = LegalizeOp(Node->getOperand(1));
1416 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1417 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1420 case ISD::EXTRACT_SUBVECTOR:
1421 Tmp1 = Node->getOperand(0);
1422 Tmp2 = LegalizeOp(Node->getOperand(1));
1423 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1424 Result = ExpandEXTRACT_SUBVECTOR(Result);
1427 case ISD::CALLSEQ_START: {
1428 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1430 // Recursively Legalize all of the inputs of the call end that do not lead
1431 // to this call start. This ensures that any libcalls that need be inserted
1432 // are inserted *before* the CALLSEQ_START.
1433 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1434 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1435 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
1439 // Now that we legalized all of the inputs (which may have inserted
1440 // libcalls) create the new CALLSEQ_START node.
1441 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1443 // Merge in the last call, to ensure that this call start after the last
1445 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1446 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1447 Tmp1 = LegalizeOp(Tmp1);
1450 // Do not try to legalize the target-specific arguments (#1+).
1451 if (Tmp1 != Node->getOperand(0)) {
1452 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1454 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1457 // Remember that the CALLSEQ_START is legalized.
1458 AddLegalizedOperand(Op.getValue(0), Result);
1459 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1460 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1462 // Now that the callseq_start and all of the non-call nodes above this call
1463 // sequence have been legalized, legalize the call itself. During this
1464 // process, no libcalls can/will be inserted, guaranteeing that no calls
1466 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1467 SDOperand InCallSEQ = LastCALLSEQ_END;
1468 // Note that we are selecting this call!
1469 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1470 IsLegalizingCall = true;
1472 // Legalize the call, starting from the CALLSEQ_END.
1473 LegalizeOp(LastCALLSEQ_END);
1474 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1477 case ISD::CALLSEQ_END:
1478 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1479 // will cause this node to be legalized as well as handling libcalls right.
1480 if (LastCALLSEQ_END.Val != Node) {
1481 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1482 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1483 assert(I != LegalizedNodes.end() &&
1484 "Legalizing the call start should have legalized this node!");
1488 // Otherwise, the call start has been legalized and everything is going
1489 // according to plan. Just legalize ourselves normally here.
1490 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1491 // Do not try to legalize the target-specific arguments (#1+), except for
1492 // an optional flag input.
1493 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1494 if (Tmp1 != Node->getOperand(0)) {
1495 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1497 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1500 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1501 if (Tmp1 != Node->getOperand(0) ||
1502 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1503 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1506 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1509 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1510 // This finishes up call legalization.
1511 IsLegalizingCall = false;
1513 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1514 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1515 if (Node->getNumValues() == 2)
1516 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1517 return Result.getValue(Op.ResNo);
1518 case ISD::DYNAMIC_STACKALLOC: {
1519 MVT::ValueType VT = Node->getValueType(0);
1520 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1521 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1522 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1523 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1525 Tmp1 = Result.getValue(0);
1526 Tmp2 = Result.getValue(1);
1527 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1528 default: assert(0 && "This action is not supported yet!");
1529 case TargetLowering::Expand: {
1530 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1531 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1532 " not tell us which reg is the stack pointer!");
1533 SDOperand Chain = Tmp1.getOperand(0);
1535 // Chain the dynamic stack allocation so that it doesn't modify the stack
1536 // pointer when other instructions are using the stack.
1537 Chain = DAG.getCALLSEQ_START(Chain,
1538 DAG.getConstant(0, TLI.getPointerTy()));
1540 SDOperand Size = Tmp2.getOperand(1);
1541 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT);
1542 Chain = SP.getValue(1);
1543 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue();
1544 unsigned StackAlign =
1545 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1546 if (Align > StackAlign)
1547 SP = DAG.getNode(ISD::AND, VT, SP,
1548 DAG.getConstant(-(uint64_t)Align, VT));
1549 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value
1550 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
1553 DAG.getCALLSEQ_END(Chain,
1554 DAG.getConstant(0, TLI.getPointerTy()),
1555 DAG.getConstant(0, TLI.getPointerTy()),
1558 Tmp1 = LegalizeOp(Tmp1);
1559 Tmp2 = LegalizeOp(Tmp2);
1562 case TargetLowering::Custom:
1563 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1565 Tmp1 = LegalizeOp(Tmp3);
1566 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1569 case TargetLowering::Legal:
1572 // Since this op produce two values, make sure to remember that we
1573 // legalized both of them.
1574 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1575 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1576 return Op.ResNo ? Tmp2 : Tmp1;
1578 case ISD::INLINEASM: {
1579 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1580 bool Changed = false;
1581 // Legalize all of the operands of the inline asm, in case they are nodes
1582 // that need to be expanded or something. Note we skip the asm string and
1583 // all of the TargetConstant flags.
1584 SDOperand Op = LegalizeOp(Ops[0]);
1585 Changed = Op != Ops[0];
1588 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1589 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1590 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1591 for (++i; NumVals; ++i, --NumVals) {
1592 SDOperand Op = LegalizeOp(Ops[i]);
1601 Op = LegalizeOp(Ops.back());
1602 Changed |= Op != Ops.back();
1607 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1609 // INLINE asm returns a chain and flag, make sure to add both to the map.
1610 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1611 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1612 return Result.getValue(Op.ResNo);
1615 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1616 // Ensure that libcalls are emitted before a branch.
1617 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1618 Tmp1 = LegalizeOp(Tmp1);
1619 LastCALLSEQ_END = DAG.getEntryNode();
1621 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1624 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1625 // Ensure that libcalls are emitted before a branch.
1626 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1627 Tmp1 = LegalizeOp(Tmp1);
1628 LastCALLSEQ_END = DAG.getEntryNode();
1630 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1631 default: assert(0 && "Indirect target must be legal type (pointer)!");
1633 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1636 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1639 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1640 // Ensure that libcalls are emitted before a branch.
1641 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1642 Tmp1 = LegalizeOp(Tmp1);
1643 LastCALLSEQ_END = DAG.getEntryNode();
1645 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1646 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1648 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1649 default: assert(0 && "This action is not supported yet!");
1650 case TargetLowering::Legal: break;
1651 case TargetLowering::Custom:
1652 Tmp1 = TLI.LowerOperation(Result, DAG);
1653 if (Tmp1.Val) Result = Tmp1;
1655 case TargetLowering::Expand: {
1656 SDOperand Chain = Result.getOperand(0);
1657 SDOperand Table = Result.getOperand(1);
1658 SDOperand Index = Result.getOperand(2);
1660 MVT::ValueType PTy = TLI.getPointerTy();
1661 MachineFunction &MF = DAG.getMachineFunction();
1662 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
1663 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1664 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1667 switch (EntrySize) {
1668 default: assert(0 && "Size of jump table not supported yet."); break;
1669 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, NULL, 0); break;
1670 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, NULL, 0); break;
1674 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1675 // For PIC, the sequence is:
1676 // BRIND(load(Jumptable + index) + RelocBase)
1677 // RelocBase can be JumpTable, GOT or some sort of global base.
1678 if (PTy != MVT::i32)
1679 Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr);
1680 Addr = DAG.getNode(ISD::ADD, PTy, Addr,
1681 TLI.getPICJumpTableRelocBase(Table, DAG));
1683 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1688 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1689 // Ensure that libcalls are emitted before a return.
1690 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1691 Tmp1 = LegalizeOp(Tmp1);
1692 LastCALLSEQ_END = DAG.getEntryNode();
1694 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1695 case Expand: assert(0 && "It's impossible to expand bools");
1697 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1700 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1702 // The top bits of the promoted condition are not necessarily zero, ensure
1703 // that the value is properly zero extended.
1704 if (!DAG.MaskedValueIsZero(Tmp2,
1705 MVT::getIntVTBitMask(Tmp2.getValueType())^1))
1706 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1710 // Basic block destination (Op#2) is always legal.
1711 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1713 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1714 default: assert(0 && "This action is not supported yet!");
1715 case TargetLowering::Legal: break;
1716 case TargetLowering::Custom:
1717 Tmp1 = TLI.LowerOperation(Result, DAG);
1718 if (Tmp1.Val) Result = Tmp1;
1720 case TargetLowering::Expand:
1721 // Expand brcond's setcc into its constituent parts and create a BR_CC
1723 if (Tmp2.getOpcode() == ISD::SETCC) {
1724 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1725 Tmp2.getOperand(0), Tmp2.getOperand(1),
1726 Node->getOperand(2));
1728 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1729 DAG.getCondCode(ISD::SETNE), Tmp2,
1730 DAG.getConstant(0, Tmp2.getValueType()),
1731 Node->getOperand(2));
1737 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1738 // Ensure that libcalls are emitted before a branch.
1739 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1740 Tmp1 = LegalizeOp(Tmp1);
1741 Tmp2 = Node->getOperand(2); // LHS
1742 Tmp3 = Node->getOperand(3); // RHS
1743 Tmp4 = Node->getOperand(1); // CC
1745 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1746 LastCALLSEQ_END = DAG.getEntryNode();
1748 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1749 // the LHS is a legal SETCC itself. In this case, we need to compare
1750 // the result against zero to select between true and false values.
1751 if (Tmp3.Val == 0) {
1752 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1753 Tmp4 = DAG.getCondCode(ISD::SETNE);
1756 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1757 Node->getOperand(4));
1759 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1760 default: assert(0 && "Unexpected action for BR_CC!");
1761 case TargetLowering::Legal: break;
1762 case TargetLowering::Custom:
1763 Tmp4 = TLI.LowerOperation(Result, DAG);
1764 if (Tmp4.Val) Result = Tmp4;
1769 LoadSDNode *LD = cast<LoadSDNode>(Node);
1770 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1771 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1773 ISD::LoadExtType ExtType = LD->getExtensionType();
1774 if (ExtType == ISD::NON_EXTLOAD) {
1775 MVT::ValueType VT = Node->getValueType(0);
1776 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1777 Tmp3 = Result.getValue(0);
1778 Tmp4 = Result.getValue(1);
1780 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1781 default: assert(0 && "This action is not supported yet!");
1782 case TargetLowering::Legal:
1783 // If this is an unaligned load and the target doesn't support it,
1785 if (!TLI.allowsUnalignedMemoryAccesses()) {
1786 unsigned ABIAlignment = TLI.getTargetData()->
1787 getABITypeAlignment(MVT::getTypeForValueType(LD->getLoadedVT()));
1788 if (LD->getAlignment() < ABIAlignment){
1789 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
1791 Tmp3 = Result.getOperand(0);
1792 Tmp4 = Result.getOperand(1);
1793 Tmp3 = LegalizeOp(Tmp3);
1794 Tmp4 = LegalizeOp(Tmp4);
1798 case TargetLowering::Custom:
1799 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1801 Tmp3 = LegalizeOp(Tmp1);
1802 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1805 case TargetLowering::Promote: {
1806 // Only promote a load of vector type to another.
1807 assert(MVT::isVector(VT) && "Cannot promote this load!");
1808 // Change base type to a different vector type.
1809 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1811 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1812 LD->getSrcValueOffset(),
1813 LD->isVolatile(), LD->getAlignment());
1814 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1815 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1819 // Since loads produce two values, make sure to remember that we
1820 // legalized both of them.
1821 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1822 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1823 return Op.ResNo ? Tmp4 : Tmp3;
1825 MVT::ValueType SrcVT = LD->getLoadedVT();
1826 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
1827 default: assert(0 && "This action is not supported yet!");
1828 case TargetLowering::Promote:
1829 assert(SrcVT == MVT::i1 &&
1830 "Can only promote extending LOAD from i1 -> i8!");
1831 Result = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
1832 LD->getSrcValue(), LD->getSrcValueOffset(),
1833 MVT::i8, LD->isVolatile(), LD->getAlignment());
1834 Tmp1 = Result.getValue(0);
1835 Tmp2 = Result.getValue(1);
1837 case TargetLowering::Custom:
1840 case TargetLowering::Legal:
1841 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1842 Tmp1 = Result.getValue(0);
1843 Tmp2 = Result.getValue(1);
1846 Tmp3 = TLI.LowerOperation(Result, DAG);
1848 Tmp1 = LegalizeOp(Tmp3);
1849 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1852 // If this is an unaligned load and the target doesn't support it,
1854 if (!TLI.allowsUnalignedMemoryAccesses()) {
1855 unsigned ABIAlignment = TLI.getTargetData()->
1856 getABITypeAlignment(MVT::getTypeForValueType(LD->getLoadedVT()));
1857 if (LD->getAlignment() < ABIAlignment){
1858 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
1860 Tmp1 = Result.getOperand(0);
1861 Tmp2 = Result.getOperand(1);
1862 Tmp1 = LegalizeOp(Tmp1);
1863 Tmp2 = LegalizeOp(Tmp2);
1868 case TargetLowering::Expand:
1869 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1870 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1871 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
1872 LD->getSrcValueOffset(),
1873 LD->isVolatile(), LD->getAlignment());
1874 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
1875 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1876 Tmp2 = LegalizeOp(Load.getValue(1));
1879 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
1880 // Turn the unsupported load into an EXTLOAD followed by an explicit
1881 // zero/sign extend inreg.
1882 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
1883 Tmp1, Tmp2, LD->getSrcValue(),
1884 LD->getSrcValueOffset(), SrcVT,
1885 LD->isVolatile(), LD->getAlignment());
1887 if (ExtType == ISD::SEXTLOAD)
1888 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1889 Result, DAG.getValueType(SrcVT));
1891 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
1892 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1893 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1896 // Since loads produce two values, make sure to remember that we legalized
1898 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1899 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1900 return Op.ResNo ? Tmp2 : Tmp1;
1903 case ISD::EXTRACT_ELEMENT: {
1904 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
1905 switch (getTypeAction(OpTy)) {
1906 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
1908 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
1910 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
1911 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
1912 TLI.getShiftAmountTy()));
1913 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
1916 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
1917 Node->getOperand(0));
1921 // Get both the low and high parts.
1922 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1923 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
1924 Result = Tmp2; // 1 -> Hi
1926 Result = Tmp1; // 0 -> Lo
1932 case ISD::CopyToReg:
1933 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1935 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
1936 "Register type must be legal!");
1937 // Legalize the incoming value (must be a legal type).
1938 Tmp2 = LegalizeOp(Node->getOperand(2));
1939 if (Node->getNumValues() == 1) {
1940 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
1942 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
1943 if (Node->getNumOperands() == 4) {
1944 Tmp3 = LegalizeOp(Node->getOperand(3));
1945 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
1948 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1951 // Since this produces two values, make sure to remember that we legalized
1953 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1954 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1960 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1962 // Ensure that libcalls are emitted before a return.
1963 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1964 Tmp1 = LegalizeOp(Tmp1);
1965 LastCALLSEQ_END = DAG.getEntryNode();
1967 switch (Node->getNumOperands()) {
1969 Tmp2 = Node->getOperand(1);
1970 Tmp3 = Node->getOperand(2); // Signness
1971 switch (getTypeAction(Tmp2.getValueType())) {
1973 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
1976 if (!MVT::isVector(Tmp2.getValueType())) {
1978 ExpandOp(Tmp2, Lo, Hi);
1980 // Big endian systems want the hi reg first.
1981 if (!TLI.isLittleEndian())
1985 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
1987 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
1988 Result = LegalizeOp(Result);
1990 SDNode *InVal = Tmp2.Val;
1991 int InIx = Tmp2.ResNo;
1992 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx));
1993 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx));
1995 // Figure out if there is a simple type corresponding to this Vector
1996 // type. If so, convert to the vector type.
1997 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1998 if (TLI.isTypeLegal(TVT)) {
1999 // Turn this into a return of the vector type.
2000 Tmp2 = LegalizeOp(Tmp2);
2001 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2002 } else if (NumElems == 1) {
2003 // Turn this into a return of the scalar type.
2004 Tmp2 = ScalarizeVectorOp(Tmp2);
2005 Tmp2 = LegalizeOp(Tmp2);
2006 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2008 // FIXME: Returns of gcc generic vectors smaller than a legal type
2009 // should be returned in integer registers!
2011 // The scalarized value type may not be legal, e.g. it might require
2012 // promotion or expansion. Relegalize the return.
2013 Result = LegalizeOp(Result);
2015 // FIXME: Returns of gcc generic vectors larger than a legal vector
2016 // type should be returned by reference!
2018 SplitVectorOp(Tmp2, Lo, Hi);
2019 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2020 Result = LegalizeOp(Result);
2025 Tmp2 = PromoteOp(Node->getOperand(1));
2026 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2027 Result = LegalizeOp(Result);
2032 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2034 default: { // ret <values>
2035 SmallVector<SDOperand, 8> NewValues;
2036 NewValues.push_back(Tmp1);
2037 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
2038 switch (getTypeAction(Node->getOperand(i).getValueType())) {
2040 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
2041 NewValues.push_back(Node->getOperand(i+1));
2045 assert(!MVT::isExtendedVT(Node->getOperand(i).getValueType()) &&
2046 "FIXME: TODO: implement returning non-legal vector types!");
2047 ExpandOp(Node->getOperand(i), Lo, Hi);
2048 NewValues.push_back(Lo);
2049 NewValues.push_back(Node->getOperand(i+1));
2051 NewValues.push_back(Hi);
2052 NewValues.push_back(Node->getOperand(i+1));
2057 assert(0 && "Can't promote multiple return value yet!");
2060 if (NewValues.size() == Node->getNumOperands())
2061 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
2063 Result = DAG.getNode(ISD::RET, MVT::Other,
2064 &NewValues[0], NewValues.size());
2069 if (Result.getOpcode() == ISD::RET) {
2070 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
2071 default: assert(0 && "This action is not supported yet!");
2072 case TargetLowering::Legal: break;
2073 case TargetLowering::Custom:
2074 Tmp1 = TLI.LowerOperation(Result, DAG);
2075 if (Tmp1.Val) Result = Tmp1;
2081 StoreSDNode *ST = cast<StoreSDNode>(Node);
2082 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
2083 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
2084 int SVOffset = ST->getSrcValueOffset();
2085 unsigned Alignment = ST->getAlignment();
2086 bool isVolatile = ST->isVolatile();
2088 if (!ST->isTruncatingStore()) {
2089 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
2090 // FIXME: We shouldn't do this for TargetConstantFP's.
2091 // FIXME: move this to the DAG Combiner! Note that we can't regress due
2092 // to phase ordering between legalized code and the dag combiner. This
2093 // probably means that we need to integrate dag combiner and legalizer
2095 // We generally can't do this one for long doubles.
2096 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
2097 if (CFP->getValueType(0) == MVT::f32 &&
2098 getTypeAction(MVT::i32) == Legal) {
2099 Tmp3 = DAG.getConstant((uint32_t)CFP->getValueAPF().
2100 convertToAPInt().getZExtValue(),
2102 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2103 SVOffset, isVolatile, Alignment);
2105 } else if (CFP->getValueType(0) == MVT::f64) {
2106 // If this target supports 64-bit registers, do a single 64-bit store.
2107 if (getTypeAction(MVT::i64) == Legal) {
2108 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt().
2109 getZExtValue(), MVT::i64);
2110 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2111 SVOffset, isVolatile, Alignment);
2113 } else if (getTypeAction(MVT::i32) == Legal) {
2114 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
2115 // stores. If the target supports neither 32- nor 64-bits, this
2116 // xform is certainly not worth it.
2117 uint64_t IntVal =CFP->getValueAPF().convertToAPInt().getZExtValue();
2118 SDOperand Lo = DAG.getConstant(uint32_t(IntVal), MVT::i32);
2119 SDOperand Hi = DAG.getConstant(uint32_t(IntVal >>32), MVT::i32);
2120 if (!TLI.isLittleEndian()) std::swap(Lo, Hi);
2122 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2123 SVOffset, isVolatile, Alignment);
2124 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2125 getIntPtrConstant(4));
2126 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
2127 isVolatile, MinAlign(Alignment, 4U));
2129 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2135 switch (getTypeAction(ST->getStoredVT())) {
2137 Tmp3 = LegalizeOp(ST->getValue());
2138 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2141 MVT::ValueType VT = Tmp3.getValueType();
2142 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2143 default: assert(0 && "This action is not supported yet!");
2144 case TargetLowering::Legal:
2145 // If this is an unaligned store and the target doesn't support it,
2147 if (!TLI.allowsUnalignedMemoryAccesses()) {
2148 unsigned ABIAlignment = TLI.getTargetData()->
2149 getABITypeAlignment(MVT::getTypeForValueType(ST->getStoredVT()));
2150 if (ST->getAlignment() < ABIAlignment)
2151 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2155 case TargetLowering::Custom:
2156 Tmp1 = TLI.LowerOperation(Result, DAG);
2157 if (Tmp1.Val) Result = Tmp1;
2159 case TargetLowering::Promote:
2160 assert(MVT::isVector(VT) && "Unknown legal promote case!");
2161 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
2162 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2163 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
2164 ST->getSrcValue(), SVOffset, isVolatile,
2171 // Truncate the value and store the result.
2172 Tmp3 = PromoteOp(ST->getValue());
2173 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2174 SVOffset, ST->getStoredVT(),
2175 isVolatile, Alignment);
2179 unsigned IncrementSize = 0;
2182 // If this is a vector type, then we have to calculate the increment as
2183 // the product of the element size in bytes, and the number of elements
2184 // in the high half of the vector.
2185 if (MVT::isVector(ST->getValue().getValueType())) {
2186 SDNode *InVal = ST->getValue().Val;
2187 int InIx = ST->getValue().ResNo;
2188 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx));
2189 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx));
2191 // Figure out if there is a simple type corresponding to this Vector
2192 // type. If so, convert to the vector type.
2193 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2194 if (TLI.isTypeLegal(TVT)) {
2195 // Turn this into a normal store of the vector type.
2196 Tmp3 = LegalizeOp(Node->getOperand(1));
2197 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2198 SVOffset, isVolatile, Alignment);
2199 Result = LegalizeOp(Result);
2201 } else if (NumElems == 1) {
2202 // Turn this into a normal store of the scalar type.
2203 Tmp3 = ScalarizeVectorOp(Node->getOperand(1));
2204 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2205 SVOffset, isVolatile, Alignment);
2206 // The scalarized value type may not be legal, e.g. it might require
2207 // promotion or expansion. Relegalize the scalar store.
2208 Result = LegalizeOp(Result);
2211 SplitVectorOp(Node->getOperand(1), Lo, Hi);
2212 IncrementSize = MVT::getVectorNumElements(Lo.Val->getValueType(0)) *
2213 MVT::getSizeInBits(EVT)/8;
2216 ExpandOp(Node->getOperand(1), Lo, Hi);
2217 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0;
2219 if (!TLI.isLittleEndian())
2223 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2224 SVOffset, isVolatile, Alignment);
2226 if (Hi.Val == NULL) {
2227 // Must be int <-> float one-to-one expansion.
2232 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2233 getIntPtrConstant(IncrementSize));
2234 assert(isTypeLegal(Tmp2.getValueType()) &&
2235 "Pointers must be legal!");
2236 SVOffset += IncrementSize;
2237 Alignment = MinAlign(Alignment, IncrementSize);
2238 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2239 SVOffset, isVolatile, Alignment);
2240 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2245 assert(isTypeLegal(ST->getValue().getValueType()) &&
2246 "Cannot handle illegal TRUNCSTORE yet!");
2247 Tmp3 = LegalizeOp(ST->getValue());
2249 // The only promote case we handle is TRUNCSTORE:i1 X into
2250 // -> TRUNCSTORE:i8 (and X, 1)
2251 if (ST->getStoredVT() == MVT::i1 &&
2252 TLI.getStoreXAction(MVT::i1) == TargetLowering::Promote) {
2253 // Promote the bool to a mask then store.
2254 Tmp3 = DAG.getNode(ISD::AND, Tmp3.getValueType(), Tmp3,
2255 DAG.getConstant(1, Tmp3.getValueType()));
2256 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2258 isVolatile, Alignment);
2259 } else if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2260 Tmp2 != ST->getBasePtr()) {
2261 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2265 MVT::ValueType StVT = cast<StoreSDNode>(Result.Val)->getStoredVT();
2266 switch (TLI.getStoreXAction(StVT)) {
2267 default: assert(0 && "This action is not supported yet!");
2268 case TargetLowering::Legal:
2269 // If this is an unaligned store and the target doesn't support it,
2271 if (!TLI.allowsUnalignedMemoryAccesses()) {
2272 unsigned ABIAlignment = TLI.getTargetData()->
2273 getABITypeAlignment(MVT::getTypeForValueType(ST->getStoredVT()));
2274 if (ST->getAlignment() < ABIAlignment)
2275 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2279 case TargetLowering::Custom:
2280 Tmp1 = TLI.LowerOperation(Result, DAG);
2281 if (Tmp1.Val) Result = Tmp1;
2288 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2289 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2291 case ISD::STACKSAVE:
2292 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2293 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2294 Tmp1 = Result.getValue(0);
2295 Tmp2 = Result.getValue(1);
2297 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2298 default: assert(0 && "This action is not supported yet!");
2299 case TargetLowering::Legal: break;
2300 case TargetLowering::Custom:
2301 Tmp3 = TLI.LowerOperation(Result, DAG);
2303 Tmp1 = LegalizeOp(Tmp3);
2304 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2307 case TargetLowering::Expand:
2308 // Expand to CopyFromReg if the target set
2309 // StackPointerRegisterToSaveRestore.
2310 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2311 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
2312 Node->getValueType(0));
2313 Tmp2 = Tmp1.getValue(1);
2315 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
2316 Tmp2 = Node->getOperand(0);
2321 // Since stacksave produce two values, make sure to remember that we
2322 // legalized both of them.
2323 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2324 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2325 return Op.ResNo ? Tmp2 : Tmp1;
2327 case ISD::STACKRESTORE:
2328 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2329 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2330 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2332 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2333 default: assert(0 && "This action is not supported yet!");
2334 case TargetLowering::Legal: break;
2335 case TargetLowering::Custom:
2336 Tmp1 = TLI.LowerOperation(Result, DAG);
2337 if (Tmp1.Val) Result = Tmp1;
2339 case TargetLowering::Expand:
2340 // Expand to CopyToReg if the target set
2341 // StackPointerRegisterToSaveRestore.
2342 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2343 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
2351 case ISD::READCYCLECOUNTER:
2352 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2353 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2354 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2355 Node->getValueType(0))) {
2356 default: assert(0 && "This action is not supported yet!");
2357 case TargetLowering::Legal:
2358 Tmp1 = Result.getValue(0);
2359 Tmp2 = Result.getValue(1);
2361 case TargetLowering::Custom:
2362 Result = TLI.LowerOperation(Result, DAG);
2363 Tmp1 = LegalizeOp(Result.getValue(0));
2364 Tmp2 = LegalizeOp(Result.getValue(1));
2368 // Since rdcc produce two values, make sure to remember that we legalized
2370 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2371 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2375 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2376 case Expand: assert(0 && "It's impossible to expand bools");
2378 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2381 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2382 // Make sure the condition is either zero or one.
2383 if (!DAG.MaskedValueIsZero(Tmp1,
2384 MVT::getIntVTBitMask(Tmp1.getValueType())^1))
2385 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2388 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2389 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2391 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2393 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2394 default: assert(0 && "This action is not supported yet!");
2395 case TargetLowering::Legal: break;
2396 case TargetLowering::Custom: {
2397 Tmp1 = TLI.LowerOperation(Result, DAG);
2398 if (Tmp1.Val) Result = Tmp1;
2401 case TargetLowering::Expand:
2402 if (Tmp1.getOpcode() == ISD::SETCC) {
2403 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2405 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2407 Result = DAG.getSelectCC(Tmp1,
2408 DAG.getConstant(0, Tmp1.getValueType()),
2409 Tmp2, Tmp3, ISD::SETNE);
2412 case TargetLowering::Promote: {
2413 MVT::ValueType NVT =
2414 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2415 unsigned ExtOp, TruncOp;
2416 if (MVT::isVector(Tmp2.getValueType())) {
2417 ExtOp = ISD::BIT_CONVERT;
2418 TruncOp = ISD::BIT_CONVERT;
2419 } else if (MVT::isInteger(Tmp2.getValueType())) {
2420 ExtOp = ISD::ANY_EXTEND;
2421 TruncOp = ISD::TRUNCATE;
2423 ExtOp = ISD::FP_EXTEND;
2424 TruncOp = ISD::FP_ROUND;
2426 // Promote each of the values to the new type.
2427 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2428 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2429 // Perform the larger operation, then round down.
2430 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2431 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2436 case ISD::SELECT_CC: {
2437 Tmp1 = Node->getOperand(0); // LHS
2438 Tmp2 = Node->getOperand(1); // RHS
2439 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2440 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2441 SDOperand CC = Node->getOperand(4);
2443 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
2445 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
2446 // the LHS is a legal SETCC itself. In this case, we need to compare
2447 // the result against zero to select between true and false values.
2448 if (Tmp2.Val == 0) {
2449 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2450 CC = DAG.getCondCode(ISD::SETNE);
2452 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
2454 // Everything is legal, see if we should expand this op or something.
2455 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
2456 default: assert(0 && "This action is not supported yet!");
2457 case TargetLowering::Legal: break;
2458 case TargetLowering::Custom:
2459 Tmp1 = TLI.LowerOperation(Result, DAG);
2460 if (Tmp1.Val) Result = Tmp1;
2466 Tmp1 = Node->getOperand(0);
2467 Tmp2 = Node->getOperand(1);
2468 Tmp3 = Node->getOperand(2);
2469 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
2471 // If we had to Expand the SetCC operands into a SELECT node, then it may
2472 // not always be possible to return a true LHS & RHS. In this case, just
2473 // return the value we legalized, returned in the LHS
2474 if (Tmp2.Val == 0) {
2479 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
2480 default: assert(0 && "Cannot handle this action for SETCC yet!");
2481 case TargetLowering::Custom:
2484 case TargetLowering::Legal:
2485 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2487 Tmp4 = TLI.LowerOperation(Result, DAG);
2488 if (Tmp4.Val) Result = Tmp4;
2491 case TargetLowering::Promote: {
2492 // First step, figure out the appropriate operation to use.
2493 // Allow SETCC to not be supported for all legal data types
2494 // Mostly this targets FP
2495 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
2496 MVT::ValueType OldVT = NewInTy; OldVT = OldVT;
2498 // Scan for the appropriate larger type to use.
2500 NewInTy = (MVT::ValueType)(NewInTy+1);
2502 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
2503 "Fell off of the edge of the integer world");
2504 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
2505 "Fell off of the edge of the floating point world");
2507 // If the target supports SETCC of this type, use it.
2508 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2511 if (MVT::isInteger(NewInTy))
2512 assert(0 && "Cannot promote Legal Integer SETCC yet");
2514 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2515 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2517 Tmp1 = LegalizeOp(Tmp1);
2518 Tmp2 = LegalizeOp(Tmp2);
2519 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2520 Result = LegalizeOp(Result);
2523 case TargetLowering::Expand:
2524 // Expand a setcc node into a select_cc of the same condition, lhs, and
2525 // rhs that selects between const 1 (true) and const 0 (false).
2526 MVT::ValueType VT = Node->getValueType(0);
2527 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2528 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2535 case ISD::MEMMOVE: {
2536 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
2537 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
2539 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
2540 switch (getTypeAction(Node->getOperand(2).getValueType())) {
2541 case Expand: assert(0 && "Cannot expand a byte!");
2543 Tmp3 = LegalizeOp(Node->getOperand(2));
2546 Tmp3 = PromoteOp(Node->getOperand(2));
2550 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
2554 switch (getTypeAction(Node->getOperand(3).getValueType())) {
2556 // Length is too big, just take the lo-part of the length.
2558 ExpandOp(Node->getOperand(3), Tmp4, HiPart);
2562 Tmp4 = LegalizeOp(Node->getOperand(3));
2565 Tmp4 = PromoteOp(Node->getOperand(3));
2570 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
2571 case Expand: assert(0 && "Cannot expand this yet!");
2573 Tmp5 = LegalizeOp(Node->getOperand(4));
2576 Tmp5 = PromoteOp(Node->getOperand(4));
2581 switch (getTypeAction(Node->getOperand(5).getValueType())) { // bool
2582 case Expand: assert(0 && "Cannot expand this yet!");
2584 Tmp6 = LegalizeOp(Node->getOperand(5));
2587 Tmp6 = PromoteOp(Node->getOperand(5));
2591 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2592 default: assert(0 && "This action not implemented for this operation!");
2593 case TargetLowering::Custom:
2596 case TargetLowering::Legal: {
2597 SDOperand Ops[] = { Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6 };
2598 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
2600 Tmp1 = TLI.LowerOperation(Result, DAG);
2601 if (Tmp1.Val) Result = Tmp1;
2605 case TargetLowering::Expand: {
2606 // Otherwise, the target does not support this operation. Lower the
2607 // operation to an explicit libcall as appropriate.
2608 MVT::ValueType IntPtr = TLI.getPointerTy();
2609 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType();
2610 TargetLowering::ArgListTy Args;
2611 TargetLowering::ArgListEntry Entry;
2613 const char *FnName = 0;
2614 if (Node->getOpcode() == ISD::MEMSET) {
2615 Entry.Node = Tmp2; Entry.Ty = IntPtrTy;
2616 Args.push_back(Entry);
2617 // Extend the (previously legalized) ubyte argument to be an int value
2619 if (Tmp3.getValueType() > MVT::i32)
2620 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
2622 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
2623 Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSExt = true;
2624 Args.push_back(Entry);
2625 Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSExt = false;
2626 Args.push_back(Entry);
2629 } else if (Node->getOpcode() == ISD::MEMCPY ||
2630 Node->getOpcode() == ISD::MEMMOVE) {
2631 Entry.Ty = IntPtrTy;
2632 Entry.Node = Tmp2; Args.push_back(Entry);
2633 Entry.Node = Tmp3; Args.push_back(Entry);
2634 Entry.Node = Tmp4; Args.push_back(Entry);
2635 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
2637 assert(0 && "Unknown op!");
2640 std::pair<SDOperand,SDOperand> CallResult =
2641 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, CallingConv::C, false,
2642 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
2643 Result = CallResult.second;
2650 case ISD::SHL_PARTS:
2651 case ISD::SRA_PARTS:
2652 case ISD::SRL_PARTS: {
2653 SmallVector<SDOperand, 8> Ops;
2654 bool Changed = false;
2655 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2656 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2657 Changed |= Ops.back() != Node->getOperand(i);
2660 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2662 switch (TLI.getOperationAction(Node->getOpcode(),
2663 Node->getValueType(0))) {
2664 default: assert(0 && "This action is not supported yet!");
2665 case TargetLowering::Legal: break;
2666 case TargetLowering::Custom:
2667 Tmp1 = TLI.LowerOperation(Result, DAG);
2669 SDOperand Tmp2, RetVal(0, 0);
2670 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2671 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2672 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2676 assert(RetVal.Val && "Illegal result number");
2682 // Since these produce multiple values, make sure to remember that we
2683 // legalized all of them.
2684 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2685 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2686 return Result.getValue(Op.ResNo);
2708 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2709 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2710 case Expand: assert(0 && "Not possible");
2712 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2715 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2719 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2721 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2722 default: assert(0 && "BinOp legalize operation not supported");
2723 case TargetLowering::Legal: break;
2724 case TargetLowering::Custom:
2725 Tmp1 = TLI.LowerOperation(Result, DAG);
2726 if (Tmp1.Val) Result = Tmp1;
2728 case TargetLowering::Expand: {
2729 MVT::ValueType VT = Op.getValueType();
2731 // See if multiply or divide can be lowered using two-result operations.
2732 SDVTList VTs = DAG.getVTList(VT, VT);
2733 if (Node->getOpcode() == ISD::MUL) {
2734 // We just need the low half of the multiply; try both the signed
2735 // and unsigned forms. If the target supports both SMUL_LOHI and
2736 // UMUL_LOHI, form a preference by checking which forms of plain
2737 // MULH it supports.
2738 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT);
2739 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT);
2740 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT);
2741 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT);
2742 unsigned OpToUse = 0;
2743 if (HasSMUL_LOHI && !HasMULHS) {
2744 OpToUse = ISD::SMUL_LOHI;
2745 } else if (HasUMUL_LOHI && !HasMULHU) {
2746 OpToUse = ISD::UMUL_LOHI;
2747 } else if (HasSMUL_LOHI) {
2748 OpToUse = ISD::SMUL_LOHI;
2749 } else if (HasUMUL_LOHI) {
2750 OpToUse = ISD::UMUL_LOHI;
2753 Result = SDOperand(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).Val, 0);
2757 if (Node->getOpcode() == ISD::MULHS &&
2758 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) {
2759 Result = SDOperand(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
2762 if (Node->getOpcode() == ISD::MULHU &&
2763 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) {
2764 Result = SDOperand(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
2767 if (Node->getOpcode() == ISD::SDIV &&
2768 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
2769 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 0);
2772 if (Node->getOpcode() == ISD::UDIV &&
2773 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
2774 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 0);
2778 // Check to see if we have a libcall for this operator.
2779 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2780 bool isSigned = false;
2781 switch (Node->getOpcode()) {
2784 if (VT == MVT::i32) {
2785 LC = Node->getOpcode() == ISD::UDIV
2786 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
2787 isSigned = Node->getOpcode() == ISD::SDIV;
2791 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
2792 RTLIB::POW_PPCF128);
2796 if (LC != RTLIB::UNKNOWN_LIBCALL) {
2798 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
2802 assert(MVT::isVector(Node->getValueType(0)) &&
2803 "Cannot expand this binary operator!");
2804 // Expand the operation into a bunch of nasty scalar code.
2805 Result = LegalizeOp(UnrollVectorOp(Op));
2808 case TargetLowering::Promote: {
2809 switch (Node->getOpcode()) {
2810 default: assert(0 && "Do not know how to promote this BinOp!");
2814 MVT::ValueType OVT = Node->getValueType(0);
2815 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2816 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
2817 // Bit convert each of the values to the new type.
2818 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
2819 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
2820 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2821 // Bit convert the result back the original type.
2822 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
2830 case ISD::SMUL_LOHI:
2831 case ISD::UMUL_LOHI:
2834 // These nodes will only be produced by target-specific lowering, so
2835 // they shouldn't be here if they aren't legal.
2836 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
2837 "This must be legal!");
2839 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2840 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2841 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2844 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
2845 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2846 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2847 case Expand: assert(0 && "Not possible");
2849 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2852 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2856 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2858 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2859 default: assert(0 && "Operation not supported");
2860 case TargetLowering::Custom:
2861 Tmp1 = TLI.LowerOperation(Result, DAG);
2862 if (Tmp1.Val) Result = Tmp1;
2864 case TargetLowering::Legal: break;
2865 case TargetLowering::Expand: {
2866 // If this target supports fabs/fneg natively and select is cheap,
2867 // do this efficiently.
2868 if (!TLI.isSelectExpensive() &&
2869 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
2870 TargetLowering::Legal &&
2871 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
2872 TargetLowering::Legal) {
2873 // Get the sign bit of the RHS.
2874 MVT::ValueType IVT =
2875 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
2876 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
2877 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
2878 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
2879 // Get the absolute value of the result.
2880 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
2881 // Select between the nabs and abs value based on the sign bit of
2883 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
2884 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
2887 Result = LegalizeOp(Result);
2891 // Otherwise, do bitwise ops!
2892 MVT::ValueType NVT =
2893 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
2894 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
2895 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
2896 Result = LegalizeOp(Result);
2904 Tmp1 = LegalizeOp(Node->getOperand(0));
2905 Tmp2 = LegalizeOp(Node->getOperand(1));
2906 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2907 // Since this produces two values, make sure to remember that we legalized
2909 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2910 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2915 Tmp1 = LegalizeOp(Node->getOperand(0));
2916 Tmp2 = LegalizeOp(Node->getOperand(1));
2917 Tmp3 = LegalizeOp(Node->getOperand(2));
2918 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2919 // Since this produces two values, make sure to remember that we legalized
2921 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2922 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2925 case ISD::BUILD_PAIR: {
2926 MVT::ValueType PairTy = Node->getValueType(0);
2927 // TODO: handle the case where the Lo and Hi operands are not of legal type
2928 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
2929 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
2930 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
2931 case TargetLowering::Promote:
2932 case TargetLowering::Custom:
2933 assert(0 && "Cannot promote/custom this yet!");
2934 case TargetLowering::Legal:
2935 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
2936 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
2938 case TargetLowering::Expand:
2939 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
2940 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
2941 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
2942 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
2943 TLI.getShiftAmountTy()));
2944 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
2953 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2954 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2956 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2957 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
2958 case TargetLowering::Custom:
2961 case TargetLowering::Legal:
2962 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2964 Tmp1 = TLI.LowerOperation(Result, DAG);
2965 if (Tmp1.Val) Result = Tmp1;
2968 case TargetLowering::Expand: {
2969 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
2970 bool isSigned = DivOpc == ISD::SDIV;
2971 MVT::ValueType VT = Node->getValueType(0);
2973 // See if remainder can be lowered using two-result operations.
2974 SDVTList VTs = DAG.getVTList(VT, VT);
2975 if (Node->getOpcode() == ISD::SREM &&
2976 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
2977 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 1);
2980 if (Node->getOpcode() == ISD::UREM &&
2981 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
2982 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 1);
2986 if (MVT::isInteger(VT)) {
2987 if (TLI.getOperationAction(DivOpc, VT) ==
2988 TargetLowering::Legal) {
2990 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
2991 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
2992 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
2993 } else if (MVT::isVector(VT)) {
2994 Result = LegalizeOp(UnrollVectorOp(Op));
2996 assert(VT == MVT::i32 &&
2997 "Cannot expand this binary operator!");
2998 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
2999 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
3001 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
3004 assert(MVT::isFloatingPoint(VT) &&
3005 "remainder op must have integer or floating-point type");
3006 if (MVT::isVector(VT)) {
3007 Result = LegalizeOp(UnrollVectorOp(Op));
3009 // Floating point mod -> fmod libcall.
3010 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
3011 RTLIB::REM_F80, RTLIB::REM_PPCF128);
3013 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3014 false/*sign irrelevant*/, Dummy);
3022 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3023 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3025 MVT::ValueType VT = Node->getValueType(0);
3026 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
3027 default: assert(0 && "This action is not supported yet!");
3028 case TargetLowering::Custom:
3031 case TargetLowering::Legal:
3032 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3033 Result = Result.getValue(0);
3034 Tmp1 = Result.getValue(1);
3037 Tmp2 = TLI.LowerOperation(Result, DAG);
3039 Result = LegalizeOp(Tmp2);
3040 Tmp1 = LegalizeOp(Tmp2.getValue(1));
3044 case TargetLowering::Expand: {
3045 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
3046 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
3047 SV->getValue(), SV->getOffset());
3048 // Increment the pointer, VAList, to the next vaarg
3049 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3050 DAG.getConstant(MVT::getSizeInBits(VT)/8,
3051 TLI.getPointerTy()));
3052 // Store the incremented VAList to the legalized pointer
3053 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
3055 // Load the actual argument out of the pointer VAList
3056 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
3057 Tmp1 = LegalizeOp(Result.getValue(1));
3058 Result = LegalizeOp(Result);
3062 // Since VAARG produces two values, make sure to remember that we
3063 // legalized both of them.
3064 AddLegalizedOperand(SDOperand(Node, 0), Result);
3065 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
3066 return Op.ResNo ? Tmp1 : Result;
3070 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3071 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
3072 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
3074 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
3075 default: assert(0 && "This action is not supported yet!");
3076 case TargetLowering::Custom:
3079 case TargetLowering::Legal:
3080 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
3081 Node->getOperand(3), Node->getOperand(4));
3083 Tmp1 = TLI.LowerOperation(Result, DAG);
3084 if (Tmp1.Val) Result = Tmp1;
3087 case TargetLowering::Expand:
3088 // This defaults to loading a pointer from the input and storing it to the
3089 // output, returning the chain.
3090 SrcValueSDNode *SVD = cast<SrcValueSDNode>(Node->getOperand(3));
3091 SrcValueSDNode *SVS = cast<SrcValueSDNode>(Node->getOperand(4));
3092 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD->getValue(),
3094 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, SVS->getValue(),
3101 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3102 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3104 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
3105 default: assert(0 && "This action is not supported yet!");
3106 case TargetLowering::Custom:
3109 case TargetLowering::Legal:
3110 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3112 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
3113 if (Tmp1.Val) Result = Tmp1;
3116 case TargetLowering::Expand:
3117 Result = Tmp1; // Default to a no-op, return the chain
3123 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3124 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3126 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3128 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
3129 default: assert(0 && "This action is not supported yet!");
3130 case TargetLowering::Legal: break;
3131 case TargetLowering::Custom:
3132 Tmp1 = TLI.LowerOperation(Result, DAG);
3133 if (Tmp1.Val) Result = Tmp1;
3140 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3141 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3142 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3143 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3145 assert(0 && "ROTL/ROTR legalize operation not supported");
3147 case TargetLowering::Legal:
3149 case TargetLowering::Custom:
3150 Tmp1 = TLI.LowerOperation(Result, DAG);
3151 if (Tmp1.Val) Result = Tmp1;
3153 case TargetLowering::Promote:
3154 assert(0 && "Do not know how to promote ROTL/ROTR");
3156 case TargetLowering::Expand:
3157 assert(0 && "Do not know how to expand ROTL/ROTR");
3163 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3164 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3165 case TargetLowering::Custom:
3166 assert(0 && "Cannot custom legalize this yet!");
3167 case TargetLowering::Legal:
3168 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3170 case TargetLowering::Promote: {
3171 MVT::ValueType OVT = Tmp1.getValueType();
3172 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3173 unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT);
3175 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3176 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3177 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3178 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3181 case TargetLowering::Expand:
3182 Result = ExpandBSWAP(Tmp1);
3190 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3191 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3192 case TargetLowering::Custom:
3193 case TargetLowering::Legal:
3194 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3195 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3196 TargetLowering::Custom) {
3197 Tmp1 = TLI.LowerOperation(Result, DAG);
3203 case TargetLowering::Promote: {
3204 MVT::ValueType OVT = Tmp1.getValueType();
3205 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3207 // Zero extend the argument.
3208 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3209 // Perform the larger operation, then subtract if needed.
3210 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
3211 switch (Node->getOpcode()) {
3216 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3217 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
3218 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
3220 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3221 DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1);
3224 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3225 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3226 DAG.getConstant(MVT::getSizeInBits(NVT) -
3227 MVT::getSizeInBits(OVT), NVT));
3232 case TargetLowering::Expand:
3233 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
3244 Tmp1 = LegalizeOp(Node->getOperand(0));
3245 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3246 case TargetLowering::Promote:
3247 case TargetLowering::Custom:
3250 case TargetLowering::Legal:
3251 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3253 Tmp1 = TLI.LowerOperation(Result, DAG);
3254 if (Tmp1.Val) Result = Tmp1;
3257 case TargetLowering::Expand:
3258 switch (Node->getOpcode()) {
3259 default: assert(0 && "Unreachable!");
3261 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3262 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3263 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
3266 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3267 MVT::ValueType VT = Node->getValueType(0);
3268 Tmp2 = DAG.getConstantFP(0.0, VT);
3269 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
3270 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
3271 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
3277 MVT::ValueType VT = Node->getValueType(0);
3279 // Expand unsupported unary vector operators by unrolling them.
3280 if (MVT::isVector(VT)) {
3281 Result = LegalizeOp(UnrollVectorOp(Op));
3285 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3286 switch(Node->getOpcode()) {
3288 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3289 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
3292 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
3293 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
3296 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
3297 RTLIB::COS_F80, RTLIB::COS_PPCF128);
3299 default: assert(0 && "Unreachable!");
3302 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3303 false/*sign irrelevant*/, Dummy);
3311 MVT::ValueType VT = Node->getValueType(0);
3313 // Expand unsupported unary vector operators by unrolling them.
3314 if (MVT::isVector(VT)) {
3315 Result = LegalizeOp(UnrollVectorOp(Op));
3319 // We always lower FPOWI into a libcall. No target support for it yet.
3320 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
3321 RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
3323 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3324 false/*sign irrelevant*/, Dummy);
3327 case ISD::BIT_CONVERT:
3328 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3329 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
3330 } else if (MVT::isVector(Op.getOperand(0).getValueType())) {
3331 // The input has to be a vector type, we have to either scalarize it, pack
3332 // it, or convert it based on whether the input vector type is legal.
3333 SDNode *InVal = Node->getOperand(0).Val;
3334 int InIx = Node->getOperand(0).ResNo;
3335 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx));
3336 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx));
3338 // Figure out if there is a simple type corresponding to this Vector
3339 // type. If so, convert to the vector type.
3340 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
3341 if (TLI.isTypeLegal(TVT)) {
3342 // Turn this into a bit convert of the vector input.
3343 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3344 LegalizeOp(Node->getOperand(0)));
3346 } else if (NumElems == 1) {
3347 // Turn this into a bit convert of the scalar input.
3348 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3349 ScalarizeVectorOp(Node->getOperand(0)));
3352 // FIXME: UNIMP! Store then reload
3353 assert(0 && "Cast from unsupported vector type not implemented yet!");
3356 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3357 Node->getOperand(0).getValueType())) {
3358 default: assert(0 && "Unknown operation action!");
3359 case TargetLowering::Expand:
3360 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
3362 case TargetLowering::Legal:
3363 Tmp1 = LegalizeOp(Node->getOperand(0));
3364 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3370 // Conversion operators. The source and destination have different types.
3371 case ISD::SINT_TO_FP:
3372 case ISD::UINT_TO_FP: {
3373 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
3374 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3376 switch (TLI.getOperationAction(Node->getOpcode(),
3377 Node->getOperand(0).getValueType())) {
3378 default: assert(0 && "Unknown operation action!");
3379 case TargetLowering::Custom:
3382 case TargetLowering::Legal:
3383 Tmp1 = LegalizeOp(Node->getOperand(0));
3384 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3386 Tmp1 = TLI.LowerOperation(Result, DAG);
3387 if (Tmp1.Val) Result = Tmp1;
3390 case TargetLowering::Expand:
3391 Result = ExpandLegalINT_TO_FP(isSigned,
3392 LegalizeOp(Node->getOperand(0)),
3393 Node->getValueType(0));
3395 case TargetLowering::Promote:
3396 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
3397 Node->getValueType(0),
3403 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
3404 Node->getValueType(0), Node->getOperand(0));
3407 Tmp1 = PromoteOp(Node->getOperand(0));
3409 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
3410 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
3412 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
3413 Node->getOperand(0).getValueType());
3415 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3416 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
3422 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3424 Tmp1 = LegalizeOp(Node->getOperand(0));
3425 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3428 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3430 // Since the result is legal, we should just be able to truncate the low
3431 // part of the source.
3432 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
3435 Result = PromoteOp(Node->getOperand(0));
3436 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
3441 case ISD::FP_TO_SINT:
3442 case ISD::FP_TO_UINT:
3443 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3445 Tmp1 = LegalizeOp(Node->getOperand(0));
3447 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
3448 default: assert(0 && "Unknown operation action!");
3449 case TargetLowering::Custom:
3452 case TargetLowering::Legal:
3453 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3455 Tmp1 = TLI.LowerOperation(Result, DAG);
3456 if (Tmp1.Val) Result = Tmp1;
3459 case TargetLowering::Promote:
3460 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
3461 Node->getOpcode() == ISD::FP_TO_SINT);
3463 case TargetLowering::Expand:
3464 if (Node->getOpcode() == ISD::FP_TO_UINT) {
3465 SDOperand True, False;
3466 MVT::ValueType VT = Node->getOperand(0).getValueType();
3467 MVT::ValueType NVT = Node->getValueType(0);
3468 unsigned ShiftAmt = MVT::getSizeInBits(NVT)-1;
3469 const uint64_t zero[] = {0, 0};
3470 APFloat apf = APFloat(APInt(MVT::getSizeInBits(VT), 2, zero));
3471 uint64_t x = 1ULL << ShiftAmt;
3472 (void)apf.convertFromZeroExtendedInteger
3473 (&x, MVT::getSizeInBits(NVT), false, APFloat::rmNearestTiesToEven);
3474 Tmp2 = DAG.getConstantFP(apf, VT);
3475 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
3476 Node->getOperand(0), Tmp2, ISD::SETLT);
3477 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
3478 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
3479 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
3481 False = DAG.getNode(ISD::XOR, NVT, False,
3482 DAG.getConstant(1ULL << ShiftAmt, NVT));
3483 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
3486 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
3492 MVT::ValueType VT = Op.getValueType();
3493 MVT::ValueType OVT = Node->getOperand(0).getValueType();
3494 // Convert ppcf128 to i32
3495 if (OVT == MVT::ppcf128 && VT == MVT::i32) {
3496 if (Node->getOpcode()==ISD::FP_TO_SINT)
3497 Result = DAG.getNode(ISD::FP_TO_SINT, VT,
3498 DAG.getNode(ISD::FP_ROUND, MVT::f64,
3499 (DAG.getNode(ISD::FP_ROUND_INREG,
3500 MVT::ppcf128, Node->getOperand(0),
3501 DAG.getValueType(MVT::f64)))));
3503 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
3504 APFloat apf = APFloat(APInt(128, 2, TwoE31));
3505 Tmp2 = DAG.getConstantFP(apf, OVT);
3506 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
3507 // FIXME: generated code sucks.
3508 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2,
3509 DAG.getNode(ISD::ADD, MVT::i32,
3510 DAG.getNode(ISD::FP_TO_SINT, VT,
3511 DAG.getNode(ISD::FSUB, OVT,
3512 Node->getOperand(0), Tmp2)),
3513 DAG.getConstant(0x80000000, MVT::i32)),
3514 DAG.getNode(ISD::FP_TO_SINT, VT,
3515 Node->getOperand(0)),
3516 DAG.getCondCode(ISD::SETGE));
3520 // Convert f32 / f64 to i32 / i64.
3521 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3522 switch (Node->getOpcode()) {
3523 case ISD::FP_TO_SINT: {
3524 if (OVT == MVT::f32)
3525 LC = (VT == MVT::i32)
3526 ? RTLIB::FPTOSINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3527 else if (OVT == MVT::f64)
3528 LC = (VT == MVT::i32)
3529 ? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3530 else if (OVT == MVT::f80) {
3531 assert(VT == MVT::i64);
3532 LC = RTLIB::FPTOSINT_F80_I64;
3534 else if (OVT == MVT::ppcf128) {
3535 assert(VT == MVT::i64);
3536 LC = RTLIB::FPTOSINT_PPCF128_I64;
3540 case ISD::FP_TO_UINT: {
3541 if (OVT == MVT::f32)
3542 LC = (VT == MVT::i32)
3543 ? RTLIB::FPTOUINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3544 else if (OVT == MVT::f64)
3545 LC = (VT == MVT::i32)
3546 ? RTLIB::FPTOUINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3547 else if (OVT == MVT::f80) {
3548 LC = (VT == MVT::i32)
3549 ? RTLIB::FPTOUINT_F80_I32 : RTLIB::FPTOUINT_F80_I64;
3551 else if (OVT == MVT::ppcf128) {
3552 assert(VT == MVT::i64);
3553 LC = RTLIB::FPTOUINT_PPCF128_I64;
3557 default: assert(0 && "Unreachable!");
3560 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3561 false/*sign irrelevant*/, Dummy);
3565 Tmp1 = PromoteOp(Node->getOperand(0));
3566 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
3567 Result = LegalizeOp(Result);
3572 case ISD::FP_EXTEND:
3573 case ISD::FP_ROUND: {
3574 MVT::ValueType newVT = Op.getValueType();
3575 MVT::ValueType oldVT = Op.getOperand(0).getValueType();
3576 if (TLI.getConvertAction(oldVT, newVT) == TargetLowering::Expand) {
3577 if (Node->getOpcode() == ISD::FP_ROUND && oldVT == MVT::ppcf128) {
3579 ExpandOp(Node->getOperand(0), Lo, Hi);
3580 if (newVT == MVT::f64)
3583 Result = DAG.getNode(ISD::FP_ROUND, newVT, Hi);
3586 // The only other way we can lower this is to turn it into a STORE,
3587 // LOAD pair, targetting a temporary location (a stack slot).
3589 // NOTE: there is a choice here between constantly creating new stack
3590 // slots and always reusing the same one. We currently always create
3591 // new ones, as reuse may inhibit scheduling.
3592 MVT::ValueType slotVT =
3593 (Node->getOpcode() == ISD::FP_EXTEND) ? oldVT : newVT;
3594 const Type *Ty = MVT::getTypeForValueType(slotVT);
3595 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
3596 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
3597 MachineFunction &MF = DAG.getMachineFunction();
3599 MF.getFrameInfo()->CreateStackObject(TySize, Align);
3600 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3601 if (Node->getOpcode() == ISD::FP_EXTEND) {
3602 Result = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0),
3603 StackSlot, NULL, 0);
3604 Result = DAG.getExtLoad(ISD::EXTLOAD, newVT,
3605 Result, StackSlot, NULL, 0, oldVT);
3607 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0),
3608 StackSlot, NULL, 0, newVT);
3609 Result = DAG.getLoad(newVT, Result, StackSlot, NULL, 0);
3616 case ISD::ANY_EXTEND:
3617 case ISD::ZERO_EXTEND:
3618 case ISD::SIGN_EXTEND:
3619 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3620 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3622 Tmp1 = LegalizeOp(Node->getOperand(0));
3623 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3626 switch (Node->getOpcode()) {
3627 case ISD::ANY_EXTEND:
3628 Tmp1 = PromoteOp(Node->getOperand(0));
3629 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
3631 case ISD::ZERO_EXTEND:
3632 Result = PromoteOp(Node->getOperand(0));
3633 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3634 Result = DAG.getZeroExtendInReg(Result,
3635 Node->getOperand(0).getValueType());
3637 case ISD::SIGN_EXTEND:
3638 Result = PromoteOp(Node->getOperand(0));
3639 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3640 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3642 DAG.getValueType(Node->getOperand(0).getValueType()));
3644 case ISD::FP_EXTEND:
3645 Result = PromoteOp(Node->getOperand(0));
3646 if (Result.getValueType() != Op.getValueType())
3647 // Dynamically dead while we have only 2 FP types.
3648 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result);
3651 Result = PromoteOp(Node->getOperand(0));
3652 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
3657 case ISD::FP_ROUND_INREG:
3658 case ISD::SIGN_EXTEND_INREG: {
3659 Tmp1 = LegalizeOp(Node->getOperand(0));
3660 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3662 // If this operation is not supported, convert it to a shl/shr or load/store
3664 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
3665 default: assert(0 && "This action not supported for this op yet!");
3666 case TargetLowering::Legal:
3667 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3669 case TargetLowering::Expand:
3670 // If this is an integer extend and shifts are supported, do that.
3671 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
3672 // NOTE: we could fall back on load/store here too for targets without
3673 // SAR. However, it is doubtful that any exist.
3674 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
3675 MVT::getSizeInBits(ExtraVT);
3676 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
3677 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
3678 Node->getOperand(0), ShiftCst);
3679 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
3681 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
3682 // The only way we can lower this is to turn it into a TRUNCSTORE,
3683 // EXTLOAD pair, targetting a temporary location (a stack slot).
3685 // NOTE: there is a choice here between constantly creating new stack
3686 // slots and always reusing the same one. We currently always create
3687 // new ones, as reuse may inhibit scheduling.
3688 const Type *Ty = MVT::getTypeForValueType(ExtraVT);
3689 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
3690 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
3691 MachineFunction &MF = DAG.getMachineFunction();
3693 MF.getFrameInfo()->CreateStackObject(TySize, Align);
3694 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3695 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0),
3696 StackSlot, NULL, 0, ExtraVT);
3697 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
3698 Result, StackSlot, NULL, 0, ExtraVT);
3700 assert(0 && "Unknown op");
3706 case ISD::TRAMPOLINE: {
3708 for (unsigned i = 0; i != 6; ++i)
3709 Ops[i] = LegalizeOp(Node->getOperand(i));
3710 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
3711 // The only option for this node is to custom lower it.
3712 Result = TLI.LowerOperation(Result, DAG);
3713 assert(Result.Val && "Should always custom lower!");
3715 // Since trampoline produces two values, make sure to remember that we
3716 // legalized both of them.
3717 Tmp1 = LegalizeOp(Result.getValue(1));
3718 Result = LegalizeOp(Result);
3719 AddLegalizedOperand(SDOperand(Node, 0), Result);
3720 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
3721 return Op.ResNo ? Tmp1 : Result;
3723 case ISD::FLT_ROUNDS: {
3724 MVT::ValueType VT = Node->getValueType(0);
3725 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
3726 default: assert(0 && "This action not supported for this op yet!");
3727 case TargetLowering::Custom:
3728 Result = TLI.LowerOperation(Op, DAG);
3729 if (Result.Val) break;
3731 case TargetLowering::Legal:
3732 // If this operation is not supported, lower it to constant 1
3733 Result = DAG.getConstant(1, VT);
3738 MVT::ValueType VT = Node->getValueType(0);
3739 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
3740 default: assert(0 && "This action not supported for this op yet!");
3741 case TargetLowering::Custom:
3742 Result = TLI.LowerOperation(Op, DAG);
3743 if (Result.Val) break;
3745 case TargetLowering::Legal:
3746 // If this operation is not supported, lower it to 'abort()' call
3747 SDOperand Chain = LegalizeOp(Node->getOperand(0));
3748 TargetLowering::ArgListTy Args;
3749 std::pair<SDOperand,SDOperand> CallResult =
3750 TLI.LowerCallTo(Chain, Type::VoidTy, false, false, CallingConv::C, false,
3751 DAG.getExternalSymbol("abort", MVT::Other), Args, DAG);
3752 Result = CallResult.second;
3758 assert(Result.getValueType() == Op.getValueType() &&
3759 "Bad legalization!");
3761 // Make sure that the generated code is itself legal.
3763 Result = LegalizeOp(Result);
3765 // Note that LegalizeOp may be reentered even from single-use nodes, which
3766 // means that we always must cache transformed nodes.
3767 AddLegalizedOperand(Op, Result);
3771 /// PromoteOp - Given an operation that produces a value in an invalid type,
3772 /// promote it to compute the value into a larger type. The produced value will
3773 /// have the correct bits for the low portion of the register, but no guarantee
3774 /// is made about the top bits: it may be zero, sign-extended, or garbage.
3775 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
3776 MVT::ValueType VT = Op.getValueType();
3777 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3778 assert(getTypeAction(VT) == Promote &&
3779 "Caller should expand or legalize operands that are not promotable!");
3780 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
3781 "Cannot promote to smaller type!");
3783 SDOperand Tmp1, Tmp2, Tmp3;
3785 SDNode *Node = Op.Val;
3787 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
3788 if (I != PromotedNodes.end()) return I->second;
3790 switch (Node->getOpcode()) {
3791 case ISD::CopyFromReg:
3792 assert(0 && "CopyFromReg must be legal!");
3795 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
3797 assert(0 && "Do not know how to promote this operator!");
3800 Result = DAG.getNode(ISD::UNDEF, NVT);
3804 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
3806 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
3807 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
3809 case ISD::ConstantFP:
3810 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
3811 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
3815 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
3816 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
3817 Node->getOperand(1), Node->getOperand(2));
3821 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3823 Result = LegalizeOp(Node->getOperand(0));
3824 assert(Result.getValueType() >= NVT &&
3825 "This truncation doesn't make sense!");
3826 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
3827 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
3830 // The truncation is not required, because we don't guarantee anything
3831 // about high bits anyway.
3832 Result = PromoteOp(Node->getOperand(0));
3835 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3836 // Truncate the low part of the expanded value to the result type
3837 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
3840 case ISD::SIGN_EXTEND:
3841 case ISD::ZERO_EXTEND:
3842 case ISD::ANY_EXTEND:
3843 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3844 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
3846 // Input is legal? Just do extend all the way to the larger type.
3847 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
3850 // Promote the reg if it's smaller.
3851 Result = PromoteOp(Node->getOperand(0));
3852 // The high bits are not guaranteed to be anything. Insert an extend.
3853 if (Node->getOpcode() == ISD::SIGN_EXTEND)
3854 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3855 DAG.getValueType(Node->getOperand(0).getValueType()));
3856 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
3857 Result = DAG.getZeroExtendInReg(Result,
3858 Node->getOperand(0).getValueType());
3862 case ISD::BIT_CONVERT:
3863 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
3864 Result = PromoteOp(Result);
3867 case ISD::FP_EXTEND:
3868 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
3870 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3871 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
3872 case Promote: assert(0 && "Unreachable with 2 FP types!");
3874 // Input is legal? Do an FP_ROUND_INREG.
3875 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
3876 DAG.getValueType(VT));
3881 case ISD::SINT_TO_FP:
3882 case ISD::UINT_TO_FP:
3883 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3885 // No extra round required here.
3886 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
3890 Result = PromoteOp(Node->getOperand(0));
3891 if (Node->getOpcode() == ISD::SINT_TO_FP)
3892 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3894 DAG.getValueType(Node->getOperand(0).getValueType()));
3896 Result = DAG.getZeroExtendInReg(Result,
3897 Node->getOperand(0).getValueType());
3898 // No extra round required here.
3899 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
3902 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
3903 Node->getOperand(0));
3904 // Round if we cannot tolerate excess precision.
3905 if (NoExcessFPPrecision)
3906 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3907 DAG.getValueType(VT));
3912 case ISD::SIGN_EXTEND_INREG:
3913 Result = PromoteOp(Node->getOperand(0));
3914 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3915 Node->getOperand(1));
3917 case ISD::FP_TO_SINT:
3918 case ISD::FP_TO_UINT:
3919 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3922 Tmp1 = Node->getOperand(0);
3925 // The input result is prerounded, so we don't have to do anything
3927 Tmp1 = PromoteOp(Node->getOperand(0));
3930 // If we're promoting a UINT to a larger size, check to see if the new node
3931 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
3932 // we can use that instead. This allows us to generate better code for
3933 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
3934 // legal, such as PowerPC.
3935 if (Node->getOpcode() == ISD::FP_TO_UINT &&
3936 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
3937 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
3938 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
3939 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
3941 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3947 Tmp1 = PromoteOp(Node->getOperand(0));
3948 assert(Tmp1.getValueType() == NVT);
3949 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3950 // NOTE: we do not have to do any extra rounding here for
3951 // NoExcessFPPrecision, because we know the input will have the appropriate
3952 // precision, and these operations don't modify precision at all.
3958 Tmp1 = PromoteOp(Node->getOperand(0));
3959 assert(Tmp1.getValueType() == NVT);
3960 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3961 if (NoExcessFPPrecision)
3962 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3963 DAG.getValueType(VT));
3967 // Promote f32 powi to f64 powi. Note that this could insert a libcall
3968 // directly as well, which may be better.
3969 Tmp1 = PromoteOp(Node->getOperand(0));
3970 assert(Tmp1.getValueType() == NVT);
3971 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1));
3972 if (NoExcessFPPrecision)
3973 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3974 DAG.getValueType(VT));
3984 // The input may have strange things in the top bits of the registers, but
3985 // these operations don't care. They may have weird bits going out, but
3986 // that too is okay if they are integer operations.
3987 Tmp1 = PromoteOp(Node->getOperand(0));
3988 Tmp2 = PromoteOp(Node->getOperand(1));
3989 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3990 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3995 Tmp1 = PromoteOp(Node->getOperand(0));
3996 Tmp2 = PromoteOp(Node->getOperand(1));
3997 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3998 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4000 // Floating point operations will give excess precision that we may not be
4001 // able to tolerate. If we DO allow excess precision, just leave it,
4002 // otherwise excise it.
4003 // FIXME: Why would we need to round FP ops more than integer ones?
4004 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
4005 if (NoExcessFPPrecision)
4006 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4007 DAG.getValueType(VT));
4012 // These operators require that their input be sign extended.
4013 Tmp1 = PromoteOp(Node->getOperand(0));
4014 Tmp2 = PromoteOp(Node->getOperand(1));
4015 if (MVT::isInteger(NVT)) {
4016 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4017 DAG.getValueType(VT));
4018 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4019 DAG.getValueType(VT));
4021 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4023 // Perform FP_ROUND: this is probably overly pessimistic.
4024 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
4025 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4026 DAG.getValueType(VT));
4030 case ISD::FCOPYSIGN:
4031 // These operators require that their input be fp extended.
4032 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4034 Tmp1 = LegalizeOp(Node->getOperand(0));
4037 Tmp1 = PromoteOp(Node->getOperand(0));
4040 assert(0 && "not implemented");
4042 switch (getTypeAction(Node->getOperand(1).getValueType())) {
4044 Tmp2 = LegalizeOp(Node->getOperand(1));
4047 Tmp2 = PromoteOp(Node->getOperand(1));
4050 assert(0 && "not implemented");
4052 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4054 // Perform FP_ROUND: this is probably overly pessimistic.
4055 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
4056 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4057 DAG.getValueType(VT));
4062 // These operators require that their input be zero extended.
4063 Tmp1 = PromoteOp(Node->getOperand(0));
4064 Tmp2 = PromoteOp(Node->getOperand(1));
4065 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
4066 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4067 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4068 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4072 Tmp1 = PromoteOp(Node->getOperand(0));
4073 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
4076 // The input value must be properly sign extended.
4077 Tmp1 = PromoteOp(Node->getOperand(0));
4078 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4079 DAG.getValueType(VT));
4080 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
4083 // The input value must be properly zero extended.
4084 Tmp1 = PromoteOp(Node->getOperand(0));
4085 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4086 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
4090 Tmp1 = Node->getOperand(0); // Get the chain.
4091 Tmp2 = Node->getOperand(1); // Get the pointer.
4092 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
4093 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
4094 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
4096 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
4097 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
4098 SV->getValue(), SV->getOffset());
4099 // Increment the pointer, VAList, to the next vaarg
4100 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
4101 DAG.getConstant(MVT::getSizeInBits(VT)/8,
4102 TLI.getPointerTy()));
4103 // Store the incremented VAList to the legalized pointer
4104 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
4106 // Load the actual argument out of the pointer VAList
4107 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
4109 // Remember that we legalized the chain.
4110 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4114 LoadSDNode *LD = cast<LoadSDNode>(Node);
4115 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
4116 ? ISD::EXTLOAD : LD->getExtensionType();
4117 Result = DAG.getExtLoad(ExtType, NVT,
4118 LD->getChain(), LD->getBasePtr(),
4119 LD->getSrcValue(), LD->getSrcValueOffset(),
4122 LD->getAlignment());
4123 // Remember that we legalized the chain.
4124 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4128 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
4129 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
4130 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
4132 case ISD::SELECT_CC:
4133 Tmp2 = PromoteOp(Node->getOperand(2)); // True
4134 Tmp3 = PromoteOp(Node->getOperand(3)); // False
4135 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4136 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
4139 Tmp1 = Node->getOperand(0);
4140 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
4141 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
4142 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
4143 DAG.getConstant(MVT::getSizeInBits(NVT) -
4144 MVT::getSizeInBits(VT),
4145 TLI.getShiftAmountTy()));
4150 // Zero extend the argument
4151 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4152 // Perform the larger operation, then subtract if needed.
4153 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4154 switch(Node->getOpcode()) {
4159 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
4160 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
4161 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
4163 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
4164 DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1);
4167 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4168 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
4169 DAG.getConstant(MVT::getSizeInBits(NVT) -
4170 MVT::getSizeInBits(VT), NVT));
4174 case ISD::EXTRACT_SUBVECTOR:
4175 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
4177 case ISD::EXTRACT_VECTOR_ELT:
4178 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
4182 assert(Result.Val && "Didn't set a result!");
4184 // Make sure the result is itself legal.
4185 Result = LegalizeOp(Result);
4187 // Remember that we promoted this!
4188 AddPromotedOperand(Op, Result);
4192 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
4193 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
4194 /// based on the vector type. The return type of this matches the element type
4195 /// of the vector, which may not be legal for the target.
4196 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
4197 // We know that operand #0 is the Vec vector. If the index is a constant
4198 // or if the invec is a supported hardware type, we can use it. Otherwise,
4199 // lower to a store then an indexed load.
4200 SDOperand Vec = Op.getOperand(0);
4201 SDOperand Idx = Op.getOperand(1);
4203 MVT::ValueType TVT = Vec.getValueType();
4204 unsigned NumElems = MVT::getVectorNumElements(TVT);
4206 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
4207 default: assert(0 && "This action is not supported yet!");
4208 case TargetLowering::Custom: {
4209 Vec = LegalizeOp(Vec);
4210 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4211 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG);
4216 case TargetLowering::Legal:
4217 if (isTypeLegal(TVT)) {
4218 Vec = LegalizeOp(Vec);
4219 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4223 case TargetLowering::Expand:
4227 if (NumElems == 1) {
4228 // This must be an access of the only element. Return it.
4229 Op = ScalarizeVectorOp(Vec);
4230 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
4231 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4233 SplitVectorOp(Vec, Lo, Hi);
4234 if (CIdx->getValue() < NumElems/2) {
4238 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2,
4239 Idx.getValueType());
4242 // It's now an extract from the appropriate high or low part. Recurse.
4243 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4244 Op = ExpandEXTRACT_VECTOR_ELT(Op);
4246 // Store the value to a temporary stack slot, then LOAD the scalar
4247 // element back out.
4248 SDOperand StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
4249 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
4251 // Add the offset to the index.
4252 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
4253 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
4254 DAG.getConstant(EltSize, Idx.getValueType()));
4256 if (MVT::getSizeInBits(Idx.getValueType()) >
4257 MVT::getSizeInBits(TLI.getPointerTy()))
4258 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx);
4260 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
4262 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
4264 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
4269 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
4270 /// we assume the operation can be split if it is not already legal.
4271 SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) {
4272 // We know that operand #0 is the Vec vector. For now we assume the index
4273 // is a constant and that the extracted result is a supported hardware type.
4274 SDOperand Vec = Op.getOperand(0);
4275 SDOperand Idx = LegalizeOp(Op.getOperand(1));
4277 unsigned NumElems = MVT::getVectorNumElements(Vec.getValueType());
4279 if (NumElems == MVT::getVectorNumElements(Op.getValueType())) {
4280 // This must be an access of the desired vector length. Return it.
4284 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4286 SplitVectorOp(Vec, Lo, Hi);
4287 if (CIdx->getValue() < NumElems/2) {
4291 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
4294 // It's now an extract from the appropriate high or low part. Recurse.
4295 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4296 return ExpandEXTRACT_SUBVECTOR(Op);
4299 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
4300 /// with condition CC on the current target. This usually involves legalizing
4301 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
4302 /// there may be no choice but to create a new SetCC node to represent the
4303 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
4304 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
4305 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
4308 SDOperand Tmp1, Tmp2, Tmp3, Result;
4310 switch (getTypeAction(LHS.getValueType())) {
4312 Tmp1 = LegalizeOp(LHS); // LHS
4313 Tmp2 = LegalizeOp(RHS); // RHS
4316 Tmp1 = PromoteOp(LHS); // LHS
4317 Tmp2 = PromoteOp(RHS); // RHS
4319 // If this is an FP compare, the operands have already been extended.
4320 if (MVT::isInteger(LHS.getValueType())) {
4321 MVT::ValueType VT = LHS.getValueType();
4322 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4324 // Otherwise, we have to insert explicit sign or zero extends. Note
4325 // that we could insert sign extends for ALL conditions, but zero extend
4326 // is cheaper on many machines (an AND instead of two shifts), so prefer
4328 switch (cast<CondCodeSDNode>(CC)->get()) {
4329 default: assert(0 && "Unknown integer comparison!");
4336 // ALL of these operations will work if we either sign or zero extend
4337 // the operands (including the unsigned comparisons!). Zero extend is
4338 // usually a simpler/cheaper operation, so prefer it.
4339 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4340 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4346 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4347 DAG.getValueType(VT));
4348 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4349 DAG.getValueType(VT));
4355 MVT::ValueType VT = LHS.getValueType();
4356 if (VT == MVT::f32 || VT == MVT::f64) {
4357 // Expand into one or more soft-fp libcall(s).
4358 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL;
4359 switch (cast<CondCodeSDNode>(CC)->get()) {
4362 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4366 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
4370 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4374 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4378 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4382 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4385 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4388 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
4391 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4392 switch (cast<CondCodeSDNode>(CC)->get()) {
4394 // SETONE = SETOLT | SETOGT
4395 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4398 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4401 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4404 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4407 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4410 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4412 default: assert(0 && "Unsupported FP setcc!");
4417 Tmp1 = ExpandLibCall(TLI.getLibcallName(LC1),
4418 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4419 false /*sign irrelevant*/, Dummy);
4420 Tmp2 = DAG.getConstant(0, MVT::i32);
4421 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
4422 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
4423 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC);
4424 LHS = ExpandLibCall(TLI.getLibcallName(LC2),
4425 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4426 false /*sign irrelevant*/, Dummy);
4427 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2,
4428 DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
4429 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4437 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
4438 ExpandOp(LHS, LHSLo, LHSHi);
4439 ExpandOp(RHS, RHSLo, RHSHi);
4440 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
4442 if (VT==MVT::ppcf128) {
4443 // FIXME: This generated code sucks. We want to generate
4444 // FCMP crN, hi1, hi2
4446 // FCMP crN, lo1, lo2
4447 // The following can be improved, but not that much.
4448 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
4449 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, CCCode);
4450 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4451 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETNE);
4452 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, CCCode);
4453 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4454 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
4463 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
4464 if (RHSCST->isAllOnesValue()) {
4465 // Comparison to -1.
4466 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
4471 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
4472 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
4473 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4474 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
4477 // If this is a comparison of the sign bit, just look at the top part.
4479 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
4480 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
4481 CST->getValue() == 0) || // X < 0
4482 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
4483 CST->isAllOnesValue())) { // X > -1
4489 // FIXME: This generated code sucks.
4490 ISD::CondCode LowCC;
4492 default: assert(0 && "Unknown integer setcc!");
4494 case ISD::SETULT: LowCC = ISD::SETULT; break;
4496 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
4498 case ISD::SETULE: LowCC = ISD::SETULE; break;
4500 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
4503 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
4504 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
4505 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
4507 // NOTE: on targets without efficient SELECT of bools, we can always use
4508 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
4509 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
4510 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC,
4511 false, DagCombineInfo);
4513 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
4514 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
4515 CCCode, false, DagCombineInfo);
4517 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi,CC);
4519 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
4520 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
4521 if ((Tmp1C && Tmp1C->getValue() == 0) ||
4522 (Tmp2C && Tmp2C->getValue() == 0 &&
4523 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
4524 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
4525 (Tmp2C && Tmp2C->getValue() == 1 &&
4526 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
4527 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
4528 // low part is known false, returns high part.
4529 // For LE / GE, if high part is known false, ignore the low part.
4530 // For LT / GT, if high part is known true, ignore the low part.
4534 Result = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
4535 ISD::SETEQ, false, DagCombineInfo);
4537 Result=DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
4538 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
4539 Result, Tmp1, Tmp2));
4550 /// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination.
4551 /// The resultant code need not be legal. Note that SrcOp is the input operand
4552 /// to the BIT_CONVERT, not the BIT_CONVERT node itself.
4553 SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT,
4555 // Create the stack frame object.
4556 SDOperand FIPtr = DAG.CreateStackTemporary(DestVT);
4558 // Emit a store to the stack slot.
4559 SDOperand Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0);
4560 // Result is a load from the stack slot.
4561 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0);
4564 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
4565 // Create a vector sized/aligned stack slot, store the value to element #0,
4566 // then load the whole vector back out.
4567 SDOperand StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
4568 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
4570 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, NULL, 0);
4574 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
4575 /// support the operation, but do support the resultant vector type.
4576 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
4578 // If the only non-undef value is the low element, turn this into a
4579 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
4580 unsigned NumElems = Node->getNumOperands();
4581 bool isOnlyLowElement = true;
4582 SDOperand SplatValue = Node->getOperand(0);
4583 std::map<SDOperand, std::vector<unsigned> > Values;
4584 Values[SplatValue].push_back(0);
4585 bool isConstant = true;
4586 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
4587 SplatValue.getOpcode() != ISD::UNDEF)
4590 for (unsigned i = 1; i < NumElems; ++i) {
4591 SDOperand V = Node->getOperand(i);
4592 Values[V].push_back(i);
4593 if (V.getOpcode() != ISD::UNDEF)
4594 isOnlyLowElement = false;
4595 if (SplatValue != V)
4596 SplatValue = SDOperand(0,0);
4598 // If this isn't a constant element or an undef, we can't use a constant
4600 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
4601 V.getOpcode() != ISD::UNDEF)
4605 if (isOnlyLowElement) {
4606 // If the low element is an undef too, then this whole things is an undef.
4607 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
4608 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
4609 // Otherwise, turn this into a scalar_to_vector node.
4610 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4611 Node->getOperand(0));
4614 // If all elements are constants, create a load from the constant pool.
4616 MVT::ValueType VT = Node->getValueType(0);
4618 MVT::getTypeForValueType(Node->getOperand(0).getValueType());
4619 std::vector<Constant*> CV;
4620 for (unsigned i = 0, e = NumElems; i != e; ++i) {
4621 if (ConstantFPSDNode *V =
4622 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
4623 CV.push_back(ConstantFP::get(OpNTy, V->getValueAPF()));
4624 } else if (ConstantSDNode *V =
4625 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
4626 CV.push_back(ConstantInt::get(OpNTy, V->getValue()));
4628 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
4629 CV.push_back(UndefValue::get(OpNTy));
4632 Constant *CP = ConstantVector::get(CV);
4633 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
4634 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
4637 if (SplatValue.Val) { // Splat of one value?
4638 // Build the shuffle constant vector: <0, 0, 0, 0>
4639 MVT::ValueType MaskVT =
4640 MVT::getIntVectorWithNumElements(NumElems);
4641 SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT));
4642 std::vector<SDOperand> ZeroVec(NumElems, Zero);
4643 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4644 &ZeroVec[0], ZeroVec.size());
4646 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4647 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
4648 // Get the splatted value into the low element of a vector register.
4649 SDOperand LowValVec =
4650 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
4652 // Return shuffle(LowValVec, undef, <0,0,0,0>)
4653 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
4654 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
4659 // If there are only two unique elements, we may be able to turn this into a
4661 if (Values.size() == 2) {
4662 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
4663 MVT::ValueType MaskVT =
4664 MVT::getIntVectorWithNumElements(NumElems);
4665 std::vector<SDOperand> MaskVec(NumElems);
4667 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
4668 E = Values.end(); I != E; ++I) {
4669 for (std::vector<unsigned>::iterator II = I->second.begin(),
4670 EE = I->second.end(); II != EE; ++II)
4671 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorElementType(MaskVT));
4674 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4675 &MaskVec[0], MaskVec.size());
4677 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4678 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
4679 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
4680 SmallVector<SDOperand, 8> Ops;
4681 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
4682 E = Values.end(); I != E; ++I) {
4683 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4687 Ops.push_back(ShuffleMask);
4689 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
4690 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0),
4691 &Ops[0], Ops.size());
4695 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
4696 // aligned object on the stack, store each element into it, then load
4697 // the result as a vector.
4698 MVT::ValueType VT = Node->getValueType(0);
4699 // Create the stack frame object.
4700 SDOperand FIPtr = DAG.CreateStackTemporary(VT);
4702 // Emit a store of each element to the stack slot.
4703 SmallVector<SDOperand, 8> Stores;
4704 unsigned TypeByteSize =
4705 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
4706 // Store (in the right endianness) the elements to memory.
4707 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
4708 // Ignore undef elements.
4709 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
4711 unsigned Offset = TypeByteSize*i;
4713 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
4714 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
4716 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
4720 SDOperand StoreChain;
4721 if (!Stores.empty()) // Not all undef elements?
4722 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4723 &Stores[0], Stores.size());
4725 StoreChain = DAG.getEntryNode();
4727 // Result is a load from the stack slot.
4728 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
4731 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
4732 SDOperand Op, SDOperand Amt,
4733 SDOperand &Lo, SDOperand &Hi) {
4734 // Expand the subcomponents.
4735 SDOperand LHSL, LHSH;
4736 ExpandOp(Op, LHSL, LHSH);
4738 SDOperand Ops[] = { LHSL, LHSH, Amt };
4739 MVT::ValueType VT = LHSL.getValueType();
4740 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
4741 Hi = Lo.getValue(1);
4745 /// ExpandShift - Try to find a clever way to expand this shift operation out to
4746 /// smaller elements. If we can't find a way that is more efficient than a
4747 /// libcall on this target, return false. Otherwise, return true with the
4748 /// low-parts expanded into Lo and Hi.
4749 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
4750 SDOperand &Lo, SDOperand &Hi) {
4751 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
4752 "This is not a shift!");
4754 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
4755 SDOperand ShAmt = LegalizeOp(Amt);
4756 MVT::ValueType ShTy = ShAmt.getValueType();
4757 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
4758 unsigned NVTBits = MVT::getSizeInBits(NVT);
4760 // Handle the case when Amt is an immediate.
4761 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
4762 unsigned Cst = CN->getValue();
4763 // Expand the incoming operand to be shifted, so that we have its parts
4765 ExpandOp(Op, InL, InH);
4769 Lo = DAG.getConstant(0, NVT);
4770 Hi = DAG.getConstant(0, NVT);
4771 } else if (Cst > NVTBits) {
4772 Lo = DAG.getConstant(0, NVT);
4773 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
4774 } else if (Cst == NVTBits) {
4775 Lo = DAG.getConstant(0, NVT);
4778 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
4779 Hi = DAG.getNode(ISD::OR, NVT,
4780 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
4781 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
4786 Lo = DAG.getConstant(0, NVT);
4787 Hi = DAG.getConstant(0, NVT);
4788 } else if (Cst > NVTBits) {
4789 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
4790 Hi = DAG.getConstant(0, NVT);
4791 } else if (Cst == NVTBits) {
4793 Hi = DAG.getConstant(0, NVT);
4795 Lo = DAG.getNode(ISD::OR, NVT,
4796 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
4797 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
4798 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
4803 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
4804 DAG.getConstant(NVTBits-1, ShTy));
4805 } else if (Cst > NVTBits) {
4806 Lo = DAG.getNode(ISD::SRA, NVT, InH,
4807 DAG.getConstant(Cst-NVTBits, ShTy));
4808 Hi = DAG.getNode(ISD::SRA, NVT, InH,
4809 DAG.getConstant(NVTBits-1, ShTy));
4810 } else if (Cst == NVTBits) {
4812 Hi = DAG.getNode(ISD::SRA, NVT, InH,
4813 DAG.getConstant(NVTBits-1, ShTy));
4815 Lo = DAG.getNode(ISD::OR, NVT,
4816 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
4817 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
4818 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
4824 // Okay, the shift amount isn't constant. However, if we can tell that it is
4825 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
4826 uint64_t Mask = NVTBits, KnownZero, KnownOne;
4827 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
4829 // If we know that the high bit of the shift amount is one, then we can do
4830 // this as a couple of simple shifts.
4831 if (KnownOne & Mask) {
4832 // Mask out the high bit, which we know is set.
4833 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
4834 DAG.getConstant(NVTBits-1, Amt.getValueType()));
4836 // Expand the incoming operand to be shifted, so that we have its parts
4838 ExpandOp(Op, InL, InH);
4841 Lo = DAG.getConstant(0, NVT); // Low part is zero.
4842 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
4845 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
4846 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
4849 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
4850 DAG.getConstant(NVTBits-1, Amt.getValueType()));
4851 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
4856 // If we know that the high bit of the shift amount is zero, then we can do
4857 // this as a couple of simple shifts.
4858 if (KnownZero & Mask) {
4860 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
4861 DAG.getConstant(NVTBits, Amt.getValueType()),
4864 // Expand the incoming operand to be shifted, so that we have its parts
4866 ExpandOp(Op, InL, InH);
4869 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
4870 Hi = DAG.getNode(ISD::OR, NVT,
4871 DAG.getNode(ISD::SHL, NVT, InH, Amt),
4872 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
4875 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
4876 Lo = DAG.getNode(ISD::OR, NVT,
4877 DAG.getNode(ISD::SRL, NVT, InL, Amt),
4878 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
4881 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
4882 Lo = DAG.getNode(ISD::OR, NVT,
4883 DAG.getNode(ISD::SRL, NVT, InL, Amt),
4884 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
4893 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
4894 // does not fit into a register, return the lo part and set the hi part to the
4895 // by-reg argument. If it does fit into a single register, return the result
4896 // and leave the Hi part unset.
4897 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
4898 bool isSigned, SDOperand &Hi) {
4899 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
4900 // The input chain to this libcall is the entry node of the function.
4901 // Legalizing the call will automatically add the previous call to the
4903 SDOperand InChain = DAG.getEntryNode();
4905 TargetLowering::ArgListTy Args;
4906 TargetLowering::ArgListEntry Entry;
4907 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
4908 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
4909 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
4910 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
4911 Entry.isSExt = isSigned;
4912 Args.push_back(Entry);
4914 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
4916 // Splice the libcall in wherever FindInputOutputChains tells us to.
4917 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
4918 std::pair<SDOperand,SDOperand> CallInfo =
4919 TLI.LowerCallTo(InChain, RetTy, isSigned, false, CallingConv::C, false,
4922 // Legalize the call sequence, starting with the chain. This will advance
4923 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
4924 // was added by LowerCallTo (guaranteeing proper serialization of calls).
4925 LegalizeOp(CallInfo.second);
4927 switch (getTypeAction(CallInfo.first.getValueType())) {
4928 default: assert(0 && "Unknown thing");
4930 Result = CallInfo.first;
4933 ExpandOp(CallInfo.first, Result, Hi);
4940 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
4942 SDOperand SelectionDAGLegalize::
4943 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
4944 assert(getTypeAction(Source.getValueType()) == Expand &&
4945 "This is not an expansion!");
4946 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
4949 assert(Source.getValueType() == MVT::i64 &&
4950 "This only works for 64-bit -> FP");
4951 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
4952 // incoming integer is set. To handle this, we dynamically test to see if
4953 // it is set, and, if so, add a fudge factor.
4955 ExpandOp(Source, Lo, Hi);
4957 // If this is unsigned, and not supported, first perform the conversion to
4958 // signed, then adjust the result if the sign bit is set.
4959 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
4960 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
4962 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
4963 DAG.getConstant(0, Hi.getValueType()),
4965 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
4966 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
4967 SignSet, Four, Zero);
4968 uint64_t FF = 0x5f800000ULL;
4969 if (TLI.isLittleEndian()) FF <<= 32;
4970 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
4972 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
4973 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
4974 SDOperand FudgeInReg;
4975 if (DestTy == MVT::f32)
4976 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
4977 else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32))
4978 // FIXME: Avoid the extend by construction the right constantpool?
4979 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
4980 CPIdx, NULL, 0, MVT::f32);
4982 assert(0 && "Unexpected conversion");
4984 MVT::ValueType SCVT = SignedConv.getValueType();
4985 if (SCVT != DestTy) {
4986 // Destination type needs to be expanded as well. The FADD now we are
4987 // constructing will be expanded into a libcall.
4988 if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) {
4989 assert(SCVT == MVT::i32 && DestTy == MVT::f64);
4990 SignedConv = DAG.getNode(ISD::BUILD_PAIR, MVT::i64,
4991 SignedConv, SignedConv.getValue(1));
4993 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
4995 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
4998 // Check to see if the target has a custom way to lower this. If so, use it.
4999 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
5000 default: assert(0 && "This action not implemented for this operation!");
5001 case TargetLowering::Legal:
5002 case TargetLowering::Expand:
5003 break; // This case is handled below.
5004 case TargetLowering::Custom: {
5005 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
5008 return LegalizeOp(NV);
5009 break; // The target decided this was legal after all
5013 // Expand the source, then glue it back together for the call. We must expand
5014 // the source in case it is shared (this pass of legalize must traverse it).
5015 SDOperand SrcLo, SrcHi;
5016 ExpandOp(Source, SrcLo, SrcHi);
5017 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
5020 if (DestTy == MVT::f32)
5021 LC = RTLIB::SINTTOFP_I64_F32;
5023 assert(DestTy == MVT::f64 && "Unknown fp value type!");
5024 LC = RTLIB::SINTTOFP_I64_F64;
5027 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!");
5028 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
5029 SDOperand UnusedHiPart;
5030 return ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned,
5034 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
5035 /// INT_TO_FP operation of the specified operand when the target requests that
5036 /// we expand it. At this point, we know that the result and operand types are
5037 /// legal for the target.
5038 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
5040 MVT::ValueType DestVT) {
5041 if (Op0.getValueType() == MVT::i32) {
5042 // simple 32-bit [signed|unsigned] integer to float/double expansion
5044 // get the stack frame index of a 8 byte buffer, pessimistically aligned
5045 MachineFunction &MF = DAG.getMachineFunction();
5046 const Type *F64Type = MVT::getTypeForValueType(MVT::f64);
5047 unsigned StackAlign =
5048 (unsigned)TLI.getTargetData()->getPrefTypeAlignment(F64Type);
5049 int SSFI = MF.getFrameInfo()->CreateStackObject(8, StackAlign);
5050 // get address of 8 byte buffer
5051 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5052 // word offset constant for Hi/Lo address computation
5053 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
5054 // set up Hi and Lo (into buffer) address based on endian
5055 SDOperand Hi = StackSlot;
5056 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
5057 if (TLI.isLittleEndian())
5060 // if signed map to unsigned space
5061 SDOperand Op0Mapped;
5063 // constant used to invert sign bit (signed to unsigned mapping)
5064 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
5065 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
5069 // store the lo of the constructed double - based on integer input
5070 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(),
5071 Op0Mapped, Lo, NULL, 0);
5072 // initial hi portion of constructed double
5073 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
5074 // store the hi of the constructed double - biased exponent
5075 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
5076 // load the constructed double
5077 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
5078 // FP constant to bias correct the final result
5079 SDOperand Bias = DAG.getConstantFP(isSigned ?
5080 BitsToDouble(0x4330000080000000ULL)
5081 : BitsToDouble(0x4330000000000000ULL),
5083 // subtract the bias
5084 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
5087 // handle final rounding
5088 if (DestVT == MVT::f64) {
5091 } else if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(MVT::f64)) {
5092 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub);
5093 } else if (MVT::getSizeInBits(DestVT) > MVT::getSizeInBits(MVT::f64)) {
5094 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
5098 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
5099 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
5101 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
5102 DAG.getConstant(0, Op0.getValueType()),
5104 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
5105 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5106 SignSet, Four, Zero);
5108 // If the sign bit of the integer is set, the large number will be treated
5109 // as a negative number. To counteract this, the dynamic code adds an
5110 // offset depending on the data type.
5112 switch (Op0.getValueType()) {
5113 default: assert(0 && "Unsupported integer type!");
5114 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
5115 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
5116 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
5117 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
5119 if (TLI.isLittleEndian()) FF <<= 32;
5120 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5122 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5123 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5124 SDOperand FudgeInReg;
5125 if (DestVT == MVT::f32)
5126 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
5128 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT,
5129 DAG.getEntryNode(), CPIdx,
5130 NULL, 0, MVT::f32));
5133 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
5136 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
5137 /// *INT_TO_FP operation of the specified operand when the target requests that
5138 /// we promote it. At this point, we know that the result and operand types are
5139 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
5140 /// operation that takes a larger input.
5141 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
5142 MVT::ValueType DestVT,
5144 // First step, figure out the appropriate *INT_TO_FP operation to use.
5145 MVT::ValueType NewInTy = LegalOp.getValueType();
5147 unsigned OpToUse = 0;
5149 // Scan for the appropriate larger type to use.
5151 NewInTy = (MVT::ValueType)(NewInTy+1);
5152 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
5154 // If the target supports SINT_TO_FP of this type, use it.
5155 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
5157 case TargetLowering::Legal:
5158 if (!TLI.isTypeLegal(NewInTy))
5159 break; // Can't use this datatype.
5161 case TargetLowering::Custom:
5162 OpToUse = ISD::SINT_TO_FP;
5166 if (isSigned) continue;
5168 // If the target supports UINT_TO_FP of this type, use it.
5169 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
5171 case TargetLowering::Legal:
5172 if (!TLI.isTypeLegal(NewInTy))
5173 break; // Can't use this datatype.
5175 case TargetLowering::Custom:
5176 OpToUse = ISD::UINT_TO_FP;
5181 // Otherwise, try a larger type.
5184 // Okay, we found the operation and type to use. Zero extend our input to the
5185 // desired type then run the operation on it.
5186 return DAG.getNode(OpToUse, DestVT,
5187 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
5191 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
5192 /// FP_TO_*INT operation of the specified operand when the target requests that
5193 /// we promote it. At this point, we know that the result and operand types are
5194 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
5195 /// operation that returns a larger result.
5196 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
5197 MVT::ValueType DestVT,
5199 // First step, figure out the appropriate FP_TO*INT operation to use.
5200 MVT::ValueType NewOutTy = DestVT;
5202 unsigned OpToUse = 0;
5204 // Scan for the appropriate larger type to use.
5206 NewOutTy = (MVT::ValueType)(NewOutTy+1);
5207 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
5209 // If the target supports FP_TO_SINT returning this type, use it.
5210 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
5212 case TargetLowering::Legal:
5213 if (!TLI.isTypeLegal(NewOutTy))
5214 break; // Can't use this datatype.
5216 case TargetLowering::Custom:
5217 OpToUse = ISD::FP_TO_SINT;
5222 // If the target supports FP_TO_UINT of this type, use it.
5223 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
5225 case TargetLowering::Legal:
5226 if (!TLI.isTypeLegal(NewOutTy))
5227 break; // Can't use this datatype.
5229 case TargetLowering::Custom:
5230 OpToUse = ISD::FP_TO_UINT;
5235 // Otherwise, try a larger type.
5239 // Okay, we found the operation and type to use.
5240 SDOperand Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp);
5242 // If the operation produces an invalid type, it must be custom lowered. Use
5243 // the target lowering hooks to expand it. Just keep the low part of the
5244 // expanded operation, we know that we're truncating anyway.
5245 if (getTypeAction(NewOutTy) == Expand) {
5246 Operation = SDOperand(TLI.ExpandOperationResult(Operation.Val, DAG), 0);
5247 assert(Operation.Val && "Didn't return anything");
5250 // Truncate the result of the extended FP_TO_*INT operation to the desired
5252 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation);
5255 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
5257 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
5258 MVT::ValueType VT = Op.getValueType();
5259 MVT::ValueType SHVT = TLI.getShiftAmountTy();
5260 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
5262 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
5264 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5265 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5266 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
5268 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5269 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5270 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5271 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5272 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
5273 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
5274 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5275 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5276 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5278 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
5279 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
5280 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5281 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5282 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5283 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5284 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
5285 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
5286 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
5287 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
5288 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
5289 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
5290 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
5291 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
5292 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
5293 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
5294 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5295 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5296 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
5297 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5298 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
5302 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
5304 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
5306 default: assert(0 && "Cannot expand this yet!");
5308 static const uint64_t mask[6] = {
5309 0x5555555555555555ULL, 0x3333333333333333ULL,
5310 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
5311 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
5313 MVT::ValueType VT = Op.getValueType();
5314 MVT::ValueType ShVT = TLI.getShiftAmountTy();
5315 unsigned len = MVT::getSizeInBits(VT);
5316 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5317 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
5318 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
5319 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5320 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
5321 DAG.getNode(ISD::AND, VT,
5322 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
5327 // for now, we do this:
5328 // x = x | (x >> 1);
5329 // x = x | (x >> 2);
5331 // x = x | (x >>16);
5332 // x = x | (x >>32); // for 64-bit input
5333 // return popcount(~x);
5335 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
5336 MVT::ValueType VT = Op.getValueType();
5337 MVT::ValueType ShVT = TLI.getShiftAmountTy();
5338 unsigned len = MVT::getSizeInBits(VT);
5339 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5340 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5341 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
5343 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
5344 return DAG.getNode(ISD::CTPOP, VT, Op);
5347 // for now, we use: { return popcount(~x & (x - 1)); }
5348 // unless the target has ctlz but not ctpop, in which case we use:
5349 // { return 32 - nlz(~x & (x-1)); }
5350 // see also http://www.hackersdelight.org/HDcode/ntz.cc
5351 MVT::ValueType VT = Op.getValueType();
5352 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
5353 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
5354 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
5355 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
5356 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
5357 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
5358 TLI.isOperationLegal(ISD::CTLZ, VT))
5359 return DAG.getNode(ISD::SUB, VT,
5360 DAG.getConstant(MVT::getSizeInBits(VT), VT),
5361 DAG.getNode(ISD::CTLZ, VT, Tmp3));
5362 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
5367 /// ExpandOp - Expand the specified SDOperand into its two component pieces
5368 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
5369 /// LegalizeNodes map is filled in for any results that are not expanded, the
5370 /// ExpandedNodes map is filled in for any results that are expanded, and the
5371 /// Lo/Hi values are returned.
5372 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
5373 MVT::ValueType VT = Op.getValueType();
5374 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
5375 SDNode *Node = Op.Val;
5376 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
5377 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) ||
5378 MVT::isVector(VT)) &&
5379 "Cannot expand to FP value or to larger int value!");
5381 // See if we already expanded it.
5382 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
5383 = ExpandedNodes.find(Op);
5384 if (I != ExpandedNodes.end()) {
5385 Lo = I->second.first;
5386 Hi = I->second.second;
5390 switch (Node->getOpcode()) {
5391 case ISD::CopyFromReg:
5392 assert(0 && "CopyFromReg must be legal!");
5393 case ISD::FP_ROUND_INREG:
5394 if (VT == MVT::ppcf128 &&
5395 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
5396 TargetLowering::Custom) {
5397 SDOperand SrcLo, SrcHi, Src;
5398 ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
5399 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi);
5400 SDOperand Result = TLI.LowerOperation(
5401 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG);
5402 assert(Result.Val->getOpcode() == ISD::BUILD_PAIR);
5403 Lo = Result.Val->getOperand(0);
5404 Hi = Result.Val->getOperand(1);
5410 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
5412 assert(0 && "Do not know how to expand this operator!");
5414 case ISD::EXTRACT_VECTOR_ELT:
5415 assert(VT==MVT::i64 && "Do not know how to expand this operator!");
5416 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types.
5417 Lo = ExpandEXTRACT_VECTOR_ELT(Op);
5418 return ExpandOp(Lo, Lo, Hi);
5420 NVT = TLI.getTypeToExpandTo(VT);
5421 Lo = DAG.getNode(ISD::UNDEF, NVT);
5422 Hi = DAG.getNode(ISD::UNDEF, NVT);
5424 case ISD::Constant: {
5425 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
5426 Lo = DAG.getConstant(Cst, NVT);
5427 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
5430 case ISD::ConstantFP: {
5431 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
5432 if (CFP->getValueType(0) == MVT::ppcf128) {
5433 APInt api = CFP->getValueAPF().convertToAPInt();
5434 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
5436 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
5440 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
5441 if (getTypeAction(Lo.getValueType()) == Expand)
5442 ExpandOp(Lo, Lo, Hi);
5445 case ISD::BUILD_PAIR:
5446 // Return the operands.
5447 Lo = Node->getOperand(0);
5448 Hi = Node->getOperand(1);
5451 case ISD::MERGE_VALUES:
5452 if (Node->getNumValues() == 1) {
5453 ExpandOp(Op.getOperand(0), Lo, Hi);
5456 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y)
5457 assert(Op.ResNo == 0 && Node->getNumValues() == 2 &&
5458 Op.getValue(1).getValueType() == MVT::Other &&
5459 "unhandled MERGE_VALUES");
5460 ExpandOp(Op.getOperand(0), Lo, Hi);
5461 // Remember that we legalized the chain.
5462 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1)));
5465 case ISD::SIGN_EXTEND_INREG:
5466 ExpandOp(Node->getOperand(0), Lo, Hi);
5467 // sext_inreg the low part if needed.
5468 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
5470 // The high part gets the sign extension from the lo-part. This handles
5471 // things like sextinreg V:i64 from i8.
5472 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5473 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
5474 TLI.getShiftAmountTy()));
5478 ExpandOp(Node->getOperand(0), Lo, Hi);
5479 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
5480 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
5486 ExpandOp(Node->getOperand(0), Lo, Hi);
5487 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
5488 DAG.getNode(ISD::CTPOP, NVT, Lo),
5489 DAG.getNode(ISD::CTPOP, NVT, Hi));
5490 Hi = DAG.getConstant(0, NVT);
5494 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
5495 ExpandOp(Node->getOperand(0), Lo, Hi);
5496 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5497 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
5498 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
5500 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
5501 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
5503 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
5504 Hi = DAG.getConstant(0, NVT);
5509 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
5510 ExpandOp(Node->getOperand(0), Lo, Hi);
5511 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5512 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
5513 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
5515 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
5516 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
5518 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
5519 Hi = DAG.getConstant(0, NVT);
5524 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
5525 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
5526 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
5527 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
5529 // Remember that we legalized the chain.
5530 Hi = LegalizeOp(Hi);
5531 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
5532 if (!TLI.isLittleEndian())
5538 LoadSDNode *LD = cast<LoadSDNode>(Node);
5539 SDOperand Ch = LD->getChain(); // Legalize the chain.
5540 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer.
5541 ISD::LoadExtType ExtType = LD->getExtensionType();
5542 int SVOffset = LD->getSrcValueOffset();
5543 unsigned Alignment = LD->getAlignment();
5544 bool isVolatile = LD->isVolatile();
5546 if (ExtType == ISD::NON_EXTLOAD) {
5547 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5548 isVolatile, Alignment);
5549 if (VT == MVT::f32 || VT == MVT::f64) {
5550 // f32->i32 or f64->i64 one to one expansion.
5551 // Remember that we legalized the chain.
5552 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5553 // Recursively expand the new load.
5554 if (getTypeAction(NVT) == Expand)
5555 ExpandOp(Lo, Lo, Hi);
5559 // Increment the pointer to the other half.
5560 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
5561 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
5562 getIntPtrConstant(IncrementSize));
5563 SVOffset += IncrementSize;
5564 Alignment = MinAlign(Alignment, IncrementSize);
5565 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5566 isVolatile, Alignment);
5568 // Build a factor node to remember that this load is independent of the
5570 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
5573 // Remember that we legalized the chain.
5574 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
5575 if (!TLI.isLittleEndian())
5578 MVT::ValueType EVT = LD->getLoadedVT();
5580 if ((VT == MVT::f64 && EVT == MVT::f32) ||
5581 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
5582 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
5583 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(),
5584 SVOffset, isVolatile, Alignment);
5585 // Remember that we legalized the chain.
5586 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1)));
5587 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
5592 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),
5593 SVOffset, isVolatile, Alignment);
5595 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(),
5596 SVOffset, EVT, isVolatile,
5599 // Remember that we legalized the chain.
5600 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5602 if (ExtType == ISD::SEXTLOAD) {
5603 // The high part is obtained by SRA'ing all but one of the bits of the
5605 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
5606 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5607 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5608 } else if (ExtType == ISD::ZEXTLOAD) {
5609 // The high part is just a zero.
5610 Hi = DAG.getConstant(0, NVT);
5611 } else /* if (ExtType == ISD::EXTLOAD) */ {
5612 // The high part is undefined.
5613 Hi = DAG.getNode(ISD::UNDEF, NVT);
5620 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
5621 SDOperand LL, LH, RL, RH;
5622 ExpandOp(Node->getOperand(0), LL, LH);
5623 ExpandOp(Node->getOperand(1), RL, RH);
5624 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
5625 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
5629 SDOperand LL, LH, RL, RH;
5630 ExpandOp(Node->getOperand(1), LL, LH);
5631 ExpandOp(Node->getOperand(2), RL, RH);
5632 if (getTypeAction(NVT) == Expand)
5633 NVT = TLI.getTypeToExpandTo(NVT);
5634 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
5636 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
5639 case ISD::SELECT_CC: {
5640 SDOperand TL, TH, FL, FH;
5641 ExpandOp(Node->getOperand(2), TL, TH);
5642 ExpandOp(Node->getOperand(3), FL, FH);
5643 if (getTypeAction(NVT) == Expand)
5644 NVT = TLI.getTypeToExpandTo(NVT);
5645 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
5646 Node->getOperand(1), TL, FL, Node->getOperand(4));
5648 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
5649 Node->getOperand(1), TH, FH, Node->getOperand(4));
5652 case ISD::ANY_EXTEND:
5653 // The low part is any extension of the input (which degenerates to a copy).
5654 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
5655 // The high part is undefined.
5656 Hi = DAG.getNode(ISD::UNDEF, NVT);
5658 case ISD::SIGN_EXTEND: {
5659 // The low part is just a sign extension of the input (which degenerates to
5661 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
5663 // The high part is obtained by SRA'ing all but one of the bits of the lo
5665 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
5666 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5667 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5670 case ISD::ZERO_EXTEND:
5671 // The low part is just a zero extension of the input (which degenerates to
5673 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
5675 // The high part is just a zero.
5676 Hi = DAG.getConstant(0, NVT);
5679 case ISD::TRUNCATE: {
5680 // The input value must be larger than this value. Expand *it*.
5682 ExpandOp(Node->getOperand(0), NewLo, Hi);
5684 // The low part is now either the right size, or it is closer. If not the
5685 // right size, make an illegal truncate so we recursively expand it.
5686 if (NewLo.getValueType() != Node->getValueType(0))
5687 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
5688 ExpandOp(NewLo, Lo, Hi);
5692 case ISD::BIT_CONVERT: {
5694 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
5695 // If the target wants to, allow it to lower this itself.
5696 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5697 case Expand: assert(0 && "cannot expand FP!");
5698 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
5699 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
5701 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
5704 // f32 / f64 must be expanded to i32 / i64.
5705 if (VT == MVT::f32 || VT == MVT::f64) {
5706 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
5707 if (getTypeAction(NVT) == Expand)
5708 ExpandOp(Lo, Lo, Hi);
5712 // If source operand will be expanded to the same type as VT, i.e.
5713 // i64 <- f64, i32 <- f32, expand the source operand instead.
5714 MVT::ValueType VT0 = Node->getOperand(0).getValueType();
5715 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
5716 ExpandOp(Node->getOperand(0), Lo, Hi);
5720 // Turn this into a load/store pair by default.
5722 Tmp = ExpandBIT_CONVERT(VT, Node->getOperand(0));
5724 ExpandOp(Tmp, Lo, Hi);
5728 case ISD::READCYCLECOUNTER: {
5729 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
5730 TargetLowering::Custom &&
5731 "Must custom expand ReadCycleCounter");
5732 SDOperand Tmp = TLI.LowerOperation(Op, DAG);
5733 assert(Tmp.Val && "Node must be custom expanded!");
5734 ExpandOp(Tmp.getValue(0), Lo, Hi);
5735 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
5736 LegalizeOp(Tmp.getValue(1)));
5740 // These operators cannot be expanded directly, emit them as calls to
5741 // library functions.
5742 case ISD::FP_TO_SINT: {
5743 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
5745 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5746 case Expand: assert(0 && "cannot expand FP!");
5747 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
5748 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
5751 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
5753 // Now that the custom expander is done, expand the result, which is still
5756 ExpandOp(Op, Lo, Hi);
5761 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
5762 if (Node->getOperand(0).getValueType() == MVT::f32)
5763 LC = RTLIB::FPTOSINT_F32_I64;
5764 else if (Node->getOperand(0).getValueType() == MVT::f64)
5765 LC = RTLIB::FPTOSINT_F64_I64;
5766 else if (Node->getOperand(0).getValueType() == MVT::f80)
5767 LC = RTLIB::FPTOSINT_F80_I64;
5768 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
5769 LC = RTLIB::FPTOSINT_PPCF128_I64;
5770 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
5771 false/*sign irrelevant*/, Hi);
5775 case ISD::FP_TO_UINT: {
5776 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
5778 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5779 case Expand: assert(0 && "cannot expand FP!");
5780 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
5781 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
5784 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
5786 // Now that the custom expander is done, expand the result.
5788 ExpandOp(Op, Lo, Hi);
5793 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
5794 if (Node->getOperand(0).getValueType() == MVT::f32)
5795 LC = RTLIB::FPTOUINT_F32_I64;
5796 else if (Node->getOperand(0).getValueType() == MVT::f64)
5797 LC = RTLIB::FPTOUINT_F64_I64;
5798 else if (Node->getOperand(0).getValueType() == MVT::f80)
5799 LC = RTLIB::FPTOUINT_F80_I64;
5800 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
5801 LC = RTLIB::FPTOUINT_PPCF128_I64;
5802 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
5803 false/*sign irrelevant*/, Hi);
5808 // If the target wants custom lowering, do so.
5809 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5810 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
5811 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
5812 Op = TLI.LowerOperation(Op, DAG);
5814 // Now that the custom expander is done, expand the result, which is
5816 ExpandOp(Op, Lo, Hi);
5821 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
5822 // this X << 1 as X+X.
5823 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
5824 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
5825 TLI.isOperationLegal(ISD::ADDE, NVT)) {
5826 SDOperand LoOps[2], HiOps[3];
5827 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
5828 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
5829 LoOps[1] = LoOps[0];
5830 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5832 HiOps[1] = HiOps[0];
5833 HiOps[2] = Lo.getValue(1);
5834 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5839 // If we can emit an efficient shift operation, do so now.
5840 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
5843 // If this target supports SHL_PARTS, use it.
5844 TargetLowering::LegalizeAction Action =
5845 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
5846 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5847 Action == TargetLowering::Custom) {
5848 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5852 // Otherwise, emit a libcall.
5853 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SHL_I64), Node,
5854 false/*left shift=unsigned*/, Hi);
5859 // If the target wants custom lowering, do so.
5860 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5861 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
5862 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
5863 Op = TLI.LowerOperation(Op, DAG);
5865 // Now that the custom expander is done, expand the result, which is
5867 ExpandOp(Op, Lo, Hi);
5872 // If we can emit an efficient shift operation, do so now.
5873 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
5876 // If this target supports SRA_PARTS, use it.
5877 TargetLowering::LegalizeAction Action =
5878 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
5879 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5880 Action == TargetLowering::Custom) {
5881 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5885 // Otherwise, emit a libcall.
5886 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRA_I64), Node,
5887 true/*ashr is signed*/, Hi);
5892 // If the target wants custom lowering, do so.
5893 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5894 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
5895 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
5896 Op = TLI.LowerOperation(Op, DAG);
5898 // Now that the custom expander is done, expand the result, which is
5900 ExpandOp(Op, Lo, Hi);
5905 // If we can emit an efficient shift operation, do so now.
5906 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
5909 // If this target supports SRL_PARTS, use it.
5910 TargetLowering::LegalizeAction Action =
5911 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
5912 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5913 Action == TargetLowering::Custom) {
5914 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5918 // Otherwise, emit a libcall.
5919 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), Node,
5920 false/*lshr is unsigned*/, Hi);
5926 // If the target wants to custom expand this, let them.
5927 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
5928 TargetLowering::Custom) {
5929 Op = TLI.LowerOperation(Op, DAG);
5931 ExpandOp(Op, Lo, Hi);
5936 // Expand the subcomponents.
5937 SDOperand LHSL, LHSH, RHSL, RHSH;
5938 ExpandOp(Node->getOperand(0), LHSL, LHSH);
5939 ExpandOp(Node->getOperand(1), RHSL, RHSH);
5940 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
5941 SDOperand LoOps[2], HiOps[3];
5946 if (Node->getOpcode() == ISD::ADD) {
5947 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5948 HiOps[2] = Lo.getValue(1);
5949 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5951 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
5952 HiOps[2] = Lo.getValue(1);
5953 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
5960 // Expand the subcomponents.
5961 SDOperand LHSL, LHSH, RHSL, RHSH;
5962 ExpandOp(Node->getOperand(0), LHSL, LHSH);
5963 ExpandOp(Node->getOperand(1), RHSL, RHSH);
5964 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
5965 SDOperand LoOps[2] = { LHSL, RHSL };
5966 SDOperand HiOps[3] = { LHSH, RHSH };
5968 if (Node->getOpcode() == ISD::ADDC) {
5969 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5970 HiOps[2] = Lo.getValue(1);
5971 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5973 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
5974 HiOps[2] = Lo.getValue(1);
5975 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
5977 // Remember that we legalized the flag.
5978 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
5983 // Expand the subcomponents.
5984 SDOperand LHSL, LHSH, RHSL, RHSH;
5985 ExpandOp(Node->getOperand(0), LHSL, LHSH);
5986 ExpandOp(Node->getOperand(1), RHSL, RHSH);
5987 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
5988 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
5989 SDOperand HiOps[3] = { LHSH, RHSH };
5991 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
5992 HiOps[2] = Lo.getValue(1);
5993 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
5995 // Remember that we legalized the flag.
5996 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6000 // If the target wants to custom expand this, let them.
6001 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
6002 SDOperand New = TLI.LowerOperation(Op, DAG);
6004 ExpandOp(New, Lo, Hi);
6009 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
6010 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
6011 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
6012 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
6013 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
6014 SDOperand LL, LH, RL, RH;
6015 ExpandOp(Node->getOperand(0), LL, LH);
6016 ExpandOp(Node->getOperand(1), RL, RH);
6017 unsigned BitSize = MVT::getSizeInBits(RH.getValueType());
6018 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
6019 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
6020 // FIXME: generalize this to handle other bit sizes
6021 if (LHSSB == 32 && RHSSB == 32 &&
6022 DAG.MaskedValueIsZero(Op.getOperand(0), 0xFFFFFFFF00000000ULL) &&
6023 DAG.MaskedValueIsZero(Op.getOperand(1), 0xFFFFFFFF00000000ULL)) {
6024 // The inputs are both zero-extended.
6026 // We can emit a umul_lohi.
6027 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6028 Hi = SDOperand(Lo.Val, 1);
6032 // We can emit a mulhu+mul.
6033 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6034 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6038 if (LHSSB > BitSize && RHSSB > BitSize) {
6039 // The input values are both sign-extended.
6041 // We can emit a smul_lohi.
6042 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6043 Hi = SDOperand(Lo.Val, 1);
6047 // We can emit a mulhs+mul.
6048 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6049 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
6054 // Lo,Hi = umul LHS, RHS.
6055 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
6056 DAG.getVTList(NVT, NVT), LL, RL);
6058 Hi = UMulLOHI.getValue(1);
6059 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6060 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6061 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6062 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6066 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6067 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6068 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6069 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6070 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6071 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6076 // If nothing else, we can make a libcall.
6077 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), Node,
6078 false/*sign irrelevant*/, Hi);
6082 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SDIV_I64), Node, true, Hi);
6085 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UDIV_I64), Node, true, Hi);
6088 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SREM_I64), Node, true, Hi);
6091 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UREM_I64), Node, true, Hi);
6095 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::ADD_F32,
6098 RTLIB::ADD_PPCF128)),
6102 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::SUB_F32,
6105 RTLIB::SUB_PPCF128)),
6109 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::MUL_F32,
6112 RTLIB::MUL_PPCF128)),
6116 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::DIV_F32,
6119 RTLIB::DIV_PPCF128)),
6122 case ISD::FP_EXTEND:
6123 if (VT == MVT::ppcf128) {
6124 assert(Node->getOperand(0).getValueType()==MVT::f32 ||
6125 Node->getOperand(0).getValueType()==MVT::f64);
6126 const uint64_t zero = 0;
6127 if (Node->getOperand(0).getValueType()==MVT::f32)
6128 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0));
6130 Hi = Node->getOperand(0);
6131 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6134 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPEXT_F32_F64), Node, true,Hi);
6137 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi);
6140 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::POWI_F32,
6143 RTLIB::POWI_PPCF128)),
6149 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6150 switch(Node->getOpcode()) {
6152 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
6153 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
6156 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
6157 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
6160 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
6161 RTLIB::COS_F80, RTLIB::COS_PPCF128);
6163 default: assert(0 && "Unreachable!");
6165 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false, Hi);
6169 if (VT == MVT::ppcf128) {
6171 ExpandOp(Node->getOperand(0), Lo, Tmp);
6172 Hi = DAG.getNode(ISD::FABS, NVT, Tmp);
6173 // lo = hi==fabs(hi) ? lo : -lo;
6174 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp,
6175 Lo, DAG.getNode(ISD::FNEG, NVT, Lo),
6176 DAG.getCondCode(ISD::SETEQ));
6179 SDOperand Mask = (VT == MVT::f64)
6180 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
6181 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
6182 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6183 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6184 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
6185 if (getTypeAction(NVT) == Expand)
6186 ExpandOp(Lo, Lo, Hi);
6190 if (VT == MVT::ppcf128) {
6191 ExpandOp(Node->getOperand(0), Lo, Hi);
6192 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo);
6193 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi);
6196 SDOperand Mask = (VT == MVT::f64)
6197 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
6198 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
6199 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6200 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6201 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
6202 if (getTypeAction(NVT) == Expand)
6203 ExpandOp(Lo, Lo, Hi);
6206 case ISD::FCOPYSIGN: {
6207 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
6208 if (getTypeAction(NVT) == Expand)
6209 ExpandOp(Lo, Lo, Hi);
6212 case ISD::SINT_TO_FP:
6213 case ISD::UINT_TO_FP: {
6214 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
6215 MVT::ValueType SrcVT = Node->getOperand(0).getValueType();
6216 if (VT == MVT::ppcf128 && SrcVT != MVT::i64) {
6217 static uint64_t zero = 0;
6219 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6220 Node->getOperand(0)));
6221 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6223 static uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
6224 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6225 Node->getOperand(0)));
6226 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6227 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6228 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
6229 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6230 DAG.getConstant(0, MVT::i32),
6231 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6233 APFloat(APInt(128, 2, TwoE32)),
6236 DAG.getCondCode(ISD::SETLT)),
6241 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) {
6242 // si64->ppcf128 done by libcall, below
6243 static uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
6244 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)),
6246 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6247 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
6248 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6249 DAG.getConstant(0, MVT::i64),
6250 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6252 APFloat(APInt(128, 2, TwoE64)),
6255 DAG.getCondCode(ISD::SETLT)),
6259 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6260 if (Node->getOperand(0).getValueType() == MVT::i64) {
6262 LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32;
6263 else if (VT == MVT::f64)
6264 LC = isSigned ? RTLIB::SINTTOFP_I64_F64 : RTLIB::UINTTOFP_I64_F64;
6265 else if (VT == MVT::f80) {
6267 LC = RTLIB::SINTTOFP_I64_F80;
6269 else if (VT == MVT::ppcf128) {
6271 LC = RTLIB::SINTTOFP_I64_PPCF128;
6275 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32;
6277 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64;
6280 // Promote the operand if needed.
6281 if (getTypeAction(SrcVT) == Promote) {
6282 SDOperand Tmp = PromoteOp(Node->getOperand(0));
6284 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
6285 DAG.getValueType(SrcVT))
6286 : DAG.getZeroExtendInReg(Tmp, SrcVT);
6287 Node = DAG.UpdateNodeOperands(Op, Tmp).Val;
6290 const char *LibCall = TLI.getLibcallName(LC);
6292 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Hi);
6294 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
6295 Node->getOperand(0));
6296 if (getTypeAction(Lo.getValueType()) == Expand)
6297 ExpandOp(Lo, Lo, Hi);
6303 // Make sure the resultant values have been legalized themselves, unless this
6304 // is a type that requires multi-step expansion.
6305 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
6306 Lo = LegalizeOp(Lo);
6308 // Don't legalize the high part if it is expanded to a single node.
6309 Hi = LegalizeOp(Hi);
6312 // Remember in a map if the values will be reused later.
6313 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi)));
6314 assert(isNew && "Value already expanded?!?");
6317 /// SplitVectorOp - Given an operand of vector type, break it down into
6318 /// two smaller values, still of vector type.
6319 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
6321 assert(MVT::isVector(Op.getValueType()) && "Cannot split non-vector type!");
6322 SDNode *Node = Op.Val;
6323 unsigned NumElements = MVT::getVectorNumElements(Op.getValueType());
6324 assert(NumElements > 1 && "Cannot split a single element vector!");
6326 MVT::ValueType NewEltVT = MVT::getVectorElementType(Op.getValueType());
6328 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
6329 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
6331 MVT::ValueType NewVT_Lo = MVT::getVectorType(NewEltVT, NewNumElts_Lo);
6332 MVT::ValueType NewVT_Hi = MVT::getVectorType(NewEltVT, NewNumElts_Hi);
6334 // See if we already split it.
6335 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
6336 = SplitNodes.find(Op);
6337 if (I != SplitNodes.end()) {
6338 Lo = I->second.first;
6339 Hi = I->second.second;
6343 switch (Node->getOpcode()) {
6348 assert(0 && "Unhandled operation in SplitVectorOp!");
6350 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo);
6351 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi);
6353 case ISD::BUILD_PAIR:
6354 Lo = Node->getOperand(0);
6355 Hi = Node->getOperand(1);
6357 case ISD::INSERT_VECTOR_ELT: {
6358 SplitVectorOp(Node->getOperand(0), Lo, Hi);
6359 unsigned Index = cast<ConstantSDNode>(Node->getOperand(2))->getValue();
6360 SDOperand ScalarOp = Node->getOperand(1);
6361 if (Index < NewNumElts_Lo)
6362 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp,
6363 DAG.getConstant(Index, TLI.getPointerTy()));
6365 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp,
6366 DAG.getConstant(Index - NewNumElts_Lo,
6367 TLI.getPointerTy()));
6370 case ISD::VECTOR_SHUFFLE: {
6371 // Build the low part.
6372 SDOperand Mask = Node->getOperand(2);
6373 SmallVector<SDOperand, 8> Ops;
6374 MVT::ValueType PtrVT = TLI.getPointerTy();
6376 // Insert all of the elements from the input that are needed. We use
6377 // buildvector of extractelement here because the input vectors will have
6378 // to be legalized, so this makes the code simpler.
6379 for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
6380 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
6381 SDOperand InVec = Node->getOperand(0);
6382 if (Idx >= NumElements) {
6383 InVec = Node->getOperand(1);
6386 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6387 DAG.getConstant(Idx, PtrVT)));
6389 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6392 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
6393 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
6394 SDOperand InVec = Node->getOperand(0);
6395 if (Idx >= NumElements) {
6396 InVec = Node->getOperand(1);
6399 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6400 DAG.getConstant(Idx, PtrVT)));
6402 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6405 case ISD::BUILD_VECTOR: {
6406 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
6407 Node->op_begin()+NewNumElts_Lo);
6408 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size());
6410 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
6412 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size());
6415 case ISD::CONCAT_VECTORS: {
6416 // FIXME: Handle non-power-of-two vectors?
6417 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
6418 if (NewNumSubvectors == 1) {
6419 Lo = Node->getOperand(0);
6420 Hi = Node->getOperand(1);
6422 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
6423 Node->op_begin()+NewNumSubvectors);
6424 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size());
6426 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors,
6428 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size());
6433 SDOperand Cond = Node->getOperand(0);
6435 SDOperand LL, LH, RL, RH;
6436 SplitVectorOp(Node->getOperand(1), LL, LH);
6437 SplitVectorOp(Node->getOperand(2), RL, RH);
6439 if (MVT::isVector(Cond.getValueType())) {
6440 // Handle a vector merge.
6442 SplitVectorOp(Cond, CL, CH);
6443 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL);
6444 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH);
6446 // Handle a simple select with vector operands.
6447 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL);
6448 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH);
6468 SDOperand LL, LH, RL, RH;
6469 SplitVectorOp(Node->getOperand(0), LL, LH);
6470 SplitVectorOp(Node->getOperand(1), RL, RH);
6472 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL);
6473 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH);
6478 SplitVectorOp(Node->getOperand(0), L, H);
6480 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1));
6481 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1));
6492 case ISD::FP_TO_SINT:
6493 case ISD::FP_TO_UINT:
6494 case ISD::SINT_TO_FP:
6495 case ISD::UINT_TO_FP: {
6497 SplitVectorOp(Node->getOperand(0), L, H);
6499 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L);
6500 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H);
6504 LoadSDNode *LD = cast<LoadSDNode>(Node);
6505 SDOperand Ch = LD->getChain();
6506 SDOperand Ptr = LD->getBasePtr();
6507 const Value *SV = LD->getSrcValue();
6508 int SVOffset = LD->getSrcValueOffset();
6509 unsigned Alignment = LD->getAlignment();
6510 bool isVolatile = LD->isVolatile();
6512 Lo = DAG.getLoad(NewVT_Lo, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
6513 unsigned IncrementSize = NewNumElts_Lo * MVT::getSizeInBits(NewEltVT)/8;
6514 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
6515 getIntPtrConstant(IncrementSize));
6516 SVOffset += IncrementSize;
6517 Alignment = MinAlign(Alignment, IncrementSize);
6518 Hi = DAG.getLoad(NewVT_Hi, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
6520 // Build a factor node to remember that this load is independent of the
6522 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
6525 // Remember that we legalized the chain.
6526 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
6529 case ISD::BIT_CONVERT: {
6530 // We know the result is a vector. The input may be either a vector or a
6532 SDOperand InOp = Node->getOperand(0);
6533 if (!MVT::isVector(InOp.getValueType()) ||
6534 MVT::getVectorNumElements(InOp.getValueType()) == 1) {
6535 // The input is a scalar or single-element vector.
6536 // Lower to a store/load so that it can be split.
6537 // FIXME: this could be improved probably.
6538 SDOperand Ptr = DAG.CreateStackTemporary(InOp.getValueType());
6540 SDOperand St = DAG.getStore(DAG.getEntryNode(),
6541 InOp, Ptr, NULL, 0);
6542 InOp = DAG.getLoad(Op.getValueType(), St, Ptr, NULL, 0);
6544 // Split the vector and convert each of the pieces now.
6545 SplitVectorOp(InOp, Lo, Hi);
6546 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo);
6547 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi);
6552 // Remember in a map if the values will be reused later.
6554 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
6555 assert(isNew && "Value already split?!?");
6559 /// ScalarizeVectorOp - Given an operand of single-element vector type
6560 /// (e.g. v1f32), convert it into the equivalent operation that returns a
6561 /// scalar (e.g. f32) value.
6562 SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) {
6563 assert(MVT::isVector(Op.getValueType()) &&
6564 "Bad ScalarizeVectorOp invocation!");
6565 SDNode *Node = Op.Val;
6566 MVT::ValueType NewVT = MVT::getVectorElementType(Op.getValueType());
6567 assert(MVT::getVectorNumElements(Op.getValueType()) == 1);
6569 // See if we already scalarized it.
6570 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op);
6571 if (I != ScalarizedNodes.end()) return I->second;
6574 switch (Node->getOpcode()) {
6577 Node->dump(&DAG); cerr << "\n";
6579 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
6596 Result = DAG.getNode(Node->getOpcode(),
6598 ScalarizeVectorOp(Node->getOperand(0)),
6599 ScalarizeVectorOp(Node->getOperand(1)));
6606 Result = DAG.getNode(Node->getOpcode(),
6608 ScalarizeVectorOp(Node->getOperand(0)));
6611 Result = DAG.getNode(Node->getOpcode(),
6613 ScalarizeVectorOp(Node->getOperand(0)),
6614 Node->getOperand(1));
6617 LoadSDNode *LD = cast<LoadSDNode>(Node);
6618 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
6619 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
6621 const Value *SV = LD->getSrcValue();
6622 int SVOffset = LD->getSrcValueOffset();
6623 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset,
6624 LD->isVolatile(), LD->getAlignment());
6626 // Remember that we legalized the chain.
6627 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
6630 case ISD::BUILD_VECTOR:
6631 Result = Node->getOperand(0);
6633 case ISD::INSERT_VECTOR_ELT:
6634 // Returning the inserted scalar element.
6635 Result = Node->getOperand(1);
6637 case ISD::CONCAT_VECTORS:
6638 assert(Node->getOperand(0).getValueType() == NewVT &&
6639 "Concat of non-legal vectors not yet supported!");
6640 Result = Node->getOperand(0);
6642 case ISD::VECTOR_SHUFFLE: {
6643 // Figure out if the scalar is the LHS or RHS and return it.
6644 SDOperand EltNum = Node->getOperand(2).getOperand(0);
6645 if (cast<ConstantSDNode>(EltNum)->getValue())
6646 Result = ScalarizeVectorOp(Node->getOperand(1));
6648 Result = ScalarizeVectorOp(Node->getOperand(0));
6651 case ISD::EXTRACT_SUBVECTOR:
6652 Result = Node->getOperand(0);
6653 assert(Result.getValueType() == NewVT);
6655 case ISD::BIT_CONVERT:
6656 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));
6659 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
6660 ScalarizeVectorOp(Op.getOperand(1)),
6661 ScalarizeVectorOp(Op.getOperand(2)));
6665 if (TLI.isTypeLegal(NewVT))
6666 Result = LegalizeOp(Result);
6667 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
6668 assert(isNew && "Value already scalarized?");
6673 // SelectionDAG::Legalize - This is the entry point for the file.
6675 void SelectionDAG::Legalize() {
6676 if (ViewLegalizeDAGs) viewGraph();
6678 /// run - This is the main entry point to this class.
6680 SelectionDAGLegalize(*this).LegalizeDAG();