1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/Analysis/DebugInfo.h"
20 #include "llvm/CodeGen/PseudoSourceValue.h"
21 #include "llvm/Target/TargetFrameInfo.h"
22 #include "llvm/Target/TargetLowering.h"
23 #include "llvm/Target/TargetData.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Target/TargetOptions.h"
26 #include "llvm/CallingConv.h"
27 #include "llvm/Constants.h"
28 #include "llvm/DerivedTypes.h"
29 #include "llvm/Function.h"
30 #include "llvm/GlobalVariable.h"
31 #include "llvm/LLVMContext.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/Support/raw_ostream.h"
37 #include "llvm/ADT/DenseMap.h"
38 #include "llvm/ADT/SmallVector.h"
39 #include "llvm/ADT/SmallPtrSet.h"
42 //===----------------------------------------------------------------------===//
43 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
44 /// hacks on it until the target machine can handle it. This involves
45 /// eliminating value sizes the machine cannot handle (promoting small sizes to
46 /// large sizes or splitting up large values into small values) as well as
47 /// eliminating operations the machine cannot handle.
49 /// This code also does a small amount of optimization and recognition of idioms
50 /// as part of its processing. For example, if a target does not support a
51 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
52 /// will attempt merge setcc and brc instructions into brcc's.
55 class SelectionDAGLegalize {
56 const TargetMachine &TM;
57 const TargetLowering &TLI;
59 CodeGenOpt::Level OptLevel;
61 // Libcall insertion helpers.
63 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
64 /// legalized. We use this to ensure that calls are properly serialized
65 /// against each other, including inserted libcalls.
66 SDValue LastCALLSEQ_END;
68 /// IsLegalizingCall - This member is used *only* for purposes of providing
69 /// helpful assertions that a libcall isn't created while another call is
70 /// being legalized (which could lead to non-serialized call sequences).
71 bool IsLegalizingCall;
74 Legal, // The target natively supports this operation.
75 Promote, // This operation should be executed in a larger type.
76 Expand // Try to expand this to other ops, otherwise use a libcall.
79 /// ValueTypeActions - This is a bitvector that contains two bits for each
80 /// value type, where the two bits correspond to the LegalizeAction enum.
81 /// This can be queried with "getTypeAction(VT)".
82 TargetLowering::ValueTypeActionImpl ValueTypeActions;
84 /// LegalizedNodes - For nodes that are of legal width, and that have more
85 /// than one use, this map indicates what regularized operand to use. This
86 /// allows us to avoid legalizing the same thing more than once.
87 DenseMap<SDValue, SDValue> LegalizedNodes;
89 void AddLegalizedOperand(SDValue From, SDValue To) {
90 LegalizedNodes.insert(std::make_pair(From, To));
91 // If someone requests legalization of the new node, return itself.
93 LegalizedNodes.insert(std::make_pair(To, To));
97 SelectionDAGLegalize(SelectionDAG &DAG, CodeGenOpt::Level ol);
99 /// getTypeAction - Return how we should legalize values of this type, either
100 /// it is already legal or we need to expand it into multiple registers of
101 /// smaller integer type, or we need to promote it to a larger type.
102 LegalizeAction getTypeAction(EVT VT) const {
103 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
106 /// isTypeLegal - Return true if this type is legal on this target.
108 bool isTypeLegal(EVT VT) const {
109 return getTypeAction(VT) == Legal;
115 /// LegalizeOp - We know that the specified value has a legal type.
116 /// Recursively ensure that the operands have legal types, then return the
118 SDValue LegalizeOp(SDValue O);
120 SDValue OptimizeFloatStore(StoreSDNode *ST);
122 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
123 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
124 /// is necessary to spill the vector being inserted into to memory, perform
125 /// the insert there, and then read the result back.
126 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
127 SDValue Idx, DebugLoc dl);
128 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
129 SDValue Idx, DebugLoc dl);
131 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
132 /// performs the same shuffe in terms of order or result bytes, but on a type
133 /// whose vector element type is narrower than the original shuffle type.
134 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
135 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
136 SDValue N1, SDValue N2,
137 SmallVectorImpl<int> &Mask) const;
139 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
140 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
142 void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
145 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
146 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
147 SDNode *Node, bool isSigned);
148 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
149 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
150 RTLIB::Libcall Call_PPCF128);
151 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
152 RTLIB::Libcall Call_I8,
153 RTLIB::Libcall Call_I16,
154 RTLIB::Libcall Call_I32,
155 RTLIB::Libcall Call_I64,
156 RTLIB::Libcall Call_I128);
158 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl);
159 SDValue ExpandBUILD_VECTOR(SDNode *Node);
160 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
161 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
162 SmallVectorImpl<SDValue> &Results);
163 SDValue ExpandFCOPYSIGN(SDNode *Node);
164 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
166 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
168 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
171 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl);
172 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl);
174 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
175 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
177 std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node);
179 void ExpandNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
180 void PromoteNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
184 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
185 /// performs the same shuffe in terms of order or result bytes, but on a type
186 /// whose vector element type is narrower than the original shuffle type.
187 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
189 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
190 SDValue N1, SDValue N2,
191 SmallVectorImpl<int> &Mask) const {
192 unsigned NumMaskElts = VT.getVectorNumElements();
193 unsigned NumDestElts = NVT.getVectorNumElements();
194 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
196 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
198 if (NumEltsGrowth == 1)
199 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
201 SmallVector<int, 8> NewMask;
202 for (unsigned i = 0; i != NumMaskElts; ++i) {
204 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
206 NewMask.push_back(-1);
208 NewMask.push_back(Idx * NumEltsGrowth + j);
211 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
212 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
213 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
216 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag,
217 CodeGenOpt::Level ol)
218 : TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()),
219 DAG(dag), OptLevel(ol),
220 ValueTypeActions(TLI.getValueTypeActions()) {
221 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
222 "Too many value types for ValueTypeActions to hold!");
225 void SelectionDAGLegalize::LegalizeDAG() {
226 LastCALLSEQ_END = DAG.getEntryNode();
227 IsLegalizingCall = false;
229 // The legalize process is inherently a bottom-up recursive process (users
230 // legalize their uses before themselves). Given infinite stack space, we
231 // could just start legalizing on the root and traverse the whole graph. In
232 // practice however, this causes us to run out of stack space on large basic
233 // blocks. To avoid this problem, compute an ordering of the nodes where each
234 // node is only legalized after all of its operands are legalized.
235 DAG.AssignTopologicalOrder();
236 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
237 E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I)
238 LegalizeOp(SDValue(I, 0));
240 // Finally, it's possible the root changed. Get the new root.
241 SDValue OldRoot = DAG.getRoot();
242 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
243 DAG.setRoot(LegalizedNodes[OldRoot]);
245 LegalizedNodes.clear();
247 // Remove dead nodes now.
248 DAG.RemoveDeadNodes();
252 /// FindCallEndFromCallStart - Given a chained node that is part of a call
253 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
254 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
255 if (Node->getOpcode() == ISD::CALLSEQ_END)
257 if (Node->use_empty())
258 return 0; // No CallSeqEnd
260 // The chain is usually at the end.
261 SDValue TheChain(Node, Node->getNumValues()-1);
262 if (TheChain.getValueType() != MVT::Other) {
263 // Sometimes it's at the beginning.
264 TheChain = SDValue(Node, 0);
265 if (TheChain.getValueType() != MVT::Other) {
266 // Otherwise, hunt for it.
267 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
268 if (Node->getValueType(i) == MVT::Other) {
269 TheChain = SDValue(Node, i);
273 // Otherwise, we walked into a node without a chain.
274 if (TheChain.getValueType() != MVT::Other)
279 for (SDNode::use_iterator UI = Node->use_begin(),
280 E = Node->use_end(); UI != E; ++UI) {
282 // Make sure to only follow users of our token chain.
284 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
285 if (User->getOperand(i) == TheChain)
286 if (SDNode *Result = FindCallEndFromCallStart(User))
292 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
293 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
294 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
295 assert(Node && "Didn't find callseq_start for a call??");
296 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
298 assert(Node->getOperand(0).getValueType() == MVT::Other &&
299 "Node doesn't have a token chain argument!");
300 return FindCallStartFromCallEnd(Node->getOperand(0).getNode());
303 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
304 /// see if any uses can reach Dest. If no dest operands can get to dest,
305 /// legalize them, legalize ourself, and return false, otherwise, return true.
307 /// Keep track of the nodes we fine that actually do lead to Dest in
308 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
310 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
311 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
312 if (N == Dest) return true; // N certainly leads to Dest :)
314 // If we've already processed this node and it does lead to Dest, there is no
315 // need to reprocess it.
316 if (NodesLeadingTo.count(N)) return true;
318 // If the first result of this node has been already legalized, then it cannot
320 if (LegalizedNodes.count(SDValue(N, 0))) return false;
322 // Okay, this node has not already been legalized. Check and legalize all
323 // operands. If none lead to Dest, then we can legalize this node.
324 bool OperandsLeadToDest = false;
325 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
326 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
327 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest,
330 if (OperandsLeadToDest) {
331 NodesLeadingTo.insert(N);
335 // Okay, this node looks safe, legalize it and return false.
336 LegalizeOp(SDValue(N, 0));
340 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
341 /// a load from the constant pool.
342 static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
343 SelectionDAG &DAG, const TargetLowering &TLI) {
345 DebugLoc dl = CFP->getDebugLoc();
347 // If a FP immediate is precise when represented as a float and if the
348 // target can do an extending load from float to double, we put it into
349 // the constant pool as a float, even if it's is statically typed as a
350 // double. This shrinks FP constants and canonicalizes them for targets where
351 // an FP extending load is the same cost as a normal load (such as on the x87
352 // fp stack or PPC FP unit).
353 EVT VT = CFP->getValueType(0);
354 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
356 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
357 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
358 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
363 while (SVT != MVT::f32) {
364 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
365 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) &&
366 // Only do this if the target has a native EXTLOAD instruction from
368 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
369 TLI.ShouldShrinkFPConstant(OrigVT)) {
370 const Type *SType = SVT.getTypeForEVT(*DAG.getContext());
371 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
377 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
378 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
380 return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, dl,
382 CPIdx, MachinePointerInfo::getConstantPool(),
383 VT, false, false, Alignment);
384 return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
385 MachinePointerInfo::getConstantPool(), false, false,
389 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
391 SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
392 const TargetLowering &TLI) {
393 SDValue Chain = ST->getChain();
394 SDValue Ptr = ST->getBasePtr();
395 SDValue Val = ST->getValue();
396 EVT VT = Val.getValueType();
397 int Alignment = ST->getAlignment();
398 DebugLoc dl = ST->getDebugLoc();
399 if (ST->getMemoryVT().isFloatingPoint() ||
400 ST->getMemoryVT().isVector()) {
401 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
402 if (TLI.isTypeLegal(intVT)) {
403 // Expand to a bitconvert of the value to the integer type of the
404 // same size, then a (misaligned) int store.
405 // FIXME: Does not handle truncating floating point stores!
406 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, intVT, Val);
407 return DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
408 ST->isVolatile(), ST->isNonTemporal(), Alignment);
410 // Do a (aligned) store to a stack slot, then copy from the stack slot
411 // to the final destination using (unaligned) integer loads and stores.
412 EVT StoredVT = ST->getMemoryVT();
414 TLI.getRegisterType(*DAG.getContext(),
415 EVT::getIntegerVT(*DAG.getContext(),
416 StoredVT.getSizeInBits()));
417 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
418 unsigned RegBytes = RegVT.getSizeInBits() / 8;
419 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
421 // Make sure the stack slot is also aligned for the register type.
422 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
424 // Perform the original store, only redirected to the stack slot.
425 SDValue Store = DAG.getTruncStore(Chain, dl,
426 Val, StackPtr, MachinePointerInfo(),
427 StoredVT, false, false, 0);
428 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
429 SmallVector<SDValue, 8> Stores;
432 // Do all but one copies using the full register width.
433 for (unsigned i = 1; i < NumRegs; i++) {
434 // Load one integer register's worth from the stack slot.
435 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr,
436 MachinePointerInfo(),
438 // Store it to the final location. Remember the store.
439 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
440 ST->getPointerInfo().getWithOffset(Offset),
441 ST->isVolatile(), ST->isNonTemporal(),
442 MinAlign(ST->getAlignment(), Offset)));
443 // Increment the pointers.
445 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
447 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
450 // The last store may be partial. Do a truncating store. On big-endian
451 // machines this requires an extending load from the stack slot to ensure
452 // that the bits are in the right place.
453 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
454 8 * (StoredBytes - Offset));
456 // Load from the stack slot.
457 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, RegVT, dl, Store, StackPtr,
458 MachinePointerInfo(),
459 MemVT, false, false, 0);
461 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
463 .getWithOffset(Offset),
464 MemVT, ST->isVolatile(),
466 MinAlign(ST->getAlignment(), Offset)));
467 // The order of the stores doesn't matter - say it with a TokenFactor.
468 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
472 assert(ST->getMemoryVT().isInteger() &&
473 !ST->getMemoryVT().isVector() &&
474 "Unaligned store of unknown type.");
475 // Get the half-size VT
476 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext());
477 int NumBits = NewStoredVT.getSizeInBits();
478 int IncrementSize = NumBits / 8;
480 // Divide the stored value in two parts.
481 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
483 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
485 // Store the two parts
486 SDValue Store1, Store2;
487 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
488 ST->getPointerInfo(), NewStoredVT,
489 ST->isVolatile(), ST->isNonTemporal(), Alignment);
490 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
491 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
492 Alignment = MinAlign(Alignment, IncrementSize);
493 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
494 ST->getPointerInfo().getWithOffset(IncrementSize),
495 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(),
498 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
501 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
503 SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
504 const TargetLowering &TLI) {
505 SDValue Chain = LD->getChain();
506 SDValue Ptr = LD->getBasePtr();
507 EVT VT = LD->getValueType(0);
508 EVT LoadedVT = LD->getMemoryVT();
509 DebugLoc dl = LD->getDebugLoc();
510 if (VT.isFloatingPoint() || VT.isVector()) {
511 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
512 if (TLI.isTypeLegal(intVT)) {
513 // Expand to a (misaligned) integer load of the same size,
514 // then bitconvert to floating point or vector.
515 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getPointerInfo(),
517 LD->isNonTemporal(), LD->getAlignment());
518 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, LoadedVT, newLoad);
519 if (VT.isFloatingPoint() && LoadedVT != VT)
520 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result);
522 SDValue Ops[] = { Result, Chain };
523 return DAG.getMergeValues(Ops, 2, dl);
526 // Copy the value to a (aligned) stack slot using (unaligned) integer
527 // loads and stores, then do a (aligned) load from the stack slot.
528 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
529 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
530 unsigned RegBytes = RegVT.getSizeInBits() / 8;
531 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
533 // Make sure the stack slot is also aligned for the register type.
534 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
536 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
537 SmallVector<SDValue, 8> Stores;
538 SDValue StackPtr = StackBase;
541 // Do all but one copies using the full register width.
542 for (unsigned i = 1; i < NumRegs; i++) {
543 // Load one integer register's worth from the original location.
544 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr,
545 LD->getPointerInfo().getWithOffset(Offset),
546 LD->isVolatile(), LD->isNonTemporal(),
547 MinAlign(LD->getAlignment(), Offset));
548 // Follow the load with a store to the stack slot. Remember the store.
549 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
550 MachinePointerInfo(), false, false, 0));
551 // Increment the pointers.
553 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
554 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
558 // The last copy may be partial. Do an extending load.
559 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
560 8 * (LoadedBytes - Offset));
561 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, RegVT, dl, Chain, Ptr,
562 LD->getPointerInfo().getWithOffset(Offset),
563 MemVT, LD->isVolatile(),
565 MinAlign(LD->getAlignment(), Offset));
566 // Follow the load with a store to the stack slot. Remember the store.
567 // On big-endian machines this requires a truncating store to ensure
568 // that the bits end up in the right place.
569 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
570 MachinePointerInfo(), MemVT,
573 // The order of the stores doesn't matter - say it with a TokenFactor.
574 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
577 // Finally, perform the original load only redirected to the stack slot.
578 Load = DAG.getExtLoad(LD->getExtensionType(), VT, dl, TF, StackBase,
579 MachinePointerInfo(), LoadedVT, false, false, 0);
581 // Callers expect a MERGE_VALUES node.
582 SDValue Ops[] = { Load, TF };
583 return DAG.getMergeValues(Ops, 2, dl);
585 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
586 "Unaligned load of unsupported type.");
588 // Compute the new VT that is half the size of the old one. This is an
590 unsigned NumBits = LoadedVT.getSizeInBits();
592 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
595 unsigned Alignment = LD->getAlignment();
596 unsigned IncrementSize = NumBits / 8;
597 ISD::LoadExtType HiExtType = LD->getExtensionType();
599 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
600 if (HiExtType == ISD::NON_EXTLOAD)
601 HiExtType = ISD::ZEXTLOAD;
603 // Load the value in two parts
605 if (TLI.isLittleEndian()) {
606 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, dl, Chain, Ptr, LD->getPointerInfo(),
607 NewLoadedVT, LD->isVolatile(),
608 LD->isNonTemporal(), Alignment);
609 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
610 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
611 Hi = DAG.getExtLoad(HiExtType, VT, dl, Chain, Ptr,
612 LD->getPointerInfo().getWithOffset(IncrementSize),
613 NewLoadedVT, LD->isVolatile(),
614 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
616 Hi = DAG.getExtLoad(HiExtType, VT, dl, Chain, Ptr, LD->getPointerInfo(),
617 NewLoadedVT, LD->isVolatile(),
618 LD->isNonTemporal(), Alignment);
619 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
620 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
621 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, dl, Chain, Ptr,
622 LD->getPointerInfo().getWithOffset(IncrementSize),
623 NewLoadedVT, LD->isVolatile(),
624 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
627 // aggregate the two parts
628 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
629 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
630 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
632 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
635 SDValue Ops[] = { Result, TF };
636 return DAG.getMergeValues(Ops, 2, dl);
639 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
640 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
641 /// is necessary to spill the vector being inserted into to memory, perform
642 /// the insert there, and then read the result back.
643 SDValue SelectionDAGLegalize::
644 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
650 // If the target doesn't support this, we have to spill the input vector
651 // to a temporary stack slot, update the element, then reload it. This is
652 // badness. We could also load the value into a vector register (either
653 // with a "move to register" or "extload into register" instruction, then
654 // permute it into place, if the idx is a constant and if the idx is
655 // supported by the target.
656 EVT VT = Tmp1.getValueType();
657 EVT EltVT = VT.getVectorElementType();
658 EVT IdxVT = Tmp3.getValueType();
659 EVT PtrVT = TLI.getPointerTy();
660 SDValue StackPtr = DAG.CreateStackTemporary(VT);
662 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
665 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
666 MachinePointerInfo::getFixedStack(SPFI),
669 // Truncate or zero extend offset to target pointer type.
670 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
671 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
672 // Add the offset to the index.
673 unsigned EltSize = EltVT.getSizeInBits()/8;
674 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
675 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
676 // Store the scalar value.
677 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT,
679 // Load the updated vector.
680 return DAG.getLoad(VT, dl, Ch, StackPtr,
681 MachinePointerInfo::getFixedStack(SPFI), false, false, 0);
685 SDValue SelectionDAGLegalize::
686 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) {
687 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
688 // SCALAR_TO_VECTOR requires that the type of the value being inserted
689 // match the element type of the vector being created, except for
690 // integers in which case the inserted value can be over width.
691 EVT EltVT = Vec.getValueType().getVectorElementType();
692 if (Val.getValueType() == EltVT ||
693 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
694 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
695 Vec.getValueType(), Val);
697 unsigned NumElts = Vec.getValueType().getVectorNumElements();
698 // We generate a shuffle of InVec and ScVec, so the shuffle mask
699 // should be 0,1,2,3,4,5... with the appropriate element replaced with
701 SmallVector<int, 8> ShufOps;
702 for (unsigned i = 0; i != NumElts; ++i)
703 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
705 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
709 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
712 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
713 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
714 // FIXME: We shouldn't do this for TargetConstantFP's.
715 // FIXME: move this to the DAG Combiner! Note that we can't regress due
716 // to phase ordering between legalized code and the dag combiner. This
717 // probably means that we need to integrate dag combiner and legalizer
719 // We generally can't do this one for long doubles.
720 SDValue Tmp1 = ST->getChain();
721 SDValue Tmp2 = ST->getBasePtr();
723 unsigned Alignment = ST->getAlignment();
724 bool isVolatile = ST->isVolatile();
725 bool isNonTemporal = ST->isNonTemporal();
726 DebugLoc dl = ST->getDebugLoc();
727 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
728 if (CFP->getValueType(0) == MVT::f32 &&
729 getTypeAction(MVT::i32) == Legal) {
730 Tmp3 = DAG.getConstant(CFP->getValueAPF().
731 bitcastToAPInt().zextOrTrunc(32),
733 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
734 isVolatile, isNonTemporal, Alignment);
737 if (CFP->getValueType(0) == MVT::f64) {
738 // If this target supports 64-bit registers, do a single 64-bit store.
739 if (getTypeAction(MVT::i64) == Legal) {
740 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
741 zextOrTrunc(64), MVT::i64);
742 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
743 isVolatile, isNonTemporal, Alignment);
746 if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
747 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
748 // stores. If the target supports neither 32- nor 64-bits, this
749 // xform is certainly not worth it.
750 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
751 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
752 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
753 if (TLI.isBigEndian()) std::swap(Lo, Hi);
755 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getPointerInfo(), isVolatile,
756 isNonTemporal, Alignment);
757 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
758 DAG.getIntPtrConstant(4));
759 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2,
760 ST->getPointerInfo().getWithOffset(4),
761 isVolatile, isNonTemporal, MinAlign(Alignment, 4U));
763 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
770 /// LegalizeOp - We know that the specified value has a legal type, and
771 /// that its operands are legal. Now ensure that the operation itself
772 /// is legal, recursively ensuring that the operands' operations remain
774 SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
775 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
778 SDNode *Node = Op.getNode();
779 DebugLoc dl = Node->getDebugLoc();
781 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
782 assert(getTypeAction(Node->getValueType(i)) == Legal &&
783 "Unexpected illegal type!");
785 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
786 assert((isTypeLegal(Node->getOperand(i).getValueType()) ||
787 Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
788 "Unexpected illegal type!");
790 // Note that LegalizeOp may be reentered even from single-use nodes, which
791 // means that we always must cache transformed nodes.
792 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
793 if (I != LegalizedNodes.end()) return I->second;
795 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
797 bool isCustom = false;
799 // Figure out the correct action; the way to query this varies by opcode
800 TargetLowering::LegalizeAction Action;
801 bool SimpleFinishLegalizing = true;
802 switch (Node->getOpcode()) {
803 case ISD::INTRINSIC_W_CHAIN:
804 case ISD::INTRINSIC_WO_CHAIN:
805 case ISD::INTRINSIC_VOID:
808 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
810 case ISD::SINT_TO_FP:
811 case ISD::UINT_TO_FP:
812 case ISD::EXTRACT_VECTOR_ELT:
813 Action = TLI.getOperationAction(Node->getOpcode(),
814 Node->getOperand(0).getValueType());
816 case ISD::FP_ROUND_INREG:
817 case ISD::SIGN_EXTEND_INREG: {
818 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
819 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
825 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
826 Node->getOpcode() == ISD::SETCC ? 2 : 1;
827 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
828 EVT OpVT = Node->getOperand(CompareOperand).getValueType();
829 ISD::CondCode CCCode =
830 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
831 Action = TLI.getCondCodeAction(CCCode, OpVT);
832 if (Action == TargetLowering::Legal) {
833 if (Node->getOpcode() == ISD::SELECT_CC)
834 Action = TLI.getOperationAction(Node->getOpcode(),
835 Node->getValueType(0));
837 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
843 // FIXME: Model these properly. LOAD and STORE are complicated, and
844 // STORE expects the unlegalized operand in some cases.
845 SimpleFinishLegalizing = false;
847 case ISD::CALLSEQ_START:
848 case ISD::CALLSEQ_END:
849 // FIXME: This shouldn't be necessary. These nodes have special properties
850 // dealing with the recursive nature of legalization. Removing this
851 // special case should be done as part of making LegalizeDAG non-recursive.
852 SimpleFinishLegalizing = false;
854 case ISD::EXTRACT_ELEMENT:
855 case ISD::FLT_ROUNDS_:
863 case ISD::MERGE_VALUES:
865 case ISD::FRAME_TO_ARGS_OFFSET:
866 case ISD::EH_SJLJ_SETJMP:
867 case ISD::EH_SJLJ_LONGJMP:
868 // These operations lie about being legal: when they claim to be legal,
869 // they should actually be expanded.
870 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
871 if (Action == TargetLowering::Legal)
872 Action = TargetLowering::Expand;
874 case ISD::TRAMPOLINE:
876 case ISD::RETURNADDR:
877 // These operations lie about being legal: when they claim to be legal,
878 // they should actually be custom-lowered.
879 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
880 if (Action == TargetLowering::Legal)
881 Action = TargetLowering::Custom;
883 case ISD::BUILD_VECTOR:
884 // A weird case: legalization for BUILD_VECTOR never legalizes the
886 // FIXME: This really sucks... changing it isn't semantically incorrect,
887 // but it massively pessimizes the code for floating-point BUILD_VECTORs
888 // because ConstantFP operands get legalized into constant pool loads
889 // before the BUILD_VECTOR code can see them. It doesn't usually bite,
890 // though, because BUILD_VECTORS usually get lowered into other nodes
891 // which get legalized properly.
892 SimpleFinishLegalizing = false;
895 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
896 Action = TargetLowering::Legal;
898 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
903 if (SimpleFinishLegalizing) {
904 SmallVector<SDValue, 8> Ops, ResultVals;
905 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
906 Ops.push_back(LegalizeOp(Node->getOperand(i)));
907 switch (Node->getOpcode()) {
914 // Branches tweak the chain to include LastCALLSEQ_END
915 Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0],
917 Ops[0] = LegalizeOp(Ops[0]);
918 LastCALLSEQ_END = DAG.getEntryNode();
925 // Legalizing shifts/rotates requires adjusting the shift amount
926 // to the appropriate width.
927 if (!Ops[1].getValueType().isVector())
928 Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[1]));
933 // Legalizing shifts/rotates requires adjusting the shift amount
934 // to the appropriate width.
935 if (!Ops[2].getValueType().isVector())
936 Ops[2] = LegalizeOp(DAG.getShiftAmountOperand(Ops[2]));
940 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), Ops.data(),
943 case TargetLowering::Legal:
944 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
945 ResultVals.push_back(Result.getValue(i));
947 case TargetLowering::Custom:
948 // FIXME: The handling for custom lowering with multiple results is
950 Tmp1 = TLI.LowerOperation(Result, DAG);
951 if (Tmp1.getNode()) {
952 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
954 ResultVals.push_back(Tmp1);
956 ResultVals.push_back(Tmp1.getValue(i));
962 case TargetLowering::Expand:
963 ExpandNode(Result.getNode(), ResultVals);
965 case TargetLowering::Promote:
966 PromoteNode(Result.getNode(), ResultVals);
969 if (!ResultVals.empty()) {
970 for (unsigned i = 0, e = ResultVals.size(); i != e; ++i) {
971 if (ResultVals[i] != SDValue(Node, i))
972 ResultVals[i] = LegalizeOp(ResultVals[i]);
973 AddLegalizedOperand(SDValue(Node, i), ResultVals[i]);
975 return ResultVals[Op.getResNo()];
979 switch (Node->getOpcode()) {
986 assert(0 && "Do not know how to legalize this operator!");
988 case ISD::BUILD_VECTOR:
989 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
990 default: assert(0 && "This action is not supported yet!");
991 case TargetLowering::Custom:
992 Tmp3 = TLI.LowerOperation(Result, DAG);
993 if (Tmp3.getNode()) {
998 case TargetLowering::Expand:
999 Result = ExpandBUILD_VECTOR(Result.getNode());
1003 case ISD::CALLSEQ_START: {
1004 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1006 // Recursively Legalize all of the inputs of the call end that do not lead
1007 // to this call start. This ensures that any libcalls that need be inserted
1008 // are inserted *before* the CALLSEQ_START.
1009 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1010 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1011 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
1015 // Now that we have legalized all of the inputs (which may have inserted
1016 // libcalls), create the new CALLSEQ_START node.
1017 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1019 // Merge in the last call to ensure that this call starts after the last
1021 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1022 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1023 Tmp1, LastCALLSEQ_END);
1024 Tmp1 = LegalizeOp(Tmp1);
1027 // Do not try to legalize the target-specific arguments (#1+).
1028 if (Tmp1 != Node->getOperand(0)) {
1029 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1031 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), &Ops[0],
1032 Ops.size()), Result.getResNo());
1035 // Remember that the CALLSEQ_START is legalized.
1036 AddLegalizedOperand(Op.getValue(0), Result);
1037 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1038 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1040 // Now that the callseq_start and all of the non-call nodes above this call
1041 // sequence have been legalized, legalize the call itself. During this
1042 // process, no libcalls can/will be inserted, guaranteeing that no calls
1044 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1045 // Note that we are selecting this call!
1046 LastCALLSEQ_END = SDValue(CallEnd, 0);
1047 IsLegalizingCall = true;
1049 // Legalize the call, starting from the CALLSEQ_END.
1050 LegalizeOp(LastCALLSEQ_END);
1051 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1054 case ISD::CALLSEQ_END:
1055 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1056 // will cause this node to be legalized as well as handling libcalls right.
1057 if (LastCALLSEQ_END.getNode() != Node) {
1058 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
1059 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1060 assert(I != LegalizedNodes.end() &&
1061 "Legalizing the call start should have legalized this node!");
1065 // Otherwise, the call start has been legalized and everything is going
1066 // according to plan. Just legalize ourselves normally here.
1067 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1068 // Do not try to legalize the target-specific arguments (#1+), except for
1069 // an optional flag input.
1070 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1071 if (Tmp1 != Node->getOperand(0)) {
1072 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1074 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1075 &Ops[0], Ops.size()),
1079 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1080 if (Tmp1 != Node->getOperand(0) ||
1081 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1082 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1085 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1086 &Ops[0], Ops.size()),
1090 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1091 // This finishes up call legalization.
1092 IsLegalizingCall = false;
1094 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1095 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1096 if (Node->getNumValues() == 2)
1097 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1098 return Result.getValue(Op.getResNo());
1100 LoadSDNode *LD = cast<LoadSDNode>(Node);
1101 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1102 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1104 ISD::LoadExtType ExtType = LD->getExtensionType();
1105 if (ExtType == ISD::NON_EXTLOAD) {
1106 EVT VT = Node->getValueType(0);
1107 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1108 Tmp1, Tmp2, LD->getOffset()),
1110 Tmp3 = Result.getValue(0);
1111 Tmp4 = Result.getValue(1);
1113 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1114 default: assert(0 && "This action is not supported yet!");
1115 case TargetLowering::Legal:
1116 // If this is an unaligned load and the target doesn't support it,
1118 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
1119 const Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1120 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
1121 if (LD->getAlignment() < ABIAlignment){
1122 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
1124 Tmp3 = Result.getOperand(0);
1125 Tmp4 = Result.getOperand(1);
1126 Tmp3 = LegalizeOp(Tmp3);
1127 Tmp4 = LegalizeOp(Tmp4);
1131 case TargetLowering::Custom:
1132 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1133 if (Tmp1.getNode()) {
1134 Tmp3 = LegalizeOp(Tmp1);
1135 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1138 case TargetLowering::Promote: {
1139 // Only promote a load of vector type to another.
1140 assert(VT.isVector() && "Cannot promote this load!");
1141 // Change base type to a different vector type.
1142 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1144 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getPointerInfo(),
1145 LD->isVolatile(), LD->isNonTemporal(),
1146 LD->getAlignment());
1147 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp1));
1148 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1152 // Since loads produce two values, make sure to remember that we
1153 // legalized both of them.
1154 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
1155 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
1156 return Op.getResNo() ? Tmp4 : Tmp3;
1159 EVT SrcVT = LD->getMemoryVT();
1160 unsigned SrcWidth = SrcVT.getSizeInBits();
1161 unsigned Alignment = LD->getAlignment();
1162 bool isVolatile = LD->isVolatile();
1163 bool isNonTemporal = LD->isNonTemporal();
1165 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
1166 // Some targets pretend to have an i1 loading operation, and actually
1167 // load an i8. This trick is correct for ZEXTLOAD because the top 7
1168 // bits are guaranteed to be zero; it helps the optimizers understand
1169 // that these bits are zero. It is also useful for EXTLOAD, since it
1170 // tells the optimizers that those bits are undefined. It would be
1171 // nice to have an effective generic way of getting these benefits...
1172 // Until such a way is found, don't insist on promoting i1 here.
1173 (SrcVT != MVT::i1 ||
1174 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
1175 // Promote to a byte-sized load if not loading an integral number of
1176 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
1177 unsigned NewWidth = SrcVT.getStoreSizeInBits();
1178 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
1181 // The extra bits are guaranteed to be zero, since we stored them that
1182 // way. A zext load from NVT thus automatically gives zext from SrcVT.
1184 ISD::LoadExtType NewExtType =
1185 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
1187 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0), dl,
1188 Tmp1, Tmp2, LD->getPointerInfo(),
1189 NVT, isVolatile, isNonTemporal, Alignment);
1191 Ch = Result.getValue(1); // The chain.
1193 if (ExtType == ISD::SEXTLOAD)
1194 // Having the top bits zero doesn't help when sign extending.
1195 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1196 Result.getValueType(),
1197 Result, DAG.getValueType(SrcVT));
1198 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
1199 // All the top bits are guaranteed to be zero - inform the optimizers.
1200 Result = DAG.getNode(ISD::AssertZext, dl,
1201 Result.getValueType(), Result,
1202 DAG.getValueType(SrcVT));
1204 Tmp1 = LegalizeOp(Result);
1205 Tmp2 = LegalizeOp(Ch);
1206 } else if (SrcWidth & (SrcWidth - 1)) {
1207 // If not loading a power-of-2 number of bits, expand as two loads.
1208 assert(!SrcVT.isVector() && "Unsupported extload!");
1209 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
1210 assert(RoundWidth < SrcWidth);
1211 unsigned ExtraWidth = SrcWidth - RoundWidth;
1212 assert(ExtraWidth < RoundWidth);
1213 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1214 "Load size not an integral number of bytes!");
1215 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
1216 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
1218 unsigned IncrementSize;
1220 if (TLI.isLittleEndian()) {
1221 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1222 // Load the bottom RoundWidth bits.
1223 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), dl,
1225 LD->getPointerInfo(), RoundVT, isVolatile,
1226 isNonTemporal, Alignment);
1228 // Load the remaining ExtraWidth bits.
1229 IncrementSize = RoundWidth / 8;
1230 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1231 DAG.getIntPtrConstant(IncrementSize));
1232 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), dl, Tmp1, Tmp2,
1233 LD->getPointerInfo().getWithOffset(IncrementSize),
1234 ExtraVT, isVolatile, isNonTemporal,
1235 MinAlign(Alignment, IncrementSize));
1237 // Build a factor node to remember that this load is independent of
1239 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1242 // Move the top bits to the right place.
1243 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1244 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
1246 // Join the hi and lo parts.
1247 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1249 // Big endian - avoid unaligned loads.
1250 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1251 // Load the top RoundWidth bits.
1252 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), dl, Tmp1, Tmp2,
1253 LD->getPointerInfo(), RoundVT, isVolatile,
1254 isNonTemporal, Alignment);
1256 // Load the remaining ExtraWidth bits.
1257 IncrementSize = RoundWidth / 8;
1258 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1259 DAG.getIntPtrConstant(IncrementSize));
1260 Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
1261 Node->getValueType(0), dl, Tmp1, Tmp2,
1262 LD->getPointerInfo().getWithOffset(IncrementSize),
1263 ExtraVT, isVolatile, isNonTemporal,
1264 MinAlign(Alignment, IncrementSize));
1266 // Build a factor node to remember that this load is independent of
1268 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1271 // Move the top bits to the right place.
1272 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1273 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
1275 // Join the hi and lo parts.
1276 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1279 Tmp1 = LegalizeOp(Result);
1280 Tmp2 = LegalizeOp(Ch);
1282 switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
1283 default: assert(0 && "This action is not supported yet!");
1284 case TargetLowering::Custom:
1287 case TargetLowering::Legal:
1288 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1289 Tmp1, Tmp2, LD->getOffset()),
1291 Tmp1 = Result.getValue(0);
1292 Tmp2 = Result.getValue(1);
1295 Tmp3 = TLI.LowerOperation(Result, DAG);
1296 if (Tmp3.getNode()) {
1297 Tmp1 = LegalizeOp(Tmp3);
1298 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1301 // If this is an unaligned load and the target doesn't support it,
1303 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
1305 LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1306 unsigned ABIAlignment =
1307 TLI.getTargetData()->getABITypeAlignment(Ty);
1308 if (LD->getAlignment() < ABIAlignment){
1309 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
1311 Tmp1 = Result.getOperand(0);
1312 Tmp2 = Result.getOperand(1);
1313 Tmp1 = LegalizeOp(Tmp1);
1314 Tmp2 = LegalizeOp(Tmp2);
1319 case TargetLowering::Expand:
1320 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) && isTypeLegal(SrcVT)) {
1321 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2,
1322 LD->getPointerInfo(),
1323 LD->isVolatile(), LD->isNonTemporal(),
1324 LD->getAlignment());
1328 ExtendOp = (SrcVT.isFloatingPoint() ?
1329 ISD::FP_EXTEND : ISD::ANY_EXTEND);
1331 case ISD::SEXTLOAD: ExtendOp = ISD::SIGN_EXTEND; break;
1332 case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break;
1333 default: llvm_unreachable("Unexpected extend load type!");
1335 Result = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
1336 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1337 Tmp2 = LegalizeOp(Load.getValue(1));
1340 // FIXME: This does not work for vectors on most targets. Sign- and
1341 // zero-extend operations are currently folded into extending loads,
1342 // whether they are legal or not, and then we end up here without any
1343 // support for legalizing them.
1344 assert(ExtType != ISD::EXTLOAD &&
1345 "EXTLOAD should always be supported!");
1346 // Turn the unsupported load into an EXTLOAD followed by an explicit
1347 // zero/sign extend inreg.
1348 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), dl,
1349 Tmp1, Tmp2, LD->getPointerInfo(), SrcVT,
1350 LD->isVolatile(), LD->isNonTemporal(),
1351 LD->getAlignment());
1353 if (ExtType == ISD::SEXTLOAD)
1354 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1355 Result.getValueType(),
1356 Result, DAG.getValueType(SrcVT));
1358 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT);
1359 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1360 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1365 // Since loads produce two values, make sure to remember that we legalized
1367 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
1368 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
1369 return Op.getResNo() ? Tmp2 : Tmp1;
1372 StoreSDNode *ST = cast<StoreSDNode>(Node);
1373 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
1374 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
1375 unsigned Alignment = ST->getAlignment();
1376 bool isVolatile = ST->isVolatile();
1377 bool isNonTemporal = ST->isNonTemporal();
1379 if (!ST->isTruncatingStore()) {
1380 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
1381 Result = SDValue(OptStore, 0);
1386 Tmp3 = LegalizeOp(ST->getValue());
1387 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1392 EVT VT = Tmp3.getValueType();
1393 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1394 default: assert(0 && "This action is not supported yet!");
1395 case TargetLowering::Legal:
1396 // If this is an unaligned store and the target doesn't support it,
1398 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
1399 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
1400 unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty);
1401 if (ST->getAlignment() < ABIAlignment)
1402 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()),
1406 case TargetLowering::Custom:
1407 Tmp1 = TLI.LowerOperation(Result, DAG);
1408 if (Tmp1.getNode()) Result = Tmp1;
1410 case TargetLowering::Promote:
1411 assert(VT.isVector() && "Unknown legal promote case!");
1412 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, dl,
1413 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
1414 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2,
1415 ST->getPointerInfo(), isVolatile,
1416 isNonTemporal, Alignment);
1422 Tmp3 = LegalizeOp(ST->getValue());
1424 EVT StVT = ST->getMemoryVT();
1425 unsigned StWidth = StVT.getSizeInBits();
1427 if (StWidth != StVT.getStoreSizeInBits()) {
1428 // Promote to a byte-sized store with upper bits zero if not
1429 // storing an integral number of bytes. For example, promote
1430 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
1431 EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
1432 StVT.getStoreSizeInBits());
1433 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT);
1434 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
1435 NVT, isVolatile, isNonTemporal, Alignment);
1436 } else if (StWidth & (StWidth - 1)) {
1437 // If not storing a power-of-2 number of bits, expand as two stores.
1438 assert(!StVT.isVector() && "Unsupported truncstore!");
1439 unsigned RoundWidth = 1 << Log2_32(StWidth);
1440 assert(RoundWidth < StWidth);
1441 unsigned ExtraWidth = StWidth - RoundWidth;
1442 assert(ExtraWidth < RoundWidth);
1443 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1444 "Store size not an integral number of bytes!");
1445 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
1446 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
1448 unsigned IncrementSize;
1450 if (TLI.isLittleEndian()) {
1451 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
1452 // Store the bottom RoundWidth bits.
1453 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
1455 isVolatile, isNonTemporal, Alignment);
1457 // Store the remaining ExtraWidth bits.
1458 IncrementSize = RoundWidth / 8;
1459 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1460 DAG.getIntPtrConstant(IncrementSize));
1461 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
1462 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
1463 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2,
1464 ST->getPointerInfo().getWithOffset(IncrementSize),
1465 ExtraVT, isVolatile, isNonTemporal,
1466 MinAlign(Alignment, IncrementSize));
1468 // Big endian - avoid unaligned stores.
1469 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
1470 // Store the top RoundWidth bits.
1471 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
1472 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
1473 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getPointerInfo(),
1474 RoundVT, isVolatile, isNonTemporal, Alignment);
1476 // Store the remaining ExtraWidth bits.
1477 IncrementSize = RoundWidth / 8;
1478 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1479 DAG.getIntPtrConstant(IncrementSize));
1480 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2,
1481 ST->getPointerInfo().getWithOffset(IncrementSize),
1482 ExtraVT, isVolatile, isNonTemporal,
1483 MinAlign(Alignment, IncrementSize));
1486 // The order of the stores doesn't matter.
1487 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
1489 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
1490 Tmp2 != ST->getBasePtr())
1491 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1496 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
1497 default: assert(0 && "This action is not supported yet!");
1498 case TargetLowering::Legal:
1499 // If this is an unaligned store and the target doesn't support it,
1501 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
1502 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
1503 unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty);
1504 if (ST->getAlignment() < ABIAlignment)
1505 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()),
1509 case TargetLowering::Custom:
1510 Result = TLI.LowerOperation(Result, DAG);
1513 // TRUNCSTORE:i16 i32 -> STORE i16
1514 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
1515 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3);
1516 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
1517 isVolatile, isNonTemporal, Alignment);
1525 assert(Result.getValueType() == Op.getValueType() &&
1526 "Bad legalization!");
1528 // Make sure that the generated code is itself legal.
1530 Result = LegalizeOp(Result);
1532 // Note that LegalizeOp may be reentered even from single-use nodes, which
1533 // means that we always must cache transformed nodes.
1534 AddLegalizedOperand(Op, Result);
1538 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1539 SDValue Vec = Op.getOperand(0);
1540 SDValue Idx = Op.getOperand(1);
1541 DebugLoc dl = Op.getDebugLoc();
1542 // Store the value to a temporary stack slot, then LOAD the returned part.
1543 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1544 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1545 MachinePointerInfo(), false, false, 0);
1547 // Add the offset to the index.
1549 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1550 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1551 DAG.getConstant(EltSize, Idx.getValueType()));
1553 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1554 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1556 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1558 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1560 if (Op.getValueType().isVector())
1561 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,MachinePointerInfo(),
1563 return DAG.getExtLoad(ISD::EXTLOAD, Op.getValueType(), dl, Ch, StackPtr,
1564 MachinePointerInfo(),
1565 Vec.getValueType().getVectorElementType(),
1569 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1570 // We can't handle this case efficiently. Allocate a sufficiently
1571 // aligned object on the stack, store each element into it, then load
1572 // the result as a vector.
1573 // Create the stack frame object.
1574 EVT VT = Node->getValueType(0);
1575 EVT EltVT = VT.getVectorElementType();
1576 DebugLoc dl = Node->getDebugLoc();
1577 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1578 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1579 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1581 // Emit a store of each element to the stack slot.
1582 SmallVector<SDValue, 8> Stores;
1583 unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1584 // Store (in the right endianness) the elements to memory.
1585 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1586 // Ignore undef elements.
1587 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1589 unsigned Offset = TypeByteSize*i;
1591 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
1592 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1594 // If the destination vector element type is narrower than the source
1595 // element type, only store the bits necessary.
1596 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1597 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1598 Node->getOperand(i), Idx,
1599 PtrInfo.getWithOffset(Offset),
1600 EltVT, false, false, 0));
1602 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
1603 Node->getOperand(i), Idx,
1604 PtrInfo.getWithOffset(Offset),
1609 if (!Stores.empty()) // Not all undef elements?
1610 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1611 &Stores[0], Stores.size());
1613 StoreChain = DAG.getEntryNode();
1615 // Result is a load from the stack slot.
1616 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo, false, false, 0);
1619 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
1620 DebugLoc dl = Node->getDebugLoc();
1621 SDValue Tmp1 = Node->getOperand(0);
1622 SDValue Tmp2 = Node->getOperand(1);
1624 // Get the sign bit of the RHS. First obtain a value that has the same
1625 // sign as the sign bit, i.e. negative if and only if the sign bit is 1.
1627 EVT FloatVT = Tmp2.getValueType();
1628 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits());
1629 if (isTypeLegal(IVT)) {
1630 // Convert to an integer with the same sign bit.
1631 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, IVT, Tmp2);
1633 // Store the float to memory, then load the sign part out as an integer.
1634 MVT LoadTy = TLI.getPointerTy();
1635 // First create a temporary that is aligned for both the load and store.
1636 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1637 // Then store the float to it.
1639 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, MachinePointerInfo(),
1641 if (TLI.isBigEndian()) {
1642 assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1643 // Load out a legal integer with the same sign bit as the float.
1644 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, MachinePointerInfo(),
1646 } else { // Little endian
1647 SDValue LoadPtr = StackPtr;
1648 // The float may be wider than the integer we are going to load. Advance
1649 // the pointer so that the loaded integer will contain the sign bit.
1650 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits();
1651 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8;
1652 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(),
1653 LoadPtr, DAG.getIntPtrConstant(ByteOffset));
1654 // Load a legal integer containing the sign bit.
1655 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(),
1657 // Move the sign bit to the top bit of the loaded integer.
1658 unsigned BitShift = LoadTy.getSizeInBits() -
1659 (FloatVT.getSizeInBits() - 8 * ByteOffset);
1660 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?");
1662 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit,
1663 DAG.getConstant(BitShift,TLI.getShiftAmountTy()));
1666 // Now get the sign bit proper, by seeing whether the value is negative.
1667 SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()),
1668 SignBit, DAG.getConstant(0, SignBit.getValueType()),
1670 // Get the absolute value of the result.
1671 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1672 // Select between the nabs and abs value based on the sign bit of
1674 return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit,
1675 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1679 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1680 SmallVectorImpl<SDValue> &Results) {
1681 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1682 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1683 " not tell us which reg is the stack pointer!");
1684 DebugLoc dl = Node->getDebugLoc();
1685 EVT VT = Node->getValueType(0);
1686 SDValue Tmp1 = SDValue(Node, 0);
1687 SDValue Tmp2 = SDValue(Node, 1);
1688 SDValue Tmp3 = Node->getOperand(2);
1689 SDValue Chain = Tmp1.getOperand(0);
1691 // Chain the dynamic stack allocation so that it doesn't modify the stack
1692 // pointer when other instructions are using the stack.
1693 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1695 SDValue Size = Tmp2.getOperand(1);
1696 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1697 Chain = SP.getValue(1);
1698 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1699 unsigned StackAlign = TM.getFrameInfo()->getStackAlignment();
1700 if (Align > StackAlign)
1701 SP = DAG.getNode(ISD::AND, dl, VT, SP,
1702 DAG.getConstant(-(uint64_t)Align, VT));
1703 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1704 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1706 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1707 DAG.getIntPtrConstant(0, true), SDValue());
1709 Results.push_back(Tmp1);
1710 Results.push_back(Tmp2);
1713 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
1714 /// condition code CC on the current target. This routine expands SETCC with
1715 /// illegal condition code into AND / OR of multiple SETCC values.
1716 void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1717 SDValue &LHS, SDValue &RHS,
1720 EVT OpVT = LHS.getValueType();
1721 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1722 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1723 default: assert(0 && "Unknown condition code action!");
1724 case TargetLowering::Legal:
1727 case TargetLowering::Expand: {
1728 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1731 default: assert(0 && "Don't know how to expand this condition!");
1732 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break;
1733 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1734 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1735 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1736 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1737 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1738 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1739 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1740 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1741 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1742 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1743 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1744 // FIXME: Implement more expansions.
1747 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1748 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1749 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1757 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
1758 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1759 /// a load from the stack slot to DestVT, extending it if needed.
1760 /// The resultant code need not be legal.
1761 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
1765 // Create the stack frame object.
1767 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType().
1768 getTypeForEVT(*DAG.getContext()));
1769 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1771 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1772 int SPFI = StackPtrFI->getIndex();
1773 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(SPFI);
1775 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
1776 unsigned SlotSize = SlotVT.getSizeInBits();
1777 unsigned DestSize = DestVT.getSizeInBits();
1778 const Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
1779 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(DestType);
1781 // Emit a store to the stack slot. Use a truncstore if the input value is
1782 // later than DestVT.
1785 if (SrcSize > SlotSize)
1786 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1787 PtrInfo, SlotVT, false, false, SrcAlign);
1789 assert(SrcSize == SlotSize && "Invalid store");
1790 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1791 PtrInfo, false, false, SrcAlign);
1794 // Result is a load from the stack slot.
1795 if (SlotSize == DestSize)
1796 return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo,
1797 false, false, DestAlign);
1799 assert(SlotSize < DestSize && "Unknown extension!");
1800 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, dl, Store, FIPtr,
1801 PtrInfo, SlotVT, false, false, DestAlign);
1804 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1805 DebugLoc dl = Node->getDebugLoc();
1806 // Create a vector sized/aligned stack slot, store the value to element #0,
1807 // then load the whole vector back out.
1808 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1810 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1811 int SPFI = StackPtrFI->getIndex();
1813 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0),
1815 MachinePointerInfo::getFixedStack(SPFI),
1816 Node->getValueType(0).getVectorElementType(),
1818 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
1819 MachinePointerInfo::getFixedStack(SPFI),
1824 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
1825 /// support the operation, but do support the resultant vector type.
1826 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1827 unsigned NumElems = Node->getNumOperands();
1828 SDValue Value1, Value2;
1829 DebugLoc dl = Node->getDebugLoc();
1830 EVT VT = Node->getValueType(0);
1831 EVT OpVT = Node->getOperand(0).getValueType();
1832 EVT EltVT = VT.getVectorElementType();
1834 // If the only non-undef value is the low element, turn this into a
1835 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1836 bool isOnlyLowElement = true;
1837 bool MoreThanTwoValues = false;
1838 bool isConstant = true;
1839 for (unsigned i = 0; i < NumElems; ++i) {
1840 SDValue V = Node->getOperand(i);
1841 if (V.getOpcode() == ISD::UNDEF)
1844 isOnlyLowElement = false;
1845 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1848 if (!Value1.getNode()) {
1850 } else if (!Value2.getNode()) {
1853 } else if (V != Value1 && V != Value2) {
1854 MoreThanTwoValues = true;
1858 if (!Value1.getNode())
1859 return DAG.getUNDEF(VT);
1861 if (isOnlyLowElement)
1862 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1864 // If all elements are constants, create a load from the constant pool.
1866 std::vector<Constant*> CV;
1867 for (unsigned i = 0, e = NumElems; i != e; ++i) {
1868 if (ConstantFPSDNode *V =
1869 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1870 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1871 } else if (ConstantSDNode *V =
1872 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1874 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1876 // If OpVT and EltVT don't match, EltVT is not legal and the
1877 // element values have been promoted/truncated earlier. Undo this;
1878 // we don't want a v16i8 to become a v16i32 for example.
1879 const ConstantInt *CI = V->getConstantIntValue();
1880 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
1881 CI->getZExtValue()));
1884 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
1885 const Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
1886 CV.push_back(UndefValue::get(OpNTy));
1889 Constant *CP = ConstantVector::get(CV);
1890 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
1891 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
1892 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
1893 MachinePointerInfo::getConstantPool(),
1894 false, false, Alignment);
1897 if (!MoreThanTwoValues) {
1898 SmallVector<int, 8> ShuffleVec(NumElems, -1);
1899 for (unsigned i = 0; i < NumElems; ++i) {
1900 SDValue V = Node->getOperand(i);
1901 if (V.getOpcode() == ISD::UNDEF)
1903 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
1905 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
1906 // Get the splatted value into the low element of a vector register.
1907 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
1909 if (Value2.getNode())
1910 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
1912 Vec2 = DAG.getUNDEF(VT);
1914 // Return shuffle(LowValVec, undef, <0,0,0,0>)
1915 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
1919 // Otherwise, we can't handle this case efficiently.
1920 return ExpandVectorBuildThroughStack(Node);
1923 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
1924 // does not fit into a register, return the lo part and set the hi part to the
1925 // by-reg argument. If it does fit into a single register, return the result
1926 // and leave the Hi part unset.
1927 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
1929 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
1930 // The input chain to this libcall is the entry node of the function.
1931 // Legalizing the call will automatically add the previous call to the
1933 SDValue InChain = DAG.getEntryNode();
1935 TargetLowering::ArgListTy Args;
1936 TargetLowering::ArgListEntry Entry;
1937 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1938 EVT ArgVT = Node->getOperand(i).getValueType();
1939 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1940 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
1941 Entry.isSExt = isSigned;
1942 Entry.isZExt = !isSigned;
1943 Args.push_back(Entry);
1945 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1946 TLI.getPointerTy());
1948 // Splice the libcall in wherever FindInputOutputChains tells us to.
1949 const Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
1950 std::pair<SDValue, SDValue> CallInfo =
1951 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
1952 0, TLI.getLibcallCallingConv(LC), false,
1953 /*isReturnValueUsed=*/true,
1954 Callee, Args, DAG, Node->getDebugLoc());
1956 // Legalize the call sequence, starting with the chain. This will advance
1957 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
1958 // was added by LowerCallTo (guaranteeing proper serialization of calls).
1959 LegalizeOp(CallInfo.second);
1960 return CallInfo.first;
1963 // ExpandChainLibCall - Expand a node into a call to a libcall. Similar to
1964 // ExpandLibCall except that the first operand is the in-chain.
1965 std::pair<SDValue, SDValue>
1966 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
1969 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
1970 SDValue InChain = Node->getOperand(0);
1972 TargetLowering::ArgListTy Args;
1973 TargetLowering::ArgListEntry Entry;
1974 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) {
1975 EVT ArgVT = Node->getOperand(i).getValueType();
1976 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1977 Entry.Node = Node->getOperand(i);
1979 Entry.isSExt = isSigned;
1980 Entry.isZExt = !isSigned;
1981 Args.push_back(Entry);
1983 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1984 TLI.getPointerTy());
1986 // Splice the libcall in wherever FindInputOutputChains tells us to.
1987 const Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
1988 std::pair<SDValue, SDValue> CallInfo =
1989 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
1990 0, TLI.getLibcallCallingConv(LC), false,
1991 /*isReturnValueUsed=*/true,
1992 Callee, Args, DAG, Node->getDebugLoc());
1994 // Legalize the call sequence, starting with the chain. This will advance
1995 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
1996 // was added by LowerCallTo (guaranteeing proper serialization of calls).
1997 LegalizeOp(CallInfo.second);
2001 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
2002 RTLIB::Libcall Call_F32,
2003 RTLIB::Libcall Call_F64,
2004 RTLIB::Libcall Call_F80,
2005 RTLIB::Libcall Call_PPCF128) {
2007 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
2008 default: assert(0 && "Unexpected request for libcall!");
2009 case MVT::f32: LC = Call_F32; break;
2010 case MVT::f64: LC = Call_F64; break;
2011 case MVT::f80: LC = Call_F80; break;
2012 case MVT::ppcf128: LC = Call_PPCF128; break;
2014 return ExpandLibCall(LC, Node, false);
2017 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
2018 RTLIB::Libcall Call_I8,
2019 RTLIB::Libcall Call_I16,
2020 RTLIB::Libcall Call_I32,
2021 RTLIB::Libcall Call_I64,
2022 RTLIB::Libcall Call_I128) {
2024 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
2025 default: assert(0 && "Unexpected request for libcall!");
2026 case MVT::i8: LC = Call_I8; break;
2027 case MVT::i16: LC = Call_I16; break;
2028 case MVT::i32: LC = Call_I32; break;
2029 case MVT::i64: LC = Call_I64; break;
2030 case MVT::i128: LC = Call_I128; break;
2032 return ExpandLibCall(LC, Node, isSigned);
2035 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
2036 /// INT_TO_FP operation of the specified operand when the target requests that
2037 /// we expand it. At this point, we know that the result and operand types are
2038 /// legal for the target.
2039 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
2043 if (Op0.getValueType() == MVT::i32) {
2044 // simple 32-bit [signed|unsigned] integer to float/double expansion
2046 // Get the stack frame index of a 8 byte buffer.
2047 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2049 // word offset constant for Hi/Lo address computation
2050 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
2051 // set up Hi and Lo (into buffer) address based on endian
2052 SDValue Hi = StackSlot;
2053 SDValue Lo = DAG.getNode(ISD::ADD, dl,
2054 TLI.getPointerTy(), StackSlot, WordOff);
2055 if (TLI.isLittleEndian())
2058 // if signed map to unsigned space
2061 // constant used to invert sign bit (signed to unsigned mapping)
2062 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
2063 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2067 // store the lo of the constructed double - based on integer input
2068 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
2069 Op0Mapped, Lo, MachinePointerInfo(),
2071 // initial hi portion of constructed double
2072 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
2073 // store the hi of the constructed double - biased exponent
2074 SDValue Store2 = DAG.getStore(Store1, dl, InitialHi, Hi,
2075 MachinePointerInfo(),
2077 // load the constructed double
2078 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot,
2079 MachinePointerInfo(), false, false, 0);
2080 // FP constant to bias correct the final result
2081 SDValue Bias = DAG.getConstantFP(isSigned ?
2082 BitsToDouble(0x4330000080000000ULL) :
2083 BitsToDouble(0x4330000000000000ULL),
2085 // subtract the bias
2086 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2089 // handle final rounding
2090 if (DestVT == MVT::f64) {
2093 } else if (DestVT.bitsLT(MVT::f64)) {
2094 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2095 DAG.getIntPtrConstant(0));
2096 } else if (DestVT.bitsGT(MVT::f64)) {
2097 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2101 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2102 // Code below here assumes !isSigned without checking again.
2104 // Implementation of unsigned i64 to f64 following the algorithm in
2105 // __floatundidf in compiler_rt. This implementation has the advantage
2106 // of performing rounding correctly, both in the default rounding mode
2107 // and in all alternate rounding modes.
2108 // TODO: Generalize this for use with other types.
2109 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
2111 DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64);
2112 SDValue TwoP84PlusTwoP52 =
2113 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64);
2115 DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64);
2117 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32);
2118 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2119 DAG.getConstant(32, MVT::i64));
2120 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2121 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2122 SDValue LoFlt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, LoOr);
2123 SDValue HiFlt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, HiOr);
2124 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
2126 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
2129 // Implementation of unsigned i64 to f32.
2130 // TODO: Generalize this for use with other types.
2131 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) {
2132 // For unsigned conversions, convert them to signed conversions using the
2133 // algorithm from the x86_64 __floatundidf in compiler_rt.
2135 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0);
2137 SDValue ShiftConst = DAG.getConstant(1, TLI.getShiftAmountTy());
2138 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
2139 SDValue AndConst = DAG.getConstant(1, MVT::i64);
2140 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst);
2141 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr);
2143 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or);
2144 SDValue Slow = DAG.getNode(ISD::FADD, dl, MVT::f32, SignCvt, SignCvt);
2146 // TODO: This really should be implemented using a branch rather than a
2147 // select. We happen to get lucky and machinesink does the right
2148 // thing most of the time. This would be a good candidate for a
2149 //pseudo-op, or, even better, for whole-function isel.
2150 SDValue SignBitTest = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2151 Op0, DAG.getConstant(0, MVT::i64), ISD::SETLT);
2152 return DAG.getNode(ISD::SELECT, dl, MVT::f32, SignBitTest, Slow, Fast);
2155 // Otherwise, implement the fully general conversion.
2156 EVT SHVT = TLI.getShiftAmountTy();
2158 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2159 DAG.getConstant(UINT64_C(0xfffffffffffff800), MVT::i64));
2160 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
2161 DAG.getConstant(UINT64_C(0x800), MVT::i64));
2162 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2163 DAG.getConstant(UINT64_C(0x7ff), MVT::i64));
2164 SDValue Ne = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2165 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE);
2166 SDValue Sel = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ne, Or, Op0);
2167 SDValue Ge = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2168 Op0, DAG.getConstant(UINT64_C(0x0020000000000000), MVT::i64),
2170 SDValue Sel2 = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ge, Sel, Op0);
2172 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2173 DAG.getConstant(32, SHVT));
2174 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh);
2175 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc);
2177 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), MVT::f64);
2178 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt);
2179 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2);
2180 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo);
2181 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2);
2182 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd,
2183 DAG.getIntPtrConstant(0));
2186 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2188 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()),
2189 Op0, DAG.getConstant(0, Op0.getValueType()),
2191 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
2192 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
2193 SignSet, Four, Zero);
2195 // If the sign bit of the integer is set, the large number will be treated
2196 // as a negative number. To counteract this, the dynamic code adds an
2197 // offset depending on the data type.
2199 switch (Op0.getValueType().getSimpleVT().SimpleTy) {
2200 default: assert(0 && "Unsupported integer type!");
2201 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2202 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2203 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2204 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2206 if (TLI.isLittleEndian()) FF <<= 32;
2207 Constant *FudgeFactor = ConstantInt::get(
2208 Type::getInt64Ty(*DAG.getContext()), FF);
2210 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
2211 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2212 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
2213 Alignment = std::min(Alignment, 4u);
2215 if (DestVT == MVT::f32)
2216 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2217 MachinePointerInfo::getConstantPool(),
2218 false, false, Alignment);
2221 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT, dl,
2222 DAG.getEntryNode(), CPIdx,
2223 MachinePointerInfo::getConstantPool(),
2224 MVT::f32, false, false, Alignment));
2227 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2230 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
2231 /// *INT_TO_FP operation of the specified operand when the target requests that
2232 /// we promote it. At this point, we know that the result and operand types are
2233 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2234 /// operation that takes a larger input.
2235 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2239 // First step, figure out the appropriate *INT_TO_FP operation to use.
2240 EVT NewInTy = LegalOp.getValueType();
2242 unsigned OpToUse = 0;
2244 // Scan for the appropriate larger type to use.
2246 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2247 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2249 // If the target supports SINT_TO_FP of this type, use it.
2250 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2251 OpToUse = ISD::SINT_TO_FP;
2254 if (isSigned) continue;
2256 // If the target supports UINT_TO_FP of this type, use it.
2257 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2258 OpToUse = ISD::UINT_TO_FP;
2262 // Otherwise, try a larger type.
2265 // Okay, we found the operation and type to use. Zero extend our input to the
2266 // desired type then run the operation on it.
2267 return DAG.getNode(OpToUse, dl, DestVT,
2268 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2269 dl, NewInTy, LegalOp));
2272 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
2273 /// FP_TO_*INT operation of the specified operand when the target requests that
2274 /// we promote it. At this point, we know that the result and operand types are
2275 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2276 /// operation that returns a larger result.
2277 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2281 // First step, figure out the appropriate FP_TO*INT operation to use.
2282 EVT NewOutTy = DestVT;
2284 unsigned OpToUse = 0;
2286 // Scan for the appropriate larger type to use.
2288 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2289 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2291 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2292 OpToUse = ISD::FP_TO_SINT;
2296 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2297 OpToUse = ISD::FP_TO_UINT;
2301 // Otherwise, try a larger type.
2305 // Okay, we found the operation and type to use.
2306 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2308 // Truncate the result of the extended FP_TO_*INT operation to the desired
2310 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2313 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
2315 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) {
2316 EVT VT = Op.getValueType();
2317 EVT SHVT = TLI.getShiftAmountTy();
2318 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2319 switch (VT.getSimpleVT().SimpleTy) {
2320 default: assert(0 && "Unhandled Expand type in BSWAP!");
2322 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2323 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2324 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2326 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2327 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2328 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2329 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2330 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
2331 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
2332 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2333 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2334 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2336 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
2337 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
2338 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2339 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2340 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2341 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2342 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
2343 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
2344 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
2345 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
2346 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
2347 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
2348 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
2349 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
2350 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2351 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2352 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2353 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2354 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2355 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2356 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2360 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
2362 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2365 default: assert(0 && "Cannot expand this yet!");
2367 static const uint64_t mask[6] = {
2368 0x5555555555555555ULL, 0x3333333333333333ULL,
2369 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
2370 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
2372 EVT VT = Op.getValueType();
2373 EVT ShVT = TLI.getShiftAmountTy();
2374 unsigned len = VT.getSizeInBits();
2375 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2376 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
2377 unsigned EltSize = VT.isVector() ?
2378 VT.getVectorElementType().getSizeInBits() : len;
2379 SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT);
2380 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2381 Op = DAG.getNode(ISD::ADD, dl, VT,
2382 DAG.getNode(ISD::AND, dl, VT, Op, Tmp2),
2383 DAG.getNode(ISD::AND, dl, VT,
2384 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3),
2390 // for now, we do this:
2391 // x = x | (x >> 1);
2392 // x = x | (x >> 2);
2394 // x = x | (x >>16);
2395 // x = x | (x >>32); // for 64-bit input
2396 // return popcount(~x);
2398 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
2399 EVT VT = Op.getValueType();
2400 EVT ShVT = TLI.getShiftAmountTy();
2401 unsigned len = VT.getSizeInBits();
2402 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2403 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2404 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2405 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2407 Op = DAG.getNOT(dl, Op, VT);
2408 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2411 // for now, we use: { return popcount(~x & (x - 1)); }
2412 // unless the target has ctlz but not ctpop, in which case we use:
2413 // { return 32 - nlz(~x & (x-1)); }
2414 // see also http://www.hackersdelight.org/HDcode/ntz.cc
2415 EVT VT = Op.getValueType();
2416 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2417 DAG.getNOT(dl, Op, VT),
2418 DAG.getNode(ISD::SUB, dl, VT, Op,
2419 DAG.getConstant(1, VT)));
2420 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2421 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2422 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2423 return DAG.getNode(ISD::SUB, dl, VT,
2424 DAG.getConstant(VT.getSizeInBits(), VT),
2425 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2426 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2431 std::pair <SDValue, SDValue> SelectionDAGLegalize::ExpandAtomic(SDNode *Node) {
2432 unsigned Opc = Node->getOpcode();
2433 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
2438 llvm_unreachable("Unhandled atomic intrinsic Expand!");
2440 case ISD::ATOMIC_SWAP:
2441 switch (VT.SimpleTy) {
2442 default: llvm_unreachable("Unexpected value type for atomic!");
2443 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break;
2444 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
2445 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
2446 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
2449 case ISD::ATOMIC_CMP_SWAP:
2450 switch (VT.SimpleTy) {
2451 default: llvm_unreachable("Unexpected value type for atomic!");
2452 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break;
2453 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;
2454 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;
2455 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
2458 case ISD::ATOMIC_LOAD_ADD:
2459 switch (VT.SimpleTy) {
2460 default: llvm_unreachable("Unexpected value type for atomic!");
2461 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break;
2462 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;
2463 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;
2464 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
2467 case ISD::ATOMIC_LOAD_SUB:
2468 switch (VT.SimpleTy) {
2469 default: llvm_unreachable("Unexpected value type for atomic!");
2470 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break;
2471 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;
2472 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;
2473 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
2476 case ISD::ATOMIC_LOAD_AND:
2477 switch (VT.SimpleTy) {
2478 default: llvm_unreachable("Unexpected value type for atomic!");
2479 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break;
2480 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;
2481 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;
2482 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
2485 case ISD::ATOMIC_LOAD_OR:
2486 switch (VT.SimpleTy) {
2487 default: llvm_unreachable("Unexpected value type for atomic!");
2488 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break;
2489 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;
2490 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;
2491 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
2494 case ISD::ATOMIC_LOAD_XOR:
2495 switch (VT.SimpleTy) {
2496 default: llvm_unreachable("Unexpected value type for atomic!");
2497 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break;
2498 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;
2499 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;
2500 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
2503 case ISD::ATOMIC_LOAD_NAND:
2504 switch (VT.SimpleTy) {
2505 default: llvm_unreachable("Unexpected value type for atomic!");
2506 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break;
2507 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;
2508 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;
2509 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
2514 return ExpandChainLibCall(LC, Node, false);
2517 void SelectionDAGLegalize::ExpandNode(SDNode *Node,
2518 SmallVectorImpl<SDValue> &Results) {
2519 DebugLoc dl = Node->getDebugLoc();
2520 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2521 switch (Node->getOpcode()) {
2525 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
2526 Results.push_back(Tmp1);
2529 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2531 case ISD::FRAMEADDR:
2532 case ISD::RETURNADDR:
2533 case ISD::FRAME_TO_ARGS_OFFSET:
2534 Results.push_back(DAG.getConstant(0, Node->getValueType(0)));
2536 case ISD::FLT_ROUNDS_:
2537 Results.push_back(DAG.getConstant(1, Node->getValueType(0)));
2539 case ISD::EH_RETURN:
2543 case ISD::EH_SJLJ_LONGJMP:
2544 Results.push_back(Node->getOperand(0));
2546 case ISD::EH_SJLJ_SETJMP:
2547 Results.push_back(DAG.getConstant(0, MVT::i32));
2548 Results.push_back(Node->getOperand(0));
2550 case ISD::MEMBARRIER: {
2551 // If the target didn't lower this, lower it to '__sync_synchronize()' call
2552 TargetLowering::ArgListTy Args;
2553 std::pair<SDValue, SDValue> CallResult =
2554 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()),
2555 false, false, false, false, 0, CallingConv::C, false,
2556 /*isReturnValueUsed=*/true,
2557 DAG.getExternalSymbol("__sync_synchronize",
2558 TLI.getPointerTy()),
2560 Results.push_back(CallResult.second);
2563 // By default, atomic intrinsics are marked Legal and lowered. Targets
2564 // which don't support them directly, however, may want libcalls, in which
2565 // case they mark them Expand, and we get here.
2566 // FIXME: Unimplemented for now. Add libcalls.
2567 case ISD::ATOMIC_SWAP:
2568 case ISD::ATOMIC_LOAD_ADD:
2569 case ISD::ATOMIC_LOAD_SUB:
2570 case ISD::ATOMIC_LOAD_AND:
2571 case ISD::ATOMIC_LOAD_OR:
2572 case ISD::ATOMIC_LOAD_XOR:
2573 case ISD::ATOMIC_LOAD_NAND:
2574 case ISD::ATOMIC_LOAD_MIN:
2575 case ISD::ATOMIC_LOAD_MAX:
2576 case ISD::ATOMIC_LOAD_UMIN:
2577 case ISD::ATOMIC_LOAD_UMAX:
2578 case ISD::ATOMIC_CMP_SWAP: {
2579 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node);
2580 Results.push_back(Tmp.first);
2581 Results.push_back(Tmp.second);
2584 case ISD::DYNAMIC_STACKALLOC:
2585 ExpandDYNAMIC_STACKALLOC(Node, Results);
2587 case ISD::MERGE_VALUES:
2588 for (unsigned i = 0; i < Node->getNumValues(); i++)
2589 Results.push_back(Node->getOperand(i));
2592 EVT VT = Node->getValueType(0);
2594 Results.push_back(DAG.getConstant(0, VT));
2596 assert(VT.isFloatingPoint() && "Unknown value type!");
2597 Results.push_back(DAG.getConstantFP(0, VT));
2602 // If this operation is not supported, lower it to 'abort()' call
2603 TargetLowering::ArgListTy Args;
2604 std::pair<SDValue, SDValue> CallResult =
2605 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()),
2606 false, false, false, false, 0, CallingConv::C, false,
2607 /*isReturnValueUsed=*/true,
2608 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
2610 Results.push_back(CallResult.second);
2614 case ISD::BIT_CONVERT:
2615 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
2616 Node->getValueType(0), dl);
2617 Results.push_back(Tmp1);
2619 case ISD::FP_EXTEND:
2620 Tmp1 = EmitStackConvert(Node->getOperand(0),
2621 Node->getOperand(0).getValueType(),
2622 Node->getValueType(0), dl);
2623 Results.push_back(Tmp1);
2625 case ISD::SIGN_EXTEND_INREG: {
2626 // NOTE: we could fall back on load/store here too for targets without
2627 // SAR. However, it is doubtful that any exist.
2628 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2629 EVT VT = Node->getValueType(0);
2630 EVT ShiftAmountTy = TLI.getShiftAmountTy();
2633 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
2634 ExtraVT.getScalarType().getSizeInBits();
2635 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy);
2636 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
2637 Node->getOperand(0), ShiftCst);
2638 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
2639 Results.push_back(Tmp1);
2642 case ISD::FP_ROUND_INREG: {
2643 // The only way we can lower this is to turn it into a TRUNCSTORE,
2644 // EXTLOAD pair, targetting a temporary location (a stack slot).
2646 // NOTE: there is a choice here between constantly creating new stack
2647 // slots and always reusing the same one. We currently always create
2648 // new ones, as reuse may inhibit scheduling.
2649 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2650 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
2651 Node->getValueType(0), dl);
2652 Results.push_back(Tmp1);
2655 case ISD::SINT_TO_FP:
2656 case ISD::UINT_TO_FP:
2657 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
2658 Node->getOperand(0), Node->getValueType(0), dl);
2659 Results.push_back(Tmp1);
2661 case ISD::FP_TO_UINT: {
2662 SDValue True, False;
2663 EVT VT = Node->getOperand(0).getValueType();
2664 EVT NVT = Node->getValueType(0);
2665 const uint64_t zero[] = {0, 0};
2666 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero));
2667 APInt x = APInt::getSignBit(NVT.getSizeInBits());
2668 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
2669 Tmp1 = DAG.getConstantFP(apf, VT);
2670 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
2671 Node->getOperand(0),
2673 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
2674 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
2675 DAG.getNode(ISD::FSUB, dl, VT,
2676 Node->getOperand(0), Tmp1));
2677 False = DAG.getNode(ISD::XOR, dl, NVT, False,
2678 DAG.getConstant(x, NVT));
2679 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False);
2680 Results.push_back(Tmp1);
2684 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2685 EVT VT = Node->getValueType(0);
2686 Tmp1 = Node->getOperand(0);
2687 Tmp2 = Node->getOperand(1);
2688 unsigned Align = Node->getConstantOperandVal(3);
2690 SDValue VAListLoad = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2,
2691 MachinePointerInfo(V), false, false, 0);
2692 SDValue VAList = VAListLoad;
2694 if (Align > TLI.getMinStackArgumentAlignment()) {
2695 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
2697 VAList = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
2698 DAG.getConstant(Align - 1,
2699 TLI.getPointerTy()));
2701 VAList = DAG.getNode(ISD::AND, dl, TLI.getPointerTy(), VAList,
2702 DAG.getConstant(-Align,
2703 TLI.getPointerTy()));
2706 // Increment the pointer, VAList, to the next vaarg
2707 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
2708 DAG.getConstant(TLI.getTargetData()->
2709 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())),
2710 TLI.getPointerTy()));
2711 // Store the incremented VAList to the legalized pointer
2712 Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2,
2713 MachinePointerInfo(V), false, false, 0);
2714 // Load the actual argument out of the pointer VAList
2715 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(),
2717 Results.push_back(Results[0].getValue(1));
2721 // This defaults to loading a pointer from the input and storing it to the
2722 // output, returning the chain.
2723 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
2724 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
2725 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0),
2726 Node->getOperand(2), MachinePointerInfo(VS),
2728 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1),
2729 MachinePointerInfo(VD), false, false, 0);
2730 Results.push_back(Tmp1);
2733 case ISD::EXTRACT_VECTOR_ELT:
2734 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
2735 // This must be an access of the only element. Return it.
2736 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0),
2737 Node->getOperand(0));
2739 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
2740 Results.push_back(Tmp1);
2742 case ISD::EXTRACT_SUBVECTOR:
2743 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
2745 case ISD::CONCAT_VECTORS: {
2746 Results.push_back(ExpandVectorBuildThroughStack(Node));
2749 case ISD::SCALAR_TO_VECTOR:
2750 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
2752 case ISD::INSERT_VECTOR_ELT:
2753 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
2754 Node->getOperand(1),
2755 Node->getOperand(2), dl));
2757 case ISD::VECTOR_SHUFFLE: {
2758 SmallVector<int, 8> Mask;
2759 cast<ShuffleVectorSDNode>(Node)->getMask(Mask);
2761 EVT VT = Node->getValueType(0);
2762 EVT EltVT = VT.getVectorElementType();
2763 if (getTypeAction(EltVT) == Promote)
2764 EltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
2765 unsigned NumElems = VT.getVectorNumElements();
2766 SmallVector<SDValue, 8> Ops;
2767 for (unsigned i = 0; i != NumElems; ++i) {
2769 Ops.push_back(DAG.getUNDEF(EltVT));
2772 unsigned Idx = Mask[i];
2774 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
2775 Node->getOperand(0),
2776 DAG.getIntPtrConstant(Idx)));
2778 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
2779 Node->getOperand(1),
2780 DAG.getIntPtrConstant(Idx - NumElems)));
2782 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
2783 Results.push_back(Tmp1);
2786 case ISD::EXTRACT_ELEMENT: {
2787 EVT OpTy = Node->getOperand(0).getValueType();
2788 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
2790 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
2791 DAG.getConstant(OpTy.getSizeInBits()/2,
2792 TLI.getShiftAmountTy()));
2793 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
2796 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
2797 Node->getOperand(0));
2799 Results.push_back(Tmp1);
2802 case ISD::STACKSAVE:
2803 // Expand to CopyFromReg if the target set
2804 // StackPointerRegisterToSaveRestore.
2805 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2806 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
2807 Node->getValueType(0)));
2808 Results.push_back(Results[0].getValue(1));
2810 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
2811 Results.push_back(Node->getOperand(0));
2814 case ISD::STACKRESTORE:
2815 // Expand to CopyToReg if the target set
2816 // StackPointerRegisterToSaveRestore.
2817 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2818 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
2819 Node->getOperand(1)));
2821 Results.push_back(Node->getOperand(0));
2824 case ISD::FCOPYSIGN:
2825 Results.push_back(ExpandFCOPYSIGN(Node));
2828 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2829 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2830 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
2831 Node->getOperand(0));
2832 Results.push_back(Tmp1);
2835 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2836 EVT VT = Node->getValueType(0);
2837 Tmp1 = Node->getOperand(0);
2838 Tmp2 = DAG.getConstantFP(0.0, VT);
2839 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
2840 Tmp1, Tmp2, ISD::SETUGT);
2841 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
2842 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3);
2843 Results.push_back(Tmp1);
2847 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
2848 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128));
2851 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
2852 RTLIB::SIN_F80, RTLIB::SIN_PPCF128));
2855 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
2856 RTLIB::COS_F80, RTLIB::COS_PPCF128));
2859 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
2860 RTLIB::LOG_F80, RTLIB::LOG_PPCF128));
2863 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
2864 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128));
2867 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
2868 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128));
2871 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
2872 RTLIB::EXP_F80, RTLIB::EXP_PPCF128));
2875 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
2876 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128));
2879 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
2880 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128));
2883 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
2884 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128));
2887 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
2888 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128));
2891 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
2892 RTLIB::RINT_F80, RTLIB::RINT_PPCF128));
2894 case ISD::FNEARBYINT:
2895 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
2896 RTLIB::NEARBYINT_F64,
2897 RTLIB::NEARBYINT_F80,
2898 RTLIB::NEARBYINT_PPCF128));
2901 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
2902 RTLIB::POWI_F80, RTLIB::POWI_PPCF128));
2905 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
2906 RTLIB::POW_F80, RTLIB::POW_PPCF128));
2909 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
2910 RTLIB::DIV_F80, RTLIB::DIV_PPCF128));
2913 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
2914 RTLIB::REM_F80, RTLIB::REM_PPCF128));
2916 case ISD::FP16_TO_FP32:
2917 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
2919 case ISD::FP32_TO_FP16:
2920 Results.push_back(ExpandLibCall(RTLIB::FPROUND_F32_F16, Node, false));
2922 case ISD::ConstantFP: {
2923 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
2924 // Check to see if this FP immediate is already legal.
2925 // If this is a legal constant, turn it into a TargetConstantFP node.
2926 if (TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
2927 Results.push_back(SDValue(Node, 0));
2929 Results.push_back(ExpandConstantFP(CFP, true, DAG, TLI));
2932 case ISD::EHSELECTION: {
2933 unsigned Reg = TLI.getExceptionSelectorRegister();
2934 assert(Reg && "Can't expand to unknown register!");
2935 Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg,
2936 Node->getValueType(0)));
2937 Results.push_back(Results[0].getValue(1));
2940 case ISD::EXCEPTIONADDR: {
2941 unsigned Reg = TLI.getExceptionAddressRegister();
2942 assert(Reg && "Can't expand to unknown register!");
2943 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg,
2944 Node->getValueType(0)));
2945 Results.push_back(Results[0].getValue(1));
2949 EVT VT = Node->getValueType(0);
2950 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
2951 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
2952 "Don't know how to expand this subtraction!");
2953 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
2954 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
2955 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT));
2956 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
2961 EVT VT = Node->getValueType(0);
2962 SDVTList VTs = DAG.getVTList(VT, VT);
2963 bool isSigned = Node->getOpcode() == ISD::SREM;
2964 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
2965 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2966 Tmp2 = Node->getOperand(0);
2967 Tmp3 = Node->getOperand(1);
2968 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) {
2969 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
2970 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
2972 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
2973 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
2974 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
2975 } else if (isSigned) {
2976 Tmp1 = ExpandIntLibCall(Node, true,
2978 RTLIB::SREM_I16, RTLIB::SREM_I32,
2979 RTLIB::SREM_I64, RTLIB::SREM_I128);
2981 Tmp1 = ExpandIntLibCall(Node, false,
2983 RTLIB::UREM_I16, RTLIB::UREM_I32,
2984 RTLIB::UREM_I64, RTLIB::UREM_I128);
2986 Results.push_back(Tmp1);
2991 bool isSigned = Node->getOpcode() == ISD::SDIV;
2992 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2993 EVT VT = Node->getValueType(0);
2994 SDVTList VTs = DAG.getVTList(VT, VT);
2995 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT))
2996 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
2997 Node->getOperand(1));
2999 Tmp1 = ExpandIntLibCall(Node, true,
3001 RTLIB::SDIV_I16, RTLIB::SDIV_I32,
3002 RTLIB::SDIV_I64, RTLIB::SDIV_I128);
3004 Tmp1 = ExpandIntLibCall(Node, false,
3006 RTLIB::UDIV_I16, RTLIB::UDIV_I32,
3007 RTLIB::UDIV_I64, RTLIB::UDIV_I128);
3008 Results.push_back(Tmp1);
3013 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
3015 EVT VT = Node->getValueType(0);
3016 SDVTList VTs = DAG.getVTList(VT, VT);
3017 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
3018 "If this wasn't legal, it shouldn't have been created!");
3019 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
3020 Node->getOperand(1));
3021 Results.push_back(Tmp1.getValue(1));
3025 EVT VT = Node->getValueType(0);
3026 SDVTList VTs = DAG.getVTList(VT, VT);
3027 // See if multiply or divide can be lowered using two-result operations.
3028 // We just need the low half of the multiply; try both the signed
3029 // and unsigned forms. If the target supports both SMUL_LOHI and
3030 // UMUL_LOHI, form a preference by checking which forms of plain
3031 // MULH it supports.
3032 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3033 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3034 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3035 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3036 unsigned OpToUse = 0;
3037 if (HasSMUL_LOHI && !HasMULHS) {
3038 OpToUse = ISD::SMUL_LOHI;
3039 } else if (HasUMUL_LOHI && !HasMULHU) {
3040 OpToUse = ISD::UMUL_LOHI;
3041 } else if (HasSMUL_LOHI) {
3042 OpToUse = ISD::SMUL_LOHI;
3043 } else if (HasUMUL_LOHI) {
3044 OpToUse = ISD::UMUL_LOHI;
3047 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
3048 Node->getOperand(1)));
3051 Tmp1 = ExpandIntLibCall(Node, false,
3053 RTLIB::MUL_I16, RTLIB::MUL_I32,
3054 RTLIB::MUL_I64, RTLIB::MUL_I128);
3055 Results.push_back(Tmp1);
3060 SDValue LHS = Node->getOperand(0);
3061 SDValue RHS = Node->getOperand(1);
3062 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3063 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3065 Results.push_back(Sum);
3066 EVT OType = Node->getValueType(1);
3068 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
3070 // LHSSign -> LHS >= 0
3071 // RHSSign -> RHS >= 0
3072 // SumSign -> Sum >= 0
3075 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3077 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3079 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3080 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3081 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
3082 Node->getOpcode() == ISD::SADDO ?
3083 ISD::SETEQ : ISD::SETNE);
3085 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3086 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3088 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3089 Results.push_back(Cmp);
3094 SDValue LHS = Node->getOperand(0);
3095 SDValue RHS = Node->getOperand(1);
3096 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
3097 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3099 Results.push_back(Sum);
3100 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS,
3101 Node->getOpcode () == ISD::UADDO ?
3102 ISD::SETULT : ISD::SETUGT));
3107 EVT VT = Node->getValueType(0);
3108 SDValue LHS = Node->getOperand(0);
3109 SDValue RHS = Node->getOperand(1);
3112 static const unsigned Ops[2][3] =
3113 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
3114 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
3115 bool isSigned = Node->getOpcode() == ISD::SMULO;
3116 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3117 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3118 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3119 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3120 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3122 TopHalf = BottomHalf.getValue(1);
3124 // FIXME: We should be able to fall back to a libcall with an illegal
3125 // type in some cases.
3126 // Also, we can fall back to a division in some cases, but that's a big
3127 // performance hit in the general case.
3128 assert(TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(),
3129 VT.getSizeInBits() * 2)) &&
3130 "Don't know how to expand this operation yet!");
3131 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
3132 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
3133 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
3134 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
3135 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3136 DAG.getIntPtrConstant(0));
3137 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3138 DAG.getIntPtrConstant(1));
3141 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1, TLI.getShiftAmountTy());
3142 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3143 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1,
3146 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf,
3147 DAG.getConstant(0, VT), ISD::SETNE);
3149 Results.push_back(BottomHalf);
3150 Results.push_back(TopHalf);
3153 case ISD::BUILD_PAIR: {
3154 EVT PairTy = Node->getValueType(0);
3155 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3156 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3157 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
3158 DAG.getConstant(PairTy.getSizeInBits()/2,
3159 TLI.getShiftAmountTy()));
3160 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3164 Tmp1 = Node->getOperand(0);
3165 Tmp2 = Node->getOperand(1);
3166 Tmp3 = Node->getOperand(2);
3167 if (Tmp1.getOpcode() == ISD::SETCC) {
3168 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3170 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3172 Tmp1 = DAG.getSelectCC(dl, Tmp1,
3173 DAG.getConstant(0, Tmp1.getValueType()),
3174 Tmp2, Tmp3, ISD::SETNE);
3176 Results.push_back(Tmp1);
3179 SDValue Chain = Node->getOperand(0);
3180 SDValue Table = Node->getOperand(1);
3181 SDValue Index = Node->getOperand(2);
3183 EVT PTy = TLI.getPointerTy();
3185 const TargetData &TD = *TLI.getTargetData();
3186 unsigned EntrySize =
3187 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
3189 Index = DAG.getNode(ISD::MUL, dl, PTy,
3190 Index, DAG.getConstant(EntrySize, PTy));
3191 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
3193 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
3194 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, PTy, dl, Chain, Addr,
3195 MachinePointerInfo::getJumpTable(), MemVT,
3198 if (TM.getRelocationModel() == Reloc::PIC_) {
3199 // For PIC, the sequence is:
3200 // BRIND(load(Jumptable + index) + RelocBase)
3201 // RelocBase can be JumpTable, GOT or some sort of global base.
3202 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3203 TLI.getPICJumpTableRelocBase(Table, DAG));
3205 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
3206 Results.push_back(Tmp1);
3210 // Expand brcond's setcc into its constituent parts and create a BR_CC
3212 Tmp1 = Node->getOperand(0);
3213 Tmp2 = Node->getOperand(1);
3214 if (Tmp2.getOpcode() == ISD::SETCC) {
3215 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3216 Tmp1, Tmp2.getOperand(2),
3217 Tmp2.getOperand(0), Tmp2.getOperand(1),
3218 Node->getOperand(2));
3220 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3221 DAG.getCondCode(ISD::SETNE), Tmp2,
3222 DAG.getConstant(0, Tmp2.getValueType()),
3223 Node->getOperand(2));
3225 Results.push_back(Tmp1);
3228 Tmp1 = Node->getOperand(0);
3229 Tmp2 = Node->getOperand(1);
3230 Tmp3 = Node->getOperand(2);
3231 LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl);
3233 // If we expanded the SETCC into an AND/OR, return the new node
3234 if (Tmp2.getNode() == 0) {
3235 Results.push_back(Tmp1);
3239 // Otherwise, SETCC for the given comparison type must be completely
3240 // illegal; expand it into a SELECT_CC.
3241 EVT VT = Node->getValueType(0);
3242 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3243 DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3);
3244 Results.push_back(Tmp1);
3247 case ISD::SELECT_CC: {
3248 Tmp1 = Node->getOperand(0); // LHS
3249 Tmp2 = Node->getOperand(1); // RHS
3250 Tmp3 = Node->getOperand(2); // True
3251 Tmp4 = Node->getOperand(3); // False
3252 SDValue CC = Node->getOperand(4);
3254 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()),
3255 Tmp1, Tmp2, CC, dl);
3257 assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!");
3258 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3259 CC = DAG.getCondCode(ISD::SETNE);
3260 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2,
3262 Results.push_back(Tmp1);
3266 Tmp1 = Node->getOperand(0); // Chain
3267 Tmp2 = Node->getOperand(2); // LHS
3268 Tmp3 = Node->getOperand(3); // RHS
3269 Tmp4 = Node->getOperand(1); // CC
3271 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()),
3272 Tmp2, Tmp3, Tmp4, dl);
3273 LastCALLSEQ_END = DAG.getEntryNode();
3275 assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!");
3276 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
3277 Tmp4 = DAG.getCondCode(ISD::SETNE);
3278 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2,
3279 Tmp3, Node->getOperand(4));
3280 Results.push_back(Tmp1);
3283 case ISD::GLOBAL_OFFSET_TABLE:
3284 case ISD::GlobalAddress:
3285 case ISD::GlobalTLSAddress:
3286 case ISD::ExternalSymbol:
3287 case ISD::ConstantPool:
3288 case ISD::JumpTable:
3289 case ISD::INTRINSIC_W_CHAIN:
3290 case ISD::INTRINSIC_WO_CHAIN:
3291 case ISD::INTRINSIC_VOID:
3292 // FIXME: Custom lowering for these operations shouldn't return null!
3293 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
3294 Results.push_back(SDValue(Node, i));
3298 void SelectionDAGLegalize::PromoteNode(SDNode *Node,
3299 SmallVectorImpl<SDValue> &Results) {
3300 EVT OVT = Node->getValueType(0);
3301 if (Node->getOpcode() == ISD::UINT_TO_FP ||
3302 Node->getOpcode() == ISD::SINT_TO_FP ||
3303 Node->getOpcode() == ISD::SETCC) {
3304 OVT = Node->getOperand(0).getValueType();
3306 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3307 DebugLoc dl = Node->getDebugLoc();
3308 SDValue Tmp1, Tmp2, Tmp3;
3309 switch (Node->getOpcode()) {
3313 // Zero extend the argument.
3314 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3315 // Perform the larger operation.
3316 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
3317 if (Node->getOpcode() == ISD::CTTZ) {
3318 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3319 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
3320 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
3322 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
3323 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3324 } else if (Node->getOpcode() == ISD::CTLZ) {
3325 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3326 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
3327 DAG.getConstant(NVT.getSizeInBits() -
3328 OVT.getSizeInBits(), NVT));
3330 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
3333 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3334 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3335 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
3336 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
3337 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3338 Results.push_back(Tmp1);
3341 case ISD::FP_TO_UINT:
3342 case ISD::FP_TO_SINT:
3343 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
3344 Node->getOpcode() == ISD::FP_TO_SINT, dl);
3345 Results.push_back(Tmp1);
3347 case ISD::UINT_TO_FP:
3348 case ISD::SINT_TO_FP:
3349 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
3350 Node->getOpcode() == ISD::SINT_TO_FP, dl);
3351 Results.push_back(Tmp1);
3356 unsigned ExtOp, TruncOp;
3357 if (OVT.isVector()) {
3358 ExtOp = ISD::BIT_CONVERT;
3359 TruncOp = ISD::BIT_CONVERT;
3361 assert(OVT.isInteger() && "Cannot promote logic operation");
3362 ExtOp = ISD::ANY_EXTEND;
3363 TruncOp = ISD::TRUNCATE;
3365 // Promote each of the values to the new type.
3366 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3367 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3368 // Perform the larger operation, then convert back
3369 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3370 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
3374 unsigned ExtOp, TruncOp;
3375 if (Node->getValueType(0).isVector()) {
3376 ExtOp = ISD::BIT_CONVERT;
3377 TruncOp = ISD::BIT_CONVERT;
3378 } else if (Node->getValueType(0).isInteger()) {
3379 ExtOp = ISD::ANY_EXTEND;
3380 TruncOp = ISD::TRUNCATE;
3382 ExtOp = ISD::FP_EXTEND;
3383 TruncOp = ISD::FP_ROUND;
3385 Tmp1 = Node->getOperand(0);
3386 // Promote each of the values to the new type.
3387 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3388 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
3389 // Perform the larger operation, then round down.
3390 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3);
3391 if (TruncOp != ISD::FP_ROUND)
3392 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
3394 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
3395 DAG.getIntPtrConstant(0));
3396 Results.push_back(Tmp1);
3399 case ISD::VECTOR_SHUFFLE: {
3400 SmallVector<int, 8> Mask;
3401 cast<ShuffleVectorSDNode>(Node)->getMask(Mask);
3403 // Cast the two input vectors.
3404 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
3405 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(1));
3407 // Convert the shuffle mask to the right # elements.
3408 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
3409 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Tmp1);
3410 Results.push_back(Tmp1);
3414 unsigned ExtOp = ISD::FP_EXTEND;
3415 if (NVT.isInteger()) {
3416 ISD::CondCode CCCode =
3417 cast<CondCodeSDNode>(Node->getOperand(2))->get();
3418 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3420 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3421 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3422 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3423 Tmp1, Tmp2, Node->getOperand(2)));
3429 // SelectionDAG::Legalize - This is the entry point for the file.
3431 void SelectionDAG::Legalize(CodeGenOpt::Level OptLevel) {
3432 /// run - This is the main entry point to this class.
3434 SelectionDAGLegalize(*this, OptLevel).LegalizeDAG();