1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/CodeGen/PseudoSourceValue.h"
20 #include "llvm/Target/TargetFrameInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/Target/TargetData.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/Target/TargetSubtarget.h"
26 #include "llvm/CallingConv.h"
27 #include "llvm/Constants.h"
28 #include "llvm/DerivedTypes.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Compiler.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/ADT/DenseMap.h"
33 #include "llvm/ADT/SmallVector.h"
34 #include "llvm/ADT/SmallPtrSet.h"
40 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
41 cl::desc("Pop up a window to show dags before legalize"));
43 static const bool ViewLegalizeDAGs = 0;
46 //===----------------------------------------------------------------------===//
47 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
48 /// hacks on it until the target machine can handle it. This involves
49 /// eliminating value sizes the machine cannot handle (promoting small sizes to
50 /// large sizes or splitting up large values into small values) as well as
51 /// eliminating operations the machine cannot handle.
53 /// This code also does a small amount of optimization and recognition of idioms
54 /// as part of its processing. For example, if a target does not support a
55 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
56 /// will attempt merge setcc and brc instructions into brcc's.
59 class VISIBILITY_HIDDEN SelectionDAGLegalize {
63 // Libcall insertion helpers.
65 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
66 /// legalized. We use this to ensure that calls are properly serialized
67 /// against each other, including inserted libcalls.
68 SDOperand LastCALLSEQ_END;
70 /// IsLegalizingCall - This member is used *only* for purposes of providing
71 /// helpful assertions that a libcall isn't created while another call is
72 /// being legalized (which could lead to non-serialized call sequences).
73 bool IsLegalizingCall;
76 Legal, // The target natively supports this operation.
77 Promote, // This operation should be executed in a larger type.
78 Expand // Try to expand this to other ops, otherwise use a libcall.
81 /// ValueTypeActions - This is a bitvector that contains two bits for each
82 /// value type, where the two bits correspond to the LegalizeAction enum.
83 /// This can be queried with "getTypeAction(VT)".
84 TargetLowering::ValueTypeActionImpl ValueTypeActions;
86 /// LegalizedNodes - For nodes that are of legal width, and that have more
87 /// than one use, this map indicates what regularized operand to use. This
88 /// allows us to avoid legalizing the same thing more than once.
89 DenseMap<SDOperand, SDOperand> LegalizedNodes;
91 /// PromotedNodes - For nodes that are below legal width, and that have more
92 /// than one use, this map indicates what promoted value to use. This allows
93 /// us to avoid promoting the same thing more than once.
94 DenseMap<SDOperand, SDOperand> PromotedNodes;
96 /// ExpandedNodes - For nodes that need to be expanded this map indicates
97 /// which which operands are the expanded version of the input. This allows
98 /// us to avoid expanding the same node more than once.
99 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
101 /// SplitNodes - For vector nodes that need to be split, this map indicates
102 /// which which operands are the split version of the input. This allows us
103 /// to avoid splitting the same node more than once.
104 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
106 /// ScalarizedNodes - For nodes that need to be converted from vector types to
107 /// scalar types, this contains the mapping of ones we have already
108 /// processed to the result.
109 std::map<SDOperand, SDOperand> ScalarizedNodes;
111 void AddLegalizedOperand(SDOperand From, SDOperand To) {
112 LegalizedNodes.insert(std::make_pair(From, To));
113 // If someone requests legalization of the new node, return itself.
115 LegalizedNodes.insert(std::make_pair(To, To));
117 void AddPromotedOperand(SDOperand From, SDOperand To) {
118 bool isNew = PromotedNodes.insert(std::make_pair(From, To));
119 assert(isNew && "Got into the map somehow?");
120 // If someone requests legalization of the new node, return itself.
121 LegalizedNodes.insert(std::make_pair(To, To));
126 SelectionDAGLegalize(SelectionDAG &DAG);
128 /// getTypeAction - Return how we should legalize values of this type, either
129 /// it is already legal or we need to expand it into multiple registers of
130 /// smaller integer type, or we need to promote it to a larger type.
131 LegalizeAction getTypeAction(MVT::ValueType VT) const {
132 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
135 /// isTypeLegal - Return true if this type is legal on this target.
137 bool isTypeLegal(MVT::ValueType VT) const {
138 return getTypeAction(VT) == Legal;
144 /// HandleOp - Legalize, Promote, or Expand the specified operand as
145 /// appropriate for its type.
146 void HandleOp(SDOperand Op);
148 /// LegalizeOp - We know that the specified value has a legal type.
149 /// Recursively ensure that the operands have legal types, then return the
151 SDOperand LegalizeOp(SDOperand O);
153 /// UnrollVectorOp - We know that the given vector has a legal type, however
154 /// the operation it performs is not legal and is an operation that we have
155 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
156 /// operating on each element individually.
157 SDOperand UnrollVectorOp(SDOperand O);
159 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
160 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
161 /// is necessary to spill the vector being inserted into to memory, perform
162 /// the insert there, and then read the result back.
163 SDOperand PerformInsertVectorEltInMemory(SDOperand Vec, SDOperand Val,
166 /// PromoteOp - Given an operation that produces a value in an invalid type,
167 /// promote it to compute the value into a larger type. The produced value
168 /// will have the correct bits for the low portion of the register, but no
169 /// guarantee is made about the top bits: it may be zero, sign-extended, or
171 SDOperand PromoteOp(SDOperand O);
173 /// ExpandOp - Expand the specified SDOperand into its two component pieces
174 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
175 /// the LegalizeNodes map is filled in for any results that are not expanded,
176 /// the ExpandedNodes map is filled in for any results that are expanded, and
177 /// the Lo/Hi values are returned. This applies to integer types and Vector
179 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
181 /// SplitVectorOp - Given an operand of vector type, break it down into
182 /// two smaller values.
183 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
185 /// ScalarizeVectorOp - Given an operand of single-element vector type
186 /// (e.g. v1f32), convert it into the equivalent operation that returns a
187 /// scalar (e.g. f32) value.
188 SDOperand ScalarizeVectorOp(SDOperand O);
190 /// isShuffleLegal - Return true if a vector shuffle is legal with the
191 /// specified mask and type. Targets can specify exactly which masks they
192 /// support and the code generator is tasked with not creating illegal masks.
194 /// Note that this will also return true for shuffles that are promoted to a
197 /// If this is a legal shuffle, this method returns the (possibly promoted)
198 /// build_vector Mask. If it's not a legal shuffle, it returns null.
199 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
201 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
202 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
204 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
206 SDOperand ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned,
208 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
211 SDOperand EmitStackConvert(SDOperand SrcOp, MVT::ValueType SlotVT,
212 MVT::ValueType DestVT);
213 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
214 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
215 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
217 MVT::ValueType DestVT);
218 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
220 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
223 SDOperand ExpandBSWAP(SDOperand Op);
224 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
225 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
226 SDOperand &Lo, SDOperand &Hi);
227 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
228 SDOperand &Lo, SDOperand &Hi);
230 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op);
231 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
235 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
236 /// specified mask and type. Targets can specify exactly which masks they
237 /// support and the code generator is tasked with not creating illegal masks.
239 /// Note that this will also return true for shuffles that are promoted to a
241 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
242 SDOperand Mask) const {
243 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
245 case TargetLowering::Legal:
246 case TargetLowering::Custom:
248 case TargetLowering::Promote: {
249 // If this is promoted to a different type, convert the shuffle mask and
250 // ask if it is legal in the promoted type!
251 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
253 // If we changed # elements, change the shuffle mask.
254 unsigned NumEltsGrowth =
255 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
256 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
257 if (NumEltsGrowth > 1) {
258 // Renumber the elements.
259 SmallVector<SDOperand, 8> Ops;
260 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
261 SDOperand InOp = Mask.getOperand(i);
262 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
263 if (InOp.getOpcode() == ISD::UNDEF)
264 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
266 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
267 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
271 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
277 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
280 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
281 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
282 ValueTypeActions(TLI.getValueTypeActions()) {
283 assert(MVT::LAST_VALUETYPE <= 32 &&
284 "Too many value types for ValueTypeActions to hold!");
287 /// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order
288 /// contains all of a nodes operands before it contains the node.
289 static void ComputeTopDownOrdering(SelectionDAG &DAG,
290 SmallVector<SDNode*, 64> &Order) {
292 DenseMap<SDNode*, unsigned> Visited;
293 std::vector<SDNode*> Worklist;
294 Worklist.reserve(128);
296 // Compute ordering from all of the leaves in the graphs, those (like the
297 // entry node) that have no operands.
298 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
299 E = DAG.allnodes_end(); I != E; ++I) {
300 if (I->getNumOperands() == 0) {
302 Worklist.push_back(I);
306 while (!Worklist.empty()) {
307 SDNode *N = Worklist.back();
310 if (++Visited[N] != N->getNumOperands())
311 continue; // Haven't visited all operands yet
315 // Now that we have N in, add anything that uses it if all of their operands
317 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
319 Worklist.push_back(UI->getUser());
322 assert(Order.size() == Visited.size() &&
324 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
325 "Error: DAG is cyclic!");
329 void SelectionDAGLegalize::LegalizeDAG() {
330 LastCALLSEQ_END = DAG.getEntryNode();
331 IsLegalizingCall = false;
333 // The legalize process is inherently a bottom-up recursive process (users
334 // legalize their uses before themselves). Given infinite stack space, we
335 // could just start legalizing on the root and traverse the whole graph. In
336 // practice however, this causes us to run out of stack space on large basic
337 // blocks. To avoid this problem, compute an ordering of the nodes where each
338 // node is only legalized after all of its operands are legalized.
339 SmallVector<SDNode*, 64> Order;
340 ComputeTopDownOrdering(DAG, Order);
342 for (unsigned i = 0, e = Order.size(); i != e; ++i)
343 HandleOp(SDOperand(Order[i], 0));
345 // Finally, it's possible the root changed. Get the new root.
346 SDOperand OldRoot = DAG.getRoot();
347 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
348 DAG.setRoot(LegalizedNodes[OldRoot]);
350 ExpandedNodes.clear();
351 LegalizedNodes.clear();
352 PromotedNodes.clear();
354 ScalarizedNodes.clear();
356 // Remove dead nodes now.
357 DAG.RemoveDeadNodes();
361 /// FindCallEndFromCallStart - Given a chained node that is part of a call
362 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
363 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
364 if (Node->getOpcode() == ISD::CALLSEQ_END)
366 if (Node->use_empty())
367 return 0; // No CallSeqEnd
369 // The chain is usually at the end.
370 SDOperand TheChain(Node, Node->getNumValues()-1);
371 if (TheChain.getValueType() != MVT::Other) {
372 // Sometimes it's at the beginning.
373 TheChain = SDOperand(Node, 0);
374 if (TheChain.getValueType() != MVT::Other) {
375 // Otherwise, hunt for it.
376 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
377 if (Node->getValueType(i) == MVT::Other) {
378 TheChain = SDOperand(Node, i);
382 // Otherwise, we walked into a node without a chain.
383 if (TheChain.getValueType() != MVT::Other)
388 for (SDNode::use_iterator UI = Node->use_begin(),
389 E = Node->use_end(); UI != E; ++UI) {
391 // Make sure to only follow users of our token chain.
392 SDNode *User = UI->getUser();
393 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
394 if (User->getOperand(i) == TheChain)
395 if (SDNode *Result = FindCallEndFromCallStart(User))
401 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
402 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
403 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
404 assert(Node && "Didn't find callseq_start for a call??");
405 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
407 assert(Node->getOperand(0).getValueType() == MVT::Other &&
408 "Node doesn't have a token chain argument!");
409 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
412 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
413 /// see if any uses can reach Dest. If no dest operands can get to dest,
414 /// legalize them, legalize ourself, and return false, otherwise, return true.
416 /// Keep track of the nodes we fine that actually do lead to Dest in
417 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
419 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
420 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
421 if (N == Dest) return true; // N certainly leads to Dest :)
423 // If we've already processed this node and it does lead to Dest, there is no
424 // need to reprocess it.
425 if (NodesLeadingTo.count(N)) return true;
427 // If the first result of this node has been already legalized, then it cannot
429 switch (getTypeAction(N->getValueType(0))) {
431 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
434 if (PromotedNodes.count(SDOperand(N, 0))) return false;
437 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
441 // Okay, this node has not already been legalized. Check and legalize all
442 // operands. If none lead to Dest, then we can legalize this node.
443 bool OperandsLeadToDest = false;
444 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
445 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
446 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
448 if (OperandsLeadToDest) {
449 NodesLeadingTo.insert(N);
453 // Okay, this node looks safe, legalize it and return false.
454 HandleOp(SDOperand(N, 0));
458 /// HandleOp - Legalize, Promote, or Expand the specified operand as
459 /// appropriate for its type.
460 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
461 MVT::ValueType VT = Op.getValueType();
462 switch (getTypeAction(VT)) {
463 default: assert(0 && "Bad type action!");
464 case Legal: (void)LegalizeOp(Op); break;
465 case Promote: (void)PromoteOp(Op); break;
467 if (!MVT::isVector(VT)) {
468 // If this is an illegal scalar, expand it into its two component
471 if (Op.getOpcode() == ISD::TargetConstant)
472 break; // Allow illegal target nodes.
474 } else if (MVT::getVectorNumElements(VT) == 1) {
475 // If this is an illegal single element vector, convert it to a
477 (void)ScalarizeVectorOp(Op);
479 // Otherwise, this is an illegal multiple element vector.
480 // Split it in half and legalize both parts.
482 SplitVectorOp(Op, X, Y);
488 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
489 /// a load from the constant pool.
490 static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
491 SelectionDAG &DAG, TargetLowering &TLI) {
494 // If a FP immediate is precise when represented as a float and if the
495 // target can do an extending load from float to double, we put it into
496 // the constant pool as a float, even if it's is statically typed as a
497 // double. This shrinks FP constants and canonicalizes them for targets where
498 // an FP extending load is the same cost as a normal load (such as on the x87
499 // fp stack or PPC FP unit).
500 MVT::ValueType VT = CFP->getValueType(0);
501 ConstantFP *LLVMC = ConstantFP::get(CFP->getValueAPF());
503 if (VT!=MVT::f64 && VT!=MVT::f32)
504 assert(0 && "Invalid type expansion");
505 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt(),
506 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
509 MVT::ValueType OrigVT = VT;
510 MVT::ValueType SVT = VT;
511 while (SVT != MVT::f32) {
512 SVT = (unsigned)SVT - 1;
513 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
514 // Only do this if the target has a native EXTLOAD instruction from
516 TLI.isLoadXLegal(ISD::EXTLOAD, SVT) &&
517 TLI.ShouldShrinkFPConstant(OrigVT)) {
518 const Type *SType = MVT::getTypeForValueType(SVT);
519 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
525 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
527 return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, DAG.getEntryNode(),
528 CPIdx, PseudoSourceValue::getConstantPool(),
530 return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx,
531 PseudoSourceValue::getConstantPool(), 0);
535 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
538 SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT,
539 SelectionDAG &DAG, TargetLowering &TLI) {
540 MVT::ValueType VT = Node->getValueType(0);
541 MVT::ValueType SrcVT = Node->getOperand(1).getValueType();
542 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
543 "fcopysign expansion only supported for f32 and f64");
544 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
546 // First get the sign bit of second operand.
547 SDOperand Mask1 = (SrcVT == MVT::f64)
548 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
549 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
550 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
551 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
552 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
553 // Shift right or sign-extend it if the two operands have different types.
554 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT);
556 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
557 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
558 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
559 } else if (SizeDiff < 0)
560 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit);
562 // Clear the sign bit of first operand.
563 SDOperand Mask2 = (VT == MVT::f64)
564 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
565 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
566 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
567 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
568 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
570 // Or the value with the sign bit.
571 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
575 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
577 SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
578 TargetLowering &TLI) {
579 SDOperand Chain = ST->getChain();
580 SDOperand Ptr = ST->getBasePtr();
581 SDOperand Val = ST->getValue();
582 MVT::ValueType VT = Val.getValueType();
583 int Alignment = ST->getAlignment();
584 int SVOffset = ST->getSrcValueOffset();
585 if (MVT::isFloatingPoint(ST->getMemoryVT()) ||
586 MVT::isVector(ST->getMemoryVT())) {
587 // Expand to a bitconvert of the value to the integer type of the
588 // same size, then a (misaligned) int store.
589 MVT::ValueType intVT;
590 if (MVT::is128BitVector(VT) || VT == MVT::ppcf128 || VT == MVT::f128)
592 else if (MVT::is64BitVector(VT) || VT==MVT::f64)
594 else if (VT==MVT::f32)
597 assert(0 && "Unaligned store of unsupported type");
599 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val);
600 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(),
601 SVOffset, ST->isVolatile(), Alignment);
603 assert(MVT::isInteger(ST->getMemoryVT()) &&
604 !MVT::isVector(ST->getMemoryVT()) &&
605 "Unaligned store of unknown type.");
606 // Get the half-size VT
607 MVT::ValueType NewStoredVT = ST->getMemoryVT() - 1;
608 int NumBits = MVT::getSizeInBits(NewStoredVT);
609 int IncrementSize = NumBits / 8;
611 // Divide the stored value in two parts.
612 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
614 SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
616 // Store the two parts
617 SDOperand Store1, Store2;
618 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr,
619 ST->getSrcValue(), SVOffset, NewStoredVT,
620 ST->isVolatile(), Alignment);
621 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
622 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
623 Alignment = MinAlign(Alignment, IncrementSize);
624 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr,
625 ST->getSrcValue(), SVOffset + IncrementSize,
626 NewStoredVT, ST->isVolatile(), Alignment);
628 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2);
631 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
633 SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
634 TargetLowering &TLI) {
635 int SVOffset = LD->getSrcValueOffset();
636 SDOperand Chain = LD->getChain();
637 SDOperand Ptr = LD->getBasePtr();
638 MVT::ValueType VT = LD->getValueType(0);
639 MVT::ValueType LoadedVT = LD->getMemoryVT();
640 if (MVT::isFloatingPoint(VT) || MVT::isVector(VT)) {
641 // Expand to a (misaligned) integer load of the same size,
642 // then bitconvert to floating point or vector.
643 MVT::ValueType intVT;
644 if (MVT::is128BitVector(LoadedVT) ||
645 LoadedVT == MVT::ppcf128 || LoadedVT == MVT::f128)
647 else if (MVT::is64BitVector(LoadedVT) || LoadedVT == MVT::f64)
649 else if (LoadedVT == MVT::f32)
652 assert(0 && "Unaligned load of unsupported type");
654 SDOperand newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(),
655 SVOffset, LD->isVolatile(),
657 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad);
658 if (MVT::isFloatingPoint(VT) && LoadedVT != VT)
659 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result);
661 SDOperand Ops[] = { Result, Chain };
662 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
665 assert(MVT::isInteger(LoadedVT) && !MVT::isVector(LoadedVT) &&
666 "Unaligned load of unsupported type.");
668 // Compute the new VT that is half the size of the old one. This is an
670 unsigned NumBits = MVT::getSizeInBits(LoadedVT);
671 MVT::ValueType NewLoadedVT;
672 NewLoadedVT = MVT::getIntegerType(NumBits/2);
675 unsigned Alignment = LD->getAlignment();
676 unsigned IncrementSize = NumBits / 8;
677 ISD::LoadExtType HiExtType = LD->getExtensionType();
679 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
680 if (HiExtType == ISD::NON_EXTLOAD)
681 HiExtType = ISD::ZEXTLOAD;
683 // Load the value in two parts
685 if (TLI.isLittleEndian()) {
686 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
687 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
688 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
689 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
690 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(),
691 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
692 MinAlign(Alignment, IncrementSize));
694 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset,
695 NewLoadedVT,LD->isVolatile(), Alignment);
696 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
697 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
698 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
699 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
700 MinAlign(Alignment, IncrementSize));
703 // aggregate the two parts
704 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
705 SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
706 Result = DAG.getNode(ISD::OR, VT, Result, Lo);
708 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
711 SDOperand Ops[] = { Result, TF };
712 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2);
715 /// UnrollVectorOp - We know that the given vector has a legal type, however
716 /// the operation it performs is not legal and is an operation that we have
717 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
718 /// operating on each element individually.
719 SDOperand SelectionDAGLegalize::UnrollVectorOp(SDOperand Op) {
720 MVT::ValueType VT = Op.getValueType();
721 assert(isTypeLegal(VT) &&
722 "Caller should expand or promote operands that are not legal!");
723 assert(Op.Val->getNumValues() == 1 &&
724 "Can't unroll a vector with multiple results!");
725 unsigned NE = MVT::getVectorNumElements(VT);
726 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
728 SmallVector<SDOperand, 8> Scalars;
729 SmallVector<SDOperand, 4> Operands(Op.getNumOperands());
730 for (unsigned i = 0; i != NE; ++i) {
731 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
732 SDOperand Operand = Op.getOperand(j);
733 MVT::ValueType OperandVT = Operand.getValueType();
734 if (MVT::isVector(OperandVT)) {
735 // A vector operand; extract a single element.
736 MVT::ValueType OperandEltVT = MVT::getVectorElementType(OperandVT);
737 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
740 DAG.getConstant(i, MVT::i32));
742 // A scalar operand; just use it as is.
743 Operands[j] = Operand;
746 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT,
747 &Operands[0], Operands.size()));
750 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size());
753 /// GetFPLibCall - Return the right libcall for the given floating point type.
754 static RTLIB::Libcall GetFPLibCall(MVT::ValueType VT,
755 RTLIB::Libcall Call_F32,
756 RTLIB::Libcall Call_F64,
757 RTLIB::Libcall Call_F80,
758 RTLIB::Libcall Call_PPCF128) {
760 VT == MVT::f32 ? Call_F32 :
761 VT == MVT::f64 ? Call_F64 :
762 VT == MVT::f80 ? Call_F80 :
763 VT == MVT::ppcf128 ? Call_PPCF128 :
764 RTLIB::UNKNOWN_LIBCALL;
767 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
768 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
769 /// is necessary to spill the vector being inserted into to memory, perform
770 /// the insert there, and then read the result back.
771 SDOperand SelectionDAGLegalize::
772 PerformInsertVectorEltInMemory(SDOperand Vec, SDOperand Val, SDOperand Idx) {
773 SDOperand Tmp1 = Vec;
774 SDOperand Tmp2 = Val;
775 SDOperand Tmp3 = Idx;
777 // If the target doesn't support this, we have to spill the input vector
778 // to a temporary stack slot, update the element, then reload it. This is
779 // badness. We could also load the value into a vector register (either
780 // with a "move to register" or "extload into register" instruction, then
781 // permute it into place, if the idx is a constant and if the idx is
782 // supported by the target.
783 MVT::ValueType VT = Tmp1.getValueType();
784 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
785 MVT::ValueType IdxVT = Tmp3.getValueType();
786 MVT::ValueType PtrVT = TLI.getPointerTy();
787 SDOperand StackPtr = DAG.CreateStackTemporary(VT);
789 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr.Val);
790 int SPFI = StackPtrFI->getIndex();
793 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr,
794 PseudoSourceValue::getFixedStack(),
797 // Truncate or zero extend offset to target pointer type.
798 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
799 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
800 // Add the offset to the index.
801 unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
802 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
803 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
804 // Store the scalar value.
805 Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2,
806 PseudoSourceValue::getFixedStack(), SPFI, EltVT);
807 // Load the updated vector.
808 return DAG.getLoad(VT, Ch, StackPtr, PseudoSourceValue::getFixedStack(),SPFI);
811 /// LegalizeOp - We know that the specified value has a legal type, and
812 /// that its operands are legal. Now ensure that the operation itself
813 /// is legal, recursively ensuring that the operands' operations remain
815 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
816 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
819 assert(isTypeLegal(Op.getValueType()) &&
820 "Caller should expand or promote operands that are not legal!");
821 SDNode *Node = Op.Val;
823 // If this operation defines any values that cannot be represented in a
824 // register on this target, make sure to expand or promote them.
825 if (Node->getNumValues() > 1) {
826 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
827 if (getTypeAction(Node->getValueType(i)) != Legal) {
828 HandleOp(Op.getValue(i));
829 assert(LegalizedNodes.count(Op) &&
830 "Handling didn't add legal operands!");
831 return LegalizedNodes[Op];
835 // Note that LegalizeOp may be reentered even from single-use nodes, which
836 // means that we always must cache transformed nodes.
837 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
838 if (I != LegalizedNodes.end()) return I->second;
840 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
841 SDOperand Result = Op;
842 bool isCustom = false;
844 switch (Node->getOpcode()) {
845 case ISD::FrameIndex:
846 case ISD::EntryToken:
848 case ISD::BasicBlock:
849 case ISD::TargetFrameIndex:
850 case ISD::TargetJumpTable:
851 case ISD::TargetConstant:
852 case ISD::TargetConstantFP:
853 case ISD::TargetConstantPool:
854 case ISD::TargetGlobalAddress:
855 case ISD::TargetGlobalTLSAddress:
856 case ISD::TargetExternalSymbol:
859 case ISD::MEMOPERAND:
863 // Primitives must all be legal.
864 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
865 "This must be legal!");
868 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
869 // If this is a target node, legalize it by legalizing the operands then
870 // passing it through.
871 SmallVector<SDOperand, 8> Ops;
872 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
873 Ops.push_back(LegalizeOp(Node->getOperand(i)));
875 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
877 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
878 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
879 return Result.getValue(Op.ResNo);
881 // Otherwise this is an unhandled builtin node. splat.
883 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
885 assert(0 && "Do not know how to legalize this operator!");
887 case ISD::GLOBAL_OFFSET_TABLE:
888 case ISD::GlobalAddress:
889 case ISD::GlobalTLSAddress:
890 case ISD::ExternalSymbol:
891 case ISD::ConstantPool:
892 case ISD::JumpTable: // Nothing to do.
893 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
894 default: assert(0 && "This action is not supported yet!");
895 case TargetLowering::Custom:
896 Tmp1 = TLI.LowerOperation(Op, DAG);
897 if (Tmp1.Val) Result = Tmp1;
898 // FALLTHROUGH if the target doesn't want to lower this op after all.
899 case TargetLowering::Legal:
904 case ISD::RETURNADDR:
905 // The only option for these nodes is to custom lower them. If the target
906 // does not custom lower them, then return zero.
907 Tmp1 = TLI.LowerOperation(Op, DAG);
911 Result = DAG.getConstant(0, TLI.getPointerTy());
913 case ISD::FRAME_TO_ARGS_OFFSET: {
914 MVT::ValueType VT = Node->getValueType(0);
915 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
916 default: assert(0 && "This action is not supported yet!");
917 case TargetLowering::Custom:
918 Result = TLI.LowerOperation(Op, DAG);
919 if (Result.Val) break;
921 case TargetLowering::Legal:
922 Result = DAG.getConstant(0, VT);
927 case ISD::EXCEPTIONADDR: {
928 Tmp1 = LegalizeOp(Node->getOperand(0));
929 MVT::ValueType VT = Node->getValueType(0);
930 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
931 default: assert(0 && "This action is not supported yet!");
932 case TargetLowering::Expand: {
933 unsigned Reg = TLI.getExceptionAddressRegister();
934 Result = DAG.getCopyFromReg(Tmp1, Reg, VT);
937 case TargetLowering::Custom:
938 Result = TLI.LowerOperation(Op, DAG);
939 if (Result.Val) break;
941 case TargetLowering::Legal: {
942 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 };
943 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
949 if (Result.Val->getNumValues() == 1) break;
951 assert(Result.Val->getNumValues() == 2 &&
952 "Cannot return more than two values!");
954 // Since we produced two values, make sure to remember that we
955 // legalized both of them.
956 Tmp1 = LegalizeOp(Result);
957 Tmp2 = LegalizeOp(Result.getValue(1));
958 AddLegalizedOperand(Op.getValue(0), Tmp1);
959 AddLegalizedOperand(Op.getValue(1), Tmp2);
960 return Op.ResNo ? Tmp2 : Tmp1;
961 case ISD::EHSELECTION: {
962 Tmp1 = LegalizeOp(Node->getOperand(0));
963 Tmp2 = LegalizeOp(Node->getOperand(1));
964 MVT::ValueType VT = Node->getValueType(0);
965 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
966 default: assert(0 && "This action is not supported yet!");
967 case TargetLowering::Expand: {
968 unsigned Reg = TLI.getExceptionSelectorRegister();
969 Result = DAG.getCopyFromReg(Tmp2, Reg, VT);
972 case TargetLowering::Custom:
973 Result = TLI.LowerOperation(Op, DAG);
974 if (Result.Val) break;
976 case TargetLowering::Legal: {
977 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 };
978 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
984 if (Result.Val->getNumValues() == 1) break;
986 assert(Result.Val->getNumValues() == 2 &&
987 "Cannot return more than two values!");
989 // Since we produced two values, make sure to remember that we
990 // legalized both of them.
991 Tmp1 = LegalizeOp(Result);
992 Tmp2 = LegalizeOp(Result.getValue(1));
993 AddLegalizedOperand(Op.getValue(0), Tmp1);
994 AddLegalizedOperand(Op.getValue(1), Tmp2);
995 return Op.ResNo ? Tmp2 : Tmp1;
996 case ISD::EH_RETURN: {
997 MVT::ValueType VT = Node->getValueType(0);
998 // The only "good" option for this node is to custom lower it.
999 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1000 default: assert(0 && "This action is not supported at all!");
1001 case TargetLowering::Custom:
1002 Result = TLI.LowerOperation(Op, DAG);
1003 if (Result.Val) break;
1005 case TargetLowering::Legal:
1006 // Target does not know, how to lower this, lower to noop
1007 Result = LegalizeOp(Node->getOperand(0));
1012 case ISD::AssertSext:
1013 case ISD::AssertZext:
1014 Tmp1 = LegalizeOp(Node->getOperand(0));
1015 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1017 case ISD::MERGE_VALUES:
1018 // Legalize eliminates MERGE_VALUES nodes.
1019 Result = Node->getOperand(Op.ResNo);
1021 case ISD::CopyFromReg:
1022 Tmp1 = LegalizeOp(Node->getOperand(0));
1023 Result = Op.getValue(0);
1024 if (Node->getNumValues() == 2) {
1025 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1027 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
1028 if (Node->getNumOperands() == 3) {
1029 Tmp2 = LegalizeOp(Node->getOperand(2));
1030 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1032 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1034 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
1036 // Since CopyFromReg produces two values, make sure to remember that we
1037 // legalized both of them.
1038 AddLegalizedOperand(Op.getValue(0), Result);
1039 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1040 return Result.getValue(Op.ResNo);
1042 MVT::ValueType VT = Op.getValueType();
1043 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
1044 default: assert(0 && "This action is not supported yet!");
1045 case TargetLowering::Expand:
1046 if (MVT::isInteger(VT))
1047 Result = DAG.getConstant(0, VT);
1048 else if (MVT::isFloatingPoint(VT))
1049 Result = DAG.getConstantFP(APFloat(APInt(MVT::getSizeInBits(VT), 0)),
1052 assert(0 && "Unknown value type!");
1054 case TargetLowering::Legal:
1060 case ISD::INTRINSIC_W_CHAIN:
1061 case ISD::INTRINSIC_WO_CHAIN:
1062 case ISD::INTRINSIC_VOID: {
1063 SmallVector<SDOperand, 8> Ops;
1064 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1065 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1066 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1068 // Allow the target to custom lower its intrinsics if it wants to.
1069 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
1070 TargetLowering::Custom) {
1071 Tmp3 = TLI.LowerOperation(Result, DAG);
1072 if (Tmp3.Val) Result = Tmp3;
1075 if (Result.Val->getNumValues() == 1) break;
1077 // Must have return value and chain result.
1078 assert(Result.Val->getNumValues() == 2 &&
1079 "Cannot return more than two values!");
1081 // Since loads produce two values, make sure to remember that we
1082 // legalized both of them.
1083 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1084 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1085 return Result.getValue(Op.ResNo);
1089 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
1090 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
1092 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
1093 case TargetLowering::Promote:
1094 default: assert(0 && "This action is not supported yet!");
1095 case TargetLowering::Expand: {
1096 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
1097 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
1098 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other);
1100 if (MMI && (useDEBUG_LOC || useLABEL)) {
1101 const std::string &FName =
1102 cast<StringSDNode>(Node->getOperand(3))->getValue();
1103 const std::string &DirName =
1104 cast<StringSDNode>(Node->getOperand(4))->getValue();
1105 unsigned SrcFile = MMI->RecordSource(DirName, FName);
1107 SmallVector<SDOperand, 8> Ops;
1108 Ops.push_back(Tmp1); // chain
1109 SDOperand LineOp = Node->getOperand(1);
1110 SDOperand ColOp = Node->getOperand(2);
1113 Ops.push_back(LineOp); // line #
1114 Ops.push_back(ColOp); // col #
1115 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
1116 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
1118 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
1119 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
1120 unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile);
1121 Ops.push_back(DAG.getConstant(ID, MVT::i32));
1122 Ops.push_back(DAG.getConstant(0, MVT::i32)); // a debug label
1123 Result = DAG.getNode(ISD::LABEL, MVT::Other, &Ops[0], Ops.size());
1126 Result = Tmp1; // chain
1130 case TargetLowering::Legal:
1131 if (Tmp1 != Node->getOperand(0) ||
1132 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
1133 SmallVector<SDOperand, 8> Ops;
1134 Ops.push_back(Tmp1);
1135 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
1136 Ops.push_back(Node->getOperand(1)); // line # must be legal.
1137 Ops.push_back(Node->getOperand(2)); // col # must be legal.
1139 // Otherwise promote them.
1140 Ops.push_back(PromoteOp(Node->getOperand(1)));
1141 Ops.push_back(PromoteOp(Node->getOperand(2)));
1143 Ops.push_back(Node->getOperand(3)); // filename must be legal.
1144 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
1145 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1152 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!");
1153 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) {
1154 default: assert(0 && "This action is not supported yet!");
1155 case TargetLowering::Legal:
1156 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1157 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1158 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable.
1159 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1161 case TargetLowering::Expand:
1162 Result = LegalizeOp(Node->getOperand(0));
1167 case ISD::DEBUG_LOC:
1168 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
1169 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
1170 default: assert(0 && "This action is not supported yet!");
1171 case TargetLowering::Legal:
1172 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1173 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1174 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1175 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1176 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1182 assert(Node->getNumOperands() == 3 && "Invalid LABEL node!");
1183 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) {
1184 default: assert(0 && "This action is not supported yet!");
1185 case TargetLowering::Legal:
1186 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1187 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
1188 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the "flavor" operand.
1189 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1191 case TargetLowering::Expand:
1192 Result = LegalizeOp(Node->getOperand(0));
1198 assert(Node->getNumOperands() == 4 && "Invalid Prefetch node!");
1199 switch (TLI.getOperationAction(ISD::PREFETCH, MVT::Other)) {
1200 default: assert(0 && "This action is not supported yet!");
1201 case TargetLowering::Legal:
1202 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1203 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1204 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the rw specifier.
1205 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize locality specifier.
1206 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1208 case TargetLowering::Expand:
1210 Result = LegalizeOp(Node->getOperand(0));
1215 case ISD::MEMBARRIER: {
1216 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!");
1217 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) {
1218 default: assert(0 && "This action is not supported yet!");
1219 case TargetLowering::Legal: {
1221 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1222 for (int x = 1; x < 6; ++x) {
1223 Ops[x] = Node->getOperand(x);
1224 if (!isTypeLegal(Ops[x].getValueType()))
1225 Ops[x] = PromoteOp(Ops[x]);
1227 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6);
1230 case TargetLowering::Expand:
1231 //There is no libgcc call for this op
1232 Result = Node->getOperand(0); // Noop
1238 case ISD::ATOMIC_LCS: {
1239 unsigned int num_operands = 4;
1240 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1242 for (unsigned int x = 0; x < num_operands; ++x)
1243 Ops[x] = LegalizeOp(Node->getOperand(x));
1244 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1246 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1247 default: assert(0 && "This action is not supported yet!");
1248 case TargetLowering::Custom:
1249 Result = TLI.LowerOperation(Result, DAG);
1251 case TargetLowering::Legal:
1254 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1255 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1256 return Result.getValue(Op.ResNo);
1258 case ISD::ATOMIC_LAS:
1259 case ISD::ATOMIC_LSS:
1260 case ISD::ATOMIC_LOAD_AND:
1261 case ISD::ATOMIC_LOAD_OR:
1262 case ISD::ATOMIC_LOAD_XOR:
1263 case ISD::ATOMIC_LOAD_MIN:
1264 case ISD::ATOMIC_LOAD_MAX:
1265 case ISD::ATOMIC_LOAD_UMIN:
1266 case ISD::ATOMIC_LOAD_UMAX:
1267 case ISD::ATOMIC_SWAP: {
1268 unsigned int num_operands = 3;
1269 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1271 for (unsigned int x = 0; x < num_operands; ++x)
1272 Ops[x] = LegalizeOp(Node->getOperand(x));
1273 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1275 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1276 default: assert(0 && "This action is not supported yet!");
1277 case TargetLowering::Custom:
1278 Result = TLI.LowerOperation(Result, DAG);
1280 case TargetLowering::Expand:
1281 Result = SDOperand(TLI.ExpandOperationResult(Op.Val, DAG),0);
1283 case TargetLowering::Legal:
1286 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1287 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1288 return Result.getValue(Op.ResNo);
1290 case ISD::Constant: {
1291 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1293 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1295 // We know we don't need to expand constants here, constants only have one
1296 // value and we check that it is fine above.
1298 if (opAction == TargetLowering::Custom) {
1299 Tmp1 = TLI.LowerOperation(Result, DAG);
1305 case ISD::ConstantFP: {
1306 // Spill FP immediates to the constant pool if the target cannot directly
1307 // codegen them. Targets often have some immediate values that can be
1308 // efficiently generated into an FP register without a load. We explicitly
1309 // leave these constants as ConstantFP nodes for the target to deal with.
1310 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1312 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1313 default: assert(0 && "This action is not supported yet!");
1314 case TargetLowering::Legal:
1316 case TargetLowering::Custom:
1317 Tmp3 = TLI.LowerOperation(Result, DAG);
1323 case TargetLowering::Expand: {
1324 // Check to see if this FP immediate is already legal.
1325 bool isLegal = false;
1326 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1327 E = TLI.legal_fpimm_end(); I != E; ++I) {
1328 if (CFP->isExactlyValue(*I)) {
1333 // If this is a legal constant, turn it into a TargetConstantFP node.
1336 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1341 case ISD::TokenFactor:
1342 if (Node->getNumOperands() == 2) {
1343 Tmp1 = LegalizeOp(Node->getOperand(0));
1344 Tmp2 = LegalizeOp(Node->getOperand(1));
1345 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1346 } else if (Node->getNumOperands() == 3) {
1347 Tmp1 = LegalizeOp(Node->getOperand(0));
1348 Tmp2 = LegalizeOp(Node->getOperand(1));
1349 Tmp3 = LegalizeOp(Node->getOperand(2));
1350 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1352 SmallVector<SDOperand, 8> Ops;
1353 // Legalize the operands.
1354 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1355 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1356 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1360 case ISD::FORMAL_ARGUMENTS:
1362 // The only option for this is to custom lower it.
1363 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1364 assert(Tmp3.Val && "Target didn't custom lower this node!");
1365 // A call within a calling sequence must be legalized to something
1366 // other than the normal CALLSEQ_END. Violating this gets Legalize
1367 // into an infinite loop.
1368 assert ((!IsLegalizingCall ||
1369 Node->getOpcode() != ISD::CALL ||
1370 Tmp3.Val->getOpcode() != ISD::CALLSEQ_END) &&
1371 "Nested CALLSEQ_START..CALLSEQ_END not supported.");
1373 // The number of incoming and outgoing values should match; unless the final
1374 // outgoing value is a flag.
1375 assert((Tmp3.Val->getNumValues() == Result.Val->getNumValues() ||
1376 (Tmp3.Val->getNumValues() == Result.Val->getNumValues() + 1 &&
1377 Tmp3.Val->getValueType(Tmp3.Val->getNumValues() - 1) ==
1379 "Lowering call/formal_arguments produced unexpected # results!");
1381 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1382 // remember that we legalized all of them, so it doesn't get relegalized.
1383 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
1384 if (Tmp3.Val->getValueType(i) == MVT::Flag)
1386 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1389 AddLegalizedOperand(SDOperand(Node, i), Tmp1);
1392 case ISD::EXTRACT_SUBREG: {
1393 Tmp1 = LegalizeOp(Node->getOperand(0));
1394 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1395 assert(idx && "Operand must be a constant");
1396 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1397 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1400 case ISD::INSERT_SUBREG: {
1401 Tmp1 = LegalizeOp(Node->getOperand(0));
1402 Tmp2 = LegalizeOp(Node->getOperand(1));
1403 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1404 assert(idx && "Operand must be a constant");
1405 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1406 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1409 case ISD::BUILD_VECTOR:
1410 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1411 default: assert(0 && "This action is not supported yet!");
1412 case TargetLowering::Custom:
1413 Tmp3 = TLI.LowerOperation(Result, DAG);
1419 case TargetLowering::Expand:
1420 Result = ExpandBUILD_VECTOR(Result.Val);
1424 case ISD::INSERT_VECTOR_ELT:
1425 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1426 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1428 // The type of the value to insert may not be legal, even though the vector
1429 // type is legal. Legalize/Promote accordingly. We do not handle Expand
1431 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1432 default: assert(0 && "Cannot expand insert element operand");
1433 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
1434 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
1436 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1438 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1439 Node->getValueType(0))) {
1440 default: assert(0 && "This action is not supported yet!");
1441 case TargetLowering::Legal:
1443 case TargetLowering::Custom:
1444 Tmp4 = TLI.LowerOperation(Result, DAG);
1450 case TargetLowering::Expand: {
1451 // If the insert index is a constant, codegen this as a scalar_to_vector,
1452 // then a shuffle that inserts it into the right position in the vector.
1453 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1454 // SCALAR_TO_VECTOR requires that the type of the value being inserted
1455 // match the element type of the vector being created.
1456 if (Tmp2.getValueType() ==
1457 MVT::getVectorElementType(Op.getValueType())) {
1458 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
1459 Tmp1.getValueType(), Tmp2);
1461 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
1462 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
1463 MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT);
1465 // We generate a shuffle of InVec and ScVec, so the shuffle mask
1466 // should be 0,1,2,3,4,5... with the appropriate element replaced with
1467 // elt 0 of the RHS.
1468 SmallVector<SDOperand, 8> ShufOps;
1469 for (unsigned i = 0; i != NumElts; ++i) {
1470 if (i != InsertPos->getValue())
1471 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1473 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1475 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1476 &ShufOps[0], ShufOps.size());
1478 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1479 Tmp1, ScVec, ShufMask);
1480 Result = LegalizeOp(Result);
1484 Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3);
1489 case ISD::SCALAR_TO_VECTOR:
1490 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1491 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1495 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1496 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1497 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1498 Node->getValueType(0))) {
1499 default: assert(0 && "This action is not supported yet!");
1500 case TargetLowering::Legal:
1502 case TargetLowering::Custom:
1503 Tmp3 = TLI.LowerOperation(Result, DAG);
1509 case TargetLowering::Expand:
1510 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1514 case ISD::VECTOR_SHUFFLE:
1515 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1516 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1517 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1519 // Allow targets to custom lower the SHUFFLEs they support.
1520 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1521 default: assert(0 && "Unknown operation action!");
1522 case TargetLowering::Legal:
1523 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1524 "vector shuffle should not be created if not legal!");
1526 case TargetLowering::Custom:
1527 Tmp3 = TLI.LowerOperation(Result, DAG);
1533 case TargetLowering::Expand: {
1534 MVT::ValueType VT = Node->getValueType(0);
1535 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
1536 MVT::ValueType PtrVT = TLI.getPointerTy();
1537 SDOperand Mask = Node->getOperand(2);
1538 unsigned NumElems = Mask.getNumOperands();
1539 SmallVector<SDOperand,8> Ops;
1540 for (unsigned i = 0; i != NumElems; ++i) {
1541 SDOperand Arg = Mask.getOperand(i);
1542 if (Arg.getOpcode() == ISD::UNDEF) {
1543 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1545 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1546 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
1548 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1549 DAG.getConstant(Idx, PtrVT)));
1551 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1552 DAG.getConstant(Idx - NumElems, PtrVT)));
1555 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1558 case TargetLowering::Promote: {
1559 // Change base type to a different vector type.
1560 MVT::ValueType OVT = Node->getValueType(0);
1561 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1563 // Cast the two input vectors.
1564 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1565 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1567 // Convert the shuffle mask to the right # elements.
1568 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1569 assert(Tmp3.Val && "Shuffle not legal?");
1570 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1571 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1577 case ISD::EXTRACT_VECTOR_ELT:
1578 Tmp1 = Node->getOperand(0);
1579 Tmp2 = LegalizeOp(Node->getOperand(1));
1580 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1581 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1584 case ISD::EXTRACT_SUBVECTOR:
1585 Tmp1 = Node->getOperand(0);
1586 Tmp2 = LegalizeOp(Node->getOperand(1));
1587 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1588 Result = ExpandEXTRACT_SUBVECTOR(Result);
1591 case ISD::CALLSEQ_START: {
1592 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1594 // Recursively Legalize all of the inputs of the call end that do not lead
1595 // to this call start. This ensures that any libcalls that need be inserted
1596 // are inserted *before* the CALLSEQ_START.
1597 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1598 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1599 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
1603 // Now that we legalized all of the inputs (which may have inserted
1604 // libcalls) create the new CALLSEQ_START node.
1605 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1607 // Merge in the last call, to ensure that this call start after the last
1609 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1610 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1611 Tmp1 = LegalizeOp(Tmp1);
1614 // Do not try to legalize the target-specific arguments (#1+).
1615 if (Tmp1 != Node->getOperand(0)) {
1616 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1618 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1621 // Remember that the CALLSEQ_START is legalized.
1622 AddLegalizedOperand(Op.getValue(0), Result);
1623 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1624 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1626 // Now that the callseq_start and all of the non-call nodes above this call
1627 // sequence have been legalized, legalize the call itself. During this
1628 // process, no libcalls can/will be inserted, guaranteeing that no calls
1630 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1631 // Note that we are selecting this call!
1632 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1633 IsLegalizingCall = true;
1635 // Legalize the call, starting from the CALLSEQ_END.
1636 LegalizeOp(LastCALLSEQ_END);
1637 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1640 case ISD::CALLSEQ_END:
1641 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1642 // will cause this node to be legalized as well as handling libcalls right.
1643 if (LastCALLSEQ_END.Val != Node) {
1644 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1645 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1646 assert(I != LegalizedNodes.end() &&
1647 "Legalizing the call start should have legalized this node!");
1651 // Otherwise, the call start has been legalized and everything is going
1652 // according to plan. Just legalize ourselves normally here.
1653 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1654 // Do not try to legalize the target-specific arguments (#1+), except for
1655 // an optional flag input.
1656 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1657 if (Tmp1 != Node->getOperand(0)) {
1658 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1660 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1663 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1664 if (Tmp1 != Node->getOperand(0) ||
1665 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1666 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1669 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1672 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1673 // This finishes up call legalization.
1674 IsLegalizingCall = false;
1676 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1677 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1678 if (Node->getNumValues() == 2)
1679 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1680 return Result.getValue(Op.ResNo);
1681 case ISD::DYNAMIC_STACKALLOC: {
1682 MVT::ValueType VT = Node->getValueType(0);
1683 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1684 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1685 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1686 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1688 Tmp1 = Result.getValue(0);
1689 Tmp2 = Result.getValue(1);
1690 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1691 default: assert(0 && "This action is not supported yet!");
1692 case TargetLowering::Expand: {
1693 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1694 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1695 " not tell us which reg is the stack pointer!");
1696 SDOperand Chain = Tmp1.getOperand(0);
1698 // Chain the dynamic stack allocation so that it doesn't modify the stack
1699 // pointer when other instructions are using the stack.
1700 Chain = DAG.getCALLSEQ_START(Chain,
1701 DAG.getConstant(0, TLI.getPointerTy()));
1703 SDOperand Size = Tmp2.getOperand(1);
1704 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT);
1705 Chain = SP.getValue(1);
1706 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue();
1707 unsigned StackAlign =
1708 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1709 if (Align > StackAlign)
1710 SP = DAG.getNode(ISD::AND, VT, SP,
1711 DAG.getConstant(-(uint64_t)Align, VT));
1712 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value
1713 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
1716 DAG.getCALLSEQ_END(Chain,
1717 DAG.getConstant(0, TLI.getPointerTy()),
1718 DAG.getConstant(0, TLI.getPointerTy()),
1721 Tmp1 = LegalizeOp(Tmp1);
1722 Tmp2 = LegalizeOp(Tmp2);
1725 case TargetLowering::Custom:
1726 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1728 Tmp1 = LegalizeOp(Tmp3);
1729 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1732 case TargetLowering::Legal:
1735 // Since this op produce two values, make sure to remember that we
1736 // legalized both of them.
1737 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1738 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1739 return Op.ResNo ? Tmp2 : Tmp1;
1741 case ISD::INLINEASM: {
1742 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1743 bool Changed = false;
1744 // Legalize all of the operands of the inline asm, in case they are nodes
1745 // that need to be expanded or something. Note we skip the asm string and
1746 // all of the TargetConstant flags.
1747 SDOperand Op = LegalizeOp(Ops[0]);
1748 Changed = Op != Ops[0];
1751 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1752 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1753 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1754 for (++i; NumVals; ++i, --NumVals) {
1755 SDOperand Op = LegalizeOp(Ops[i]);
1764 Op = LegalizeOp(Ops.back());
1765 Changed |= Op != Ops.back();
1770 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1772 // INLINE asm returns a chain and flag, make sure to add both to the map.
1773 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1774 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1775 return Result.getValue(Op.ResNo);
1778 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1779 // Ensure that libcalls are emitted before a branch.
1780 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1781 Tmp1 = LegalizeOp(Tmp1);
1782 LastCALLSEQ_END = DAG.getEntryNode();
1784 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1787 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1788 // Ensure that libcalls are emitted before a branch.
1789 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1790 Tmp1 = LegalizeOp(Tmp1);
1791 LastCALLSEQ_END = DAG.getEntryNode();
1793 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1794 default: assert(0 && "Indirect target must be legal type (pointer)!");
1796 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1799 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1802 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1803 // Ensure that libcalls are emitted before a branch.
1804 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1805 Tmp1 = LegalizeOp(Tmp1);
1806 LastCALLSEQ_END = DAG.getEntryNode();
1808 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1809 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1811 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1812 default: assert(0 && "This action is not supported yet!");
1813 case TargetLowering::Legal: break;
1814 case TargetLowering::Custom:
1815 Tmp1 = TLI.LowerOperation(Result, DAG);
1816 if (Tmp1.Val) Result = Tmp1;
1818 case TargetLowering::Expand: {
1819 SDOperand Chain = Result.getOperand(0);
1820 SDOperand Table = Result.getOperand(1);
1821 SDOperand Index = Result.getOperand(2);
1823 MVT::ValueType PTy = TLI.getPointerTy();
1824 MachineFunction &MF = DAG.getMachineFunction();
1825 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
1826 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1827 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1830 switch (EntrySize) {
1831 default: assert(0 && "Size of jump table not supported yet."); break;
1832 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr,
1833 PseudoSourceValue::getJumpTable(), 0); break;
1834 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr,
1835 PseudoSourceValue::getJumpTable(), 0); break;
1839 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1840 // For PIC, the sequence is:
1841 // BRIND(load(Jumptable + index) + RelocBase)
1842 // RelocBase can be JumpTable, GOT or some sort of global base.
1843 if (PTy != MVT::i32)
1844 Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr);
1845 Addr = DAG.getNode(ISD::ADD, PTy, Addr,
1846 TLI.getPICJumpTableRelocBase(Table, DAG));
1848 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1853 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1854 // Ensure that libcalls are emitted before a return.
1855 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1856 Tmp1 = LegalizeOp(Tmp1);
1857 LastCALLSEQ_END = DAG.getEntryNode();
1859 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1860 case Expand: assert(0 && "It's impossible to expand bools");
1862 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1865 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1867 // The top bits of the promoted condition are not necessarily zero, ensure
1868 // that the value is properly zero extended.
1869 unsigned BitWidth = Tmp2.getValueSizeInBits();
1870 if (!DAG.MaskedValueIsZero(Tmp2,
1871 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
1872 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1877 // Basic block destination (Op#2) is always legal.
1878 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1880 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1881 default: assert(0 && "This action is not supported yet!");
1882 case TargetLowering::Legal: break;
1883 case TargetLowering::Custom:
1884 Tmp1 = TLI.LowerOperation(Result, DAG);
1885 if (Tmp1.Val) Result = Tmp1;
1887 case TargetLowering::Expand:
1888 // Expand brcond's setcc into its constituent parts and create a BR_CC
1890 if (Tmp2.getOpcode() == ISD::SETCC) {
1891 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1892 Tmp2.getOperand(0), Tmp2.getOperand(1),
1893 Node->getOperand(2));
1895 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1896 DAG.getCondCode(ISD::SETNE), Tmp2,
1897 DAG.getConstant(0, Tmp2.getValueType()),
1898 Node->getOperand(2));
1904 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1905 // Ensure that libcalls are emitted before a branch.
1906 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1907 Tmp1 = LegalizeOp(Tmp1);
1908 Tmp2 = Node->getOperand(2); // LHS
1909 Tmp3 = Node->getOperand(3); // RHS
1910 Tmp4 = Node->getOperand(1); // CC
1912 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1913 LastCALLSEQ_END = DAG.getEntryNode();
1915 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1916 // the LHS is a legal SETCC itself. In this case, we need to compare
1917 // the result against zero to select between true and false values.
1918 if (Tmp3.Val == 0) {
1919 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1920 Tmp4 = DAG.getCondCode(ISD::SETNE);
1923 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1924 Node->getOperand(4));
1926 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1927 default: assert(0 && "Unexpected action for BR_CC!");
1928 case TargetLowering::Legal: break;
1929 case TargetLowering::Custom:
1930 Tmp4 = TLI.LowerOperation(Result, DAG);
1931 if (Tmp4.Val) Result = Tmp4;
1936 LoadSDNode *LD = cast<LoadSDNode>(Node);
1937 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1938 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1940 ISD::LoadExtType ExtType = LD->getExtensionType();
1941 if (ExtType == ISD::NON_EXTLOAD) {
1942 MVT::ValueType VT = Node->getValueType(0);
1943 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1944 Tmp3 = Result.getValue(0);
1945 Tmp4 = Result.getValue(1);
1947 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1948 default: assert(0 && "This action is not supported yet!");
1949 case TargetLowering::Legal:
1950 // If this is an unaligned load and the target doesn't support it,
1952 if (!TLI.allowsUnalignedMemoryAccesses()) {
1953 unsigned ABIAlignment = TLI.getTargetData()->
1954 getABITypeAlignment(MVT::getTypeForValueType(LD->getMemoryVT()));
1955 if (LD->getAlignment() < ABIAlignment){
1956 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
1958 Tmp3 = Result.getOperand(0);
1959 Tmp4 = Result.getOperand(1);
1960 Tmp3 = LegalizeOp(Tmp3);
1961 Tmp4 = LegalizeOp(Tmp4);
1965 case TargetLowering::Custom:
1966 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1968 Tmp3 = LegalizeOp(Tmp1);
1969 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1972 case TargetLowering::Promote: {
1973 // Only promote a load of vector type to another.
1974 assert(MVT::isVector(VT) && "Cannot promote this load!");
1975 // Change base type to a different vector type.
1976 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1978 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1979 LD->getSrcValueOffset(),
1980 LD->isVolatile(), LD->getAlignment());
1981 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1982 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1986 // Since loads produce two values, make sure to remember that we
1987 // legalized both of them.
1988 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1989 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1990 return Op.ResNo ? Tmp4 : Tmp3;
1992 MVT::ValueType SrcVT = LD->getMemoryVT();
1993 unsigned SrcWidth = MVT::getSizeInBits(SrcVT);
1994 int SVOffset = LD->getSrcValueOffset();
1995 unsigned Alignment = LD->getAlignment();
1996 bool isVolatile = LD->isVolatile();
1998 if (SrcWidth != MVT::getStoreSizeInBits(SrcVT) &&
1999 // Some targets pretend to have an i1 loading operation, and actually
2000 // load an i8. This trick is correct for ZEXTLOAD because the top 7
2001 // bits are guaranteed to be zero; it helps the optimizers understand
2002 // that these bits are zero. It is also useful for EXTLOAD, since it
2003 // tells the optimizers that those bits are undefined. It would be
2004 // nice to have an effective generic way of getting these benefits...
2005 // Until such a way is found, don't insist on promoting i1 here.
2006 (SrcVT != MVT::i1 ||
2007 TLI.getLoadXAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
2008 // Promote to a byte-sized load if not loading an integral number of
2009 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
2010 unsigned NewWidth = MVT::getStoreSizeInBits(SrcVT);
2011 MVT::ValueType NVT = MVT::getIntegerType(NewWidth);
2014 // The extra bits are guaranteed to be zero, since we stored them that
2015 // way. A zext load from NVT thus automatically gives zext from SrcVT.
2017 ISD::LoadExtType NewExtType =
2018 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
2020 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0),
2021 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
2022 NVT, isVolatile, Alignment);
2024 Ch = Result.getValue(1); // The chain.
2026 if (ExtType == ISD::SEXTLOAD)
2027 // Having the top bits zero doesn't help when sign extending.
2028 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2029 Result, DAG.getValueType(SrcVT));
2030 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
2031 // All the top bits are guaranteed to be zero - inform the optimizers.
2032 Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result,
2033 DAG.getValueType(SrcVT));
2035 Tmp1 = LegalizeOp(Result);
2036 Tmp2 = LegalizeOp(Ch);
2037 } else if (SrcWidth & (SrcWidth - 1)) {
2038 // If not loading a power-of-2 number of bits, expand as two loads.
2039 assert(MVT::isExtendedVT(SrcVT) && !MVT::isVector(SrcVT) &&
2040 "Unsupported extload!");
2041 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
2042 assert(RoundWidth < SrcWidth);
2043 unsigned ExtraWidth = SrcWidth - RoundWidth;
2044 assert(ExtraWidth < RoundWidth);
2045 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2046 "Load size not an integral number of bytes!");
2047 MVT::ValueType RoundVT = MVT::getIntegerType(RoundWidth);
2048 MVT::ValueType ExtraVT = MVT::getIntegerType(ExtraWidth);
2049 SDOperand Lo, Hi, Ch;
2050 unsigned IncrementSize;
2052 if (TLI.isLittleEndian()) {
2053 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
2054 // Load the bottom RoundWidth bits.
2055 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2056 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2059 // Load the remaining ExtraWidth bits.
2060 IncrementSize = RoundWidth / 8;
2061 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2062 DAG.getIntPtrConstant(IncrementSize));
2063 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2064 LD->getSrcValue(), SVOffset + IncrementSize,
2065 ExtraVT, isVolatile,
2066 MinAlign(Alignment, IncrementSize));
2068 // Build a factor node to remember that this load is independent of the
2070 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2073 // Move the top bits to the right place.
2074 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2075 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2077 // Join the hi and lo parts.
2078 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2080 // Big endian - avoid unaligned loads.
2081 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
2082 // Load the top RoundWidth bits.
2083 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2084 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2087 // Load the remaining ExtraWidth bits.
2088 IncrementSize = RoundWidth / 8;
2089 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2090 DAG.getIntPtrConstant(IncrementSize));
2091 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2092 LD->getSrcValue(), SVOffset + IncrementSize,
2093 ExtraVT, isVolatile,
2094 MinAlign(Alignment, IncrementSize));
2096 // Build a factor node to remember that this load is independent of the
2098 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2101 // Move the top bits to the right place.
2102 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2103 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2105 // Join the hi and lo parts.
2106 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2109 Tmp1 = LegalizeOp(Result);
2110 Tmp2 = LegalizeOp(Ch);
2112 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
2113 default: assert(0 && "This action is not supported yet!");
2114 case TargetLowering::Custom:
2117 case TargetLowering::Legal:
2118 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2119 Tmp1 = Result.getValue(0);
2120 Tmp2 = Result.getValue(1);
2123 Tmp3 = TLI.LowerOperation(Result, DAG);
2125 Tmp1 = LegalizeOp(Tmp3);
2126 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2129 // If this is an unaligned load and the target doesn't support it,
2131 if (!TLI.allowsUnalignedMemoryAccesses()) {
2132 unsigned ABIAlignment = TLI.getTargetData()->
2133 getABITypeAlignment(MVT::getTypeForValueType(LD->getMemoryVT()));
2134 if (LD->getAlignment() < ABIAlignment){
2135 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
2137 Tmp1 = Result.getOperand(0);
2138 Tmp2 = Result.getOperand(1);
2139 Tmp1 = LegalizeOp(Tmp1);
2140 Tmp2 = LegalizeOp(Tmp2);
2145 case TargetLowering::Expand:
2146 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
2147 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
2148 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
2149 LD->getSrcValueOffset(),
2150 LD->isVolatile(), LD->getAlignment());
2151 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
2152 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
2153 Tmp2 = LegalizeOp(Load.getValue(1));
2156 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
2157 // Turn the unsupported load into an EXTLOAD followed by an explicit
2158 // zero/sign extend inreg.
2159 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2160 Tmp1, Tmp2, LD->getSrcValue(),
2161 LD->getSrcValueOffset(), SrcVT,
2162 LD->isVolatile(), LD->getAlignment());
2164 if (ExtType == ISD::SEXTLOAD)
2165 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2166 Result, DAG.getValueType(SrcVT));
2168 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
2169 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
2170 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
2175 // Since loads produce two values, make sure to remember that we legalized
2177 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2178 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2179 return Op.ResNo ? Tmp2 : Tmp1;
2182 case ISD::EXTRACT_ELEMENT: {
2183 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
2184 switch (getTypeAction(OpTy)) {
2185 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
2187 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
2189 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
2190 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
2191 TLI.getShiftAmountTy()));
2192 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
2195 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
2196 Node->getOperand(0));
2200 // Get both the low and high parts.
2201 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2202 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
2203 Result = Tmp2; // 1 -> Hi
2205 Result = Tmp1; // 0 -> Lo
2211 case ISD::CopyToReg:
2212 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2214 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
2215 "Register type must be legal!");
2216 // Legalize the incoming value (must be a legal type).
2217 Tmp2 = LegalizeOp(Node->getOperand(2));
2218 if (Node->getNumValues() == 1) {
2219 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
2221 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
2222 if (Node->getNumOperands() == 4) {
2223 Tmp3 = LegalizeOp(Node->getOperand(3));
2224 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
2227 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
2230 // Since this produces two values, make sure to remember that we legalized
2232 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2233 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2239 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2241 // Ensure that libcalls are emitted before a return.
2242 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2243 Tmp1 = LegalizeOp(Tmp1);
2244 LastCALLSEQ_END = DAG.getEntryNode();
2246 switch (Node->getNumOperands()) {
2248 Tmp2 = Node->getOperand(1);
2249 Tmp3 = Node->getOperand(2); // Signness
2250 switch (getTypeAction(Tmp2.getValueType())) {
2252 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
2255 if (!MVT::isVector(Tmp2.getValueType())) {
2257 ExpandOp(Tmp2, Lo, Hi);
2259 // Big endian systems want the hi reg first.
2260 if (TLI.isBigEndian())
2264 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2266 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
2267 Result = LegalizeOp(Result);
2269 SDNode *InVal = Tmp2.Val;
2270 int InIx = Tmp2.ResNo;
2271 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx));
2272 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx));
2274 // Figure out if there is a simple type corresponding to this Vector
2275 // type. If so, convert to the vector type.
2276 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2277 if (TLI.isTypeLegal(TVT)) {
2278 // Turn this into a return of the vector type.
2279 Tmp2 = LegalizeOp(Tmp2);
2280 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2281 } else if (NumElems == 1) {
2282 // Turn this into a return of the scalar type.
2283 Tmp2 = ScalarizeVectorOp(Tmp2);
2284 Tmp2 = LegalizeOp(Tmp2);
2285 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2287 // FIXME: Returns of gcc generic vectors smaller than a legal type
2288 // should be returned in integer registers!
2290 // The scalarized value type may not be legal, e.g. it might require
2291 // promotion or expansion. Relegalize the return.
2292 Result = LegalizeOp(Result);
2294 // FIXME: Returns of gcc generic vectors larger than a legal vector
2295 // type should be returned by reference!
2297 SplitVectorOp(Tmp2, Lo, Hi);
2298 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2299 Result = LegalizeOp(Result);
2304 Tmp2 = PromoteOp(Node->getOperand(1));
2305 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2306 Result = LegalizeOp(Result);
2311 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2313 default: { // ret <values>
2314 SmallVector<SDOperand, 8> NewValues;
2315 NewValues.push_back(Tmp1);
2316 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
2317 switch (getTypeAction(Node->getOperand(i).getValueType())) {
2319 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
2320 NewValues.push_back(Node->getOperand(i+1));
2324 assert(!MVT::isExtendedVT(Node->getOperand(i).getValueType()) &&
2325 "FIXME: TODO: implement returning non-legal vector types!");
2326 ExpandOp(Node->getOperand(i), Lo, Hi);
2327 NewValues.push_back(Lo);
2328 NewValues.push_back(Node->getOperand(i+1));
2330 NewValues.push_back(Hi);
2331 NewValues.push_back(Node->getOperand(i+1));
2336 assert(0 && "Can't promote multiple return value yet!");
2339 if (NewValues.size() == Node->getNumOperands())
2340 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
2342 Result = DAG.getNode(ISD::RET, MVT::Other,
2343 &NewValues[0], NewValues.size());
2348 if (Result.getOpcode() == ISD::RET) {
2349 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
2350 default: assert(0 && "This action is not supported yet!");
2351 case TargetLowering::Legal: break;
2352 case TargetLowering::Custom:
2353 Tmp1 = TLI.LowerOperation(Result, DAG);
2354 if (Tmp1.Val) Result = Tmp1;
2360 StoreSDNode *ST = cast<StoreSDNode>(Node);
2361 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
2362 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
2363 int SVOffset = ST->getSrcValueOffset();
2364 unsigned Alignment = ST->getAlignment();
2365 bool isVolatile = ST->isVolatile();
2367 if (!ST->isTruncatingStore()) {
2368 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
2369 // FIXME: We shouldn't do this for TargetConstantFP's.
2370 // FIXME: move this to the DAG Combiner! Note that we can't regress due
2371 // to phase ordering between legalized code and the dag combiner. This
2372 // probably means that we need to integrate dag combiner and legalizer
2374 // We generally can't do this one for long doubles.
2375 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
2376 if (CFP->getValueType(0) == MVT::f32 &&
2377 getTypeAction(MVT::i32) == Legal) {
2378 Tmp3 = DAG.getConstant(CFP->getValueAPF().
2379 convertToAPInt().zextOrTrunc(32),
2381 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2382 SVOffset, isVolatile, Alignment);
2384 } else if (CFP->getValueType(0) == MVT::f64) {
2385 // If this target supports 64-bit registers, do a single 64-bit store.
2386 if (getTypeAction(MVT::i64) == Legal) {
2387 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt().
2388 zextOrTrunc(64), MVT::i64);
2389 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2390 SVOffset, isVolatile, Alignment);
2392 } else if (getTypeAction(MVT::i32) == Legal) {
2393 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
2394 // stores. If the target supports neither 32- nor 64-bits, this
2395 // xform is certainly not worth it.
2396 const APInt &IntVal =CFP->getValueAPF().convertToAPInt();
2397 SDOperand Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
2398 SDOperand Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
2399 if (TLI.isBigEndian()) std::swap(Lo, Hi);
2401 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2402 SVOffset, isVolatile, Alignment);
2403 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2404 DAG.getIntPtrConstant(4));
2405 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
2406 isVolatile, MinAlign(Alignment, 4U));
2408 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2414 switch (getTypeAction(ST->getMemoryVT())) {
2416 Tmp3 = LegalizeOp(ST->getValue());
2417 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2420 MVT::ValueType VT = Tmp3.getValueType();
2421 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2422 default: assert(0 && "This action is not supported yet!");
2423 case TargetLowering::Legal:
2424 // If this is an unaligned store and the target doesn't support it,
2426 if (!TLI.allowsUnalignedMemoryAccesses()) {
2427 unsigned ABIAlignment = TLI.getTargetData()->
2428 getABITypeAlignment(MVT::getTypeForValueType(ST->getMemoryVT()));
2429 if (ST->getAlignment() < ABIAlignment)
2430 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2434 case TargetLowering::Custom:
2435 Tmp1 = TLI.LowerOperation(Result, DAG);
2436 if (Tmp1.Val) Result = Tmp1;
2438 case TargetLowering::Promote:
2439 assert(MVT::isVector(VT) && "Unknown legal promote case!");
2440 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
2441 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2442 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
2443 ST->getSrcValue(), SVOffset, isVolatile,
2450 // Truncate the value and store the result.
2451 Tmp3 = PromoteOp(ST->getValue());
2452 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2453 SVOffset, ST->getMemoryVT(),
2454 isVolatile, Alignment);
2458 unsigned IncrementSize = 0;
2461 // If this is a vector type, then we have to calculate the increment as
2462 // the product of the element size in bytes, and the number of elements
2463 // in the high half of the vector.
2464 if (MVT::isVector(ST->getValue().getValueType())) {
2465 SDNode *InVal = ST->getValue().Val;
2466 int InIx = ST->getValue().ResNo;
2467 MVT::ValueType InVT = InVal->getValueType(InIx);
2468 unsigned NumElems = MVT::getVectorNumElements(InVT);
2469 MVT::ValueType EVT = MVT::getVectorElementType(InVT);
2471 // Figure out if there is a simple type corresponding to this Vector
2472 // type. If so, convert to the vector type.
2473 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2474 if (TLI.isTypeLegal(TVT)) {
2475 // Turn this into a normal store of the vector type.
2476 Tmp3 = LegalizeOp(ST->getValue());
2477 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2478 SVOffset, isVolatile, Alignment);
2479 Result = LegalizeOp(Result);
2481 } else if (NumElems == 1) {
2482 // Turn this into a normal store of the scalar type.
2483 Tmp3 = ScalarizeVectorOp(ST->getValue());
2484 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2485 SVOffset, isVolatile, Alignment);
2486 // The scalarized value type may not be legal, e.g. it might require
2487 // promotion or expansion. Relegalize the scalar store.
2488 Result = LegalizeOp(Result);
2491 SplitVectorOp(ST->getValue(), Lo, Hi);
2492 IncrementSize = MVT::getVectorNumElements(Lo.Val->getValueType(0)) *
2493 MVT::getSizeInBits(EVT)/8;
2496 ExpandOp(ST->getValue(), Lo, Hi);
2497 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0;
2499 if (TLI.isBigEndian())
2503 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2504 SVOffset, isVolatile, Alignment);
2506 if (Hi.Val == NULL) {
2507 // Must be int <-> float one-to-one expansion.
2512 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2513 DAG.getIntPtrConstant(IncrementSize));
2514 assert(isTypeLegal(Tmp2.getValueType()) &&
2515 "Pointers must be legal!");
2516 SVOffset += IncrementSize;
2517 Alignment = MinAlign(Alignment, IncrementSize);
2518 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2519 SVOffset, isVolatile, Alignment);
2520 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2524 switch (getTypeAction(ST->getValue().getValueType())) {
2526 Tmp3 = LegalizeOp(ST->getValue());
2529 // We can promote the value, the truncstore will still take care of it.
2530 Tmp3 = PromoteOp(ST->getValue());
2533 // Just store the low part. This may become a non-trunc store, so make
2534 // sure to use getTruncStore, not UpdateNodeOperands below.
2535 ExpandOp(ST->getValue(), Tmp3, Tmp4);
2536 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2537 SVOffset, MVT::i8, isVolatile, Alignment);
2540 MVT::ValueType StVT = ST->getMemoryVT();
2541 unsigned StWidth = MVT::getSizeInBits(StVT);
2543 if (StWidth != MVT::getStoreSizeInBits(StVT)) {
2544 // Promote to a byte-sized store with upper bits zero if not
2545 // storing an integral number of bytes. For example, promote
2546 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
2547 MVT::ValueType NVT = MVT::getIntegerType(MVT::getStoreSizeInBits(StVT));
2548 Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT);
2549 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2550 SVOffset, NVT, isVolatile, Alignment);
2551 } else if (StWidth & (StWidth - 1)) {
2552 // If not storing a power-of-2 number of bits, expand as two stores.
2553 assert(MVT::isExtendedVT(StVT) && !MVT::isVector(StVT) &&
2554 "Unsupported truncstore!");
2555 unsigned RoundWidth = 1 << Log2_32(StWidth);
2556 assert(RoundWidth < StWidth);
2557 unsigned ExtraWidth = StWidth - RoundWidth;
2558 assert(ExtraWidth < RoundWidth);
2559 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2560 "Store size not an integral number of bytes!");
2561 MVT::ValueType RoundVT = MVT::getIntegerType(RoundWidth);
2562 MVT::ValueType ExtraVT = MVT::getIntegerType(ExtraWidth);
2564 unsigned IncrementSize;
2566 if (TLI.isLittleEndian()) {
2567 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
2568 // Store the bottom RoundWidth bits.
2569 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2571 isVolatile, Alignment);
2573 // Store the remaining ExtraWidth bits.
2574 IncrementSize = RoundWidth / 8;
2575 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2576 DAG.getIntPtrConstant(IncrementSize));
2577 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2578 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2579 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2580 SVOffset + IncrementSize, ExtraVT, isVolatile,
2581 MinAlign(Alignment, IncrementSize));
2583 // Big endian - avoid unaligned stores.
2584 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
2585 // Store the top RoundWidth bits.
2586 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2587 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2588 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset,
2589 RoundVT, isVolatile, Alignment);
2591 // Store the remaining ExtraWidth bits.
2592 IncrementSize = RoundWidth / 8;
2593 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2594 DAG.getIntPtrConstant(IncrementSize));
2595 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2596 SVOffset + IncrementSize, ExtraVT, isVolatile,
2597 MinAlign(Alignment, IncrementSize));
2600 // The order of the stores doesn't matter.
2601 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2603 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2604 Tmp2 != ST->getBasePtr())
2605 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2608 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
2609 default: assert(0 && "This action is not supported yet!");
2610 case TargetLowering::Legal:
2611 // If this is an unaligned store and the target doesn't support it,
2613 if (!TLI.allowsUnalignedMemoryAccesses()) {
2614 unsigned ABIAlignment = TLI.getTargetData()->
2615 getABITypeAlignment(MVT::getTypeForValueType(ST->getMemoryVT()));
2616 if (ST->getAlignment() < ABIAlignment)
2617 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2621 case TargetLowering::Custom:
2622 Result = TLI.LowerOperation(Result, DAG);
2625 // TRUNCSTORE:i16 i32 -> STORE i16
2626 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
2627 Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3);
2628 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset,
2629 isVolatile, Alignment);
2637 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2638 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2640 case ISD::STACKSAVE:
2641 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2642 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2643 Tmp1 = Result.getValue(0);
2644 Tmp2 = Result.getValue(1);
2646 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2647 default: assert(0 && "This action is not supported yet!");
2648 case TargetLowering::Legal: break;
2649 case TargetLowering::Custom:
2650 Tmp3 = TLI.LowerOperation(Result, DAG);
2652 Tmp1 = LegalizeOp(Tmp3);
2653 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2656 case TargetLowering::Expand:
2657 // Expand to CopyFromReg if the target set
2658 // StackPointerRegisterToSaveRestore.
2659 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2660 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
2661 Node->getValueType(0));
2662 Tmp2 = Tmp1.getValue(1);
2664 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
2665 Tmp2 = Node->getOperand(0);
2670 // Since stacksave produce two values, make sure to remember that we
2671 // legalized both of them.
2672 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2673 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2674 return Op.ResNo ? Tmp2 : Tmp1;
2676 case ISD::STACKRESTORE:
2677 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2678 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2679 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2681 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2682 default: assert(0 && "This action is not supported yet!");
2683 case TargetLowering::Legal: break;
2684 case TargetLowering::Custom:
2685 Tmp1 = TLI.LowerOperation(Result, DAG);
2686 if (Tmp1.Val) Result = Tmp1;
2688 case TargetLowering::Expand:
2689 // Expand to CopyToReg if the target set
2690 // StackPointerRegisterToSaveRestore.
2691 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2692 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
2700 case ISD::READCYCLECOUNTER:
2701 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2702 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2703 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2704 Node->getValueType(0))) {
2705 default: assert(0 && "This action is not supported yet!");
2706 case TargetLowering::Legal:
2707 Tmp1 = Result.getValue(0);
2708 Tmp2 = Result.getValue(1);
2710 case TargetLowering::Custom:
2711 Result = TLI.LowerOperation(Result, DAG);
2712 Tmp1 = LegalizeOp(Result.getValue(0));
2713 Tmp2 = LegalizeOp(Result.getValue(1));
2717 // Since rdcc produce two values, make sure to remember that we legalized
2719 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2720 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2724 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2725 case Expand: assert(0 && "It's impossible to expand bools");
2727 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2730 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2731 // Make sure the condition is either zero or one.
2732 unsigned BitWidth = Tmp1.getValueSizeInBits();
2733 if (!DAG.MaskedValueIsZero(Tmp1,
2734 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2735 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2739 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2740 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2742 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2744 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2745 default: assert(0 && "This action is not supported yet!");
2746 case TargetLowering::Legal: break;
2747 case TargetLowering::Custom: {
2748 Tmp1 = TLI.LowerOperation(Result, DAG);
2749 if (Tmp1.Val) Result = Tmp1;
2752 case TargetLowering::Expand:
2753 if (Tmp1.getOpcode() == ISD::SETCC) {
2754 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2756 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2758 Result = DAG.getSelectCC(Tmp1,
2759 DAG.getConstant(0, Tmp1.getValueType()),
2760 Tmp2, Tmp3, ISD::SETNE);
2763 case TargetLowering::Promote: {
2764 MVT::ValueType NVT =
2765 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2766 unsigned ExtOp, TruncOp;
2767 if (MVT::isVector(Tmp2.getValueType())) {
2768 ExtOp = ISD::BIT_CONVERT;
2769 TruncOp = ISD::BIT_CONVERT;
2770 } else if (MVT::isInteger(Tmp2.getValueType())) {
2771 ExtOp = ISD::ANY_EXTEND;
2772 TruncOp = ISD::TRUNCATE;
2774 ExtOp = ISD::FP_EXTEND;
2775 TruncOp = ISD::FP_ROUND;
2777 // Promote each of the values to the new type.
2778 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2779 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2780 // Perform the larger operation, then round down.
2781 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2782 if (TruncOp != ISD::FP_ROUND)
2783 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2785 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result,
2786 DAG.getIntPtrConstant(0));
2791 case ISD::SELECT_CC: {
2792 Tmp1 = Node->getOperand(0); // LHS
2793 Tmp2 = Node->getOperand(1); // RHS
2794 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2795 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2796 SDOperand CC = Node->getOperand(4);
2798 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
2800 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
2801 // the LHS is a legal SETCC itself. In this case, we need to compare
2802 // the result against zero to select between true and false values.
2803 if (Tmp2.Val == 0) {
2804 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2805 CC = DAG.getCondCode(ISD::SETNE);
2807 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
2809 // Everything is legal, see if we should expand this op or something.
2810 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
2811 default: assert(0 && "This action is not supported yet!");
2812 case TargetLowering::Legal: break;
2813 case TargetLowering::Custom:
2814 Tmp1 = TLI.LowerOperation(Result, DAG);
2815 if (Tmp1.Val) Result = Tmp1;
2821 Tmp1 = Node->getOperand(0);
2822 Tmp2 = Node->getOperand(1);
2823 Tmp3 = Node->getOperand(2);
2824 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
2826 // If we had to Expand the SetCC operands into a SELECT node, then it may
2827 // not always be possible to return a true LHS & RHS. In this case, just
2828 // return the value we legalized, returned in the LHS
2829 if (Tmp2.Val == 0) {
2834 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
2835 default: assert(0 && "Cannot handle this action for SETCC yet!");
2836 case TargetLowering::Custom:
2839 case TargetLowering::Legal:
2840 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2842 Tmp4 = TLI.LowerOperation(Result, DAG);
2843 if (Tmp4.Val) Result = Tmp4;
2846 case TargetLowering::Promote: {
2847 // First step, figure out the appropriate operation to use.
2848 // Allow SETCC to not be supported for all legal data types
2849 // Mostly this targets FP
2850 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
2851 MVT::ValueType OldVT = NewInTy; OldVT = OldVT;
2853 // Scan for the appropriate larger type to use.
2855 NewInTy = (MVT::ValueType)(NewInTy+1);
2857 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
2858 "Fell off of the edge of the integer world");
2859 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
2860 "Fell off of the edge of the floating point world");
2862 // If the target supports SETCC of this type, use it.
2863 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2866 if (MVT::isInteger(NewInTy))
2867 assert(0 && "Cannot promote Legal Integer SETCC yet");
2869 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2870 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2872 Tmp1 = LegalizeOp(Tmp1);
2873 Tmp2 = LegalizeOp(Tmp2);
2874 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2875 Result = LegalizeOp(Result);
2878 case TargetLowering::Expand:
2879 // Expand a setcc node into a select_cc of the same condition, lhs, and
2880 // rhs that selects between const 1 (true) and const 0 (false).
2881 MVT::ValueType VT = Node->getValueType(0);
2882 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2883 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2889 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2890 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2891 SDOperand CC = Node->getOperand(2);
2893 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, CC);
2895 // Everything is legal, see if we should expand this op or something.
2896 switch (TLI.getOperationAction(ISD::VSETCC, Tmp1.getValueType())) {
2897 default: assert(0 && "This action is not supported yet!");
2898 case TargetLowering::Legal: break;
2899 case TargetLowering::Custom:
2900 Tmp1 = TLI.LowerOperation(Result, DAG);
2901 if (Tmp1.Val) Result = Tmp1;
2907 case ISD::SHL_PARTS:
2908 case ISD::SRA_PARTS:
2909 case ISD::SRL_PARTS: {
2910 SmallVector<SDOperand, 8> Ops;
2911 bool Changed = false;
2912 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2913 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2914 Changed |= Ops.back() != Node->getOperand(i);
2917 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2919 switch (TLI.getOperationAction(Node->getOpcode(),
2920 Node->getValueType(0))) {
2921 default: assert(0 && "This action is not supported yet!");
2922 case TargetLowering::Legal: break;
2923 case TargetLowering::Custom:
2924 Tmp1 = TLI.LowerOperation(Result, DAG);
2926 SDOperand Tmp2, RetVal(0, 0);
2927 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2928 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2929 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2933 assert(RetVal.Val && "Illegal result number");
2939 // Since these produce multiple values, make sure to remember that we
2940 // legalized all of them.
2941 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2942 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2943 return Result.getValue(Op.ResNo);
2965 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2966 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2967 case Expand: assert(0 && "Not possible");
2969 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2972 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2976 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2978 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2979 default: assert(0 && "BinOp legalize operation not supported");
2980 case TargetLowering::Legal: break;
2981 case TargetLowering::Custom:
2982 Tmp1 = TLI.LowerOperation(Result, DAG);
2983 if (Tmp1.Val) Result = Tmp1;
2985 case TargetLowering::Expand: {
2986 MVT::ValueType VT = Op.getValueType();
2988 // See if multiply or divide can be lowered using two-result operations.
2989 SDVTList VTs = DAG.getVTList(VT, VT);
2990 if (Node->getOpcode() == ISD::MUL) {
2991 // We just need the low half of the multiply; try both the signed
2992 // and unsigned forms. If the target supports both SMUL_LOHI and
2993 // UMUL_LOHI, form a preference by checking which forms of plain
2994 // MULH it supports.
2995 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT);
2996 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT);
2997 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT);
2998 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT);
2999 unsigned OpToUse = 0;
3000 if (HasSMUL_LOHI && !HasMULHS) {
3001 OpToUse = ISD::SMUL_LOHI;
3002 } else if (HasUMUL_LOHI && !HasMULHU) {
3003 OpToUse = ISD::UMUL_LOHI;
3004 } else if (HasSMUL_LOHI) {
3005 OpToUse = ISD::SMUL_LOHI;
3006 } else if (HasUMUL_LOHI) {
3007 OpToUse = ISD::UMUL_LOHI;
3010 Result = SDOperand(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).Val, 0);
3014 if (Node->getOpcode() == ISD::MULHS &&
3015 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) {
3016 Result = SDOperand(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
3019 if (Node->getOpcode() == ISD::MULHU &&
3020 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) {
3021 Result = SDOperand(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
3024 if (Node->getOpcode() == ISD::SDIV &&
3025 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3026 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 0);
3029 if (Node->getOpcode() == ISD::UDIV &&
3030 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3031 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 0);
3035 // Check to see if we have a libcall for this operator.
3036 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3037 bool isSigned = false;
3038 switch (Node->getOpcode()) {
3041 if (VT == MVT::i32) {
3042 LC = Node->getOpcode() == ISD::UDIV
3043 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
3044 isSigned = Node->getOpcode() == ISD::SDIV;
3048 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
3049 RTLIB::POW_PPCF128);
3053 if (LC != RTLIB::UNKNOWN_LIBCALL) {
3055 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3059 assert(MVT::isVector(Node->getValueType(0)) &&
3060 "Cannot expand this binary operator!");
3061 // Expand the operation into a bunch of nasty scalar code.
3062 Result = LegalizeOp(UnrollVectorOp(Op));
3065 case TargetLowering::Promote: {
3066 switch (Node->getOpcode()) {
3067 default: assert(0 && "Do not know how to promote this BinOp!");
3071 MVT::ValueType OVT = Node->getValueType(0);
3072 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3073 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
3074 // Bit convert each of the values to the new type.
3075 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
3076 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
3077 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3078 // Bit convert the result back the original type.
3079 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
3087 case ISD::SMUL_LOHI:
3088 case ISD::UMUL_LOHI:
3091 // These nodes will only be produced by target-specific lowering, so
3092 // they shouldn't be here if they aren't legal.
3093 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
3094 "This must be legal!");
3096 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3097 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3098 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3101 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
3102 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3103 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3104 case Expand: assert(0 && "Not possible");
3106 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3109 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3113 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3115 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3116 default: assert(0 && "Operation not supported");
3117 case TargetLowering::Custom:
3118 Tmp1 = TLI.LowerOperation(Result, DAG);
3119 if (Tmp1.Val) Result = Tmp1;
3121 case TargetLowering::Legal: break;
3122 case TargetLowering::Expand: {
3123 // If this target supports fabs/fneg natively and select is cheap,
3124 // do this efficiently.
3125 if (!TLI.isSelectExpensive() &&
3126 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
3127 TargetLowering::Legal &&
3128 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
3129 TargetLowering::Legal) {
3130 // Get the sign bit of the RHS.
3131 MVT::ValueType IVT =
3132 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
3133 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
3134 SignBit = DAG.getSetCC(TLI.getSetCCResultType(SignBit),
3135 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
3136 // Get the absolute value of the result.
3137 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
3138 // Select between the nabs and abs value based on the sign bit of
3140 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
3141 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
3144 Result = LegalizeOp(Result);
3148 // Otherwise, do bitwise ops!
3149 MVT::ValueType NVT =
3150 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
3151 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
3152 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
3153 Result = LegalizeOp(Result);
3161 Tmp1 = LegalizeOp(Node->getOperand(0));
3162 Tmp2 = LegalizeOp(Node->getOperand(1));
3163 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3164 // Since this produces two values, make sure to remember that we legalized
3166 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
3167 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
3172 Tmp1 = LegalizeOp(Node->getOperand(0));
3173 Tmp2 = LegalizeOp(Node->getOperand(1));
3174 Tmp3 = LegalizeOp(Node->getOperand(2));
3175 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3176 // Since this produces two values, make sure to remember that we legalized
3178 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
3179 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
3182 case ISD::BUILD_PAIR: {
3183 MVT::ValueType PairTy = Node->getValueType(0);
3184 // TODO: handle the case where the Lo and Hi operands are not of legal type
3185 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
3186 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
3187 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
3188 case TargetLowering::Promote:
3189 case TargetLowering::Custom:
3190 assert(0 && "Cannot promote/custom this yet!");
3191 case TargetLowering::Legal:
3192 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
3193 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
3195 case TargetLowering::Expand:
3196 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
3197 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
3198 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
3199 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
3200 TLI.getShiftAmountTy()));
3201 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
3210 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3211 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3213 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3214 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
3215 case TargetLowering::Custom:
3218 case TargetLowering::Legal:
3219 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3221 Tmp1 = TLI.LowerOperation(Result, DAG);
3222 if (Tmp1.Val) Result = Tmp1;
3225 case TargetLowering::Expand: {
3226 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
3227 bool isSigned = DivOpc == ISD::SDIV;
3228 MVT::ValueType VT = Node->getValueType(0);
3230 // See if remainder can be lowered using two-result operations.
3231 SDVTList VTs = DAG.getVTList(VT, VT);
3232 if (Node->getOpcode() == ISD::SREM &&
3233 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3234 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 1);
3237 if (Node->getOpcode() == ISD::UREM &&
3238 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3239 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 1);
3243 if (MVT::isInteger(VT)) {
3244 if (TLI.getOperationAction(DivOpc, VT) ==
3245 TargetLowering::Legal) {
3247 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
3248 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
3249 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
3250 } else if (MVT::isVector(VT)) {
3251 Result = LegalizeOp(UnrollVectorOp(Op));
3253 assert(VT == MVT::i32 &&
3254 "Cannot expand this binary operator!");
3255 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
3256 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
3258 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3261 assert(MVT::isFloatingPoint(VT) &&
3262 "remainder op must have integer or floating-point type");
3263 if (MVT::isVector(VT)) {
3264 Result = LegalizeOp(UnrollVectorOp(Op));
3266 // Floating point mod -> fmod libcall.
3267 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
3268 RTLIB::REM_F80, RTLIB::REM_PPCF128);
3270 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3278 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3279 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3281 MVT::ValueType VT = Node->getValueType(0);
3282 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
3283 default: assert(0 && "This action is not supported yet!");
3284 case TargetLowering::Custom:
3287 case TargetLowering::Legal:
3288 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3289 Result = Result.getValue(0);
3290 Tmp1 = Result.getValue(1);
3293 Tmp2 = TLI.LowerOperation(Result, DAG);
3295 Result = LegalizeOp(Tmp2);
3296 Tmp1 = LegalizeOp(Tmp2.getValue(1));
3300 case TargetLowering::Expand: {
3301 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3302 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
3303 // Increment the pointer, VAList, to the next vaarg
3304 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3305 DAG.getConstant(MVT::getSizeInBits(VT)/8,
3306 TLI.getPointerTy()));
3307 // Store the incremented VAList to the legalized pointer
3308 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
3309 // Load the actual argument out of the pointer VAList
3310 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
3311 Tmp1 = LegalizeOp(Result.getValue(1));
3312 Result = LegalizeOp(Result);
3316 // Since VAARG produces two values, make sure to remember that we
3317 // legalized both of them.
3318 AddLegalizedOperand(SDOperand(Node, 0), Result);
3319 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
3320 return Op.ResNo ? Tmp1 : Result;
3324 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3325 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
3326 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
3328 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
3329 default: assert(0 && "This action is not supported yet!");
3330 case TargetLowering::Custom:
3333 case TargetLowering::Legal:
3334 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
3335 Node->getOperand(3), Node->getOperand(4));
3337 Tmp1 = TLI.LowerOperation(Result, DAG);
3338 if (Tmp1.Val) Result = Tmp1;
3341 case TargetLowering::Expand:
3342 // This defaults to loading a pointer from the input and storing it to the
3343 // output, returning the chain.
3344 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3345 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3346 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VS, 0);
3347 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VD, 0);
3353 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3354 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3356 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
3357 default: assert(0 && "This action is not supported yet!");
3358 case TargetLowering::Custom:
3361 case TargetLowering::Legal:
3362 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3364 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
3365 if (Tmp1.Val) Result = Tmp1;
3368 case TargetLowering::Expand:
3369 Result = Tmp1; // Default to a no-op, return the chain
3375 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3376 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3378 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3380 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
3381 default: assert(0 && "This action is not supported yet!");
3382 case TargetLowering::Legal: break;
3383 case TargetLowering::Custom:
3384 Tmp1 = TLI.LowerOperation(Result, DAG);
3385 if (Tmp1.Val) Result = Tmp1;
3392 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3393 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3394 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3395 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3397 assert(0 && "ROTL/ROTR legalize operation not supported");
3399 case TargetLowering::Legal:
3401 case TargetLowering::Custom:
3402 Tmp1 = TLI.LowerOperation(Result, DAG);
3403 if (Tmp1.Val) Result = Tmp1;
3405 case TargetLowering::Promote:
3406 assert(0 && "Do not know how to promote ROTL/ROTR");
3408 case TargetLowering::Expand:
3409 assert(0 && "Do not know how to expand ROTL/ROTR");
3415 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3416 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3417 case TargetLowering::Custom:
3418 assert(0 && "Cannot custom legalize this yet!");
3419 case TargetLowering::Legal:
3420 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3422 case TargetLowering::Promote: {
3423 MVT::ValueType OVT = Tmp1.getValueType();
3424 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3425 unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT);
3427 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3428 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3429 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3430 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3433 case TargetLowering::Expand:
3434 Result = ExpandBSWAP(Tmp1);
3442 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3443 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3444 case TargetLowering::Custom:
3445 case TargetLowering::Legal:
3446 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3447 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3448 TargetLowering::Custom) {
3449 Tmp1 = TLI.LowerOperation(Result, DAG);
3455 case TargetLowering::Promote: {
3456 MVT::ValueType OVT = Tmp1.getValueType();
3457 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3459 // Zero extend the argument.
3460 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3461 // Perform the larger operation, then subtract if needed.
3462 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
3463 switch (Node->getOpcode()) {
3468 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3469 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
3470 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
3472 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3473 DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1);
3476 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3477 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3478 DAG.getConstant(MVT::getSizeInBits(NVT) -
3479 MVT::getSizeInBits(OVT), NVT));
3484 case TargetLowering::Expand:
3485 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
3496 Tmp1 = LegalizeOp(Node->getOperand(0));
3497 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3498 case TargetLowering::Promote:
3499 case TargetLowering::Custom:
3502 case TargetLowering::Legal:
3503 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3505 Tmp1 = TLI.LowerOperation(Result, DAG);
3506 if (Tmp1.Val) Result = Tmp1;
3509 case TargetLowering::Expand:
3510 switch (Node->getOpcode()) {
3511 default: assert(0 && "Unreachable!");
3513 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3514 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3515 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
3518 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3519 MVT::ValueType VT = Node->getValueType(0);
3520 Tmp2 = DAG.getConstantFP(0.0, VT);
3521 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
3523 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
3524 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
3530 MVT::ValueType VT = Node->getValueType(0);
3532 // Expand unsupported unary vector operators by unrolling them.
3533 if (MVT::isVector(VT)) {
3534 Result = LegalizeOp(UnrollVectorOp(Op));
3538 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3539 switch(Node->getOpcode()) {
3541 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3542 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
3545 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
3546 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
3549 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
3550 RTLIB::COS_F80, RTLIB::COS_PPCF128);
3552 default: assert(0 && "Unreachable!");
3555 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3563 MVT::ValueType VT = Node->getValueType(0);
3565 // Expand unsupported unary vector operators by unrolling them.
3566 if (MVT::isVector(VT)) {
3567 Result = LegalizeOp(UnrollVectorOp(Op));
3571 // We always lower FPOWI into a libcall. No target support for it yet.
3572 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
3573 RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
3575 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3578 case ISD::BIT_CONVERT:
3579 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3580 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3581 Node->getValueType(0));
3582 } else if (MVT::isVector(Op.getOperand(0).getValueType())) {
3583 // The input has to be a vector type, we have to either scalarize it, pack
3584 // it, or convert it based on whether the input vector type is legal.
3585 SDNode *InVal = Node->getOperand(0).Val;
3586 int InIx = Node->getOperand(0).ResNo;
3587 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx));
3588 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx));
3590 // Figure out if there is a simple type corresponding to this Vector
3591 // type. If so, convert to the vector type.
3592 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
3593 if (TLI.isTypeLegal(TVT)) {
3594 // Turn this into a bit convert of the vector input.
3595 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3596 LegalizeOp(Node->getOperand(0)));
3598 } else if (NumElems == 1) {
3599 // Turn this into a bit convert of the scalar input.
3600 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3601 ScalarizeVectorOp(Node->getOperand(0)));
3604 // FIXME: UNIMP! Store then reload
3605 assert(0 && "Cast from unsupported vector type not implemented yet!");
3608 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3609 Node->getOperand(0).getValueType())) {
3610 default: assert(0 && "Unknown operation action!");
3611 case TargetLowering::Expand:
3612 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3613 Node->getValueType(0));
3615 case TargetLowering::Legal:
3616 Tmp1 = LegalizeOp(Node->getOperand(0));
3617 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3623 // Conversion operators. The source and destination have different types.
3624 case ISD::SINT_TO_FP:
3625 case ISD::UINT_TO_FP: {
3626 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
3627 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3629 switch (TLI.getOperationAction(Node->getOpcode(),
3630 Node->getOperand(0).getValueType())) {
3631 default: assert(0 && "Unknown operation action!");
3632 case TargetLowering::Custom:
3635 case TargetLowering::Legal:
3636 Tmp1 = LegalizeOp(Node->getOperand(0));
3637 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3639 Tmp1 = TLI.LowerOperation(Result, DAG);
3640 if (Tmp1.Val) Result = Tmp1;
3643 case TargetLowering::Expand:
3644 Result = ExpandLegalINT_TO_FP(isSigned,
3645 LegalizeOp(Node->getOperand(0)),
3646 Node->getValueType(0));
3648 case TargetLowering::Promote:
3649 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
3650 Node->getValueType(0),
3656 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
3657 Node->getValueType(0), Node->getOperand(0));
3660 Tmp1 = PromoteOp(Node->getOperand(0));
3662 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
3663 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
3665 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
3666 Node->getOperand(0).getValueType());
3668 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3669 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
3675 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3677 Tmp1 = LegalizeOp(Node->getOperand(0));
3678 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3681 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3683 // Since the result is legal, we should just be able to truncate the low
3684 // part of the source.
3685 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
3688 Result = PromoteOp(Node->getOperand(0));
3689 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
3694 case ISD::FP_TO_SINT:
3695 case ISD::FP_TO_UINT:
3696 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3698 Tmp1 = LegalizeOp(Node->getOperand(0));
3700 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
3701 default: assert(0 && "Unknown operation action!");
3702 case TargetLowering::Custom:
3705 case TargetLowering::Legal:
3706 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3708 Tmp1 = TLI.LowerOperation(Result, DAG);
3709 if (Tmp1.Val) Result = Tmp1;
3712 case TargetLowering::Promote:
3713 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
3714 Node->getOpcode() == ISD::FP_TO_SINT);
3716 case TargetLowering::Expand:
3717 if (Node->getOpcode() == ISD::FP_TO_UINT) {
3718 SDOperand True, False;
3719 MVT::ValueType VT = Node->getOperand(0).getValueType();
3720 MVT::ValueType NVT = Node->getValueType(0);
3721 const uint64_t zero[] = {0, 0};
3722 APFloat apf = APFloat(APInt(MVT::getSizeInBits(VT), 2, zero));
3723 APInt x = APInt::getSignBit(MVT::getSizeInBits(NVT));
3724 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
3725 Tmp2 = DAG.getConstantFP(apf, VT);
3726 Tmp3 = DAG.getSetCC(TLI.getSetCCResultType(Node->getOperand(0)),
3727 Node->getOperand(0), Tmp2, ISD::SETLT);
3728 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
3729 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
3730 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
3732 False = DAG.getNode(ISD::XOR, NVT, False,
3733 DAG.getConstant(x, NVT));
3734 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
3737 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
3743 MVT::ValueType VT = Op.getValueType();
3744 MVT::ValueType OVT = Node->getOperand(0).getValueType();
3745 // Convert ppcf128 to i32
3746 if (OVT == MVT::ppcf128 && VT == MVT::i32) {
3747 if (Node->getOpcode() == ISD::FP_TO_SINT) {
3748 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128,
3749 Node->getOperand(0), DAG.getValueType(MVT::f64));
3750 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result,
3751 DAG.getIntPtrConstant(1));
3752 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result);
3754 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
3755 APFloat apf = APFloat(APInt(128, 2, TwoE31));
3756 Tmp2 = DAG.getConstantFP(apf, OVT);
3757 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
3758 // FIXME: generated code sucks.
3759 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2,
3760 DAG.getNode(ISD::ADD, MVT::i32,
3761 DAG.getNode(ISD::FP_TO_SINT, VT,
3762 DAG.getNode(ISD::FSUB, OVT,
3763 Node->getOperand(0), Tmp2)),
3764 DAG.getConstant(0x80000000, MVT::i32)),
3765 DAG.getNode(ISD::FP_TO_SINT, VT,
3766 Node->getOperand(0)),
3767 DAG.getCondCode(ISD::SETGE));
3771 // Convert f32 / f64 to i32 / i64 / i128.
3772 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3773 switch (Node->getOpcode()) {
3774 case ISD::FP_TO_SINT: {
3775 if (VT == MVT::i32) {
3776 if (OVT == MVT::f32)
3777 LC = RTLIB::FPTOSINT_F32_I32;
3778 else if (OVT == MVT::f64)
3779 LC = RTLIB::FPTOSINT_F64_I32;
3781 assert(0 && "Unexpected i32-to-fp conversion!");
3782 } else if (VT == MVT::i64) {
3783 if (OVT == MVT::f32)
3784 LC = RTLIB::FPTOSINT_F32_I64;
3785 else if (OVT == MVT::f64)
3786 LC = RTLIB::FPTOSINT_F64_I64;
3787 else if (OVT == MVT::f80)
3788 LC = RTLIB::FPTOSINT_F80_I64;
3789 else if (OVT == MVT::ppcf128)
3790 LC = RTLIB::FPTOSINT_PPCF128_I64;
3792 assert(0 && "Unexpected i64-to-fp conversion!");
3793 } else if (VT == MVT::i128) {
3794 if (OVT == MVT::f32)
3795 LC = RTLIB::FPTOSINT_F32_I128;
3796 else if (OVT == MVT::f64)
3797 LC = RTLIB::FPTOSINT_F64_I128;
3798 else if (OVT == MVT::f80)
3799 LC = RTLIB::FPTOSINT_F80_I128;
3800 else if (OVT == MVT::ppcf128)
3801 LC = RTLIB::FPTOSINT_PPCF128_I128;
3803 assert(0 && "Unexpected i128-to-fp conversion!");
3805 assert(0 && "Unexpectd int-to-fp conversion!");
3809 case ISD::FP_TO_UINT: {
3810 if (VT == MVT::i32) {
3811 if (OVT == MVT::f32)
3812 LC = RTLIB::FPTOUINT_F32_I32;
3813 else if (OVT == MVT::f64)
3814 LC = RTLIB::FPTOUINT_F64_I32;
3815 else if (OVT == MVT::f80)
3816 LC = RTLIB::FPTOUINT_F80_I32;
3818 assert(0 && "Unexpected i32-to-fp conversion!");
3819 } else if (VT == MVT::i64) {
3820 if (OVT == MVT::f32)
3821 LC = RTLIB::FPTOUINT_F32_I64;
3822 else if (OVT == MVT::f64)
3823 LC = RTLIB::FPTOUINT_F64_I64;
3824 else if (OVT == MVT::f80)
3825 LC = RTLIB::FPTOUINT_F80_I64;
3826 else if (OVT == MVT::ppcf128)
3827 LC = RTLIB::FPTOUINT_PPCF128_I64;
3829 assert(0 && "Unexpected i64-to-fp conversion!");
3830 } else if (VT == MVT::i128) {
3831 if (OVT == MVT::f32)
3832 LC = RTLIB::FPTOUINT_F32_I128;
3833 else if (OVT == MVT::f64)
3834 LC = RTLIB::FPTOUINT_F64_I128;
3835 else if (OVT == MVT::f80)
3836 LC = RTLIB::FPTOUINT_F80_I128;
3837 else if (OVT == MVT::ppcf128)
3838 LC = RTLIB::FPTOUINT_PPCF128_I128;
3840 assert(0 && "Unexpected i128-to-fp conversion!");
3842 assert(0 && "Unexpectd int-to-fp conversion!");
3846 default: assert(0 && "Unreachable!");
3849 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3853 Tmp1 = PromoteOp(Node->getOperand(0));
3854 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
3855 Result = LegalizeOp(Result);
3860 case ISD::FP_EXTEND: {
3861 MVT::ValueType DstVT = Op.getValueType();
3862 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3863 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3864 // The only other way we can lower this is to turn it into a STORE,
3865 // LOAD pair, targetting a temporary location (a stack slot).
3866 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT);
3869 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3870 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3872 Tmp1 = LegalizeOp(Node->getOperand(0));
3873 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3876 Tmp1 = PromoteOp(Node->getOperand(0));
3877 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1);
3882 case ISD::FP_ROUND: {
3883 MVT::ValueType DstVT = Op.getValueType();
3884 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3885 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3886 if (SrcVT == MVT::ppcf128) {
3888 ExpandOp(Node->getOperand(0), Lo, Result);
3889 // Round it the rest of the way (e.g. to f32) if needed.
3890 if (DstVT!=MVT::f64)
3891 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1));
3894 // The only other way we can lower this is to turn it into a STORE,
3895 // LOAD pair, targetting a temporary location (a stack slot).
3896 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT);
3899 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3900 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3902 Tmp1 = LegalizeOp(Node->getOperand(0));
3903 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3906 Tmp1 = PromoteOp(Node->getOperand(0));
3907 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1,
3908 Node->getOperand(1));
3913 case ISD::ANY_EXTEND:
3914 case ISD::ZERO_EXTEND:
3915 case ISD::SIGN_EXTEND:
3916 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3917 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3919 Tmp1 = LegalizeOp(Node->getOperand(0));
3920 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3921 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3922 TargetLowering::Custom) {
3923 Tmp1 = TLI.LowerOperation(Result, DAG);
3924 if (Tmp1.Val) Result = Tmp1;
3928 switch (Node->getOpcode()) {
3929 case ISD::ANY_EXTEND:
3930 Tmp1 = PromoteOp(Node->getOperand(0));
3931 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
3933 case ISD::ZERO_EXTEND:
3934 Result = PromoteOp(Node->getOperand(0));
3935 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3936 Result = DAG.getZeroExtendInReg(Result,
3937 Node->getOperand(0).getValueType());
3939 case ISD::SIGN_EXTEND:
3940 Result = PromoteOp(Node->getOperand(0));
3941 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3942 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3944 DAG.getValueType(Node->getOperand(0).getValueType()));
3949 case ISD::FP_ROUND_INREG:
3950 case ISD::SIGN_EXTEND_INREG: {
3951 Tmp1 = LegalizeOp(Node->getOperand(0));
3952 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3954 // If this operation is not supported, convert it to a shl/shr or load/store
3956 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
3957 default: assert(0 && "This action not supported for this op yet!");
3958 case TargetLowering::Legal:
3959 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3961 case TargetLowering::Expand:
3962 // If this is an integer extend and shifts are supported, do that.
3963 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
3964 // NOTE: we could fall back on load/store here too for targets without
3965 // SAR. However, it is doubtful that any exist.
3966 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
3967 MVT::getSizeInBits(ExtraVT);
3968 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
3969 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
3970 Node->getOperand(0), ShiftCst);
3971 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
3973 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
3974 // The only way we can lower this is to turn it into a TRUNCSTORE,
3975 // EXTLOAD pair, targetting a temporary location (a stack slot).
3977 // NOTE: there is a choice here between constantly creating new stack
3978 // slots and always reusing the same one. We currently always create
3979 // new ones, as reuse may inhibit scheduling.
3980 Result = EmitStackConvert(Node->getOperand(0), ExtraVT,
3981 Node->getValueType(0));
3983 assert(0 && "Unknown op");
3989 case ISD::TRAMPOLINE: {
3991 for (unsigned i = 0; i != 6; ++i)
3992 Ops[i] = LegalizeOp(Node->getOperand(i));
3993 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
3994 // The only option for this node is to custom lower it.
3995 Result = TLI.LowerOperation(Result, DAG);
3996 assert(Result.Val && "Should always custom lower!");
3998 // Since trampoline produces two values, make sure to remember that we
3999 // legalized both of them.
4000 Tmp1 = LegalizeOp(Result.getValue(1));
4001 Result = LegalizeOp(Result);
4002 AddLegalizedOperand(SDOperand(Node, 0), Result);
4003 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
4004 return Op.ResNo ? Tmp1 : Result;
4006 case ISD::FLT_ROUNDS_: {
4007 MVT::ValueType VT = Node->getValueType(0);
4008 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4009 default: assert(0 && "This action not supported for this op yet!");
4010 case TargetLowering::Custom:
4011 Result = TLI.LowerOperation(Op, DAG);
4012 if (Result.Val) break;
4014 case TargetLowering::Legal:
4015 // If this operation is not supported, lower it to constant 1
4016 Result = DAG.getConstant(1, VT);
4022 MVT::ValueType VT = Node->getValueType(0);
4023 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4024 default: assert(0 && "This action not supported for this op yet!");
4025 case TargetLowering::Legal:
4026 Tmp1 = LegalizeOp(Node->getOperand(0));
4027 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4029 case TargetLowering::Custom:
4030 Result = TLI.LowerOperation(Op, DAG);
4031 if (Result.Val) break;
4033 case TargetLowering::Expand:
4034 // If this operation is not supported, lower it to 'abort()' call
4035 Tmp1 = LegalizeOp(Node->getOperand(0));
4036 TargetLowering::ArgListTy Args;
4037 std::pair<SDOperand,SDOperand> CallResult =
4038 TLI.LowerCallTo(Tmp1, Type::VoidTy,
4039 false, false, false, CallingConv::C, false,
4040 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
4042 Result = CallResult.second;
4049 assert(Result.getValueType() == Op.getValueType() &&
4050 "Bad legalization!");
4052 // Make sure that the generated code is itself legal.
4054 Result = LegalizeOp(Result);
4056 // Note that LegalizeOp may be reentered even from single-use nodes, which
4057 // means that we always must cache transformed nodes.
4058 AddLegalizedOperand(Op, Result);
4062 /// PromoteOp - Given an operation that produces a value in an invalid type,
4063 /// promote it to compute the value into a larger type. The produced value will
4064 /// have the correct bits for the low portion of the register, but no guarantee
4065 /// is made about the top bits: it may be zero, sign-extended, or garbage.
4066 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
4067 MVT::ValueType VT = Op.getValueType();
4068 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4069 assert(getTypeAction(VT) == Promote &&
4070 "Caller should expand or legalize operands that are not promotable!");
4071 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
4072 "Cannot promote to smaller type!");
4074 SDOperand Tmp1, Tmp2, Tmp3;
4076 SDNode *Node = Op.Val;
4078 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
4079 if (I != PromotedNodes.end()) return I->second;
4081 switch (Node->getOpcode()) {
4082 case ISD::CopyFromReg:
4083 assert(0 && "CopyFromReg must be legal!");
4086 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
4088 assert(0 && "Do not know how to promote this operator!");
4091 Result = DAG.getNode(ISD::UNDEF, NVT);
4095 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
4097 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
4098 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
4100 case ISD::ConstantFP:
4101 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
4102 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
4106 assert(isTypeLegal(TLI.getSetCCResultType(Node->getOperand(0)))
4107 && "SetCC type is not legal??");
4108 Result = DAG.getNode(ISD::SETCC,
4109 TLI.getSetCCResultType(Node->getOperand(0)),
4110 Node->getOperand(0), Node->getOperand(1),
4111 Node->getOperand(2));
4115 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4117 Result = LegalizeOp(Node->getOperand(0));
4118 assert(Result.getValueType() >= NVT &&
4119 "This truncation doesn't make sense!");
4120 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
4121 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
4124 // The truncation is not required, because we don't guarantee anything
4125 // about high bits anyway.
4126 Result = PromoteOp(Node->getOperand(0));
4129 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4130 // Truncate the low part of the expanded value to the result type
4131 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
4134 case ISD::SIGN_EXTEND:
4135 case ISD::ZERO_EXTEND:
4136 case ISD::ANY_EXTEND:
4137 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4138 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
4140 // Input is legal? Just do extend all the way to the larger type.
4141 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4144 // Promote the reg if it's smaller.
4145 Result = PromoteOp(Node->getOperand(0));
4146 // The high bits are not guaranteed to be anything. Insert an extend.
4147 if (Node->getOpcode() == ISD::SIGN_EXTEND)
4148 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4149 DAG.getValueType(Node->getOperand(0).getValueType()));
4150 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
4151 Result = DAG.getZeroExtendInReg(Result,
4152 Node->getOperand(0).getValueType());
4156 case ISD::BIT_CONVERT:
4157 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
4158 Node->getValueType(0));
4159 Result = PromoteOp(Result);
4162 case ISD::FP_EXTEND:
4163 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
4165 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4166 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
4167 case Promote: assert(0 && "Unreachable with 2 FP types!");
4169 if (Node->getConstantOperandVal(1) == 0) {
4170 // Input is legal? Do an FP_ROUND_INREG.
4171 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
4172 DAG.getValueType(VT));
4174 // Just remove the truncate, it isn't affecting the value.
4175 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0),
4176 Node->getOperand(1));
4181 case ISD::SINT_TO_FP:
4182 case ISD::UINT_TO_FP:
4183 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4185 // No extra round required here.
4186 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4190 Result = PromoteOp(Node->getOperand(0));
4191 if (Node->getOpcode() == ISD::SINT_TO_FP)
4192 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
4194 DAG.getValueType(Node->getOperand(0).getValueType()));
4196 Result = DAG.getZeroExtendInReg(Result,
4197 Node->getOperand(0).getValueType());
4198 // No extra round required here.
4199 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
4202 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
4203 Node->getOperand(0));
4204 // Round if we cannot tolerate excess precision.
4205 if (NoExcessFPPrecision)
4206 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4207 DAG.getValueType(VT));
4212 case ISD::SIGN_EXTEND_INREG:
4213 Result = PromoteOp(Node->getOperand(0));
4214 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4215 Node->getOperand(1));
4217 case ISD::FP_TO_SINT:
4218 case ISD::FP_TO_UINT:
4219 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4222 Tmp1 = Node->getOperand(0);
4225 // The input result is prerounded, so we don't have to do anything
4227 Tmp1 = PromoteOp(Node->getOperand(0));
4230 // If we're promoting a UINT to a larger size, check to see if the new node
4231 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
4232 // we can use that instead. This allows us to generate better code for
4233 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
4234 // legal, such as PowerPC.
4235 if (Node->getOpcode() == ISD::FP_TO_UINT &&
4236 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
4237 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
4238 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
4239 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
4241 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4247 Tmp1 = PromoteOp(Node->getOperand(0));
4248 assert(Tmp1.getValueType() == NVT);
4249 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4250 // NOTE: we do not have to do any extra rounding here for
4251 // NoExcessFPPrecision, because we know the input will have the appropriate
4252 // precision, and these operations don't modify precision at all.
4258 Tmp1 = PromoteOp(Node->getOperand(0));
4259 assert(Tmp1.getValueType() == NVT);
4260 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4261 if (NoExcessFPPrecision)
4262 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4263 DAG.getValueType(VT));
4267 // Promote f32 powi to f64 powi. Note that this could insert a libcall
4268 // directly as well, which may be better.
4269 Tmp1 = PromoteOp(Node->getOperand(0));
4270 assert(Tmp1.getValueType() == NVT);
4271 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1));
4272 if (NoExcessFPPrecision)
4273 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4274 DAG.getValueType(VT));
4278 case ISD::ATOMIC_LCS: {
4279 Tmp2 = PromoteOp(Node->getOperand(2));
4280 Tmp3 = PromoteOp(Node->getOperand(3));
4281 Result = DAG.getAtomic(Node->getOpcode(), Node->getOperand(0),
4282 Node->getOperand(1), Tmp2, Tmp3,
4283 cast<AtomicSDNode>(Node)->getVT());
4284 // Remember that we legalized the chain.
4285 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4288 case ISD::ATOMIC_LAS:
4289 case ISD::ATOMIC_LSS:
4290 case ISD::ATOMIC_LOAD_AND:
4291 case ISD::ATOMIC_LOAD_OR:
4292 case ISD::ATOMIC_LOAD_XOR:
4293 case ISD::ATOMIC_LOAD_MIN:
4294 case ISD::ATOMIC_LOAD_MAX:
4295 case ISD::ATOMIC_LOAD_UMIN:
4296 case ISD::ATOMIC_LOAD_UMAX:
4297 case ISD::ATOMIC_SWAP: {
4298 Tmp2 = PromoteOp(Node->getOperand(2));
4299 Result = DAG.getAtomic(Node->getOpcode(), Node->getOperand(0),
4300 Node->getOperand(1), Tmp2,
4301 cast<AtomicSDNode>(Node)->getVT());
4302 // Remember that we legalized the chain.
4303 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4313 // The input may have strange things in the top bits of the registers, but
4314 // these operations don't care. They may have weird bits going out, but
4315 // that too is okay if they are integer operations.
4316 Tmp1 = PromoteOp(Node->getOperand(0));
4317 Tmp2 = PromoteOp(Node->getOperand(1));
4318 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4319 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4324 Tmp1 = PromoteOp(Node->getOperand(0));
4325 Tmp2 = PromoteOp(Node->getOperand(1));
4326 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4327 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4329 // Floating point operations will give excess precision that we may not be
4330 // able to tolerate. If we DO allow excess precision, just leave it,
4331 // otherwise excise it.
4332 // FIXME: Why would we need to round FP ops more than integer ones?
4333 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
4334 if (NoExcessFPPrecision)
4335 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4336 DAG.getValueType(VT));
4341 // These operators require that their input be sign extended.
4342 Tmp1 = PromoteOp(Node->getOperand(0));
4343 Tmp2 = PromoteOp(Node->getOperand(1));
4344 if (MVT::isInteger(NVT)) {
4345 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4346 DAG.getValueType(VT));
4347 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4348 DAG.getValueType(VT));
4350 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4352 // Perform FP_ROUND: this is probably overly pessimistic.
4353 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
4354 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4355 DAG.getValueType(VT));
4359 case ISD::FCOPYSIGN:
4360 // These operators require that their input be fp extended.
4361 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4362 case Expand: assert(0 && "not implemented");
4363 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break;
4364 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break;
4366 switch (getTypeAction(Node->getOperand(1).getValueType())) {
4367 case Expand: assert(0 && "not implemented");
4368 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
4369 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
4371 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4373 // Perform FP_ROUND: this is probably overly pessimistic.
4374 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
4375 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4376 DAG.getValueType(VT));
4381 // These operators require that their input be zero extended.
4382 Tmp1 = PromoteOp(Node->getOperand(0));
4383 Tmp2 = PromoteOp(Node->getOperand(1));
4384 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
4385 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4386 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4387 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4391 Tmp1 = PromoteOp(Node->getOperand(0));
4392 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
4395 // The input value must be properly sign extended.
4396 Tmp1 = PromoteOp(Node->getOperand(0));
4397 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4398 DAG.getValueType(VT));
4399 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
4402 // The input value must be properly zero extended.
4403 Tmp1 = PromoteOp(Node->getOperand(0));
4404 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4405 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
4409 Tmp1 = Node->getOperand(0); // Get the chain.
4410 Tmp2 = Node->getOperand(1); // Get the pointer.
4411 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
4412 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
4413 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
4415 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
4416 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
4417 // Increment the pointer, VAList, to the next vaarg
4418 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
4419 DAG.getConstant(MVT::getSizeInBits(VT)/8,
4420 TLI.getPointerTy()));
4421 // Store the incremented VAList to the legalized pointer
4422 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
4423 // Load the actual argument out of the pointer VAList
4424 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
4426 // Remember that we legalized the chain.
4427 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4431 LoadSDNode *LD = cast<LoadSDNode>(Node);
4432 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
4433 ? ISD::EXTLOAD : LD->getExtensionType();
4434 Result = DAG.getExtLoad(ExtType, NVT,
4435 LD->getChain(), LD->getBasePtr(),
4436 LD->getSrcValue(), LD->getSrcValueOffset(),
4439 LD->getAlignment());
4440 // Remember that we legalized the chain.
4441 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4445 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
4446 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
4448 unsigned VT2 = Tmp2.getValueType();
4449 assert(VT2 == Tmp3.getValueType()
4450 && "PromoteOp SELECT: Operands 2 and 3 ValueTypes don't match");
4451 // Ensure that the resulting node is at least the same size as the operands'
4452 // value types, because we cannot assume that TLI.getSetCCValueType() is
4454 Result = DAG.getNode(ISD::SELECT, VT2, Node->getOperand(0), Tmp2, Tmp3);
4457 case ISD::SELECT_CC:
4458 Tmp2 = PromoteOp(Node->getOperand(2)); // True
4459 Tmp3 = PromoteOp(Node->getOperand(3)); // False
4460 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4461 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
4464 Tmp1 = Node->getOperand(0);
4465 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
4466 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
4467 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
4468 DAG.getConstant(MVT::getSizeInBits(NVT) -
4469 MVT::getSizeInBits(VT),
4470 TLI.getShiftAmountTy()));
4475 // Zero extend the argument
4476 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4477 // Perform the larger operation, then subtract if needed.
4478 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4479 switch(Node->getOpcode()) {
4484 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
4485 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
4486 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
4488 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
4489 DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1);
4492 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4493 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
4494 DAG.getConstant(MVT::getSizeInBits(NVT) -
4495 MVT::getSizeInBits(VT), NVT));
4499 case ISD::EXTRACT_SUBVECTOR:
4500 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
4502 case ISD::EXTRACT_VECTOR_ELT:
4503 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
4507 assert(Result.Val && "Didn't set a result!");
4509 // Make sure the result is itself legal.
4510 Result = LegalizeOp(Result);
4512 // Remember that we promoted this!
4513 AddPromotedOperand(Op, Result);
4517 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
4518 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
4519 /// based on the vector type. The return type of this matches the element type
4520 /// of the vector, which may not be legal for the target.
4521 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
4522 // We know that operand #0 is the Vec vector. If the index is a constant
4523 // or if the invec is a supported hardware type, we can use it. Otherwise,
4524 // lower to a store then an indexed load.
4525 SDOperand Vec = Op.getOperand(0);
4526 SDOperand Idx = Op.getOperand(1);
4528 MVT::ValueType TVT = Vec.getValueType();
4529 unsigned NumElems = MVT::getVectorNumElements(TVT);
4531 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
4532 default: assert(0 && "This action is not supported yet!");
4533 case TargetLowering::Custom: {
4534 Vec = LegalizeOp(Vec);
4535 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4536 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG);
4541 case TargetLowering::Legal:
4542 if (isTypeLegal(TVT)) {
4543 Vec = LegalizeOp(Vec);
4544 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4548 case TargetLowering::Expand:
4552 if (NumElems == 1) {
4553 // This must be an access of the only element. Return it.
4554 Op = ScalarizeVectorOp(Vec);
4555 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
4556 unsigned NumLoElts = 1 << Log2_32(NumElems-1);
4557 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4559 SplitVectorOp(Vec, Lo, Hi);
4560 if (CIdx->getValue() < NumLoElts) {
4564 Idx = DAG.getConstant(CIdx->getValue() - NumLoElts,
4565 Idx.getValueType());
4568 // It's now an extract from the appropriate high or low part. Recurse.
4569 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4570 Op = ExpandEXTRACT_VECTOR_ELT(Op);
4572 // Store the value to a temporary stack slot, then LOAD the scalar
4573 // element back out.
4574 SDOperand StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
4575 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
4577 // Add the offset to the index.
4578 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
4579 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
4580 DAG.getConstant(EltSize, Idx.getValueType()));
4582 if (MVT::getSizeInBits(Idx.getValueType()) >
4583 MVT::getSizeInBits(TLI.getPointerTy()))
4584 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx);
4586 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
4588 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
4590 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
4595 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
4596 /// we assume the operation can be split if it is not already legal.
4597 SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) {
4598 // We know that operand #0 is the Vec vector. For now we assume the index
4599 // is a constant and that the extracted result is a supported hardware type.
4600 SDOperand Vec = Op.getOperand(0);
4601 SDOperand Idx = LegalizeOp(Op.getOperand(1));
4603 unsigned NumElems = MVT::getVectorNumElements(Vec.getValueType());
4605 if (NumElems == MVT::getVectorNumElements(Op.getValueType())) {
4606 // This must be an access of the desired vector length. Return it.
4610 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4612 SplitVectorOp(Vec, Lo, Hi);
4613 if (CIdx->getValue() < NumElems/2) {
4617 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
4620 // It's now an extract from the appropriate high or low part. Recurse.
4621 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4622 return ExpandEXTRACT_SUBVECTOR(Op);
4625 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
4626 /// with condition CC on the current target. This usually involves legalizing
4627 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
4628 /// there may be no choice but to create a new SetCC node to represent the
4629 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
4630 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
4631 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
4634 SDOperand Tmp1, Tmp2, Tmp3, Result;
4636 switch (getTypeAction(LHS.getValueType())) {
4638 Tmp1 = LegalizeOp(LHS); // LHS
4639 Tmp2 = LegalizeOp(RHS); // RHS
4642 Tmp1 = PromoteOp(LHS); // LHS
4643 Tmp2 = PromoteOp(RHS); // RHS
4645 // If this is an FP compare, the operands have already been extended.
4646 if (MVT::isInteger(LHS.getValueType())) {
4647 MVT::ValueType VT = LHS.getValueType();
4648 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4650 // Otherwise, we have to insert explicit sign or zero extends. Note
4651 // that we could insert sign extends for ALL conditions, but zero extend
4652 // is cheaper on many machines (an AND instead of two shifts), so prefer
4654 switch (cast<CondCodeSDNode>(CC)->get()) {
4655 default: assert(0 && "Unknown integer comparison!");
4662 // ALL of these operations will work if we either sign or zero extend
4663 // the operands (including the unsigned comparisons!). Zero extend is
4664 // usually a simpler/cheaper operation, so prefer it.
4665 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4666 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4672 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4673 DAG.getValueType(VT));
4674 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4675 DAG.getValueType(VT));
4681 MVT::ValueType VT = LHS.getValueType();
4682 if (VT == MVT::f32 || VT == MVT::f64) {
4683 // Expand into one or more soft-fp libcall(s).
4684 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL;
4685 switch (cast<CondCodeSDNode>(CC)->get()) {
4688 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4692 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
4696 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4700 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4704 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4708 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4711 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4714 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
4717 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4718 switch (cast<CondCodeSDNode>(CC)->get()) {
4720 // SETONE = SETOLT | SETOGT
4721 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4724 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4727 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4730 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4733 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4736 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4738 default: assert(0 && "Unsupported FP setcc!");
4743 Tmp1 = ExpandLibCall(LC1,
4744 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4745 false /*sign irrelevant*/, Dummy);
4746 Tmp2 = DAG.getConstant(0, MVT::i32);
4747 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
4748 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
4749 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
4751 LHS = ExpandLibCall(LC2,
4752 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4753 false /*sign irrelevant*/, Dummy);
4754 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, Tmp2,
4755 DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
4756 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4764 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
4765 ExpandOp(LHS, LHSLo, LHSHi);
4766 ExpandOp(RHS, RHSLo, RHSHi);
4767 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
4769 if (VT==MVT::ppcf128) {
4770 // FIXME: This generated code sucks. We want to generate
4771 // FCMP crN, hi1, hi2
4773 // FCMP crN, lo1, lo2
4774 // The following can be improved, but not that much.
4775 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETEQ);
4776 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, CCCode);
4777 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4778 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETNE);
4779 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode);
4780 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4781 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
4790 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
4791 if (RHSCST->isAllOnesValue()) {
4792 // Comparison to -1.
4793 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
4798 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
4799 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
4800 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4801 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
4804 // If this is a comparison of the sign bit, just look at the top part.
4806 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
4807 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
4808 CST->isNullValue()) || // X < 0
4809 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
4810 CST->isAllOnesValue())) { // X > -1
4816 // FIXME: This generated code sucks.
4817 ISD::CondCode LowCC;
4819 default: assert(0 && "Unknown integer setcc!");
4821 case ISD::SETULT: LowCC = ISD::SETULT; break;
4823 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
4825 case ISD::SETULE: LowCC = ISD::SETULE; break;
4827 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
4830 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
4831 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
4832 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
4834 // NOTE: on targets without efficient SELECT of bools, we can always use
4835 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
4836 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
4837 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo,
4838 LowCC, false, DagCombineInfo);
4840 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC);
4841 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4842 CCCode, false, DagCombineInfo);
4844 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi,
4847 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
4848 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
4849 if ((Tmp1C && Tmp1C->isNullValue()) ||
4850 (Tmp2C && Tmp2C->isNullValue() &&
4851 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
4852 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
4853 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
4854 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
4855 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
4856 // low part is known false, returns high part.
4857 // For LE / GE, if high part is known false, ignore the low part.
4858 // For LT / GT, if high part is known true, ignore the low part.
4862 Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4863 ISD::SETEQ, false, DagCombineInfo);
4865 Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4867 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
4868 Result, Tmp1, Tmp2));
4879 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
4880 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
4881 /// a load from the stack slot to DestVT, extending it if needed.
4882 /// The resultant code need not be legal.
4883 SDOperand SelectionDAGLegalize::EmitStackConvert(SDOperand SrcOp,
4884 MVT::ValueType SlotVT,
4885 MVT::ValueType DestVT) {
4886 // Create the stack frame object.
4887 SDOperand FIPtr = DAG.CreateStackTemporary(SlotVT);
4889 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
4890 int SPFI = StackPtrFI->getIndex();
4892 unsigned SrcSize = MVT::getSizeInBits(SrcOp.getValueType());
4893 unsigned SlotSize = MVT::getSizeInBits(SlotVT);
4894 unsigned DestSize = MVT::getSizeInBits(DestVT);
4896 // Emit a store to the stack slot. Use a truncstore if the input value is
4897 // later than DestVT.
4899 if (SrcSize > SlotSize)
4900 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr,
4901 PseudoSourceValue::getFixedStack(),
4904 assert(SrcSize == SlotSize && "Invalid store");
4905 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr,
4906 PseudoSourceValue::getFixedStack(),
4910 // Result is a load from the stack slot.
4911 if (SlotSize == DestSize)
4912 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0);
4914 assert(SlotSize < DestSize && "Unknown extension!");
4915 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT);
4918 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
4919 // Create a vector sized/aligned stack slot, store the value to element #0,
4920 // then load the whole vector back out.
4921 SDOperand StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
4923 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
4924 int SPFI = StackPtrFI->getIndex();
4926 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
4927 PseudoSourceValue::getFixedStack(), SPFI);
4928 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,
4929 PseudoSourceValue::getFixedStack(), SPFI);
4933 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
4934 /// support the operation, but do support the resultant vector type.
4935 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
4937 // If the only non-undef value is the low element, turn this into a
4938 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
4939 unsigned NumElems = Node->getNumOperands();
4940 bool isOnlyLowElement = true;
4941 SDOperand SplatValue = Node->getOperand(0);
4943 // FIXME: it would be far nicer to change this into map<SDOperand,uint64_t>
4944 // and use a bitmask instead of a list of elements.
4945 std::map<SDOperand, std::vector<unsigned> > Values;
4946 Values[SplatValue].push_back(0);
4947 bool isConstant = true;
4948 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
4949 SplatValue.getOpcode() != ISD::UNDEF)
4952 for (unsigned i = 1; i < NumElems; ++i) {
4953 SDOperand V = Node->getOperand(i);
4954 Values[V].push_back(i);
4955 if (V.getOpcode() != ISD::UNDEF)
4956 isOnlyLowElement = false;
4957 if (SplatValue != V)
4958 SplatValue = SDOperand(0,0);
4960 // If this isn't a constant element or an undef, we can't use a constant
4962 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
4963 V.getOpcode() != ISD::UNDEF)
4967 if (isOnlyLowElement) {
4968 // If the low element is an undef too, then this whole things is an undef.
4969 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
4970 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
4971 // Otherwise, turn this into a scalar_to_vector node.
4972 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4973 Node->getOperand(0));
4976 // If all elements are constants, create a load from the constant pool.
4978 MVT::ValueType VT = Node->getValueType(0);
4979 std::vector<Constant*> CV;
4980 for (unsigned i = 0, e = NumElems; i != e; ++i) {
4981 if (ConstantFPSDNode *V =
4982 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
4983 CV.push_back(ConstantFP::get(V->getValueAPF()));
4984 } else if (ConstantSDNode *V =
4985 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
4986 CV.push_back(ConstantInt::get(V->getAPIntValue()));
4988 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
4990 MVT::getTypeForValueType(Node->getOperand(0).getValueType());
4991 CV.push_back(UndefValue::get(OpNTy));
4994 Constant *CP = ConstantVector::get(CV);
4995 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
4996 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4997 PseudoSourceValue::getConstantPool(), 0);
5000 if (SplatValue.Val) { // Splat of one value?
5001 // Build the shuffle constant vector: <0, 0, 0, 0>
5002 MVT::ValueType MaskVT =
5003 MVT::getIntVectorWithNumElements(NumElems);
5004 SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT));
5005 std::vector<SDOperand> ZeroVec(NumElems, Zero);
5006 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
5007 &ZeroVec[0], ZeroVec.size());
5009 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
5010 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
5011 // Get the splatted value into the low element of a vector register.
5012 SDOperand LowValVec =
5013 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
5015 // Return shuffle(LowValVec, undef, <0,0,0,0>)
5016 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
5017 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
5022 // If there are only two unique elements, we may be able to turn this into a
5024 if (Values.size() == 2) {
5025 // Get the two values in deterministic order.
5026 SDOperand Val1 = Node->getOperand(1);
5028 std::map<SDOperand, std::vector<unsigned> >::iterator MI = Values.begin();
5029 if (MI->first != Val1)
5032 Val2 = (++MI)->first;
5034 // If Val1 is an undef, make sure end ends up as Val2, to ensure that our
5035 // vector shuffle has the undef vector on the RHS.
5036 if (Val1.getOpcode() == ISD::UNDEF)
5037 std::swap(Val1, Val2);
5039 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
5040 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
5041 MVT::ValueType MaskEltVT = MVT::getVectorElementType(MaskVT);
5042 std::vector<SDOperand> MaskVec(NumElems);
5044 // Set elements of the shuffle mask for Val1.
5045 std::vector<unsigned> &Val1Elts = Values[Val1];
5046 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i)
5047 MaskVec[Val1Elts[i]] = DAG.getConstant(0, MaskEltVT);
5049 // Set elements of the shuffle mask for Val2.
5050 std::vector<unsigned> &Val2Elts = Values[Val2];
5051 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i)
5052 if (Val2.getOpcode() != ISD::UNDEF)
5053 MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT);
5055 MaskVec[Val2Elts[i]] = DAG.getNode(ISD::UNDEF, MaskEltVT);
5057 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
5058 &MaskVec[0], MaskVec.size());
5060 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it.
5061 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
5062 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
5063 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val1);
5064 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val2);
5065 SDOperand Ops[] = { Val1, Val2, ShuffleMask };
5067 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
5068 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops, 3);
5072 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
5073 // aligned object on the stack, store each element into it, then load
5074 // the result as a vector.
5075 MVT::ValueType VT = Node->getValueType(0);
5076 // Create the stack frame object.
5077 SDOperand FIPtr = DAG.CreateStackTemporary(VT);
5079 // Emit a store of each element to the stack slot.
5080 SmallVector<SDOperand, 8> Stores;
5081 unsigned TypeByteSize =
5082 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
5083 // Store (in the right endianness) the elements to memory.
5084 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5085 // Ignore undef elements.
5086 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
5088 unsigned Offset = TypeByteSize*i;
5090 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
5091 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
5093 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
5097 SDOperand StoreChain;
5098 if (!Stores.empty()) // Not all undef elements?
5099 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
5100 &Stores[0], Stores.size());
5102 StoreChain = DAG.getEntryNode();
5104 // Result is a load from the stack slot.
5105 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
5108 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
5109 SDOperand Op, SDOperand Amt,
5110 SDOperand &Lo, SDOperand &Hi) {
5111 // Expand the subcomponents.
5112 SDOperand LHSL, LHSH;
5113 ExpandOp(Op, LHSL, LHSH);
5115 SDOperand Ops[] = { LHSL, LHSH, Amt };
5116 MVT::ValueType VT = LHSL.getValueType();
5117 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
5118 Hi = Lo.getValue(1);
5122 /// ExpandShift - Try to find a clever way to expand this shift operation out to
5123 /// smaller elements. If we can't find a way that is more efficient than a
5124 /// libcall on this target, return false. Otherwise, return true with the
5125 /// low-parts expanded into Lo and Hi.
5126 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
5127 SDOperand &Lo, SDOperand &Hi) {
5128 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
5129 "This is not a shift!");
5131 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
5132 SDOperand ShAmt = LegalizeOp(Amt);
5133 MVT::ValueType ShTy = ShAmt.getValueType();
5134 unsigned ShBits = MVT::getSizeInBits(ShTy);
5135 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
5136 unsigned NVTBits = MVT::getSizeInBits(NVT);
5138 // Handle the case when Amt is an immediate.
5139 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
5140 unsigned Cst = CN->getValue();
5141 // Expand the incoming operand to be shifted, so that we have its parts
5143 ExpandOp(Op, InL, InH);
5147 Lo = DAG.getConstant(0, NVT);
5148 Hi = DAG.getConstant(0, NVT);
5149 } else if (Cst > NVTBits) {
5150 Lo = DAG.getConstant(0, NVT);
5151 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
5152 } else if (Cst == NVTBits) {
5153 Lo = DAG.getConstant(0, NVT);
5156 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
5157 Hi = DAG.getNode(ISD::OR, NVT,
5158 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
5159 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
5164 Lo = DAG.getConstant(0, NVT);
5165 Hi = DAG.getConstant(0, NVT);
5166 } else if (Cst > NVTBits) {
5167 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
5168 Hi = DAG.getConstant(0, NVT);
5169 } else if (Cst == NVTBits) {
5171 Hi = DAG.getConstant(0, NVT);
5173 Lo = DAG.getNode(ISD::OR, NVT,
5174 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5175 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5176 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
5181 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
5182 DAG.getConstant(NVTBits-1, ShTy));
5183 } else if (Cst > NVTBits) {
5184 Lo = DAG.getNode(ISD::SRA, NVT, InH,
5185 DAG.getConstant(Cst-NVTBits, ShTy));
5186 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5187 DAG.getConstant(NVTBits-1, ShTy));
5188 } else if (Cst == NVTBits) {
5190 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5191 DAG.getConstant(NVTBits-1, ShTy));
5193 Lo = DAG.getNode(ISD::OR, NVT,
5194 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5195 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5196 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
5202 // Okay, the shift amount isn't constant. However, if we can tell that it is
5203 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
5204 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
5205 APInt KnownZero, KnownOne;
5206 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
5208 // If we know that if any of the high bits of the shift amount are one, then
5209 // we can do this as a couple of simple shifts.
5210 if (KnownOne.intersects(Mask)) {
5211 // Mask out the high bit, which we know is set.
5212 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
5213 DAG.getConstant(~Mask, Amt.getValueType()));
5215 // Expand the incoming operand to be shifted, so that we have its parts
5217 ExpandOp(Op, InL, InH);
5220 Lo = DAG.getConstant(0, NVT); // Low part is zero.
5221 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
5224 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
5225 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
5228 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
5229 DAG.getConstant(NVTBits-1, Amt.getValueType()));
5230 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
5235 // If we know that the high bits of the shift amount are all zero, then we can
5236 // do this as a couple of simple shifts.
5237 if ((KnownZero & Mask) == Mask) {
5239 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
5240 DAG.getConstant(NVTBits, Amt.getValueType()),
5243 // Expand the incoming operand to be shifted, so that we have its parts
5245 ExpandOp(Op, InL, InH);
5248 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
5249 Hi = DAG.getNode(ISD::OR, NVT,
5250 DAG.getNode(ISD::SHL, NVT, InH, Amt),
5251 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
5254 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
5255 Lo = DAG.getNode(ISD::OR, NVT,
5256 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5257 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5260 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
5261 Lo = DAG.getNode(ISD::OR, NVT,
5262 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5263 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5272 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
5273 // does not fit into a register, return the lo part and set the hi part to the
5274 // by-reg argument. If it does fit into a single register, return the result
5275 // and leave the Hi part unset.
5276 SDOperand SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
5277 bool isSigned, SDOperand &Hi) {
5278 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
5279 // The input chain to this libcall is the entry node of the function.
5280 // Legalizing the call will automatically add the previous call to the
5282 SDOperand InChain = DAG.getEntryNode();
5284 TargetLowering::ArgListTy Args;
5285 TargetLowering::ArgListEntry Entry;
5286 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5287 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
5288 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
5289 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
5290 Entry.isSExt = isSigned;
5291 Entry.isZExt = !isSigned;
5292 Args.push_back(Entry);
5294 SDOperand Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
5295 TLI.getPointerTy());
5297 // Splice the libcall in wherever FindInputOutputChains tells us to.
5298 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
5299 std::pair<SDOperand,SDOperand> CallInfo =
5300 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, CallingConv::C,
5301 false, Callee, Args, DAG);
5303 // Legalize the call sequence, starting with the chain. This will advance
5304 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
5305 // was added by LowerCallTo (guaranteeing proper serialization of calls).
5306 LegalizeOp(CallInfo.second);
5308 switch (getTypeAction(CallInfo.first.getValueType())) {
5309 default: assert(0 && "Unknown thing");
5311 Result = CallInfo.first;
5314 ExpandOp(CallInfo.first, Result, Hi);
5321 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
5323 SDOperand SelectionDAGLegalize::
5324 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
5325 MVT::ValueType SourceVT = Source.getValueType();
5326 bool ExpandSource = getTypeAction(SourceVT) == Expand;
5328 // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc.
5329 if (!isSigned && SourceVT != MVT::i32) {
5330 // The integer value loaded will be incorrectly if the 'sign bit' of the
5331 // incoming integer is set. To handle this, we dynamically test to see if
5332 // it is set, and, if so, add a fudge factor.
5336 ExpandOp(Source, Lo, Hi);
5337 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi);
5339 // The comparison for the sign bit will use the entire operand.
5343 // If this is unsigned, and not supported, first perform the conversion to
5344 // signed, then adjust the result if the sign bit is set.
5345 SDOperand SignedConv = ExpandIntToFP(true, DestTy, Source);
5347 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
5348 DAG.getConstant(0, Hi.getValueType()),
5350 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5351 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5352 SignSet, Four, Zero);
5353 uint64_t FF = 0x5f800000ULL;
5354 if (TLI.isLittleEndian()) FF <<= 32;
5355 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5357 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5358 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5359 SDOperand FudgeInReg;
5360 if (DestTy == MVT::f32)
5361 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5362 PseudoSourceValue::getConstantPool(), 0);
5363 else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32))
5364 // FIXME: Avoid the extend by construction the right constantpool?
5365 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
5367 PseudoSourceValue::getConstantPool(), 0,
5370 assert(0 && "Unexpected conversion");
5372 MVT::ValueType SCVT = SignedConv.getValueType();
5373 if (SCVT != DestTy) {
5374 // Destination type needs to be expanded as well. The FADD now we are
5375 // constructing will be expanded into a libcall.
5376 if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) {
5377 assert(MVT::getSizeInBits(SCVT) * 2 == MVT::getSizeInBits(DestTy));
5378 SignedConv = DAG.getNode(ISD::BUILD_PAIR, DestTy,
5379 SignedConv, SignedConv.getValue(1));
5381 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
5383 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
5386 // Check to see if the target has a custom way to lower this. If so, use it.
5387 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) {
5388 default: assert(0 && "This action not implemented for this operation!");
5389 case TargetLowering::Legal:
5390 case TargetLowering::Expand:
5391 break; // This case is handled below.
5392 case TargetLowering::Custom: {
5393 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
5396 return LegalizeOp(NV);
5397 break; // The target decided this was legal after all
5401 // Expand the source, then glue it back together for the call. We must expand
5402 // the source in case it is shared (this pass of legalize must traverse it).
5404 SDOperand SrcLo, SrcHi;
5405 ExpandOp(Source, SrcLo, SrcHi);
5406 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, SrcLo, SrcHi);
5410 if (SourceVT == MVT::i32) {
5411 if (DestTy == MVT::f32)
5412 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32;
5414 assert(DestTy == MVT::f64 && "Unknown fp value type!");
5415 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64;
5417 } else if (SourceVT == MVT::i64) {
5418 if (DestTy == MVT::f32)
5419 LC = RTLIB::SINTTOFP_I64_F32;
5420 else if (DestTy == MVT::f64)
5421 LC = RTLIB::SINTTOFP_I64_F64;
5422 else if (DestTy == MVT::f80)
5423 LC = RTLIB::SINTTOFP_I64_F80;
5425 assert(DestTy == MVT::ppcf128 && "Unknown fp value type!");
5426 LC = RTLIB::SINTTOFP_I64_PPCF128;
5428 } else if (SourceVT == MVT::i128) {
5429 if (DestTy == MVT::f32)
5430 LC = RTLIB::SINTTOFP_I128_F32;
5431 else if (DestTy == MVT::f64)
5432 LC = RTLIB::SINTTOFP_I128_F64;
5433 else if (DestTy == MVT::f80)
5434 LC = RTLIB::SINTTOFP_I128_F80;
5436 assert(DestTy == MVT::ppcf128 && "Unknown fp value type!");
5437 LC = RTLIB::SINTTOFP_I128_PPCF128;
5440 assert(0 && "Unknown int value type");
5443 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!");
5444 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
5446 SDOperand Result = ExpandLibCall(LC, Source.Val, isSigned, HiPart);
5447 if (Result.getValueType() != DestTy && HiPart.Val)
5448 Result = DAG.getNode(ISD::BUILD_PAIR, DestTy, Result, HiPart);
5452 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
5453 /// INT_TO_FP operation of the specified operand when the target requests that
5454 /// we expand it. At this point, we know that the result and operand types are
5455 /// legal for the target.
5456 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
5458 MVT::ValueType DestVT) {
5459 if (Op0.getValueType() == MVT::i32) {
5460 // simple 32-bit [signed|unsigned] integer to float/double expansion
5462 // Get the stack frame index of a 8 byte buffer.
5463 SDOperand StackSlot = DAG.CreateStackTemporary(MVT::f64);
5465 // word offset constant for Hi/Lo address computation
5466 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
5467 // set up Hi and Lo (into buffer) address based on endian
5468 SDOperand Hi = StackSlot;
5469 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
5470 if (TLI.isLittleEndian())
5473 // if signed map to unsigned space
5474 SDOperand Op0Mapped;
5476 // constant used to invert sign bit (signed to unsigned mapping)
5477 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
5478 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
5482 // store the lo of the constructed double - based on integer input
5483 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(),
5484 Op0Mapped, Lo, NULL, 0);
5485 // initial hi portion of constructed double
5486 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
5487 // store the hi of the constructed double - biased exponent
5488 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
5489 // load the constructed double
5490 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
5491 // FP constant to bias correct the final result
5492 SDOperand Bias = DAG.getConstantFP(isSigned ?
5493 BitsToDouble(0x4330000080000000ULL)
5494 : BitsToDouble(0x4330000000000000ULL),
5496 // subtract the bias
5497 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
5500 // handle final rounding
5501 if (DestVT == MVT::f64) {
5504 } else if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(MVT::f64)) {
5505 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub,
5506 DAG.getIntPtrConstant(0));
5507 } else if (MVT::getSizeInBits(DestVT) > MVT::getSizeInBits(MVT::f64)) {
5508 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
5512 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
5513 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
5515 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Op0), Op0,
5516 DAG.getConstant(0, Op0.getValueType()),
5518 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5519 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5520 SignSet, Four, Zero);
5522 // If the sign bit of the integer is set, the large number will be treated
5523 // as a negative number. To counteract this, the dynamic code adds an
5524 // offset depending on the data type.
5526 switch (Op0.getValueType()) {
5527 default: assert(0 && "Unsupported integer type!");
5528 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
5529 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
5530 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
5531 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
5533 if (TLI.isLittleEndian()) FF <<= 32;
5534 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5536 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5537 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5538 SDOperand FudgeInReg;
5539 if (DestVT == MVT::f32)
5540 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5541 PseudoSourceValue::getConstantPool(), 0);
5544 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT,
5545 DAG.getEntryNode(), CPIdx,
5546 PseudoSourceValue::getConstantPool(), 0,
5550 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
5553 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
5554 /// *INT_TO_FP operation of the specified operand when the target requests that
5555 /// we promote it. At this point, we know that the result and operand types are
5556 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
5557 /// operation that takes a larger input.
5558 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
5559 MVT::ValueType DestVT,
5561 // First step, figure out the appropriate *INT_TO_FP operation to use.
5562 MVT::ValueType NewInTy = LegalOp.getValueType();
5564 unsigned OpToUse = 0;
5566 // Scan for the appropriate larger type to use.
5568 NewInTy = (MVT::ValueType)(NewInTy+1);
5569 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
5571 // If the target supports SINT_TO_FP of this type, use it.
5572 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
5574 case TargetLowering::Legal:
5575 if (!TLI.isTypeLegal(NewInTy))
5576 break; // Can't use this datatype.
5578 case TargetLowering::Custom:
5579 OpToUse = ISD::SINT_TO_FP;
5583 if (isSigned) continue;
5585 // If the target supports UINT_TO_FP of this type, use it.
5586 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
5588 case TargetLowering::Legal:
5589 if (!TLI.isTypeLegal(NewInTy))
5590 break; // Can't use this datatype.
5592 case TargetLowering::Custom:
5593 OpToUse = ISD::UINT_TO_FP;
5598 // Otherwise, try a larger type.
5601 // Okay, we found the operation and type to use. Zero extend our input to the
5602 // desired type then run the operation on it.
5603 return DAG.getNode(OpToUse, DestVT,
5604 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
5608 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
5609 /// FP_TO_*INT operation of the specified operand when the target requests that
5610 /// we promote it. At this point, we know that the result and operand types are
5611 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
5612 /// operation that returns a larger result.
5613 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
5614 MVT::ValueType DestVT,
5616 // First step, figure out the appropriate FP_TO*INT operation to use.
5617 MVT::ValueType NewOutTy = DestVT;
5619 unsigned OpToUse = 0;
5621 // Scan for the appropriate larger type to use.
5623 NewOutTy = (MVT::ValueType)(NewOutTy+1);
5624 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
5626 // If the target supports FP_TO_SINT returning this type, use it.
5627 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
5629 case TargetLowering::Legal:
5630 if (!TLI.isTypeLegal(NewOutTy))
5631 break; // Can't use this datatype.
5633 case TargetLowering::Custom:
5634 OpToUse = ISD::FP_TO_SINT;
5639 // If the target supports FP_TO_UINT of this type, use it.
5640 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
5642 case TargetLowering::Legal:
5643 if (!TLI.isTypeLegal(NewOutTy))
5644 break; // Can't use this datatype.
5646 case TargetLowering::Custom:
5647 OpToUse = ISD::FP_TO_UINT;
5652 // Otherwise, try a larger type.
5656 // Okay, we found the operation and type to use.
5657 SDOperand Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp);
5659 // If the operation produces an invalid type, it must be custom lowered. Use
5660 // the target lowering hooks to expand it. Just keep the low part of the
5661 // expanded operation, we know that we're truncating anyway.
5662 if (getTypeAction(NewOutTy) == Expand) {
5663 Operation = SDOperand(TLI.ExpandOperationResult(Operation.Val, DAG), 0);
5664 assert(Operation.Val && "Didn't return anything");
5667 // Truncate the result of the extended FP_TO_*INT operation to the desired
5669 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation);
5672 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
5674 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
5675 MVT::ValueType VT = Op.getValueType();
5676 MVT::ValueType SHVT = TLI.getShiftAmountTy();
5677 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
5679 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
5681 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5682 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5683 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
5685 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5686 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5687 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5688 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5689 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
5690 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
5691 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5692 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5693 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5695 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
5696 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
5697 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5698 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5699 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5700 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5701 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
5702 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
5703 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
5704 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
5705 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
5706 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
5707 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
5708 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
5709 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
5710 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
5711 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5712 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5713 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
5714 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5715 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
5719 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
5721 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
5723 default: assert(0 && "Cannot expand this yet!");
5725 static const uint64_t mask[6] = {
5726 0x5555555555555555ULL, 0x3333333333333333ULL,
5727 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
5728 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
5730 MVT::ValueType VT = Op.getValueType();
5731 MVT::ValueType ShVT = TLI.getShiftAmountTy();
5732 unsigned len = MVT::getSizeInBits(VT);
5733 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5734 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
5735 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
5736 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5737 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
5738 DAG.getNode(ISD::AND, VT,
5739 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
5744 // for now, we do this:
5745 // x = x | (x >> 1);
5746 // x = x | (x >> 2);
5748 // x = x | (x >>16);
5749 // x = x | (x >>32); // for 64-bit input
5750 // return popcount(~x);
5752 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
5753 MVT::ValueType VT = Op.getValueType();
5754 MVT::ValueType ShVT = TLI.getShiftAmountTy();
5755 unsigned len = MVT::getSizeInBits(VT);
5756 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5757 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5758 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
5760 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
5761 return DAG.getNode(ISD::CTPOP, VT, Op);
5764 // for now, we use: { return popcount(~x & (x - 1)); }
5765 // unless the target has ctlz but not ctpop, in which case we use:
5766 // { return 32 - nlz(~x & (x-1)); }
5767 // see also http://www.hackersdelight.org/HDcode/ntz.cc
5768 MVT::ValueType VT = Op.getValueType();
5769 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
5770 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
5771 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
5772 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
5773 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
5774 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
5775 TLI.isOperationLegal(ISD::CTLZ, VT))
5776 return DAG.getNode(ISD::SUB, VT,
5777 DAG.getConstant(MVT::getSizeInBits(VT), VT),
5778 DAG.getNode(ISD::CTLZ, VT, Tmp3));
5779 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
5784 /// ExpandOp - Expand the specified SDOperand into its two component pieces
5785 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
5786 /// LegalizeNodes map is filled in for any results that are not expanded, the
5787 /// ExpandedNodes map is filled in for any results that are expanded, and the
5788 /// Lo/Hi values are returned.
5789 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
5790 MVT::ValueType VT = Op.getValueType();
5791 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
5792 SDNode *Node = Op.Val;
5793 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
5794 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) ||
5795 MVT::isVector(VT)) &&
5796 "Cannot expand to FP value or to larger int value!");
5798 // See if we already expanded it.
5799 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
5800 = ExpandedNodes.find(Op);
5801 if (I != ExpandedNodes.end()) {
5802 Lo = I->second.first;
5803 Hi = I->second.second;
5807 switch (Node->getOpcode()) {
5808 case ISD::CopyFromReg:
5809 assert(0 && "CopyFromReg must be legal!");
5810 case ISD::FP_ROUND_INREG:
5811 if (VT == MVT::ppcf128 &&
5812 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
5813 TargetLowering::Custom) {
5814 SDOperand SrcLo, SrcHi, Src;
5815 ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
5816 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi);
5817 SDOperand Result = TLI.LowerOperation(
5818 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG);
5819 assert(Result.Val->getOpcode() == ISD::BUILD_PAIR);
5820 Lo = Result.Val->getOperand(0);
5821 Hi = Result.Val->getOperand(1);
5827 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
5829 assert(0 && "Do not know how to expand this operator!");
5831 case ISD::EXTRACT_ELEMENT:
5832 ExpandOp(Node->getOperand(0), Lo, Hi);
5833 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
5834 return ExpandOp(Hi, Lo, Hi);
5835 return ExpandOp(Lo, Lo, Hi);
5836 case ISD::EXTRACT_VECTOR_ELT:
5837 assert(VT==MVT::i64 && "Do not know how to expand this operator!");
5838 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types.
5839 Lo = ExpandEXTRACT_VECTOR_ELT(Op);
5840 return ExpandOp(Lo, Lo, Hi);
5842 NVT = TLI.getTypeToExpandTo(VT);
5843 Lo = DAG.getNode(ISD::UNDEF, NVT);
5844 Hi = DAG.getNode(ISD::UNDEF, NVT);
5846 case ISD::Constant: {
5847 unsigned NVTBits = MVT::getSizeInBits(NVT);
5848 const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue();
5849 Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT);
5850 Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT);
5853 case ISD::ConstantFP: {
5854 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
5855 if (CFP->getValueType(0) == MVT::ppcf128) {
5856 APInt api = CFP->getValueAPF().convertToAPInt();
5857 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
5859 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
5863 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
5864 if (getTypeAction(Lo.getValueType()) == Expand)
5865 ExpandOp(Lo, Lo, Hi);
5868 case ISD::BUILD_PAIR:
5869 // Return the operands.
5870 Lo = Node->getOperand(0);
5871 Hi = Node->getOperand(1);
5874 case ISD::MERGE_VALUES:
5875 if (Node->getNumValues() == 1) {
5876 ExpandOp(Op.getOperand(0), Lo, Hi);
5879 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y)
5880 assert(Op.ResNo == 0 && Node->getNumValues() == 2 &&
5881 Op.getValue(1).getValueType() == MVT::Other &&
5882 "unhandled MERGE_VALUES");
5883 ExpandOp(Op.getOperand(0), Lo, Hi);
5884 // Remember that we legalized the chain.
5885 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1)));
5888 case ISD::SIGN_EXTEND_INREG:
5889 ExpandOp(Node->getOperand(0), Lo, Hi);
5890 // sext_inreg the low part if needed.
5891 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
5893 // The high part gets the sign extension from the lo-part. This handles
5894 // things like sextinreg V:i64 from i8.
5895 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5896 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
5897 TLI.getShiftAmountTy()));
5901 ExpandOp(Node->getOperand(0), Lo, Hi);
5902 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
5903 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
5909 ExpandOp(Node->getOperand(0), Lo, Hi);
5910 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
5911 DAG.getNode(ISD::CTPOP, NVT, Lo),
5912 DAG.getNode(ISD::CTPOP, NVT, Hi));
5913 Hi = DAG.getConstant(0, NVT);
5917 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
5918 ExpandOp(Node->getOperand(0), Lo, Hi);
5919 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5920 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
5921 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(HLZ), HLZ, BitsC,
5923 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
5924 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
5926 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
5927 Hi = DAG.getConstant(0, NVT);
5932 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
5933 ExpandOp(Node->getOperand(0), Lo, Hi);
5934 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5935 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
5936 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(LTZ), LTZ, BitsC,
5938 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
5939 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
5941 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
5942 Hi = DAG.getConstant(0, NVT);
5947 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
5948 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
5949 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
5950 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
5952 // Remember that we legalized the chain.
5953 Hi = LegalizeOp(Hi);
5954 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
5955 if (TLI.isBigEndian())
5961 LoadSDNode *LD = cast<LoadSDNode>(Node);
5962 SDOperand Ch = LD->getChain(); // Legalize the chain.
5963 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer.
5964 ISD::LoadExtType ExtType = LD->getExtensionType();
5965 int SVOffset = LD->getSrcValueOffset();
5966 unsigned Alignment = LD->getAlignment();
5967 bool isVolatile = LD->isVolatile();
5969 if (ExtType == ISD::NON_EXTLOAD) {
5970 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5971 isVolatile, Alignment);
5972 if (VT == MVT::f32 || VT == MVT::f64) {
5973 // f32->i32 or f64->i64 one to one expansion.
5974 // Remember that we legalized the chain.
5975 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5976 // Recursively expand the new load.
5977 if (getTypeAction(NVT) == Expand)
5978 ExpandOp(Lo, Lo, Hi);
5982 // Increment the pointer to the other half.
5983 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
5984 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
5985 DAG.getIntPtrConstant(IncrementSize));
5986 SVOffset += IncrementSize;
5987 Alignment = MinAlign(Alignment, IncrementSize);
5988 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5989 isVolatile, Alignment);
5991 // Build a factor node to remember that this load is independent of the
5993 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
5996 // Remember that we legalized the chain.
5997 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
5998 if (TLI.isBigEndian())
6001 MVT::ValueType EVT = LD->getMemoryVT();
6003 if ((VT == MVT::f64 && EVT == MVT::f32) ||
6004 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
6005 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
6006 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(),
6007 SVOffset, isVolatile, Alignment);
6008 // Remember that we legalized the chain.
6009 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1)));
6010 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
6015 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),
6016 SVOffset, isVolatile, Alignment);
6018 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(),
6019 SVOffset, EVT, isVolatile,
6022 // Remember that we legalized the chain.
6023 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
6025 if (ExtType == ISD::SEXTLOAD) {
6026 // The high part is obtained by SRA'ing all but one of the bits of the
6028 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
6029 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6030 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6031 } else if (ExtType == ISD::ZEXTLOAD) {
6032 // The high part is just a zero.
6033 Hi = DAG.getConstant(0, NVT);
6034 } else /* if (ExtType == ISD::EXTLOAD) */ {
6035 // The high part is undefined.
6036 Hi = DAG.getNode(ISD::UNDEF, NVT);
6043 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
6044 SDOperand LL, LH, RL, RH;
6045 ExpandOp(Node->getOperand(0), LL, LH);
6046 ExpandOp(Node->getOperand(1), RL, RH);
6047 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
6048 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
6052 SDOperand LL, LH, RL, RH;
6053 ExpandOp(Node->getOperand(1), LL, LH);
6054 ExpandOp(Node->getOperand(2), RL, RH);
6055 if (getTypeAction(NVT) == Expand)
6056 NVT = TLI.getTypeToExpandTo(NVT);
6057 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
6059 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
6062 case ISD::SELECT_CC: {
6063 SDOperand TL, TH, FL, FH;
6064 ExpandOp(Node->getOperand(2), TL, TH);
6065 ExpandOp(Node->getOperand(3), FL, FH);
6066 if (getTypeAction(NVT) == Expand)
6067 NVT = TLI.getTypeToExpandTo(NVT);
6068 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
6069 Node->getOperand(1), TL, FL, Node->getOperand(4));
6071 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
6072 Node->getOperand(1), TH, FH, Node->getOperand(4));
6075 case ISD::ANY_EXTEND:
6076 // The low part is any extension of the input (which degenerates to a copy).
6077 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
6078 // The high part is undefined.
6079 Hi = DAG.getNode(ISD::UNDEF, NVT);
6081 case ISD::SIGN_EXTEND: {
6082 // The low part is just a sign extension of the input (which degenerates to
6084 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
6086 // The high part is obtained by SRA'ing all but one of the bits of the lo
6088 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
6089 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6090 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6093 case ISD::ZERO_EXTEND:
6094 // The low part is just a zero extension of the input (which degenerates to
6096 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
6098 // The high part is just a zero.
6099 Hi = DAG.getConstant(0, NVT);
6102 case ISD::TRUNCATE: {
6103 // The input value must be larger than this value. Expand *it*.
6105 ExpandOp(Node->getOperand(0), NewLo, Hi);
6107 // The low part is now either the right size, or it is closer. If not the
6108 // right size, make an illegal truncate so we recursively expand it.
6109 if (NewLo.getValueType() != Node->getValueType(0))
6110 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
6111 ExpandOp(NewLo, Lo, Hi);
6115 case ISD::BIT_CONVERT: {
6117 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
6118 // If the target wants to, allow it to lower this itself.
6119 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6120 case Expand: assert(0 && "cannot expand FP!");
6121 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
6122 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
6124 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
6127 // f32 / f64 must be expanded to i32 / i64.
6128 if (VT == MVT::f32 || VT == MVT::f64) {
6129 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6130 if (getTypeAction(NVT) == Expand)
6131 ExpandOp(Lo, Lo, Hi);
6135 // If source operand will be expanded to the same type as VT, i.e.
6136 // i64 <- f64, i32 <- f32, expand the source operand instead.
6137 MVT::ValueType VT0 = Node->getOperand(0).getValueType();
6138 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
6139 ExpandOp(Node->getOperand(0), Lo, Hi);
6143 // Turn this into a load/store pair by default.
6145 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT);
6147 ExpandOp(Tmp, Lo, Hi);
6151 case ISD::READCYCLECOUNTER: {
6152 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
6153 TargetLowering::Custom &&
6154 "Must custom expand ReadCycleCounter");
6155 SDOperand Tmp = TLI.LowerOperation(Op, DAG);
6156 assert(Tmp.Val && "Node must be custom expanded!");
6157 ExpandOp(Tmp.getValue(0), Lo, Hi);
6158 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
6159 LegalizeOp(Tmp.getValue(1)));
6163 case ISD::ATOMIC_LCS: {
6164 SDOperand Tmp = TLI.LowerOperation(Op, DAG);
6165 assert(Tmp.Val && "Node must be custom expanded!");
6166 ExpandOp(Tmp.getValue(0), Lo, Hi);
6167 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
6168 LegalizeOp(Tmp.getValue(1)));
6174 // These operators cannot be expanded directly, emit them as calls to
6175 // library functions.
6176 case ISD::FP_TO_SINT: {
6177 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
6179 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6180 case Expand: assert(0 && "cannot expand FP!");
6181 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6182 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6185 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
6187 // Now that the custom expander is done, expand the result, which is still
6190 ExpandOp(Op, Lo, Hi);
6195 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6196 if (VT == MVT::i64) {
6197 if (Node->getOperand(0).getValueType() == MVT::f32)
6198 LC = RTLIB::FPTOSINT_F32_I64;
6199 else if (Node->getOperand(0).getValueType() == MVT::f64)
6200 LC = RTLIB::FPTOSINT_F64_I64;
6201 else if (Node->getOperand(0).getValueType() == MVT::f80)
6202 LC = RTLIB::FPTOSINT_F80_I64;
6203 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
6204 LC = RTLIB::FPTOSINT_PPCF128_I64;
6205 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6206 } else if (VT == MVT::i128) {
6207 if (Node->getOperand(0).getValueType() == MVT::f32)
6208 LC = RTLIB::FPTOSINT_F32_I128;
6209 else if (Node->getOperand(0).getValueType() == MVT::f64)
6210 LC = RTLIB::FPTOSINT_F64_I128;
6211 else if (Node->getOperand(0).getValueType() == MVT::f80)
6212 LC = RTLIB::FPTOSINT_F80_I128;
6213 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
6214 LC = RTLIB::FPTOSINT_PPCF128_I128;
6215 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6217 assert(0 && "Unexpected uint-to-fp conversion!");
6222 case ISD::FP_TO_UINT: {
6223 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
6225 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6226 case Expand: assert(0 && "cannot expand FP!");
6227 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6228 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6231 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
6233 // Now that the custom expander is done, expand the result.
6235 ExpandOp(Op, Lo, Hi);
6240 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6241 if (VT == MVT::i64) {
6242 if (Node->getOperand(0).getValueType() == MVT::f32)
6243 LC = RTLIB::FPTOUINT_F32_I64;
6244 else if (Node->getOperand(0).getValueType() == MVT::f64)
6245 LC = RTLIB::FPTOUINT_F64_I64;
6246 else if (Node->getOperand(0).getValueType() == MVT::f80)
6247 LC = RTLIB::FPTOUINT_F80_I64;
6248 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
6249 LC = RTLIB::FPTOUINT_PPCF128_I64;
6250 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6251 } else if (VT == MVT::i128) {
6252 if (Node->getOperand(0).getValueType() == MVT::f32)
6253 LC = RTLIB::FPTOUINT_F32_I128;
6254 else if (Node->getOperand(0).getValueType() == MVT::f64)
6255 LC = RTLIB::FPTOUINT_F64_I128;
6256 else if (Node->getOperand(0).getValueType() == MVT::f80)
6257 LC = RTLIB::FPTOUINT_F80_I128;
6258 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
6259 LC = RTLIB::FPTOUINT_PPCF128_I128;
6260 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6262 assert(0 && "Unexpected uint-to-fp conversion!");
6268 // If the target wants custom lowering, do so.
6269 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6270 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
6271 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
6272 Op = TLI.LowerOperation(Op, DAG);
6274 // Now that the custom expander is done, expand the result, which is
6276 ExpandOp(Op, Lo, Hi);
6281 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
6282 // this X << 1 as X+X.
6283 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
6284 if (ShAmt->getAPIntValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
6285 TLI.isOperationLegal(ISD::ADDE, NVT)) {
6286 SDOperand LoOps[2], HiOps[3];
6287 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
6288 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
6289 LoOps[1] = LoOps[0];
6290 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6292 HiOps[1] = HiOps[0];
6293 HiOps[2] = Lo.getValue(1);
6294 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6299 // If we can emit an efficient shift operation, do so now.
6300 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6303 // If this target supports SHL_PARTS, use it.
6304 TargetLowering::LegalizeAction Action =
6305 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
6306 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6307 Action == TargetLowering::Custom) {
6308 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6312 // Otherwise, emit a libcall.
6313 Lo = ExpandLibCall(RTLIB::SHL_I64, Node, false/*left shift=unsigned*/, Hi);
6318 // If the target wants custom lowering, do so.
6319 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6320 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
6321 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
6322 Op = TLI.LowerOperation(Op, DAG);
6324 // Now that the custom expander is done, expand the result, which is
6326 ExpandOp(Op, Lo, Hi);
6331 // If we can emit an efficient shift operation, do so now.
6332 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
6335 // If this target supports SRA_PARTS, use it.
6336 TargetLowering::LegalizeAction Action =
6337 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
6338 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6339 Action == TargetLowering::Custom) {
6340 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6344 // Otherwise, emit a libcall.
6345 Lo = ExpandLibCall(RTLIB::SRA_I64, Node, true/*ashr is signed*/, Hi);
6350 // If the target wants custom lowering, do so.
6351 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6352 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
6353 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
6354 Op = TLI.LowerOperation(Op, DAG);
6356 // Now that the custom expander is done, expand the result, which is
6358 ExpandOp(Op, Lo, Hi);
6363 // If we can emit an efficient shift operation, do so now.
6364 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6367 // If this target supports SRL_PARTS, use it.
6368 TargetLowering::LegalizeAction Action =
6369 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
6370 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6371 Action == TargetLowering::Custom) {
6372 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6376 // Otherwise, emit a libcall.
6377 Lo = ExpandLibCall(RTLIB::SRL_I64, Node, false/*lshr is unsigned*/, Hi);
6383 // If the target wants to custom expand this, let them.
6384 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
6385 TargetLowering::Custom) {
6386 Op = TLI.LowerOperation(Op, DAG);
6388 ExpandOp(Op, Lo, Hi);
6393 // Expand the subcomponents.
6394 SDOperand LHSL, LHSH, RHSL, RHSH;
6395 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6396 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6397 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6398 SDOperand LoOps[2], HiOps[3];
6403 if (Node->getOpcode() == ISD::ADD) {
6404 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6405 HiOps[2] = Lo.getValue(1);
6406 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6408 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6409 HiOps[2] = Lo.getValue(1);
6410 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6417 // Expand the subcomponents.
6418 SDOperand LHSL, LHSH, RHSL, RHSH;
6419 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6420 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6421 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6422 SDOperand LoOps[2] = { LHSL, RHSL };
6423 SDOperand HiOps[3] = { LHSH, RHSH };
6425 if (Node->getOpcode() == ISD::ADDC) {
6426 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6427 HiOps[2] = Lo.getValue(1);
6428 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6430 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6431 HiOps[2] = Lo.getValue(1);
6432 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6434 // Remember that we legalized the flag.
6435 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6440 // Expand the subcomponents.
6441 SDOperand LHSL, LHSH, RHSL, RHSH;
6442 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6443 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6444 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6445 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
6446 SDOperand HiOps[3] = { LHSH, RHSH };
6448 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
6449 HiOps[2] = Lo.getValue(1);
6450 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
6452 // Remember that we legalized the flag.
6453 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6457 // If the target wants to custom expand this, let them.
6458 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
6459 SDOperand New = TLI.LowerOperation(Op, DAG);
6461 ExpandOp(New, Lo, Hi);
6466 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
6467 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
6468 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
6469 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
6470 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
6471 SDOperand LL, LH, RL, RH;
6472 ExpandOp(Node->getOperand(0), LL, LH);
6473 ExpandOp(Node->getOperand(1), RL, RH);
6474 unsigned OuterBitSize = Op.getValueSizeInBits();
6475 unsigned InnerBitSize = RH.getValueSizeInBits();
6476 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
6477 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
6478 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
6479 if (DAG.MaskedValueIsZero(Node->getOperand(0), HighMask) &&
6480 DAG.MaskedValueIsZero(Node->getOperand(1), HighMask)) {
6481 // The inputs are both zero-extended.
6483 // We can emit a umul_lohi.
6484 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6485 Hi = SDOperand(Lo.Val, 1);
6489 // We can emit a mulhu+mul.
6490 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6491 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6495 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
6496 // The input values are both sign-extended.
6498 // We can emit a smul_lohi.
6499 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6500 Hi = SDOperand(Lo.Val, 1);
6504 // We can emit a mulhs+mul.
6505 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6506 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
6511 // Lo,Hi = umul LHS, RHS.
6512 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
6513 DAG.getVTList(NVT, NVT), LL, RL);
6515 Hi = UMulLOHI.getValue(1);
6516 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6517 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6518 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6519 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6523 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6524 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6525 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6526 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6527 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6528 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6533 // If nothing else, we can make a libcall.
6534 Lo = ExpandLibCall(RTLIB::MUL_I64, Node, false/*sign irrelevant*/, Hi);
6538 Lo = ExpandLibCall(RTLIB::SDIV_I64, Node, true, Hi);
6541 Lo = ExpandLibCall(RTLIB::UDIV_I64, Node, true, Hi);
6544 Lo = ExpandLibCall(RTLIB::SREM_I64, Node, true, Hi);
6547 Lo = ExpandLibCall(RTLIB::UREM_I64, Node, true, Hi);
6551 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::ADD_F32,
6554 RTLIB::ADD_PPCF128),
6558 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::SUB_F32,
6561 RTLIB::SUB_PPCF128),
6565 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::MUL_F32,
6568 RTLIB::MUL_PPCF128),
6572 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::DIV_F32,
6575 RTLIB::DIV_PPCF128),
6578 case ISD::FP_EXTEND:
6579 if (VT == MVT::ppcf128) {
6580 assert(Node->getOperand(0).getValueType()==MVT::f32 ||
6581 Node->getOperand(0).getValueType()==MVT::f64);
6582 const uint64_t zero = 0;
6583 if (Node->getOperand(0).getValueType()==MVT::f32)
6584 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0));
6586 Hi = Node->getOperand(0);
6587 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6590 Lo = ExpandLibCall(RTLIB::FPEXT_F32_F64, Node, true, Hi);
6593 Lo = ExpandLibCall(RTLIB::FPROUND_F64_F32, Node, true, Hi);
6596 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::POWI_F32,
6599 RTLIB::POWI_PPCF128),
6605 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6606 switch(Node->getOpcode()) {
6608 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
6609 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
6612 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
6613 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
6616 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
6617 RTLIB::COS_F80, RTLIB::COS_PPCF128);
6619 default: assert(0 && "Unreachable!");
6621 Lo = ExpandLibCall(LC, Node, false, Hi);
6625 if (VT == MVT::ppcf128) {
6627 ExpandOp(Node->getOperand(0), Lo, Tmp);
6628 Hi = DAG.getNode(ISD::FABS, NVT, Tmp);
6629 // lo = hi==fabs(hi) ? lo : -lo;
6630 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp,
6631 Lo, DAG.getNode(ISD::FNEG, NVT, Lo),
6632 DAG.getCondCode(ISD::SETEQ));
6635 SDOperand Mask = (VT == MVT::f64)
6636 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
6637 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
6638 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6639 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6640 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
6641 if (getTypeAction(NVT) == Expand)
6642 ExpandOp(Lo, Lo, Hi);
6646 if (VT == MVT::ppcf128) {
6647 ExpandOp(Node->getOperand(0), Lo, Hi);
6648 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo);
6649 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi);
6652 SDOperand Mask = (VT == MVT::f64)
6653 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
6654 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
6655 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6656 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6657 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
6658 if (getTypeAction(NVT) == Expand)
6659 ExpandOp(Lo, Lo, Hi);
6662 case ISD::FCOPYSIGN: {
6663 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
6664 if (getTypeAction(NVT) == Expand)
6665 ExpandOp(Lo, Lo, Hi);
6668 case ISD::SINT_TO_FP:
6669 case ISD::UINT_TO_FP: {
6670 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
6671 MVT::ValueType SrcVT = Node->getOperand(0).getValueType();
6673 // Promote the operand if needed. Do this before checking for
6674 // ppcf128 so conversions of i16 and i8 work.
6675 if (getTypeAction(SrcVT) == Promote) {
6676 SDOperand Tmp = PromoteOp(Node->getOperand(0));
6678 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
6679 DAG.getValueType(SrcVT))
6680 : DAG.getZeroExtendInReg(Tmp, SrcVT);
6681 Node = DAG.UpdateNodeOperands(Op, Tmp).Val;
6682 SrcVT = Node->getOperand(0).getValueType();
6685 if (VT == MVT::ppcf128 && SrcVT == MVT::i32) {
6686 static const uint64_t zero = 0;
6688 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6689 Node->getOperand(0)));
6690 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6692 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
6693 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6694 Node->getOperand(0)));
6695 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6696 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6697 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
6698 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6699 DAG.getConstant(0, MVT::i32),
6700 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6702 APFloat(APInt(128, 2, TwoE32)),
6705 DAG.getCondCode(ISD::SETLT)),
6710 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) {
6711 // si64->ppcf128 done by libcall, below
6712 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
6713 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)),
6715 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6716 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
6717 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6718 DAG.getConstant(0, MVT::i64),
6719 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6721 APFloat(APInt(128, 2, TwoE64)),
6724 DAG.getCondCode(ISD::SETLT)),
6729 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
6730 Node->getOperand(0));
6731 if (getTypeAction(Lo.getValueType()) == Expand)
6732 // float to i32 etc. can be 'expanded' to a single node.
6733 ExpandOp(Lo, Lo, Hi);
6738 // Make sure the resultant values have been legalized themselves, unless this
6739 // is a type that requires multi-step expansion.
6740 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
6741 Lo = LegalizeOp(Lo);
6743 // Don't legalize the high part if it is expanded to a single node.
6744 Hi = LegalizeOp(Hi);
6747 // Remember in a map if the values will be reused later.
6748 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi)));
6749 assert(isNew && "Value already expanded?!?");
6752 /// SplitVectorOp - Given an operand of vector type, break it down into
6753 /// two smaller values, still of vector type.
6754 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
6756 assert(MVT::isVector(Op.getValueType()) && "Cannot split non-vector type!");
6757 SDNode *Node = Op.Val;
6758 unsigned NumElements = MVT::getVectorNumElements(Op.getValueType());
6759 assert(NumElements > 1 && "Cannot split a single element vector!");
6761 MVT::ValueType NewEltVT = MVT::getVectorElementType(Op.getValueType());
6763 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
6764 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
6766 MVT::ValueType NewVT_Lo = MVT::getVectorType(NewEltVT, NewNumElts_Lo);
6767 MVT::ValueType NewVT_Hi = MVT::getVectorType(NewEltVT, NewNumElts_Hi);
6769 // See if we already split it.
6770 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
6771 = SplitNodes.find(Op);
6772 if (I != SplitNodes.end()) {
6773 Lo = I->second.first;
6774 Hi = I->second.second;
6778 switch (Node->getOpcode()) {
6783 assert(0 && "Unhandled operation in SplitVectorOp!");
6785 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo);
6786 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi);
6788 case ISD::BUILD_PAIR:
6789 Lo = Node->getOperand(0);
6790 Hi = Node->getOperand(1);
6792 case ISD::INSERT_VECTOR_ELT: {
6793 if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) {
6794 SplitVectorOp(Node->getOperand(0), Lo, Hi);
6795 unsigned Index = Idx->getValue();
6796 SDOperand ScalarOp = Node->getOperand(1);
6797 if (Index < NewNumElts_Lo)
6798 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp,
6799 DAG.getIntPtrConstant(Index));
6801 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp,
6802 DAG.getIntPtrConstant(Index - NewNumElts_Lo));
6805 SDOperand Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0),
6806 Node->getOperand(1),
6807 Node->getOperand(2));
6808 SplitVectorOp(Tmp, Lo, Hi);
6811 case ISD::VECTOR_SHUFFLE: {
6812 // Build the low part.
6813 SDOperand Mask = Node->getOperand(2);
6814 SmallVector<SDOperand, 8> Ops;
6815 MVT::ValueType PtrVT = TLI.getPointerTy();
6817 // Insert all of the elements from the input that are needed. We use
6818 // buildvector of extractelement here because the input vectors will have
6819 // to be legalized, so this makes the code simpler.
6820 for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
6821 SDOperand IdxNode = Mask.getOperand(i);
6822 if (IdxNode.getOpcode() == ISD::UNDEF) {
6823 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
6826 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getValue();
6827 SDOperand InVec = Node->getOperand(0);
6828 if (Idx >= NumElements) {
6829 InVec = Node->getOperand(1);
6832 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6833 DAG.getConstant(Idx, PtrVT)));
6835 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6838 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
6839 SDOperand IdxNode = Mask.getOperand(i);
6840 if (IdxNode.getOpcode() == ISD::UNDEF) {
6841 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
6844 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getValue();
6845 SDOperand InVec = Node->getOperand(0);
6846 if (Idx >= NumElements) {
6847 InVec = Node->getOperand(1);
6850 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6851 DAG.getConstant(Idx, PtrVT)));
6853 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6856 case ISD::BUILD_VECTOR: {
6857 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
6858 Node->op_begin()+NewNumElts_Lo);
6859 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size());
6861 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
6863 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size());
6866 case ISD::CONCAT_VECTORS: {
6867 // FIXME: Handle non-power-of-two vectors?
6868 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
6869 if (NewNumSubvectors == 1) {
6870 Lo = Node->getOperand(0);
6871 Hi = Node->getOperand(1);
6873 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
6874 Node->op_begin()+NewNumSubvectors);
6875 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size());
6877 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors,
6879 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size());
6884 SDOperand Cond = Node->getOperand(0);
6886 SDOperand LL, LH, RL, RH;
6887 SplitVectorOp(Node->getOperand(1), LL, LH);
6888 SplitVectorOp(Node->getOperand(2), RL, RH);
6890 if (MVT::isVector(Cond.getValueType())) {
6891 // Handle a vector merge.
6893 SplitVectorOp(Cond, CL, CH);
6894 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL);
6895 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH);
6897 // Handle a simple select with vector operands.
6898 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL);
6899 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH);
6904 SDOperand LL, LH, RL, RH;
6905 SplitVectorOp(Node->getOperand(0), LL, LH);
6906 SplitVectorOp(Node->getOperand(1), RL, RH);
6907 Lo = DAG.getNode(ISD::VSETCC, NewVT_Lo, LL, RL, Node->getOperand(2));
6908 Hi = DAG.getNode(ISD::VSETCC, NewVT_Hi, LH, RH, Node->getOperand(2));
6927 SDOperand LL, LH, RL, RH;
6928 SplitVectorOp(Node->getOperand(0), LL, LH);
6929 SplitVectorOp(Node->getOperand(1), RL, RH);
6931 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL);
6932 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH);
6937 SplitVectorOp(Node->getOperand(0), L, H);
6939 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1));
6940 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1));
6951 case ISD::FP_TO_SINT:
6952 case ISD::FP_TO_UINT:
6953 case ISD::SINT_TO_FP:
6954 case ISD::UINT_TO_FP: {
6956 SplitVectorOp(Node->getOperand(0), L, H);
6958 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L);
6959 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H);
6963 LoadSDNode *LD = cast<LoadSDNode>(Node);
6964 SDOperand Ch = LD->getChain();
6965 SDOperand Ptr = LD->getBasePtr();
6966 const Value *SV = LD->getSrcValue();
6967 int SVOffset = LD->getSrcValueOffset();
6968 unsigned Alignment = LD->getAlignment();
6969 bool isVolatile = LD->isVolatile();
6971 Lo = DAG.getLoad(NewVT_Lo, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
6972 unsigned IncrementSize = NewNumElts_Lo * MVT::getSizeInBits(NewEltVT)/8;
6973 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
6974 DAG.getIntPtrConstant(IncrementSize));
6975 SVOffset += IncrementSize;
6976 Alignment = MinAlign(Alignment, IncrementSize);
6977 Hi = DAG.getLoad(NewVT_Hi, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
6979 // Build a factor node to remember that this load is independent of the
6981 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
6984 // Remember that we legalized the chain.
6985 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
6988 case ISD::BIT_CONVERT: {
6989 // We know the result is a vector. The input may be either a vector or a
6991 SDOperand InOp = Node->getOperand(0);
6992 if (!MVT::isVector(InOp.getValueType()) ||
6993 MVT::getVectorNumElements(InOp.getValueType()) == 1) {
6994 // The input is a scalar or single-element vector.
6995 // Lower to a store/load so that it can be split.
6996 // FIXME: this could be improved probably.
6997 SDOperand Ptr = DAG.CreateStackTemporary(InOp.getValueType());
6998 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(Ptr.Val);
7000 SDOperand St = DAG.getStore(DAG.getEntryNode(),
7002 PseudoSourceValue::getFixedStack(),
7004 InOp = DAG.getLoad(Op.getValueType(), St, Ptr,
7005 PseudoSourceValue::getFixedStack(),
7008 // Split the vector and convert each of the pieces now.
7009 SplitVectorOp(InOp, Lo, Hi);
7010 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo);
7011 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi);
7016 // Remember in a map if the values will be reused later.
7018 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
7019 assert(isNew && "Value already split?!?");
7023 /// ScalarizeVectorOp - Given an operand of single-element vector type
7024 /// (e.g. v1f32), convert it into the equivalent operation that returns a
7025 /// scalar (e.g. f32) value.
7026 SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) {
7027 assert(MVT::isVector(Op.getValueType()) &&
7028 "Bad ScalarizeVectorOp invocation!");
7029 SDNode *Node = Op.Val;
7030 MVT::ValueType NewVT = MVT::getVectorElementType(Op.getValueType());
7031 assert(MVT::getVectorNumElements(Op.getValueType()) == 1);
7033 // See if we already scalarized it.
7034 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op);
7035 if (I != ScalarizedNodes.end()) return I->second;
7038 switch (Node->getOpcode()) {
7041 Node->dump(&DAG); cerr << "\n";
7043 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
7060 Result = DAG.getNode(Node->getOpcode(),
7062 ScalarizeVectorOp(Node->getOperand(0)),
7063 ScalarizeVectorOp(Node->getOperand(1)));
7070 Result = DAG.getNode(Node->getOpcode(),
7072 ScalarizeVectorOp(Node->getOperand(0)));
7075 Result = DAG.getNode(Node->getOpcode(),
7077 ScalarizeVectorOp(Node->getOperand(0)),
7078 Node->getOperand(1));
7081 LoadSDNode *LD = cast<LoadSDNode>(Node);
7082 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
7083 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
7085 const Value *SV = LD->getSrcValue();
7086 int SVOffset = LD->getSrcValueOffset();
7087 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset,
7088 LD->isVolatile(), LD->getAlignment());
7090 // Remember that we legalized the chain.
7091 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
7094 case ISD::BUILD_VECTOR:
7095 Result = Node->getOperand(0);
7097 case ISD::INSERT_VECTOR_ELT:
7098 // Returning the inserted scalar element.
7099 Result = Node->getOperand(1);
7101 case ISD::CONCAT_VECTORS:
7102 assert(Node->getOperand(0).getValueType() == NewVT &&
7103 "Concat of non-legal vectors not yet supported!");
7104 Result = Node->getOperand(0);
7106 case ISD::VECTOR_SHUFFLE: {
7107 // Figure out if the scalar is the LHS or RHS and return it.
7108 SDOperand EltNum = Node->getOperand(2).getOperand(0);
7109 if (cast<ConstantSDNode>(EltNum)->getValue())
7110 Result = ScalarizeVectorOp(Node->getOperand(1));
7112 Result = ScalarizeVectorOp(Node->getOperand(0));
7115 case ISD::EXTRACT_SUBVECTOR:
7116 Result = Node->getOperand(0);
7117 assert(Result.getValueType() == NewVT);
7119 case ISD::BIT_CONVERT: {
7120 SDOperand Op0 = Op.getOperand(0);
7121 if (MVT::getVectorNumElements(Op0.getValueType()) == 1)
7122 Op0 = ScalarizeVectorOp(Op0);
7123 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op0);
7127 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
7128 ScalarizeVectorOp(Op.getOperand(1)),
7129 ScalarizeVectorOp(Op.getOperand(2)));
7132 SDOperand Op0 = ScalarizeVectorOp(Op.getOperand(0));
7133 SDOperand Op1 = ScalarizeVectorOp(Op.getOperand(1));
7134 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Op0), Op0, Op1,
7136 Result = DAG.getNode(ISD::SELECT, NewVT, Result,
7137 DAG.getConstant(-1ULL, NewVT),
7138 DAG.getConstant(0ULL, NewVT));
7143 if (TLI.isTypeLegal(NewVT))
7144 Result = LegalizeOp(Result);
7145 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
7146 assert(isNew && "Value already scalarized?");
7151 // SelectionDAG::Legalize - This is the entry point for the file.
7153 void SelectionDAG::Legalize() {
7154 if (ViewLegalizeDAGs) viewGraph();
7156 /// run - This is the main entry point to this class.
7158 SelectionDAGLegalize(*this).LegalizeDAG();