1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/CodeGen/PseudoSourceValue.h"
20 #include "llvm/Target/TargetFrameInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/Target/TargetData.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/Target/TargetSubtarget.h"
26 #include "llvm/CallingConv.h"
27 #include "llvm/Constants.h"
28 #include "llvm/DerivedTypes.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Compiler.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/ADT/DenseMap.h"
33 #include "llvm/ADT/SmallVector.h"
34 #include "llvm/ADT/SmallPtrSet.h"
38 //===----------------------------------------------------------------------===//
39 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
40 /// hacks on it until the target machine can handle it. This involves
41 /// eliminating value sizes the machine cannot handle (promoting small sizes to
42 /// large sizes or splitting up large values into small values) as well as
43 /// eliminating operations the machine cannot handle.
45 /// This code also does a small amount of optimization and recognition of idioms
46 /// as part of its processing. For example, if a target does not support a
47 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
48 /// will attempt merge setcc and brc instructions into brcc's.
51 class VISIBILITY_HIDDEN SelectionDAGLegalize {
55 // Libcall insertion helpers.
57 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
58 /// legalized. We use this to ensure that calls are properly serialized
59 /// against each other, including inserted libcalls.
60 SDValue LastCALLSEQ_END;
62 /// IsLegalizingCall - This member is used *only* for purposes of providing
63 /// helpful assertions that a libcall isn't created while another call is
64 /// being legalized (which could lead to non-serialized call sequences).
65 bool IsLegalizingCall;
68 Legal, // The target natively supports this operation.
69 Promote, // This operation should be executed in a larger type.
70 Expand // Try to expand this to other ops, otherwise use a libcall.
73 /// ValueTypeActions - This is a bitvector that contains two bits for each
74 /// value type, where the two bits correspond to the LegalizeAction enum.
75 /// This can be queried with "getTypeAction(VT)".
76 TargetLowering::ValueTypeActionImpl ValueTypeActions;
78 /// LegalizedNodes - For nodes that are of legal width, and that have more
79 /// than one use, this map indicates what regularized operand to use. This
80 /// allows us to avoid legalizing the same thing more than once.
81 DenseMap<SDValue, SDValue> LegalizedNodes;
83 /// PromotedNodes - For nodes that are below legal width, and that have more
84 /// than one use, this map indicates what promoted value to use. This allows
85 /// us to avoid promoting the same thing more than once.
86 DenseMap<SDValue, SDValue> PromotedNodes;
88 /// ExpandedNodes - For nodes that need to be expanded this map indicates
89 /// which which operands are the expanded version of the input. This allows
90 /// us to avoid expanding the same node more than once.
91 DenseMap<SDValue, std::pair<SDValue, SDValue> > ExpandedNodes;
93 /// SplitNodes - For vector nodes that need to be split, this map indicates
94 /// which which operands are the split version of the input. This allows us
95 /// to avoid splitting the same node more than once.
96 std::map<SDValue, std::pair<SDValue, SDValue> > SplitNodes;
98 /// ScalarizedNodes - For nodes that need to be converted from vector types to
99 /// scalar types, this contains the mapping of ones we have already
100 /// processed to the result.
101 std::map<SDValue, SDValue> ScalarizedNodes;
103 void AddLegalizedOperand(SDValue From, SDValue To) {
104 LegalizedNodes.insert(std::make_pair(From, To));
105 // If someone requests legalization of the new node, return itself.
107 LegalizedNodes.insert(std::make_pair(To, To));
109 void AddPromotedOperand(SDValue From, SDValue To) {
110 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
111 assert(isNew && "Got into the map somehow?");
112 // If someone requests legalization of the new node, return itself.
113 LegalizedNodes.insert(std::make_pair(To, To));
117 explicit SelectionDAGLegalize(SelectionDAG &DAG);
119 /// getTypeAction - Return how we should legalize values of this type, either
120 /// it is already legal or we need to expand it into multiple registers of
121 /// smaller integer type, or we need to promote it to a larger type.
122 LegalizeAction getTypeAction(MVT VT) const {
123 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
126 /// isTypeLegal - Return true if this type is legal on this target.
128 bool isTypeLegal(MVT VT) const {
129 return getTypeAction(VT) == Legal;
135 /// HandleOp - Legalize, Promote, or Expand the specified operand as
136 /// appropriate for its type.
137 void HandleOp(SDValue Op);
139 /// LegalizeOp - We know that the specified value has a legal type.
140 /// Recursively ensure that the operands have legal types, then return the
142 SDValue LegalizeOp(SDValue O);
144 /// UnrollVectorOp - We know that the given vector has a legal type, however
145 /// the operation it performs is not legal and is an operation that we have
146 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
147 /// operating on each element individually.
148 SDValue UnrollVectorOp(SDValue O);
150 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
151 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
152 /// is necessary to spill the vector being inserted into to memory, perform
153 /// the insert there, and then read the result back.
154 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
157 /// PromoteOp - Given an operation that produces a value in an invalid type,
158 /// promote it to compute the value into a larger type. The produced value
159 /// will have the correct bits for the low portion of the register, but no
160 /// guarantee is made about the top bits: it may be zero, sign-extended, or
162 SDValue PromoteOp(SDValue O);
164 /// ExpandOp - Expand the specified SDValue into its two component pieces
165 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
166 /// the LegalizeNodes map is filled in for any results that are not expanded,
167 /// the ExpandedNodes map is filled in for any results that are expanded, and
168 /// the Lo/Hi values are returned. This applies to integer types and Vector
170 void ExpandOp(SDValue O, SDValue &Lo, SDValue &Hi);
172 /// SplitVectorOp - Given an operand of vector type, break it down into
173 /// two smaller values.
174 void SplitVectorOp(SDValue O, SDValue &Lo, SDValue &Hi);
176 /// ScalarizeVectorOp - Given an operand of single-element vector type
177 /// (e.g. v1f32), convert it into the equivalent operation that returns a
178 /// scalar (e.g. f32) value.
179 SDValue ScalarizeVectorOp(SDValue O);
181 /// isShuffleLegal - Return non-null if a vector shuffle is legal with the
182 /// specified mask and type. Targets can specify exactly which masks they
183 /// support and the code generator is tasked with not creating illegal masks.
185 /// Note that this will also return true for shuffles that are promoted to a
188 /// If this is a legal shuffle, this method returns the (possibly promoted)
189 /// build_vector Mask. If it's not a legal shuffle, it returns null.
190 SDNode *isShuffleLegal(MVT VT, SDValue Mask) const;
192 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
193 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
195 void LegalizeSetCCOperands(SDValue &LHS, SDValue &RHS, SDValue &CC);
197 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned,
199 SDValue ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source);
201 SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT);
202 SDValue ExpandBUILD_VECTOR(SDNode *Node);
203 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
204 SDValue LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op);
205 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT);
206 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, bool isSigned);
207 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned);
209 SDValue ExpandBSWAP(SDValue Op);
210 SDValue ExpandBitCount(unsigned Opc, SDValue Op);
211 bool ExpandShift(unsigned Opc, SDValue Op, SDValue Amt,
212 SDValue &Lo, SDValue &Hi);
213 void ExpandShiftParts(unsigned NodeOp, SDValue Op, SDValue Amt,
214 SDValue &Lo, SDValue &Hi);
216 SDValue ExpandEXTRACT_SUBVECTOR(SDValue Op);
217 SDValue ExpandEXTRACT_VECTOR_ELT(SDValue Op);
221 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
222 /// specified mask and type. Targets can specify exactly which masks they
223 /// support and the code generator is tasked with not creating illegal masks.
225 /// Note that this will also return true for shuffles that are promoted to a
227 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDValue Mask) const {
228 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
230 case TargetLowering::Legal:
231 case TargetLowering::Custom:
233 case TargetLowering::Promote: {
234 // If this is promoted to a different type, convert the shuffle mask and
235 // ask if it is legal in the promoted type!
236 MVT NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
237 MVT EltVT = NVT.getVectorElementType();
239 // If we changed # elements, change the shuffle mask.
240 unsigned NumEltsGrowth =
241 NVT.getVectorNumElements() / VT.getVectorNumElements();
242 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
243 if (NumEltsGrowth > 1) {
244 // Renumber the elements.
245 SmallVector<SDValue, 8> Ops;
246 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
247 SDValue InOp = Mask.getOperand(i);
248 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
249 if (InOp.getOpcode() == ISD::UNDEF)
250 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
252 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
253 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, EltVT));
257 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
263 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
266 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
267 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
268 ValueTypeActions(TLI.getValueTypeActions()) {
269 assert(MVT::LAST_VALUETYPE <= 32 &&
270 "Too many value types for ValueTypeActions to hold!");
273 /// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order
274 /// contains all of a nodes operands before it contains the node.
275 static void ComputeTopDownOrdering(SelectionDAG &DAG,
276 SmallVector<SDNode*, 64> &Order) {
278 DenseMap<SDNode*, unsigned> Visited;
279 std::vector<SDNode*> Worklist;
280 Worklist.reserve(128);
282 // Compute ordering from all of the leaves in the graphs, those (like the
283 // entry node) that have no operands.
284 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
285 E = DAG.allnodes_end(); I != E; ++I) {
286 if (I->getNumOperands() == 0) {
288 Worklist.push_back(I);
292 while (!Worklist.empty()) {
293 SDNode *N = Worklist.back();
296 if (++Visited[N] != N->getNumOperands())
297 continue; // Haven't visited all operands yet
301 // Now that we have N in, add anything that uses it if all of their operands
303 Worklist.insert(Worklist.end(), N->use_begin(), N->use_end());
306 assert(Order.size() == Visited.size() &&
307 Order.size() == DAG.allnodes_size() &&
308 "Error: DAG is cyclic!");
312 void SelectionDAGLegalize::LegalizeDAG() {
313 LastCALLSEQ_END = DAG.getEntryNode();
314 IsLegalizingCall = false;
316 // The legalize process is inherently a bottom-up recursive process (users
317 // legalize their uses before themselves). Given infinite stack space, we
318 // could just start legalizing on the root and traverse the whole graph. In
319 // practice however, this causes us to run out of stack space on large basic
320 // blocks. To avoid this problem, compute an ordering of the nodes where each
321 // node is only legalized after all of its operands are legalized.
322 SmallVector<SDNode*, 64> Order;
323 ComputeTopDownOrdering(DAG, Order);
325 for (unsigned i = 0, e = Order.size(); i != e; ++i)
326 HandleOp(SDValue(Order[i], 0));
328 // Finally, it's possible the root changed. Get the new root.
329 SDValue OldRoot = DAG.getRoot();
330 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
331 DAG.setRoot(LegalizedNodes[OldRoot]);
333 ExpandedNodes.clear();
334 LegalizedNodes.clear();
335 PromotedNodes.clear();
337 ScalarizedNodes.clear();
339 // Remove dead nodes now.
340 DAG.RemoveDeadNodes();
344 /// FindCallEndFromCallStart - Given a chained node that is part of a call
345 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
346 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
347 if (Node->getOpcode() == ISD::CALLSEQ_END)
349 if (Node->use_empty())
350 return 0; // No CallSeqEnd
352 // The chain is usually at the end.
353 SDValue TheChain(Node, Node->getNumValues()-1);
354 if (TheChain.getValueType() != MVT::Other) {
355 // Sometimes it's at the beginning.
356 TheChain = SDValue(Node, 0);
357 if (TheChain.getValueType() != MVT::Other) {
358 // Otherwise, hunt for it.
359 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
360 if (Node->getValueType(i) == MVT::Other) {
361 TheChain = SDValue(Node, i);
365 // Otherwise, we walked into a node without a chain.
366 if (TheChain.getValueType() != MVT::Other)
371 for (SDNode::use_iterator UI = Node->use_begin(),
372 E = Node->use_end(); UI != E; ++UI) {
374 // Make sure to only follow users of our token chain.
376 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
377 if (User->getOperand(i) == TheChain)
378 if (SDNode *Result = FindCallEndFromCallStart(User))
384 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
385 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
386 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
387 assert(Node && "Didn't find callseq_start for a call??");
388 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
390 assert(Node->getOperand(0).getValueType() == MVT::Other &&
391 "Node doesn't have a token chain argument!");
392 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
395 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
396 /// see if any uses can reach Dest. If no dest operands can get to dest,
397 /// legalize them, legalize ourself, and return false, otherwise, return true.
399 /// Keep track of the nodes we fine that actually do lead to Dest in
400 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
402 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
403 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
404 if (N == Dest) return true; // N certainly leads to Dest :)
406 // If we've already processed this node and it does lead to Dest, there is no
407 // need to reprocess it.
408 if (NodesLeadingTo.count(N)) return true;
410 // If the first result of this node has been already legalized, then it cannot
412 switch (getTypeAction(N->getValueType(0))) {
414 if (LegalizedNodes.count(SDValue(N, 0))) return false;
417 if (PromotedNodes.count(SDValue(N, 0))) return false;
420 if (ExpandedNodes.count(SDValue(N, 0))) return false;
424 // Okay, this node has not already been legalized. Check and legalize all
425 // operands. If none lead to Dest, then we can legalize this node.
426 bool OperandsLeadToDest = false;
427 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
428 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
429 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
431 if (OperandsLeadToDest) {
432 NodesLeadingTo.insert(N);
436 // Okay, this node looks safe, legalize it and return false.
437 HandleOp(SDValue(N, 0));
441 /// HandleOp - Legalize, Promote, or Expand the specified operand as
442 /// appropriate for its type.
443 void SelectionDAGLegalize::HandleOp(SDValue Op) {
444 MVT VT = Op.getValueType();
445 switch (getTypeAction(VT)) {
446 default: assert(0 && "Bad type action!");
447 case Legal: (void)LegalizeOp(Op); break;
448 case Promote: (void)PromoteOp(Op); break;
450 if (!VT.isVector()) {
451 // If this is an illegal scalar, expand it into its two component
454 if (Op.getOpcode() == ISD::TargetConstant)
455 break; // Allow illegal target nodes.
457 } else if (VT.getVectorNumElements() == 1) {
458 // If this is an illegal single element vector, convert it to a
460 (void)ScalarizeVectorOp(Op);
462 // Otherwise, this is an illegal multiple element vector.
463 // Split it in half and legalize both parts.
465 SplitVectorOp(Op, X, Y);
471 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
472 /// a load from the constant pool.
473 static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
474 SelectionDAG &DAG, TargetLowering &TLI) {
477 // If a FP immediate is precise when represented as a float and if the
478 // target can do an extending load from float to double, we put it into
479 // the constant pool as a float, even if it's is statically typed as a
480 // double. This shrinks FP constants and canonicalizes them for targets where
481 // an FP extending load is the same cost as a normal load (such as on the x87
482 // fp stack or PPC FP unit).
483 MVT VT = CFP->getValueType(0);
484 ConstantFP *LLVMC = ConstantFP::get(CFP->getValueAPF());
486 if (VT!=MVT::f64 && VT!=MVT::f32)
487 assert(0 && "Invalid type expansion");
488 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt(),
489 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
494 while (SVT != MVT::f32) {
495 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1);
496 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
497 // Only do this if the target has a native EXTLOAD instruction from
499 TLI.isLoadXLegal(ISD::EXTLOAD, SVT) &&
500 TLI.ShouldShrinkFPConstant(OrigVT)) {
501 const Type *SType = SVT.getTypeForMVT();
502 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
508 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
510 return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, DAG.getEntryNode(),
511 CPIdx, PseudoSourceValue::getConstantPool(),
513 return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx,
514 PseudoSourceValue::getConstantPool(), 0);
518 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
521 SDValue ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT,
522 SelectionDAG &DAG, TargetLowering &TLI) {
523 MVT VT = Node->getValueType(0);
524 MVT SrcVT = Node->getOperand(1).getValueType();
525 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
526 "fcopysign expansion only supported for f32 and f64");
527 MVT SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
529 // First get the sign bit of second operand.
530 SDValue Mask1 = (SrcVT == MVT::f64)
531 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
532 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
533 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
534 SDValue SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
535 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
536 // Shift right or sign-extend it if the two operands have different types.
537 int SizeDiff = SrcNVT.getSizeInBits() - NVT.getSizeInBits();
539 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
540 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
541 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
542 } else if (SizeDiff < 0) {
543 SignBit = DAG.getNode(ISD::ZERO_EXTEND, NVT, SignBit);
544 SignBit = DAG.getNode(ISD::SHL, NVT, SignBit,
545 DAG.getConstant(-SizeDiff, TLI.getShiftAmountTy()));
548 // Clear the sign bit of first operand.
549 SDValue Mask2 = (VT == MVT::f64)
550 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
551 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
552 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
553 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
554 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
556 // Or the value with the sign bit.
557 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
561 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
563 SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
564 TargetLowering &TLI) {
565 SDValue Chain = ST->getChain();
566 SDValue Ptr = ST->getBasePtr();
567 SDValue Val = ST->getValue();
568 MVT VT = Val.getValueType();
569 int Alignment = ST->getAlignment();
570 int SVOffset = ST->getSrcValueOffset();
571 if (ST->getMemoryVT().isFloatingPoint() ||
572 ST->getMemoryVT().isVector()) {
573 // Expand to a bitconvert of the value to the integer type of the
574 // same size, then a (misaligned) int store.
576 if (VT.is128BitVector() || VT == MVT::ppcf128 || VT == MVT::f128)
578 else if (VT.is64BitVector() || VT==MVT::f64)
580 else if (VT==MVT::f32)
583 assert(0 && "Unaligned store of unsupported type");
585 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val);
586 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(),
587 SVOffset, ST->isVolatile(), Alignment);
589 assert(ST->getMemoryVT().isInteger() &&
590 !ST->getMemoryVT().isVector() &&
591 "Unaligned store of unknown type.");
592 // Get the half-size VT
594 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1);
595 int NumBits = NewStoredVT.getSizeInBits();
596 int IncrementSize = NumBits / 8;
598 // Divide the stored value in two parts.
599 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
601 SDValue Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
603 // Store the two parts
604 SDValue Store1, Store2;
605 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr,
606 ST->getSrcValue(), SVOffset, NewStoredVT,
607 ST->isVolatile(), Alignment);
608 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
609 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
610 Alignment = MinAlign(Alignment, IncrementSize);
611 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr,
612 ST->getSrcValue(), SVOffset + IncrementSize,
613 NewStoredVT, ST->isVolatile(), Alignment);
615 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2);
618 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
620 SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
621 TargetLowering &TLI) {
622 int SVOffset = LD->getSrcValueOffset();
623 SDValue Chain = LD->getChain();
624 SDValue Ptr = LD->getBasePtr();
625 MVT VT = LD->getValueType(0);
626 MVT LoadedVT = LD->getMemoryVT();
627 if (VT.isFloatingPoint() || VT.isVector()) {
628 // Expand to a (misaligned) integer load of the same size,
629 // then bitconvert to floating point or vector.
631 if (LoadedVT.is128BitVector() ||
632 LoadedVT == MVT::ppcf128 || LoadedVT == MVT::f128)
634 else if (LoadedVT.is64BitVector() || LoadedVT == MVT::f64)
636 else if (LoadedVT == MVT::f32)
639 assert(0 && "Unaligned load of unsupported type");
641 SDValue newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(),
642 SVOffset, LD->isVolatile(),
644 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad);
645 if (VT.isFloatingPoint() && LoadedVT != VT)
646 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result);
648 SDValue Ops[] = { Result, Chain };
649 return DAG.getMergeValues(Ops, 2);
651 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
652 "Unaligned load of unsupported type.");
654 // Compute the new VT that is half the size of the old one. This is an
656 unsigned NumBits = LoadedVT.getSizeInBits();
658 NewLoadedVT = MVT::getIntegerVT(NumBits/2);
661 unsigned Alignment = LD->getAlignment();
662 unsigned IncrementSize = NumBits / 8;
663 ISD::LoadExtType HiExtType = LD->getExtensionType();
665 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
666 if (HiExtType == ISD::NON_EXTLOAD)
667 HiExtType = ISD::ZEXTLOAD;
669 // Load the value in two parts
671 if (TLI.isLittleEndian()) {
672 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
673 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
674 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
675 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
676 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(),
677 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
678 MinAlign(Alignment, IncrementSize));
680 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset,
681 NewLoadedVT,LD->isVolatile(), Alignment);
682 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
683 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
684 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
685 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
686 MinAlign(Alignment, IncrementSize));
689 // aggregate the two parts
690 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
691 SDValue Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
692 Result = DAG.getNode(ISD::OR, VT, Result, Lo);
694 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
697 SDValue Ops[] = { Result, TF };
698 return DAG.getMergeValues(Ops, 2);
701 /// UnrollVectorOp - We know that the given vector has a legal type, however
702 /// the operation it performs is not legal and is an operation that we have
703 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
704 /// operating on each element individually.
705 SDValue SelectionDAGLegalize::UnrollVectorOp(SDValue Op) {
706 MVT VT = Op.getValueType();
707 assert(isTypeLegal(VT) &&
708 "Caller should expand or promote operands that are not legal!");
709 assert(Op.Val->getNumValues() == 1 &&
710 "Can't unroll a vector with multiple results!");
711 unsigned NE = VT.getVectorNumElements();
712 MVT EltVT = VT.getVectorElementType();
714 SmallVector<SDValue, 8> Scalars;
715 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
716 for (unsigned i = 0; i != NE; ++i) {
717 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
718 SDValue Operand = Op.getOperand(j);
719 MVT OperandVT = Operand.getValueType();
720 if (OperandVT.isVector()) {
721 // A vector operand; extract a single element.
722 MVT OperandEltVT = OperandVT.getVectorElementType();
723 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
726 DAG.getConstant(i, MVT::i32));
728 // A scalar operand; just use it as is.
729 Operands[j] = Operand;
732 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT,
733 &Operands[0], Operands.size()));
736 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size());
739 /// GetFPLibCall - Return the right libcall for the given floating point type.
740 static RTLIB::Libcall GetFPLibCall(MVT VT,
741 RTLIB::Libcall Call_F32,
742 RTLIB::Libcall Call_F64,
743 RTLIB::Libcall Call_F80,
744 RTLIB::Libcall Call_PPCF128) {
746 VT == MVT::f32 ? Call_F32 :
747 VT == MVT::f64 ? Call_F64 :
748 VT == MVT::f80 ? Call_F80 :
749 VT == MVT::ppcf128 ? Call_PPCF128 :
750 RTLIB::UNKNOWN_LIBCALL;
753 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
754 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
755 /// is necessary to spill the vector being inserted into to memory, perform
756 /// the insert there, and then read the result back.
757 SDValue SelectionDAGLegalize::
758 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx) {
763 // If the target doesn't support this, we have to spill the input vector
764 // to a temporary stack slot, update the element, then reload it. This is
765 // badness. We could also load the value into a vector register (either
766 // with a "move to register" or "extload into register" instruction, then
767 // permute it into place, if the idx is a constant and if the idx is
768 // supported by the target.
769 MVT VT = Tmp1.getValueType();
770 MVT EltVT = VT.getVectorElementType();
771 MVT IdxVT = Tmp3.getValueType();
772 MVT PtrVT = TLI.getPointerTy();
773 SDValue StackPtr = DAG.CreateStackTemporary(VT);
775 int SPFI = cast<FrameIndexSDNode>(StackPtr.Val)->getIndex();
778 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr,
779 PseudoSourceValue::getFixedStack(SPFI), 0);
781 // Truncate or zero extend offset to target pointer type.
782 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
783 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
784 // Add the offset to the index.
785 unsigned EltSize = EltVT.getSizeInBits()/8;
786 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
787 SDValue StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
788 // Store the scalar value.
789 Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2,
790 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT);
791 // Load the updated vector.
792 return DAG.getLoad(VT, Ch, StackPtr,
793 PseudoSourceValue::getFixedStack(SPFI), 0);
796 /// LegalizeOp - We know that the specified value has a legal type, and
797 /// that its operands are legal. Now ensure that the operation itself
798 /// is legal, recursively ensuring that the operands' operations remain
800 SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
801 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
804 assert(isTypeLegal(Op.getValueType()) &&
805 "Caller should expand or promote operands that are not legal!");
806 SDNode *Node = Op.Val;
808 // If this operation defines any values that cannot be represented in a
809 // register on this target, make sure to expand or promote them.
810 if (Node->getNumValues() > 1) {
811 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
812 if (getTypeAction(Node->getValueType(i)) != Legal) {
813 HandleOp(Op.getValue(i));
814 assert(LegalizedNodes.count(Op) &&
815 "Handling didn't add legal operands!");
816 return LegalizedNodes[Op];
820 // Note that LegalizeOp may be reentered even from single-use nodes, which
821 // means that we always must cache transformed nodes.
822 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
823 if (I != LegalizedNodes.end()) return I->second;
825 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
827 bool isCustom = false;
829 switch (Node->getOpcode()) {
830 case ISD::FrameIndex:
831 case ISD::EntryToken:
833 case ISD::BasicBlock:
834 case ISD::TargetFrameIndex:
835 case ISD::TargetJumpTable:
836 case ISD::TargetConstant:
837 case ISD::TargetConstantFP:
838 case ISD::TargetConstantPool:
839 case ISD::TargetGlobalAddress:
840 case ISD::TargetGlobalTLSAddress:
841 case ISD::TargetExternalSymbol:
844 case ISD::MEMOPERAND:
847 // Primitives must all be legal.
848 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
849 "This must be legal!");
852 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
853 // If this is a target node, legalize it by legalizing the operands then
854 // passing it through.
855 SmallVector<SDValue, 8> Ops;
856 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
857 Ops.push_back(LegalizeOp(Node->getOperand(i)));
859 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
861 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
862 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
863 return Result.getValue(Op.ResNo);
865 // Otherwise this is an unhandled builtin node. splat.
867 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
869 assert(0 && "Do not know how to legalize this operator!");
871 case ISD::GLOBAL_OFFSET_TABLE:
872 case ISD::GlobalAddress:
873 case ISD::GlobalTLSAddress:
874 case ISD::ExternalSymbol:
875 case ISD::ConstantPool:
876 case ISD::JumpTable: // Nothing to do.
877 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
878 default: assert(0 && "This action is not supported yet!");
879 case TargetLowering::Custom:
880 Tmp1 = TLI.LowerOperation(Op, DAG);
881 if (Tmp1.Val) Result = Tmp1;
882 // FALLTHROUGH if the target doesn't want to lower this op after all.
883 case TargetLowering::Legal:
888 case ISD::RETURNADDR:
889 // The only option for these nodes is to custom lower them. If the target
890 // does not custom lower them, then return zero.
891 Tmp1 = TLI.LowerOperation(Op, DAG);
895 Result = DAG.getConstant(0, TLI.getPointerTy());
897 case ISD::FRAME_TO_ARGS_OFFSET: {
898 MVT VT = Node->getValueType(0);
899 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
900 default: assert(0 && "This action is not supported yet!");
901 case TargetLowering::Custom:
902 Result = TLI.LowerOperation(Op, DAG);
903 if (Result.Val) break;
905 case TargetLowering::Legal:
906 Result = DAG.getConstant(0, VT);
911 case ISD::EXCEPTIONADDR: {
912 Tmp1 = LegalizeOp(Node->getOperand(0));
913 MVT VT = Node->getValueType(0);
914 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
915 default: assert(0 && "This action is not supported yet!");
916 case TargetLowering::Expand: {
917 unsigned Reg = TLI.getExceptionAddressRegister();
918 Result = DAG.getCopyFromReg(Tmp1, Reg, VT);
921 case TargetLowering::Custom:
922 Result = TLI.LowerOperation(Op, DAG);
923 if (Result.Val) break;
925 case TargetLowering::Legal: {
926 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp1 };
927 Result = DAG.getMergeValues(Ops, 2);
932 if (Result.Val->getNumValues() == 1) break;
934 assert(Result.Val->getNumValues() == 2 &&
935 "Cannot return more than two values!");
937 // Since we produced two values, make sure to remember that we
938 // legalized both of them.
939 Tmp1 = LegalizeOp(Result);
940 Tmp2 = LegalizeOp(Result.getValue(1));
941 AddLegalizedOperand(Op.getValue(0), Tmp1);
942 AddLegalizedOperand(Op.getValue(1), Tmp2);
943 return Op.ResNo ? Tmp2 : Tmp1;
944 case ISD::EHSELECTION: {
945 Tmp1 = LegalizeOp(Node->getOperand(0));
946 Tmp2 = LegalizeOp(Node->getOperand(1));
947 MVT VT = Node->getValueType(0);
948 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
949 default: assert(0 && "This action is not supported yet!");
950 case TargetLowering::Expand: {
951 unsigned Reg = TLI.getExceptionSelectorRegister();
952 Result = DAG.getCopyFromReg(Tmp2, Reg, VT);
955 case TargetLowering::Custom:
956 Result = TLI.LowerOperation(Op, DAG);
957 if (Result.Val) break;
959 case TargetLowering::Legal: {
960 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp2 };
961 Result = DAG.getMergeValues(Ops, 2);
966 if (Result.Val->getNumValues() == 1) break;
968 assert(Result.Val->getNumValues() == 2 &&
969 "Cannot return more than two values!");
971 // Since we produced two values, make sure to remember that we
972 // legalized both of them.
973 Tmp1 = LegalizeOp(Result);
974 Tmp2 = LegalizeOp(Result.getValue(1));
975 AddLegalizedOperand(Op.getValue(0), Tmp1);
976 AddLegalizedOperand(Op.getValue(1), Tmp2);
977 return Op.ResNo ? Tmp2 : Tmp1;
978 case ISD::EH_RETURN: {
979 MVT VT = Node->getValueType(0);
980 // The only "good" option for this node is to custom lower it.
981 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
982 default: assert(0 && "This action is not supported at all!");
983 case TargetLowering::Custom:
984 Result = TLI.LowerOperation(Op, DAG);
985 if (Result.Val) break;
987 case TargetLowering::Legal:
988 // Target does not know, how to lower this, lower to noop
989 Result = LegalizeOp(Node->getOperand(0));
994 case ISD::AssertSext:
995 case ISD::AssertZext:
996 Tmp1 = LegalizeOp(Node->getOperand(0));
997 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
999 case ISD::MERGE_VALUES:
1000 // Legalize eliminates MERGE_VALUES nodes.
1001 Result = Node->getOperand(Op.ResNo);
1003 case ISD::CopyFromReg:
1004 Tmp1 = LegalizeOp(Node->getOperand(0));
1005 Result = Op.getValue(0);
1006 if (Node->getNumValues() == 2) {
1007 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1009 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
1010 if (Node->getNumOperands() == 3) {
1011 Tmp2 = LegalizeOp(Node->getOperand(2));
1012 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1014 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1016 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
1018 // Since CopyFromReg produces two values, make sure to remember that we
1019 // legalized both of them.
1020 AddLegalizedOperand(Op.getValue(0), Result);
1021 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1022 return Result.getValue(Op.ResNo);
1024 MVT VT = Op.getValueType();
1025 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
1026 default: assert(0 && "This action is not supported yet!");
1027 case TargetLowering::Expand:
1029 Result = DAG.getConstant(0, VT);
1030 else if (VT.isFloatingPoint())
1031 Result = DAG.getConstantFP(APFloat(APInt(VT.getSizeInBits(), 0)),
1034 assert(0 && "Unknown value type!");
1036 case TargetLowering::Legal:
1042 case ISD::INTRINSIC_W_CHAIN:
1043 case ISD::INTRINSIC_WO_CHAIN:
1044 case ISD::INTRINSIC_VOID: {
1045 SmallVector<SDValue, 8> Ops;
1046 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1047 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1048 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1050 // Allow the target to custom lower its intrinsics if it wants to.
1051 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
1052 TargetLowering::Custom) {
1053 Tmp3 = TLI.LowerOperation(Result, DAG);
1054 if (Tmp3.Val) Result = Tmp3;
1057 if (Result.Val->getNumValues() == 1) break;
1059 // Must have return value and chain result.
1060 assert(Result.Val->getNumValues() == 2 &&
1061 "Cannot return more than two values!");
1063 // Since loads produce two values, make sure to remember that we
1064 // legalized both of them.
1065 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1066 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1067 return Result.getValue(Op.ResNo);
1070 case ISD::DBG_STOPPOINT:
1071 assert(Node->getNumOperands() == 1 && "Invalid DBG_STOPPOINT node!");
1072 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
1074 switch (TLI.getOperationAction(ISD::DBG_STOPPOINT, MVT::Other)) {
1075 case TargetLowering::Promote:
1076 default: assert(0 && "This action is not supported yet!");
1077 case TargetLowering::Expand: {
1078 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
1079 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
1080 bool useLABEL = TLI.isOperationLegal(ISD::DBG_LABEL, MVT::Other);
1082 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node);
1083 if (MMI && (useDEBUG_LOC || useLABEL)) {
1084 const CompileUnitDesc *CompileUnit = DSP->getCompileUnit();
1085 unsigned SrcFile = MMI->RecordSource(CompileUnit);
1087 unsigned Line = DSP->getLine();
1088 unsigned Col = DSP->getColumn();
1091 SDValue Ops[] = { Tmp1, DAG.getConstant(Line, MVT::i32),
1092 DAG.getConstant(Col, MVT::i32),
1093 DAG.getConstant(SrcFile, MVT::i32) };
1094 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops, 4);
1096 unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile);
1097 Result = DAG.getLabel(ISD::DBG_LABEL, Tmp1, ID);
1100 Result = Tmp1; // chain
1104 case TargetLowering::Legal: {
1105 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1106 if (Action == Legal && Tmp1 == Node->getOperand(0))
1109 SmallVector<SDValue, 8> Ops;
1110 Ops.push_back(Tmp1);
1111 if (Action == Legal) {
1112 Ops.push_back(Node->getOperand(1)); // line # must be legal.
1113 Ops.push_back(Node->getOperand(2)); // col # must be legal.
1115 // Otherwise promote them.
1116 Ops.push_back(PromoteOp(Node->getOperand(1)));
1117 Ops.push_back(PromoteOp(Node->getOperand(2)));
1119 Ops.push_back(Node->getOperand(3)); // filename must be legal.
1120 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
1121 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1128 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!");
1129 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) {
1130 default: assert(0 && "This action is not supported yet!");
1131 case TargetLowering::Legal:
1132 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1133 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1134 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable.
1135 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1137 case TargetLowering::Expand:
1138 Result = LegalizeOp(Node->getOperand(0));
1143 case ISD::DEBUG_LOC:
1144 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
1145 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
1146 default: assert(0 && "This action is not supported yet!");
1147 case TargetLowering::Legal: {
1148 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1149 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1150 if (Action == Legal && Tmp1 == Node->getOperand(0))
1152 if (Action == Legal) {
1153 Tmp2 = Node->getOperand(1);
1154 Tmp3 = Node->getOperand(2);
1155 Tmp4 = Node->getOperand(3);
1157 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1158 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1159 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1161 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1167 case ISD::DBG_LABEL:
1169 assert(Node->getNumOperands() == 1 && "Invalid LABEL node!");
1170 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
1171 default: assert(0 && "This action is not supported yet!");
1172 case TargetLowering::Legal:
1173 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1174 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1176 case TargetLowering::Expand:
1177 Result = LegalizeOp(Node->getOperand(0));
1183 assert(Node->getNumOperands() == 4 && "Invalid Prefetch node!");
1184 switch (TLI.getOperationAction(ISD::PREFETCH, MVT::Other)) {
1185 default: assert(0 && "This action is not supported yet!");
1186 case TargetLowering::Legal:
1187 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1188 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1189 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the rw specifier.
1190 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize locality specifier.
1191 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1193 case TargetLowering::Expand:
1195 Result = LegalizeOp(Node->getOperand(0));
1200 case ISD::MEMBARRIER: {
1201 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!");
1202 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) {
1203 default: assert(0 && "This action is not supported yet!");
1204 case TargetLowering::Legal: {
1206 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1207 for (int x = 1; x < 6; ++x) {
1208 Ops[x] = Node->getOperand(x);
1209 if (!isTypeLegal(Ops[x].getValueType()))
1210 Ops[x] = PromoteOp(Ops[x]);
1212 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6);
1215 case TargetLowering::Expand:
1216 //There is no libgcc call for this op
1217 Result = Node->getOperand(0); // Noop
1223 case ISD::ATOMIC_CMP_SWAP: {
1224 unsigned int num_operands = 4;
1225 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1227 for (unsigned int x = 0; x < num_operands; ++x)
1228 Ops[x] = LegalizeOp(Node->getOperand(x));
1229 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1231 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1232 default: assert(0 && "This action is not supported yet!");
1233 case TargetLowering::Custom:
1234 Result = TLI.LowerOperation(Result, DAG);
1236 case TargetLowering::Legal:
1239 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1240 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1241 return Result.getValue(Op.ResNo);
1243 case ISD::ATOMIC_LOAD_ADD:
1244 case ISD::ATOMIC_LOAD_SUB:
1245 case ISD::ATOMIC_LOAD_AND:
1246 case ISD::ATOMIC_LOAD_OR:
1247 case ISD::ATOMIC_LOAD_XOR:
1248 case ISD::ATOMIC_LOAD_NAND:
1249 case ISD::ATOMIC_LOAD_MIN:
1250 case ISD::ATOMIC_LOAD_MAX:
1251 case ISD::ATOMIC_LOAD_UMIN:
1252 case ISD::ATOMIC_LOAD_UMAX:
1253 case ISD::ATOMIC_SWAP: {
1254 unsigned int num_operands = 3;
1255 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1257 for (unsigned int x = 0; x < num_operands; ++x)
1258 Ops[x] = LegalizeOp(Node->getOperand(x));
1259 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1261 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1262 default: assert(0 && "This action is not supported yet!");
1263 case TargetLowering::Custom:
1264 Result = TLI.LowerOperation(Result, DAG);
1266 case TargetLowering::Expand:
1267 Result = SDValue(TLI.ReplaceNodeResults(Op.Val, DAG),0);
1269 case TargetLowering::Legal:
1272 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1273 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1274 return Result.getValue(Op.ResNo);
1276 case ISD::Constant: {
1277 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1279 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1281 // We know we don't need to expand constants here, constants only have one
1282 // value and we check that it is fine above.
1284 if (opAction == TargetLowering::Custom) {
1285 Tmp1 = TLI.LowerOperation(Result, DAG);
1291 case ISD::ConstantFP: {
1292 // Spill FP immediates to the constant pool if the target cannot directly
1293 // codegen them. Targets often have some immediate values that can be
1294 // efficiently generated into an FP register without a load. We explicitly
1295 // leave these constants as ConstantFP nodes for the target to deal with.
1296 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1298 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1299 default: assert(0 && "This action is not supported yet!");
1300 case TargetLowering::Legal:
1302 case TargetLowering::Custom:
1303 Tmp3 = TLI.LowerOperation(Result, DAG);
1309 case TargetLowering::Expand: {
1310 // Check to see if this FP immediate is already legal.
1311 bool isLegal = false;
1312 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1313 E = TLI.legal_fpimm_end(); I != E; ++I) {
1314 if (CFP->isExactlyValue(*I)) {
1319 // If this is a legal constant, turn it into a TargetConstantFP node.
1322 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1327 case ISD::TokenFactor:
1328 if (Node->getNumOperands() == 2) {
1329 Tmp1 = LegalizeOp(Node->getOperand(0));
1330 Tmp2 = LegalizeOp(Node->getOperand(1));
1331 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1332 } else if (Node->getNumOperands() == 3) {
1333 Tmp1 = LegalizeOp(Node->getOperand(0));
1334 Tmp2 = LegalizeOp(Node->getOperand(1));
1335 Tmp3 = LegalizeOp(Node->getOperand(2));
1336 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1338 SmallVector<SDValue, 8> Ops;
1339 // Legalize the operands.
1340 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1341 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1342 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1346 case ISD::FORMAL_ARGUMENTS:
1348 // The only option for this is to custom lower it.
1349 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1350 assert(Tmp3.Val && "Target didn't custom lower this node!");
1351 // A call within a calling sequence must be legalized to something
1352 // other than the normal CALLSEQ_END. Violating this gets Legalize
1353 // into an infinite loop.
1354 assert ((!IsLegalizingCall ||
1355 Node->getOpcode() != ISD::CALL ||
1356 Tmp3.Val->getOpcode() != ISD::CALLSEQ_END) &&
1357 "Nested CALLSEQ_START..CALLSEQ_END not supported.");
1359 // The number of incoming and outgoing values should match; unless the final
1360 // outgoing value is a flag.
1361 assert((Tmp3.Val->getNumValues() == Result.Val->getNumValues() ||
1362 (Tmp3.Val->getNumValues() == Result.Val->getNumValues() + 1 &&
1363 Tmp3.Val->getValueType(Tmp3.Val->getNumValues() - 1) ==
1365 "Lowering call/formal_arguments produced unexpected # results!");
1367 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1368 // remember that we legalized all of them, so it doesn't get relegalized.
1369 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
1370 if (Tmp3.Val->getValueType(i) == MVT::Flag)
1372 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1375 AddLegalizedOperand(SDValue(Node, i), Tmp1);
1378 case ISD::EXTRACT_SUBREG: {
1379 Tmp1 = LegalizeOp(Node->getOperand(0));
1380 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1381 assert(idx && "Operand must be a constant");
1382 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1383 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1386 case ISD::INSERT_SUBREG: {
1387 Tmp1 = LegalizeOp(Node->getOperand(0));
1388 Tmp2 = LegalizeOp(Node->getOperand(1));
1389 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1390 assert(idx && "Operand must be a constant");
1391 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1392 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1395 case ISD::BUILD_VECTOR:
1396 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1397 default: assert(0 && "This action is not supported yet!");
1398 case TargetLowering::Custom:
1399 Tmp3 = TLI.LowerOperation(Result, DAG);
1405 case TargetLowering::Expand:
1406 Result = ExpandBUILD_VECTOR(Result.Val);
1410 case ISD::INSERT_VECTOR_ELT:
1411 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1412 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1414 // The type of the value to insert may not be legal, even though the vector
1415 // type is legal. Legalize/Promote accordingly. We do not handle Expand
1417 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1418 default: assert(0 && "Cannot expand insert element operand");
1419 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
1420 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
1422 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1424 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1425 Node->getValueType(0))) {
1426 default: assert(0 && "This action is not supported yet!");
1427 case TargetLowering::Legal:
1429 case TargetLowering::Custom:
1430 Tmp4 = TLI.LowerOperation(Result, DAG);
1436 case TargetLowering::Expand: {
1437 // If the insert index is a constant, codegen this as a scalar_to_vector,
1438 // then a shuffle that inserts it into the right position in the vector.
1439 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1440 // SCALAR_TO_VECTOR requires that the type of the value being inserted
1441 // match the element type of the vector being created.
1442 if (Tmp2.getValueType() ==
1443 Op.getValueType().getVectorElementType()) {
1444 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
1445 Tmp1.getValueType(), Tmp2);
1447 unsigned NumElts = Tmp1.getValueType().getVectorNumElements();
1449 MVT::getIntVectorWithNumElements(NumElts);
1450 MVT ShufMaskEltVT = ShufMaskVT.getVectorElementType();
1452 // We generate a shuffle of InVec and ScVec, so the shuffle mask
1453 // should be 0,1,2,3,4,5... with the appropriate element replaced with
1454 // elt 0 of the RHS.
1455 SmallVector<SDValue, 8> ShufOps;
1456 for (unsigned i = 0; i != NumElts; ++i) {
1457 if (i != InsertPos->getValue())
1458 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1460 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1462 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1463 &ShufOps[0], ShufOps.size());
1465 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1466 Tmp1, ScVec, ShufMask);
1467 Result = LegalizeOp(Result);
1471 Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3);
1476 case ISD::SCALAR_TO_VECTOR:
1477 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1478 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1482 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1483 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1484 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1485 Node->getValueType(0))) {
1486 default: assert(0 && "This action is not supported yet!");
1487 case TargetLowering::Legal:
1489 case TargetLowering::Custom:
1490 Tmp3 = TLI.LowerOperation(Result, DAG);
1496 case TargetLowering::Expand:
1497 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1501 case ISD::VECTOR_SHUFFLE:
1502 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1503 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1504 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1506 // Allow targets to custom lower the SHUFFLEs they support.
1507 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1508 default: assert(0 && "Unknown operation action!");
1509 case TargetLowering::Legal:
1510 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1511 "vector shuffle should not be created if not legal!");
1513 case TargetLowering::Custom:
1514 Tmp3 = TLI.LowerOperation(Result, DAG);
1520 case TargetLowering::Expand: {
1521 MVT VT = Node->getValueType(0);
1522 MVT EltVT = VT.getVectorElementType();
1523 MVT PtrVT = TLI.getPointerTy();
1524 SDValue Mask = Node->getOperand(2);
1525 unsigned NumElems = Mask.getNumOperands();
1526 SmallVector<SDValue,8> Ops;
1527 for (unsigned i = 0; i != NumElems; ++i) {
1528 SDValue Arg = Mask.getOperand(i);
1529 if (Arg.getOpcode() == ISD::UNDEF) {
1530 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1532 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1533 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
1535 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1536 DAG.getConstant(Idx, PtrVT)));
1538 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1539 DAG.getConstant(Idx - NumElems, PtrVT)));
1542 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1545 case TargetLowering::Promote: {
1546 // Change base type to a different vector type.
1547 MVT OVT = Node->getValueType(0);
1548 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1550 // Cast the two input vectors.
1551 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1552 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1554 // Convert the shuffle mask to the right # elements.
1555 Tmp3 = SDValue(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1556 assert(Tmp3.Val && "Shuffle not legal?");
1557 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1558 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1564 case ISD::EXTRACT_VECTOR_ELT:
1565 Tmp1 = Node->getOperand(0);
1566 Tmp2 = LegalizeOp(Node->getOperand(1));
1567 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1568 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1571 case ISD::EXTRACT_SUBVECTOR:
1572 Tmp1 = Node->getOperand(0);
1573 Tmp2 = LegalizeOp(Node->getOperand(1));
1574 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1575 Result = ExpandEXTRACT_SUBVECTOR(Result);
1578 case ISD::CALLSEQ_START: {
1579 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1581 // Recursively Legalize all of the inputs of the call end that do not lead
1582 // to this call start. This ensures that any libcalls that need be inserted
1583 // are inserted *before* the CALLSEQ_START.
1584 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1585 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1586 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
1590 // Now that we legalized all of the inputs (which may have inserted
1591 // libcalls) create the new CALLSEQ_START node.
1592 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1594 // Merge in the last call, to ensure that this call start after the last
1596 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1597 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1598 Tmp1 = LegalizeOp(Tmp1);
1601 // Do not try to legalize the target-specific arguments (#1+).
1602 if (Tmp1 != Node->getOperand(0)) {
1603 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1605 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1608 // Remember that the CALLSEQ_START is legalized.
1609 AddLegalizedOperand(Op.getValue(0), Result);
1610 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1611 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1613 // Now that the callseq_start and all of the non-call nodes above this call
1614 // sequence have been legalized, legalize the call itself. During this
1615 // process, no libcalls can/will be inserted, guaranteeing that no calls
1617 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1618 // Note that we are selecting this call!
1619 LastCALLSEQ_END = SDValue(CallEnd, 0);
1620 IsLegalizingCall = true;
1622 // Legalize the call, starting from the CALLSEQ_END.
1623 LegalizeOp(LastCALLSEQ_END);
1624 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1627 case ISD::CALLSEQ_END:
1628 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1629 // will cause this node to be legalized as well as handling libcalls right.
1630 if (LastCALLSEQ_END.Val != Node) {
1631 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
1632 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1633 assert(I != LegalizedNodes.end() &&
1634 "Legalizing the call start should have legalized this node!");
1638 // Otherwise, the call start has been legalized and everything is going
1639 // according to plan. Just legalize ourselves normally here.
1640 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1641 // Do not try to legalize the target-specific arguments (#1+), except for
1642 // an optional flag input.
1643 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1644 if (Tmp1 != Node->getOperand(0)) {
1645 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1647 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1650 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1651 if (Tmp1 != Node->getOperand(0) ||
1652 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1653 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1656 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1659 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1660 // This finishes up call legalization.
1661 IsLegalizingCall = false;
1663 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1664 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1665 if (Node->getNumValues() == 2)
1666 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1667 return Result.getValue(Op.ResNo);
1668 case ISD::DYNAMIC_STACKALLOC: {
1669 MVT VT = Node->getValueType(0);
1670 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1671 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1672 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1673 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1675 Tmp1 = Result.getValue(0);
1676 Tmp2 = Result.getValue(1);
1677 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1678 default: assert(0 && "This action is not supported yet!");
1679 case TargetLowering::Expand: {
1680 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1681 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1682 " not tell us which reg is the stack pointer!");
1683 SDValue Chain = Tmp1.getOperand(0);
1685 // Chain the dynamic stack allocation so that it doesn't modify the stack
1686 // pointer when other instructions are using the stack.
1687 Chain = DAG.getCALLSEQ_START(Chain,
1688 DAG.getConstant(0, TLI.getPointerTy()));
1690 SDValue Size = Tmp2.getOperand(1);
1691 SDValue SP = DAG.getCopyFromReg(Chain, SPReg, VT);
1692 Chain = SP.getValue(1);
1693 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue();
1694 unsigned StackAlign =
1695 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1696 if (Align > StackAlign)
1697 SP = DAG.getNode(ISD::AND, VT, SP,
1698 DAG.getConstant(-(uint64_t)Align, VT));
1699 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value
1700 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
1703 DAG.getCALLSEQ_END(Chain,
1704 DAG.getConstant(0, TLI.getPointerTy()),
1705 DAG.getConstant(0, TLI.getPointerTy()),
1708 Tmp1 = LegalizeOp(Tmp1);
1709 Tmp2 = LegalizeOp(Tmp2);
1712 case TargetLowering::Custom:
1713 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1715 Tmp1 = LegalizeOp(Tmp3);
1716 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1719 case TargetLowering::Legal:
1722 // Since this op produce two values, make sure to remember that we
1723 // legalized both of them.
1724 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
1725 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
1726 return Op.ResNo ? Tmp2 : Tmp1;
1728 case ISD::INLINEASM: {
1729 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1730 bool Changed = false;
1731 // Legalize all of the operands of the inline asm, in case they are nodes
1732 // that need to be expanded or something. Note we skip the asm string and
1733 // all of the TargetConstant flags.
1734 SDValue Op = LegalizeOp(Ops[0]);
1735 Changed = Op != Ops[0];
1738 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1739 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1740 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1741 for (++i; NumVals; ++i, --NumVals) {
1742 SDValue Op = LegalizeOp(Ops[i]);
1751 Op = LegalizeOp(Ops.back());
1752 Changed |= Op != Ops.back();
1757 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1759 // INLINE asm returns a chain and flag, make sure to add both to the map.
1760 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1761 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1762 return Result.getValue(Op.ResNo);
1765 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1766 // Ensure that libcalls are emitted before a branch.
1767 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1768 Tmp1 = LegalizeOp(Tmp1);
1769 LastCALLSEQ_END = DAG.getEntryNode();
1771 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1774 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1775 // Ensure that libcalls are emitted before a branch.
1776 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1777 Tmp1 = LegalizeOp(Tmp1);
1778 LastCALLSEQ_END = DAG.getEntryNode();
1780 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1781 default: assert(0 && "Indirect target must be legal type (pointer)!");
1783 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1786 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1789 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1790 // Ensure that libcalls are emitted before a branch.
1791 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1792 Tmp1 = LegalizeOp(Tmp1);
1793 LastCALLSEQ_END = DAG.getEntryNode();
1795 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1796 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1798 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1799 default: assert(0 && "This action is not supported yet!");
1800 case TargetLowering::Legal: break;
1801 case TargetLowering::Custom:
1802 Tmp1 = TLI.LowerOperation(Result, DAG);
1803 if (Tmp1.Val) Result = Tmp1;
1805 case TargetLowering::Expand: {
1806 SDValue Chain = Result.getOperand(0);
1807 SDValue Table = Result.getOperand(1);
1808 SDValue Index = Result.getOperand(2);
1810 MVT PTy = TLI.getPointerTy();
1811 MachineFunction &MF = DAG.getMachineFunction();
1812 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
1813 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1814 SDValue Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1817 switch (EntrySize) {
1818 default: assert(0 && "Size of jump table not supported yet."); break;
1819 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr,
1820 PseudoSourceValue::getJumpTable(), 0); break;
1821 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr,
1822 PseudoSourceValue::getJumpTable(), 0); break;
1826 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1827 // For PIC, the sequence is:
1828 // BRIND(load(Jumptable + index) + RelocBase)
1829 // RelocBase can be JumpTable, GOT or some sort of global base.
1830 if (PTy != MVT::i32)
1831 Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr);
1832 Addr = DAG.getNode(ISD::ADD, PTy, Addr,
1833 TLI.getPICJumpTableRelocBase(Table, DAG));
1835 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1840 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1841 // Ensure that libcalls are emitted before a return.
1842 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1843 Tmp1 = LegalizeOp(Tmp1);
1844 LastCALLSEQ_END = DAG.getEntryNode();
1846 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1847 case Expand: assert(0 && "It's impossible to expand bools");
1849 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1852 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1854 // The top bits of the promoted condition are not necessarily zero, ensure
1855 // that the value is properly zero extended.
1856 unsigned BitWidth = Tmp2.getValueSizeInBits();
1857 if (!DAG.MaskedValueIsZero(Tmp2,
1858 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
1859 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1864 // Basic block destination (Op#2) is always legal.
1865 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1867 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1868 default: assert(0 && "This action is not supported yet!");
1869 case TargetLowering::Legal: break;
1870 case TargetLowering::Custom:
1871 Tmp1 = TLI.LowerOperation(Result, DAG);
1872 if (Tmp1.Val) Result = Tmp1;
1874 case TargetLowering::Expand:
1875 // Expand brcond's setcc into its constituent parts and create a BR_CC
1877 if (Tmp2.getOpcode() == ISD::SETCC) {
1878 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1879 Tmp2.getOperand(0), Tmp2.getOperand(1),
1880 Node->getOperand(2));
1882 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1883 DAG.getCondCode(ISD::SETNE), Tmp2,
1884 DAG.getConstant(0, Tmp2.getValueType()),
1885 Node->getOperand(2));
1891 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1892 // Ensure that libcalls are emitted before a branch.
1893 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1894 Tmp1 = LegalizeOp(Tmp1);
1895 Tmp2 = Node->getOperand(2); // LHS
1896 Tmp3 = Node->getOperand(3); // RHS
1897 Tmp4 = Node->getOperand(1); // CC
1899 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1900 LastCALLSEQ_END = DAG.getEntryNode();
1902 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1903 // the LHS is a legal SETCC itself. In this case, we need to compare
1904 // the result against zero to select between true and false values.
1905 if (Tmp3.Val == 0) {
1906 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1907 Tmp4 = DAG.getCondCode(ISD::SETNE);
1910 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1911 Node->getOperand(4));
1913 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1914 default: assert(0 && "Unexpected action for BR_CC!");
1915 case TargetLowering::Legal: break;
1916 case TargetLowering::Custom:
1917 Tmp4 = TLI.LowerOperation(Result, DAG);
1918 if (Tmp4.Val) Result = Tmp4;
1923 LoadSDNode *LD = cast<LoadSDNode>(Node);
1924 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1925 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1927 ISD::LoadExtType ExtType = LD->getExtensionType();
1928 if (ExtType == ISD::NON_EXTLOAD) {
1929 MVT VT = Node->getValueType(0);
1930 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1931 Tmp3 = Result.getValue(0);
1932 Tmp4 = Result.getValue(1);
1934 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1935 default: assert(0 && "This action is not supported yet!");
1936 case TargetLowering::Legal:
1937 // If this is an unaligned load and the target doesn't support it,
1939 if (!TLI.allowsUnalignedMemoryAccesses()) {
1940 unsigned ABIAlignment = TLI.getTargetData()->
1941 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
1942 if (LD->getAlignment() < ABIAlignment){
1943 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
1945 Tmp3 = Result.getOperand(0);
1946 Tmp4 = Result.getOperand(1);
1947 Tmp3 = LegalizeOp(Tmp3);
1948 Tmp4 = LegalizeOp(Tmp4);
1952 case TargetLowering::Custom:
1953 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1955 Tmp3 = LegalizeOp(Tmp1);
1956 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1959 case TargetLowering::Promote: {
1960 // Only promote a load of vector type to another.
1961 assert(VT.isVector() && "Cannot promote this load!");
1962 // Change base type to a different vector type.
1963 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1965 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1966 LD->getSrcValueOffset(),
1967 LD->isVolatile(), LD->getAlignment());
1968 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1969 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1973 // Since loads produce two values, make sure to remember that we
1974 // legalized both of them.
1975 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
1976 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
1977 return Op.ResNo ? Tmp4 : Tmp3;
1979 MVT SrcVT = LD->getMemoryVT();
1980 unsigned SrcWidth = SrcVT.getSizeInBits();
1981 int SVOffset = LD->getSrcValueOffset();
1982 unsigned Alignment = LD->getAlignment();
1983 bool isVolatile = LD->isVolatile();
1985 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
1986 // Some targets pretend to have an i1 loading operation, and actually
1987 // load an i8. This trick is correct for ZEXTLOAD because the top 7
1988 // bits are guaranteed to be zero; it helps the optimizers understand
1989 // that these bits are zero. It is also useful for EXTLOAD, since it
1990 // tells the optimizers that those bits are undefined. It would be
1991 // nice to have an effective generic way of getting these benefits...
1992 // Until such a way is found, don't insist on promoting i1 here.
1993 (SrcVT != MVT::i1 ||
1994 TLI.getLoadXAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
1995 // Promote to a byte-sized load if not loading an integral number of
1996 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
1997 unsigned NewWidth = SrcVT.getStoreSizeInBits();
1998 MVT NVT = MVT::getIntegerVT(NewWidth);
2001 // The extra bits are guaranteed to be zero, since we stored them that
2002 // way. A zext load from NVT thus automatically gives zext from SrcVT.
2004 ISD::LoadExtType NewExtType =
2005 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
2007 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0),
2008 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
2009 NVT, isVolatile, Alignment);
2011 Ch = Result.getValue(1); // The chain.
2013 if (ExtType == ISD::SEXTLOAD)
2014 // Having the top bits zero doesn't help when sign extending.
2015 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2016 Result, DAG.getValueType(SrcVT));
2017 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
2018 // All the top bits are guaranteed to be zero - inform the optimizers.
2019 Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result,
2020 DAG.getValueType(SrcVT));
2022 Tmp1 = LegalizeOp(Result);
2023 Tmp2 = LegalizeOp(Ch);
2024 } else if (SrcWidth & (SrcWidth - 1)) {
2025 // If not loading a power-of-2 number of bits, expand as two loads.
2026 assert(SrcVT.isExtended() && !SrcVT.isVector() &&
2027 "Unsupported extload!");
2028 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
2029 assert(RoundWidth < SrcWidth);
2030 unsigned ExtraWidth = SrcWidth - RoundWidth;
2031 assert(ExtraWidth < RoundWidth);
2032 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2033 "Load size not an integral number of bytes!");
2034 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2035 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2037 unsigned IncrementSize;
2039 if (TLI.isLittleEndian()) {
2040 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
2041 // Load the bottom RoundWidth bits.
2042 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2043 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2046 // Load the remaining ExtraWidth bits.
2047 IncrementSize = RoundWidth / 8;
2048 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2049 DAG.getIntPtrConstant(IncrementSize));
2050 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2051 LD->getSrcValue(), SVOffset + IncrementSize,
2052 ExtraVT, isVolatile,
2053 MinAlign(Alignment, IncrementSize));
2055 // Build a factor node to remember that this load is independent of the
2057 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2060 // Move the top bits to the right place.
2061 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2062 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2064 // Join the hi and lo parts.
2065 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2067 // Big endian - avoid unaligned loads.
2068 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
2069 // Load the top RoundWidth bits.
2070 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2071 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2074 // Load the remaining ExtraWidth bits.
2075 IncrementSize = RoundWidth / 8;
2076 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2077 DAG.getIntPtrConstant(IncrementSize));
2078 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2079 LD->getSrcValue(), SVOffset + IncrementSize,
2080 ExtraVT, isVolatile,
2081 MinAlign(Alignment, IncrementSize));
2083 // Build a factor node to remember that this load is independent of the
2085 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2088 // Move the top bits to the right place.
2089 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2090 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2092 // Join the hi and lo parts.
2093 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2096 Tmp1 = LegalizeOp(Result);
2097 Tmp2 = LegalizeOp(Ch);
2099 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
2100 default: assert(0 && "This action is not supported yet!");
2101 case TargetLowering::Custom:
2104 case TargetLowering::Legal:
2105 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2106 Tmp1 = Result.getValue(0);
2107 Tmp2 = Result.getValue(1);
2110 Tmp3 = TLI.LowerOperation(Result, DAG);
2112 Tmp1 = LegalizeOp(Tmp3);
2113 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2116 // If this is an unaligned load and the target doesn't support it,
2118 if (!TLI.allowsUnalignedMemoryAccesses()) {
2119 unsigned ABIAlignment = TLI.getTargetData()->
2120 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
2121 if (LD->getAlignment() < ABIAlignment){
2122 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
2124 Tmp1 = Result.getOperand(0);
2125 Tmp2 = Result.getOperand(1);
2126 Tmp1 = LegalizeOp(Tmp1);
2127 Tmp2 = LegalizeOp(Tmp2);
2132 case TargetLowering::Expand:
2133 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
2134 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
2135 SDValue Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
2136 LD->getSrcValueOffset(),
2137 LD->isVolatile(), LD->getAlignment());
2138 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
2139 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
2140 Tmp2 = LegalizeOp(Load.getValue(1));
2143 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
2144 // Turn the unsupported load into an EXTLOAD followed by an explicit
2145 // zero/sign extend inreg.
2146 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2147 Tmp1, Tmp2, LD->getSrcValue(),
2148 LD->getSrcValueOffset(), SrcVT,
2149 LD->isVolatile(), LD->getAlignment());
2151 if (ExtType == ISD::SEXTLOAD)
2152 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2153 Result, DAG.getValueType(SrcVT));
2155 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
2156 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
2157 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
2162 // Since loads produce two values, make sure to remember that we legalized
2164 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2165 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2166 return Op.ResNo ? Tmp2 : Tmp1;
2169 case ISD::EXTRACT_ELEMENT: {
2170 MVT OpTy = Node->getOperand(0).getValueType();
2171 switch (getTypeAction(OpTy)) {
2172 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
2174 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
2176 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
2177 DAG.getConstant(OpTy.getSizeInBits()/2,
2178 TLI.getShiftAmountTy()));
2179 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
2182 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
2183 Node->getOperand(0));
2187 // Get both the low and high parts.
2188 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2189 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
2190 Result = Tmp2; // 1 -> Hi
2192 Result = Tmp1; // 0 -> Lo
2198 case ISD::CopyToReg:
2199 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2201 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
2202 "Register type must be legal!");
2203 // Legalize the incoming value (must be a legal type).
2204 Tmp2 = LegalizeOp(Node->getOperand(2));
2205 if (Node->getNumValues() == 1) {
2206 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
2208 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
2209 if (Node->getNumOperands() == 4) {
2210 Tmp3 = LegalizeOp(Node->getOperand(3));
2211 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
2214 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
2217 // Since this produces two values, make sure to remember that we legalized
2219 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
2220 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
2226 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2228 // Ensure that libcalls are emitted before a return.
2229 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2230 Tmp1 = LegalizeOp(Tmp1);
2231 LastCALLSEQ_END = DAG.getEntryNode();
2233 switch (Node->getNumOperands()) {
2235 Tmp2 = Node->getOperand(1);
2236 Tmp3 = Node->getOperand(2); // Signness
2237 switch (getTypeAction(Tmp2.getValueType())) {
2239 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
2242 if (!Tmp2.getValueType().isVector()) {
2244 ExpandOp(Tmp2, Lo, Hi);
2246 // Big endian systems want the hi reg first.
2247 if (TLI.isBigEndian())
2251 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2253 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
2254 Result = LegalizeOp(Result);
2256 SDNode *InVal = Tmp2.Val;
2257 int InIx = Tmp2.ResNo;
2258 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
2259 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
2261 // Figure out if there is a simple type corresponding to this Vector
2262 // type. If so, convert to the vector type.
2263 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2264 if (TLI.isTypeLegal(TVT)) {
2265 // Turn this into a return of the vector type.
2266 Tmp2 = LegalizeOp(Tmp2);
2267 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2268 } else if (NumElems == 1) {
2269 // Turn this into a return of the scalar type.
2270 Tmp2 = ScalarizeVectorOp(Tmp2);
2271 Tmp2 = LegalizeOp(Tmp2);
2272 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2274 // FIXME: Returns of gcc generic vectors smaller than a legal type
2275 // should be returned in integer registers!
2277 // The scalarized value type may not be legal, e.g. it might require
2278 // promotion or expansion. Relegalize the return.
2279 Result = LegalizeOp(Result);
2281 // FIXME: Returns of gcc generic vectors larger than a legal vector
2282 // type should be returned by reference!
2284 SplitVectorOp(Tmp2, Lo, Hi);
2285 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2286 Result = LegalizeOp(Result);
2291 Tmp2 = PromoteOp(Node->getOperand(1));
2292 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2293 Result = LegalizeOp(Result);
2298 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2300 default: { // ret <values>
2301 SmallVector<SDValue, 8> NewValues;
2302 NewValues.push_back(Tmp1);
2303 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
2304 switch (getTypeAction(Node->getOperand(i).getValueType())) {
2306 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
2307 NewValues.push_back(Node->getOperand(i+1));
2311 assert(!Node->getOperand(i).getValueType().isExtended() &&
2312 "FIXME: TODO: implement returning non-legal vector types!");
2313 ExpandOp(Node->getOperand(i), Lo, Hi);
2314 NewValues.push_back(Lo);
2315 NewValues.push_back(Node->getOperand(i+1));
2317 NewValues.push_back(Hi);
2318 NewValues.push_back(Node->getOperand(i+1));
2323 assert(0 && "Can't promote multiple return value yet!");
2326 if (NewValues.size() == Node->getNumOperands())
2327 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
2329 Result = DAG.getNode(ISD::RET, MVT::Other,
2330 &NewValues[0], NewValues.size());
2335 if (Result.getOpcode() == ISD::RET) {
2336 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
2337 default: assert(0 && "This action is not supported yet!");
2338 case TargetLowering::Legal: break;
2339 case TargetLowering::Custom:
2340 Tmp1 = TLI.LowerOperation(Result, DAG);
2341 if (Tmp1.Val) Result = Tmp1;
2347 StoreSDNode *ST = cast<StoreSDNode>(Node);
2348 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
2349 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
2350 int SVOffset = ST->getSrcValueOffset();
2351 unsigned Alignment = ST->getAlignment();
2352 bool isVolatile = ST->isVolatile();
2354 if (!ST->isTruncatingStore()) {
2355 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
2356 // FIXME: We shouldn't do this for TargetConstantFP's.
2357 // FIXME: move this to the DAG Combiner! Note that we can't regress due
2358 // to phase ordering between legalized code and the dag combiner. This
2359 // probably means that we need to integrate dag combiner and legalizer
2361 // We generally can't do this one for long doubles.
2362 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
2363 if (CFP->getValueType(0) == MVT::f32 &&
2364 getTypeAction(MVT::i32) == Legal) {
2365 Tmp3 = DAG.getConstant(CFP->getValueAPF().
2366 convertToAPInt().zextOrTrunc(32),
2368 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2369 SVOffset, isVolatile, Alignment);
2371 } else if (CFP->getValueType(0) == MVT::f64) {
2372 // If this target supports 64-bit registers, do a single 64-bit store.
2373 if (getTypeAction(MVT::i64) == Legal) {
2374 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt().
2375 zextOrTrunc(64), MVT::i64);
2376 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2377 SVOffset, isVolatile, Alignment);
2379 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
2380 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
2381 // stores. If the target supports neither 32- nor 64-bits, this
2382 // xform is certainly not worth it.
2383 const APInt &IntVal =CFP->getValueAPF().convertToAPInt();
2384 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
2385 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
2386 if (TLI.isBigEndian()) std::swap(Lo, Hi);
2388 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2389 SVOffset, isVolatile, Alignment);
2390 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2391 DAG.getIntPtrConstant(4));
2392 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
2393 isVolatile, MinAlign(Alignment, 4U));
2395 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2401 switch (getTypeAction(ST->getMemoryVT())) {
2403 Tmp3 = LegalizeOp(ST->getValue());
2404 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2407 MVT VT = Tmp3.getValueType();
2408 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2409 default: assert(0 && "This action is not supported yet!");
2410 case TargetLowering::Legal:
2411 // If this is an unaligned store and the target doesn't support it,
2413 if (!TLI.allowsUnalignedMemoryAccesses()) {
2414 unsigned ABIAlignment = TLI.getTargetData()->
2415 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2416 if (ST->getAlignment() < ABIAlignment)
2417 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2421 case TargetLowering::Custom:
2422 Tmp1 = TLI.LowerOperation(Result, DAG);
2423 if (Tmp1.Val) Result = Tmp1;
2425 case TargetLowering::Promote:
2426 assert(VT.isVector() && "Unknown legal promote case!");
2427 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
2428 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2429 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
2430 ST->getSrcValue(), SVOffset, isVolatile,
2437 // Truncate the value and store the result.
2438 Tmp3 = PromoteOp(ST->getValue());
2439 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2440 SVOffset, ST->getMemoryVT(),
2441 isVolatile, Alignment);
2445 unsigned IncrementSize = 0;
2448 // If this is a vector type, then we have to calculate the increment as
2449 // the product of the element size in bytes, and the number of elements
2450 // in the high half of the vector.
2451 if (ST->getValue().getValueType().isVector()) {
2452 SDNode *InVal = ST->getValue().Val;
2453 int InIx = ST->getValue().ResNo;
2454 MVT InVT = InVal->getValueType(InIx);
2455 unsigned NumElems = InVT.getVectorNumElements();
2456 MVT EVT = InVT.getVectorElementType();
2458 // Figure out if there is a simple type corresponding to this Vector
2459 // type. If so, convert to the vector type.
2460 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2461 if (TLI.isTypeLegal(TVT)) {
2462 // Turn this into a normal store of the vector type.
2463 Tmp3 = LegalizeOp(ST->getValue());
2464 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2465 SVOffset, isVolatile, Alignment);
2466 Result = LegalizeOp(Result);
2468 } else if (NumElems == 1) {
2469 // Turn this into a normal store of the scalar type.
2470 Tmp3 = ScalarizeVectorOp(ST->getValue());
2471 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2472 SVOffset, isVolatile, Alignment);
2473 // The scalarized value type may not be legal, e.g. it might require
2474 // promotion or expansion. Relegalize the scalar store.
2475 Result = LegalizeOp(Result);
2478 SplitVectorOp(ST->getValue(), Lo, Hi);
2479 IncrementSize = Lo.Val->getValueType(0).getVectorNumElements() *
2480 EVT.getSizeInBits()/8;
2483 ExpandOp(ST->getValue(), Lo, Hi);
2484 IncrementSize = Hi.Val ? Hi.getValueType().getSizeInBits()/8 : 0;
2486 if (TLI.isBigEndian())
2490 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2491 SVOffset, isVolatile, Alignment);
2493 if (Hi.Val == NULL) {
2494 // Must be int <-> float one-to-one expansion.
2499 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2500 DAG.getIntPtrConstant(IncrementSize));
2501 assert(isTypeLegal(Tmp2.getValueType()) &&
2502 "Pointers must be legal!");
2503 SVOffset += IncrementSize;
2504 Alignment = MinAlign(Alignment, IncrementSize);
2505 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2506 SVOffset, isVolatile, Alignment);
2507 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2511 switch (getTypeAction(ST->getValue().getValueType())) {
2513 Tmp3 = LegalizeOp(ST->getValue());
2516 // We can promote the value, the truncstore will still take care of it.
2517 Tmp3 = PromoteOp(ST->getValue());
2520 // Just store the low part. This may become a non-trunc store, so make
2521 // sure to use getTruncStore, not UpdateNodeOperands below.
2522 ExpandOp(ST->getValue(), Tmp3, Tmp4);
2523 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2524 SVOffset, MVT::i8, isVolatile, Alignment);
2527 MVT StVT = ST->getMemoryVT();
2528 unsigned StWidth = StVT.getSizeInBits();
2530 if (StWidth != StVT.getStoreSizeInBits()) {
2531 // Promote to a byte-sized store with upper bits zero if not
2532 // storing an integral number of bytes. For example, promote
2533 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
2534 MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits());
2535 Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT);
2536 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2537 SVOffset, NVT, isVolatile, Alignment);
2538 } else if (StWidth & (StWidth - 1)) {
2539 // If not storing a power-of-2 number of bits, expand as two stores.
2540 assert(StVT.isExtended() && !StVT.isVector() &&
2541 "Unsupported truncstore!");
2542 unsigned RoundWidth = 1 << Log2_32(StWidth);
2543 assert(RoundWidth < StWidth);
2544 unsigned ExtraWidth = StWidth - RoundWidth;
2545 assert(ExtraWidth < RoundWidth);
2546 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2547 "Store size not an integral number of bytes!");
2548 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2549 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2551 unsigned IncrementSize;
2553 if (TLI.isLittleEndian()) {
2554 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
2555 // Store the bottom RoundWidth bits.
2556 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2558 isVolatile, Alignment);
2560 // Store the remaining ExtraWidth bits.
2561 IncrementSize = RoundWidth / 8;
2562 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2563 DAG.getIntPtrConstant(IncrementSize));
2564 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2565 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2566 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2567 SVOffset + IncrementSize, ExtraVT, isVolatile,
2568 MinAlign(Alignment, IncrementSize));
2570 // Big endian - avoid unaligned stores.
2571 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
2572 // Store the top RoundWidth bits.
2573 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2574 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2575 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset,
2576 RoundVT, isVolatile, Alignment);
2578 // Store the remaining ExtraWidth bits.
2579 IncrementSize = RoundWidth / 8;
2580 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2581 DAG.getIntPtrConstant(IncrementSize));
2582 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2583 SVOffset + IncrementSize, ExtraVT, isVolatile,
2584 MinAlign(Alignment, IncrementSize));
2587 // The order of the stores doesn't matter.
2588 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2590 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2591 Tmp2 != ST->getBasePtr())
2592 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2595 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
2596 default: assert(0 && "This action is not supported yet!");
2597 case TargetLowering::Legal:
2598 // If this is an unaligned store and the target doesn't support it,
2600 if (!TLI.allowsUnalignedMemoryAccesses()) {
2601 unsigned ABIAlignment = TLI.getTargetData()->
2602 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2603 if (ST->getAlignment() < ABIAlignment)
2604 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2608 case TargetLowering::Custom:
2609 Result = TLI.LowerOperation(Result, DAG);
2612 // TRUNCSTORE:i16 i32 -> STORE i16
2613 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
2614 Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3);
2615 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset,
2616 isVolatile, Alignment);
2624 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2625 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2627 case ISD::STACKSAVE:
2628 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2629 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2630 Tmp1 = Result.getValue(0);
2631 Tmp2 = Result.getValue(1);
2633 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2634 default: assert(0 && "This action is not supported yet!");
2635 case TargetLowering::Legal: break;
2636 case TargetLowering::Custom:
2637 Tmp3 = TLI.LowerOperation(Result, DAG);
2639 Tmp1 = LegalizeOp(Tmp3);
2640 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2643 case TargetLowering::Expand:
2644 // Expand to CopyFromReg if the target set
2645 // StackPointerRegisterToSaveRestore.
2646 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2647 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
2648 Node->getValueType(0));
2649 Tmp2 = Tmp1.getValue(1);
2651 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
2652 Tmp2 = Node->getOperand(0);
2657 // Since stacksave produce two values, make sure to remember that we
2658 // legalized both of them.
2659 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2660 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2661 return Op.ResNo ? Tmp2 : Tmp1;
2663 case ISD::STACKRESTORE:
2664 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2665 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2666 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2668 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2669 default: assert(0 && "This action is not supported yet!");
2670 case TargetLowering::Legal: break;
2671 case TargetLowering::Custom:
2672 Tmp1 = TLI.LowerOperation(Result, DAG);
2673 if (Tmp1.Val) Result = Tmp1;
2675 case TargetLowering::Expand:
2676 // Expand to CopyToReg if the target set
2677 // StackPointerRegisterToSaveRestore.
2678 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2679 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
2687 case ISD::READCYCLECOUNTER:
2688 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2689 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2690 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2691 Node->getValueType(0))) {
2692 default: assert(0 && "This action is not supported yet!");
2693 case TargetLowering::Legal:
2694 Tmp1 = Result.getValue(0);
2695 Tmp2 = Result.getValue(1);
2697 case TargetLowering::Custom:
2698 Result = TLI.LowerOperation(Result, DAG);
2699 Tmp1 = LegalizeOp(Result.getValue(0));
2700 Tmp2 = LegalizeOp(Result.getValue(1));
2704 // Since rdcc produce two values, make sure to remember that we legalized
2706 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2707 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2711 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2712 case Expand: assert(0 && "It's impossible to expand bools");
2714 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2717 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2718 // Make sure the condition is either zero or one.
2719 unsigned BitWidth = Tmp1.getValueSizeInBits();
2720 if (!DAG.MaskedValueIsZero(Tmp1,
2721 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2722 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2726 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2727 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2729 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2731 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2732 default: assert(0 && "This action is not supported yet!");
2733 case TargetLowering::Legal: break;
2734 case TargetLowering::Custom: {
2735 Tmp1 = TLI.LowerOperation(Result, DAG);
2736 if (Tmp1.Val) Result = Tmp1;
2739 case TargetLowering::Expand:
2740 if (Tmp1.getOpcode() == ISD::SETCC) {
2741 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2743 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2745 Result = DAG.getSelectCC(Tmp1,
2746 DAG.getConstant(0, Tmp1.getValueType()),
2747 Tmp2, Tmp3, ISD::SETNE);
2750 case TargetLowering::Promote: {
2752 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2753 unsigned ExtOp, TruncOp;
2754 if (Tmp2.getValueType().isVector()) {
2755 ExtOp = ISD::BIT_CONVERT;
2756 TruncOp = ISD::BIT_CONVERT;
2757 } else if (Tmp2.getValueType().isInteger()) {
2758 ExtOp = ISD::ANY_EXTEND;
2759 TruncOp = ISD::TRUNCATE;
2761 ExtOp = ISD::FP_EXTEND;
2762 TruncOp = ISD::FP_ROUND;
2764 // Promote each of the values to the new type.
2765 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2766 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2767 // Perform the larger operation, then round down.
2768 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2769 if (TruncOp != ISD::FP_ROUND)
2770 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2772 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result,
2773 DAG.getIntPtrConstant(0));
2778 case ISD::SELECT_CC: {
2779 Tmp1 = Node->getOperand(0); // LHS
2780 Tmp2 = Node->getOperand(1); // RHS
2781 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2782 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2783 SDValue CC = Node->getOperand(4);
2785 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
2787 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
2788 // the LHS is a legal SETCC itself. In this case, we need to compare
2789 // the result against zero to select between true and false values.
2790 if (Tmp2.Val == 0) {
2791 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2792 CC = DAG.getCondCode(ISD::SETNE);
2794 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
2796 // Everything is legal, see if we should expand this op or something.
2797 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
2798 default: assert(0 && "This action is not supported yet!");
2799 case TargetLowering::Legal: break;
2800 case TargetLowering::Custom:
2801 Tmp1 = TLI.LowerOperation(Result, DAG);
2802 if (Tmp1.Val) Result = Tmp1;
2808 Tmp1 = Node->getOperand(0);
2809 Tmp2 = Node->getOperand(1);
2810 Tmp3 = Node->getOperand(2);
2811 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
2813 // If we had to Expand the SetCC operands into a SELECT node, then it may
2814 // not always be possible to return a true LHS & RHS. In this case, just
2815 // return the value we legalized, returned in the LHS
2816 if (Tmp2.Val == 0) {
2821 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
2822 default: assert(0 && "Cannot handle this action for SETCC yet!");
2823 case TargetLowering::Custom:
2826 case TargetLowering::Legal:
2827 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2829 Tmp4 = TLI.LowerOperation(Result, DAG);
2830 if (Tmp4.Val) Result = Tmp4;
2833 case TargetLowering::Promote: {
2834 // First step, figure out the appropriate operation to use.
2835 // Allow SETCC to not be supported for all legal data types
2836 // Mostly this targets FP
2837 MVT NewInTy = Node->getOperand(0).getValueType();
2838 MVT OldVT = NewInTy; OldVT = OldVT;
2840 // Scan for the appropriate larger type to use.
2842 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
2844 assert(NewInTy.isInteger() == OldVT.isInteger() &&
2845 "Fell off of the edge of the integer world");
2846 assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() &&
2847 "Fell off of the edge of the floating point world");
2849 // If the target supports SETCC of this type, use it.
2850 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2853 if (NewInTy.isInteger())
2854 assert(0 && "Cannot promote Legal Integer SETCC yet");
2856 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2857 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2859 Tmp1 = LegalizeOp(Tmp1);
2860 Tmp2 = LegalizeOp(Tmp2);
2861 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2862 Result = LegalizeOp(Result);
2865 case TargetLowering::Expand:
2866 // Expand a setcc node into a select_cc of the same condition, lhs, and
2867 // rhs that selects between const 1 (true) and const 0 (false).
2868 MVT VT = Node->getValueType(0);
2869 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2870 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2876 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2877 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2878 SDValue CC = Node->getOperand(2);
2880 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, CC);
2882 // Everything is legal, see if we should expand this op or something.
2883 switch (TLI.getOperationAction(ISD::VSETCC, Tmp1.getValueType())) {
2884 default: assert(0 && "This action is not supported yet!");
2885 case TargetLowering::Legal: break;
2886 case TargetLowering::Custom:
2887 Tmp1 = TLI.LowerOperation(Result, DAG);
2888 if (Tmp1.Val) Result = Tmp1;
2894 case ISD::SHL_PARTS:
2895 case ISD::SRA_PARTS:
2896 case ISD::SRL_PARTS: {
2897 SmallVector<SDValue, 8> Ops;
2898 bool Changed = false;
2899 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2900 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2901 Changed |= Ops.back() != Node->getOperand(i);
2904 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2906 switch (TLI.getOperationAction(Node->getOpcode(),
2907 Node->getValueType(0))) {
2908 default: assert(0 && "This action is not supported yet!");
2909 case TargetLowering::Legal: break;
2910 case TargetLowering::Custom:
2911 Tmp1 = TLI.LowerOperation(Result, DAG);
2913 SDValue Tmp2, RetVal(0, 0);
2914 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2915 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2916 AddLegalizedOperand(SDValue(Node, i), Tmp2);
2920 assert(RetVal.Val && "Illegal result number");
2926 // Since these produce multiple values, make sure to remember that we
2927 // legalized all of them.
2928 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2929 AddLegalizedOperand(SDValue(Node, i), Result.getValue(i));
2930 return Result.getValue(Op.ResNo);
2952 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2953 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2954 case Expand: assert(0 && "Not possible");
2956 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2959 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2963 if ((Node->getOpcode() == ISD::SHL ||
2964 Node->getOpcode() == ISD::SRL ||
2965 Node->getOpcode() == ISD::SRA) &&
2966 !Node->getValueType(0).isVector()) {
2967 if (TLI.getShiftAmountTy().bitsLT(Tmp2.getValueType()))
2968 Tmp2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Tmp2);
2969 else if (TLI.getShiftAmountTy().bitsGT(Tmp2.getValueType()))
2970 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Tmp2);
2973 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2975 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2976 default: assert(0 && "BinOp legalize operation not supported");
2977 case TargetLowering::Legal: break;
2978 case TargetLowering::Custom:
2979 Tmp1 = TLI.LowerOperation(Result, DAG);
2984 // Fall through if the custom lower can't deal with the operation
2985 case TargetLowering::Expand: {
2986 MVT VT = Op.getValueType();
2988 // See if multiply or divide can be lowered using two-result operations.
2989 SDVTList VTs = DAG.getVTList(VT, VT);
2990 if (Node->getOpcode() == ISD::MUL) {
2991 // We just need the low half of the multiply; try both the signed
2992 // and unsigned forms. If the target supports both SMUL_LOHI and
2993 // UMUL_LOHI, form a preference by checking which forms of plain
2994 // MULH it supports.
2995 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT);
2996 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT);
2997 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT);
2998 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT);
2999 unsigned OpToUse = 0;
3000 if (HasSMUL_LOHI && !HasMULHS) {
3001 OpToUse = ISD::SMUL_LOHI;
3002 } else if (HasUMUL_LOHI && !HasMULHU) {
3003 OpToUse = ISD::UMUL_LOHI;
3004 } else if (HasSMUL_LOHI) {
3005 OpToUse = ISD::SMUL_LOHI;
3006 } else if (HasUMUL_LOHI) {
3007 OpToUse = ISD::UMUL_LOHI;
3010 Result = SDValue(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).Val, 0);
3014 if (Node->getOpcode() == ISD::MULHS &&
3015 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) {
3016 Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
3019 if (Node->getOpcode() == ISD::MULHU &&
3020 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) {
3021 Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
3024 if (Node->getOpcode() == ISD::SDIV &&
3025 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3026 Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 0);
3029 if (Node->getOpcode() == ISD::UDIV &&
3030 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3031 Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 0);
3035 // Check to see if we have a libcall for this operator.
3036 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3037 bool isSigned = false;
3038 switch (Node->getOpcode()) {
3041 if (VT == MVT::i32) {
3042 LC = Node->getOpcode() == ISD::UDIV
3043 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
3044 isSigned = Node->getOpcode() == ISD::SDIV;
3048 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
3049 RTLIB::POW_PPCF128);
3053 if (LC != RTLIB::UNKNOWN_LIBCALL) {
3055 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3059 assert(Node->getValueType(0).isVector() &&
3060 "Cannot expand this binary operator!");
3061 // Expand the operation into a bunch of nasty scalar code.
3062 Result = LegalizeOp(UnrollVectorOp(Op));
3065 case TargetLowering::Promote: {
3066 switch (Node->getOpcode()) {
3067 default: assert(0 && "Do not know how to promote this BinOp!");
3071 MVT OVT = Node->getValueType(0);
3072 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3073 assert(OVT.isVector() && "Cannot promote this BinOp!");
3074 // Bit convert each of the values to the new type.
3075 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
3076 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
3077 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3078 // Bit convert the result back the original type.
3079 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
3087 case ISD::SMUL_LOHI:
3088 case ISD::UMUL_LOHI:
3091 // These nodes will only be produced by target-specific lowering, so
3092 // they shouldn't be here if they aren't legal.
3093 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
3094 "This must be legal!");
3096 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3097 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3098 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3101 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
3102 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3103 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3104 case Expand: assert(0 && "Not possible");
3106 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3109 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3113 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3115 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3116 default: assert(0 && "Operation not supported");
3117 case TargetLowering::Custom:
3118 Tmp1 = TLI.LowerOperation(Result, DAG);
3119 if (Tmp1.Val) Result = Tmp1;
3121 case TargetLowering::Legal: break;
3122 case TargetLowering::Expand: {
3123 // If this target supports fabs/fneg natively and select is cheap,
3124 // do this efficiently.
3125 if (!TLI.isSelectExpensive() &&
3126 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
3127 TargetLowering::Legal &&
3128 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
3129 TargetLowering::Legal) {
3130 // Get the sign bit of the RHS.
3132 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
3133 SDValue SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
3134 SignBit = DAG.getSetCC(TLI.getSetCCResultType(SignBit),
3135 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
3136 // Get the absolute value of the result.
3137 SDValue AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
3138 // Select between the nabs and abs value based on the sign bit of
3140 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
3141 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
3144 Result = LegalizeOp(Result);
3148 // Otherwise, do bitwise ops!
3150 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
3151 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
3152 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
3153 Result = LegalizeOp(Result);
3161 Tmp1 = LegalizeOp(Node->getOperand(0));
3162 Tmp2 = LegalizeOp(Node->getOperand(1));
3163 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3164 // Since this produces two values, make sure to remember that we legalized
3166 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
3167 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
3172 Tmp1 = LegalizeOp(Node->getOperand(0));
3173 Tmp2 = LegalizeOp(Node->getOperand(1));
3174 Tmp3 = LegalizeOp(Node->getOperand(2));
3175 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3176 // Since this produces two values, make sure to remember that we legalized
3178 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
3179 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
3182 case ISD::BUILD_PAIR: {
3183 MVT PairTy = Node->getValueType(0);
3184 // TODO: handle the case where the Lo and Hi operands are not of legal type
3185 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
3186 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
3187 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
3188 case TargetLowering::Promote:
3189 case TargetLowering::Custom:
3190 assert(0 && "Cannot promote/custom this yet!");
3191 case TargetLowering::Legal:
3192 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
3193 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
3195 case TargetLowering::Expand:
3196 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
3197 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
3198 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
3199 DAG.getConstant(PairTy.getSizeInBits()/2,
3200 TLI.getShiftAmountTy()));
3201 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
3210 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3211 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3213 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3214 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
3215 case TargetLowering::Custom:
3218 case TargetLowering::Legal:
3219 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3221 Tmp1 = TLI.LowerOperation(Result, DAG);
3222 if (Tmp1.Val) Result = Tmp1;
3225 case TargetLowering::Expand: {
3226 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
3227 bool isSigned = DivOpc == ISD::SDIV;
3228 MVT VT = Node->getValueType(0);
3230 // See if remainder can be lowered using two-result operations.
3231 SDVTList VTs = DAG.getVTList(VT, VT);
3232 if (Node->getOpcode() == ISD::SREM &&
3233 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3234 Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 1);
3237 if (Node->getOpcode() == ISD::UREM &&
3238 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3239 Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 1);
3243 if (VT.isInteger()) {
3244 if (TLI.getOperationAction(DivOpc, VT) ==
3245 TargetLowering::Legal) {
3247 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
3248 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
3249 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
3250 } else if (VT.isVector()) {
3251 Result = LegalizeOp(UnrollVectorOp(Op));
3253 assert(VT == MVT::i32 &&
3254 "Cannot expand this binary operator!");
3255 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
3256 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
3258 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3261 assert(VT.isFloatingPoint() &&
3262 "remainder op must have integer or floating-point type");
3263 if (VT.isVector()) {
3264 Result = LegalizeOp(UnrollVectorOp(Op));
3266 // Floating point mod -> fmod libcall.
3267 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
3268 RTLIB::REM_F80, RTLIB::REM_PPCF128);
3270 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3278 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3279 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3281 MVT VT = Node->getValueType(0);
3282 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
3283 default: assert(0 && "This action is not supported yet!");
3284 case TargetLowering::Custom:
3287 case TargetLowering::Legal:
3288 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3289 Result = Result.getValue(0);
3290 Tmp1 = Result.getValue(1);
3293 Tmp2 = TLI.LowerOperation(Result, DAG);
3295 Result = LegalizeOp(Tmp2);
3296 Tmp1 = LegalizeOp(Tmp2.getValue(1));
3300 case TargetLowering::Expand: {
3301 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3302 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
3303 // Increment the pointer, VAList, to the next vaarg
3304 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3305 DAG.getConstant(VT.getSizeInBits()/8,
3306 TLI.getPointerTy()));
3307 // Store the incremented VAList to the legalized pointer
3308 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
3309 // Load the actual argument out of the pointer VAList
3310 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
3311 Tmp1 = LegalizeOp(Result.getValue(1));
3312 Result = LegalizeOp(Result);
3316 // Since VAARG produces two values, make sure to remember that we
3317 // legalized both of them.
3318 AddLegalizedOperand(SDValue(Node, 0), Result);
3319 AddLegalizedOperand(SDValue(Node, 1), Tmp1);
3320 return Op.ResNo ? Tmp1 : Result;
3324 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3325 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
3326 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
3328 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
3329 default: assert(0 && "This action is not supported yet!");
3330 case TargetLowering::Custom:
3333 case TargetLowering::Legal:
3334 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
3335 Node->getOperand(3), Node->getOperand(4));
3337 Tmp1 = TLI.LowerOperation(Result, DAG);
3338 if (Tmp1.Val) Result = Tmp1;
3341 case TargetLowering::Expand:
3342 // This defaults to loading a pointer from the input and storing it to the
3343 // output, returning the chain.
3344 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3345 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3346 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VS, 0);
3347 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VD, 0);
3353 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3354 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3356 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
3357 default: assert(0 && "This action is not supported yet!");
3358 case TargetLowering::Custom:
3361 case TargetLowering::Legal:
3362 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3364 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
3365 if (Tmp1.Val) Result = Tmp1;
3368 case TargetLowering::Expand:
3369 Result = Tmp1; // Default to a no-op, return the chain
3375 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3376 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3378 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3380 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
3381 default: assert(0 && "This action is not supported yet!");
3382 case TargetLowering::Legal: break;
3383 case TargetLowering::Custom:
3384 Tmp1 = TLI.LowerOperation(Result, DAG);
3385 if (Tmp1.Val) Result = Tmp1;
3392 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3393 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3394 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3395 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3397 assert(0 && "ROTL/ROTR legalize operation not supported");
3399 case TargetLowering::Legal:
3401 case TargetLowering::Custom:
3402 Tmp1 = TLI.LowerOperation(Result, DAG);
3403 if (Tmp1.Val) Result = Tmp1;
3405 case TargetLowering::Promote:
3406 assert(0 && "Do not know how to promote ROTL/ROTR");
3408 case TargetLowering::Expand:
3409 assert(0 && "Do not know how to expand ROTL/ROTR");
3415 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3416 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3417 case TargetLowering::Custom:
3418 assert(0 && "Cannot custom legalize this yet!");
3419 case TargetLowering::Legal:
3420 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3422 case TargetLowering::Promote: {
3423 MVT OVT = Tmp1.getValueType();
3424 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3425 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3427 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3428 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3429 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3430 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3433 case TargetLowering::Expand:
3434 Result = ExpandBSWAP(Tmp1);
3442 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3443 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3444 case TargetLowering::Custom:
3445 case TargetLowering::Legal:
3446 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3447 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3448 TargetLowering::Custom) {
3449 Tmp1 = TLI.LowerOperation(Result, DAG);
3455 case TargetLowering::Promote: {
3456 MVT OVT = Tmp1.getValueType();
3457 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3459 // Zero extend the argument.
3460 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3461 // Perform the larger operation, then subtract if needed.
3462 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
3463 switch (Node->getOpcode()) {
3468 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3469 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
3470 DAG.getConstant(NVT.getSizeInBits(), NVT),
3472 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3473 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3476 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3477 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3478 DAG.getConstant(NVT.getSizeInBits() -
3479 OVT.getSizeInBits(), NVT));
3484 case TargetLowering::Expand:
3485 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
3500 case ISD::FNEARBYINT:
3501 Tmp1 = LegalizeOp(Node->getOperand(0));
3502 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3503 case TargetLowering::Promote:
3504 case TargetLowering::Custom:
3507 case TargetLowering::Legal:
3508 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3510 Tmp1 = TLI.LowerOperation(Result, DAG);
3511 if (Tmp1.Val) Result = Tmp1;
3514 case TargetLowering::Expand:
3515 switch (Node->getOpcode()) {
3516 default: assert(0 && "Unreachable!");
3518 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3519 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3520 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
3523 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3524 MVT VT = Node->getValueType(0);
3525 Tmp2 = DAG.getConstantFP(0.0, VT);
3526 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
3528 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
3529 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
3535 MVT VT = Node->getValueType(0);
3537 // Expand unsupported unary vector operators by unrolling them.
3538 if (VT.isVector()) {
3539 Result = LegalizeOp(UnrollVectorOp(Op));
3543 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3544 switch(Node->getOpcode()) {
3546 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3547 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
3550 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
3551 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
3554 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
3555 RTLIB::COS_F80, RTLIB::COS_PPCF128);
3557 default: assert(0 && "Unreachable!");
3560 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3568 MVT VT = Node->getValueType(0);
3570 // Expand unsupported unary vector operators by unrolling them.
3571 if (VT.isVector()) {
3572 Result = LegalizeOp(UnrollVectorOp(Op));
3576 // We always lower FPOWI into a libcall. No target support for it yet.
3577 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
3578 RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
3580 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3583 case ISD::BIT_CONVERT:
3584 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3585 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3586 Node->getValueType(0));
3587 } else if (Op.getOperand(0).getValueType().isVector()) {
3588 // The input has to be a vector type, we have to either scalarize it, pack
3589 // it, or convert it based on whether the input vector type is legal.
3590 SDNode *InVal = Node->getOperand(0).Val;
3591 int InIx = Node->getOperand(0).ResNo;
3592 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
3593 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
3595 // Figure out if there is a simple type corresponding to this Vector
3596 // type. If so, convert to the vector type.
3597 MVT TVT = MVT::getVectorVT(EVT, NumElems);
3598 if (TLI.isTypeLegal(TVT)) {
3599 // Turn this into a bit convert of the vector input.
3600 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3601 LegalizeOp(Node->getOperand(0)));
3603 } else if (NumElems == 1) {
3604 // Turn this into a bit convert of the scalar input.
3605 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3606 ScalarizeVectorOp(Node->getOperand(0)));
3609 // FIXME: UNIMP! Store then reload
3610 assert(0 && "Cast from unsupported vector type not implemented yet!");
3613 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3614 Node->getOperand(0).getValueType())) {
3615 default: assert(0 && "Unknown operation action!");
3616 case TargetLowering::Expand:
3617 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3618 Node->getValueType(0));
3620 case TargetLowering::Legal:
3621 Tmp1 = LegalizeOp(Node->getOperand(0));
3622 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3628 // Conversion operators. The source and destination have different types.
3629 case ISD::SINT_TO_FP:
3630 case ISD::UINT_TO_FP: {
3631 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
3632 Result = LegalizeINT_TO_FP(Result, isSigned,
3633 Node->getValueType(0), Node->getOperand(0));
3637 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3639 Tmp1 = LegalizeOp(Node->getOperand(0));
3640 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3643 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3645 // Since the result is legal, we should just be able to truncate the low
3646 // part of the source.
3647 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
3650 Result = PromoteOp(Node->getOperand(0));
3651 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
3656 case ISD::FP_TO_SINT:
3657 case ISD::FP_TO_UINT:
3658 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3660 Tmp1 = LegalizeOp(Node->getOperand(0));
3662 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
3663 default: assert(0 && "Unknown operation action!");
3664 case TargetLowering::Custom:
3667 case TargetLowering::Legal:
3668 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3670 Tmp1 = TLI.LowerOperation(Result, DAG);
3671 if (Tmp1.Val) Result = Tmp1;
3674 case TargetLowering::Promote:
3675 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
3676 Node->getOpcode() == ISD::FP_TO_SINT);
3678 case TargetLowering::Expand:
3679 if (Node->getOpcode() == ISD::FP_TO_UINT) {
3680 SDValue True, False;
3681 MVT VT = Node->getOperand(0).getValueType();
3682 MVT NVT = Node->getValueType(0);
3683 const uint64_t zero[] = {0, 0};
3684 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero));
3685 APInt x = APInt::getSignBit(NVT.getSizeInBits());
3686 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
3687 Tmp2 = DAG.getConstantFP(apf, VT);
3688 Tmp3 = DAG.getSetCC(TLI.getSetCCResultType(Node->getOperand(0)),
3689 Node->getOperand(0), Tmp2, ISD::SETLT);
3690 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
3691 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
3692 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
3694 False = DAG.getNode(ISD::XOR, NVT, False,
3695 DAG.getConstant(x, NVT));
3696 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
3699 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
3705 MVT VT = Op.getValueType();
3706 MVT OVT = Node->getOperand(0).getValueType();
3707 // Convert ppcf128 to i32
3708 if (OVT == MVT::ppcf128 && VT == MVT::i32) {
3709 if (Node->getOpcode() == ISD::FP_TO_SINT) {
3710 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128,
3711 Node->getOperand(0), DAG.getValueType(MVT::f64));
3712 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result,
3713 DAG.getIntPtrConstant(1));
3714 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result);
3716 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
3717 APFloat apf = APFloat(APInt(128, 2, TwoE31));
3718 Tmp2 = DAG.getConstantFP(apf, OVT);
3719 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
3720 // FIXME: generated code sucks.
3721 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2,
3722 DAG.getNode(ISD::ADD, MVT::i32,
3723 DAG.getNode(ISD::FP_TO_SINT, VT,
3724 DAG.getNode(ISD::FSUB, OVT,
3725 Node->getOperand(0), Tmp2)),
3726 DAG.getConstant(0x80000000, MVT::i32)),
3727 DAG.getNode(ISD::FP_TO_SINT, VT,
3728 Node->getOperand(0)),
3729 DAG.getCondCode(ISD::SETGE));
3733 // Convert f32 / f64 to i32 / i64 / i128.
3734 RTLIB::Libcall LC = (Node->getOpcode() == ISD::FP_TO_SINT) ?
3735 RTLIB::getFPTOSINT(OVT, VT) : RTLIB::getFPTOUINT(OVT, VT);
3736 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpectd fp-to-int conversion!");
3738 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3742 Tmp1 = PromoteOp(Node->getOperand(0));
3743 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
3744 Result = LegalizeOp(Result);
3749 case ISD::FP_EXTEND: {
3750 MVT DstVT = Op.getValueType();
3751 MVT SrcVT = Op.getOperand(0).getValueType();
3752 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3753 // The only other way we can lower this is to turn it into a STORE,
3754 // LOAD pair, targetting a temporary location (a stack slot).
3755 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT);
3758 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3759 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3761 Tmp1 = LegalizeOp(Node->getOperand(0));
3762 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3765 Tmp1 = PromoteOp(Node->getOperand(0));
3766 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1);
3771 case ISD::FP_ROUND: {
3772 MVT DstVT = Op.getValueType();
3773 MVT SrcVT = Op.getOperand(0).getValueType();
3774 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3775 if (SrcVT == MVT::ppcf128) {
3777 ExpandOp(Node->getOperand(0), Lo, Result);
3778 // Round it the rest of the way (e.g. to f32) if needed.
3779 if (DstVT!=MVT::f64)
3780 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1));
3783 // The only other way we can lower this is to turn it into a STORE,
3784 // LOAD pair, targetting a temporary location (a stack slot).
3785 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT);
3788 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3789 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3791 Tmp1 = LegalizeOp(Node->getOperand(0));
3792 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3795 Tmp1 = PromoteOp(Node->getOperand(0));
3796 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1,
3797 Node->getOperand(1));
3802 case ISD::ANY_EXTEND:
3803 case ISD::ZERO_EXTEND:
3804 case ISD::SIGN_EXTEND:
3805 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3806 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3808 Tmp1 = LegalizeOp(Node->getOperand(0));
3809 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3810 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3811 TargetLowering::Custom) {
3812 Tmp1 = TLI.LowerOperation(Result, DAG);
3813 if (Tmp1.Val) Result = Tmp1;
3817 switch (Node->getOpcode()) {
3818 case ISD::ANY_EXTEND:
3819 Tmp1 = PromoteOp(Node->getOperand(0));
3820 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
3822 case ISD::ZERO_EXTEND:
3823 Result = PromoteOp(Node->getOperand(0));
3824 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3825 Result = DAG.getZeroExtendInReg(Result,
3826 Node->getOperand(0).getValueType());
3828 case ISD::SIGN_EXTEND:
3829 Result = PromoteOp(Node->getOperand(0));
3830 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3831 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3833 DAG.getValueType(Node->getOperand(0).getValueType()));
3838 case ISD::FP_ROUND_INREG:
3839 case ISD::SIGN_EXTEND_INREG: {
3840 Tmp1 = LegalizeOp(Node->getOperand(0));
3841 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3843 // If this operation is not supported, convert it to a shl/shr or load/store
3845 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
3846 default: assert(0 && "This action not supported for this op yet!");
3847 case TargetLowering::Legal:
3848 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3850 case TargetLowering::Expand:
3851 // If this is an integer extend and shifts are supported, do that.
3852 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
3853 // NOTE: we could fall back on load/store here too for targets without
3854 // SAR. However, it is doubtful that any exist.
3855 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() -
3856 ExtraVT.getSizeInBits();
3857 SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
3858 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
3859 Node->getOperand(0), ShiftCst);
3860 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
3862 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
3863 // The only way we can lower this is to turn it into a TRUNCSTORE,
3864 // EXTLOAD pair, targetting a temporary location (a stack slot).
3866 // NOTE: there is a choice here between constantly creating new stack
3867 // slots and always reusing the same one. We currently always create
3868 // new ones, as reuse may inhibit scheduling.
3869 Result = EmitStackConvert(Node->getOperand(0), ExtraVT,
3870 Node->getValueType(0));
3872 assert(0 && "Unknown op");
3878 case ISD::TRAMPOLINE: {
3880 for (unsigned i = 0; i != 6; ++i)
3881 Ops[i] = LegalizeOp(Node->getOperand(i));
3882 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
3883 // The only option for this node is to custom lower it.
3884 Result = TLI.LowerOperation(Result, DAG);
3885 assert(Result.Val && "Should always custom lower!");
3887 // Since trampoline produces two values, make sure to remember that we
3888 // legalized both of them.
3889 Tmp1 = LegalizeOp(Result.getValue(1));
3890 Result = LegalizeOp(Result);
3891 AddLegalizedOperand(SDValue(Node, 0), Result);
3892 AddLegalizedOperand(SDValue(Node, 1), Tmp1);
3893 return Op.ResNo ? Tmp1 : Result;
3895 case ISD::FLT_ROUNDS_: {
3896 MVT VT = Node->getValueType(0);
3897 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
3898 default: assert(0 && "This action not supported for this op yet!");
3899 case TargetLowering::Custom:
3900 Result = TLI.LowerOperation(Op, DAG);
3901 if (Result.Val) break;
3903 case TargetLowering::Legal:
3904 // If this operation is not supported, lower it to constant 1
3905 Result = DAG.getConstant(1, VT);
3911 MVT VT = Node->getValueType(0);
3912 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
3913 default: assert(0 && "This action not supported for this op yet!");
3914 case TargetLowering::Legal:
3915 Tmp1 = LegalizeOp(Node->getOperand(0));
3916 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3918 case TargetLowering::Custom:
3919 Result = TLI.LowerOperation(Op, DAG);
3920 if (Result.Val) break;
3922 case TargetLowering::Expand:
3923 // If this operation is not supported, lower it to 'abort()' call
3924 Tmp1 = LegalizeOp(Node->getOperand(0));
3925 TargetLowering::ArgListTy Args;
3926 std::pair<SDValue,SDValue> CallResult =
3927 TLI.LowerCallTo(Tmp1, Type::VoidTy,
3928 false, false, false, CallingConv::C, false,
3929 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
3931 Result = CallResult.second;
3938 assert(Result.getValueType() == Op.getValueType() &&
3939 "Bad legalization!");
3941 // Make sure that the generated code is itself legal.
3943 Result = LegalizeOp(Result);
3945 // Note that LegalizeOp may be reentered even from single-use nodes, which
3946 // means that we always must cache transformed nodes.
3947 AddLegalizedOperand(Op, Result);
3951 /// PromoteOp - Given an operation that produces a value in an invalid type,
3952 /// promote it to compute the value into a larger type. The produced value will
3953 /// have the correct bits for the low portion of the register, but no guarantee
3954 /// is made about the top bits: it may be zero, sign-extended, or garbage.
3955 SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) {
3956 MVT VT = Op.getValueType();
3957 MVT NVT = TLI.getTypeToTransformTo(VT);
3958 assert(getTypeAction(VT) == Promote &&
3959 "Caller should expand or legalize operands that are not promotable!");
3960 assert(NVT.bitsGT(VT) && NVT.isInteger() == VT.isInteger() &&
3961 "Cannot promote to smaller type!");
3963 SDValue Tmp1, Tmp2, Tmp3;
3965 SDNode *Node = Op.Val;
3967 DenseMap<SDValue, SDValue>::iterator I = PromotedNodes.find(Op);
3968 if (I != PromotedNodes.end()) return I->second;
3970 switch (Node->getOpcode()) {
3971 case ISD::CopyFromReg:
3972 assert(0 && "CopyFromReg must be legal!");
3975 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
3977 assert(0 && "Do not know how to promote this operator!");
3980 Result = DAG.getNode(ISD::UNDEF, NVT);
3984 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
3986 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
3987 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
3989 case ISD::ConstantFP:
3990 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
3991 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
3995 assert(isTypeLegal(TLI.getSetCCResultType(Node->getOperand(0)))
3996 && "SetCC type is not legal??");
3997 Result = DAG.getNode(ISD::SETCC,
3998 TLI.getSetCCResultType(Node->getOperand(0)),
3999 Node->getOperand(0), Node->getOperand(1),
4000 Node->getOperand(2));
4004 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4006 Result = LegalizeOp(Node->getOperand(0));
4007 assert(Result.getValueType().bitsGE(NVT) &&
4008 "This truncation doesn't make sense!");
4009 if (Result.getValueType().bitsGT(NVT)) // Truncate to NVT instead of VT
4010 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
4013 // The truncation is not required, because we don't guarantee anything
4014 // about high bits anyway.
4015 Result = PromoteOp(Node->getOperand(0));
4018 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4019 // Truncate the low part of the expanded value to the result type
4020 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
4023 case ISD::SIGN_EXTEND:
4024 case ISD::ZERO_EXTEND:
4025 case ISD::ANY_EXTEND:
4026 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4027 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
4029 // Input is legal? Just do extend all the way to the larger type.
4030 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4033 // Promote the reg if it's smaller.
4034 Result = PromoteOp(Node->getOperand(0));
4035 // The high bits are not guaranteed to be anything. Insert an extend.
4036 if (Node->getOpcode() == ISD::SIGN_EXTEND)
4037 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4038 DAG.getValueType(Node->getOperand(0).getValueType()));
4039 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
4040 Result = DAG.getZeroExtendInReg(Result,
4041 Node->getOperand(0).getValueType());
4045 case ISD::BIT_CONVERT:
4046 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
4047 Node->getValueType(0));
4048 Result = PromoteOp(Result);
4051 case ISD::FP_EXTEND:
4052 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
4054 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4055 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
4056 case Promote: assert(0 && "Unreachable with 2 FP types!");
4058 if (Node->getConstantOperandVal(1) == 0) {
4059 // Input is legal? Do an FP_ROUND_INREG.
4060 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
4061 DAG.getValueType(VT));
4063 // Just remove the truncate, it isn't affecting the value.
4064 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0),
4065 Node->getOperand(1));
4070 case ISD::SINT_TO_FP:
4071 case ISD::UINT_TO_FP:
4072 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4074 // No extra round required here.
4075 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4079 Result = PromoteOp(Node->getOperand(0));
4080 if (Node->getOpcode() == ISD::SINT_TO_FP)
4081 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
4083 DAG.getValueType(Node->getOperand(0).getValueType()));
4085 Result = DAG.getZeroExtendInReg(Result,
4086 Node->getOperand(0).getValueType());
4087 // No extra round required here.
4088 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
4091 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
4092 Node->getOperand(0));
4093 // Round if we cannot tolerate excess precision.
4094 if (NoExcessFPPrecision)
4095 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4096 DAG.getValueType(VT));
4101 case ISD::SIGN_EXTEND_INREG:
4102 Result = PromoteOp(Node->getOperand(0));
4103 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4104 Node->getOperand(1));
4106 case ISD::FP_TO_SINT:
4107 case ISD::FP_TO_UINT:
4108 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4111 Tmp1 = Node->getOperand(0);
4114 // The input result is prerounded, so we don't have to do anything
4116 Tmp1 = PromoteOp(Node->getOperand(0));
4119 // If we're promoting a UINT to a larger size, check to see if the new node
4120 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
4121 // we can use that instead. This allows us to generate better code for
4122 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
4123 // legal, such as PowerPC.
4124 if (Node->getOpcode() == ISD::FP_TO_UINT &&
4125 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
4126 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
4127 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
4128 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
4130 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4136 Tmp1 = PromoteOp(Node->getOperand(0));
4137 assert(Tmp1.getValueType() == NVT);
4138 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4139 // NOTE: we do not have to do any extra rounding here for
4140 // NoExcessFPPrecision, because we know the input will have the appropriate
4141 // precision, and these operations don't modify precision at all.
4147 Tmp1 = PromoteOp(Node->getOperand(0));
4148 assert(Tmp1.getValueType() == NVT);
4149 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4150 if (NoExcessFPPrecision)
4151 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4152 DAG.getValueType(VT));
4156 // Promote f32 powi to f64 powi. Note that this could insert a libcall
4157 // directly as well, which may be better.
4158 Tmp1 = PromoteOp(Node->getOperand(0));
4159 assert(Tmp1.getValueType() == NVT);
4160 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1));
4161 if (NoExcessFPPrecision)
4162 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4163 DAG.getValueType(VT));
4167 case ISD::ATOMIC_CMP_SWAP: {
4168 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4169 Tmp2 = PromoteOp(Node->getOperand(2));
4170 Tmp3 = PromoteOp(Node->getOperand(3));
4171 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(),
4172 AtomNode->getBasePtr(), Tmp2, Tmp3,
4173 AtomNode->getSrcValue(),
4174 AtomNode->getAlignment());
4175 // Remember that we legalized the chain.
4176 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4179 case ISD::ATOMIC_LOAD_ADD:
4180 case ISD::ATOMIC_LOAD_SUB:
4181 case ISD::ATOMIC_LOAD_AND:
4182 case ISD::ATOMIC_LOAD_OR:
4183 case ISD::ATOMIC_LOAD_XOR:
4184 case ISD::ATOMIC_LOAD_NAND:
4185 case ISD::ATOMIC_LOAD_MIN:
4186 case ISD::ATOMIC_LOAD_MAX:
4187 case ISD::ATOMIC_LOAD_UMIN:
4188 case ISD::ATOMIC_LOAD_UMAX:
4189 case ISD::ATOMIC_SWAP: {
4190 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4191 Tmp2 = PromoteOp(Node->getOperand(2));
4192 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(),
4193 AtomNode->getBasePtr(), Tmp2,
4194 AtomNode->getSrcValue(),
4195 AtomNode->getAlignment());
4196 // Remember that we legalized the chain.
4197 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4207 // The input may have strange things in the top bits of the registers, but
4208 // these operations don't care. They may have weird bits going out, but
4209 // that too is okay if they are integer operations.
4210 Tmp1 = PromoteOp(Node->getOperand(0));
4211 Tmp2 = PromoteOp(Node->getOperand(1));
4212 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4213 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4218 Tmp1 = PromoteOp(Node->getOperand(0));
4219 Tmp2 = PromoteOp(Node->getOperand(1));
4220 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4221 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4223 // Floating point operations will give excess precision that we may not be
4224 // able to tolerate. If we DO allow excess precision, just leave it,
4225 // otherwise excise it.
4226 // FIXME: Why would we need to round FP ops more than integer ones?
4227 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
4228 if (NoExcessFPPrecision)
4229 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4230 DAG.getValueType(VT));
4235 // These operators require that their input be sign extended.
4236 Tmp1 = PromoteOp(Node->getOperand(0));
4237 Tmp2 = PromoteOp(Node->getOperand(1));
4238 if (NVT.isInteger()) {
4239 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4240 DAG.getValueType(VT));
4241 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4242 DAG.getValueType(VT));
4244 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4246 // Perform FP_ROUND: this is probably overly pessimistic.
4247 if (NVT.isFloatingPoint() && NoExcessFPPrecision)
4248 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4249 DAG.getValueType(VT));
4253 case ISD::FCOPYSIGN:
4254 // These operators require that their input be fp extended.
4255 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4256 case Expand: assert(0 && "not implemented");
4257 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break;
4258 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break;
4260 switch (getTypeAction(Node->getOperand(1).getValueType())) {
4261 case Expand: assert(0 && "not implemented");
4262 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
4263 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
4265 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4267 // Perform FP_ROUND: this is probably overly pessimistic.
4268 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
4269 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4270 DAG.getValueType(VT));
4275 // These operators require that their input be zero extended.
4276 Tmp1 = PromoteOp(Node->getOperand(0));
4277 Tmp2 = PromoteOp(Node->getOperand(1));
4278 assert(NVT.isInteger() && "Operators don't apply to FP!");
4279 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4280 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4281 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4285 Tmp1 = PromoteOp(Node->getOperand(0));
4286 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
4289 // The input value must be properly sign extended.
4290 Tmp1 = PromoteOp(Node->getOperand(0));
4291 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4292 DAG.getValueType(VT));
4293 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
4296 // The input value must be properly zero extended.
4297 Tmp1 = PromoteOp(Node->getOperand(0));
4298 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4299 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
4303 Tmp1 = Node->getOperand(0); // Get the chain.
4304 Tmp2 = Node->getOperand(1); // Get the pointer.
4305 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
4306 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
4307 Result = TLI.LowerOperation(Tmp3, DAG);
4309 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
4310 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
4311 // Increment the pointer, VAList, to the next vaarg
4312 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
4313 DAG.getConstant(VT.getSizeInBits()/8,
4314 TLI.getPointerTy()));
4315 // Store the incremented VAList to the legalized pointer
4316 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
4317 // Load the actual argument out of the pointer VAList
4318 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
4320 // Remember that we legalized the chain.
4321 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4325 LoadSDNode *LD = cast<LoadSDNode>(Node);
4326 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
4327 ? ISD::EXTLOAD : LD->getExtensionType();
4328 Result = DAG.getExtLoad(ExtType, NVT,
4329 LD->getChain(), LD->getBasePtr(),
4330 LD->getSrcValue(), LD->getSrcValueOffset(),
4333 LD->getAlignment());
4334 // Remember that we legalized the chain.
4335 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4339 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
4340 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
4342 MVT VT2 = Tmp2.getValueType();
4343 assert(VT2 == Tmp3.getValueType()
4344 && "PromoteOp SELECT: Operands 2 and 3 ValueTypes don't match");
4345 // Ensure that the resulting node is at least the same size as the operands'
4346 // value types, because we cannot assume that TLI.getSetCCValueType() is
4348 Result = DAG.getNode(ISD::SELECT, VT2, Node->getOperand(0), Tmp2, Tmp3);
4351 case ISD::SELECT_CC:
4352 Tmp2 = PromoteOp(Node->getOperand(2)); // True
4353 Tmp3 = PromoteOp(Node->getOperand(3)); // False
4354 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4355 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
4358 Tmp1 = Node->getOperand(0);
4359 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
4360 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
4361 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
4362 DAG.getConstant(NVT.getSizeInBits() -
4364 TLI.getShiftAmountTy()));
4369 // Zero extend the argument
4370 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4371 // Perform the larger operation, then subtract if needed.
4372 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4373 switch(Node->getOpcode()) {
4378 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
4379 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
4380 DAG.getConstant(NVT.getSizeInBits(), NVT),
4382 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
4383 DAG.getConstant(VT.getSizeInBits(), NVT), Tmp1);
4386 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4387 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
4388 DAG.getConstant(NVT.getSizeInBits() -
4389 VT.getSizeInBits(), NVT));
4393 case ISD::EXTRACT_SUBVECTOR:
4394 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
4396 case ISD::EXTRACT_VECTOR_ELT:
4397 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
4401 assert(Result.Val && "Didn't set a result!");
4403 // Make sure the result is itself legal.
4404 Result = LegalizeOp(Result);
4406 // Remember that we promoted this!
4407 AddPromotedOperand(Op, Result);
4411 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
4412 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
4413 /// based on the vector type. The return type of this matches the element type
4414 /// of the vector, which may not be legal for the target.
4415 SDValue SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDValue Op) {
4416 // We know that operand #0 is the Vec vector. If the index is a constant
4417 // or if the invec is a supported hardware type, we can use it. Otherwise,
4418 // lower to a store then an indexed load.
4419 SDValue Vec = Op.getOperand(0);
4420 SDValue Idx = Op.getOperand(1);
4422 MVT TVT = Vec.getValueType();
4423 unsigned NumElems = TVT.getVectorNumElements();
4425 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
4426 default: assert(0 && "This action is not supported yet!");
4427 case TargetLowering::Custom: {
4428 Vec = LegalizeOp(Vec);
4429 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4430 SDValue Tmp3 = TLI.LowerOperation(Op, DAG);
4435 case TargetLowering::Legal:
4436 if (isTypeLegal(TVT)) {
4437 Vec = LegalizeOp(Vec);
4438 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4442 case TargetLowering::Expand:
4446 if (NumElems == 1) {
4447 // This must be an access of the only element. Return it.
4448 Op = ScalarizeVectorOp(Vec);
4449 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
4450 unsigned NumLoElts = 1 << Log2_32(NumElems-1);
4451 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4453 SplitVectorOp(Vec, Lo, Hi);
4454 if (CIdx->getValue() < NumLoElts) {
4458 Idx = DAG.getConstant(CIdx->getValue() - NumLoElts,
4459 Idx.getValueType());
4462 // It's now an extract from the appropriate high or low part. Recurse.
4463 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4464 Op = ExpandEXTRACT_VECTOR_ELT(Op);
4466 // Store the value to a temporary stack slot, then LOAD the scalar
4467 // element back out.
4468 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
4469 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
4471 // Add the offset to the index.
4472 unsigned EltSize = Op.getValueType().getSizeInBits()/8;
4473 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
4474 DAG.getConstant(EltSize, Idx.getValueType()));
4476 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
4477 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx);
4479 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
4481 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
4483 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
4488 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
4489 /// we assume the operation can be split if it is not already legal.
4490 SDValue SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDValue Op) {
4491 // We know that operand #0 is the Vec vector. For now we assume the index
4492 // is a constant and that the extracted result is a supported hardware type.
4493 SDValue Vec = Op.getOperand(0);
4494 SDValue Idx = LegalizeOp(Op.getOperand(1));
4496 unsigned NumElems = Vec.getValueType().getVectorNumElements();
4498 if (NumElems == Op.getValueType().getVectorNumElements()) {
4499 // This must be an access of the desired vector length. Return it.
4503 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4505 SplitVectorOp(Vec, Lo, Hi);
4506 if (CIdx->getValue() < NumElems/2) {
4510 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
4513 // It's now an extract from the appropriate high or low part. Recurse.
4514 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4515 return ExpandEXTRACT_SUBVECTOR(Op);
4518 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
4519 /// with condition CC on the current target. This usually involves legalizing
4520 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
4521 /// there may be no choice but to create a new SetCC node to represent the
4522 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
4523 /// LHS, and the SDValue returned in RHS has a nil SDNode value.
4524 void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS,
4527 SDValue Tmp1, Tmp2, Tmp3, Result;
4529 switch (getTypeAction(LHS.getValueType())) {
4531 Tmp1 = LegalizeOp(LHS); // LHS
4532 Tmp2 = LegalizeOp(RHS); // RHS
4535 Tmp1 = PromoteOp(LHS); // LHS
4536 Tmp2 = PromoteOp(RHS); // RHS
4538 // If this is an FP compare, the operands have already been extended.
4539 if (LHS.getValueType().isInteger()) {
4540 MVT VT = LHS.getValueType();
4541 MVT NVT = TLI.getTypeToTransformTo(VT);
4543 // Otherwise, we have to insert explicit sign or zero extends. Note
4544 // that we could insert sign extends for ALL conditions, but zero extend
4545 // is cheaper on many machines (an AND instead of two shifts), so prefer
4547 switch (cast<CondCodeSDNode>(CC)->get()) {
4548 default: assert(0 && "Unknown integer comparison!");
4555 // ALL of these operations will work if we either sign or zero extend
4556 // the operands (including the unsigned comparisons!). Zero extend is
4557 // usually a simpler/cheaper operation, so prefer it.
4558 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4559 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4565 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4566 DAG.getValueType(VT));
4567 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4568 DAG.getValueType(VT));
4574 MVT VT = LHS.getValueType();
4575 if (VT == MVT::f32 || VT == MVT::f64) {
4576 // Expand into one or more soft-fp libcall(s).
4577 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
4578 switch (cast<CondCodeSDNode>(CC)->get()) {
4581 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4585 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
4589 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4593 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4597 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4601 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4604 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4607 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
4610 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4611 switch (cast<CondCodeSDNode>(CC)->get()) {
4613 // SETONE = SETOLT | SETOGT
4614 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4617 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4620 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4623 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4626 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4629 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4631 default: assert(0 && "Unsupported FP setcc!");
4636 SDValue Ops[2] = { LHS, RHS };
4637 Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2).Val,
4638 false /*sign irrelevant*/, Dummy);
4639 Tmp2 = DAG.getConstant(0, MVT::i32);
4640 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
4641 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
4642 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
4644 LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2).Val,
4645 false /*sign irrelevant*/, Dummy);
4646 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, Tmp2,
4647 DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
4648 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4651 LHS = LegalizeOp(Tmp1);
4656 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
4657 ExpandOp(LHS, LHSLo, LHSHi);
4658 ExpandOp(RHS, RHSLo, RHSHi);
4659 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
4661 if (VT==MVT::ppcf128) {
4662 // FIXME: This generated code sucks. We want to generate
4663 // FCMP crN, hi1, hi2
4665 // FCMP crN, lo1, lo2
4666 // The following can be improved, but not that much.
4667 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETEQ);
4668 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, CCCode);
4669 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4670 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETNE);
4671 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode);
4672 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4673 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
4682 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
4683 if (RHSCST->isAllOnesValue()) {
4684 // Comparison to -1.
4685 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
4690 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
4691 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
4692 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4693 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
4696 // If this is a comparison of the sign bit, just look at the top part.
4698 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
4699 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
4700 CST->isNullValue()) || // X < 0
4701 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
4702 CST->isAllOnesValue())) { // X > -1
4708 // FIXME: This generated code sucks.
4709 ISD::CondCode LowCC;
4711 default: assert(0 && "Unknown integer setcc!");
4713 case ISD::SETULT: LowCC = ISD::SETULT; break;
4715 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
4717 case ISD::SETULE: LowCC = ISD::SETULE; break;
4719 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
4722 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
4723 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
4724 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
4726 // NOTE: on targets without efficient SELECT of bools, we can always use
4727 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
4728 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
4729 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo,
4730 LowCC, false, DagCombineInfo);
4732 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC);
4733 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4734 CCCode, false, DagCombineInfo);
4736 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi,
4739 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
4740 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
4741 if ((Tmp1C && Tmp1C->isNullValue()) ||
4742 (Tmp2C && Tmp2C->isNullValue() &&
4743 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
4744 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
4745 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
4746 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
4747 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
4748 // low part is known false, returns high part.
4749 // For LE / GE, if high part is known false, ignore the low part.
4750 // For LT / GT, if high part is known true, ignore the low part.
4754 Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4755 ISD::SETEQ, false, DagCombineInfo);
4757 Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4759 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
4760 Result, Tmp1, Tmp2));
4771 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
4772 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
4773 /// a load from the stack slot to DestVT, extending it if needed.
4774 /// The resultant code need not be legal.
4775 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
4778 // Create the stack frame object.
4779 unsigned SrcAlign = TLI.getTargetData()->getPrefTypeAlignment(
4780 SrcOp.getValueType().getTypeForMVT());
4781 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
4783 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
4784 int SPFI = StackPtrFI->getIndex();
4786 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
4787 unsigned SlotSize = SlotVT.getSizeInBits();
4788 unsigned DestSize = DestVT.getSizeInBits();
4789 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(
4790 DestVT.getTypeForMVT());
4792 // Emit a store to the stack slot. Use a truncstore if the input value is
4793 // later than DestVT.
4796 if (SrcSize > SlotSize)
4797 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr,
4798 PseudoSourceValue::getFixedStack(SPFI), 0,
4799 SlotVT, false, SrcAlign);
4801 assert(SrcSize == SlotSize && "Invalid store");
4802 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr,
4803 PseudoSourceValue::getFixedStack(SPFI), 0,
4807 // Result is a load from the stack slot.
4808 if (SlotSize == DestSize)
4809 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0, false, DestAlign);
4811 assert(SlotSize < DestSize && "Unknown extension!");
4812 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT,
4816 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
4817 // Create a vector sized/aligned stack slot, store the value to element #0,
4818 // then load the whole vector back out.
4819 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
4821 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
4822 int SPFI = StackPtrFI->getIndex();
4824 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
4825 PseudoSourceValue::getFixedStack(SPFI), 0);
4826 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,
4827 PseudoSourceValue::getFixedStack(SPFI), 0);
4831 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
4832 /// support the operation, but do support the resultant vector type.
4833 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
4835 // If the only non-undef value is the low element, turn this into a
4836 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
4837 unsigned NumElems = Node->getNumOperands();
4838 bool isOnlyLowElement = true;
4839 SDValue SplatValue = Node->getOperand(0);
4841 // FIXME: it would be far nicer to change this into map<SDValue,uint64_t>
4842 // and use a bitmask instead of a list of elements.
4843 std::map<SDValue, std::vector<unsigned> > Values;
4844 Values[SplatValue].push_back(0);
4845 bool isConstant = true;
4846 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
4847 SplatValue.getOpcode() != ISD::UNDEF)
4850 for (unsigned i = 1; i < NumElems; ++i) {
4851 SDValue V = Node->getOperand(i);
4852 Values[V].push_back(i);
4853 if (V.getOpcode() != ISD::UNDEF)
4854 isOnlyLowElement = false;
4855 if (SplatValue != V)
4856 SplatValue = SDValue(0,0);
4858 // If this isn't a constant element or an undef, we can't use a constant
4860 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
4861 V.getOpcode() != ISD::UNDEF)
4865 if (isOnlyLowElement) {
4866 // If the low element is an undef too, then this whole things is an undef.
4867 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
4868 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
4869 // Otherwise, turn this into a scalar_to_vector node.
4870 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4871 Node->getOperand(0));
4874 // If all elements are constants, create a load from the constant pool.
4876 MVT VT = Node->getValueType(0);
4877 std::vector<Constant*> CV;
4878 for (unsigned i = 0, e = NumElems; i != e; ++i) {
4879 if (ConstantFPSDNode *V =
4880 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
4881 CV.push_back(ConstantFP::get(V->getValueAPF()));
4882 } else if (ConstantSDNode *V =
4883 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
4884 CV.push_back(ConstantInt::get(V->getAPIntValue()));
4886 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
4888 Node->getOperand(0).getValueType().getTypeForMVT();
4889 CV.push_back(UndefValue::get(OpNTy));
4892 Constant *CP = ConstantVector::get(CV);
4893 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
4894 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4895 PseudoSourceValue::getConstantPool(), 0);
4898 if (SplatValue.Val) { // Splat of one value?
4899 // Build the shuffle constant vector: <0, 0, 0, 0>
4900 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
4901 SDValue Zero = DAG.getConstant(0, MaskVT.getVectorElementType());
4902 std::vector<SDValue> ZeroVec(NumElems, Zero);
4903 SDValue SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4904 &ZeroVec[0], ZeroVec.size());
4906 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4907 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
4908 // Get the splatted value into the low element of a vector register.
4910 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
4912 // Return shuffle(LowValVec, undef, <0,0,0,0>)
4913 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
4914 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
4919 // If there are only two unique elements, we may be able to turn this into a
4921 if (Values.size() == 2) {
4922 // Get the two values in deterministic order.
4923 SDValue Val1 = Node->getOperand(1);
4925 std::map<SDValue, std::vector<unsigned> >::iterator MI = Values.begin();
4926 if (MI->first != Val1)
4929 Val2 = (++MI)->first;
4931 // If Val1 is an undef, make sure end ends up as Val2, to ensure that our
4932 // vector shuffle has the undef vector on the RHS.
4933 if (Val1.getOpcode() == ISD::UNDEF)
4934 std::swap(Val1, Val2);
4936 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
4937 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
4938 MVT MaskEltVT = MaskVT.getVectorElementType();
4939 std::vector<SDValue> MaskVec(NumElems);
4941 // Set elements of the shuffle mask for Val1.
4942 std::vector<unsigned> &Val1Elts = Values[Val1];
4943 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i)
4944 MaskVec[Val1Elts[i]] = DAG.getConstant(0, MaskEltVT);
4946 // Set elements of the shuffle mask for Val2.
4947 std::vector<unsigned> &Val2Elts = Values[Val2];
4948 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i)
4949 if (Val2.getOpcode() != ISD::UNDEF)
4950 MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT);
4952 MaskVec[Val2Elts[i]] = DAG.getNode(ISD::UNDEF, MaskEltVT);
4954 SDValue ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4955 &MaskVec[0], MaskVec.size());
4957 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it.
4958 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
4959 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
4960 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val1);
4961 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val2);
4962 SDValue Ops[] = { Val1, Val2, ShuffleMask };
4964 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
4965 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops, 3);
4969 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
4970 // aligned object on the stack, store each element into it, then load
4971 // the result as a vector.
4972 MVT VT = Node->getValueType(0);
4973 // Create the stack frame object.
4974 SDValue FIPtr = DAG.CreateStackTemporary(VT);
4976 // Emit a store of each element to the stack slot.
4977 SmallVector<SDValue, 8> Stores;
4978 unsigned TypeByteSize = Node->getOperand(0).getValueType().getSizeInBits()/8;
4979 // Store (in the right endianness) the elements to memory.
4980 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
4981 // Ignore undef elements.
4982 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
4984 unsigned Offset = TypeByteSize*i;
4986 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
4987 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
4989 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
4994 if (!Stores.empty()) // Not all undef elements?
4995 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4996 &Stores[0], Stores.size());
4998 StoreChain = DAG.getEntryNode();
5000 // Result is a load from the stack slot.
5001 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
5004 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
5005 SDValue Op, SDValue Amt,
5006 SDValue &Lo, SDValue &Hi) {
5007 // Expand the subcomponents.
5009 ExpandOp(Op, LHSL, LHSH);
5011 SDValue Ops[] = { LHSL, LHSH, Amt };
5012 MVT VT = LHSL.getValueType();
5013 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
5014 Hi = Lo.getValue(1);
5018 /// ExpandShift - Try to find a clever way to expand this shift operation out to
5019 /// smaller elements. If we can't find a way that is more efficient than a
5020 /// libcall on this target, return false. Otherwise, return true with the
5021 /// low-parts expanded into Lo and Hi.
5022 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op,SDValue Amt,
5023 SDValue &Lo, SDValue &Hi) {
5024 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
5025 "This is not a shift!");
5027 MVT NVT = TLI.getTypeToTransformTo(Op.getValueType());
5028 SDValue ShAmt = LegalizeOp(Amt);
5029 MVT ShTy = ShAmt.getValueType();
5030 unsigned ShBits = ShTy.getSizeInBits();
5031 unsigned VTBits = Op.getValueType().getSizeInBits();
5032 unsigned NVTBits = NVT.getSizeInBits();
5034 // Handle the case when Amt is an immediate.
5035 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
5036 unsigned Cst = CN->getValue();
5037 // Expand the incoming operand to be shifted, so that we have its parts
5039 ExpandOp(Op, InL, InH);
5043 Lo = DAG.getConstant(0, NVT);
5044 Hi = DAG.getConstant(0, NVT);
5045 } else if (Cst > NVTBits) {
5046 Lo = DAG.getConstant(0, NVT);
5047 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
5048 } else if (Cst == NVTBits) {
5049 Lo = DAG.getConstant(0, NVT);
5052 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
5053 Hi = DAG.getNode(ISD::OR, NVT,
5054 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
5055 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
5060 Lo = DAG.getConstant(0, NVT);
5061 Hi = DAG.getConstant(0, NVT);
5062 } else if (Cst > NVTBits) {
5063 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
5064 Hi = DAG.getConstant(0, NVT);
5065 } else if (Cst == NVTBits) {
5067 Hi = DAG.getConstant(0, NVT);
5069 Lo = DAG.getNode(ISD::OR, NVT,
5070 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5071 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5072 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
5077 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
5078 DAG.getConstant(NVTBits-1, ShTy));
5079 } else if (Cst > NVTBits) {
5080 Lo = DAG.getNode(ISD::SRA, NVT, InH,
5081 DAG.getConstant(Cst-NVTBits, ShTy));
5082 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5083 DAG.getConstant(NVTBits-1, ShTy));
5084 } else if (Cst == NVTBits) {
5086 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5087 DAG.getConstant(NVTBits-1, ShTy));
5089 Lo = DAG.getNode(ISD::OR, NVT,
5090 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5091 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5092 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
5098 // Okay, the shift amount isn't constant. However, if we can tell that it is
5099 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
5100 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
5101 APInt KnownZero, KnownOne;
5102 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
5104 // If we know that if any of the high bits of the shift amount are one, then
5105 // we can do this as a couple of simple shifts.
5106 if (KnownOne.intersects(Mask)) {
5107 // Mask out the high bit, which we know is set.
5108 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
5109 DAG.getConstant(~Mask, Amt.getValueType()));
5111 // Expand the incoming operand to be shifted, so that we have its parts
5113 ExpandOp(Op, InL, InH);
5116 Lo = DAG.getConstant(0, NVT); // Low part is zero.
5117 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
5120 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
5121 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
5124 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
5125 DAG.getConstant(NVTBits-1, Amt.getValueType()));
5126 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
5131 // If we know that the high bits of the shift amount are all zero, then we can
5132 // do this as a couple of simple shifts.
5133 if ((KnownZero & Mask) == Mask) {
5135 SDValue Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
5136 DAG.getConstant(NVTBits, Amt.getValueType()),
5139 // Expand the incoming operand to be shifted, so that we have its parts
5141 ExpandOp(Op, InL, InH);
5144 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
5145 Hi = DAG.getNode(ISD::OR, NVT,
5146 DAG.getNode(ISD::SHL, NVT, InH, Amt),
5147 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
5150 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
5151 Lo = DAG.getNode(ISD::OR, NVT,
5152 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5153 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5156 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
5157 Lo = DAG.getNode(ISD::OR, NVT,
5158 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5159 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5168 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
5169 // does not fit into a register, return the lo part and set the hi part to the
5170 // by-reg argument. If it does fit into a single register, return the result
5171 // and leave the Hi part unset.
5172 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
5173 bool isSigned, SDValue &Hi) {
5174 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
5175 // The input chain to this libcall is the entry node of the function.
5176 // Legalizing the call will automatically add the previous call to the
5178 SDValue InChain = DAG.getEntryNode();
5180 TargetLowering::ArgListTy Args;
5181 TargetLowering::ArgListEntry Entry;
5182 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5183 MVT ArgVT = Node->getOperand(i).getValueType();
5184 const Type *ArgTy = ArgVT.getTypeForMVT();
5185 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
5186 Entry.isSExt = isSigned;
5187 Entry.isZExt = !isSigned;
5188 Args.push_back(Entry);
5190 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
5191 TLI.getPointerTy());
5193 // Splice the libcall in wherever FindInputOutputChains tells us to.
5194 const Type *RetTy = Node->getValueType(0).getTypeForMVT();
5195 std::pair<SDValue,SDValue> CallInfo =
5196 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, CallingConv::C,
5197 false, Callee, Args, DAG);
5199 // Legalize the call sequence, starting with the chain. This will advance
5200 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
5201 // was added by LowerCallTo (guaranteeing proper serialization of calls).
5202 LegalizeOp(CallInfo.second);
5204 switch (getTypeAction(CallInfo.first.getValueType())) {
5205 default: assert(0 && "Unknown thing");
5207 Result = CallInfo.first;
5210 ExpandOp(CallInfo.first, Result, Hi);
5216 /// LegalizeINT_TO_FP - Legalize a [US]INT_TO_FP operation.
5218 SDValue SelectionDAGLegalize::
5219 LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op) {
5220 bool isCustom = false;
5222 switch (getTypeAction(Op.getValueType())) {
5224 switch (TLI.getOperationAction(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5225 Op.getValueType())) {
5226 default: assert(0 && "Unknown operation action!");
5227 case TargetLowering::Custom:
5230 case TargetLowering::Legal:
5231 Tmp1 = LegalizeOp(Op);
5233 Result = DAG.UpdateNodeOperands(Result, Tmp1);
5235 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5238 Tmp1 = TLI.LowerOperation(Result, DAG);
5239 if (Tmp1.Val) Result = Tmp1;
5242 case TargetLowering::Expand:
5243 Result = ExpandLegalINT_TO_FP(isSigned, LegalizeOp(Op), DestTy);
5245 case TargetLowering::Promote:
5246 Result = PromoteLegalINT_TO_FP(LegalizeOp(Op), DestTy, isSigned);
5251 Result = ExpandIntToFP(isSigned, DestTy, Op);
5254 Tmp1 = PromoteOp(Op);
5256 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
5257 Tmp1, DAG.getValueType(Op.getValueType()));
5259 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
5263 Result = DAG.UpdateNodeOperands(Result, Tmp1);
5265 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5267 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
5273 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
5275 SDValue SelectionDAGLegalize::
5276 ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source) {
5277 MVT SourceVT = Source.getValueType();
5278 bool ExpandSource = getTypeAction(SourceVT) == Expand;
5280 // Expand unsupported int-to-fp vector casts by unrolling them.
5281 if (DestTy.isVector()) {
5283 return LegalizeOp(UnrollVectorOp(Source));
5284 MVT DestEltTy = DestTy.getVectorElementType();
5285 if (DestTy.getVectorNumElements() == 1) {
5286 SDValue Scalar = ScalarizeVectorOp(Source);
5287 SDValue Result = LegalizeINT_TO_FP(SDValue(), isSigned,
5289 return DAG.getNode(ISD::BUILD_VECTOR, DestTy, Result);
5292 SplitVectorOp(Source, Lo, Hi);
5293 MVT SplitDestTy = MVT::getVectorVT(DestEltTy,
5294 DestTy.getVectorNumElements() / 2);
5295 SDValue LoResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, Lo);
5296 SDValue HiResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, Hi);
5297 return LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, DestTy, LoResult, HiResult));
5300 // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc.
5301 if (!isSigned && SourceVT != MVT::i32) {
5302 // The integer value loaded will be incorrectly if the 'sign bit' of the
5303 // incoming integer is set. To handle this, we dynamically test to see if
5304 // it is set, and, if so, add a fudge factor.
5308 ExpandOp(Source, Lo, Hi);
5309 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi);
5311 // The comparison for the sign bit will use the entire operand.
5315 // If this is unsigned, and not supported, first perform the conversion to
5316 // signed, then adjust the result if the sign bit is set.
5317 SDValue SignedConv = ExpandIntToFP(true, DestTy, Source);
5319 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
5320 DAG.getConstant(0, Hi.getValueType()),
5322 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5323 SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5324 SignSet, Four, Zero);
5325 uint64_t FF = 0x5f800000ULL;
5326 if (TLI.isLittleEndian()) FF <<= 32;
5327 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5329 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5330 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5332 if (DestTy == MVT::f32)
5333 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5334 PseudoSourceValue::getConstantPool(), 0);
5335 else if (DestTy.bitsGT(MVT::f32))
5336 // FIXME: Avoid the extend by construction the right constantpool?
5337 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
5339 PseudoSourceValue::getConstantPool(), 0,
5342 assert(0 && "Unexpected conversion");
5344 MVT SCVT = SignedConv.getValueType();
5345 if (SCVT != DestTy) {
5346 // Destination type needs to be expanded as well. The FADD now we are
5347 // constructing will be expanded into a libcall.
5348 if (SCVT.getSizeInBits() != DestTy.getSizeInBits()) {
5349 assert(SCVT.getSizeInBits() * 2 == DestTy.getSizeInBits());
5350 SignedConv = DAG.getNode(ISD::BUILD_PAIR, DestTy,
5351 SignedConv, SignedConv.getValue(1));
5353 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
5355 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
5358 // Check to see if the target has a custom way to lower this. If so, use it.
5359 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) {
5360 default: assert(0 && "This action not implemented for this operation!");
5361 case TargetLowering::Legal:
5362 case TargetLowering::Expand:
5363 break; // This case is handled below.
5364 case TargetLowering::Custom: {
5365 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
5368 return LegalizeOp(NV);
5369 break; // The target decided this was legal after all
5373 // Expand the source, then glue it back together for the call. We must expand
5374 // the source in case it is shared (this pass of legalize must traverse it).
5376 SDValue SrcLo, SrcHi;
5377 ExpandOp(Source, SrcLo, SrcHi);
5378 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, SrcLo, SrcHi);
5381 RTLIB::Libcall LC = isSigned ?
5382 RTLIB::getSINTTOFP(SourceVT, DestTy) :
5383 RTLIB::getUINTTOFP(SourceVT, DestTy);
5384 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unknown int value type");
5386 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
5388 SDValue Result = ExpandLibCall(LC, Source.Val, isSigned, HiPart);
5389 if (Result.getValueType() != DestTy && HiPart.Val)
5390 Result = DAG.getNode(ISD::BUILD_PAIR, DestTy, Result, HiPart);
5394 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
5395 /// INT_TO_FP operation of the specified operand when the target requests that
5396 /// we expand it. At this point, we know that the result and operand types are
5397 /// legal for the target.
5398 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
5401 if (Op0.getValueType() == MVT::i32) {
5402 // simple 32-bit [signed|unsigned] integer to float/double expansion
5404 // Get the stack frame index of a 8 byte buffer.
5405 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
5407 // word offset constant for Hi/Lo address computation
5408 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
5409 // set up Hi and Lo (into buffer) address based on endian
5410 SDValue Hi = StackSlot;
5411 SDValue Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
5412 if (TLI.isLittleEndian())
5415 // if signed map to unsigned space
5418 // constant used to invert sign bit (signed to unsigned mapping)
5419 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
5420 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
5424 // store the lo of the constructed double - based on integer input
5425 SDValue Store1 = DAG.getStore(DAG.getEntryNode(),
5426 Op0Mapped, Lo, NULL, 0);
5427 // initial hi portion of constructed double
5428 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
5429 // store the hi of the constructed double - biased exponent
5430 SDValue Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
5431 // load the constructed double
5432 SDValue Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
5433 // FP constant to bias correct the final result
5434 SDValue Bias = DAG.getConstantFP(isSigned ?
5435 BitsToDouble(0x4330000080000000ULL)
5436 : BitsToDouble(0x4330000000000000ULL),
5438 // subtract the bias
5439 SDValue Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
5442 // handle final rounding
5443 if (DestVT == MVT::f64) {
5446 } else if (DestVT.bitsLT(MVT::f64)) {
5447 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub,
5448 DAG.getIntPtrConstant(0));
5449 } else if (DestVT.bitsGT(MVT::f64)) {
5450 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
5454 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
5455 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
5457 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Op0), Op0,
5458 DAG.getConstant(0, Op0.getValueType()),
5460 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5461 SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5462 SignSet, Four, Zero);
5464 // If the sign bit of the integer is set, the large number will be treated
5465 // as a negative number. To counteract this, the dynamic code adds an
5466 // offset depending on the data type.
5468 switch (Op0.getValueType().getSimpleVT()) {
5469 default: assert(0 && "Unsupported integer type!");
5470 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
5471 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
5472 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
5473 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
5475 if (TLI.isLittleEndian()) FF <<= 32;
5476 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5478 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5479 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5481 if (DestVT == MVT::f32)
5482 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5483 PseudoSourceValue::getConstantPool(), 0);
5486 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT,
5487 DAG.getEntryNode(), CPIdx,
5488 PseudoSourceValue::getConstantPool(), 0,
5492 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
5495 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
5496 /// *INT_TO_FP operation of the specified operand when the target requests that
5497 /// we promote it. At this point, we know that the result and operand types are
5498 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
5499 /// operation that takes a larger input.
5500 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
5503 // First step, figure out the appropriate *INT_TO_FP operation to use.
5504 MVT NewInTy = LegalOp.getValueType();
5506 unsigned OpToUse = 0;
5508 // Scan for the appropriate larger type to use.
5510 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
5511 assert(NewInTy.isInteger() && "Ran out of possibilities!");
5513 // If the target supports SINT_TO_FP of this type, use it.
5514 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
5516 case TargetLowering::Legal:
5517 if (!TLI.isTypeLegal(NewInTy))
5518 break; // Can't use this datatype.
5520 case TargetLowering::Custom:
5521 OpToUse = ISD::SINT_TO_FP;
5525 if (isSigned) continue;
5527 // If the target supports UINT_TO_FP of this type, use it.
5528 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
5530 case TargetLowering::Legal:
5531 if (!TLI.isTypeLegal(NewInTy))
5532 break; // Can't use this datatype.
5534 case TargetLowering::Custom:
5535 OpToUse = ISD::UINT_TO_FP;
5540 // Otherwise, try a larger type.
5543 // Okay, we found the operation and type to use. Zero extend our input to the
5544 // desired type then run the operation on it.
5545 return DAG.getNode(OpToUse, DestVT,
5546 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
5550 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
5551 /// FP_TO_*INT operation of the specified operand when the target requests that
5552 /// we promote it. At this point, we know that the result and operand types are
5553 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
5554 /// operation that returns a larger result.
5555 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
5558 // First step, figure out the appropriate FP_TO*INT operation to use.
5559 MVT NewOutTy = DestVT;
5561 unsigned OpToUse = 0;
5563 // Scan for the appropriate larger type to use.
5565 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1);
5566 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
5568 // If the target supports FP_TO_SINT returning this type, use it.
5569 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
5571 case TargetLowering::Legal:
5572 if (!TLI.isTypeLegal(NewOutTy))
5573 break; // Can't use this datatype.
5575 case TargetLowering::Custom:
5576 OpToUse = ISD::FP_TO_SINT;
5581 // If the target supports FP_TO_UINT of this type, use it.
5582 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
5584 case TargetLowering::Legal:
5585 if (!TLI.isTypeLegal(NewOutTy))
5586 break; // Can't use this datatype.
5588 case TargetLowering::Custom:
5589 OpToUse = ISD::FP_TO_UINT;
5594 // Otherwise, try a larger type.
5598 // Okay, we found the operation and type to use.
5599 SDValue Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp);
5601 // If the operation produces an invalid type, it must be custom lowered. Use
5602 // the target lowering hooks to expand it. Just keep the low part of the
5603 // expanded operation, we know that we're truncating anyway.
5604 if (getTypeAction(NewOutTy) == Expand) {
5605 Operation = SDValue(TLI.ReplaceNodeResults(Operation.Val, DAG), 0);
5606 assert(Operation.Val && "Didn't return anything");
5609 // Truncate the result of the extended FP_TO_*INT operation to the desired
5611 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation);
5614 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
5616 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op) {
5617 MVT VT = Op.getValueType();
5618 MVT SHVT = TLI.getShiftAmountTy();
5619 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
5620 switch (VT.getSimpleVT()) {
5621 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
5623 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5624 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5625 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
5627 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5628 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5629 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5630 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5631 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
5632 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
5633 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5634 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5635 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5637 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
5638 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
5639 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5640 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5641 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5642 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5643 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
5644 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
5645 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
5646 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
5647 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
5648 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
5649 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
5650 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
5651 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
5652 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
5653 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5654 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5655 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
5656 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5657 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
5661 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
5663 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op) {
5665 default: assert(0 && "Cannot expand this yet!");
5667 static const uint64_t mask[6] = {
5668 0x5555555555555555ULL, 0x3333333333333333ULL,
5669 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
5670 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
5672 MVT VT = Op.getValueType();
5673 MVT ShVT = TLI.getShiftAmountTy();
5674 unsigned len = VT.getSizeInBits();
5675 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5676 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
5677 SDValue Tmp2 = DAG.getConstant(mask[i], VT);
5678 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5679 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
5680 DAG.getNode(ISD::AND, VT,
5681 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
5686 // for now, we do this:
5687 // x = x | (x >> 1);
5688 // x = x | (x >> 2);
5690 // x = x | (x >>16);
5691 // x = x | (x >>32); // for 64-bit input
5692 // return popcount(~x);
5694 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
5695 MVT VT = Op.getValueType();
5696 MVT ShVT = TLI.getShiftAmountTy();
5697 unsigned len = VT.getSizeInBits();
5698 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5699 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5700 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
5702 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
5703 return DAG.getNode(ISD::CTPOP, VT, Op);
5706 // for now, we use: { return popcount(~x & (x - 1)); }
5707 // unless the target has ctlz but not ctpop, in which case we use:
5708 // { return 32 - nlz(~x & (x-1)); }
5709 // see also http://www.hackersdelight.org/HDcode/ntz.cc
5710 MVT VT = Op.getValueType();
5711 SDValue Tmp2 = DAG.getConstant(~0ULL, VT);
5712 SDValue Tmp3 = DAG.getNode(ISD::AND, VT,
5713 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
5714 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
5715 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
5716 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
5717 TLI.isOperationLegal(ISD::CTLZ, VT))
5718 return DAG.getNode(ISD::SUB, VT,
5719 DAG.getConstant(VT.getSizeInBits(), VT),
5720 DAG.getNode(ISD::CTLZ, VT, Tmp3));
5721 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
5726 /// ExpandOp - Expand the specified SDValue into its two component pieces
5727 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
5728 /// LegalizeNodes map is filled in for any results that are not expanded, the
5729 /// ExpandedNodes map is filled in for any results that are expanded, and the
5730 /// Lo/Hi values are returned.
5731 void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
5732 MVT VT = Op.getValueType();
5733 MVT NVT = TLI.getTypeToTransformTo(VT);
5734 SDNode *Node = Op.Val;
5735 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
5736 assert(((NVT.isInteger() && NVT.bitsLT(VT)) || VT.isFloatingPoint() ||
5737 VT.isVector()) && "Cannot expand to FP value or to larger int value!");
5739 // See if we already expanded it.
5740 DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator I
5741 = ExpandedNodes.find(Op);
5742 if (I != ExpandedNodes.end()) {
5743 Lo = I->second.first;
5744 Hi = I->second.second;
5748 switch (Node->getOpcode()) {
5749 case ISD::CopyFromReg:
5750 assert(0 && "CopyFromReg must be legal!");
5751 case ISD::FP_ROUND_INREG:
5752 if (VT == MVT::ppcf128 &&
5753 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
5754 TargetLowering::Custom) {
5755 SDValue SrcLo, SrcHi, Src;
5756 ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
5757 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi);
5758 SDValue Result = TLI.LowerOperation(
5759 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG);
5760 assert(Result.Val->getOpcode() == ISD::BUILD_PAIR);
5761 Lo = Result.Val->getOperand(0);
5762 Hi = Result.Val->getOperand(1);
5768 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
5770 assert(0 && "Do not know how to expand this operator!");
5772 case ISD::EXTRACT_ELEMENT:
5773 ExpandOp(Node->getOperand(0), Lo, Hi);
5774 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
5775 return ExpandOp(Hi, Lo, Hi);
5776 return ExpandOp(Lo, Lo, Hi);
5777 case ISD::EXTRACT_VECTOR_ELT:
5778 assert(VT==MVT::i64 && "Do not know how to expand this operator!");
5779 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types.
5780 Lo = ExpandEXTRACT_VECTOR_ELT(Op);
5781 return ExpandOp(Lo, Lo, Hi);
5783 Lo = DAG.getNode(ISD::UNDEF, NVT);
5784 Hi = DAG.getNode(ISD::UNDEF, NVT);
5786 case ISD::Constant: {
5787 unsigned NVTBits = NVT.getSizeInBits();
5788 const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue();
5789 Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT);
5790 Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT);
5793 case ISD::ConstantFP: {
5794 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
5795 if (CFP->getValueType(0) == MVT::ppcf128) {
5796 APInt api = CFP->getValueAPF().convertToAPInt();
5797 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
5799 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
5803 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
5804 if (getTypeAction(Lo.getValueType()) == Expand)
5805 ExpandOp(Lo, Lo, Hi);
5808 case ISD::BUILD_PAIR:
5809 // Return the operands.
5810 Lo = Node->getOperand(0);
5811 Hi = Node->getOperand(1);
5814 case ISD::MERGE_VALUES:
5815 if (Node->getNumValues() == 1) {
5816 ExpandOp(Op.getOperand(0), Lo, Hi);
5819 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y)
5820 assert(Op.ResNo == 0 && Node->getNumValues() == 2 &&
5821 Op.getValue(1).getValueType() == MVT::Other &&
5822 "unhandled MERGE_VALUES");
5823 ExpandOp(Op.getOperand(0), Lo, Hi);
5824 // Remember that we legalized the chain.
5825 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1)));
5828 case ISD::SIGN_EXTEND_INREG:
5829 ExpandOp(Node->getOperand(0), Lo, Hi);
5830 // sext_inreg the low part if needed.
5831 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
5833 // The high part gets the sign extension from the lo-part. This handles
5834 // things like sextinreg V:i64 from i8.
5835 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5836 DAG.getConstant(NVT.getSizeInBits()-1,
5837 TLI.getShiftAmountTy()));
5841 ExpandOp(Node->getOperand(0), Lo, Hi);
5842 SDValue TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
5843 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
5849 ExpandOp(Node->getOperand(0), Lo, Hi);
5850 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
5851 DAG.getNode(ISD::CTPOP, NVT, Lo),
5852 DAG.getNode(ISD::CTPOP, NVT, Hi));
5853 Hi = DAG.getConstant(0, NVT);
5857 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
5858 ExpandOp(Node->getOperand(0), Lo, Hi);
5859 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
5860 SDValue HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
5861 SDValue TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(HLZ), HLZ, BitsC,
5863 SDValue LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
5864 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
5866 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
5867 Hi = DAG.getConstant(0, NVT);
5872 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
5873 ExpandOp(Node->getOperand(0), Lo, Hi);
5874 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
5875 SDValue LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
5876 SDValue BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(LTZ), LTZ, BitsC,
5878 SDValue HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
5879 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
5881 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
5882 Hi = DAG.getConstant(0, NVT);
5887 SDValue Ch = Node->getOperand(0); // Legalize the chain.
5888 SDValue Ptr = Node->getOperand(1); // Legalize the pointer.
5889 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
5890 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
5892 // Remember that we legalized the chain.
5893 Hi = LegalizeOp(Hi);
5894 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
5895 if (TLI.isBigEndian())
5901 LoadSDNode *LD = cast<LoadSDNode>(Node);
5902 SDValue Ch = LD->getChain(); // Legalize the chain.
5903 SDValue Ptr = LD->getBasePtr(); // Legalize the pointer.
5904 ISD::LoadExtType ExtType = LD->getExtensionType();
5905 const Value *SV = LD->getSrcValue();
5906 int SVOffset = LD->getSrcValueOffset();
5907 unsigned Alignment = LD->getAlignment();
5908 bool isVolatile = LD->isVolatile();
5910 if (ExtType == ISD::NON_EXTLOAD) {
5911 Lo = DAG.getLoad(NVT, Ch, Ptr, SV, SVOffset,
5912 isVolatile, Alignment);
5913 if (VT == MVT::f32 || VT == MVT::f64) {
5914 // f32->i32 or f64->i64 one to one expansion.
5915 // Remember that we legalized the chain.
5916 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
5917 // Recursively expand the new load.
5918 if (getTypeAction(NVT) == Expand)
5919 ExpandOp(Lo, Lo, Hi);
5923 // Increment the pointer to the other half.
5924 unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8;
5925 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
5926 DAG.getIntPtrConstant(IncrementSize));
5927 SVOffset += IncrementSize;
5928 Alignment = MinAlign(Alignment, IncrementSize);
5929 Hi = DAG.getLoad(NVT, Ch, Ptr, SV, SVOffset,
5930 isVolatile, Alignment);
5932 // Build a factor node to remember that this load is independent of the
5934 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
5937 // Remember that we legalized the chain.
5938 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
5939 if (TLI.isBigEndian())
5942 MVT EVT = LD->getMemoryVT();
5944 if ((VT == MVT::f64 && EVT == MVT::f32) ||
5945 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
5946 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
5947 SDValue Load = DAG.getLoad(EVT, Ch, Ptr, SV,
5948 SVOffset, isVolatile, Alignment);
5949 // Remember that we legalized the chain.
5950 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Load.getValue(1)));
5951 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
5956 Lo = DAG.getLoad(NVT, Ch, Ptr, SV,
5957 SVOffset, isVolatile, Alignment);
5959 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, SV,
5960 SVOffset, EVT, isVolatile,
5963 // Remember that we legalized the chain.
5964 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
5966 if (ExtType == ISD::SEXTLOAD) {
5967 // The high part is obtained by SRA'ing all but one of the bits of the
5969 unsigned LoSize = Lo.getValueType().getSizeInBits();
5970 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5971 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5972 } else if (ExtType == ISD::ZEXTLOAD) {
5973 // The high part is just a zero.
5974 Hi = DAG.getConstant(0, NVT);
5975 } else /* if (ExtType == ISD::EXTLOAD) */ {
5976 // The high part is undefined.
5977 Hi = DAG.getNode(ISD::UNDEF, NVT);
5984 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
5985 SDValue LL, LH, RL, RH;
5986 ExpandOp(Node->getOperand(0), LL, LH);
5987 ExpandOp(Node->getOperand(1), RL, RH);
5988 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
5989 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
5993 SDValue LL, LH, RL, RH;
5994 ExpandOp(Node->getOperand(1), LL, LH);
5995 ExpandOp(Node->getOperand(2), RL, RH);
5996 if (getTypeAction(NVT) == Expand)
5997 NVT = TLI.getTypeToExpandTo(NVT);
5998 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
6000 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
6003 case ISD::SELECT_CC: {
6004 SDValue TL, TH, FL, FH;
6005 ExpandOp(Node->getOperand(2), TL, TH);
6006 ExpandOp(Node->getOperand(3), FL, FH);
6007 if (getTypeAction(NVT) == Expand)
6008 NVT = TLI.getTypeToExpandTo(NVT);
6009 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
6010 Node->getOperand(1), TL, FL, Node->getOperand(4));
6012 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
6013 Node->getOperand(1), TH, FH, Node->getOperand(4));
6016 case ISD::ANY_EXTEND:
6017 // The low part is any extension of the input (which degenerates to a copy).
6018 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
6019 // The high part is undefined.
6020 Hi = DAG.getNode(ISD::UNDEF, NVT);
6022 case ISD::SIGN_EXTEND: {
6023 // The low part is just a sign extension of the input (which degenerates to
6025 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
6027 // The high part is obtained by SRA'ing all but one of the bits of the lo
6029 unsigned LoSize = Lo.getValueType().getSizeInBits();
6030 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6031 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6034 case ISD::ZERO_EXTEND:
6035 // The low part is just a zero extension of the input (which degenerates to
6037 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
6039 // The high part is just a zero.
6040 Hi = DAG.getConstant(0, NVT);
6043 case ISD::TRUNCATE: {
6044 // The input value must be larger than this value. Expand *it*.
6046 ExpandOp(Node->getOperand(0), NewLo, Hi);
6048 // The low part is now either the right size, or it is closer. If not the
6049 // right size, make an illegal truncate so we recursively expand it.
6050 if (NewLo.getValueType() != Node->getValueType(0))
6051 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
6052 ExpandOp(NewLo, Lo, Hi);
6056 case ISD::BIT_CONVERT: {
6058 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
6059 // If the target wants to, allow it to lower this itself.
6060 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6061 case Expand: assert(0 && "cannot expand FP!");
6062 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
6063 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
6065 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
6068 // f32 / f64 must be expanded to i32 / i64.
6069 if (VT == MVT::f32 || VT == MVT::f64) {
6070 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6071 if (getTypeAction(NVT) == Expand)
6072 ExpandOp(Lo, Lo, Hi);
6076 // If source operand will be expanded to the same type as VT, i.e.
6077 // i64 <- f64, i32 <- f32, expand the source operand instead.
6078 MVT VT0 = Node->getOperand(0).getValueType();
6079 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
6080 ExpandOp(Node->getOperand(0), Lo, Hi);
6084 // Turn this into a load/store pair by default.
6086 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT);
6088 ExpandOp(Tmp, Lo, Hi);
6092 case ISD::READCYCLECOUNTER: {
6093 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
6094 TargetLowering::Custom &&
6095 "Must custom expand ReadCycleCounter");
6096 SDValue Tmp = TLI.LowerOperation(Op, DAG);
6097 assert(Tmp.Val && "Node must be custom expanded!");
6098 ExpandOp(Tmp.getValue(0), Lo, Hi);
6099 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6100 LegalizeOp(Tmp.getValue(1)));
6104 case ISD::ATOMIC_CMP_SWAP: {
6105 SDValue Tmp = TLI.LowerOperation(Op, DAG);
6106 assert(Tmp.Val && "Node must be custom expanded!");
6107 ExpandOp(Tmp.getValue(0), Lo, Hi);
6108 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6109 LegalizeOp(Tmp.getValue(1)));
6115 // These operators cannot be expanded directly, emit them as calls to
6116 // library functions.
6117 case ISD::FP_TO_SINT: {
6118 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
6120 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6121 case Expand: assert(0 && "cannot expand FP!");
6122 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6123 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6126 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
6128 // Now that the custom expander is done, expand the result, which is still
6131 ExpandOp(Op, Lo, Hi);
6136 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Node->getOperand(0).getValueType(),
6138 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected uint-to-fp conversion!");
6139 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6143 case ISD::FP_TO_UINT: {
6144 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
6146 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6147 case Expand: assert(0 && "cannot expand FP!");
6148 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6149 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6152 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
6154 // Now that the custom expander is done, expand the result.
6156 ExpandOp(Op, Lo, Hi);
6161 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Node->getOperand(0).getValueType(),
6163 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
6164 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6169 // If the target wants custom lowering, do so.
6170 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6171 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
6172 SDValue Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
6173 Op = TLI.LowerOperation(Op, DAG);
6175 // Now that the custom expander is done, expand the result, which is
6177 ExpandOp(Op, Lo, Hi);
6182 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
6183 // this X << 1 as X+X.
6184 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
6185 if (ShAmt->getAPIntValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
6186 TLI.isOperationLegal(ISD::ADDE, NVT)) {
6187 SDValue LoOps[2], HiOps[3];
6188 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
6189 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
6190 LoOps[1] = LoOps[0];
6191 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6193 HiOps[1] = HiOps[0];
6194 HiOps[2] = Lo.getValue(1);
6195 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6200 // If we can emit an efficient shift operation, do so now.
6201 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6204 // If this target supports SHL_PARTS, use it.
6205 TargetLowering::LegalizeAction Action =
6206 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
6207 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6208 Action == TargetLowering::Custom) {
6209 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6213 // Otherwise, emit a libcall.
6214 Lo = ExpandLibCall(RTLIB::SHL_I64, Node, false/*left shift=unsigned*/, Hi);
6219 // If the target wants custom lowering, do so.
6220 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6221 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
6222 SDValue Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
6223 Op = TLI.LowerOperation(Op, DAG);
6225 // Now that the custom expander is done, expand the result, which is
6227 ExpandOp(Op, Lo, Hi);
6232 // If we can emit an efficient shift operation, do so now.
6233 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
6236 // If this target supports SRA_PARTS, use it.
6237 TargetLowering::LegalizeAction Action =
6238 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
6239 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6240 Action == TargetLowering::Custom) {
6241 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6245 // Otherwise, emit a libcall.
6246 Lo = ExpandLibCall(RTLIB::SRA_I64, Node, true/*ashr is signed*/, Hi);
6251 // If the target wants custom lowering, do so.
6252 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6253 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
6254 SDValue Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
6255 Op = TLI.LowerOperation(Op, DAG);
6257 // Now that the custom expander is done, expand the result, which is
6259 ExpandOp(Op, Lo, Hi);
6264 // If we can emit an efficient shift operation, do so now.
6265 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6268 // If this target supports SRL_PARTS, use it.
6269 TargetLowering::LegalizeAction Action =
6270 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
6271 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6272 Action == TargetLowering::Custom) {
6273 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6277 // Otherwise, emit a libcall.
6278 Lo = ExpandLibCall(RTLIB::SRL_I64, Node, false/*lshr is unsigned*/, Hi);
6284 // If the target wants to custom expand this, let them.
6285 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
6286 TargetLowering::Custom) {
6287 SDValue Result = TLI.LowerOperation(Op, DAG);
6289 ExpandOp(Result, Lo, Hi);
6294 // Expand the subcomponents.
6295 SDValue LHSL, LHSH, RHSL, RHSH;
6296 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6297 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6298 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6299 SDValue LoOps[2], HiOps[3];
6304 if (Node->getOpcode() == ISD::ADD) {
6305 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6306 HiOps[2] = Lo.getValue(1);
6307 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6309 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6310 HiOps[2] = Lo.getValue(1);
6311 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6318 // Expand the subcomponents.
6319 SDValue LHSL, LHSH, RHSL, RHSH;
6320 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6321 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6322 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6323 SDValue LoOps[2] = { LHSL, RHSL };
6324 SDValue HiOps[3] = { LHSH, RHSH };
6326 if (Node->getOpcode() == ISD::ADDC) {
6327 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6328 HiOps[2] = Lo.getValue(1);
6329 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6331 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6332 HiOps[2] = Lo.getValue(1);
6333 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6335 // Remember that we legalized the flag.
6336 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6341 // Expand the subcomponents.
6342 SDValue LHSL, LHSH, RHSL, RHSH;
6343 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6344 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6345 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6346 SDValue LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
6347 SDValue HiOps[3] = { LHSH, RHSH };
6349 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
6350 HiOps[2] = Lo.getValue(1);
6351 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
6353 // Remember that we legalized the flag.
6354 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6358 // If the target wants to custom expand this, let them.
6359 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
6360 SDValue New = TLI.LowerOperation(Op, DAG);
6362 ExpandOp(New, Lo, Hi);
6367 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
6368 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
6369 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
6370 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
6371 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
6372 SDValue LL, LH, RL, RH;
6373 ExpandOp(Node->getOperand(0), LL, LH);
6374 ExpandOp(Node->getOperand(1), RL, RH);
6375 unsigned OuterBitSize = Op.getValueSizeInBits();
6376 unsigned InnerBitSize = RH.getValueSizeInBits();
6377 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
6378 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
6379 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
6380 if (DAG.MaskedValueIsZero(Node->getOperand(0), HighMask) &&
6381 DAG.MaskedValueIsZero(Node->getOperand(1), HighMask)) {
6382 // The inputs are both zero-extended.
6384 // We can emit a umul_lohi.
6385 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6386 Hi = SDValue(Lo.Val, 1);
6390 // We can emit a mulhu+mul.
6391 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6392 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6396 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
6397 // The input values are both sign-extended.
6399 // We can emit a smul_lohi.
6400 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6401 Hi = SDValue(Lo.Val, 1);
6405 // We can emit a mulhs+mul.
6406 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6407 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
6412 // Lo,Hi = umul LHS, RHS.
6413 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
6414 DAG.getVTList(NVT, NVT), LL, RL);
6416 Hi = UMulLOHI.getValue(1);
6417 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6418 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6419 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6420 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6424 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6425 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6426 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6427 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6428 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6429 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6434 // If nothing else, we can make a libcall.
6435 Lo = ExpandLibCall(RTLIB::MUL_I64, Node, false/*sign irrelevant*/, Hi);
6439 Lo = ExpandLibCall(RTLIB::SDIV_I64, Node, true, Hi);
6442 Lo = ExpandLibCall(RTLIB::UDIV_I64, Node, true, Hi);
6445 Lo = ExpandLibCall(RTLIB::SREM_I64, Node, true, Hi);
6448 Lo = ExpandLibCall(RTLIB::UREM_I64, Node, true, Hi);
6452 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::ADD_F32,
6455 RTLIB::ADD_PPCF128),
6459 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::SUB_F32,
6462 RTLIB::SUB_PPCF128),
6466 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::MUL_F32,
6469 RTLIB::MUL_PPCF128),
6473 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::DIV_F32,
6476 RTLIB::DIV_PPCF128),
6479 case ISD::FP_EXTEND: {
6480 if (VT == MVT::ppcf128) {
6481 assert(Node->getOperand(0).getValueType()==MVT::f32 ||
6482 Node->getOperand(0).getValueType()==MVT::f64);
6483 const uint64_t zero = 0;
6484 if (Node->getOperand(0).getValueType()==MVT::f32)
6485 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0));
6487 Hi = Node->getOperand(0);
6488 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6491 RTLIB::Libcall LC = RTLIB::getFPEXT(Node->getOperand(0).getValueType(), VT);
6492 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!");
6493 Lo = ExpandLibCall(LC, Node, true, Hi);
6496 case ISD::FP_ROUND: {
6497 RTLIB::Libcall LC = RTLIB::getFPROUND(Node->getOperand(0).getValueType(),
6499 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!");
6500 Lo = ExpandLibCall(LC, Node, true, Hi);
6504 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::POWI_F32,
6507 RTLIB::POWI_PPCF128),
6513 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6514 switch(Node->getOpcode()) {
6516 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
6517 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
6520 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
6521 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
6524 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
6525 RTLIB::COS_F80, RTLIB::COS_PPCF128);
6527 default: assert(0 && "Unreachable!");
6529 Lo = ExpandLibCall(LC, Node, false, Hi);
6533 if (VT == MVT::ppcf128) {
6535 ExpandOp(Node->getOperand(0), Lo, Tmp);
6536 Hi = DAG.getNode(ISD::FABS, NVT, Tmp);
6537 // lo = hi==fabs(hi) ? lo : -lo;
6538 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp,
6539 Lo, DAG.getNode(ISD::FNEG, NVT, Lo),
6540 DAG.getCondCode(ISD::SETEQ));
6543 SDValue Mask = (VT == MVT::f64)
6544 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
6545 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
6546 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6547 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6548 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
6549 if (getTypeAction(NVT) == Expand)
6550 ExpandOp(Lo, Lo, Hi);
6554 if (VT == MVT::ppcf128) {
6555 ExpandOp(Node->getOperand(0), Lo, Hi);
6556 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo);
6557 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi);
6560 SDValue Mask = (VT == MVT::f64)
6561 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
6562 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
6563 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6564 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6565 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
6566 if (getTypeAction(NVT) == Expand)
6567 ExpandOp(Lo, Lo, Hi);
6570 case ISD::FCOPYSIGN: {
6571 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
6572 if (getTypeAction(NVT) == Expand)
6573 ExpandOp(Lo, Lo, Hi);
6576 case ISD::SINT_TO_FP:
6577 case ISD::UINT_TO_FP: {
6578 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
6579 MVT SrcVT = Node->getOperand(0).getValueType();
6581 // Promote the operand if needed. Do this before checking for
6582 // ppcf128 so conversions of i16 and i8 work.
6583 if (getTypeAction(SrcVT) == Promote) {
6584 SDValue Tmp = PromoteOp(Node->getOperand(0));
6586 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
6587 DAG.getValueType(SrcVT))
6588 : DAG.getZeroExtendInReg(Tmp, SrcVT);
6589 Node = DAG.UpdateNodeOperands(Op, Tmp).Val;
6590 SrcVT = Node->getOperand(0).getValueType();
6593 if (VT == MVT::ppcf128 && SrcVT == MVT::i32) {
6594 static const uint64_t zero = 0;
6596 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6597 Node->getOperand(0)));
6598 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6600 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
6601 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6602 Node->getOperand(0)));
6603 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6604 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6605 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
6606 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6607 DAG.getConstant(0, MVT::i32),
6608 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6610 APFloat(APInt(128, 2, TwoE32)),
6613 DAG.getCondCode(ISD::SETLT)),
6618 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) {
6619 // si64->ppcf128 done by libcall, below
6620 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
6621 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)),
6623 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6624 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
6625 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6626 DAG.getConstant(0, MVT::i64),
6627 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6629 APFloat(APInt(128, 2, TwoE64)),
6632 DAG.getCondCode(ISD::SETLT)),
6637 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
6638 Node->getOperand(0));
6639 if (getTypeAction(Lo.getValueType()) == Expand)
6640 // float to i32 etc. can be 'expanded' to a single node.
6641 ExpandOp(Lo, Lo, Hi);
6646 // Make sure the resultant values have been legalized themselves, unless this
6647 // is a type that requires multi-step expansion.
6648 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
6649 Lo = LegalizeOp(Lo);
6651 // Don't legalize the high part if it is expanded to a single node.
6652 Hi = LegalizeOp(Hi);
6655 // Remember in a map if the values will be reused later.
6657 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
6658 assert(isNew && "Value already expanded?!?");
6661 /// SplitVectorOp - Given an operand of vector type, break it down into
6662 /// two smaller values, still of vector type.
6663 void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
6665 assert(Op.getValueType().isVector() && "Cannot split non-vector type!");
6666 SDNode *Node = Op.Val;
6667 unsigned NumElements = Op.getValueType().getVectorNumElements();
6668 assert(NumElements > 1 && "Cannot split a single element vector!");
6670 MVT NewEltVT = Op.getValueType().getVectorElementType();
6672 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
6673 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
6675 MVT NewVT_Lo = MVT::getVectorVT(NewEltVT, NewNumElts_Lo);
6676 MVT NewVT_Hi = MVT::getVectorVT(NewEltVT, NewNumElts_Hi);
6678 // See if we already split it.
6679 std::map<SDValue, std::pair<SDValue, SDValue> >::iterator I
6680 = SplitNodes.find(Op);
6681 if (I != SplitNodes.end()) {
6682 Lo = I->second.first;
6683 Hi = I->second.second;
6687 switch (Node->getOpcode()) {
6692 assert(0 && "Unhandled operation in SplitVectorOp!");
6694 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo);
6695 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi);
6697 case ISD::BUILD_PAIR:
6698 Lo = Node->getOperand(0);
6699 Hi = Node->getOperand(1);
6701 case ISD::INSERT_VECTOR_ELT: {
6702 if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) {
6703 SplitVectorOp(Node->getOperand(0), Lo, Hi);
6704 unsigned Index = Idx->getValue();
6705 SDValue ScalarOp = Node->getOperand(1);
6706 if (Index < NewNumElts_Lo)
6707 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp,
6708 DAG.getIntPtrConstant(Index));
6710 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp,
6711 DAG.getIntPtrConstant(Index - NewNumElts_Lo));
6714 SDValue Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0),
6715 Node->getOperand(1),
6716 Node->getOperand(2));
6717 SplitVectorOp(Tmp, Lo, Hi);
6720 case ISD::VECTOR_SHUFFLE: {
6721 // Build the low part.
6722 SDValue Mask = Node->getOperand(2);
6723 SmallVector<SDValue, 8> Ops;
6724 MVT PtrVT = TLI.getPointerTy();
6726 // Insert all of the elements from the input that are needed. We use
6727 // buildvector of extractelement here because the input vectors will have
6728 // to be legalized, so this makes the code simpler.
6729 for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
6730 SDValue IdxNode = Mask.getOperand(i);
6731 if (IdxNode.getOpcode() == ISD::UNDEF) {
6732 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
6735 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getValue();
6736 SDValue InVec = Node->getOperand(0);
6737 if (Idx >= NumElements) {
6738 InVec = Node->getOperand(1);
6741 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6742 DAG.getConstant(Idx, PtrVT)));
6744 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6747 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
6748 SDValue IdxNode = Mask.getOperand(i);
6749 if (IdxNode.getOpcode() == ISD::UNDEF) {
6750 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
6753 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getValue();
6754 SDValue InVec = Node->getOperand(0);
6755 if (Idx >= NumElements) {
6756 InVec = Node->getOperand(1);
6759 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6760 DAG.getConstant(Idx, PtrVT)));
6762 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &Ops[0], Ops.size());
6765 case ISD::BUILD_VECTOR: {
6766 SmallVector<SDValue, 8> LoOps(Node->op_begin(),
6767 Node->op_begin()+NewNumElts_Lo);
6768 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size());
6770 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
6772 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size());
6775 case ISD::CONCAT_VECTORS: {
6776 // FIXME: Handle non-power-of-two vectors?
6777 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
6778 if (NewNumSubvectors == 1) {
6779 Lo = Node->getOperand(0);
6780 Hi = Node->getOperand(1);
6782 SmallVector<SDValue, 8> LoOps(Node->op_begin(),
6783 Node->op_begin()+NewNumSubvectors);
6784 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size());
6786 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumSubvectors,
6788 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size());
6793 SDValue Cond = Node->getOperand(0);
6795 SDValue LL, LH, RL, RH;
6796 SplitVectorOp(Node->getOperand(1), LL, LH);
6797 SplitVectorOp(Node->getOperand(2), RL, RH);
6799 if (Cond.getValueType().isVector()) {
6800 // Handle a vector merge.
6802 SplitVectorOp(Cond, CL, CH);
6803 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL);
6804 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH);
6806 // Handle a simple select with vector operands.
6807 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL);
6808 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH);
6812 case ISD::SELECT_CC: {
6813 SDValue CondLHS = Node->getOperand(0);
6814 SDValue CondRHS = Node->getOperand(1);
6815 SDValue CondCode = Node->getOperand(4);
6817 SDValue LL, LH, RL, RH;
6818 SplitVectorOp(Node->getOperand(2), LL, LH);
6819 SplitVectorOp(Node->getOperand(3), RL, RH);
6821 // Handle a simple select with vector operands.
6822 Lo = DAG.getNode(ISD::SELECT_CC, NewVT_Lo, CondLHS, CondRHS,
6824 Hi = DAG.getNode(ISD::SELECT_CC, NewVT_Hi, CondLHS, CondRHS,
6829 SDValue LL, LH, RL, RH;
6830 SplitVectorOp(Node->getOperand(0), LL, LH);
6831 SplitVectorOp(Node->getOperand(1), RL, RH);
6832 Lo = DAG.getNode(ISD::VSETCC, NewVT_Lo, LL, RL, Node->getOperand(2));
6833 Hi = DAG.getNode(ISD::VSETCC, NewVT_Hi, LH, RH, Node->getOperand(2));
6852 SDValue LL, LH, RL, RH;
6853 SplitVectorOp(Node->getOperand(0), LL, LH);
6854 SplitVectorOp(Node->getOperand(1), RL, RH);
6856 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL);
6857 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH);
6863 SplitVectorOp(Node->getOperand(0), L, H);
6865 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1));
6866 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1));
6877 case ISD::FP_TO_SINT:
6878 case ISD::FP_TO_UINT:
6879 case ISD::SINT_TO_FP:
6880 case ISD::UINT_TO_FP:
6882 case ISD::ANY_EXTEND:
6883 case ISD::SIGN_EXTEND:
6884 case ISD::ZERO_EXTEND:
6885 case ISD::FP_EXTEND: {
6887 SplitVectorOp(Node->getOperand(0), L, H);
6889 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L);
6890 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H);
6894 LoadSDNode *LD = cast<LoadSDNode>(Node);
6895 SDValue Ch = LD->getChain();
6896 SDValue Ptr = LD->getBasePtr();
6897 ISD::LoadExtType ExtType = LD->getExtensionType();
6898 const Value *SV = LD->getSrcValue();
6899 int SVOffset = LD->getSrcValueOffset();
6900 MVT MemoryVT = LD->getMemoryVT();
6901 unsigned Alignment = LD->getAlignment();
6902 bool isVolatile = LD->isVolatile();
6904 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
6905 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType());
6907 MVT MemNewEltVT = MemoryVT.getVectorElementType();
6908 MVT MemNewVT_Lo = MVT::getVectorVT(MemNewEltVT, NewNumElts_Lo);
6909 MVT MemNewVT_Hi = MVT::getVectorVT(MemNewEltVT, NewNumElts_Hi);
6911 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType,
6912 NewVT_Lo, Ch, Ptr, Offset,
6913 SV, SVOffset, MemNewVT_Lo, isVolatile, Alignment);
6914 unsigned IncrementSize = NewNumElts_Lo * MemNewEltVT.getSizeInBits()/8;
6915 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
6916 DAG.getIntPtrConstant(IncrementSize));
6917 SVOffset += IncrementSize;
6918 Alignment = MinAlign(Alignment, IncrementSize);
6919 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType,
6920 NewVT_Hi, Ch, Ptr, Offset,
6921 SV, SVOffset, MemNewVT_Hi, isVolatile, Alignment);
6923 // Build a factor node to remember that this load is independent of the
6925 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
6928 // Remember that we legalized the chain.
6929 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
6932 case ISD::BIT_CONVERT: {
6933 // We know the result is a vector. The input may be either a vector or a
6935 SDValue InOp = Node->getOperand(0);
6936 if (!InOp.getValueType().isVector() ||
6937 InOp.getValueType().getVectorNumElements() == 1) {
6938 // The input is a scalar or single-element vector.
6939 // Lower to a store/load so that it can be split.
6940 // FIXME: this could be improved probably.
6941 unsigned LdAlign = TLI.getTargetData()->getPrefTypeAlignment(
6942 Op.getValueType().getTypeForMVT());
6943 SDValue Ptr = DAG.CreateStackTemporary(InOp.getValueType(), LdAlign);
6944 int FI = cast<FrameIndexSDNode>(Ptr.Val)->getIndex();
6946 SDValue St = DAG.getStore(DAG.getEntryNode(),
6948 PseudoSourceValue::getFixedStack(FI), 0);
6949 InOp = DAG.getLoad(Op.getValueType(), St, Ptr,
6950 PseudoSourceValue::getFixedStack(FI), 0);
6952 // Split the vector and convert each of the pieces now.
6953 SplitVectorOp(InOp, Lo, Hi);
6954 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo);
6955 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi);
6960 // Remember in a map if the values will be reused later.
6962 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
6963 assert(isNew && "Value already split?!?");
6967 /// ScalarizeVectorOp - Given an operand of single-element vector type
6968 /// (e.g. v1f32), convert it into the equivalent operation that returns a
6969 /// scalar (e.g. f32) value.
6970 SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) {
6971 assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!");
6972 SDNode *Node = Op.Val;
6973 MVT NewVT = Op.getValueType().getVectorElementType();
6974 assert(Op.getValueType().getVectorNumElements() == 1);
6976 // See if we already scalarized it.
6977 std::map<SDValue, SDValue>::iterator I = ScalarizedNodes.find(Op);
6978 if (I != ScalarizedNodes.end()) return I->second;
6981 switch (Node->getOpcode()) {
6984 Node->dump(&DAG); cerr << "\n";
6986 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
7003 Result = DAG.getNode(Node->getOpcode(),
7005 ScalarizeVectorOp(Node->getOperand(0)),
7006 ScalarizeVectorOp(Node->getOperand(1)));
7013 case ISD::FP_TO_SINT:
7014 case ISD::FP_TO_UINT:
7015 case ISD::SINT_TO_FP:
7016 case ISD::UINT_TO_FP:
7017 case ISD::SIGN_EXTEND:
7018 case ISD::ZERO_EXTEND:
7019 case ISD::ANY_EXTEND:
7021 case ISD::FP_EXTEND:
7022 Result = DAG.getNode(Node->getOpcode(),
7024 ScalarizeVectorOp(Node->getOperand(0)));
7028 Result = DAG.getNode(Node->getOpcode(),
7030 ScalarizeVectorOp(Node->getOperand(0)),
7031 Node->getOperand(1));
7034 LoadSDNode *LD = cast<LoadSDNode>(Node);
7035 SDValue Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
7036 SDValue Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
7037 ISD::LoadExtType ExtType = LD->getExtensionType();
7038 const Value *SV = LD->getSrcValue();
7039 int SVOffset = LD->getSrcValueOffset();
7040 MVT MemoryVT = LD->getMemoryVT();
7041 unsigned Alignment = LD->getAlignment();
7042 bool isVolatile = LD->isVolatile();
7044 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
7045 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType());
7047 Result = DAG.getLoad(ISD::UNINDEXED, ExtType,
7048 NewVT, Ch, Ptr, Offset, SV, SVOffset,
7049 MemoryVT.getVectorElementType(),
7050 isVolatile, Alignment);
7052 // Remember that we legalized the chain.
7053 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
7056 case ISD::BUILD_VECTOR:
7057 Result = Node->getOperand(0);
7059 case ISD::INSERT_VECTOR_ELT:
7060 // Returning the inserted scalar element.
7061 Result = Node->getOperand(1);
7063 case ISD::CONCAT_VECTORS:
7064 assert(Node->getOperand(0).getValueType() == NewVT &&
7065 "Concat of non-legal vectors not yet supported!");
7066 Result = Node->getOperand(0);
7068 case ISD::VECTOR_SHUFFLE: {
7069 // Figure out if the scalar is the LHS or RHS and return it.
7070 SDValue EltNum = Node->getOperand(2).getOperand(0);
7071 if (cast<ConstantSDNode>(EltNum)->getValue())
7072 Result = ScalarizeVectorOp(Node->getOperand(1));
7074 Result = ScalarizeVectorOp(Node->getOperand(0));
7077 case ISD::EXTRACT_SUBVECTOR:
7078 Result = Node->getOperand(0);
7079 assert(Result.getValueType() == NewVT);
7081 case ISD::BIT_CONVERT: {
7082 SDValue Op0 = Op.getOperand(0);
7083 if (Op0.getValueType().getVectorNumElements() == 1)
7084 Op0 = ScalarizeVectorOp(Op0);
7085 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op0);
7089 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
7090 ScalarizeVectorOp(Op.getOperand(1)),
7091 ScalarizeVectorOp(Op.getOperand(2)));
7093 case ISD::SELECT_CC:
7094 Result = DAG.getNode(ISD::SELECT_CC, NewVT, Node->getOperand(0),
7095 Node->getOperand(1),
7096 ScalarizeVectorOp(Op.getOperand(2)),
7097 ScalarizeVectorOp(Op.getOperand(3)),
7098 Node->getOperand(4));
7101 SDValue Op0 = ScalarizeVectorOp(Op.getOperand(0));
7102 SDValue Op1 = ScalarizeVectorOp(Op.getOperand(1));
7103 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Op0), Op0, Op1,
7105 Result = DAG.getNode(ISD::SELECT, NewVT, Result,
7106 DAG.getConstant(-1ULL, NewVT),
7107 DAG.getConstant(0ULL, NewVT));
7112 if (TLI.isTypeLegal(NewVT))
7113 Result = LegalizeOp(Result);
7114 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
7115 assert(isNew && "Value already scalarized?");
7120 // SelectionDAG::Legalize - This is the entry point for the file.
7122 void SelectionDAG::Legalize() {
7123 /// run - This is the main entry point to this class.
7125 SelectionDAGLegalize(*this).LegalizeDAG();