1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/Target/TargetLowering.h"
19 #include "llvm/Target/TargetData.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetOptions.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Support/MathExtras.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/Compiler.h"
28 #include "llvm/ADT/DenseMap.h"
29 #include "llvm/ADT/SmallVector.h"
30 #include "llvm/ADT/SmallPtrSet.h"
36 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
37 cl::desc("Pop up a window to show dags before legalize"));
39 static const bool ViewLegalizeDAGs = 0;
44 struct DenseMapKeyInfo<SDOperand> {
45 static inline SDOperand getEmptyKey() { return SDOperand((SDNode*)-1, -1U); }
46 static inline SDOperand getTombstoneKey() { return SDOperand((SDNode*)-1, 0);}
47 static unsigned getHashValue(const SDOperand &Val) {
48 return DenseMapKeyInfo<void*>::getHashValue(Val.Val) + Val.ResNo;
50 static bool isPod() { return true; }
54 //===----------------------------------------------------------------------===//
55 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
56 /// hacks on it until the target machine can handle it. This involves
57 /// eliminating value sizes the machine cannot handle (promoting small sizes to
58 /// large sizes or splitting up large values into small values) as well as
59 /// eliminating operations the machine cannot handle.
61 /// This code also does a small amount of optimization and recognition of idioms
62 /// as part of its processing. For example, if a target does not support a
63 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
64 /// will attempt merge setcc and brc instructions into brcc's.
67 class VISIBILITY_HIDDEN SelectionDAGLegalize {
71 // Libcall insertion helpers.
73 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
74 /// legalized. We use this to ensure that calls are properly serialized
75 /// against each other, including inserted libcalls.
76 SDOperand LastCALLSEQ_END;
78 /// IsLegalizingCall - This member is used *only* for purposes of providing
79 /// helpful assertions that a libcall isn't created while another call is
80 /// being legalized (which could lead to non-serialized call sequences).
81 bool IsLegalizingCall;
84 Legal, // The target natively supports this operation.
85 Promote, // This operation should be executed in a larger type.
86 Expand // Try to expand this to other ops, otherwise use a libcall.
89 /// ValueTypeActions - This is a bitvector that contains two bits for each
90 /// value type, where the two bits correspond to the LegalizeAction enum.
91 /// This can be queried with "getTypeAction(VT)".
92 TargetLowering::ValueTypeActionImpl ValueTypeActions;
94 /// LegalizedNodes - For nodes that are of legal width, and that have more
95 /// than one use, this map indicates what regularized operand to use. This
96 /// allows us to avoid legalizing the same thing more than once.
97 DenseMap<SDOperand, SDOperand> LegalizedNodes;
99 /// PromotedNodes - For nodes that are below legal width, and that have more
100 /// than one use, this map indicates what promoted value to use. This allows
101 /// us to avoid promoting the same thing more than once.
102 DenseMap<SDOperand, SDOperand> PromotedNodes;
104 /// ExpandedNodes - For nodes that need to be expanded this map indicates
105 /// which which operands are the expanded version of the input. This allows
106 /// us to avoid expanding the same node more than once.
107 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
109 /// SplitNodes - For vector nodes that need to be split, this map indicates
110 /// which which operands are the split version of the input. This allows us
111 /// to avoid splitting the same node more than once.
112 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
114 /// ScalarizedNodes - For nodes that need to be converted from vector types to
115 /// scalar types, this contains the mapping of ones we have already
116 /// processed to the result.
117 std::map<SDOperand, SDOperand> ScalarizedNodes;
119 void AddLegalizedOperand(SDOperand From, SDOperand To) {
120 LegalizedNodes.insert(std::make_pair(From, To));
121 // If someone requests legalization of the new node, return itself.
123 LegalizedNodes.insert(std::make_pair(To, To));
125 void AddPromotedOperand(SDOperand From, SDOperand To) {
126 bool isNew = PromotedNodes.insert(std::make_pair(From, To));
127 assert(isNew && "Got into the map somehow?");
128 // If someone requests legalization of the new node, return itself.
129 LegalizedNodes.insert(std::make_pair(To, To));
134 SelectionDAGLegalize(SelectionDAG &DAG);
136 /// getTypeAction - Return how we should legalize values of this type, either
137 /// it is already legal or we need to expand it into multiple registers of
138 /// smaller integer type, or we need to promote it to a larger type.
139 LegalizeAction getTypeAction(MVT::ValueType VT) const {
140 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
143 /// isTypeLegal - Return true if this type is legal on this target.
145 bool isTypeLegal(MVT::ValueType VT) const {
146 return getTypeAction(VT) == Legal;
152 /// HandleOp - Legalize, Promote, or Expand the specified operand as
153 /// appropriate for its type.
154 void HandleOp(SDOperand Op);
156 /// LegalizeOp - We know that the specified value has a legal type.
157 /// Recursively ensure that the operands have legal types, then return the
159 SDOperand LegalizeOp(SDOperand O);
161 /// PromoteOp - Given an operation that produces a value in an invalid type,
162 /// promote it to compute the value into a larger type. The produced value
163 /// will have the correct bits for the low portion of the register, but no
164 /// guarantee is made about the top bits: it may be zero, sign-extended, or
166 SDOperand PromoteOp(SDOperand O);
168 /// ExpandOp - Expand the specified SDOperand into its two component pieces
169 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
170 /// the LegalizeNodes map is filled in for any results that are not expanded,
171 /// the ExpandedNodes map is filled in for any results that are expanded, and
172 /// the Lo/Hi values are returned. This applies to integer types and Vector
174 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
176 /// SplitVectorOp - Given an operand of vector type, break it down into
177 /// two smaller values.
178 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
180 /// ScalarizeVectorOp - Given an operand of single-element vector type
181 /// (e.g. v1f32), convert it into the equivalent operation that returns a
182 /// scalar (e.g. f32) value.
183 SDOperand ScalarizeVectorOp(SDOperand O);
185 /// isShuffleLegal - Return true if a vector shuffle is legal with the
186 /// specified mask and type. Targets can specify exactly which masks they
187 /// support and the code generator is tasked with not creating illegal masks.
189 /// Note that this will also return true for shuffles that are promoted to a
192 /// If this is a legal shuffle, this method returns the (possibly promoted)
193 /// build_vector Mask. If it's not a legal shuffle, it returns null.
194 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
196 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
197 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
199 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
201 SDOperand CreateStackTemporary(MVT::ValueType VT);
203 SDOperand ExpandLibCall(const char *Name, SDNode *Node, bool isSigned,
205 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
208 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp);
209 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
210 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
211 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
213 MVT::ValueType DestVT);
214 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
216 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
219 SDOperand ExpandBSWAP(SDOperand Op);
220 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
221 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
222 SDOperand &Lo, SDOperand &Hi);
223 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
224 SDOperand &Lo, SDOperand &Hi);
226 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op);
227 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
229 SDOperand getIntPtrConstant(uint64_t Val) {
230 return DAG.getConstant(Val, TLI.getPointerTy());
235 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
236 /// specified mask and type. Targets can specify exactly which masks they
237 /// support and the code generator is tasked with not creating illegal masks.
239 /// Note that this will also return true for shuffles that are promoted to a
241 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
242 SDOperand Mask) const {
243 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
245 case TargetLowering::Legal:
246 case TargetLowering::Custom:
248 case TargetLowering::Promote: {
249 // If this is promoted to a different type, convert the shuffle mask and
250 // ask if it is legal in the promoted type!
251 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
253 // If we changed # elements, change the shuffle mask.
254 unsigned NumEltsGrowth =
255 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
256 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
257 if (NumEltsGrowth > 1) {
258 // Renumber the elements.
259 SmallVector<SDOperand, 8> Ops;
260 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
261 SDOperand InOp = Mask.getOperand(i);
262 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
263 if (InOp.getOpcode() == ISD::UNDEF)
264 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
266 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
267 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
271 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
277 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
280 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
281 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
282 ValueTypeActions(TLI.getValueTypeActions()) {
283 assert(MVT::LAST_VALUETYPE <= 32 &&
284 "Too many value types for ValueTypeActions to hold!");
287 /// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order
288 /// contains all of a nodes operands before it contains the node.
289 static void ComputeTopDownOrdering(SelectionDAG &DAG,
290 SmallVector<SDNode*, 64> &Order) {
292 DenseMap<SDNode*, unsigned> Visited;
293 std::vector<SDNode*> Worklist;
294 Worklist.reserve(128);
296 // Compute ordering from all of the leaves in the graphs, those (like the
297 // entry node) that have no operands.
298 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
299 E = DAG.allnodes_end(); I != E; ++I) {
300 if (I->getNumOperands() == 0) {
302 Worklist.push_back(I);
306 while (!Worklist.empty()) {
307 SDNode *N = Worklist.back();
310 if (++Visited[N] != N->getNumOperands())
311 continue; // Haven't visited all operands yet
315 // Now that we have N in, add anything that uses it if all of their operands
317 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
319 Worklist.push_back(*UI);
322 assert(Order.size() == Visited.size() &&
324 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
325 "Error: DAG is cyclic!");
329 void SelectionDAGLegalize::LegalizeDAG() {
330 LastCALLSEQ_END = DAG.getEntryNode();
331 IsLegalizingCall = false;
333 // The legalize process is inherently a bottom-up recursive process (users
334 // legalize their uses before themselves). Given infinite stack space, we
335 // could just start legalizing on the root and traverse the whole graph. In
336 // practice however, this causes us to run out of stack space on large basic
337 // blocks. To avoid this problem, compute an ordering of the nodes where each
338 // node is only legalized after all of its operands are legalized.
339 SmallVector<SDNode*, 64> Order;
340 ComputeTopDownOrdering(DAG, Order);
342 for (unsigned i = 0, e = Order.size(); i != e; ++i)
343 HandleOp(SDOperand(Order[i], 0));
345 // Finally, it's possible the root changed. Get the new root.
346 SDOperand OldRoot = DAG.getRoot();
347 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
348 DAG.setRoot(LegalizedNodes[OldRoot]);
350 ExpandedNodes.clear();
351 LegalizedNodes.clear();
352 PromotedNodes.clear();
354 ScalarizedNodes.clear();
356 // Remove dead nodes now.
357 DAG.RemoveDeadNodes();
361 /// FindCallEndFromCallStart - Given a chained node that is part of a call
362 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
363 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
364 if (Node->getOpcode() == ISD::CALLSEQ_END)
366 if (Node->use_empty())
367 return 0; // No CallSeqEnd
369 // The chain is usually at the end.
370 SDOperand TheChain(Node, Node->getNumValues()-1);
371 if (TheChain.getValueType() != MVT::Other) {
372 // Sometimes it's at the beginning.
373 TheChain = SDOperand(Node, 0);
374 if (TheChain.getValueType() != MVT::Other) {
375 // Otherwise, hunt for it.
376 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
377 if (Node->getValueType(i) == MVT::Other) {
378 TheChain = SDOperand(Node, i);
382 // Otherwise, we walked into a node without a chain.
383 if (TheChain.getValueType() != MVT::Other)
388 for (SDNode::use_iterator UI = Node->use_begin(),
389 E = Node->use_end(); UI != E; ++UI) {
391 // Make sure to only follow users of our token chain.
393 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
394 if (User->getOperand(i) == TheChain)
395 if (SDNode *Result = FindCallEndFromCallStart(User))
401 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
402 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
403 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
404 assert(Node && "Didn't find callseq_start for a call??");
405 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
407 assert(Node->getOperand(0).getValueType() == MVT::Other &&
408 "Node doesn't have a token chain argument!");
409 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
412 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
413 /// see if any uses can reach Dest. If no dest operands can get to dest,
414 /// legalize them, legalize ourself, and return false, otherwise, return true.
416 /// Keep track of the nodes we fine that actually do lead to Dest in
417 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
419 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
420 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
421 if (N == Dest) return true; // N certainly leads to Dest :)
423 // If we've already processed this node and it does lead to Dest, there is no
424 // need to reprocess it.
425 if (NodesLeadingTo.count(N)) return true;
427 // If the first result of this node has been already legalized, then it cannot
429 switch (getTypeAction(N->getValueType(0))) {
431 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
434 if (PromotedNodes.count(SDOperand(N, 0))) return false;
437 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
441 // Okay, this node has not already been legalized. Check and legalize all
442 // operands. If none lead to Dest, then we can legalize this node.
443 bool OperandsLeadToDest = false;
444 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
445 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
446 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
448 if (OperandsLeadToDest) {
449 NodesLeadingTo.insert(N);
453 // Okay, this node looks safe, legalize it and return false.
454 HandleOp(SDOperand(N, 0));
458 /// HandleOp - Legalize, Promote, or Expand the specified operand as
459 /// appropriate for its type.
460 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
461 MVT::ValueType VT = Op.getValueType();
462 switch (getTypeAction(VT)) {
463 default: assert(0 && "Bad type action!");
464 case Legal: (void)LegalizeOp(Op); break;
465 case Promote: (void)PromoteOp(Op); break;
467 if (!MVT::isVector(VT)) {
468 // If this is an illegal scalar, expand it into its two component
472 } else if (MVT::getVectorNumElements(VT) == 1) {
473 // If this is an illegal single element vector, convert it to a
475 (void)ScalarizeVectorOp(Op);
477 // Otherwise, this is an illegal multiple element vector.
478 // Split it in half and legalize both parts.
480 SplitVectorOp(Op, X, Y);
486 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
487 /// a load from the constant pool.
488 static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
489 SelectionDAG &DAG, TargetLowering &TLI) {
492 // If a FP immediate is precise when represented as a float and if the
493 // target can do an extending load from float to double, we put it into
494 // the constant pool as a float, even if it's is statically typed as a
496 MVT::ValueType VT = CFP->getValueType(0);
497 bool isDouble = VT == MVT::f64;
498 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy :
499 Type::FloatTy, CFP->getValue());
501 double Val = LLVMC->getValue();
503 ? DAG.getConstant(DoubleToBits(Val), MVT::i64)
504 : DAG.getConstant(FloatToBits(Val), MVT::i32);
507 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) &&
508 // Only do this if the target has a native EXTLOAD instruction from f32.
509 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) {
510 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC,Type::FloatTy));
515 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
517 return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
518 CPIdx, NULL, 0, MVT::f32);
520 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
525 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
528 SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT,
529 SelectionDAG &DAG, TargetLowering &TLI) {
530 MVT::ValueType VT = Node->getValueType(0);
531 MVT::ValueType SrcVT = Node->getOperand(1).getValueType();
532 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
533 "fcopysign expansion only supported for f32 and f64");
534 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
536 // First get the sign bit of second operand.
537 SDOperand Mask1 = (SrcVT == MVT::f64)
538 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
539 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
540 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
541 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
542 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
543 // Shift right or sign-extend it if the two operands have different types.
544 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT);
546 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
547 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
548 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
549 } else if (SizeDiff < 0)
550 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit);
552 // Clear the sign bit of first operand.
553 SDOperand Mask2 = (VT == MVT::f64)
554 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
555 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
556 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
557 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
558 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
560 // Or the value with the sign bit.
561 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
566 /// LegalizeOp - We know that the specified value has a legal type.
567 /// Recursively ensure that the operands have legal types, then return the
569 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
570 assert(isTypeLegal(Op.getValueType()) &&
571 "Caller should expand or promote operands that are not legal!");
572 SDNode *Node = Op.Val;
574 // If this operation defines any values that cannot be represented in a
575 // register on this target, make sure to expand or promote them.
576 if (Node->getNumValues() > 1) {
577 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
578 if (getTypeAction(Node->getValueType(i)) != Legal) {
579 HandleOp(Op.getValue(i));
580 assert(LegalizedNodes.count(Op) &&
581 "Handling didn't add legal operands!");
582 return LegalizedNodes[Op];
586 // Note that LegalizeOp may be reentered even from single-use nodes, which
587 // means that we always must cache transformed nodes.
588 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
589 if (I != LegalizedNodes.end()) return I->second;
591 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
592 SDOperand Result = Op;
593 bool isCustom = false;
595 switch (Node->getOpcode()) {
596 case ISD::FrameIndex:
597 case ISD::EntryToken:
599 case ISD::BasicBlock:
600 case ISD::TargetFrameIndex:
601 case ISD::TargetJumpTable:
602 case ISD::TargetConstant:
603 case ISD::TargetConstantFP:
604 case ISD::TargetConstantPool:
605 case ISD::TargetGlobalAddress:
606 case ISD::TargetGlobalTLSAddress:
607 case ISD::TargetExternalSymbol:
612 // Primitives must all be legal.
613 assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) &&
614 "This must be legal!");
617 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
618 // If this is a target node, legalize it by legalizing the operands then
619 // passing it through.
620 SmallVector<SDOperand, 8> Ops;
621 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
622 Ops.push_back(LegalizeOp(Node->getOperand(i)));
624 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
626 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
627 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
628 return Result.getValue(Op.ResNo);
630 // Otherwise this is an unhandled builtin node. splat.
632 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
634 assert(0 && "Do not know how to legalize this operator!");
636 case ISD::GLOBAL_OFFSET_TABLE:
637 case ISD::GlobalAddress:
638 case ISD::GlobalTLSAddress:
639 case ISD::ExternalSymbol:
640 case ISD::ConstantPool:
641 case ISD::JumpTable: // Nothing to do.
642 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
643 default: assert(0 && "This action is not supported yet!");
644 case TargetLowering::Custom:
645 Tmp1 = TLI.LowerOperation(Op, DAG);
646 if (Tmp1.Val) Result = Tmp1;
647 // FALLTHROUGH if the target doesn't want to lower this op after all.
648 case TargetLowering::Legal:
653 case ISD::RETURNADDR:
654 // The only option for these nodes is to custom lower them. If the target
655 // does not custom lower them, then return zero.
656 Tmp1 = TLI.LowerOperation(Op, DAG);
660 Result = DAG.getConstant(0, TLI.getPointerTy());
662 case ISD::EXCEPTIONADDR: {
663 Tmp1 = LegalizeOp(Node->getOperand(0));
664 MVT::ValueType VT = Node->getValueType(0);
665 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
666 default: assert(0 && "This action is not supported yet!");
667 case TargetLowering::Expand: {
668 unsigned Reg = TLI.getExceptionAddressRegister();
669 Result = DAG.getCopyFromReg(Tmp1, Reg, VT).getValue(Op.ResNo);
672 case TargetLowering::Custom:
673 Result = TLI.LowerOperation(Op, DAG);
674 if (Result.Val) break;
676 case TargetLowering::Legal: {
677 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 };
678 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
679 Ops, 2).getValue(Op.ResNo);
685 case ISD::EHSELECTION: {
686 Tmp1 = LegalizeOp(Node->getOperand(0));
687 Tmp2 = LegalizeOp(Node->getOperand(1));
688 MVT::ValueType VT = Node->getValueType(0);
689 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
690 default: assert(0 && "This action is not supported yet!");
691 case TargetLowering::Expand: {
692 unsigned Reg = TLI.getExceptionSelectorRegister();
693 Result = DAG.getCopyFromReg(Tmp2, Reg, VT).getValue(Op.ResNo);
696 case TargetLowering::Custom:
697 Result = TLI.LowerOperation(Op, DAG);
698 if (Result.Val) break;
700 case TargetLowering::Legal: {
701 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 };
702 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
703 Ops, 2).getValue(Op.ResNo);
709 case ISD::AssertSext:
710 case ISD::AssertZext:
711 Tmp1 = LegalizeOp(Node->getOperand(0));
712 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
714 case ISD::MERGE_VALUES:
715 // Legalize eliminates MERGE_VALUES nodes.
716 Result = Node->getOperand(Op.ResNo);
718 case ISD::CopyFromReg:
719 Tmp1 = LegalizeOp(Node->getOperand(0));
720 Result = Op.getValue(0);
721 if (Node->getNumValues() == 2) {
722 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
724 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
725 if (Node->getNumOperands() == 3) {
726 Tmp2 = LegalizeOp(Node->getOperand(2));
727 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
729 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
731 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
733 // Since CopyFromReg produces two values, make sure to remember that we
734 // legalized both of them.
735 AddLegalizedOperand(Op.getValue(0), Result);
736 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
737 return Result.getValue(Op.ResNo);
739 MVT::ValueType VT = Op.getValueType();
740 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
741 default: assert(0 && "This action is not supported yet!");
742 case TargetLowering::Expand:
743 if (MVT::isInteger(VT))
744 Result = DAG.getConstant(0, VT);
745 else if (MVT::isFloatingPoint(VT))
746 Result = DAG.getConstantFP(0, VT);
748 assert(0 && "Unknown value type!");
750 case TargetLowering::Legal:
756 case ISD::INTRINSIC_W_CHAIN:
757 case ISD::INTRINSIC_WO_CHAIN:
758 case ISD::INTRINSIC_VOID: {
759 SmallVector<SDOperand, 8> Ops;
760 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
761 Ops.push_back(LegalizeOp(Node->getOperand(i)));
762 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
764 // Allow the target to custom lower its intrinsics if it wants to.
765 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
766 TargetLowering::Custom) {
767 Tmp3 = TLI.LowerOperation(Result, DAG);
768 if (Tmp3.Val) Result = Tmp3;
771 if (Result.Val->getNumValues() == 1) break;
773 // Must have return value and chain result.
774 assert(Result.Val->getNumValues() == 2 &&
775 "Cannot return more than two values!");
777 // Since loads produce two values, make sure to remember that we
778 // legalized both of them.
779 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
780 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
781 return Result.getValue(Op.ResNo);
785 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
786 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
788 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
789 case TargetLowering::Promote:
790 default: assert(0 && "This action is not supported yet!");
791 case TargetLowering::Expand: {
792 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
793 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
794 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other);
796 if (MMI && (useDEBUG_LOC || useLABEL)) {
797 const std::string &FName =
798 cast<StringSDNode>(Node->getOperand(3))->getValue();
799 const std::string &DirName =
800 cast<StringSDNode>(Node->getOperand(4))->getValue();
801 unsigned SrcFile = MMI->RecordSource(DirName, FName);
803 SmallVector<SDOperand, 8> Ops;
804 Ops.push_back(Tmp1); // chain
805 SDOperand LineOp = Node->getOperand(1);
806 SDOperand ColOp = Node->getOperand(2);
809 Ops.push_back(LineOp); // line #
810 Ops.push_back(ColOp); // col #
811 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
812 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
814 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
815 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
816 unsigned ID = MMI->RecordLabel(Line, Col, SrcFile);
817 Ops.push_back(DAG.getConstant(ID, MVT::i32));
818 Result = DAG.getNode(ISD::LABEL, MVT::Other,&Ops[0],Ops.size());
821 Result = Tmp1; // chain
825 case TargetLowering::Legal:
826 if (Tmp1 != Node->getOperand(0) ||
827 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
828 SmallVector<SDOperand, 8> Ops;
830 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
831 Ops.push_back(Node->getOperand(1)); // line # must be legal.
832 Ops.push_back(Node->getOperand(2)); // col # must be legal.
834 // Otherwise promote them.
835 Ops.push_back(PromoteOp(Node->getOperand(1)));
836 Ops.push_back(PromoteOp(Node->getOperand(2)));
838 Ops.push_back(Node->getOperand(3)); // filename must be legal.
839 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
840 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
847 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
848 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
849 default: assert(0 && "This action is not supported yet!");
850 case TargetLowering::Legal:
851 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
852 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
853 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
854 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
855 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
861 assert(Node->getNumOperands() == 2 && "Invalid LABEL node!");
862 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) {
863 default: assert(0 && "This action is not supported yet!");
864 case TargetLowering::Legal:
865 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
866 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
867 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
869 case TargetLowering::Expand:
870 Result = LegalizeOp(Node->getOperand(0));
876 // We know we don't need to expand constants here, constants only have one
877 // value and we check that it is fine above.
879 // FIXME: Maybe we should handle things like targets that don't support full
880 // 32-bit immediates?
882 case ISD::ConstantFP: {
883 // Spill FP immediates to the constant pool if the target cannot directly
884 // codegen them. Targets often have some immediate values that can be
885 // efficiently generated into an FP register without a load. We explicitly
886 // leave these constants as ConstantFP nodes for the target to deal with.
887 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
889 // Check to see if this FP immediate is already legal.
890 bool isLegal = false;
891 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
892 E = TLI.legal_fpimm_end(); I != E; ++I)
893 if (CFP->isExactlyValue(*I)) {
898 // If this is a legal constant, turn it into a TargetConstantFP node.
900 Result = DAG.getTargetConstantFP(CFP->getValue(), CFP->getValueType(0));
904 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
905 default: assert(0 && "This action is not supported yet!");
906 case TargetLowering::Custom:
907 Tmp3 = TLI.LowerOperation(Result, DAG);
913 case TargetLowering::Expand:
914 Result = ExpandConstantFP(CFP, true, DAG, TLI);
918 case ISD::TokenFactor:
919 if (Node->getNumOperands() == 2) {
920 Tmp1 = LegalizeOp(Node->getOperand(0));
921 Tmp2 = LegalizeOp(Node->getOperand(1));
922 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
923 } else if (Node->getNumOperands() == 3) {
924 Tmp1 = LegalizeOp(Node->getOperand(0));
925 Tmp2 = LegalizeOp(Node->getOperand(1));
926 Tmp3 = LegalizeOp(Node->getOperand(2));
927 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
929 SmallVector<SDOperand, 8> Ops;
930 // Legalize the operands.
931 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
932 Ops.push_back(LegalizeOp(Node->getOperand(i)));
933 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
937 case ISD::FORMAL_ARGUMENTS:
939 // The only option for this is to custom lower it.
940 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
941 assert(Tmp3.Val && "Target didn't custom lower this node!");
942 assert(Tmp3.Val->getNumValues() == Result.Val->getNumValues() &&
943 "Lowering call/formal_arguments produced unexpected # results!");
945 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
946 // remember that we legalized all of them, so it doesn't get relegalized.
947 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
948 Tmp1 = LegalizeOp(Tmp3.getValue(i));
951 AddLegalizedOperand(SDOperand(Node, i), Tmp1);
955 case ISD::BUILD_VECTOR:
956 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
957 default: assert(0 && "This action is not supported yet!");
958 case TargetLowering::Custom:
959 Tmp3 = TLI.LowerOperation(Result, DAG);
965 case TargetLowering::Expand:
966 Result = ExpandBUILD_VECTOR(Result.Val);
970 case ISD::INSERT_VECTOR_ELT:
971 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
972 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal
973 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
974 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
976 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
977 Node->getValueType(0))) {
978 default: assert(0 && "This action is not supported yet!");
979 case TargetLowering::Legal:
981 case TargetLowering::Custom:
982 Tmp3 = TLI.LowerOperation(Result, DAG);
988 case TargetLowering::Expand: {
989 // If the insert index is a constant, codegen this as a scalar_to_vector,
990 // then a shuffle that inserts it into the right position in the vector.
991 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
992 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
993 Tmp1.getValueType(), Tmp2);
995 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
996 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
997 MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT);
999 // We generate a shuffle of InVec and ScVec, so the shuffle mask should
1000 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of
1002 SmallVector<SDOperand, 8> ShufOps;
1003 for (unsigned i = 0; i != NumElts; ++i) {
1004 if (i != InsertPos->getValue())
1005 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1007 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1009 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1010 &ShufOps[0], ShufOps.size());
1012 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1013 Tmp1, ScVec, ShufMask);
1014 Result = LegalizeOp(Result);
1018 // If the target doesn't support this, we have to spill the input vector
1019 // to a temporary stack slot, update the element, then reload it. This is
1020 // badness. We could also load the value into a vector register (either
1021 // with a "move to register" or "extload into register" instruction, then
1022 // permute it into place, if the idx is a constant and if the idx is
1023 // supported by the target.
1024 MVT::ValueType VT = Tmp1.getValueType();
1025 MVT::ValueType EltVT = Tmp2.getValueType();
1026 MVT::ValueType IdxVT = Tmp3.getValueType();
1027 MVT::ValueType PtrVT = TLI.getPointerTy();
1028 SDOperand StackPtr = CreateStackTemporary(VT);
1029 // Store the vector.
1030 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, NULL, 0);
1032 // Truncate or zero extend offset to target pointer type.
1033 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
1034 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
1035 // Add the offset to the index.
1036 unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
1037 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
1038 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
1039 // Store the scalar value.
1040 Ch = DAG.getStore(Ch, Tmp2, StackPtr2, NULL, 0);
1041 // Load the updated vector.
1042 Result = DAG.getLoad(VT, Ch, StackPtr, NULL, 0);
1047 case ISD::SCALAR_TO_VECTOR:
1048 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1049 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1053 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1054 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1055 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1056 Node->getValueType(0))) {
1057 default: assert(0 && "This action is not supported yet!");
1058 case TargetLowering::Legal:
1060 case TargetLowering::Custom:
1061 Tmp3 = TLI.LowerOperation(Result, DAG);
1067 case TargetLowering::Expand:
1068 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1072 case ISD::VECTOR_SHUFFLE:
1073 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1074 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1075 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1077 // Allow targets to custom lower the SHUFFLEs they support.
1078 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1079 default: assert(0 && "Unknown operation action!");
1080 case TargetLowering::Legal:
1081 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1082 "vector shuffle should not be created if not legal!");
1084 case TargetLowering::Custom:
1085 Tmp3 = TLI.LowerOperation(Result, DAG);
1091 case TargetLowering::Expand: {
1092 MVT::ValueType VT = Node->getValueType(0);
1093 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
1094 MVT::ValueType PtrVT = TLI.getPointerTy();
1095 SDOperand Mask = Node->getOperand(2);
1096 unsigned NumElems = Mask.getNumOperands();
1097 SmallVector<SDOperand,8> Ops;
1098 for (unsigned i = 0; i != NumElems; ++i) {
1099 SDOperand Arg = Mask.getOperand(i);
1100 if (Arg.getOpcode() == ISD::UNDEF) {
1101 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1103 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1104 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
1106 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1107 DAG.getConstant(Idx, PtrVT)));
1109 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1110 DAG.getConstant(Idx - NumElems, PtrVT)));
1113 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1116 case TargetLowering::Promote: {
1117 // Change base type to a different vector type.
1118 MVT::ValueType OVT = Node->getValueType(0);
1119 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1121 // Cast the two input vectors.
1122 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1123 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1125 // Convert the shuffle mask to the right # elements.
1126 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1127 assert(Tmp3.Val && "Shuffle not legal?");
1128 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1129 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1135 case ISD::EXTRACT_VECTOR_ELT:
1136 Tmp1 = Node->getOperand(0);
1137 Tmp2 = LegalizeOp(Node->getOperand(1));
1138 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1139 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1142 case ISD::EXTRACT_SUBVECTOR:
1143 Tmp1 = Node->getOperand(0);
1144 Tmp2 = LegalizeOp(Node->getOperand(1));
1145 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1146 Result = ExpandEXTRACT_SUBVECTOR(Result);
1149 case ISD::CALLSEQ_START: {
1150 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1152 // Recursively Legalize all of the inputs of the call end that do not lead
1153 // to this call start. This ensures that any libcalls that need be inserted
1154 // are inserted *before* the CALLSEQ_START.
1155 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1156 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1157 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
1161 // Now that we legalized all of the inputs (which may have inserted
1162 // libcalls) create the new CALLSEQ_START node.
1163 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1165 // Merge in the last call, to ensure that this call start after the last
1167 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1168 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1169 Tmp1 = LegalizeOp(Tmp1);
1172 // Do not try to legalize the target-specific arguments (#1+).
1173 if (Tmp1 != Node->getOperand(0)) {
1174 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1176 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1179 // Remember that the CALLSEQ_START is legalized.
1180 AddLegalizedOperand(Op.getValue(0), Result);
1181 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1182 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1184 // Now that the callseq_start and all of the non-call nodes above this call
1185 // sequence have been legalized, legalize the call itself. During this
1186 // process, no libcalls can/will be inserted, guaranteeing that no calls
1188 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1189 SDOperand InCallSEQ = LastCALLSEQ_END;
1190 // Note that we are selecting this call!
1191 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1192 IsLegalizingCall = true;
1194 // Legalize the call, starting from the CALLSEQ_END.
1195 LegalizeOp(LastCALLSEQ_END);
1196 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1199 case ISD::CALLSEQ_END:
1200 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1201 // will cause this node to be legalized as well as handling libcalls right.
1202 if (LastCALLSEQ_END.Val != Node) {
1203 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1204 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1205 assert(I != LegalizedNodes.end() &&
1206 "Legalizing the call start should have legalized this node!");
1210 // Otherwise, the call start has been legalized and everything is going
1211 // according to plan. Just legalize ourselves normally here.
1212 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1213 // Do not try to legalize the target-specific arguments (#1+), except for
1214 // an optional flag input.
1215 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1216 if (Tmp1 != Node->getOperand(0)) {
1217 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1219 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1222 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1223 if (Tmp1 != Node->getOperand(0) ||
1224 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1225 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1228 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1231 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1232 // This finishes up call legalization.
1233 IsLegalizingCall = false;
1235 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1236 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1237 if (Node->getNumValues() == 2)
1238 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1239 return Result.getValue(Op.ResNo);
1240 case ISD::DYNAMIC_STACKALLOC: {
1241 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1242 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1243 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1244 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1246 Tmp1 = Result.getValue(0);
1247 Tmp2 = Result.getValue(1);
1248 switch (TLI.getOperationAction(Node->getOpcode(),
1249 Node->getValueType(0))) {
1250 default: assert(0 && "This action is not supported yet!");
1251 case TargetLowering::Expand: {
1252 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1253 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1254 " not tell us which reg is the stack pointer!");
1255 SDOperand Chain = Tmp1.getOperand(0);
1256 SDOperand Size = Tmp2.getOperand(1);
1257 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, Node->getValueType(0));
1258 Tmp1 = DAG.getNode(ISD::SUB, Node->getValueType(0), SP, Size); // Value
1259 Tmp2 = DAG.getCopyToReg(SP.getValue(1), SPReg, Tmp1); // Output chain
1260 Tmp1 = LegalizeOp(Tmp1);
1261 Tmp2 = LegalizeOp(Tmp2);
1264 case TargetLowering::Custom:
1265 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1267 Tmp1 = LegalizeOp(Tmp3);
1268 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1271 case TargetLowering::Legal:
1274 // Since this op produce two values, make sure to remember that we
1275 // legalized both of them.
1276 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1277 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1278 return Op.ResNo ? Tmp2 : Tmp1;
1280 case ISD::INLINEASM: {
1281 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1282 bool Changed = false;
1283 // Legalize all of the operands of the inline asm, in case they are nodes
1284 // that need to be expanded or something. Note we skip the asm string and
1285 // all of the TargetConstant flags.
1286 SDOperand Op = LegalizeOp(Ops[0]);
1287 Changed = Op != Ops[0];
1290 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1291 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1292 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1293 for (++i; NumVals; ++i, --NumVals) {
1294 SDOperand Op = LegalizeOp(Ops[i]);
1303 Op = LegalizeOp(Ops.back());
1304 Changed |= Op != Ops.back();
1309 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1311 // INLINE asm returns a chain and flag, make sure to add both to the map.
1312 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1313 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1314 return Result.getValue(Op.ResNo);
1317 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1318 // Ensure that libcalls are emitted before a branch.
1319 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1320 Tmp1 = LegalizeOp(Tmp1);
1321 LastCALLSEQ_END = DAG.getEntryNode();
1323 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1326 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1327 // Ensure that libcalls are emitted before a branch.
1328 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1329 Tmp1 = LegalizeOp(Tmp1);
1330 LastCALLSEQ_END = DAG.getEntryNode();
1332 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1333 default: assert(0 && "Indirect target must be legal type (pointer)!");
1335 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1338 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1341 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1342 // Ensure that libcalls are emitted before a branch.
1343 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1344 Tmp1 = LegalizeOp(Tmp1);
1345 LastCALLSEQ_END = DAG.getEntryNode();
1347 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1348 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1350 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1351 default: assert(0 && "This action is not supported yet!");
1352 case TargetLowering::Legal: break;
1353 case TargetLowering::Custom:
1354 Tmp1 = TLI.LowerOperation(Result, DAG);
1355 if (Tmp1.Val) Result = Tmp1;
1357 case TargetLowering::Expand: {
1358 SDOperand Chain = Result.getOperand(0);
1359 SDOperand Table = Result.getOperand(1);
1360 SDOperand Index = Result.getOperand(2);
1362 MVT::ValueType PTy = TLI.getPointerTy();
1363 MachineFunction &MF = DAG.getMachineFunction();
1364 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
1365 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1366 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1369 switch (EntrySize) {
1370 default: assert(0 && "Size of jump table not supported yet."); break;
1371 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, NULL, 0); break;
1372 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, NULL, 0); break;
1375 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1376 // For PIC, the sequence is:
1377 // BRIND(load(Jumptable + index) + RelocBase)
1378 // RelocBase is the JumpTable on PPC and X86, GOT on Alpha
1380 if (TLI.usesGlobalOffsetTable())
1381 Reloc = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PTy);
1384 Addr = (PTy != MVT::i32) ? DAG.getNode(ISD::SIGN_EXTEND, PTy, LD) : LD;
1385 Addr = DAG.getNode(ISD::ADD, PTy, Addr, Reloc);
1386 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1388 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), LD);
1394 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1395 // Ensure that libcalls are emitted before a return.
1396 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1397 Tmp1 = LegalizeOp(Tmp1);
1398 LastCALLSEQ_END = DAG.getEntryNode();
1400 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1401 case Expand: assert(0 && "It's impossible to expand bools");
1403 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1406 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1408 // The top bits of the promoted condition are not necessarily zero, ensure
1409 // that the value is properly zero extended.
1410 if (!DAG.MaskedValueIsZero(Tmp2,
1411 MVT::getIntVTBitMask(Tmp2.getValueType())^1))
1412 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1416 // Basic block destination (Op#2) is always legal.
1417 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1419 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1420 default: assert(0 && "This action is not supported yet!");
1421 case TargetLowering::Legal: break;
1422 case TargetLowering::Custom:
1423 Tmp1 = TLI.LowerOperation(Result, DAG);
1424 if (Tmp1.Val) Result = Tmp1;
1426 case TargetLowering::Expand:
1427 // Expand brcond's setcc into its constituent parts and create a BR_CC
1429 if (Tmp2.getOpcode() == ISD::SETCC) {
1430 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1431 Tmp2.getOperand(0), Tmp2.getOperand(1),
1432 Node->getOperand(2));
1434 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1435 DAG.getCondCode(ISD::SETNE), Tmp2,
1436 DAG.getConstant(0, Tmp2.getValueType()),
1437 Node->getOperand(2));
1443 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1444 // Ensure that libcalls are emitted before a branch.
1445 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1446 Tmp1 = LegalizeOp(Tmp1);
1447 Tmp2 = Node->getOperand(2); // LHS
1448 Tmp3 = Node->getOperand(3); // RHS
1449 Tmp4 = Node->getOperand(1); // CC
1451 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1452 LastCALLSEQ_END = DAG.getEntryNode();
1454 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1455 // the LHS is a legal SETCC itself. In this case, we need to compare
1456 // the result against zero to select between true and false values.
1457 if (Tmp3.Val == 0) {
1458 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1459 Tmp4 = DAG.getCondCode(ISD::SETNE);
1462 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1463 Node->getOperand(4));
1465 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1466 default: assert(0 && "Unexpected action for BR_CC!");
1467 case TargetLowering::Legal: break;
1468 case TargetLowering::Custom:
1469 Tmp4 = TLI.LowerOperation(Result, DAG);
1470 if (Tmp4.Val) Result = Tmp4;
1475 LoadSDNode *LD = cast<LoadSDNode>(Node);
1476 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1477 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1479 ISD::LoadExtType ExtType = LD->getExtensionType();
1480 if (ExtType == ISD::NON_EXTLOAD) {
1481 MVT::ValueType VT = Node->getValueType(0);
1482 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1483 Tmp3 = Result.getValue(0);
1484 Tmp4 = Result.getValue(1);
1486 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1487 default: assert(0 && "This action is not supported yet!");
1488 case TargetLowering::Legal: break;
1489 case TargetLowering::Custom:
1490 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1492 Tmp3 = LegalizeOp(Tmp1);
1493 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1496 case TargetLowering::Promote: {
1497 // Only promote a load of vector type to another.
1498 assert(MVT::isVector(VT) && "Cannot promote this load!");
1499 // Change base type to a different vector type.
1500 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1502 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1503 LD->getSrcValueOffset());
1504 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1505 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1509 // Since loads produce two values, make sure to remember that we
1510 // legalized both of them.
1511 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1512 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1513 return Op.ResNo ? Tmp4 : Tmp3;
1515 MVT::ValueType SrcVT = LD->getLoadedVT();
1516 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
1517 default: assert(0 && "This action is not supported yet!");
1518 case TargetLowering::Promote:
1519 assert(SrcVT == MVT::i1 &&
1520 "Can only promote extending LOAD from i1 -> i8!");
1521 Result = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
1522 LD->getSrcValue(), LD->getSrcValueOffset(),
1524 Tmp1 = Result.getValue(0);
1525 Tmp2 = Result.getValue(1);
1527 case TargetLowering::Custom:
1530 case TargetLowering::Legal:
1531 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1532 Tmp1 = Result.getValue(0);
1533 Tmp2 = Result.getValue(1);
1536 Tmp3 = TLI.LowerOperation(Result, DAG);
1538 Tmp1 = LegalizeOp(Tmp3);
1539 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1543 case TargetLowering::Expand:
1544 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1545 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1546 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
1547 LD->getSrcValueOffset());
1548 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
1549 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1550 Tmp2 = LegalizeOp(Load.getValue(1));
1553 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
1554 // Turn the unsupported load into an EXTLOAD followed by an explicit
1555 // zero/sign extend inreg.
1556 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
1557 Tmp1, Tmp2, LD->getSrcValue(),
1558 LD->getSrcValueOffset(), SrcVT);
1560 if (ExtType == ISD::SEXTLOAD)
1561 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1562 Result, DAG.getValueType(SrcVT));
1564 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
1565 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1566 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1569 // Since loads produce two values, make sure to remember that we legalized
1571 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1572 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1573 return Op.ResNo ? Tmp2 : Tmp1;
1576 case ISD::EXTRACT_ELEMENT: {
1577 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
1578 switch (getTypeAction(OpTy)) {
1579 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
1581 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
1583 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
1584 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
1585 TLI.getShiftAmountTy()));
1586 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
1589 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
1590 Node->getOperand(0));
1594 // Get both the low and high parts.
1595 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1596 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
1597 Result = Tmp2; // 1 -> Hi
1599 Result = Tmp1; // 0 -> Lo
1605 case ISD::CopyToReg:
1606 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1608 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
1609 "Register type must be legal!");
1610 // Legalize the incoming value (must be a legal type).
1611 Tmp2 = LegalizeOp(Node->getOperand(2));
1612 if (Node->getNumValues() == 1) {
1613 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
1615 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
1616 if (Node->getNumOperands() == 4) {
1617 Tmp3 = LegalizeOp(Node->getOperand(3));
1618 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
1621 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1624 // Since this produces two values, make sure to remember that we legalized
1626 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1627 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1633 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1635 // Ensure that libcalls are emitted before a return.
1636 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1637 Tmp1 = LegalizeOp(Tmp1);
1638 LastCALLSEQ_END = DAG.getEntryNode();
1640 switch (Node->getNumOperands()) {
1642 Tmp2 = Node->getOperand(1);
1643 Tmp3 = Node->getOperand(2); // Signness
1644 switch (getTypeAction(Tmp2.getValueType())) {
1646 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
1649 if (!MVT::isVector(Tmp2.getValueType())) {
1651 ExpandOp(Tmp2, Lo, Hi);
1653 // Big endian systems want the hi reg first.
1654 if (!TLI.isLittleEndian())
1658 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
1660 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
1661 Result = LegalizeOp(Result);
1663 SDNode *InVal = Tmp2.Val;
1664 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(0));
1665 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(0));
1667 // Figure out if there is a simple type corresponding to this Vector
1668 // type. If so, convert to the vector type.
1669 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1670 if (TLI.isTypeLegal(TVT)) {
1671 // Turn this into a return of the vector type.
1672 Tmp2 = LegalizeOp(Tmp2);
1673 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1674 } else if (NumElems == 1) {
1675 // Turn this into a return of the scalar type.
1676 Tmp2 = ScalarizeVectorOp(Tmp2);
1677 Tmp2 = LegalizeOp(Tmp2);
1678 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1680 // FIXME: Returns of gcc generic vectors smaller than a legal type
1681 // should be returned in integer registers!
1683 // The scalarized value type may not be legal, e.g. it might require
1684 // promotion or expansion. Relegalize the return.
1685 Result = LegalizeOp(Result);
1687 // FIXME: Returns of gcc generic vectors larger than a legal vector
1688 // type should be returned by reference!
1690 SplitVectorOp(Tmp2, Lo, Hi);
1691 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
1692 Result = LegalizeOp(Result);
1697 Tmp2 = PromoteOp(Node->getOperand(1));
1698 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1699 Result = LegalizeOp(Result);
1704 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1706 default: { // ret <values>
1707 SmallVector<SDOperand, 8> NewValues;
1708 NewValues.push_back(Tmp1);
1709 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
1710 switch (getTypeAction(Node->getOperand(i).getValueType())) {
1712 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
1713 NewValues.push_back(Node->getOperand(i+1));
1717 assert(!MVT::isExtendedVT(Node->getOperand(i).getValueType()) &&
1718 "FIXME: TODO: implement returning non-legal vector types!");
1719 ExpandOp(Node->getOperand(i), Lo, Hi);
1720 NewValues.push_back(Lo);
1721 NewValues.push_back(Node->getOperand(i+1));
1723 NewValues.push_back(Hi);
1724 NewValues.push_back(Node->getOperand(i+1));
1729 assert(0 && "Can't promote multiple return value yet!");
1732 if (NewValues.size() == Node->getNumOperands())
1733 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
1735 Result = DAG.getNode(ISD::RET, MVT::Other,
1736 &NewValues[0], NewValues.size());
1741 if (Result.getOpcode() == ISD::RET) {
1742 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
1743 default: assert(0 && "This action is not supported yet!");
1744 case TargetLowering::Legal: break;
1745 case TargetLowering::Custom:
1746 Tmp1 = TLI.LowerOperation(Result, DAG);
1747 if (Tmp1.Val) Result = Tmp1;
1753 StoreSDNode *ST = cast<StoreSDNode>(Node);
1754 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
1755 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
1757 if (!ST->isTruncatingStore()) {
1758 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
1759 // FIXME: We shouldn't do this for TargetConstantFP's.
1760 // FIXME: move this to the DAG Combiner! Note that we can't regress due
1761 // to phase ordering between legalized code and the dag combiner. This
1762 // probably means that we need to integrate dag combiner and legalizer
1764 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
1765 if (CFP->getValueType(0) == MVT::f32) {
1766 Tmp3 = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32);
1768 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
1769 Tmp3 = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64);
1771 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1772 ST->getSrcValueOffset());
1776 switch (getTypeAction(ST->getStoredVT())) {
1778 Tmp3 = LegalizeOp(ST->getValue());
1779 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1782 MVT::ValueType VT = Tmp3.getValueType();
1783 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1784 default: assert(0 && "This action is not supported yet!");
1785 case TargetLowering::Legal: break;
1786 case TargetLowering::Custom:
1787 Tmp1 = TLI.LowerOperation(Result, DAG);
1788 if (Tmp1.Val) Result = Tmp1;
1790 case TargetLowering::Promote:
1791 assert(MVT::isVector(VT) && "Unknown legal promote case!");
1792 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
1793 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
1794 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
1795 ST->getSrcValue(), ST->getSrcValueOffset());
1801 // Truncate the value and store the result.
1802 Tmp3 = PromoteOp(ST->getValue());
1803 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1804 ST->getSrcValueOffset(), ST->getStoredVT());
1808 unsigned IncrementSize = 0;
1811 // If this is a vector type, then we have to calculate the increment as
1812 // the product of the element size in bytes, and the number of elements
1813 // in the high half of the vector.
1814 if (MVT::isVector(ST->getValue().getValueType())) {
1815 SDNode *InVal = ST->getValue().Val;
1816 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(0));
1817 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(0));
1819 // Figure out if there is a simple type corresponding to this Vector
1820 // type. If so, convert to the vector type.
1821 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1822 if (TLI.isTypeLegal(TVT)) {
1823 // Turn this into a normal store of the vector type.
1824 Tmp3 = LegalizeOp(Node->getOperand(1));
1825 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1826 ST->getSrcValueOffset(),
1828 ST->getAlignment());
1829 Result = LegalizeOp(Result);
1831 } else if (NumElems == 1) {
1832 // Turn this into a normal store of the scalar type.
1833 Tmp3 = ScalarizeVectorOp(Node->getOperand(1));
1834 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1835 ST->getSrcValueOffset(),
1837 ST->getAlignment());
1838 // The scalarized value type may not be legal, e.g. it might require
1839 // promotion or expansion. Relegalize the scalar store.
1840 Result = LegalizeOp(Result);
1843 SplitVectorOp(Node->getOperand(1), Lo, Hi);
1844 IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8;
1847 ExpandOp(Node->getOperand(1), Lo, Hi);
1848 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0;
1850 if (!TLI.isLittleEndian())
1854 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
1855 ST->getSrcValueOffset(), ST->isVolatile(),
1856 ST->getAlignment());
1858 if (Hi.Val == NULL) {
1859 // Must be int <-> float one-to-one expansion.
1864 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1865 getIntPtrConstant(IncrementSize));
1866 assert(isTypeLegal(Tmp2.getValueType()) &&
1867 "Pointers must be legal!");
1868 // FIXME: This sets the srcvalue of both halves to be the same, which is
1870 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
1871 ST->getSrcValueOffset(), ST->isVolatile(),
1872 std::min(ST->getAlignment(), IncrementSize));
1873 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
1878 assert(isTypeLegal(ST->getValue().getValueType()) &&
1879 "Cannot handle illegal TRUNCSTORE yet!");
1880 Tmp3 = LegalizeOp(ST->getValue());
1882 // The only promote case we handle is TRUNCSTORE:i1 X into
1883 // -> TRUNCSTORE:i8 (and X, 1)
1884 if (ST->getStoredVT() == MVT::i1 &&
1885 TLI.getStoreXAction(MVT::i1) == TargetLowering::Promote) {
1886 // Promote the bool to a mask then store.
1887 Tmp3 = DAG.getNode(ISD::AND, Tmp3.getValueType(), Tmp3,
1888 DAG.getConstant(1, Tmp3.getValueType()));
1889 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1890 ST->getSrcValueOffset(), MVT::i8);
1891 } else if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
1892 Tmp2 != ST->getBasePtr()) {
1893 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1897 MVT::ValueType StVT = cast<StoreSDNode>(Result.Val)->getStoredVT();
1898 switch (TLI.getStoreXAction(StVT)) {
1899 default: assert(0 && "This action is not supported yet!");
1900 case TargetLowering::Legal: break;
1901 case TargetLowering::Custom:
1902 Tmp1 = TLI.LowerOperation(Result, DAG);
1903 if (Tmp1.Val) Result = Tmp1;
1910 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1911 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1913 case ISD::STACKSAVE:
1914 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1915 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1916 Tmp1 = Result.getValue(0);
1917 Tmp2 = Result.getValue(1);
1919 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
1920 default: assert(0 && "This action is not supported yet!");
1921 case TargetLowering::Legal: break;
1922 case TargetLowering::Custom:
1923 Tmp3 = TLI.LowerOperation(Result, DAG);
1925 Tmp1 = LegalizeOp(Tmp3);
1926 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1929 case TargetLowering::Expand:
1930 // Expand to CopyFromReg if the target set
1931 // StackPointerRegisterToSaveRestore.
1932 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
1933 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
1934 Node->getValueType(0));
1935 Tmp2 = Tmp1.getValue(1);
1937 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
1938 Tmp2 = Node->getOperand(0);
1943 // Since stacksave produce two values, make sure to remember that we
1944 // legalized both of them.
1945 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1946 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1947 return Op.ResNo ? Tmp2 : Tmp1;
1949 case ISD::STACKRESTORE:
1950 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1951 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1952 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1954 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
1955 default: assert(0 && "This action is not supported yet!");
1956 case TargetLowering::Legal: break;
1957 case TargetLowering::Custom:
1958 Tmp1 = TLI.LowerOperation(Result, DAG);
1959 if (Tmp1.Val) Result = Tmp1;
1961 case TargetLowering::Expand:
1962 // Expand to CopyToReg if the target set
1963 // StackPointerRegisterToSaveRestore.
1964 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
1965 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
1973 case ISD::READCYCLECOUNTER:
1974 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
1975 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1976 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
1977 Node->getValueType(0))) {
1978 default: assert(0 && "This action is not supported yet!");
1979 case TargetLowering::Legal:
1980 Tmp1 = Result.getValue(0);
1981 Tmp2 = Result.getValue(1);
1983 case TargetLowering::Custom:
1984 Result = TLI.LowerOperation(Result, DAG);
1985 Tmp1 = LegalizeOp(Result.getValue(0));
1986 Tmp2 = LegalizeOp(Result.getValue(1));
1990 // Since rdcc produce two values, make sure to remember that we legalized
1992 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1993 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1997 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1998 case Expand: assert(0 && "It's impossible to expand bools");
2000 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2003 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2004 // Make sure the condition is either zero or one.
2005 if (!DAG.MaskedValueIsZero(Tmp1,
2006 MVT::getIntVTBitMask(Tmp1.getValueType())^1))
2007 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2010 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2011 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2013 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2015 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2016 default: assert(0 && "This action is not supported yet!");
2017 case TargetLowering::Legal: break;
2018 case TargetLowering::Custom: {
2019 Tmp1 = TLI.LowerOperation(Result, DAG);
2020 if (Tmp1.Val) Result = Tmp1;
2023 case TargetLowering::Expand:
2024 if (Tmp1.getOpcode() == ISD::SETCC) {
2025 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2027 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2029 Result = DAG.getSelectCC(Tmp1,
2030 DAG.getConstant(0, Tmp1.getValueType()),
2031 Tmp2, Tmp3, ISD::SETNE);
2034 case TargetLowering::Promote: {
2035 MVT::ValueType NVT =
2036 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2037 unsigned ExtOp, TruncOp;
2038 if (MVT::isVector(Tmp2.getValueType())) {
2039 ExtOp = ISD::BIT_CONVERT;
2040 TruncOp = ISD::BIT_CONVERT;
2041 } else if (MVT::isInteger(Tmp2.getValueType())) {
2042 ExtOp = ISD::ANY_EXTEND;
2043 TruncOp = ISD::TRUNCATE;
2045 ExtOp = ISD::FP_EXTEND;
2046 TruncOp = ISD::FP_ROUND;
2048 // Promote each of the values to the new type.
2049 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2050 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2051 // Perform the larger operation, then round down.
2052 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2053 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2058 case ISD::SELECT_CC: {
2059 Tmp1 = Node->getOperand(0); // LHS
2060 Tmp2 = Node->getOperand(1); // RHS
2061 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2062 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2063 SDOperand CC = Node->getOperand(4);
2065 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
2067 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
2068 // the LHS is a legal SETCC itself. In this case, we need to compare
2069 // the result against zero to select between true and false values.
2070 if (Tmp2.Val == 0) {
2071 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2072 CC = DAG.getCondCode(ISD::SETNE);
2074 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
2076 // Everything is legal, see if we should expand this op or something.
2077 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
2078 default: assert(0 && "This action is not supported yet!");
2079 case TargetLowering::Legal: break;
2080 case TargetLowering::Custom:
2081 Tmp1 = TLI.LowerOperation(Result, DAG);
2082 if (Tmp1.Val) Result = Tmp1;
2088 Tmp1 = Node->getOperand(0);
2089 Tmp2 = Node->getOperand(1);
2090 Tmp3 = Node->getOperand(2);
2091 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
2093 // If we had to Expand the SetCC operands into a SELECT node, then it may
2094 // not always be possible to return a true LHS & RHS. In this case, just
2095 // return the value we legalized, returned in the LHS
2096 if (Tmp2.Val == 0) {
2101 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
2102 default: assert(0 && "Cannot handle this action for SETCC yet!");
2103 case TargetLowering::Custom:
2106 case TargetLowering::Legal:
2107 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2109 Tmp4 = TLI.LowerOperation(Result, DAG);
2110 if (Tmp4.Val) Result = Tmp4;
2113 case TargetLowering::Promote: {
2114 // First step, figure out the appropriate operation to use.
2115 // Allow SETCC to not be supported for all legal data types
2116 // Mostly this targets FP
2117 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
2118 MVT::ValueType OldVT = NewInTy; OldVT = OldVT;
2120 // Scan for the appropriate larger type to use.
2122 NewInTy = (MVT::ValueType)(NewInTy+1);
2124 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
2125 "Fell off of the edge of the integer world");
2126 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
2127 "Fell off of the edge of the floating point world");
2129 // If the target supports SETCC of this type, use it.
2130 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2133 if (MVT::isInteger(NewInTy))
2134 assert(0 && "Cannot promote Legal Integer SETCC yet");
2136 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2137 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2139 Tmp1 = LegalizeOp(Tmp1);
2140 Tmp2 = LegalizeOp(Tmp2);
2141 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2142 Result = LegalizeOp(Result);
2145 case TargetLowering::Expand:
2146 // Expand a setcc node into a select_cc of the same condition, lhs, and
2147 // rhs that selects between const 1 (true) and const 0 (false).
2148 MVT::ValueType VT = Node->getValueType(0);
2149 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2150 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2157 case ISD::MEMMOVE: {
2158 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
2159 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
2161 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
2162 switch (getTypeAction(Node->getOperand(2).getValueType())) {
2163 case Expand: assert(0 && "Cannot expand a byte!");
2165 Tmp3 = LegalizeOp(Node->getOperand(2));
2168 Tmp3 = PromoteOp(Node->getOperand(2));
2172 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
2176 switch (getTypeAction(Node->getOperand(3).getValueType())) {
2178 // Length is too big, just take the lo-part of the length.
2180 ExpandOp(Node->getOperand(3), Tmp4, HiPart);
2184 Tmp4 = LegalizeOp(Node->getOperand(3));
2187 Tmp4 = PromoteOp(Node->getOperand(3));
2192 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
2193 case Expand: assert(0 && "Cannot expand this yet!");
2195 Tmp5 = LegalizeOp(Node->getOperand(4));
2198 Tmp5 = PromoteOp(Node->getOperand(4));
2202 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2203 default: assert(0 && "This action not implemented for this operation!");
2204 case TargetLowering::Custom:
2207 case TargetLowering::Legal:
2208 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, Tmp5);
2210 Tmp1 = TLI.LowerOperation(Result, DAG);
2211 if (Tmp1.Val) Result = Tmp1;
2214 case TargetLowering::Expand: {
2215 // Otherwise, the target does not support this operation. Lower the
2216 // operation to an explicit libcall as appropriate.
2217 MVT::ValueType IntPtr = TLI.getPointerTy();
2218 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType();
2219 TargetLowering::ArgListTy Args;
2220 TargetLowering::ArgListEntry Entry;
2222 const char *FnName = 0;
2223 if (Node->getOpcode() == ISD::MEMSET) {
2224 Entry.Node = Tmp2; Entry.Ty = IntPtrTy;
2225 Args.push_back(Entry);
2226 // Extend the (previously legalized) ubyte argument to be an int value
2228 if (Tmp3.getValueType() > MVT::i32)
2229 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
2231 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
2232 Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSExt = true;
2233 Args.push_back(Entry);
2234 Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSExt = false;
2235 Args.push_back(Entry);
2238 } else if (Node->getOpcode() == ISD::MEMCPY ||
2239 Node->getOpcode() == ISD::MEMMOVE) {
2240 Entry.Ty = IntPtrTy;
2241 Entry.Node = Tmp2; Args.push_back(Entry);
2242 Entry.Node = Tmp3; Args.push_back(Entry);
2243 Entry.Node = Tmp4; Args.push_back(Entry);
2244 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
2246 assert(0 && "Unknown op!");
2249 std::pair<SDOperand,SDOperand> CallResult =
2250 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, CallingConv::C, false,
2251 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
2252 Result = CallResult.second;
2259 case ISD::SHL_PARTS:
2260 case ISD::SRA_PARTS:
2261 case ISD::SRL_PARTS: {
2262 SmallVector<SDOperand, 8> Ops;
2263 bool Changed = false;
2264 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2265 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2266 Changed |= Ops.back() != Node->getOperand(i);
2269 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2271 switch (TLI.getOperationAction(Node->getOpcode(),
2272 Node->getValueType(0))) {
2273 default: assert(0 && "This action is not supported yet!");
2274 case TargetLowering::Legal: break;
2275 case TargetLowering::Custom:
2276 Tmp1 = TLI.LowerOperation(Result, DAG);
2278 SDOperand Tmp2, RetVal(0, 0);
2279 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2280 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2281 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2285 assert(RetVal.Val && "Illegal result number");
2291 // Since these produce multiple values, make sure to remember that we
2292 // legalized all of them.
2293 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2294 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2295 return Result.getValue(Op.ResNo);
2316 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2317 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2318 case Expand: assert(0 && "Not possible");
2320 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2323 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2327 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2329 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2330 default: assert(0 && "BinOp legalize operation not supported");
2331 case TargetLowering::Legal: break;
2332 case TargetLowering::Custom:
2333 Tmp1 = TLI.LowerOperation(Result, DAG);
2334 if (Tmp1.Val) Result = Tmp1;
2336 case TargetLowering::Expand: {
2337 if (Node->getValueType(0) == MVT::i32) {
2338 switch (Node->getOpcode()) {
2339 default: assert(0 && "Do not know how to expand this integer BinOp!");
2342 RTLIB::Libcall LC = Node->getOpcode() == ISD::UDIV
2343 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
2345 bool isSigned = Node->getOpcode() == ISD::SDIV;
2346 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
2351 assert(MVT::isVector(Node->getValueType(0)) &&
2352 "Cannot expand this binary operator!");
2353 // Expand the operation into a bunch of nasty scalar code.
2354 SmallVector<SDOperand, 8> Ops;
2355 MVT::ValueType EltVT = MVT::getVectorElementType(Node->getValueType(0));
2356 MVT::ValueType PtrVT = TLI.getPointerTy();
2357 for (unsigned i = 0, e = MVT::getVectorNumElements(Node->getValueType(0));
2359 SDOperand Idx = DAG.getConstant(i, PtrVT);
2360 SDOperand LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, Idx);
2361 SDOperand RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, Idx);
2362 Ops.push_back(DAG.getNode(Node->getOpcode(), EltVT, LHS, RHS));
2364 Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0),
2365 &Ops[0], Ops.size());
2368 case TargetLowering::Promote: {
2369 switch (Node->getOpcode()) {
2370 default: assert(0 && "Do not know how to promote this BinOp!");
2374 MVT::ValueType OVT = Node->getValueType(0);
2375 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2376 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
2377 // Bit convert each of the values to the new type.
2378 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
2379 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
2380 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2381 // Bit convert the result back the original type.
2382 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
2390 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
2391 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2392 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2393 case Expand: assert(0 && "Not possible");
2395 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2398 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2402 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2404 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2405 default: assert(0 && "Operation not supported");
2406 case TargetLowering::Custom:
2407 Tmp1 = TLI.LowerOperation(Result, DAG);
2408 if (Tmp1.Val) Result = Tmp1;
2410 case TargetLowering::Legal: break;
2411 case TargetLowering::Expand: {
2412 // If this target supports fabs/fneg natively and select is cheap,
2413 // do this efficiently.
2414 if (!TLI.isSelectExpensive() &&
2415 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
2416 TargetLowering::Legal &&
2417 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
2418 TargetLowering::Legal) {
2419 // Get the sign bit of the RHS.
2420 MVT::ValueType IVT =
2421 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
2422 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
2423 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
2424 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
2425 // Get the absolute value of the result.
2426 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
2427 // Select between the nabs and abs value based on the sign bit of
2429 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
2430 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
2433 Result = LegalizeOp(Result);
2437 // Otherwise, do bitwise ops!
2438 MVT::ValueType NVT =
2439 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
2440 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
2441 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
2442 Result = LegalizeOp(Result);
2450 Tmp1 = LegalizeOp(Node->getOperand(0));
2451 Tmp2 = LegalizeOp(Node->getOperand(1));
2452 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2453 // Since this produces two values, make sure to remember that we legalized
2455 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2456 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2461 Tmp1 = LegalizeOp(Node->getOperand(0));
2462 Tmp2 = LegalizeOp(Node->getOperand(1));
2463 Tmp3 = LegalizeOp(Node->getOperand(2));
2464 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2465 // Since this produces two values, make sure to remember that we legalized
2467 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2468 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2471 case ISD::BUILD_PAIR: {
2472 MVT::ValueType PairTy = Node->getValueType(0);
2473 // TODO: handle the case where the Lo and Hi operands are not of legal type
2474 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
2475 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
2476 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
2477 case TargetLowering::Promote:
2478 case TargetLowering::Custom:
2479 assert(0 && "Cannot promote/custom this yet!");
2480 case TargetLowering::Legal:
2481 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
2482 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
2484 case TargetLowering::Expand:
2485 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
2486 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
2487 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
2488 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
2489 TLI.getShiftAmountTy()));
2490 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
2499 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2500 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2502 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2503 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
2504 case TargetLowering::Custom:
2507 case TargetLowering::Legal:
2508 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2510 Tmp1 = TLI.LowerOperation(Result, DAG);
2511 if (Tmp1.Val) Result = Tmp1;
2514 case TargetLowering::Expand:
2515 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
2516 bool isSigned = DivOpc == ISD::SDIV;
2517 if (MVT::isInteger(Node->getValueType(0))) {
2518 if (TLI.getOperationAction(DivOpc, Node->getValueType(0)) ==
2519 TargetLowering::Legal) {
2521 MVT::ValueType VT = Node->getValueType(0);
2522 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
2523 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
2524 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
2526 assert(Node->getValueType(0) == MVT::i32 &&
2527 "Cannot expand this binary operator!");
2528 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
2529 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
2531 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
2534 // Floating point mod -> fmod libcall.
2535 RTLIB::Libcall LC = Node->getValueType(0) == MVT::f32
2536 ? RTLIB::REM_F32 : RTLIB::REM_F64;
2538 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
2539 false/*sign irrelevant*/, Dummy);
2545 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2546 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2548 MVT::ValueType VT = Node->getValueType(0);
2549 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2550 default: assert(0 && "This action is not supported yet!");
2551 case TargetLowering::Custom:
2554 case TargetLowering::Legal:
2555 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2556 Result = Result.getValue(0);
2557 Tmp1 = Result.getValue(1);
2560 Tmp2 = TLI.LowerOperation(Result, DAG);
2562 Result = LegalizeOp(Tmp2);
2563 Tmp1 = LegalizeOp(Tmp2.getValue(1));
2567 case TargetLowering::Expand: {
2568 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
2569 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
2570 SV->getValue(), SV->getOffset());
2571 // Increment the pointer, VAList, to the next vaarg
2572 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
2573 DAG.getConstant(MVT::getSizeInBits(VT)/8,
2574 TLI.getPointerTy()));
2575 // Store the incremented VAList to the legalized pointer
2576 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
2578 // Load the actual argument out of the pointer VAList
2579 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
2580 Tmp1 = LegalizeOp(Result.getValue(1));
2581 Result = LegalizeOp(Result);
2585 // Since VAARG produces two values, make sure to remember that we
2586 // legalized both of them.
2587 AddLegalizedOperand(SDOperand(Node, 0), Result);
2588 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
2589 return Op.ResNo ? Tmp1 : Result;
2593 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2594 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
2595 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
2597 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
2598 default: assert(0 && "This action is not supported yet!");
2599 case TargetLowering::Custom:
2602 case TargetLowering::Legal:
2603 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
2604 Node->getOperand(3), Node->getOperand(4));
2606 Tmp1 = TLI.LowerOperation(Result, DAG);
2607 if (Tmp1.Val) Result = Tmp1;
2610 case TargetLowering::Expand:
2611 // This defaults to loading a pointer from the input and storing it to the
2612 // output, returning the chain.
2613 SrcValueSDNode *SVD = cast<SrcValueSDNode>(Node->getOperand(3));
2614 SrcValueSDNode *SVS = cast<SrcValueSDNode>(Node->getOperand(4));
2615 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD->getValue(),
2617 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, SVS->getValue(),
2624 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2625 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2627 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
2628 default: assert(0 && "This action is not supported yet!");
2629 case TargetLowering::Custom:
2632 case TargetLowering::Legal:
2633 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2635 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
2636 if (Tmp1.Val) Result = Tmp1;
2639 case TargetLowering::Expand:
2640 Result = Tmp1; // Default to a no-op, return the chain
2646 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2647 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2649 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2651 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
2652 default: assert(0 && "This action is not supported yet!");
2653 case TargetLowering::Legal: break;
2654 case TargetLowering::Custom:
2655 Tmp1 = TLI.LowerOperation(Result, DAG);
2656 if (Tmp1.Val) Result = Tmp1;
2663 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2664 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2665 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2666 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2668 assert(0 && "ROTL/ROTR legalize operation not supported");
2670 case TargetLowering::Legal:
2672 case TargetLowering::Custom:
2673 Tmp1 = TLI.LowerOperation(Result, DAG);
2674 if (Tmp1.Val) Result = Tmp1;
2676 case TargetLowering::Promote:
2677 assert(0 && "Do not know how to promote ROTL/ROTR");
2679 case TargetLowering::Expand:
2680 assert(0 && "Do not know how to expand ROTL/ROTR");
2686 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2687 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2688 case TargetLowering::Custom:
2689 assert(0 && "Cannot custom legalize this yet!");
2690 case TargetLowering::Legal:
2691 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2693 case TargetLowering::Promote: {
2694 MVT::ValueType OVT = Tmp1.getValueType();
2695 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2696 unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT);
2698 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2699 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
2700 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
2701 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
2704 case TargetLowering::Expand:
2705 Result = ExpandBSWAP(Tmp1);
2713 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2714 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2715 case TargetLowering::Custom: assert(0 && "Cannot custom handle this yet!");
2716 case TargetLowering::Legal:
2717 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2719 case TargetLowering::Promote: {
2720 MVT::ValueType OVT = Tmp1.getValueType();
2721 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2723 // Zero extend the argument.
2724 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2725 // Perform the larger operation, then subtract if needed.
2726 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2727 switch (Node->getOpcode()) {
2732 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2733 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
2734 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
2736 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
2737 DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1);
2740 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2741 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
2742 DAG.getConstant(MVT::getSizeInBits(NVT) -
2743 MVT::getSizeInBits(OVT), NVT));
2748 case TargetLowering::Expand:
2749 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
2760 Tmp1 = LegalizeOp(Node->getOperand(0));
2761 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2762 case TargetLowering::Promote:
2763 case TargetLowering::Custom:
2766 case TargetLowering::Legal:
2767 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2769 Tmp1 = TLI.LowerOperation(Result, DAG);
2770 if (Tmp1.Val) Result = Tmp1;
2773 case TargetLowering::Expand:
2774 switch (Node->getOpcode()) {
2775 default: assert(0 && "Unreachable!");
2777 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2778 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2779 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
2782 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2783 MVT::ValueType VT = Node->getValueType(0);
2784 Tmp2 = DAG.getConstantFP(0.0, VT);
2785 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
2786 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
2787 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
2793 MVT::ValueType VT = Node->getValueType(0);
2794 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2795 switch(Node->getOpcode()) {
2797 LC = VT == MVT::f32 ? RTLIB::SQRT_F32 : RTLIB::SQRT_F64;
2800 LC = VT == MVT::f32 ? RTLIB::SIN_F32 : RTLIB::SIN_F64;
2803 LC = VT == MVT::f32 ? RTLIB::COS_F32 : RTLIB::COS_F64;
2805 default: assert(0 && "Unreachable!");
2808 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
2809 false/*sign irrelevant*/, Dummy);
2817 // We always lower FPOWI into a libcall. No target support it yet.
2818 RTLIB::Libcall LC = Node->getValueType(0) == MVT::f32
2819 ? RTLIB::POWI_F32 : RTLIB::POWI_F64;
2821 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
2822 false/*sign irrelevant*/, Dummy);
2825 case ISD::BIT_CONVERT:
2826 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
2827 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2828 } else if (MVT::isVector(Op.getOperand(0).getValueType())) {
2829 // The input has to be a vector type, we have to either scalarize it, pack
2830 // it, or convert it based on whether the input vector type is legal.
2831 SDNode *InVal = Node->getOperand(0).Val;
2832 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(0));
2833 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(0));
2835 // Figure out if there is a simple type corresponding to this Vector
2836 // type. If so, convert to the vector type.
2837 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2838 if (TLI.isTypeLegal(TVT)) {
2839 // Turn this into a bit convert of the packed input.
2840 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
2841 LegalizeOp(Node->getOperand(0)));
2843 } else if (NumElems == 1) {
2844 // Turn this into a bit convert of the scalar input.
2845 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
2846 ScalarizeVectorOp(Node->getOperand(0)));
2849 // FIXME: UNIMP! Store then reload
2850 assert(0 && "Cast from unsupported vector type not implemented yet!");
2853 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
2854 Node->getOperand(0).getValueType())) {
2855 default: assert(0 && "Unknown operation action!");
2856 case TargetLowering::Expand:
2857 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2859 case TargetLowering::Legal:
2860 Tmp1 = LegalizeOp(Node->getOperand(0));
2861 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2867 // Conversion operators. The source and destination have different types.
2868 case ISD::SINT_TO_FP:
2869 case ISD::UINT_TO_FP: {
2870 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
2871 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2873 switch (TLI.getOperationAction(Node->getOpcode(),
2874 Node->getOperand(0).getValueType())) {
2875 default: assert(0 && "Unknown operation action!");
2876 case TargetLowering::Custom:
2879 case TargetLowering::Legal:
2880 Tmp1 = LegalizeOp(Node->getOperand(0));
2881 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2883 Tmp1 = TLI.LowerOperation(Result, DAG);
2884 if (Tmp1.Val) Result = Tmp1;
2887 case TargetLowering::Expand:
2888 Result = ExpandLegalINT_TO_FP(isSigned,
2889 LegalizeOp(Node->getOperand(0)),
2890 Node->getValueType(0));
2892 case TargetLowering::Promote:
2893 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
2894 Node->getValueType(0),
2900 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
2901 Node->getValueType(0), Node->getOperand(0));
2904 Tmp1 = PromoteOp(Node->getOperand(0));
2906 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
2907 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
2909 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
2910 Node->getOperand(0).getValueType());
2912 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2913 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
2919 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2921 Tmp1 = LegalizeOp(Node->getOperand(0));
2922 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2925 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2927 // Since the result is legal, we should just be able to truncate the low
2928 // part of the source.
2929 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
2932 Result = PromoteOp(Node->getOperand(0));
2933 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
2938 case ISD::FP_TO_SINT:
2939 case ISD::FP_TO_UINT:
2940 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2942 Tmp1 = LegalizeOp(Node->getOperand(0));
2944 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
2945 default: assert(0 && "Unknown operation action!");
2946 case TargetLowering::Custom:
2949 case TargetLowering::Legal:
2950 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2952 Tmp1 = TLI.LowerOperation(Result, DAG);
2953 if (Tmp1.Val) Result = Tmp1;
2956 case TargetLowering::Promote:
2957 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
2958 Node->getOpcode() == ISD::FP_TO_SINT);
2960 case TargetLowering::Expand:
2961 if (Node->getOpcode() == ISD::FP_TO_UINT) {
2962 SDOperand True, False;
2963 MVT::ValueType VT = Node->getOperand(0).getValueType();
2964 MVT::ValueType NVT = Node->getValueType(0);
2965 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1;
2966 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT);
2967 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
2968 Node->getOperand(0), Tmp2, ISD::SETLT);
2969 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
2970 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
2971 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
2973 False = DAG.getNode(ISD::XOR, NVT, False,
2974 DAG.getConstant(1ULL << ShiftAmt, NVT));
2975 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
2978 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
2984 // Convert f32 / f64 to i32 / i64.
2985 MVT::ValueType VT = Op.getValueType();
2986 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2987 switch (Node->getOpcode()) {
2988 case ISD::FP_TO_SINT:
2989 if (Node->getOperand(0).getValueType() == MVT::f32)
2990 LC = (VT == MVT::i32)
2991 ? RTLIB::FPTOSINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
2993 LC = (VT == MVT::i32)
2994 ? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
2996 case ISD::FP_TO_UINT:
2997 if (Node->getOperand(0).getValueType() == MVT::f32)
2998 LC = (VT == MVT::i32)
2999 ? RTLIB::FPTOUINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3001 LC = (VT == MVT::i32)
3002 ? RTLIB::FPTOUINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3004 default: assert(0 && "Unreachable!");
3007 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3008 false/*sign irrelevant*/, Dummy);
3012 Tmp1 = PromoteOp(Node->getOperand(0));
3013 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
3014 Result = LegalizeOp(Result);
3019 case ISD::ANY_EXTEND:
3020 case ISD::ZERO_EXTEND:
3021 case ISD::SIGN_EXTEND:
3022 case ISD::FP_EXTEND:
3024 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3025 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3027 Tmp1 = LegalizeOp(Node->getOperand(0));
3028 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3031 switch (Node->getOpcode()) {
3032 case ISD::ANY_EXTEND:
3033 Tmp1 = PromoteOp(Node->getOperand(0));
3034 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
3036 case ISD::ZERO_EXTEND:
3037 Result = PromoteOp(Node->getOperand(0));
3038 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3039 Result = DAG.getZeroExtendInReg(Result,
3040 Node->getOperand(0).getValueType());
3042 case ISD::SIGN_EXTEND:
3043 Result = PromoteOp(Node->getOperand(0));
3044 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3045 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3047 DAG.getValueType(Node->getOperand(0).getValueType()));
3049 case ISD::FP_EXTEND:
3050 Result = PromoteOp(Node->getOperand(0));
3051 if (Result.getValueType() != Op.getValueType())
3052 // Dynamically dead while we have only 2 FP types.
3053 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result);
3056 Result = PromoteOp(Node->getOperand(0));
3057 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
3062 case ISD::FP_ROUND_INREG:
3063 case ISD::SIGN_EXTEND_INREG: {
3064 Tmp1 = LegalizeOp(Node->getOperand(0));
3065 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3067 // If this operation is not supported, convert it to a shl/shr or load/store
3069 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
3070 default: assert(0 && "This action not supported for this op yet!");
3071 case TargetLowering::Legal:
3072 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3074 case TargetLowering::Expand:
3075 // If this is an integer extend and shifts are supported, do that.
3076 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
3077 // NOTE: we could fall back on load/store here too for targets without
3078 // SAR. However, it is doubtful that any exist.
3079 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
3080 MVT::getSizeInBits(ExtraVT);
3081 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
3082 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
3083 Node->getOperand(0), ShiftCst);
3084 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
3086 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
3087 // The only way we can lower this is to turn it into a TRUNCSTORE,
3088 // EXTLOAD pair, targetting a temporary location (a stack slot).
3090 // NOTE: there is a choice here between constantly creating new stack
3091 // slots and always reusing the same one. We currently always create
3092 // new ones, as reuse may inhibit scheduling.
3093 const Type *Ty = MVT::getTypeForValueType(ExtraVT);
3094 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
3095 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
3096 MachineFunction &MF = DAG.getMachineFunction();
3098 MF.getFrameInfo()->CreateStackObject(TySize, Align);
3099 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3100 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0),
3101 StackSlot, NULL, 0, ExtraVT);
3102 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
3103 Result, StackSlot, NULL, 0, ExtraVT);
3105 assert(0 && "Unknown op");
3113 assert(Result.getValueType() == Op.getValueType() &&
3114 "Bad legalization!");
3116 // Make sure that the generated code is itself legal.
3118 Result = LegalizeOp(Result);
3120 // Note that LegalizeOp may be reentered even from single-use nodes, which
3121 // means that we always must cache transformed nodes.
3122 AddLegalizedOperand(Op, Result);
3126 /// PromoteOp - Given an operation that produces a value in an invalid type,
3127 /// promote it to compute the value into a larger type. The produced value will
3128 /// have the correct bits for the low portion of the register, but no guarantee
3129 /// is made about the top bits: it may be zero, sign-extended, or garbage.
3130 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
3131 MVT::ValueType VT = Op.getValueType();
3132 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3133 assert(getTypeAction(VT) == Promote &&
3134 "Caller should expand or legalize operands that are not promotable!");
3135 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
3136 "Cannot promote to smaller type!");
3138 SDOperand Tmp1, Tmp2, Tmp3;
3140 SDNode *Node = Op.Val;
3142 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
3143 if (I != PromotedNodes.end()) return I->second;
3145 switch (Node->getOpcode()) {
3146 case ISD::CopyFromReg:
3147 assert(0 && "CopyFromReg must be legal!");
3150 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
3152 assert(0 && "Do not know how to promote this operator!");
3155 Result = DAG.getNode(ISD::UNDEF, NVT);
3159 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
3161 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
3162 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
3164 case ISD::ConstantFP:
3165 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
3166 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
3170 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
3171 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
3172 Node->getOperand(1), Node->getOperand(2));
3176 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3178 Result = LegalizeOp(Node->getOperand(0));
3179 assert(Result.getValueType() >= NVT &&
3180 "This truncation doesn't make sense!");
3181 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
3182 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
3185 // The truncation is not required, because we don't guarantee anything
3186 // about high bits anyway.
3187 Result = PromoteOp(Node->getOperand(0));
3190 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3191 // Truncate the low part of the expanded value to the result type
3192 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
3195 case ISD::SIGN_EXTEND:
3196 case ISD::ZERO_EXTEND:
3197 case ISD::ANY_EXTEND:
3198 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3199 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
3201 // Input is legal? Just do extend all the way to the larger type.
3202 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
3205 // Promote the reg if it's smaller.
3206 Result = PromoteOp(Node->getOperand(0));
3207 // The high bits are not guaranteed to be anything. Insert an extend.
3208 if (Node->getOpcode() == ISD::SIGN_EXTEND)
3209 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3210 DAG.getValueType(Node->getOperand(0).getValueType()));
3211 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
3212 Result = DAG.getZeroExtendInReg(Result,
3213 Node->getOperand(0).getValueType());
3217 case ISD::BIT_CONVERT:
3218 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
3219 Result = PromoteOp(Result);
3222 case ISD::FP_EXTEND:
3223 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
3225 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3226 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
3227 case Promote: assert(0 && "Unreachable with 2 FP types!");
3229 // Input is legal? Do an FP_ROUND_INREG.
3230 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
3231 DAG.getValueType(VT));
3236 case ISD::SINT_TO_FP:
3237 case ISD::UINT_TO_FP:
3238 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3240 // No extra round required here.
3241 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
3245 Result = PromoteOp(Node->getOperand(0));
3246 if (Node->getOpcode() == ISD::SINT_TO_FP)
3247 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3249 DAG.getValueType(Node->getOperand(0).getValueType()));
3251 Result = DAG.getZeroExtendInReg(Result,
3252 Node->getOperand(0).getValueType());
3253 // No extra round required here.
3254 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
3257 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
3258 Node->getOperand(0));
3259 // Round if we cannot tolerate excess precision.
3260 if (NoExcessFPPrecision)
3261 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3262 DAG.getValueType(VT));
3267 case ISD::SIGN_EXTEND_INREG:
3268 Result = PromoteOp(Node->getOperand(0));
3269 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3270 Node->getOperand(1));
3272 case ISD::FP_TO_SINT:
3273 case ISD::FP_TO_UINT:
3274 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3277 Tmp1 = Node->getOperand(0);
3280 // The input result is prerounded, so we don't have to do anything
3282 Tmp1 = PromoteOp(Node->getOperand(0));
3285 // If we're promoting a UINT to a larger size, check to see if the new node
3286 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
3287 // we can use that instead. This allows us to generate better code for
3288 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
3289 // legal, such as PowerPC.
3290 if (Node->getOpcode() == ISD::FP_TO_UINT &&
3291 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
3292 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
3293 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
3294 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
3296 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3302 Tmp1 = PromoteOp(Node->getOperand(0));
3303 assert(Tmp1.getValueType() == NVT);
3304 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3305 // NOTE: we do not have to do any extra rounding here for
3306 // NoExcessFPPrecision, because we know the input will have the appropriate
3307 // precision, and these operations don't modify precision at all.
3313 Tmp1 = PromoteOp(Node->getOperand(0));
3314 assert(Tmp1.getValueType() == NVT);
3315 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3316 if (NoExcessFPPrecision)
3317 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3318 DAG.getValueType(VT));
3322 // Promote f32 powi to f64 powi. Note that this could insert a libcall
3323 // directly as well, which may be better.
3324 Tmp1 = PromoteOp(Node->getOperand(0));
3325 assert(Tmp1.getValueType() == NVT);
3326 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1));
3327 if (NoExcessFPPrecision)
3328 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3329 DAG.getValueType(VT));
3339 // The input may have strange things in the top bits of the registers, but
3340 // these operations don't care. They may have weird bits going out, but
3341 // that too is okay if they are integer operations.
3342 Tmp1 = PromoteOp(Node->getOperand(0));
3343 Tmp2 = PromoteOp(Node->getOperand(1));
3344 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3345 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3350 Tmp1 = PromoteOp(Node->getOperand(0));
3351 Tmp2 = PromoteOp(Node->getOperand(1));
3352 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3353 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3355 // Floating point operations will give excess precision that we may not be
3356 // able to tolerate. If we DO allow excess precision, just leave it,
3357 // otherwise excise it.
3358 // FIXME: Why would we need to round FP ops more than integer ones?
3359 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
3360 if (NoExcessFPPrecision)
3361 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3362 DAG.getValueType(VT));
3367 // These operators require that their input be sign extended.
3368 Tmp1 = PromoteOp(Node->getOperand(0));
3369 Tmp2 = PromoteOp(Node->getOperand(1));
3370 if (MVT::isInteger(NVT)) {
3371 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3372 DAG.getValueType(VT));
3373 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3374 DAG.getValueType(VT));
3376 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3378 // Perform FP_ROUND: this is probably overly pessimistic.
3379 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
3380 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3381 DAG.getValueType(VT));
3385 case ISD::FCOPYSIGN:
3386 // These operators require that their input be fp extended.
3387 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3389 Tmp1 = LegalizeOp(Node->getOperand(0));
3392 Tmp1 = PromoteOp(Node->getOperand(0));
3395 assert(0 && "not implemented");
3397 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3399 Tmp2 = LegalizeOp(Node->getOperand(1));
3402 Tmp2 = PromoteOp(Node->getOperand(1));
3405 assert(0 && "not implemented");
3407 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3409 // Perform FP_ROUND: this is probably overly pessimistic.
3410 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
3411 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3412 DAG.getValueType(VT));
3417 // These operators require that their input be zero extended.
3418 Tmp1 = PromoteOp(Node->getOperand(0));
3419 Tmp2 = PromoteOp(Node->getOperand(1));
3420 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
3421 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3422 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3423 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3427 Tmp1 = PromoteOp(Node->getOperand(0));
3428 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
3431 // The input value must be properly sign extended.
3432 Tmp1 = PromoteOp(Node->getOperand(0));
3433 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3434 DAG.getValueType(VT));
3435 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
3438 // The input value must be properly zero extended.
3439 Tmp1 = PromoteOp(Node->getOperand(0));
3440 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3441 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
3445 Tmp1 = Node->getOperand(0); // Get the chain.
3446 Tmp2 = Node->getOperand(1); // Get the pointer.
3447 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
3448 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
3449 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
3451 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
3452 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
3453 SV->getValue(), SV->getOffset());
3454 // Increment the pointer, VAList, to the next vaarg
3455 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3456 DAG.getConstant(MVT::getSizeInBits(VT)/8,
3457 TLI.getPointerTy()));
3458 // Store the incremented VAList to the legalized pointer
3459 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
3461 // Load the actual argument out of the pointer VAList
3462 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
3464 // Remember that we legalized the chain.
3465 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3469 LoadSDNode *LD = cast<LoadSDNode>(Node);
3470 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
3471 ? ISD::EXTLOAD : LD->getExtensionType();
3472 Result = DAG.getExtLoad(ExtType, NVT,
3473 LD->getChain(), LD->getBasePtr(),
3474 LD->getSrcValue(), LD->getSrcValueOffset(),
3476 // Remember that we legalized the chain.
3477 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3481 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
3482 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
3483 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
3485 case ISD::SELECT_CC:
3486 Tmp2 = PromoteOp(Node->getOperand(2)); // True
3487 Tmp3 = PromoteOp(Node->getOperand(3)); // False
3488 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3489 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
3492 Tmp1 = Node->getOperand(0);
3493 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3494 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3495 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3496 DAG.getConstant(MVT::getSizeInBits(NVT) -
3497 MVT::getSizeInBits(VT),
3498 TLI.getShiftAmountTy()));
3503 // Zero extend the argument
3504 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
3505 // Perform the larger operation, then subtract if needed.
3506 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3507 switch(Node->getOpcode()) {
3512 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3513 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
3514 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
3516 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3517 DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1);
3520 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3521 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3522 DAG.getConstant(MVT::getSizeInBits(NVT) -
3523 MVT::getSizeInBits(VT), NVT));
3527 case ISD::EXTRACT_SUBVECTOR:
3528 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
3530 case ISD::EXTRACT_VECTOR_ELT:
3531 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
3535 assert(Result.Val && "Didn't set a result!");
3537 // Make sure the result is itself legal.
3538 Result = LegalizeOp(Result);
3540 // Remember that we promoted this!
3541 AddPromotedOperand(Op, Result);
3545 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
3546 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
3547 /// based on the vector type. The return type of this matches the element type
3548 /// of the vector, which may not be legal for the target.
3549 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
3550 // We know that operand #0 is the Vec vector. If the index is a constant
3551 // or if the invec is a supported hardware type, we can use it. Otherwise,
3552 // lower to a store then an indexed load.
3553 SDOperand Vec = Op.getOperand(0);
3554 SDOperand Idx = Op.getOperand(1);
3556 SDNode *InVal = Vec.Val;
3557 MVT::ValueType TVT = InVal->getValueType(0);
3558 unsigned NumElems = MVT::getVectorNumElements(TVT);
3560 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
3561 default: assert(0 && "This action is not supported yet!");
3562 case TargetLowering::Custom: {
3563 Vec = LegalizeOp(Vec);
3564 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3565 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG);
3570 case TargetLowering::Legal:
3571 if (isTypeLegal(TVT)) {
3572 Vec = LegalizeOp(Vec);
3573 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3574 Op = LegalizeOp(Op);
3577 case TargetLowering::Expand:
3581 if (NumElems == 1) {
3582 // This must be an access of the only element. Return it.
3583 Op = ScalarizeVectorOp(Vec);
3584 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
3585 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
3587 SplitVectorOp(Vec, Lo, Hi);
3588 if (CIdx->getValue() < NumElems/2) {
3592 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2,
3593 Idx.getValueType());
3596 // It's now an extract from the appropriate high or low part. Recurse.
3597 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3598 Op = ExpandEXTRACT_VECTOR_ELT(Op);
3600 // Store the value to a temporary stack slot, then LOAD the scalar
3601 // element back out.
3602 SDOperand StackPtr = CreateStackTemporary(Vec.getValueType());
3603 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
3605 // Add the offset to the index.
3606 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
3607 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
3608 DAG.getConstant(EltSize, Idx.getValueType()));
3609 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
3611 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
3616 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
3617 /// we assume the operation can be split if it is not already legal.
3618 SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) {
3619 // We know that operand #0 is the Vec vector. For now we assume the index
3620 // is a constant and that the extracted result is a supported hardware type.
3621 SDOperand Vec = Op.getOperand(0);
3622 SDOperand Idx = LegalizeOp(Op.getOperand(1));
3624 unsigned NumElems = MVT::getVectorNumElements(Vec.getValueType());
3626 if (NumElems == MVT::getVectorNumElements(Op.getValueType())) {
3627 // This must be an access of the desired vector length. Return it.
3631 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
3633 SplitVectorOp(Vec, Lo, Hi);
3634 if (CIdx->getValue() < NumElems/2) {
3638 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
3641 // It's now an extract from the appropriate high or low part. Recurse.
3642 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3643 return ExpandEXTRACT_SUBVECTOR(Op);
3646 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
3647 /// with condition CC on the current target. This usually involves legalizing
3648 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
3649 /// there may be no choice but to create a new SetCC node to represent the
3650 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
3651 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
3652 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
3655 SDOperand Tmp1, Tmp2, Result;
3657 switch (getTypeAction(LHS.getValueType())) {
3659 Tmp1 = LegalizeOp(LHS); // LHS
3660 Tmp2 = LegalizeOp(RHS); // RHS
3663 Tmp1 = PromoteOp(LHS); // LHS
3664 Tmp2 = PromoteOp(RHS); // RHS
3666 // If this is an FP compare, the operands have already been extended.
3667 if (MVT::isInteger(LHS.getValueType())) {
3668 MVT::ValueType VT = LHS.getValueType();
3669 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3671 // Otherwise, we have to insert explicit sign or zero extends. Note
3672 // that we could insert sign extends for ALL conditions, but zero extend
3673 // is cheaper on many machines (an AND instead of two shifts), so prefer
3675 switch (cast<CondCodeSDNode>(CC)->get()) {
3676 default: assert(0 && "Unknown integer comparison!");
3683 // ALL of these operations will work if we either sign or zero extend
3684 // the operands (including the unsigned comparisons!). Zero extend is
3685 // usually a simpler/cheaper operation, so prefer it.
3686 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3687 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3693 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3694 DAG.getValueType(VT));
3695 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3696 DAG.getValueType(VT));
3702 MVT::ValueType VT = LHS.getValueType();
3703 if (VT == MVT::f32 || VT == MVT::f64) {
3704 // Expand into one or more soft-fp libcall(s).
3705 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL;
3706 switch (cast<CondCodeSDNode>(CC)->get()) {
3709 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
3713 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
3717 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
3721 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
3725 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
3729 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
3732 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
3735 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
3738 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
3739 switch (cast<CondCodeSDNode>(CC)->get()) {
3741 // SETONE = SETOLT | SETOGT
3742 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
3745 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
3748 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
3751 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
3754 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
3757 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
3759 default: assert(0 && "Unsupported FP setcc!");
3764 Tmp1 = ExpandLibCall(TLI.getLibcallName(LC1),
3765 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
3766 false /*sign irrelevant*/, Dummy);
3767 Tmp2 = DAG.getConstant(0, MVT::i32);
3768 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
3769 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
3770 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC);
3771 LHS = ExpandLibCall(TLI.getLibcallName(LC2),
3772 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
3773 false /*sign irrelevant*/, Dummy);
3774 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2,
3775 DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
3776 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
3784 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
3785 ExpandOp(LHS, LHSLo, LHSHi);
3786 ExpandOp(RHS, RHSLo, RHSHi);
3787 switch (cast<CondCodeSDNode>(CC)->get()) {
3791 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
3792 if (RHSCST->isAllOnesValue()) {
3793 // Comparison to -1.
3794 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
3799 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
3800 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
3801 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
3802 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3805 // If this is a comparison of the sign bit, just look at the top part.
3807 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
3808 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
3809 CST->getValue() == 0) || // X < 0
3810 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
3811 CST->isAllOnesValue())) { // X > -1
3817 // FIXME: This generated code sucks.
3818 ISD::CondCode LowCC;
3819 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
3821 default: assert(0 && "Unknown integer setcc!");
3823 case ISD::SETULT: LowCC = ISD::SETULT; break;
3825 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
3827 case ISD::SETULE: LowCC = ISD::SETULE; break;
3829 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
3832 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
3833 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
3834 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
3836 // NOTE: on targets without efficient SELECT of bools, we can always use
3837 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
3838 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
3839 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC,
3840 false, DagCombineInfo);
3842 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
3843 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
3844 CCCode, false, DagCombineInfo);
3846 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi, CC);
3848 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
3849 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
3850 if ((Tmp1C && Tmp1C->getValue() == 0) ||
3851 (Tmp2C && Tmp2C->getValue() == 0 &&
3852 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
3853 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
3854 (Tmp2C && Tmp2C->getValue() == 1 &&
3855 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
3856 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
3857 // low part is known false, returns high part.
3858 // For LE / GE, if high part is known false, ignore the low part.
3859 // For LT / GT, if high part is known true, ignore the low part.
3863 Result = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
3864 ISD::SETEQ, false, DagCombineInfo);
3866 Result=DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
3867 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
3868 Result, Tmp1, Tmp2));
3879 /// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination.
3880 /// The resultant code need not be legal. Note that SrcOp is the input operand
3881 /// to the BIT_CONVERT, not the BIT_CONVERT node itself.
3882 SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT,
3884 // Create the stack frame object.
3885 SDOperand FIPtr = CreateStackTemporary(DestVT);
3887 // Emit a store to the stack slot.
3888 SDOperand Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0);
3889 // Result is a load from the stack slot.
3890 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0);
3893 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
3894 // Create a vector sized/aligned stack slot, store the value to element #0,
3895 // then load the whole vector back out.
3896 SDOperand StackPtr = CreateStackTemporary(Node->getValueType(0));
3897 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
3899 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, NULL, 0);
3903 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
3904 /// support the operation, but do support the resultant packed vector type.
3905 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
3907 // If the only non-undef value is the low element, turn this into a
3908 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
3909 unsigned NumElems = Node->getNumOperands();
3910 bool isOnlyLowElement = true;
3911 SDOperand SplatValue = Node->getOperand(0);
3912 std::map<SDOperand, std::vector<unsigned> > Values;
3913 Values[SplatValue].push_back(0);
3914 bool isConstant = true;
3915 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
3916 SplatValue.getOpcode() != ISD::UNDEF)
3919 for (unsigned i = 1; i < NumElems; ++i) {
3920 SDOperand V = Node->getOperand(i);
3921 Values[V].push_back(i);
3922 if (V.getOpcode() != ISD::UNDEF)
3923 isOnlyLowElement = false;
3924 if (SplatValue != V)
3925 SplatValue = SDOperand(0,0);
3927 // If this isn't a constant element or an undef, we can't use a constant
3929 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
3930 V.getOpcode() != ISD::UNDEF)
3934 if (isOnlyLowElement) {
3935 // If the low element is an undef too, then this whole things is an undef.
3936 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
3937 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
3938 // Otherwise, turn this into a scalar_to_vector node.
3939 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
3940 Node->getOperand(0));
3943 // If all elements are constants, create a load from the constant pool.
3945 MVT::ValueType VT = Node->getValueType(0);
3947 MVT::getTypeForValueType(Node->getOperand(0).getValueType());
3948 std::vector<Constant*> CV;
3949 for (unsigned i = 0, e = NumElems; i != e; ++i) {
3950 if (ConstantFPSDNode *V =
3951 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
3952 CV.push_back(ConstantFP::get(OpNTy, V->getValue()));
3953 } else if (ConstantSDNode *V =
3954 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
3955 CV.push_back(ConstantInt::get(OpNTy, V->getValue()));
3957 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
3958 CV.push_back(UndefValue::get(OpNTy));
3961 Constant *CP = ConstantVector::get(CV);
3962 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
3963 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
3966 if (SplatValue.Val) { // Splat of one value?
3967 // Build the shuffle constant vector: <0, 0, 0, 0>
3968 MVT::ValueType MaskVT =
3969 MVT::getIntVectorWithNumElements(NumElems);
3970 SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT));
3971 std::vector<SDOperand> ZeroVec(NumElems, Zero);
3972 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3973 &ZeroVec[0], ZeroVec.size());
3975 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
3976 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
3977 // Get the splatted value into the low element of a vector register.
3978 SDOperand LowValVec =
3979 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
3981 // Return shuffle(LowValVec, undef, <0,0,0,0>)
3982 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
3983 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
3988 // If there are only two unique elements, we may be able to turn this into a
3990 if (Values.size() == 2) {
3991 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
3992 MVT::ValueType MaskVT =
3993 MVT::getIntVectorWithNumElements(NumElems);
3994 std::vector<SDOperand> MaskVec(NumElems);
3996 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
3997 E = Values.end(); I != E; ++I) {
3998 for (std::vector<unsigned>::iterator II = I->second.begin(),
3999 EE = I->second.end(); II != EE; ++II)
4000 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorElementType(MaskVT));
4003 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4004 &MaskVec[0], MaskVec.size());
4006 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4007 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
4008 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
4009 SmallVector<SDOperand, 8> Ops;
4010 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
4011 E = Values.end(); I != E; ++I) {
4012 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4016 Ops.push_back(ShuffleMask);
4018 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
4019 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0),
4020 &Ops[0], Ops.size());
4024 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
4025 // aligned object on the stack, store each element into it, then load
4026 // the result as a vector.
4027 MVT::ValueType VT = Node->getValueType(0);
4028 // Create the stack frame object.
4029 SDOperand FIPtr = CreateStackTemporary(VT);
4031 // Emit a store of each element to the stack slot.
4032 SmallVector<SDOperand, 8> Stores;
4033 unsigned TypeByteSize =
4034 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
4035 // Store (in the right endianness) the elements to memory.
4036 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
4037 // Ignore undef elements.
4038 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
4040 unsigned Offset = TypeByteSize*i;
4042 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
4043 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
4045 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
4049 SDOperand StoreChain;
4050 if (!Stores.empty()) // Not all undef elements?
4051 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4052 &Stores[0], Stores.size());
4054 StoreChain = DAG.getEntryNode();
4056 // Result is a load from the stack slot.
4057 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
4060 /// CreateStackTemporary - Create a stack temporary, suitable for holding the
4061 /// specified value type.
4062 SDOperand SelectionDAGLegalize::CreateStackTemporary(MVT::ValueType VT) {
4063 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
4064 unsigned ByteSize = MVT::getSizeInBits(VT)/8;
4065 const Type *Ty = MVT::getTypeForValueType(VT);
4066 unsigned StackAlign = (unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty);
4067 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign);
4068 return DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
4071 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
4072 SDOperand Op, SDOperand Amt,
4073 SDOperand &Lo, SDOperand &Hi) {
4074 // Expand the subcomponents.
4075 SDOperand LHSL, LHSH;
4076 ExpandOp(Op, LHSL, LHSH);
4078 SDOperand Ops[] = { LHSL, LHSH, Amt };
4079 MVT::ValueType VT = LHSL.getValueType();
4080 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
4081 Hi = Lo.getValue(1);
4085 /// ExpandShift - Try to find a clever way to expand this shift operation out to
4086 /// smaller elements. If we can't find a way that is more efficient than a
4087 /// libcall on this target, return false. Otherwise, return true with the
4088 /// low-parts expanded into Lo and Hi.
4089 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
4090 SDOperand &Lo, SDOperand &Hi) {
4091 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
4092 "This is not a shift!");
4094 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
4095 SDOperand ShAmt = LegalizeOp(Amt);
4096 MVT::ValueType ShTy = ShAmt.getValueType();
4097 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
4098 unsigned NVTBits = MVT::getSizeInBits(NVT);
4100 // Handle the case when Amt is an immediate. Other cases are currently broken
4101 // and are disabled.
4102 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
4103 unsigned Cst = CN->getValue();
4104 // Expand the incoming operand to be shifted, so that we have its parts
4106 ExpandOp(Op, InL, InH);
4110 Lo = DAG.getConstant(0, NVT);
4111 Hi = DAG.getConstant(0, NVT);
4112 } else if (Cst > NVTBits) {
4113 Lo = DAG.getConstant(0, NVT);
4114 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
4115 } else if (Cst == NVTBits) {
4116 Lo = DAG.getConstant(0, NVT);
4119 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
4120 Hi = DAG.getNode(ISD::OR, NVT,
4121 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
4122 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
4127 Lo = DAG.getConstant(0, NVT);
4128 Hi = DAG.getConstant(0, NVT);
4129 } else if (Cst > NVTBits) {
4130 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
4131 Hi = DAG.getConstant(0, NVT);
4132 } else if (Cst == NVTBits) {
4134 Hi = DAG.getConstant(0, NVT);
4136 Lo = DAG.getNode(ISD::OR, NVT,
4137 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
4138 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
4139 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
4144 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
4145 DAG.getConstant(NVTBits-1, ShTy));
4146 } else if (Cst > NVTBits) {
4147 Lo = DAG.getNode(ISD::SRA, NVT, InH,
4148 DAG.getConstant(Cst-NVTBits, ShTy));
4149 Hi = DAG.getNode(ISD::SRA, NVT, InH,
4150 DAG.getConstant(NVTBits-1, ShTy));
4151 } else if (Cst == NVTBits) {
4153 Hi = DAG.getNode(ISD::SRA, NVT, InH,
4154 DAG.getConstant(NVTBits-1, ShTy));
4156 Lo = DAG.getNode(ISD::OR, NVT,
4157 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
4158 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
4159 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
4165 // Okay, the shift amount isn't constant. However, if we can tell that it is
4166 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
4167 uint64_t Mask = NVTBits, KnownZero, KnownOne;
4168 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
4170 // If we know that the high bit of the shift amount is one, then we can do
4171 // this as a couple of simple shifts.
4172 if (KnownOne & Mask) {
4173 // Mask out the high bit, which we know is set.
4174 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
4175 DAG.getConstant(NVTBits-1, Amt.getValueType()));
4177 // Expand the incoming operand to be shifted, so that we have its parts
4179 ExpandOp(Op, InL, InH);
4182 Lo = DAG.getConstant(0, NVT); // Low part is zero.
4183 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
4186 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
4187 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
4190 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
4191 DAG.getConstant(NVTBits-1, Amt.getValueType()));
4192 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
4197 // If we know that the high bit of the shift amount is zero, then we can do
4198 // this as a couple of simple shifts.
4199 if (KnownZero & Mask) {
4201 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
4202 DAG.getConstant(NVTBits, Amt.getValueType()),
4205 // Expand the incoming operand to be shifted, so that we have its parts
4207 ExpandOp(Op, InL, InH);
4210 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
4211 Hi = DAG.getNode(ISD::OR, NVT,
4212 DAG.getNode(ISD::SHL, NVT, InH, Amt),
4213 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
4216 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
4217 Lo = DAG.getNode(ISD::OR, NVT,
4218 DAG.getNode(ISD::SRL, NVT, InL, Amt),
4219 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
4222 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
4223 Lo = DAG.getNode(ISD::OR, NVT,
4224 DAG.getNode(ISD::SRL, NVT, InL, Amt),
4225 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
4234 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
4235 // does not fit into a register, return the lo part and set the hi part to the
4236 // by-reg argument. If it does fit into a single register, return the result
4237 // and leave the Hi part unset.
4238 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
4239 bool isSigned, SDOperand &Hi) {
4240 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
4241 // The input chain to this libcall is the entry node of the function.
4242 // Legalizing the call will automatically add the previous call to the
4244 SDOperand InChain = DAG.getEntryNode();
4246 TargetLowering::ArgListTy Args;
4247 TargetLowering::ArgListEntry Entry;
4248 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
4249 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
4250 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
4251 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
4252 Entry.isSExt = isSigned;
4253 Args.push_back(Entry);
4255 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
4257 // Splice the libcall in wherever FindInputOutputChains tells us to.
4258 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
4259 std::pair<SDOperand,SDOperand> CallInfo =
4260 TLI.LowerCallTo(InChain, RetTy, isSigned, false, CallingConv::C, false,
4263 // Legalize the call sequence, starting with the chain. This will advance
4264 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
4265 // was added by LowerCallTo (guaranteeing proper serialization of calls).
4266 LegalizeOp(CallInfo.second);
4268 switch (getTypeAction(CallInfo.first.getValueType())) {
4269 default: assert(0 && "Unknown thing");
4271 Result = CallInfo.first;
4274 ExpandOp(CallInfo.first, Result, Hi);
4281 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
4283 SDOperand SelectionDAGLegalize::
4284 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
4285 assert(getTypeAction(Source.getValueType()) == Expand &&
4286 "This is not an expansion!");
4287 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
4290 assert(Source.getValueType() == MVT::i64 &&
4291 "This only works for 64-bit -> FP");
4292 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
4293 // incoming integer is set. To handle this, we dynamically test to see if
4294 // it is set, and, if so, add a fudge factor.
4296 ExpandOp(Source, Lo, Hi);
4298 // If this is unsigned, and not supported, first perform the conversion to
4299 // signed, then adjust the result if the sign bit is set.
4300 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
4301 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
4303 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
4304 DAG.getConstant(0, Hi.getValueType()),
4306 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
4307 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
4308 SignSet, Four, Zero);
4309 uint64_t FF = 0x5f800000ULL;
4310 if (TLI.isLittleEndian()) FF <<= 32;
4311 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
4313 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
4314 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
4315 SDOperand FudgeInReg;
4316 if (DestTy == MVT::f32)
4317 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
4319 assert(DestTy == MVT::f64 && "Unexpected conversion");
4320 // FIXME: Avoid the extend by construction the right constantpool?
4321 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
4322 CPIdx, NULL, 0, MVT::f32);
4324 MVT::ValueType SCVT = SignedConv.getValueType();
4325 if (SCVT != DestTy) {
4326 // Destination type needs to be expanded as well. The FADD now we are
4327 // constructing will be expanded into a libcall.
4328 if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) {
4329 assert(SCVT == MVT::i32 && DestTy == MVT::f64);
4330 SignedConv = DAG.getNode(ISD::BUILD_PAIR, MVT::i64,
4331 SignedConv, SignedConv.getValue(1));
4333 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
4335 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
4338 // Check to see if the target has a custom way to lower this. If so, use it.
4339 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
4340 default: assert(0 && "This action not implemented for this operation!");
4341 case TargetLowering::Legal:
4342 case TargetLowering::Expand:
4343 break; // This case is handled below.
4344 case TargetLowering::Custom: {
4345 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
4348 return LegalizeOp(NV);
4349 break; // The target decided this was legal after all
4353 // Expand the source, then glue it back together for the call. We must expand
4354 // the source in case it is shared (this pass of legalize must traverse it).
4355 SDOperand SrcLo, SrcHi;
4356 ExpandOp(Source, SrcLo, SrcHi);
4357 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
4360 if (DestTy == MVT::f32)
4361 LC = RTLIB::SINTTOFP_I64_F32;
4363 assert(DestTy == MVT::f64 && "Unknown fp value type!");
4364 LC = RTLIB::SINTTOFP_I64_F64;
4367 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!");
4368 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
4369 SDOperand UnusedHiPart;
4370 return ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned,
4374 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
4375 /// INT_TO_FP operation of the specified operand when the target requests that
4376 /// we expand it. At this point, we know that the result and operand types are
4377 /// legal for the target.
4378 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
4380 MVT::ValueType DestVT) {
4381 if (Op0.getValueType() == MVT::i32) {
4382 // simple 32-bit [signed|unsigned] integer to float/double expansion
4384 // get the stack frame index of a 8 byte buffer, pessimistically aligned
4385 MachineFunction &MF = DAG.getMachineFunction();
4386 const Type *F64Type = MVT::getTypeForValueType(MVT::f64);
4387 unsigned StackAlign =
4388 (unsigned)TLI.getTargetData()->getPrefTypeAlignment(F64Type);
4389 int SSFI = MF.getFrameInfo()->CreateStackObject(8, StackAlign);
4390 // get address of 8 byte buffer
4391 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
4392 // word offset constant for Hi/Lo address computation
4393 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
4394 // set up Hi and Lo (into buffer) address based on endian
4395 SDOperand Hi = StackSlot;
4396 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
4397 if (TLI.isLittleEndian())
4400 // if signed map to unsigned space
4401 SDOperand Op0Mapped;
4403 // constant used to invert sign bit (signed to unsigned mapping)
4404 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
4405 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
4409 // store the lo of the constructed double - based on integer input
4410 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(),
4411 Op0Mapped, Lo, NULL, 0);
4412 // initial hi portion of constructed double
4413 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
4414 // store the hi of the constructed double - biased exponent
4415 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
4416 // load the constructed double
4417 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
4418 // FP constant to bias correct the final result
4419 SDOperand Bias = DAG.getConstantFP(isSigned ?
4420 BitsToDouble(0x4330000080000000ULL)
4421 : BitsToDouble(0x4330000000000000ULL),
4423 // subtract the bias
4424 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
4427 // handle final rounding
4428 if (DestVT == MVT::f64) {
4432 // if f32 then cast to f32
4433 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub);
4437 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
4438 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
4440 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
4441 DAG.getConstant(0, Op0.getValueType()),
4443 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
4444 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
4445 SignSet, Four, Zero);
4447 // If the sign bit of the integer is set, the large number will be treated
4448 // as a negative number. To counteract this, the dynamic code adds an
4449 // offset depending on the data type.
4451 switch (Op0.getValueType()) {
4452 default: assert(0 && "Unsupported integer type!");
4453 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
4454 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
4455 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
4456 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
4458 if (TLI.isLittleEndian()) FF <<= 32;
4459 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
4461 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
4462 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
4463 SDOperand FudgeInReg;
4464 if (DestVT == MVT::f32)
4465 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
4467 assert(DestVT == MVT::f64 && "Unexpected conversion");
4468 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64,
4469 DAG.getEntryNode(), CPIdx,
4470 NULL, 0, MVT::f32));
4473 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
4476 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
4477 /// *INT_TO_FP operation of the specified operand when the target requests that
4478 /// we promote it. At this point, we know that the result and operand types are
4479 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
4480 /// operation that takes a larger input.
4481 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
4482 MVT::ValueType DestVT,
4484 // First step, figure out the appropriate *INT_TO_FP operation to use.
4485 MVT::ValueType NewInTy = LegalOp.getValueType();
4487 unsigned OpToUse = 0;
4489 // Scan for the appropriate larger type to use.
4491 NewInTy = (MVT::ValueType)(NewInTy+1);
4492 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
4494 // If the target supports SINT_TO_FP of this type, use it.
4495 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
4497 case TargetLowering::Legal:
4498 if (!TLI.isTypeLegal(NewInTy))
4499 break; // Can't use this datatype.
4501 case TargetLowering::Custom:
4502 OpToUse = ISD::SINT_TO_FP;
4506 if (isSigned) continue;
4508 // If the target supports UINT_TO_FP of this type, use it.
4509 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
4511 case TargetLowering::Legal:
4512 if (!TLI.isTypeLegal(NewInTy))
4513 break; // Can't use this datatype.
4515 case TargetLowering::Custom:
4516 OpToUse = ISD::UINT_TO_FP;
4521 // Otherwise, try a larger type.
4524 // Okay, we found the operation and type to use. Zero extend our input to the
4525 // desired type then run the operation on it.
4526 return DAG.getNode(OpToUse, DestVT,
4527 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
4531 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
4532 /// FP_TO_*INT operation of the specified operand when the target requests that
4533 /// we promote it. At this point, we know that the result and operand types are
4534 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
4535 /// operation that returns a larger result.
4536 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
4537 MVT::ValueType DestVT,
4539 // First step, figure out the appropriate FP_TO*INT operation to use.
4540 MVT::ValueType NewOutTy = DestVT;
4542 unsigned OpToUse = 0;
4544 // Scan for the appropriate larger type to use.
4546 NewOutTy = (MVT::ValueType)(NewOutTy+1);
4547 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
4549 // If the target supports FP_TO_SINT returning this type, use it.
4550 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
4552 case TargetLowering::Legal:
4553 if (!TLI.isTypeLegal(NewOutTy))
4554 break; // Can't use this datatype.
4556 case TargetLowering::Custom:
4557 OpToUse = ISD::FP_TO_SINT;
4562 // If the target supports FP_TO_UINT of this type, use it.
4563 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
4565 case TargetLowering::Legal:
4566 if (!TLI.isTypeLegal(NewOutTy))
4567 break; // Can't use this datatype.
4569 case TargetLowering::Custom:
4570 OpToUse = ISD::FP_TO_UINT;
4575 // Otherwise, try a larger type.
4578 // Okay, we found the operation and type to use. Truncate the result of the
4579 // extended FP_TO_*INT operation to the desired size.
4580 return DAG.getNode(ISD::TRUNCATE, DestVT,
4581 DAG.getNode(OpToUse, NewOutTy, LegalOp));
4584 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
4586 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
4587 MVT::ValueType VT = Op.getValueType();
4588 MVT::ValueType SHVT = TLI.getShiftAmountTy();
4589 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
4591 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
4593 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4594 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4595 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
4597 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4598 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4599 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4600 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4601 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
4602 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
4603 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4604 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4605 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4607 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
4608 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
4609 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4610 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4611 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4612 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4613 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
4614 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
4615 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
4616 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
4617 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
4618 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
4619 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
4620 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
4621 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
4622 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
4623 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4624 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4625 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
4626 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4627 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
4631 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
4633 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
4635 default: assert(0 && "Cannot expand this yet!");
4637 static const uint64_t mask[6] = {
4638 0x5555555555555555ULL, 0x3333333333333333ULL,
4639 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
4640 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
4642 MVT::ValueType VT = Op.getValueType();
4643 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4644 unsigned len = MVT::getSizeInBits(VT);
4645 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4646 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
4647 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
4648 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4649 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
4650 DAG.getNode(ISD::AND, VT,
4651 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
4656 // for now, we do this:
4657 // x = x | (x >> 1);
4658 // x = x | (x >> 2);
4660 // x = x | (x >>16);
4661 // x = x | (x >>32); // for 64-bit input
4662 // return popcount(~x);
4664 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
4665 MVT::ValueType VT = Op.getValueType();
4666 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4667 unsigned len = MVT::getSizeInBits(VT);
4668 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4669 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4670 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
4672 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
4673 return DAG.getNode(ISD::CTPOP, VT, Op);
4676 // for now, we use: { return popcount(~x & (x - 1)); }
4677 // unless the target has ctlz but not ctpop, in which case we use:
4678 // { return 32 - nlz(~x & (x-1)); }
4679 // see also http://www.hackersdelight.org/HDcode/ntz.cc
4680 MVT::ValueType VT = Op.getValueType();
4681 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
4682 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
4683 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
4684 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
4685 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
4686 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
4687 TLI.isOperationLegal(ISD::CTLZ, VT))
4688 return DAG.getNode(ISD::SUB, VT,
4689 DAG.getConstant(MVT::getSizeInBits(VT), VT),
4690 DAG.getNode(ISD::CTLZ, VT, Tmp3));
4691 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
4696 /// ExpandOp - Expand the specified SDOperand into its two component pieces
4697 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
4698 /// LegalizeNodes map is filled in for any results that are not expanded, the
4699 /// ExpandedNodes map is filled in for any results that are expanded, and the
4700 /// Lo/Hi values are returned.
4701 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
4702 MVT::ValueType VT = Op.getValueType();
4703 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4704 SDNode *Node = Op.Val;
4705 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
4706 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) ||
4707 MVT::isVector(VT)) &&
4708 "Cannot expand to FP value or to larger int value!");
4710 // See if we already expanded it.
4711 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
4712 = ExpandedNodes.find(Op);
4713 if (I != ExpandedNodes.end()) {
4714 Lo = I->second.first;
4715 Hi = I->second.second;
4719 switch (Node->getOpcode()) {
4720 case ISD::CopyFromReg:
4721 assert(0 && "CopyFromReg must be legal!");
4724 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
4726 assert(0 && "Do not know how to expand this operator!");
4729 NVT = TLI.getTypeToExpandTo(VT);
4730 Lo = DAG.getNode(ISD::UNDEF, NVT);
4731 Hi = DAG.getNode(ISD::UNDEF, NVT);
4733 case ISD::Constant: {
4734 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
4735 Lo = DAG.getConstant(Cst, NVT);
4736 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
4739 case ISD::ConstantFP: {
4740 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
4741 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
4742 if (getTypeAction(Lo.getValueType()) == Expand)
4743 ExpandOp(Lo, Lo, Hi);
4746 case ISD::BUILD_PAIR:
4747 // Return the operands.
4748 Lo = Node->getOperand(0);
4749 Hi = Node->getOperand(1);
4752 case ISD::SIGN_EXTEND_INREG:
4753 ExpandOp(Node->getOperand(0), Lo, Hi);
4754 // sext_inreg the low part if needed.
4755 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
4757 // The high part gets the sign extension from the lo-part. This handles
4758 // things like sextinreg V:i64 from i8.
4759 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4760 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
4761 TLI.getShiftAmountTy()));
4765 ExpandOp(Node->getOperand(0), Lo, Hi);
4766 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
4767 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
4773 ExpandOp(Node->getOperand(0), Lo, Hi);
4774 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
4775 DAG.getNode(ISD::CTPOP, NVT, Lo),
4776 DAG.getNode(ISD::CTPOP, NVT, Hi));
4777 Hi = DAG.getConstant(0, NVT);
4781 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
4782 ExpandOp(Node->getOperand(0), Lo, Hi);
4783 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
4784 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
4785 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
4787 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
4788 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
4790 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
4791 Hi = DAG.getConstant(0, NVT);
4796 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
4797 ExpandOp(Node->getOperand(0), Lo, Hi);
4798 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
4799 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
4800 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
4802 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
4803 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
4805 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
4806 Hi = DAG.getConstant(0, NVT);
4811 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
4812 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
4813 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
4814 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
4816 // Remember that we legalized the chain.
4817 Hi = LegalizeOp(Hi);
4818 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
4819 if (!TLI.isLittleEndian())
4825 LoadSDNode *LD = cast<LoadSDNode>(Node);
4826 SDOperand Ch = LD->getChain(); // Legalize the chain.
4827 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer.
4828 ISD::LoadExtType ExtType = LD->getExtensionType();
4829 unsigned SVOffset = LD->getSrcValueOffset();
4831 if (ExtType == ISD::NON_EXTLOAD) {
4832 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset);
4833 if (VT == MVT::f32 || VT == MVT::f64) {
4834 // f32->i32 or f64->i64 one to one expansion.
4835 // Remember that we legalized the chain.
4836 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
4837 // Recursively expand the new load.
4838 if (getTypeAction(NVT) == Expand)
4839 ExpandOp(Lo, Lo, Hi);
4843 // Increment the pointer to the other half.
4844 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
4845 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
4846 getIntPtrConstant(IncrementSize));
4847 SVOffset += IncrementSize;
4848 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset);
4850 // Build a factor node to remember that this load is independent of the
4852 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
4855 // Remember that we legalized the chain.
4856 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
4857 if (!TLI.isLittleEndian())
4860 MVT::ValueType EVT = LD->getLoadedVT();
4862 if (VT == MVT::f64 && EVT == MVT::f32) {
4863 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
4864 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(),
4866 // Remember that we legalized the chain.
4867 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1)));
4868 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
4873 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),
4876 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(),
4879 // Remember that we legalized the chain.
4880 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
4882 if (ExtType == ISD::SEXTLOAD) {
4883 // The high part is obtained by SRA'ing all but one of the bits of the
4885 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
4886 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4887 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
4888 } else if (ExtType == ISD::ZEXTLOAD) {
4889 // The high part is just a zero.
4890 Hi = DAG.getConstant(0, NVT);
4891 } else /* if (ExtType == ISD::EXTLOAD) */ {
4892 // The high part is undefined.
4893 Hi = DAG.getNode(ISD::UNDEF, NVT);
4900 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
4901 SDOperand LL, LH, RL, RH;
4902 ExpandOp(Node->getOperand(0), LL, LH);
4903 ExpandOp(Node->getOperand(1), RL, RH);
4904 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
4905 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
4909 SDOperand LL, LH, RL, RH;
4910 ExpandOp(Node->getOperand(1), LL, LH);
4911 ExpandOp(Node->getOperand(2), RL, RH);
4912 if (getTypeAction(NVT) == Expand)
4913 NVT = TLI.getTypeToExpandTo(NVT);
4914 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
4916 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
4919 case ISD::SELECT_CC: {
4920 SDOperand TL, TH, FL, FH;
4921 ExpandOp(Node->getOperand(2), TL, TH);
4922 ExpandOp(Node->getOperand(3), FL, FH);
4923 if (getTypeAction(NVT) == Expand)
4924 NVT = TLI.getTypeToExpandTo(NVT);
4925 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4926 Node->getOperand(1), TL, FL, Node->getOperand(4));
4928 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4929 Node->getOperand(1), TH, FH, Node->getOperand(4));
4932 case ISD::ANY_EXTEND:
4933 // The low part is any extension of the input (which degenerates to a copy).
4934 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
4935 // The high part is undefined.
4936 Hi = DAG.getNode(ISD::UNDEF, NVT);
4938 case ISD::SIGN_EXTEND: {
4939 // The low part is just a sign extension of the input (which degenerates to
4941 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
4943 // The high part is obtained by SRA'ing all but one of the bits of the lo
4945 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
4946 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4947 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
4950 case ISD::ZERO_EXTEND:
4951 // The low part is just a zero extension of the input (which degenerates to
4953 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4955 // The high part is just a zero.
4956 Hi = DAG.getConstant(0, NVT);
4959 case ISD::TRUNCATE: {
4960 // The input value must be larger than this value. Expand *it*.
4962 ExpandOp(Node->getOperand(0), NewLo, Hi);
4964 // The low part is now either the right size, or it is closer. If not the
4965 // right size, make an illegal truncate so we recursively expand it.
4966 if (NewLo.getValueType() != Node->getValueType(0))
4967 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
4968 ExpandOp(NewLo, Lo, Hi);
4972 case ISD::BIT_CONVERT: {
4974 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
4975 // If the target wants to, allow it to lower this itself.
4976 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4977 case Expand: assert(0 && "cannot expand FP!");
4978 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
4979 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
4981 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
4984 // f32 / f64 must be expanded to i32 / i64.
4985 if (VT == MVT::f32 || VT == MVT::f64) {
4986 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
4987 if (getTypeAction(NVT) == Expand)
4988 ExpandOp(Lo, Lo, Hi);
4992 // If source operand will be expanded to the same type as VT, i.e.
4993 // i64 <- f64, i32 <- f32, expand the source operand instead.
4994 MVT::ValueType VT0 = Node->getOperand(0).getValueType();
4995 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
4996 ExpandOp(Node->getOperand(0), Lo, Hi);
5000 // Turn this into a load/store pair by default.
5002 Tmp = ExpandBIT_CONVERT(VT, Node->getOperand(0));
5004 ExpandOp(Tmp, Lo, Hi);
5008 case ISD::READCYCLECOUNTER:
5009 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
5010 TargetLowering::Custom &&
5011 "Must custom expand ReadCycleCounter");
5012 Lo = TLI.LowerOperation(Op, DAG);
5013 assert(Lo.Val && "Node must be custom expanded!");
5014 Hi = Lo.getValue(1);
5015 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
5016 LegalizeOp(Lo.getValue(2)));
5019 // These operators cannot be expanded directly, emit them as calls to
5020 // library functions.
5021 case ISD::FP_TO_SINT: {
5022 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
5024 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5025 case Expand: assert(0 && "cannot expand FP!");
5026 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
5027 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
5030 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
5032 // Now that the custom expander is done, expand the result, which is still
5035 ExpandOp(Op, Lo, Hi);
5041 if (Node->getOperand(0).getValueType() == MVT::f32)
5042 LC = RTLIB::FPTOSINT_F32_I64;
5044 LC = RTLIB::FPTOSINT_F64_I64;
5045 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
5046 false/*sign irrelevant*/, Hi);
5050 case ISD::FP_TO_UINT: {
5051 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
5053 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5054 case Expand: assert(0 && "cannot expand FP!");
5055 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
5056 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
5059 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
5061 // Now that the custom expander is done, expand the result.
5063 ExpandOp(Op, Lo, Hi);
5069 if (Node->getOperand(0).getValueType() == MVT::f32)
5070 LC = RTLIB::FPTOUINT_F32_I64;
5072 LC = RTLIB::FPTOUINT_F64_I64;
5073 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
5074 false/*sign irrelevant*/, Hi);
5079 // If the target wants custom lowering, do so.
5080 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5081 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
5082 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
5083 Op = TLI.LowerOperation(Op, DAG);
5085 // Now that the custom expander is done, expand the result, which is
5087 ExpandOp(Op, Lo, Hi);
5092 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
5093 // this X << 1 as X+X.
5094 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
5095 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
5096 TLI.isOperationLegal(ISD::ADDE, NVT)) {
5097 SDOperand LoOps[2], HiOps[3];
5098 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
5099 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
5100 LoOps[1] = LoOps[0];
5101 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5103 HiOps[1] = HiOps[0];
5104 HiOps[2] = Lo.getValue(1);
5105 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5110 // If we can emit an efficient shift operation, do so now.
5111 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
5114 // If this target supports SHL_PARTS, use it.
5115 TargetLowering::LegalizeAction Action =
5116 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
5117 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5118 Action == TargetLowering::Custom) {
5119 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5123 // Otherwise, emit a libcall.
5124 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SHL_I64), Node,
5125 false/*left shift=unsigned*/, Hi);
5130 // If the target wants custom lowering, do so.
5131 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5132 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
5133 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
5134 Op = TLI.LowerOperation(Op, DAG);
5136 // Now that the custom expander is done, expand the result, which is
5138 ExpandOp(Op, Lo, Hi);
5143 // If we can emit an efficient shift operation, do so now.
5144 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
5147 // If this target supports SRA_PARTS, use it.
5148 TargetLowering::LegalizeAction Action =
5149 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
5150 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5151 Action == TargetLowering::Custom) {
5152 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5156 // Otherwise, emit a libcall.
5157 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRA_I64), Node,
5158 true/*ashr is signed*/, Hi);
5163 // If the target wants custom lowering, do so.
5164 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5165 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
5166 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
5167 Op = TLI.LowerOperation(Op, DAG);
5169 // Now that the custom expander is done, expand the result, which is
5171 ExpandOp(Op, Lo, Hi);
5176 // If we can emit an efficient shift operation, do so now.
5177 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
5180 // If this target supports SRL_PARTS, use it.
5181 TargetLowering::LegalizeAction Action =
5182 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
5183 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5184 Action == TargetLowering::Custom) {
5185 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5189 // Otherwise, emit a libcall.
5190 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), Node,
5191 false/*lshr is unsigned*/, Hi);
5197 // If the target wants to custom expand this, let them.
5198 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
5199 TargetLowering::Custom) {
5200 Op = TLI.LowerOperation(Op, DAG);
5202 ExpandOp(Op, Lo, Hi);
5207 // Expand the subcomponents.
5208 SDOperand LHSL, LHSH, RHSL, RHSH;
5209 ExpandOp(Node->getOperand(0), LHSL, LHSH);
5210 ExpandOp(Node->getOperand(1), RHSL, RHSH);
5211 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
5212 SDOperand LoOps[2], HiOps[3];
5217 if (Node->getOpcode() == ISD::ADD) {
5218 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5219 HiOps[2] = Lo.getValue(1);
5220 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5222 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
5223 HiOps[2] = Lo.getValue(1);
5224 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
5231 // Expand the subcomponents.
5232 SDOperand LHSL, LHSH, RHSL, RHSH;
5233 ExpandOp(Node->getOperand(0), LHSL, LHSH);
5234 ExpandOp(Node->getOperand(1), RHSL, RHSH);
5235 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
5236 SDOperand LoOps[2] = { LHSL, RHSL };
5237 SDOperand HiOps[3] = { LHSH, RHSH };
5239 if (Node->getOpcode() == ISD::ADDC) {
5240 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5241 HiOps[2] = Lo.getValue(1);
5242 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5244 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
5245 HiOps[2] = Lo.getValue(1);
5246 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
5248 // Remember that we legalized the flag.
5249 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
5254 // Expand the subcomponents.
5255 SDOperand LHSL, LHSH, RHSL, RHSH;
5256 ExpandOp(Node->getOperand(0), LHSL, LHSH);
5257 ExpandOp(Node->getOperand(1), RHSL, RHSH);
5258 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
5259 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
5260 SDOperand HiOps[3] = { LHSH, RHSH };
5262 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
5263 HiOps[2] = Lo.getValue(1);
5264 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
5266 // Remember that we legalized the flag.
5267 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
5271 // If the target wants to custom expand this, let them.
5272 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
5273 SDOperand New = TLI.LowerOperation(Op, DAG);
5275 ExpandOp(New, Lo, Hi);
5280 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
5281 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
5282 if (HasMULHS || HasMULHU) {
5283 SDOperand LL, LH, RL, RH;
5284 ExpandOp(Node->getOperand(0), LL, LH);
5285 ExpandOp(Node->getOperand(1), RL, RH);
5286 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1;
5287 // FIXME: Move this to the dag combiner.
5288 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp
5289 // extended the sign bit of the low half through the upper half, and if so
5290 // emit a MULHS instead of the alternate sequence that is valid for any
5291 // i64 x i64 multiply.
5293 // is RH an extension of the sign bit of RL?
5294 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL &&
5295 RH.getOperand(1).getOpcode() == ISD::Constant &&
5296 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH &&
5297 // is LH an extension of the sign bit of LL?
5298 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL &&
5299 LH.getOperand(1).getOpcode() == ISD::Constant &&
5300 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) {
5302 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
5304 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
5306 } else if (HasMULHU) {
5308 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
5311 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
5312 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
5313 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
5314 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
5315 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
5320 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), Node,
5321 false/*sign irrelevant*/, Hi);
5325 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SDIV_I64), Node, true, Hi);
5328 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UDIV_I64), Node, true, Hi);
5331 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SREM_I64), Node, true, Hi);
5334 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UREM_I64), Node, true, Hi);
5338 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5339 ? RTLIB::ADD_F32 : RTLIB::ADD_F64),
5343 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5344 ? RTLIB::SUB_F32 : RTLIB::SUB_F64),
5348 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5349 ? RTLIB::MUL_F32 : RTLIB::MUL_F64),
5353 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5354 ? RTLIB::DIV_F32 : RTLIB::DIV_F64),
5357 case ISD::FP_EXTEND:
5358 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPEXT_F32_F64), Node, true,Hi);
5361 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi);
5366 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
5367 switch(Node->getOpcode()) {
5369 LC = (VT == MVT::f32) ? RTLIB::SQRT_F32 : RTLIB::SQRT_F64;
5372 LC = (VT == MVT::f32) ? RTLIB::SIN_F32 : RTLIB::SIN_F64;
5375 LC = (VT == MVT::f32) ? RTLIB::COS_F32 : RTLIB::COS_F64;
5377 default: assert(0 && "Unreachable!");
5379 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false, Hi);
5383 SDOperand Mask = (VT == MVT::f64)
5384 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
5385 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
5386 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
5387 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
5388 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
5389 if (getTypeAction(NVT) == Expand)
5390 ExpandOp(Lo, Lo, Hi);
5394 SDOperand Mask = (VT == MVT::f64)
5395 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
5396 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
5397 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
5398 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
5399 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
5400 if (getTypeAction(NVT) == Expand)
5401 ExpandOp(Lo, Lo, Hi);
5404 case ISD::FCOPYSIGN: {
5405 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
5406 if (getTypeAction(NVT) == Expand)
5407 ExpandOp(Lo, Lo, Hi);
5410 case ISD::SINT_TO_FP:
5411 case ISD::UINT_TO_FP: {
5412 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
5413 MVT::ValueType SrcVT = Node->getOperand(0).getValueType();
5415 if (Node->getOperand(0).getValueType() == MVT::i64) {
5417 LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32;
5419 LC = isSigned ? RTLIB::SINTTOFP_I64_F64 : RTLIB::UINTTOFP_I64_F64;
5422 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32;
5424 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64;
5427 // Promote the operand if needed.
5428 if (getTypeAction(SrcVT) == Promote) {
5429 SDOperand Tmp = PromoteOp(Node->getOperand(0));
5431 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
5432 DAG.getValueType(SrcVT))
5433 : DAG.getZeroExtendInReg(Tmp, SrcVT);
5434 Node = DAG.UpdateNodeOperands(Op, Tmp).Val;
5437 const char *LibCall = TLI.getLibcallName(LC);
5439 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Hi);
5441 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
5442 Node->getOperand(0));
5443 if (getTypeAction(Lo.getValueType()) == Expand)
5444 ExpandOp(Lo, Lo, Hi);
5450 // Make sure the resultant values have been legalized themselves, unless this
5451 // is a type that requires multi-step expansion.
5452 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
5453 Lo = LegalizeOp(Lo);
5455 // Don't legalize the high part if it is expanded to a single node.
5456 Hi = LegalizeOp(Hi);
5459 // Remember in a map if the values will be reused later.
5460 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi)));
5461 assert(isNew && "Value already expanded?!?");
5464 /// SplitVectorOp - Given an operand of vector type, break it down into
5465 /// two smaller values, still of vector type.
5466 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
5468 assert(MVT::isVector(Op.getValueType()) && "Cannot split non-vector type!");
5469 SDNode *Node = Op.Val;
5470 unsigned NumElements = MVT::getVectorNumElements(Node->getValueType(0));
5471 assert(NumElements > 1 && "Cannot split a single element vector!");
5472 unsigned NewNumElts = NumElements/2;
5473 MVT::ValueType NewEltVT = MVT::getVectorElementType(Node->getValueType(0));
5474 MVT::ValueType NewVT = MVT::getVectorType(NewEltVT, NewNumElts);
5476 // See if we already split it.
5477 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
5478 = SplitNodes.find(Op);
5479 if (I != SplitNodes.end()) {
5480 Lo = I->second.first;
5481 Hi = I->second.second;
5485 switch (Node->getOpcode()) {
5490 assert(0 && "Unhandled operation in SplitVectorOp!");
5491 case ISD::BUILD_PAIR:
5492 Lo = Node->getOperand(0);
5493 Hi = Node->getOperand(1);
5495 case ISD::BUILD_VECTOR: {
5496 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
5497 Node->op_begin()+NewNumElts);
5498 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT, &LoOps[0], LoOps.size());
5500 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts,
5502 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT, &HiOps[0], HiOps.size());
5505 case ISD::CONCAT_VECTORS: {
5506 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
5507 if (NewNumSubvectors == 1) {
5508 Lo = Node->getOperand(0);
5509 Hi = Node->getOperand(1);
5511 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
5512 Node->op_begin()+NewNumSubvectors);
5513 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT, &LoOps[0], LoOps.size());
5515 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors,
5517 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT, &HiOps[0], HiOps.size());
5533 SDOperand LL, LH, RL, RH;
5534 SplitVectorOp(Node->getOperand(0), LL, LH);
5535 SplitVectorOp(Node->getOperand(1), RL, RH);
5537 Lo = DAG.getNode(Node->getOpcode(), NewVT, LL, RL);
5538 Hi = DAG.getNode(Node->getOpcode(), NewVT, LH, RH);
5542 LoadSDNode *LD = cast<LoadSDNode>(Node);
5543 SDOperand Ch = LD->getChain();
5544 SDOperand Ptr = LD->getBasePtr();
5545 const Value *SV = LD->getSrcValue();
5546 int SVOffset = LD->getSrcValueOffset();
5547 unsigned Alignment = LD->getAlignment();
5548 bool isVolatile = LD->isVolatile();
5550 Lo = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
5551 unsigned IncrementSize = NewNumElts * MVT::getSizeInBits(NewEltVT)/8;
5552 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
5553 getIntPtrConstant(IncrementSize));
5554 SVOffset += IncrementSize;
5555 if (Alignment > IncrementSize)
5556 Alignment = IncrementSize;
5557 Hi = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
5559 // Build a factor node to remember that this load is independent of the
5561 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
5564 // Remember that we legalized the chain.
5565 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
5568 case ISD::BIT_CONVERT: {
5569 // We know the result is a vector. The input may be either a vector or a
5571 if (!MVT::isVector(Op.getOperand(0).getValueType())) {
5572 // Lower to a store/load. FIXME: this could be improved probably.
5573 SDOperand Ptr = CreateStackTemporary(Op.getOperand(0).getValueType());
5575 SDOperand St = DAG.getStore(DAG.getEntryNode(),
5576 Op.getOperand(0), Ptr, NULL, 0);
5577 St = DAG.getLoad(NewVT, St, Ptr, NULL, 0);
5578 SplitVectorOp(St, Lo, Hi);
5580 // If the input is a vector type, we have to either scalarize it, pack it
5581 // or convert it based on whether the input vector type is legal.
5582 SDNode *InVal = Node->getOperand(0).Val;
5583 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(0));
5585 assert(NumElems > 1);
5587 // Split the input vector.
5588 SplitVectorOp(Op.getOperand(0), Lo, Hi);
5590 // Convert each of the pieces now.
5591 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT, Lo);
5592 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT, Hi);
5599 // Remember in a map if the values will be reused later.
5601 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
5602 assert(isNew && "Value already expanded?!?");
5606 /// ScalarizeVectorOp - Given an operand of single-element vector type
5607 /// (e.g. v1f32), convert it into the equivalent operation that returns a
5608 /// scalar (e.g. f32) value.
5609 SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) {
5610 assert(MVT::isVector(Op.getValueType()) &&
5611 "Bad ScalarizeVectorOp invocation!");
5612 SDNode *Node = Op.Val;
5613 MVT::ValueType NewVT = MVT::getVectorElementType(Op.getValueType());
5614 assert(MVT::getVectorNumElements(Op.getValueType()) == 1);
5616 // See if we already scalarized it.
5617 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op);
5618 if (I != ScalarizedNodes.end()) return I->second;
5621 switch (Node->getOpcode()) {
5624 Node->dump(&DAG); cerr << "\n";
5626 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
5642 Result = DAG.getNode(Node->getOpcode(),
5644 ScalarizeVectorOp(Node->getOperand(0)),
5645 ScalarizeVectorOp(Node->getOperand(1)));
5652 Result = DAG.getNode(Node->getOpcode(),
5654 ScalarizeVectorOp(Node->getOperand(0)));
5657 LoadSDNode *LD = cast<LoadSDNode>(Node);
5658 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
5659 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
5661 const Value *SV = LD->getSrcValue();
5662 int SVOffset = LD->getSrcValueOffset();
5663 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset,
5664 LD->isVolatile(), LD->getAlignment());
5666 // Remember that we legalized the chain.
5667 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
5670 case ISD::BUILD_VECTOR:
5671 Result = Node->getOperand(0);
5673 case ISD::INSERT_VECTOR_ELT:
5674 // Returning the inserted scalar element.
5675 Result = Node->getOperand(1);
5677 case ISD::CONCAT_VECTORS:
5678 assert(Node->getOperand(0).getValueType() == NewVT &&
5679 "Concat of non-legal vectors not yet supported!");
5680 Result = Node->getOperand(0);
5682 case ISD::VECTOR_SHUFFLE: {
5683 // Figure out if the scalar is the LHS or RHS and return it.
5684 SDOperand EltNum = Node->getOperand(2).getOperand(0);
5685 if (cast<ConstantSDNode>(EltNum)->getValue())
5686 Result = ScalarizeVectorOp(Node->getOperand(1));
5688 Result = ScalarizeVectorOp(Node->getOperand(0));
5691 case ISD::EXTRACT_SUBVECTOR:
5692 Result = Node->getOperand(0);
5693 assert(Result.getValueType() == NewVT);
5695 case ISD::BIT_CONVERT:
5696 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));
5699 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
5700 ScalarizeVectorOp(Op.getOperand(1)),
5701 ScalarizeVectorOp(Op.getOperand(2)));
5705 if (TLI.isTypeLegal(NewVT))
5706 Result = LegalizeOp(Result);
5707 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
5708 assert(isNew && "Value already scalarized?");
5713 // SelectionDAG::Legalize - This is the entry point for the file.
5715 void SelectionDAG::Legalize() {
5716 if (ViewLegalizeDAGs) viewGraph();
5718 /// run - This is the main entry point to this class.
5720 SelectionDAGLegalize(*this).LegalizeDAG();