1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/ADT/SmallPtrSet.h"
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/ADT/Triple.h"
18 #include "llvm/CodeGen/Analysis.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineJumpTableInfo.h"
21 #include "llvm/DebugInfo.h"
22 #include "llvm/IR/CallingConv.h"
23 #include "llvm/IR/Constants.h"
24 #include "llvm/IR/DataLayout.h"
25 #include "llvm/IR/DerivedTypes.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/IR/LLVMContext.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/MathExtras.h"
31 #include "llvm/Support/raw_ostream.h"
32 #include "llvm/Target/TargetFrameLowering.h"
33 #include "llvm/Target/TargetLowering.h"
34 #include "llvm/Target/TargetMachine.h"
37 //===----------------------------------------------------------------------===//
38 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
39 /// hacks on it until the target machine can handle it. This involves
40 /// eliminating value sizes the machine cannot handle (promoting small sizes to
41 /// large sizes or splitting up large values into small values) as well as
42 /// eliminating operations the machine cannot handle.
44 /// This code also does a small amount of optimization and recognition of idioms
45 /// as part of its processing. For example, if a target does not support a
46 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
47 /// will attempt merge setcc and brc instructions into brcc's.
50 class SelectionDAGLegalize : public SelectionDAG::DAGUpdateListener {
51 const TargetMachine &TM;
52 const TargetLowering &TLI;
55 /// LegalizePosition - The iterator for walking through the node list.
56 SelectionDAG::allnodes_iterator LegalizePosition;
58 /// LegalizedNodes - The set of nodes which have already been legalized.
59 SmallPtrSet<SDNode *, 16> LegalizedNodes;
61 EVT getSetCCResultType(EVT VT) const {
62 return TLI.getSetCCResultType(*DAG.getContext(), VT);
65 // Libcall insertion helpers.
68 explicit SelectionDAGLegalize(SelectionDAG &DAG);
73 /// LegalizeOp - Legalizes the given operation.
74 void LegalizeOp(SDNode *Node);
76 SDValue OptimizeFloatStore(StoreSDNode *ST);
78 void LegalizeLoadOps(SDNode *Node);
79 void LegalizeStoreOps(SDNode *Node);
81 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
82 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
83 /// is necessary to spill the vector being inserted into to memory, perform
84 /// the insert there, and then read the result back.
85 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
86 SDValue Idx, SDLoc dl);
87 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
88 SDValue Idx, SDLoc dl);
90 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
91 /// performs the same shuffe in terms of order or result bytes, but on a type
92 /// whose vector element type is narrower than the original shuffle type.
93 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
94 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl,
95 SDValue N1, SDValue N2,
96 ArrayRef<int> Mask) const;
98 void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
101 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
102 SDValue ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops,
103 unsigned NumOps, bool isSigned, SDLoc dl);
105 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
106 SDNode *Node, bool isSigned);
107 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
108 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
109 RTLIB::Libcall Call_F128,
110 RTLIB::Libcall Call_PPCF128);
111 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
112 RTLIB::Libcall Call_I8,
113 RTLIB::Libcall Call_I16,
114 RTLIB::Libcall Call_I32,
115 RTLIB::Libcall Call_I64,
116 RTLIB::Libcall Call_I128);
117 void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
118 void ExpandSinCosLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
120 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, SDLoc dl);
121 SDValue ExpandBUILD_VECTOR(SDNode *Node);
122 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
123 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
124 SmallVectorImpl<SDValue> &Results);
125 SDValue ExpandFCOPYSIGN(SDNode *Node);
126 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
128 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
130 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
133 SDValue ExpandBSWAP(SDValue Op, SDLoc dl);
134 SDValue ExpandBitCount(unsigned Opc, SDValue Op, SDLoc dl);
136 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
137 SDValue ExpandInsertToVectorThroughStack(SDValue Op);
138 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
140 SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP);
142 std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node);
144 void ExpandNode(SDNode *Node);
145 void PromoteNode(SDNode *Node);
147 void ForgetNode(SDNode *N) {
148 LegalizedNodes.erase(N);
149 if (LegalizePosition == SelectionDAG::allnodes_iterator(N))
154 // DAGUpdateListener implementation.
155 virtual void NodeDeleted(SDNode *N, SDNode *E) {
158 virtual void NodeUpdated(SDNode *N) {}
160 // Node replacement helpers
161 void ReplacedNode(SDNode *N) {
162 if (N->use_empty()) {
163 DAG.RemoveDeadNode(N);
168 void ReplaceNode(SDNode *Old, SDNode *New) {
169 DAG.ReplaceAllUsesWith(Old, New);
172 void ReplaceNode(SDValue Old, SDValue New) {
173 DAG.ReplaceAllUsesWith(Old, New);
174 ReplacedNode(Old.getNode());
176 void ReplaceNode(SDNode *Old, const SDValue *New) {
177 DAG.ReplaceAllUsesWith(Old, New);
183 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
184 /// performs the same shuffe in terms of order or result bytes, but on a type
185 /// whose vector element type is narrower than the original shuffle type.
186 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
188 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl,
189 SDValue N1, SDValue N2,
190 ArrayRef<int> Mask) const {
191 unsigned NumMaskElts = VT.getVectorNumElements();
192 unsigned NumDestElts = NVT.getVectorNumElements();
193 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
195 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
197 if (NumEltsGrowth == 1)
198 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
200 SmallVector<int, 8> NewMask;
201 for (unsigned i = 0; i != NumMaskElts; ++i) {
203 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
205 NewMask.push_back(-1);
207 NewMask.push_back(Idx * NumEltsGrowth + j);
210 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
211 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
212 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
215 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
216 : SelectionDAG::DAGUpdateListener(dag),
217 TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()),
221 void SelectionDAGLegalize::LegalizeDAG() {
222 DAG.AssignTopologicalOrder();
224 // Visit all the nodes. We start in topological order, so that we see
225 // nodes with their original operands intact. Legalization can produce
226 // new nodes which may themselves need to be legalized. Iterate until all
227 // nodes have been legalized.
229 bool AnyLegalized = false;
230 for (LegalizePosition = DAG.allnodes_end();
231 LegalizePosition != DAG.allnodes_begin(); ) {
234 SDNode *N = LegalizePosition;
235 if (LegalizedNodes.insert(N)) {
245 // Remove dead nodes now.
246 DAG.RemoveDeadNodes();
249 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
250 /// a load from the constant pool.
252 SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) {
256 // If a FP immediate is precise when represented as a float and if the
257 // target can do an extending load from float to double, we put it into
258 // the constant pool as a float, even if it's is statically typed as a
259 // double. This shrinks FP constants and canonicalizes them for targets where
260 // an FP extending load is the same cost as a normal load (such as on the x87
261 // fp stack or PPC FP unit).
262 EVT VT = CFP->getValueType(0);
263 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
265 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
266 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
267 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
272 while (SVT != MVT::f32) {
273 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
274 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) &&
275 // Only do this if the target has a native EXTLOAD instruction from
277 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
278 TLI.ShouldShrinkFPConstant(OrigVT)) {
279 Type *SType = SVT.getTypeForEVT(*DAG.getContext());
280 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
286 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
287 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
290 DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT,
292 CPIdx, MachinePointerInfo::getConstantPool(),
293 VT, false, false, Alignment);
297 DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
298 MachinePointerInfo::getConstantPool(), false, false, false,
303 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
304 static void ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
305 const TargetLowering &TLI,
306 SelectionDAGLegalize *DAGLegalize) {
307 assert(ST->getAddressingMode() == ISD::UNINDEXED &&
308 "unaligned indexed stores not implemented!");
309 SDValue Chain = ST->getChain();
310 SDValue Ptr = ST->getBasePtr();
311 SDValue Val = ST->getValue();
312 EVT VT = Val.getValueType();
313 int Alignment = ST->getAlignment();
315 if (ST->getMemoryVT().isFloatingPoint() ||
316 ST->getMemoryVT().isVector()) {
317 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
318 if (TLI.isTypeLegal(intVT)) {
319 // Expand to a bitconvert of the value to the integer type of the
320 // same size, then a (misaligned) int store.
321 // FIXME: Does not handle truncating floating point stores!
322 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
323 Result = DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
324 ST->isVolatile(), ST->isNonTemporal(), Alignment);
325 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
328 // Do a (aligned) store to a stack slot, then copy from the stack slot
329 // to the final destination using (unaligned) integer loads and stores.
330 EVT StoredVT = ST->getMemoryVT();
332 TLI.getRegisterType(*DAG.getContext(),
333 EVT::getIntegerVT(*DAG.getContext(),
334 StoredVT.getSizeInBits()));
335 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
336 unsigned RegBytes = RegVT.getSizeInBits() / 8;
337 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
339 // Make sure the stack slot is also aligned for the register type.
340 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
342 // Perform the original store, only redirected to the stack slot.
343 SDValue Store = DAG.getTruncStore(Chain, dl,
344 Val, StackPtr, MachinePointerInfo(),
345 StoredVT, false, false, 0);
346 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
347 SmallVector<SDValue, 8> Stores;
350 // Do all but one copies using the full register width.
351 for (unsigned i = 1; i < NumRegs; i++) {
352 // Load one integer register's worth from the stack slot.
353 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr,
354 MachinePointerInfo(),
355 false, false, false, 0);
356 // Store it to the final location. Remember the store.
357 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
358 ST->getPointerInfo().getWithOffset(Offset),
359 ST->isVolatile(), ST->isNonTemporal(),
360 MinAlign(ST->getAlignment(), Offset)));
361 // Increment the pointers.
363 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
365 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
368 // The last store may be partial. Do a truncating store. On big-endian
369 // machines this requires an extending load from the stack slot to ensure
370 // that the bits are in the right place.
371 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
372 8 * (StoredBytes - Offset));
374 // Load from the stack slot.
375 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
376 MachinePointerInfo(),
377 MemVT, false, false, 0);
379 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
381 .getWithOffset(Offset),
382 MemVT, ST->isVolatile(),
384 MinAlign(ST->getAlignment(), Offset)));
385 // The order of the stores doesn't matter - say it with a TokenFactor.
387 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
389 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
392 assert(ST->getMemoryVT().isInteger() &&
393 !ST->getMemoryVT().isVector() &&
394 "Unaligned store of unknown type.");
395 // Get the half-size VT
396 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext());
397 int NumBits = NewStoredVT.getSizeInBits();
398 int IncrementSize = NumBits / 8;
400 // Divide the stored value in two parts.
401 SDValue ShiftAmount = DAG.getConstant(NumBits,
402 TLI.getShiftAmountTy(Val.getValueType()));
404 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
406 // Store the two parts
407 SDValue Store1, Store2;
408 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
409 ST->getPointerInfo(), NewStoredVT,
410 ST->isVolatile(), ST->isNonTemporal(), Alignment);
411 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
412 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
413 Alignment = MinAlign(Alignment, IncrementSize);
414 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
415 ST->getPointerInfo().getWithOffset(IncrementSize),
416 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(),
420 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
421 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
424 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
426 ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
427 const TargetLowering &TLI,
428 SDValue &ValResult, SDValue &ChainResult) {
429 assert(LD->getAddressingMode() == ISD::UNINDEXED &&
430 "unaligned indexed loads not implemented!");
431 SDValue Chain = LD->getChain();
432 SDValue Ptr = LD->getBasePtr();
433 EVT VT = LD->getValueType(0);
434 EVT LoadedVT = LD->getMemoryVT();
436 if (VT.isFloatingPoint() || VT.isVector()) {
437 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
438 if (TLI.isTypeLegal(intVT) && TLI.isTypeLegal(LoadedVT)) {
439 // Expand to a (misaligned) integer load of the same size,
440 // then bitconvert to floating point or vector.
441 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getPointerInfo(),
444 LD->isInvariant(), LD->getAlignment());
445 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad);
447 Result = DAG.getNode(VT.isFloatingPoint() ? ISD::FP_EXTEND :
448 ISD::ANY_EXTEND, dl, VT, Result);
455 // Copy the value to a (aligned) stack slot using (unaligned) integer
456 // loads and stores, then do a (aligned) load from the stack slot.
457 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
458 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
459 unsigned RegBytes = RegVT.getSizeInBits() / 8;
460 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
462 // Make sure the stack slot is also aligned for the register type.
463 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
465 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
466 SmallVector<SDValue, 8> Stores;
467 SDValue StackPtr = StackBase;
470 // Do all but one copies using the full register width.
471 for (unsigned i = 1; i < NumRegs; i++) {
472 // Load one integer register's worth from the original location.
473 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr,
474 LD->getPointerInfo().getWithOffset(Offset),
475 LD->isVolatile(), LD->isNonTemporal(),
477 MinAlign(LD->getAlignment(), Offset));
478 // Follow the load with a store to the stack slot. Remember the store.
479 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
480 MachinePointerInfo(), false, false, 0));
481 // Increment the pointers.
483 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
484 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
488 // The last copy may be partial. Do an extending load.
489 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
490 8 * (LoadedBytes - Offset));
491 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
492 LD->getPointerInfo().getWithOffset(Offset),
493 MemVT, LD->isVolatile(),
495 MinAlign(LD->getAlignment(), Offset));
496 // Follow the load with a store to the stack slot. Remember the store.
497 // On big-endian machines this requires a truncating store to ensure
498 // that the bits end up in the right place.
499 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
500 MachinePointerInfo(), MemVT,
503 // The order of the stores doesn't matter - say it with a TokenFactor.
504 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
507 // Finally, perform the original load only redirected to the stack slot.
508 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
509 MachinePointerInfo(), LoadedVT, false, false, 0);
511 // Callers expect a MERGE_VALUES node.
516 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
517 "Unaligned load of unsupported type.");
519 // Compute the new VT that is half the size of the old one. This is an
521 unsigned NumBits = LoadedVT.getSizeInBits();
523 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
526 unsigned Alignment = LD->getAlignment();
527 unsigned IncrementSize = NumBits / 8;
528 ISD::LoadExtType HiExtType = LD->getExtensionType();
530 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
531 if (HiExtType == ISD::NON_EXTLOAD)
532 HiExtType = ISD::ZEXTLOAD;
534 // Load the value in two parts
536 if (TLI.isLittleEndian()) {
537 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
538 NewLoadedVT, LD->isVolatile(),
539 LD->isNonTemporal(), Alignment);
540 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
541 DAG.getConstant(IncrementSize, Ptr.getValueType()));
542 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr,
543 LD->getPointerInfo().getWithOffset(IncrementSize),
544 NewLoadedVT, LD->isVolatile(),
545 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
547 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(),
548 NewLoadedVT, LD->isVolatile(),
549 LD->isNonTemporal(), Alignment);
550 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
551 DAG.getConstant(IncrementSize, Ptr.getValueType()));
552 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
553 LD->getPointerInfo().getWithOffset(IncrementSize),
554 NewLoadedVT, LD->isVolatile(),
555 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
558 // aggregate the two parts
559 SDValue ShiftAmount = DAG.getConstant(NumBits,
560 TLI.getShiftAmountTy(Hi.getValueType()));
561 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
562 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
564 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
571 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
572 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
573 /// is necessary to spill the vector being inserted into to memory, perform
574 /// the insert there, and then read the result back.
575 SDValue SelectionDAGLegalize::
576 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
582 // If the target doesn't support this, we have to spill the input vector
583 // to a temporary stack slot, update the element, then reload it. This is
584 // badness. We could also load the value into a vector register (either
585 // with a "move to register" or "extload into register" instruction, then
586 // permute it into place, if the idx is a constant and if the idx is
587 // supported by the target.
588 EVT VT = Tmp1.getValueType();
589 EVT EltVT = VT.getVectorElementType();
590 EVT IdxVT = Tmp3.getValueType();
591 EVT PtrVT = TLI.getPointerTy();
592 SDValue StackPtr = DAG.CreateStackTemporary(VT);
594 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
597 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
598 MachinePointerInfo::getFixedStack(SPFI),
601 // Truncate or zero extend offset to target pointer type.
602 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
603 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
604 // Add the offset to the index.
605 unsigned EltSize = EltVT.getSizeInBits()/8;
606 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
607 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
608 // Store the scalar value.
609 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT,
611 // Load the updated vector.
612 return DAG.getLoad(VT, dl, Ch, StackPtr,
613 MachinePointerInfo::getFixedStack(SPFI), false, false,
618 SDValue SelectionDAGLegalize::
619 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, SDLoc dl) {
620 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
621 // SCALAR_TO_VECTOR requires that the type of the value being inserted
622 // match the element type of the vector being created, except for
623 // integers in which case the inserted value can be over width.
624 EVT EltVT = Vec.getValueType().getVectorElementType();
625 if (Val.getValueType() == EltVT ||
626 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
627 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
628 Vec.getValueType(), Val);
630 unsigned NumElts = Vec.getValueType().getVectorNumElements();
631 // We generate a shuffle of InVec and ScVec, so the shuffle mask
632 // should be 0,1,2,3,4,5... with the appropriate element replaced with
634 SmallVector<int, 8> ShufOps;
635 for (unsigned i = 0; i != NumElts; ++i)
636 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
638 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
642 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
645 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
646 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
647 // FIXME: We shouldn't do this for TargetConstantFP's.
648 // FIXME: move this to the DAG Combiner! Note that we can't regress due
649 // to phase ordering between legalized code and the dag combiner. This
650 // probably means that we need to integrate dag combiner and legalizer
652 // We generally can't do this one for long doubles.
653 SDValue Chain = ST->getChain();
654 SDValue Ptr = ST->getBasePtr();
655 unsigned Alignment = ST->getAlignment();
656 bool isVolatile = ST->isVolatile();
657 bool isNonTemporal = ST->isNonTemporal();
659 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
660 if (CFP->getValueType(0) == MVT::f32 &&
661 TLI.isTypeLegal(MVT::i32)) {
662 SDValue Con = DAG.getConstant(CFP->getValueAPF().
663 bitcastToAPInt().zextOrTrunc(32),
665 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
666 isVolatile, isNonTemporal, Alignment);
669 if (CFP->getValueType(0) == MVT::f64) {
670 // If this target supports 64-bit registers, do a single 64-bit store.
671 if (TLI.isTypeLegal(MVT::i64)) {
672 SDValue Con = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
673 zextOrTrunc(64), MVT::i64);
674 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
675 isVolatile, isNonTemporal, Alignment);
678 if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) {
679 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
680 // stores. If the target supports neither 32- nor 64-bits, this
681 // xform is certainly not worth it.
682 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
683 SDValue Lo = DAG.getConstant(IntVal.trunc(32), MVT::i32);
684 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
685 if (TLI.isBigEndian()) std::swap(Lo, Hi);
687 Lo = DAG.getStore(Chain, dl, Lo, Ptr, ST->getPointerInfo(), isVolatile,
688 isNonTemporal, Alignment);
689 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
690 DAG.getConstant(4, Ptr.getValueType()));
691 Hi = DAG.getStore(Chain, dl, Hi, Ptr,
692 ST->getPointerInfo().getWithOffset(4),
693 isVolatile, isNonTemporal, MinAlign(Alignment, 4U));
695 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
699 return SDValue(0, 0);
702 void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
703 StoreSDNode *ST = cast<StoreSDNode>(Node);
704 SDValue Chain = ST->getChain();
705 SDValue Ptr = ST->getBasePtr();
708 unsigned Alignment = ST->getAlignment();
709 bool isVolatile = ST->isVolatile();
710 bool isNonTemporal = ST->isNonTemporal();
712 if (!ST->isTruncatingStore()) {
713 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
714 ReplaceNode(ST, OptStore);
719 SDValue Value = ST->getValue();
720 MVT VT = Value.getSimpleValueType();
721 switch (TLI.getOperationAction(ISD::STORE, VT)) {
722 default: llvm_unreachable("This action is not supported yet!");
723 case TargetLowering::Legal:
724 // If this is an unaligned store and the target doesn't support it,
726 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
727 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
728 unsigned ABIAlignment= TLI.getDataLayout()->getABITypeAlignment(Ty);
729 if (ST->getAlignment() < ABIAlignment)
730 ExpandUnalignedStore(cast<StoreSDNode>(Node),
734 case TargetLowering::Custom: {
735 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
737 ReplaceNode(SDValue(Node, 0), Res);
740 case TargetLowering::Promote: {
741 MVT NVT = TLI.getTypeToPromoteTo(ISD::STORE, VT);
742 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
743 "Can only promote stores to same size type");
744 Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value);
746 DAG.getStore(Chain, dl, Value, Ptr,
747 ST->getPointerInfo(), isVolatile,
748 isNonTemporal, Alignment);
749 ReplaceNode(SDValue(Node, 0), Result);
756 SDValue Value = ST->getValue();
758 EVT StVT = ST->getMemoryVT();
759 unsigned StWidth = StVT.getSizeInBits();
761 if (StWidth != StVT.getStoreSizeInBits()) {
762 // Promote to a byte-sized store with upper bits zero if not
763 // storing an integral number of bytes. For example, promote
764 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
765 EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
766 StVT.getStoreSizeInBits());
767 Value = DAG.getZeroExtendInReg(Value, dl, StVT);
769 DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
770 NVT, isVolatile, isNonTemporal, Alignment);
771 ReplaceNode(SDValue(Node, 0), Result);
772 } else if (StWidth & (StWidth - 1)) {
773 // If not storing a power-of-2 number of bits, expand as two stores.
774 assert(!StVT.isVector() && "Unsupported truncstore!");
775 unsigned RoundWidth = 1 << Log2_32(StWidth);
776 assert(RoundWidth < StWidth);
777 unsigned ExtraWidth = StWidth - RoundWidth;
778 assert(ExtraWidth < RoundWidth);
779 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
780 "Store size not an integral number of bytes!");
781 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
782 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
784 unsigned IncrementSize;
786 if (TLI.isLittleEndian()) {
787 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
788 // Store the bottom RoundWidth bits.
789 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
791 isVolatile, isNonTemporal, Alignment);
793 // Store the remaining ExtraWidth bits.
794 IncrementSize = RoundWidth / 8;
795 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
796 DAG.getConstant(IncrementSize, Ptr.getValueType()));
797 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
798 DAG.getConstant(RoundWidth,
799 TLI.getShiftAmountTy(Value.getValueType())));
800 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr,
801 ST->getPointerInfo().getWithOffset(IncrementSize),
802 ExtraVT, isVolatile, isNonTemporal,
803 MinAlign(Alignment, IncrementSize));
805 // Big endian - avoid unaligned stores.
806 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
807 // Store the top RoundWidth bits.
808 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
809 DAG.getConstant(ExtraWidth,
810 TLI.getShiftAmountTy(Value.getValueType())));
811 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, ST->getPointerInfo(),
812 RoundVT, isVolatile, isNonTemporal, Alignment);
814 // Store the remaining ExtraWidth bits.
815 IncrementSize = RoundWidth / 8;
816 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
817 DAG.getConstant(IncrementSize, Ptr.getValueType()));
818 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr,
819 ST->getPointerInfo().getWithOffset(IncrementSize),
820 ExtraVT, isVolatile, isNonTemporal,
821 MinAlign(Alignment, IncrementSize));
824 // The order of the stores doesn't matter.
825 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
826 ReplaceNode(SDValue(Node, 0), Result);
828 switch (TLI.getTruncStoreAction(ST->getValue().getSimpleValueType(),
829 StVT.getSimpleVT())) {
830 default: llvm_unreachable("This action is not supported yet!");
831 case TargetLowering::Legal:
832 // If this is an unaligned store and the target doesn't support it,
834 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
835 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
836 unsigned ABIAlignment= TLI.getDataLayout()->getABITypeAlignment(Ty);
837 if (ST->getAlignment() < ABIAlignment)
838 ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this);
841 case TargetLowering::Custom: {
842 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
844 ReplaceNode(SDValue(Node, 0), Res);
847 case TargetLowering::Expand:
848 assert(!StVT.isVector() &&
849 "Vector Stores are handled in LegalizeVectorOps");
851 // TRUNCSTORE:i16 i32 -> STORE i16
852 assert(TLI.isTypeLegal(StVT) &&
853 "Do not know how to expand this store!");
854 Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value);
856 DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
857 isVolatile, isNonTemporal, Alignment);
858 ReplaceNode(SDValue(Node, 0), Result);
865 void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
866 LoadSDNode *LD = cast<LoadSDNode>(Node);
867 SDValue Chain = LD->getChain(); // The chain.
868 SDValue Ptr = LD->getBasePtr(); // The base pointer.
869 SDValue Value; // The value returned by the load op.
872 ISD::LoadExtType ExtType = LD->getExtensionType();
873 if (ExtType == ISD::NON_EXTLOAD) {
874 MVT VT = Node->getSimpleValueType(0);
875 SDValue RVal = SDValue(Node, 0);
876 SDValue RChain = SDValue(Node, 1);
878 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
879 default: llvm_unreachable("This action is not supported yet!");
880 case TargetLowering::Legal:
881 // If this is an unaligned load and the target doesn't support it,
883 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
884 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
885 unsigned ABIAlignment =
886 TLI.getDataLayout()->getABITypeAlignment(Ty);
887 if (LD->getAlignment() < ABIAlignment){
888 ExpandUnalignedLoad(cast<LoadSDNode>(Node), DAG, TLI, RVal, RChain);
892 case TargetLowering::Custom: {
893 SDValue Res = TLI.LowerOperation(RVal, DAG);
896 RChain = Res.getValue(1);
900 case TargetLowering::Promote: {
901 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
902 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
903 "Can only promote loads to same size type");
905 SDValue Res = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getPointerInfo(),
906 LD->isVolatile(), LD->isNonTemporal(),
907 LD->isInvariant(), LD->getAlignment());
908 RVal = DAG.getNode(ISD::BITCAST, dl, VT, Res);
909 RChain = Res.getValue(1);
913 if (RChain.getNode() != Node) {
914 assert(RVal.getNode() != Node && "Load must be completely replaced");
915 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), RVal);
916 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), RChain);
922 EVT SrcVT = LD->getMemoryVT();
923 unsigned SrcWidth = SrcVT.getSizeInBits();
924 unsigned Alignment = LD->getAlignment();
925 bool isVolatile = LD->isVolatile();
926 bool isNonTemporal = LD->isNonTemporal();
928 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
929 // Some targets pretend to have an i1 loading operation, and actually
930 // load an i8. This trick is correct for ZEXTLOAD because the top 7
931 // bits are guaranteed to be zero; it helps the optimizers understand
932 // that these bits are zero. It is also useful for EXTLOAD, since it
933 // tells the optimizers that those bits are undefined. It would be
934 // nice to have an effective generic way of getting these benefits...
935 // Until such a way is found, don't insist on promoting i1 here.
937 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
938 // Promote to a byte-sized load if not loading an integral number of
939 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
940 unsigned NewWidth = SrcVT.getStoreSizeInBits();
941 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
944 // The extra bits are guaranteed to be zero, since we stored them that
945 // way. A zext load from NVT thus automatically gives zext from SrcVT.
947 ISD::LoadExtType NewExtType =
948 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
951 DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
952 Chain, Ptr, LD->getPointerInfo(),
953 NVT, isVolatile, isNonTemporal, Alignment);
955 Ch = Result.getValue(1); // The chain.
957 if (ExtType == ISD::SEXTLOAD)
958 // Having the top bits zero doesn't help when sign extending.
959 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
960 Result.getValueType(),
961 Result, DAG.getValueType(SrcVT));
962 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
963 // All the top bits are guaranteed to be zero - inform the optimizers.
964 Result = DAG.getNode(ISD::AssertZext, dl,
965 Result.getValueType(), Result,
966 DAG.getValueType(SrcVT));
970 } else if (SrcWidth & (SrcWidth - 1)) {
971 // If not loading a power-of-2 number of bits, expand as two loads.
972 assert(!SrcVT.isVector() && "Unsupported extload!");
973 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
974 assert(RoundWidth < SrcWidth);
975 unsigned ExtraWidth = SrcWidth - RoundWidth;
976 assert(ExtraWidth < RoundWidth);
977 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
978 "Load size not an integral number of bytes!");
979 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
980 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
982 unsigned IncrementSize;
984 if (TLI.isLittleEndian()) {
985 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
986 // Load the bottom RoundWidth bits.
987 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0),
989 LD->getPointerInfo(), RoundVT, isVolatile,
990 isNonTemporal, Alignment);
992 // Load the remaining ExtraWidth bits.
993 IncrementSize = RoundWidth / 8;
994 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
995 DAG.getConstant(IncrementSize, Ptr.getValueType()));
996 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
997 LD->getPointerInfo().getWithOffset(IncrementSize),
998 ExtraVT, isVolatile, isNonTemporal,
999 MinAlign(Alignment, IncrementSize));
1001 // Build a factor node to remember that this load is independent of
1003 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1006 // Move the top bits to the right place.
1007 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1008 DAG.getConstant(RoundWidth,
1009 TLI.getShiftAmountTy(Hi.getValueType())));
1011 // Join the hi and lo parts.
1012 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1014 // Big endian - avoid unaligned loads.
1015 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1016 // Load the top RoundWidth bits.
1017 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
1018 LD->getPointerInfo(), RoundVT, isVolatile,
1019 isNonTemporal, Alignment);
1021 // Load the remaining ExtraWidth bits.
1022 IncrementSize = RoundWidth / 8;
1023 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1024 DAG.getConstant(IncrementSize, Ptr.getValueType()));
1025 Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
1026 dl, Node->getValueType(0), Chain, Ptr,
1027 LD->getPointerInfo().getWithOffset(IncrementSize),
1028 ExtraVT, isVolatile, isNonTemporal,
1029 MinAlign(Alignment, IncrementSize));
1031 // Build a factor node to remember that this load is independent of
1033 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1036 // Move the top bits to the right place.
1037 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1038 DAG.getConstant(ExtraWidth,
1039 TLI.getShiftAmountTy(Hi.getValueType())));
1041 // Join the hi and lo parts.
1042 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1047 bool isCustom = false;
1048 switch (TLI.getLoadExtAction(ExtType, SrcVT.getSimpleVT())) {
1049 default: llvm_unreachable("This action is not supported yet!");
1050 case TargetLowering::Custom:
1053 case TargetLowering::Legal: {
1054 Value = SDValue(Node, 0);
1055 Chain = SDValue(Node, 1);
1058 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1059 if (Res.getNode()) {
1061 Chain = Res.getValue(1);
1064 // If this is an unaligned load and the target doesn't support it,
1066 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
1068 LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1069 unsigned ABIAlignment =
1070 TLI.getDataLayout()->getABITypeAlignment(Ty);
1071 if (LD->getAlignment() < ABIAlignment){
1072 ExpandUnalignedLoad(cast<LoadSDNode>(Node),
1073 DAG, TLI, Value, Chain);
1079 case TargetLowering::Expand:
1080 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) && TLI.isTypeLegal(SrcVT)) {
1081 SDValue Load = DAG.getLoad(SrcVT, dl, Chain, Ptr,
1082 LD->getPointerInfo(),
1083 LD->isVolatile(), LD->isNonTemporal(),
1084 LD->isInvariant(), LD->getAlignment());
1088 ExtendOp = (SrcVT.isFloatingPoint() ?
1089 ISD::FP_EXTEND : ISD::ANY_EXTEND);
1091 case ISD::SEXTLOAD: ExtendOp = ISD::SIGN_EXTEND; break;
1092 case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break;
1093 default: llvm_unreachable("Unexpected extend load type!");
1095 Value = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
1096 Chain = Load.getValue(1);
1100 assert(!SrcVT.isVector() &&
1101 "Vector Loads are handled in LegalizeVectorOps");
1103 // FIXME: This does not work for vectors on most targets. Sign- and
1104 // zero-extend operations are currently folded into extending loads,
1105 // whether they are legal or not, and then we end up here without any
1106 // support for legalizing them.
1107 assert(ExtType != ISD::EXTLOAD &&
1108 "EXTLOAD should always be supported!");
1109 // Turn the unsupported load into an EXTLOAD followed by an explicit
1110 // zero/sign extend inreg.
1111 SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
1112 Chain, Ptr, LD->getPointerInfo(), SrcVT,
1113 LD->isVolatile(), LD->isNonTemporal(),
1114 LD->getAlignment());
1116 if (ExtType == ISD::SEXTLOAD)
1117 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1118 Result.getValueType(),
1119 Result, DAG.getValueType(SrcVT));
1121 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType());
1123 Chain = Result.getValue(1);
1128 // Since loads produce two values, make sure to remember that we legalized
1130 if (Chain.getNode() != Node) {
1131 assert(Value.getNode() != Node && "Load must be completely replaced");
1132 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Value);
1133 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
1138 /// LegalizeOp - Return a legal replacement for the given operation, with
1139 /// all legal operands.
1140 void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
1141 if (Node->getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
1144 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1145 assert(TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) ==
1146 TargetLowering::TypeLegal &&
1147 "Unexpected illegal type!");
1149 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1150 assert((TLI.getTypeAction(*DAG.getContext(),
1151 Node->getOperand(i).getValueType()) ==
1152 TargetLowering::TypeLegal ||
1153 Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
1154 "Unexpected illegal type!");
1156 // Figure out the correct action; the way to query this varies by opcode
1157 TargetLowering::LegalizeAction Action = TargetLowering::Legal;
1158 bool SimpleFinishLegalizing = true;
1159 switch (Node->getOpcode()) {
1160 case ISD::INTRINSIC_W_CHAIN:
1161 case ISD::INTRINSIC_WO_CHAIN:
1162 case ISD::INTRINSIC_VOID:
1163 case ISD::STACKSAVE:
1164 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1167 Action = TLI.getOperationAction(Node->getOpcode(),
1168 Node->getValueType(0));
1169 if (Action != TargetLowering::Promote)
1170 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1172 case ISD::SINT_TO_FP:
1173 case ISD::UINT_TO_FP:
1174 case ISD::EXTRACT_VECTOR_ELT:
1175 Action = TLI.getOperationAction(Node->getOpcode(),
1176 Node->getOperand(0).getValueType());
1178 case ISD::FP_ROUND_INREG:
1179 case ISD::SIGN_EXTEND_INREG: {
1180 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
1181 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
1184 case ISD::ATOMIC_STORE: {
1185 Action = TLI.getOperationAction(Node->getOpcode(),
1186 Node->getOperand(2).getValueType());
1189 case ISD::SELECT_CC:
1192 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
1193 Node->getOpcode() == ISD::SETCC ? 2 : 1;
1194 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
1195 MVT OpVT = Node->getOperand(CompareOperand).getSimpleValueType();
1196 ISD::CondCode CCCode =
1197 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
1198 Action = TLI.getCondCodeAction(CCCode, OpVT);
1199 if (Action == TargetLowering::Legal) {
1200 if (Node->getOpcode() == ISD::SELECT_CC)
1201 Action = TLI.getOperationAction(Node->getOpcode(),
1202 Node->getValueType(0));
1204 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
1210 // FIXME: Model these properly. LOAD and STORE are complicated, and
1211 // STORE expects the unlegalized operand in some cases.
1212 SimpleFinishLegalizing = false;
1214 case ISD::CALLSEQ_START:
1215 case ISD::CALLSEQ_END:
1216 // FIXME: This shouldn't be necessary. These nodes have special properties
1217 // dealing with the recursive nature of legalization. Removing this
1218 // special case should be done as part of making LegalizeDAG non-recursive.
1219 SimpleFinishLegalizing = false;
1221 case ISD::EXTRACT_ELEMENT:
1222 case ISD::FLT_ROUNDS_:
1230 case ISD::MERGE_VALUES:
1231 case ISD::EH_RETURN:
1232 case ISD::FRAME_TO_ARGS_OFFSET:
1233 case ISD::EH_SJLJ_SETJMP:
1234 case ISD::EH_SJLJ_LONGJMP:
1235 // These operations lie about being legal: when they claim to be legal,
1236 // they should actually be expanded.
1237 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1238 if (Action == TargetLowering::Legal)
1239 Action = TargetLowering::Expand;
1241 case ISD::INIT_TRAMPOLINE:
1242 case ISD::ADJUST_TRAMPOLINE:
1243 case ISD::FRAMEADDR:
1244 case ISD::RETURNADDR:
1245 // These operations lie about being legal: when they claim to be legal,
1246 // they should actually be custom-lowered.
1247 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1248 if (Action == TargetLowering::Legal)
1249 Action = TargetLowering::Custom;
1251 case ISD::DEBUGTRAP:
1252 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1253 if (Action == TargetLowering::Expand) {
1254 // replace ISD::DEBUGTRAP with ISD::TRAP
1256 NewVal = DAG.getNode(ISD::TRAP, SDLoc(Node), Node->getVTList(),
1257 Node->getOperand(0));
1258 ReplaceNode(Node, NewVal.getNode());
1259 LegalizeOp(NewVal.getNode());
1265 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1266 Action = TargetLowering::Legal;
1268 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1273 if (SimpleFinishLegalizing) {
1274 SDNode *NewNode = Node;
1275 switch (Node->getOpcode()) {
1282 // Legalizing shifts/rotates requires adjusting the shift amount
1283 // to the appropriate width.
1284 if (!Node->getOperand(1).getValueType().isVector()) {
1286 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1287 Node->getOperand(1));
1288 HandleSDNode Handle(SAO);
1289 LegalizeOp(SAO.getNode());
1290 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1294 case ISD::SRL_PARTS:
1295 case ISD::SRA_PARTS:
1296 case ISD::SHL_PARTS:
1297 // Legalizing shifts/rotates requires adjusting the shift amount
1298 // to the appropriate width.
1299 if (!Node->getOperand(2).getValueType().isVector()) {
1301 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1302 Node->getOperand(2));
1303 HandleSDNode Handle(SAO);
1304 LegalizeOp(SAO.getNode());
1305 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1306 Node->getOperand(1),
1312 if (NewNode != Node) {
1313 DAG.ReplaceAllUsesWith(Node, NewNode);
1314 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1315 DAG.TransferDbgValues(SDValue(Node, i), SDValue(NewNode, i));
1320 case TargetLowering::Legal:
1322 case TargetLowering::Custom: {
1323 // FIXME: The handling for custom lowering with multiple results is
1325 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1326 if (Res.getNode()) {
1327 SmallVector<SDValue, 8> ResultVals;
1328 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
1330 ResultVals.push_back(Res);
1332 ResultVals.push_back(Res.getValue(i));
1334 if (Res.getNode() != Node || Res.getResNo() != 0) {
1335 DAG.ReplaceAllUsesWith(Node, ResultVals.data());
1336 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1337 DAG.TransferDbgValues(SDValue(Node, i), ResultVals[i]);
1344 case TargetLowering::Expand:
1347 case TargetLowering::Promote:
1353 switch (Node->getOpcode()) {
1360 llvm_unreachable("Do not know how to legalize this operator!");
1362 case ISD::CALLSEQ_START:
1363 case ISD::CALLSEQ_END:
1366 return LegalizeLoadOps(Node);
1369 return LegalizeStoreOps(Node);
1374 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1375 SDValue Vec = Op.getOperand(0);
1376 SDValue Idx = Op.getOperand(1);
1378 // Store the value to a temporary stack slot, then LOAD the returned part.
1379 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1380 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1381 MachinePointerInfo(), false, false, 0);
1383 // Add the offset to the index.
1385 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1386 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1387 DAG.getConstant(EltSize, Idx.getValueType()));
1389 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1390 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1392 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1394 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1396 if (Op.getValueType().isVector())
1397 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,MachinePointerInfo(),
1398 false, false, false, 0);
1399 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
1400 MachinePointerInfo(),
1401 Vec.getValueType().getVectorElementType(),
1405 SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
1406 assert(Op.getValueType().isVector() && "Non-vector insert subvector!");
1408 SDValue Vec = Op.getOperand(0);
1409 SDValue Part = Op.getOperand(1);
1410 SDValue Idx = Op.getOperand(2);
1413 // Store the value to a temporary stack slot, then LOAD the returned part.
1415 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1416 int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1417 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1419 // First store the whole vector.
1420 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo,
1423 // Then store the inserted part.
1425 // Add the offset to the index.
1427 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1429 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1430 DAG.getConstant(EltSize, Idx.getValueType()));
1432 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1433 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1435 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1437 SDValue SubStackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
1440 // Store the subvector.
1441 Ch = DAG.getStore(DAG.getEntryNode(), dl, Part, SubStackPtr,
1442 MachinePointerInfo(), false, false, 0);
1444 // Finally, load the updated vector.
1445 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo,
1446 false, false, false, 0);
1449 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1450 // We can't handle this case efficiently. Allocate a sufficiently
1451 // aligned object on the stack, store each element into it, then load
1452 // the result as a vector.
1453 // Create the stack frame object.
1454 EVT VT = Node->getValueType(0);
1455 EVT EltVT = VT.getVectorElementType();
1457 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1458 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1459 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1461 // Emit a store of each element to the stack slot.
1462 SmallVector<SDValue, 8> Stores;
1463 unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1464 // Store (in the right endianness) the elements to memory.
1465 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1466 // Ignore undef elements.
1467 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1469 unsigned Offset = TypeByteSize*i;
1471 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
1472 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1474 // If the destination vector element type is narrower than the source
1475 // element type, only store the bits necessary.
1476 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1477 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1478 Node->getOperand(i), Idx,
1479 PtrInfo.getWithOffset(Offset),
1480 EltVT, false, false, 0));
1482 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
1483 Node->getOperand(i), Idx,
1484 PtrInfo.getWithOffset(Offset),
1489 if (!Stores.empty()) // Not all undef elements?
1490 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1491 &Stores[0], Stores.size());
1493 StoreChain = DAG.getEntryNode();
1495 // Result is a load from the stack slot.
1496 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo,
1497 false, false, false, 0);
1500 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
1502 SDValue Tmp1 = Node->getOperand(0);
1503 SDValue Tmp2 = Node->getOperand(1);
1505 // Get the sign bit of the RHS. First obtain a value that has the same
1506 // sign as the sign bit, i.e. negative if and only if the sign bit is 1.
1508 EVT FloatVT = Tmp2.getValueType();
1509 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits());
1510 if (TLI.isTypeLegal(IVT)) {
1511 // Convert to an integer with the same sign bit.
1512 SignBit = DAG.getNode(ISD::BITCAST, dl, IVT, Tmp2);
1514 // Store the float to memory, then load the sign part out as an integer.
1515 MVT LoadTy = TLI.getPointerTy();
1516 // First create a temporary that is aligned for both the load and store.
1517 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1518 // Then store the float to it.
1520 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, MachinePointerInfo(),
1522 if (TLI.isBigEndian()) {
1523 assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1524 // Load out a legal integer with the same sign bit as the float.
1525 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, MachinePointerInfo(),
1526 false, false, false, 0);
1527 } else { // Little endian
1528 SDValue LoadPtr = StackPtr;
1529 // The float may be wider than the integer we are going to load. Advance
1530 // the pointer so that the loaded integer will contain the sign bit.
1531 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits();
1532 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8;
1533 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(),
1535 DAG.getConstant(ByteOffset, LoadPtr.getValueType()));
1536 // Load a legal integer containing the sign bit.
1537 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(),
1538 false, false, false, 0);
1539 // Move the sign bit to the top bit of the loaded integer.
1540 unsigned BitShift = LoadTy.getSizeInBits() -
1541 (FloatVT.getSizeInBits() - 8 * ByteOffset);
1542 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?");
1544 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit,
1545 DAG.getConstant(BitShift,
1546 TLI.getShiftAmountTy(SignBit.getValueType())));
1549 // Now get the sign bit proper, by seeing whether the value is negative.
1550 SignBit = DAG.getSetCC(dl, getSetCCResultType(SignBit.getValueType()),
1551 SignBit, DAG.getConstant(0, SignBit.getValueType()),
1553 // Get the absolute value of the result.
1554 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1555 // Select between the nabs and abs value based on the sign bit of
1557 return DAG.getSelect(dl, AbsVal.getValueType(), SignBit,
1558 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1562 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1563 SmallVectorImpl<SDValue> &Results) {
1564 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1565 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1566 " not tell us which reg is the stack pointer!");
1568 EVT VT = Node->getValueType(0);
1569 SDValue Tmp1 = SDValue(Node, 0);
1570 SDValue Tmp2 = SDValue(Node, 1);
1571 SDValue Tmp3 = Node->getOperand(2);
1572 SDValue Chain = Tmp1.getOperand(0);
1574 // Chain the dynamic stack allocation so that it doesn't modify the stack
1575 // pointer when other instructions are using the stack.
1576 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
1579 SDValue Size = Tmp2.getOperand(1);
1580 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1581 Chain = SP.getValue(1);
1582 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1583 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
1584 if (Align > StackAlign)
1585 SP = DAG.getNode(ISD::AND, dl, VT, SP,
1586 DAG.getConstant(-(uint64_t)Align, VT));
1587 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1588 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1590 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1591 DAG.getIntPtrConstant(0, true), SDValue(),
1594 Results.push_back(Tmp1);
1595 Results.push_back(Tmp2);
1598 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
1599 /// condition code CC on the current target. This routine expands SETCC with
1600 /// illegal condition code into AND / OR of multiple SETCC values.
1601 void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1602 SDValue &LHS, SDValue &RHS,
1605 MVT OpVT = LHS.getSimpleValueType();
1606 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1607 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1608 default: llvm_unreachable("Unknown condition code action!");
1609 case TargetLowering::Legal:
1612 case TargetLowering::Expand: {
1613 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1614 ISD::CondCode InvCC = ISD::SETCC_INVALID;
1617 default: llvm_unreachable("Don't know how to expand this condition!");
1619 assert(TLI.getCondCodeAction(ISD::SETOEQ, OpVT)
1620 == TargetLowering::Legal
1621 && "If SETO is expanded, SETOEQ must be legal!");
1622 CC1 = ISD::SETOEQ; CC2 = ISD::SETOEQ; Opc = ISD::AND; break;
1624 assert(TLI.getCondCodeAction(ISD::SETUNE, OpVT)
1625 == TargetLowering::Legal
1626 && "If SETUO is expanded, SETUNE must be legal!");
1627 CC1 = ISD::SETUNE; CC2 = ISD::SETUNE; Opc = ISD::OR; break;
1640 // If we are floating point, assign and break, otherwise fall through.
1641 if (!OpVT.isInteger()) {
1642 // We can use the 4th bit to tell if we are the unordered
1643 // or ordered version of the opcode.
1644 CC2 = ((unsigned)CCCode & 0x8U) ? ISD::SETUO : ISD::SETO;
1645 Opc = ((unsigned)CCCode & 0x8U) ? ISD::OR : ISD::AND;
1646 CC1 = (ISD::CondCode)(((int)CCCode & 0x7) | 0x10);
1649 // Fallthrough if we are unsigned integer.
1656 InvCC = ISD::getSetCCSwappedOperands(CCCode);
1657 if (TLI.getCondCodeAction(InvCC, OpVT) == TargetLowering::Expand) {
1658 // We only support using the inverted operation and not a
1659 // different manner of supporting expanding these cases.
1660 llvm_unreachable("Don't know how to expand this condition!");
1662 LHS = DAG.getSetCC(dl, VT, RHS, LHS, InvCC);
1668 SDValue SetCC1, SetCC2;
1669 if (CCCode != ISD::SETO && CCCode != ISD::SETUO) {
1670 // If we aren't the ordered or unorder operation,
1671 // then the pattern is (LHS CC1 RHS) Opc (LHS CC2 RHS).
1672 SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1673 SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1675 // Otherwise, the pattern is (LHS CC1 LHS) Opc (RHS CC2 RHS)
1676 SetCC1 = DAG.getSetCC(dl, VT, LHS, LHS, CC1);
1677 SetCC2 = DAG.getSetCC(dl, VT, RHS, RHS, CC2);
1679 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1687 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
1688 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1689 /// a load from the stack slot to DestVT, extending it if needed.
1690 /// The resultant code need not be legal.
1691 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
1695 // Create the stack frame object.
1697 TLI.getDataLayout()->getPrefTypeAlignment(SrcOp.getValueType().
1698 getTypeForEVT(*DAG.getContext()));
1699 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1701 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1702 int SPFI = StackPtrFI->getIndex();
1703 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(SPFI);
1705 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
1706 unsigned SlotSize = SlotVT.getSizeInBits();
1707 unsigned DestSize = DestVT.getSizeInBits();
1708 Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
1709 unsigned DestAlign = TLI.getDataLayout()->getPrefTypeAlignment(DestType);
1711 // Emit a store to the stack slot. Use a truncstore if the input value is
1712 // later than DestVT.
1715 if (SrcSize > SlotSize)
1716 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1717 PtrInfo, SlotVT, false, false, SrcAlign);
1719 assert(SrcSize == SlotSize && "Invalid store");
1720 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1721 PtrInfo, false, false, SrcAlign);
1724 // Result is a load from the stack slot.
1725 if (SlotSize == DestSize)
1726 return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo,
1727 false, false, false, DestAlign);
1729 assert(SlotSize < DestSize && "Unknown extension!");
1730 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr,
1731 PtrInfo, SlotVT, false, false, DestAlign);
1734 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1736 // Create a vector sized/aligned stack slot, store the value to element #0,
1737 // then load the whole vector back out.
1738 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1740 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1741 int SPFI = StackPtrFI->getIndex();
1743 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0),
1745 MachinePointerInfo::getFixedStack(SPFI),
1746 Node->getValueType(0).getVectorElementType(),
1748 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
1749 MachinePointerInfo::getFixedStack(SPFI),
1750 false, false, false, 0);
1754 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
1755 /// support the operation, but do support the resultant vector type.
1756 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1757 unsigned NumElems = Node->getNumOperands();
1758 SDValue Value1, Value2;
1760 EVT VT = Node->getValueType(0);
1761 EVT OpVT = Node->getOperand(0).getValueType();
1762 EVT EltVT = VT.getVectorElementType();
1764 // If the only non-undef value is the low element, turn this into a
1765 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1766 bool isOnlyLowElement = true;
1767 bool MoreThanTwoValues = false;
1768 bool isConstant = true;
1769 for (unsigned i = 0; i < NumElems; ++i) {
1770 SDValue V = Node->getOperand(i);
1771 if (V.getOpcode() == ISD::UNDEF)
1774 isOnlyLowElement = false;
1775 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1778 if (!Value1.getNode()) {
1780 } else if (!Value2.getNode()) {
1783 } else if (V != Value1 && V != Value2) {
1784 MoreThanTwoValues = true;
1788 if (!Value1.getNode())
1789 return DAG.getUNDEF(VT);
1791 if (isOnlyLowElement)
1792 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1794 // If all elements are constants, create a load from the constant pool.
1796 SmallVector<Constant*, 16> CV;
1797 for (unsigned i = 0, e = NumElems; i != e; ++i) {
1798 if (ConstantFPSDNode *V =
1799 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1800 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1801 } else if (ConstantSDNode *V =
1802 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1804 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1806 // If OpVT and EltVT don't match, EltVT is not legal and the
1807 // element values have been promoted/truncated earlier. Undo this;
1808 // we don't want a v16i8 to become a v16i32 for example.
1809 const ConstantInt *CI = V->getConstantIntValue();
1810 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
1811 CI->getZExtValue()));
1814 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
1815 Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
1816 CV.push_back(UndefValue::get(OpNTy));
1819 Constant *CP = ConstantVector::get(CV);
1820 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
1821 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
1822 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
1823 MachinePointerInfo::getConstantPool(),
1824 false, false, false, Alignment);
1827 if (!MoreThanTwoValues) {
1828 SmallVector<int, 8> ShuffleVec(NumElems, -1);
1829 for (unsigned i = 0; i < NumElems; ++i) {
1830 SDValue V = Node->getOperand(i);
1831 if (V.getOpcode() == ISD::UNDEF)
1833 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
1835 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
1836 // Get the splatted value into the low element of a vector register.
1837 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
1839 if (Value2.getNode())
1840 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
1842 Vec2 = DAG.getUNDEF(VT);
1844 // Return shuffle(LowValVec, undef, <0,0,0,0>)
1845 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
1849 // Otherwise, we can't handle this case efficiently.
1850 return ExpandVectorBuildThroughStack(Node);
1853 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
1854 // does not fit into a register, return the lo part and set the hi part to the
1855 // by-reg argument. If it does fit into a single register, return the result
1856 // and leave the Hi part unset.
1857 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
1859 TargetLowering::ArgListTy Args;
1860 TargetLowering::ArgListEntry Entry;
1861 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1862 EVT ArgVT = Node->getOperand(i).getValueType();
1863 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1864 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
1865 Entry.isSExt = isSigned;
1866 Entry.isZExt = !isSigned;
1867 Args.push_back(Entry);
1869 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1870 TLI.getPointerTy());
1872 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
1874 // By default, the input chain to this libcall is the entry node of the
1875 // function. If the libcall is going to be emitted as a tail call then
1876 // TLI.isUsedByReturnOnly will change it to the right chain if the return
1877 // node which is being folded has a non-entry input chain.
1878 SDValue InChain = DAG.getEntryNode();
1880 // isTailCall may be true since the callee does not reference caller stack
1881 // frame. Check if it's in the right position.
1882 SDValue TCChain = InChain;
1883 bool isTailCall = TLI.isInTailCallPosition(DAG, Node, TCChain);
1888 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
1889 0, TLI.getLibcallCallingConv(LC), isTailCall,
1890 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
1891 Callee, Args, DAG, SDLoc(Node));
1892 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
1895 if (!CallInfo.second.getNode())
1896 // It's a tailcall, return the chain (which is the DAG root).
1897 return DAG.getRoot();
1899 return CallInfo.first;
1902 /// ExpandLibCall - Generate a libcall taking the given operands as arguments
1903 /// and returning a result of type RetVT.
1904 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, EVT RetVT,
1905 const SDValue *Ops, unsigned NumOps,
1906 bool isSigned, SDLoc dl) {
1907 TargetLowering::ArgListTy Args;
1908 Args.reserve(NumOps);
1910 TargetLowering::ArgListEntry Entry;
1911 for (unsigned i = 0; i != NumOps; ++i) {
1912 Entry.Node = Ops[i];
1913 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
1914 Entry.isSExt = isSigned;
1915 Entry.isZExt = !isSigned;
1916 Args.push_back(Entry);
1918 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1919 TLI.getPointerTy());
1921 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
1923 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
1924 false, 0, TLI.getLibcallCallingConv(LC),
1925 /*isTailCall=*/false,
1926 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
1927 Callee, Args, DAG, dl);
1928 std::pair<SDValue,SDValue> CallInfo = TLI.LowerCallTo(CLI);
1930 return CallInfo.first;
1933 // ExpandChainLibCall - Expand a node into a call to a libcall. Similar to
1934 // ExpandLibCall except that the first operand is the in-chain.
1935 std::pair<SDValue, SDValue>
1936 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
1939 SDValue InChain = Node->getOperand(0);
1941 TargetLowering::ArgListTy Args;
1942 TargetLowering::ArgListEntry Entry;
1943 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) {
1944 EVT ArgVT = Node->getOperand(i).getValueType();
1945 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1946 Entry.Node = Node->getOperand(i);
1948 Entry.isSExt = isSigned;
1949 Entry.isZExt = !isSigned;
1950 Args.push_back(Entry);
1952 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1953 TLI.getPointerTy());
1955 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
1957 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
1958 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
1959 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
1960 Callee, Args, DAG, SDLoc(Node));
1961 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
1966 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
1967 RTLIB::Libcall Call_F32,
1968 RTLIB::Libcall Call_F64,
1969 RTLIB::Libcall Call_F80,
1970 RTLIB::Libcall Call_F128,
1971 RTLIB::Libcall Call_PPCF128) {
1973 switch (Node->getSimpleValueType(0).SimpleTy) {
1974 default: llvm_unreachable("Unexpected request for libcall!");
1975 case MVT::f32: LC = Call_F32; break;
1976 case MVT::f64: LC = Call_F64; break;
1977 case MVT::f80: LC = Call_F80; break;
1978 case MVT::f128: LC = Call_F128; break;
1979 case MVT::ppcf128: LC = Call_PPCF128; break;
1981 return ExpandLibCall(LC, Node, false);
1984 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
1985 RTLIB::Libcall Call_I8,
1986 RTLIB::Libcall Call_I16,
1987 RTLIB::Libcall Call_I32,
1988 RTLIB::Libcall Call_I64,
1989 RTLIB::Libcall Call_I128) {
1991 switch (Node->getSimpleValueType(0).SimpleTy) {
1992 default: llvm_unreachable("Unexpected request for libcall!");
1993 case MVT::i8: LC = Call_I8; break;
1994 case MVT::i16: LC = Call_I16; break;
1995 case MVT::i32: LC = Call_I32; break;
1996 case MVT::i64: LC = Call_I64; break;
1997 case MVT::i128: LC = Call_I128; break;
1999 return ExpandLibCall(LC, Node, isSigned);
2002 /// isDivRemLibcallAvailable - Return true if divmod libcall is available.
2003 static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
2004 const TargetLowering &TLI) {
2006 switch (Node->getSimpleValueType(0).SimpleTy) {
2007 default: llvm_unreachable("Unexpected request for libcall!");
2008 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2009 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2010 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2011 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2012 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2015 return TLI.getLibcallName(LC) != 0;
2018 /// useDivRem - Only issue divrem libcall if both quotient and remainder are
2020 static bool useDivRem(SDNode *Node, bool isSigned, bool isDIV) {
2021 // The other use might have been replaced with a divrem already.
2022 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2023 unsigned OtherOpcode = 0;
2025 OtherOpcode = isDIV ? ISD::SREM : ISD::SDIV;
2027 OtherOpcode = isDIV ? ISD::UREM : ISD::UDIV;
2029 SDValue Op0 = Node->getOperand(0);
2030 SDValue Op1 = Node->getOperand(1);
2031 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2032 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2036 if ((User->getOpcode() == OtherOpcode || User->getOpcode() == DivRemOpc) &&
2037 User->getOperand(0) == Op0 &&
2038 User->getOperand(1) == Op1)
2044 /// ExpandDivRemLibCall - Issue libcalls to __{u}divmod to compute div / rem
2047 SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
2048 SmallVectorImpl<SDValue> &Results) {
2049 unsigned Opcode = Node->getOpcode();
2050 bool isSigned = Opcode == ISD::SDIVREM;
2053 switch (Node->getSimpleValueType(0).SimpleTy) {
2054 default: llvm_unreachable("Unexpected request for libcall!");
2055 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2056 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2057 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2058 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2059 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2062 // The input chain to this libcall is the entry node of the function.
2063 // Legalizing the call will automatically add the previous call to the
2065 SDValue InChain = DAG.getEntryNode();
2067 EVT RetVT = Node->getValueType(0);
2068 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2070 TargetLowering::ArgListTy Args;
2071 TargetLowering::ArgListEntry Entry;
2072 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2073 EVT ArgVT = Node->getOperand(i).getValueType();
2074 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2075 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
2076 Entry.isSExt = isSigned;
2077 Entry.isZExt = !isSigned;
2078 Args.push_back(Entry);
2081 // Also pass the return address of the remainder.
2082 SDValue FIPtr = DAG.CreateStackTemporary(RetVT);
2084 Entry.Ty = RetTy->getPointerTo();
2085 Entry.isSExt = isSigned;
2086 Entry.isZExt = !isSigned;
2087 Args.push_back(Entry);
2089 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2090 TLI.getPointerTy());
2094 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
2095 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
2096 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2097 Callee, Args, DAG, dl);
2098 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2100 // Remainder is loaded back from the stack frame.
2101 SDValue Rem = DAG.getLoad(RetVT, dl, CallInfo.second, FIPtr,
2102 MachinePointerInfo(), false, false, false, 0);
2103 Results.push_back(CallInfo.first);
2104 Results.push_back(Rem);
2107 /// isSinCosLibcallAvailable - Return true if sincos libcall is available.
2108 static bool isSinCosLibcallAvailable(SDNode *Node, const TargetLowering &TLI) {
2110 switch (Node->getSimpleValueType(0).SimpleTy) {
2111 default: llvm_unreachable("Unexpected request for libcall!");
2112 case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2113 case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2114 case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2115 case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2116 case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2118 return TLI.getLibcallName(LC) != 0;
2121 /// canCombineSinCosLibcall - Return true if sincos libcall is available and
2122 /// can be used to combine sin and cos.
2123 static bool canCombineSinCosLibcall(SDNode *Node, const TargetLowering &TLI,
2124 const TargetMachine &TM) {
2125 if (!isSinCosLibcallAvailable(Node, TLI))
2127 // GNU sin/cos functions set errno while sincos does not. Therefore
2128 // combining sin and cos is only safe if unsafe-fpmath is enabled.
2129 bool isGNU = Triple(TM.getTargetTriple()).getEnvironment() == Triple::GNU;
2130 if (isGNU && !TM.Options.UnsafeFPMath)
2135 /// useSinCos - Only issue sincos libcall if both sin and cos are
2137 static bool useSinCos(SDNode *Node) {
2138 unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN
2139 ? ISD::FCOS : ISD::FSIN;
2141 SDValue Op0 = Node->getOperand(0);
2142 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2143 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2147 // The other user might have been turned into sincos already.
2148 if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS)
2154 /// ExpandSinCosLibCall - Issue libcalls to sincos to compute sin / cos
2157 SelectionDAGLegalize::ExpandSinCosLibCall(SDNode *Node,
2158 SmallVectorImpl<SDValue> &Results) {
2160 switch (Node->getSimpleValueType(0).SimpleTy) {
2161 default: llvm_unreachable("Unexpected request for libcall!");
2162 case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2163 case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2164 case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2165 case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2166 case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2169 // The input chain to this libcall is the entry node of the function.
2170 // Legalizing the call will automatically add the previous call to the
2172 SDValue InChain = DAG.getEntryNode();
2174 EVT RetVT = Node->getValueType(0);
2175 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2177 TargetLowering::ArgListTy Args;
2178 TargetLowering::ArgListEntry Entry;
2180 // Pass the argument.
2181 Entry.Node = Node->getOperand(0);
2183 Entry.isSExt = false;
2184 Entry.isZExt = false;
2185 Args.push_back(Entry);
2187 // Pass the return address of sin.
2188 SDValue SinPtr = DAG.CreateStackTemporary(RetVT);
2189 Entry.Node = SinPtr;
2190 Entry.Ty = RetTy->getPointerTo();
2191 Entry.isSExt = false;
2192 Entry.isZExt = false;
2193 Args.push_back(Entry);
2195 // Also pass the return address of the cos.
2196 SDValue CosPtr = DAG.CreateStackTemporary(RetVT);
2197 Entry.Node = CosPtr;
2198 Entry.Ty = RetTy->getPointerTo();
2199 Entry.isSExt = false;
2200 Entry.isZExt = false;
2201 Args.push_back(Entry);
2203 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2204 TLI.getPointerTy());
2208 CallLoweringInfo CLI(InChain, Type::getVoidTy(*DAG.getContext()),
2209 false, false, false, false,
2210 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
2211 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2212 Callee, Args, DAG, dl);
2213 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2215 Results.push_back(DAG.getLoad(RetVT, dl, CallInfo.second, SinPtr,
2216 MachinePointerInfo(), false, false, false, 0));
2217 Results.push_back(DAG.getLoad(RetVT, dl, CallInfo.second, CosPtr,
2218 MachinePointerInfo(), false, false, false, 0));
2221 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
2222 /// INT_TO_FP operation of the specified operand when the target requests that
2223 /// we expand it. At this point, we know that the result and operand types are
2224 /// legal for the target.
2225 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
2229 if (Op0.getValueType() == MVT::i32 && TLI.isTypeLegal(MVT::f64)) {
2230 // simple 32-bit [signed|unsigned] integer to float/double expansion
2232 // Get the stack frame index of a 8 byte buffer.
2233 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2235 // word offset constant for Hi/Lo address computation
2236 SDValue WordOff = DAG.getConstant(sizeof(int), StackSlot.getValueType());
2237 // set up Hi and Lo (into buffer) address based on endian
2238 SDValue Hi = StackSlot;
2239 SDValue Lo = DAG.getNode(ISD::ADD, dl, StackSlot.getValueType(),
2240 StackSlot, WordOff);
2241 if (TLI.isLittleEndian())
2244 // if signed map to unsigned space
2247 // constant used to invert sign bit (signed to unsigned mapping)
2248 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
2249 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2253 // store the lo of the constructed double - based on integer input
2254 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
2255 Op0Mapped, Lo, MachinePointerInfo(),
2257 // initial hi portion of constructed double
2258 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
2259 // store the hi of the constructed double - biased exponent
2260 SDValue Store2 = DAG.getStore(Store1, dl, InitialHi, Hi,
2261 MachinePointerInfo(),
2263 // load the constructed double
2264 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot,
2265 MachinePointerInfo(), false, false, false, 0);
2266 // FP constant to bias correct the final result
2267 SDValue Bias = DAG.getConstantFP(isSigned ?
2268 BitsToDouble(0x4330000080000000ULL) :
2269 BitsToDouble(0x4330000000000000ULL),
2271 // subtract the bias
2272 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2275 // handle final rounding
2276 if (DestVT == MVT::f64) {
2279 } else if (DestVT.bitsLT(MVT::f64)) {
2280 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2281 DAG.getIntPtrConstant(0));
2282 } else if (DestVT.bitsGT(MVT::f64)) {
2283 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2287 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2288 // Code below here assumes !isSigned without checking again.
2290 // Implementation of unsigned i64 to f64 following the algorithm in
2291 // __floatundidf in compiler_rt. This implementation has the advantage
2292 // of performing rounding correctly, both in the default rounding mode
2293 // and in all alternate rounding modes.
2294 // TODO: Generalize this for use with other types.
2295 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
2297 DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64);
2298 SDValue TwoP84PlusTwoP52 =
2299 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64);
2301 DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64);
2303 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32);
2304 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2305 DAG.getConstant(32, MVT::i64));
2306 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2307 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2308 SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr);
2309 SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr);
2310 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
2312 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
2315 // Implementation of unsigned i64 to f32.
2316 // TODO: Generalize this for use with other types.
2317 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) {
2318 // For unsigned conversions, convert them to signed conversions using the
2319 // algorithm from the x86_64 __floatundidf in compiler_rt.
2321 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0);
2323 SDValue ShiftConst =
2324 DAG.getConstant(1, TLI.getShiftAmountTy(Op0.getValueType()));
2325 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
2326 SDValue AndConst = DAG.getConstant(1, MVT::i64);
2327 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst);
2328 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr);
2330 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or);
2331 SDValue Slow = DAG.getNode(ISD::FADD, dl, MVT::f32, SignCvt, SignCvt);
2333 // TODO: This really should be implemented using a branch rather than a
2334 // select. We happen to get lucky and machinesink does the right
2335 // thing most of the time. This would be a good candidate for a
2336 //pseudo-op, or, even better, for whole-function isel.
2337 SDValue SignBitTest = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
2338 Op0, DAG.getConstant(0, MVT::i64), ISD::SETLT);
2339 return DAG.getSelect(dl, MVT::f32, SignBitTest, Slow, Fast);
2342 // Otherwise, implement the fully general conversion.
2344 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2345 DAG.getConstant(UINT64_C(0xfffffffffffff800), MVT::i64));
2346 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
2347 DAG.getConstant(UINT64_C(0x800), MVT::i64));
2348 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2349 DAG.getConstant(UINT64_C(0x7ff), MVT::i64));
2350 SDValue Ne = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
2351 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE);
2352 SDValue Sel = DAG.getSelect(dl, MVT::i64, Ne, Or, Op0);
2353 SDValue Ge = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
2354 Op0, DAG.getConstant(UINT64_C(0x0020000000000000), MVT::i64),
2356 SDValue Sel2 = DAG.getSelect(dl, MVT::i64, Ge, Sel, Op0);
2357 EVT SHVT = TLI.getShiftAmountTy(Sel2.getValueType());
2359 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2360 DAG.getConstant(32, SHVT));
2361 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh);
2362 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc);
2364 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), MVT::f64);
2365 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt);
2366 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2);
2367 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo);
2368 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2);
2369 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd,
2370 DAG.getIntPtrConstant(0));
2373 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2375 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(Op0.getValueType()),
2376 Op0, DAG.getConstant(0, Op0.getValueType()),
2378 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
2379 SDValue CstOffset = DAG.getSelect(dl, Zero.getValueType(),
2380 SignSet, Four, Zero);
2382 // If the sign bit of the integer is set, the large number will be treated
2383 // as a negative number. To counteract this, the dynamic code adds an
2384 // offset depending on the data type.
2386 switch (Op0.getSimpleValueType().SimpleTy) {
2387 default: llvm_unreachable("Unsupported integer type!");
2388 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2389 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2390 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2391 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2393 if (TLI.isLittleEndian()) FF <<= 32;
2394 Constant *FudgeFactor = ConstantInt::get(
2395 Type::getInt64Ty(*DAG.getContext()), FF);
2397 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
2398 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2399 CPIdx = DAG.getNode(ISD::ADD, dl, CPIdx.getValueType(), CPIdx, CstOffset);
2400 Alignment = std::min(Alignment, 4u);
2402 if (DestVT == MVT::f32)
2403 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2404 MachinePointerInfo::getConstantPool(),
2405 false, false, false, Alignment);
2407 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
2408 DAG.getEntryNode(), CPIdx,
2409 MachinePointerInfo::getConstantPool(),
2410 MVT::f32, false, false, Alignment);
2411 HandleSDNode Handle(Load);
2412 LegalizeOp(Load.getNode());
2413 FudgeInReg = Handle.getValue();
2416 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2419 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
2420 /// *INT_TO_FP operation of the specified operand when the target requests that
2421 /// we promote it. At this point, we know that the result and operand types are
2422 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2423 /// operation that takes a larger input.
2424 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2428 // First step, figure out the appropriate *INT_TO_FP operation to use.
2429 EVT NewInTy = LegalOp.getValueType();
2431 unsigned OpToUse = 0;
2433 // Scan for the appropriate larger type to use.
2435 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2436 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2438 // If the target supports SINT_TO_FP of this type, use it.
2439 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2440 OpToUse = ISD::SINT_TO_FP;
2443 if (isSigned) continue;
2445 // If the target supports UINT_TO_FP of this type, use it.
2446 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2447 OpToUse = ISD::UINT_TO_FP;
2451 // Otherwise, try a larger type.
2454 // Okay, we found the operation and type to use. Zero extend our input to the
2455 // desired type then run the operation on it.
2456 return DAG.getNode(OpToUse, dl, DestVT,
2457 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2458 dl, NewInTy, LegalOp));
2461 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
2462 /// FP_TO_*INT operation of the specified operand when the target requests that
2463 /// we promote it. At this point, we know that the result and operand types are
2464 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2465 /// operation that returns a larger result.
2466 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2470 // First step, figure out the appropriate FP_TO*INT operation to use.
2471 EVT NewOutTy = DestVT;
2473 unsigned OpToUse = 0;
2475 // Scan for the appropriate larger type to use.
2477 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2478 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2480 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2481 OpToUse = ISD::FP_TO_SINT;
2485 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2486 OpToUse = ISD::FP_TO_UINT;
2490 // Otherwise, try a larger type.
2494 // Okay, we found the operation and type to use.
2495 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2497 // Truncate the result of the extended FP_TO_*INT operation to the desired
2499 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2502 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
2504 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, SDLoc dl) {
2505 EVT VT = Op.getValueType();
2506 EVT SHVT = TLI.getShiftAmountTy(VT);
2507 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2508 switch (VT.getSimpleVT().SimpleTy) {
2509 default: llvm_unreachable("Unhandled Expand type in BSWAP!");
2511 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2512 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2513 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2515 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2516 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2517 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2518 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2519 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
2520 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
2521 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2522 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2523 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2525 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
2526 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
2527 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2528 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2529 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2530 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2531 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
2532 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
2533 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
2534 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
2535 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
2536 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
2537 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
2538 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
2539 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2540 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2541 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2542 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2543 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2544 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2545 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2549 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
2551 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2554 default: llvm_unreachable("Cannot expand this yet!");
2556 EVT VT = Op.getValueType();
2557 EVT ShVT = TLI.getShiftAmountTy(VT);
2558 unsigned Len = VT.getSizeInBits();
2560 assert(VT.isInteger() && Len <= 128 && Len % 8 == 0 &&
2561 "CTPOP not implemented for this type.");
2563 // This is the "best" algorithm from
2564 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
2566 SDValue Mask55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)), VT);
2567 SDValue Mask33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)), VT);
2568 SDValue Mask0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)), VT);
2569 SDValue Mask01 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x01)), VT);
2571 // v = v - ((v >> 1) & 0x55555555...)
2572 Op = DAG.getNode(ISD::SUB, dl, VT, Op,
2573 DAG.getNode(ISD::AND, dl, VT,
2574 DAG.getNode(ISD::SRL, dl, VT, Op,
2575 DAG.getConstant(1, ShVT)),
2577 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
2578 Op = DAG.getNode(ISD::ADD, dl, VT,
2579 DAG.getNode(ISD::AND, dl, VT, Op, Mask33),
2580 DAG.getNode(ISD::AND, dl, VT,
2581 DAG.getNode(ISD::SRL, dl, VT, Op,
2582 DAG.getConstant(2, ShVT)),
2584 // v = (v + (v >> 4)) & 0x0F0F0F0F...
2585 Op = DAG.getNode(ISD::AND, dl, VT,
2586 DAG.getNode(ISD::ADD, dl, VT, Op,
2587 DAG.getNode(ISD::SRL, dl, VT, Op,
2588 DAG.getConstant(4, ShVT))),
2590 // v = (v * 0x01010101...) >> (Len - 8)
2591 Op = DAG.getNode(ISD::SRL, dl, VT,
2592 DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
2593 DAG.getConstant(Len - 8, ShVT));
2597 case ISD::CTLZ_ZERO_UNDEF:
2598 // This trivially expands to CTLZ.
2599 return DAG.getNode(ISD::CTLZ, dl, Op.getValueType(), Op);
2601 // for now, we do this:
2602 // x = x | (x >> 1);
2603 // x = x | (x >> 2);
2605 // x = x | (x >>16);
2606 // x = x | (x >>32); // for 64-bit input
2607 // return popcount(~x);
2609 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
2610 EVT VT = Op.getValueType();
2611 EVT ShVT = TLI.getShiftAmountTy(VT);
2612 unsigned len = VT.getSizeInBits();
2613 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2614 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2615 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2616 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2618 Op = DAG.getNOT(dl, Op, VT);
2619 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2621 case ISD::CTTZ_ZERO_UNDEF:
2622 // This trivially expands to CTTZ.
2623 return DAG.getNode(ISD::CTTZ, dl, Op.getValueType(), Op);
2625 // for now, we use: { return popcount(~x & (x - 1)); }
2626 // unless the target has ctlz but not ctpop, in which case we use:
2627 // { return 32 - nlz(~x & (x-1)); }
2628 // see also http://www.hackersdelight.org/HDcode/ntz.cc
2629 EVT VT = Op.getValueType();
2630 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2631 DAG.getNOT(dl, Op, VT),
2632 DAG.getNode(ISD::SUB, dl, VT, Op,
2633 DAG.getConstant(1, VT)));
2634 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2635 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2636 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2637 return DAG.getNode(ISD::SUB, dl, VT,
2638 DAG.getConstant(VT.getSizeInBits(), VT),
2639 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2640 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2645 std::pair <SDValue, SDValue> SelectionDAGLegalize::ExpandAtomic(SDNode *Node) {
2646 unsigned Opc = Node->getOpcode();
2647 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
2652 llvm_unreachable("Unhandled atomic intrinsic Expand!");
2653 case ISD::ATOMIC_SWAP:
2654 switch (VT.SimpleTy) {
2655 default: llvm_unreachable("Unexpected value type for atomic!");
2656 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break;
2657 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
2658 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
2659 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
2662 case ISD::ATOMIC_CMP_SWAP:
2663 switch (VT.SimpleTy) {
2664 default: llvm_unreachable("Unexpected value type for atomic!");
2665 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break;
2666 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;
2667 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;
2668 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
2671 case ISD::ATOMIC_LOAD_ADD:
2672 switch (VT.SimpleTy) {
2673 default: llvm_unreachable("Unexpected value type for atomic!");
2674 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break;
2675 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;
2676 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;
2677 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
2680 case ISD::ATOMIC_LOAD_SUB:
2681 switch (VT.SimpleTy) {
2682 default: llvm_unreachable("Unexpected value type for atomic!");
2683 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break;
2684 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;
2685 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;
2686 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
2689 case ISD::ATOMIC_LOAD_AND:
2690 switch (VT.SimpleTy) {
2691 default: llvm_unreachable("Unexpected value type for atomic!");
2692 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break;
2693 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;
2694 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;
2695 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
2698 case ISD::ATOMIC_LOAD_OR:
2699 switch (VT.SimpleTy) {
2700 default: llvm_unreachable("Unexpected value type for atomic!");
2701 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break;
2702 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;
2703 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;
2704 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
2707 case ISD::ATOMIC_LOAD_XOR:
2708 switch (VT.SimpleTy) {
2709 default: llvm_unreachable("Unexpected value type for atomic!");
2710 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break;
2711 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;
2712 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;
2713 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
2716 case ISD::ATOMIC_LOAD_NAND:
2717 switch (VT.SimpleTy) {
2718 default: llvm_unreachable("Unexpected value type for atomic!");
2719 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break;
2720 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;
2721 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;
2722 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
2727 return ExpandChainLibCall(LC, Node, false);
2730 void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
2731 SmallVector<SDValue, 8> Results;
2733 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2734 switch (Node->getOpcode()) {
2737 case ISD::CTLZ_ZERO_UNDEF:
2739 case ISD::CTTZ_ZERO_UNDEF:
2740 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
2741 Results.push_back(Tmp1);
2744 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2746 case ISD::FRAMEADDR:
2747 case ISD::RETURNADDR:
2748 case ISD::FRAME_TO_ARGS_OFFSET:
2749 Results.push_back(DAG.getConstant(0, Node->getValueType(0)));
2751 case ISD::FLT_ROUNDS_:
2752 Results.push_back(DAG.getConstant(1, Node->getValueType(0)));
2754 case ISD::EH_RETURN:
2758 case ISD::EH_SJLJ_LONGJMP:
2759 // If the target didn't expand these, there's nothing to do, so just
2760 // preserve the chain and be done.
2761 Results.push_back(Node->getOperand(0));
2763 case ISD::EH_SJLJ_SETJMP:
2764 // If the target didn't expand this, just return 'zero' and preserve the
2766 Results.push_back(DAG.getConstant(0, MVT::i32));
2767 Results.push_back(Node->getOperand(0));
2769 case ISD::ATOMIC_FENCE: {
2770 // If the target didn't lower this, lower it to '__sync_synchronize()' call
2771 // FIXME: handle "fence singlethread" more efficiently.
2772 TargetLowering::ArgListTy Args;
2774 CallLoweringInfo CLI(Node->getOperand(0),
2775 Type::getVoidTy(*DAG.getContext()),
2776 false, false, false, false, 0, CallingConv::C,
2777 /*isTailCall=*/false,
2778 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2779 DAG.getExternalSymbol("__sync_synchronize",
2780 TLI.getPointerTy()),
2782 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
2784 Results.push_back(CallResult.second);
2787 case ISD::ATOMIC_LOAD: {
2788 // There is no libcall for atomic load; fake it with ATOMIC_CMP_SWAP.
2789 SDValue Zero = DAG.getConstant(0, Node->getValueType(0));
2790 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl,
2791 cast<AtomicSDNode>(Node)->getMemoryVT(),
2792 Node->getOperand(0),
2793 Node->getOperand(1), Zero, Zero,
2794 cast<AtomicSDNode>(Node)->getMemOperand(),
2795 cast<AtomicSDNode>(Node)->getOrdering(),
2796 cast<AtomicSDNode>(Node)->getSynchScope());
2797 Results.push_back(Swap.getValue(0));
2798 Results.push_back(Swap.getValue(1));
2801 case ISD::ATOMIC_STORE: {
2802 // There is no libcall for atomic store; fake it with ATOMIC_SWAP.
2803 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
2804 cast<AtomicSDNode>(Node)->getMemoryVT(),
2805 Node->getOperand(0),
2806 Node->getOperand(1), Node->getOperand(2),
2807 cast<AtomicSDNode>(Node)->getMemOperand(),
2808 cast<AtomicSDNode>(Node)->getOrdering(),
2809 cast<AtomicSDNode>(Node)->getSynchScope());
2810 Results.push_back(Swap.getValue(1));
2813 // By default, atomic intrinsics are marked Legal and lowered. Targets
2814 // which don't support them directly, however, may want libcalls, in which
2815 // case they mark them Expand, and we get here.
2816 case ISD::ATOMIC_SWAP:
2817 case ISD::ATOMIC_LOAD_ADD:
2818 case ISD::ATOMIC_LOAD_SUB:
2819 case ISD::ATOMIC_LOAD_AND:
2820 case ISD::ATOMIC_LOAD_OR:
2821 case ISD::ATOMIC_LOAD_XOR:
2822 case ISD::ATOMIC_LOAD_NAND:
2823 case ISD::ATOMIC_LOAD_MIN:
2824 case ISD::ATOMIC_LOAD_MAX:
2825 case ISD::ATOMIC_LOAD_UMIN:
2826 case ISD::ATOMIC_LOAD_UMAX:
2827 case ISD::ATOMIC_CMP_SWAP: {
2828 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node);
2829 Results.push_back(Tmp.first);
2830 Results.push_back(Tmp.second);
2833 case ISD::DYNAMIC_STACKALLOC:
2834 ExpandDYNAMIC_STACKALLOC(Node, Results);
2836 case ISD::MERGE_VALUES:
2837 for (unsigned i = 0; i < Node->getNumValues(); i++)
2838 Results.push_back(Node->getOperand(i));
2841 EVT VT = Node->getValueType(0);
2843 Results.push_back(DAG.getConstant(0, VT));
2845 assert(VT.isFloatingPoint() && "Unknown value type!");
2846 Results.push_back(DAG.getConstantFP(0, VT));
2851 // If this operation is not supported, lower it to 'abort()' call
2852 TargetLowering::ArgListTy Args;
2854 CallLoweringInfo CLI(Node->getOperand(0),
2855 Type::getVoidTy(*DAG.getContext()),
2856 false, false, false, false, 0, CallingConv::C,
2857 /*isTailCall=*/false,
2858 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2859 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
2861 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
2863 Results.push_back(CallResult.second);
2868 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
2869 Node->getValueType(0), dl);
2870 Results.push_back(Tmp1);
2872 case ISD::FP_EXTEND:
2873 Tmp1 = EmitStackConvert(Node->getOperand(0),
2874 Node->getOperand(0).getValueType(),
2875 Node->getValueType(0), dl);
2876 Results.push_back(Tmp1);
2878 case ISD::SIGN_EXTEND_INREG: {
2879 // NOTE: we could fall back on load/store here too for targets without
2880 // SAR. However, it is doubtful that any exist.
2881 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2882 EVT VT = Node->getValueType(0);
2883 EVT ShiftAmountTy = TLI.getShiftAmountTy(VT);
2886 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
2887 ExtraVT.getScalarType().getSizeInBits();
2888 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy);
2889 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
2890 Node->getOperand(0), ShiftCst);
2891 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
2892 Results.push_back(Tmp1);
2895 case ISD::FP_ROUND_INREG: {
2896 // The only way we can lower this is to turn it into a TRUNCSTORE,
2897 // EXTLOAD pair, targeting a temporary location (a stack slot).
2899 // NOTE: there is a choice here between constantly creating new stack
2900 // slots and always reusing the same one. We currently always create
2901 // new ones, as reuse may inhibit scheduling.
2902 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2903 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
2904 Node->getValueType(0), dl);
2905 Results.push_back(Tmp1);
2908 case ISD::SINT_TO_FP:
2909 case ISD::UINT_TO_FP:
2910 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
2911 Node->getOperand(0), Node->getValueType(0), dl);
2912 Results.push_back(Tmp1);
2914 case ISD::FP_TO_UINT: {
2915 SDValue True, False;
2916 EVT VT = Node->getOperand(0).getValueType();
2917 EVT NVT = Node->getValueType(0);
2918 APFloat apf(DAG.EVTToAPFloatSemantics(VT),
2919 APInt::getNullValue(VT.getSizeInBits()));
2920 APInt x = APInt::getSignBit(NVT.getSizeInBits());
2921 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
2922 Tmp1 = DAG.getConstantFP(apf, VT);
2923 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(VT),
2924 Node->getOperand(0),
2926 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
2927 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
2928 DAG.getNode(ISD::FSUB, dl, VT,
2929 Node->getOperand(0), Tmp1));
2930 False = DAG.getNode(ISD::XOR, dl, NVT, False,
2931 DAG.getConstant(x, NVT));
2932 Tmp1 = DAG.getSelect(dl, NVT, Tmp2, True, False);
2933 Results.push_back(Tmp1);
2937 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2938 EVT VT = Node->getValueType(0);
2939 Tmp1 = Node->getOperand(0);
2940 Tmp2 = Node->getOperand(1);
2941 unsigned Align = Node->getConstantOperandVal(3);
2943 SDValue VAListLoad = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2,
2944 MachinePointerInfo(V),
2945 false, false, false, 0);
2946 SDValue VAList = VAListLoad;
2948 if (Align > TLI.getMinStackArgumentAlignment()) {
2949 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
2951 VAList = DAG.getNode(ISD::ADD, dl, VAList.getValueType(), VAList,
2952 DAG.getConstant(Align - 1,
2953 VAList.getValueType()));
2955 VAList = DAG.getNode(ISD::AND, dl, VAList.getValueType(), VAList,
2956 DAG.getConstant(-(int64_t)Align,
2957 VAList.getValueType()));
2960 // Increment the pointer, VAList, to the next vaarg
2961 Tmp3 = DAG.getNode(ISD::ADD, dl, VAList.getValueType(), VAList,
2962 DAG.getConstant(TLI.getDataLayout()->
2963 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())),
2964 VAList.getValueType()));
2965 // Store the incremented VAList to the legalized pointer
2966 Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2,
2967 MachinePointerInfo(V), false, false, 0);
2968 // Load the actual argument out of the pointer VAList
2969 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(),
2970 false, false, false, 0));
2971 Results.push_back(Results[0].getValue(1));
2975 // This defaults to loading a pointer from the input and storing it to the
2976 // output, returning the chain.
2977 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
2978 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
2979 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0),
2980 Node->getOperand(2), MachinePointerInfo(VS),
2981 false, false, false, 0);
2982 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1),
2983 MachinePointerInfo(VD), false, false, 0);
2984 Results.push_back(Tmp1);
2987 case ISD::EXTRACT_VECTOR_ELT:
2988 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
2989 // This must be an access of the only element. Return it.
2990 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
2991 Node->getOperand(0));
2993 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
2994 Results.push_back(Tmp1);
2996 case ISD::EXTRACT_SUBVECTOR:
2997 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
2999 case ISD::INSERT_SUBVECTOR:
3000 Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0)));
3002 case ISD::CONCAT_VECTORS: {
3003 Results.push_back(ExpandVectorBuildThroughStack(Node));
3006 case ISD::SCALAR_TO_VECTOR:
3007 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
3009 case ISD::INSERT_VECTOR_ELT:
3010 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
3011 Node->getOperand(1),
3012 Node->getOperand(2), dl));
3014 case ISD::VECTOR_SHUFFLE: {
3015 SmallVector<int, 32> NewMask;
3016 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
3018 EVT VT = Node->getValueType(0);
3019 EVT EltVT = VT.getVectorElementType();
3020 SDValue Op0 = Node->getOperand(0);
3021 SDValue Op1 = Node->getOperand(1);
3022 if (!TLI.isTypeLegal(EltVT)) {
3024 EVT NewEltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
3026 // BUILD_VECTOR operands are allowed to be wider than the element type.
3027 // But if NewEltVT is smaller that EltVT the BUILD_VECTOR does not accept it
3028 if (NewEltVT.bitsLT(EltVT)) {
3030 // Convert shuffle node.
3031 // If original node was v4i64 and the new EltVT is i32,
3032 // cast operands to v8i32 and re-build the mask.
3034 // Calculate new VT, the size of the new VT should be equal to original.
3035 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), NewEltVT,
3036 VT.getSizeInBits()/NewEltVT.getSizeInBits());
3037 assert(NewVT.bitsEq(VT));
3039 // cast operands to new VT
3040 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0);
3041 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1);
3043 // Convert the shuffle mask
3044 unsigned int factor = NewVT.getVectorNumElements()/VT.getVectorNumElements();
3046 // EltVT gets smaller
3049 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
3051 for (unsigned fi = 0; fi < factor; ++fi)
3052 NewMask.push_back(Mask[i]);
3055 for (unsigned fi = 0; fi < factor; ++fi)
3056 NewMask.push_back(Mask[i]*factor+fi);
3064 unsigned NumElems = VT.getVectorNumElements();
3065 SmallVector<SDValue, 16> Ops;
3066 for (unsigned i = 0; i != NumElems; ++i) {
3068 Ops.push_back(DAG.getUNDEF(EltVT));
3071 unsigned Idx = Mask[i];
3073 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3075 DAG.getConstant(Idx, TLI.getVectorIdxTy())));
3077 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3079 DAG.getConstant(Idx - NumElems,
3080 TLI.getVectorIdxTy())));
3083 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
3084 // We may have changed the BUILD_VECTOR type. Cast it back to the Node type.
3085 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), Tmp1);
3086 Results.push_back(Tmp1);
3089 case ISD::EXTRACT_ELEMENT: {
3090 EVT OpTy = Node->getOperand(0).getValueType();
3091 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
3093 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
3094 DAG.getConstant(OpTy.getSizeInBits()/2,
3095 TLI.getShiftAmountTy(Node->getOperand(0).getValueType())));
3096 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
3099 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
3100 Node->getOperand(0));
3102 Results.push_back(Tmp1);
3105 case ISD::STACKSAVE:
3106 // Expand to CopyFromReg if the target set
3107 // StackPointerRegisterToSaveRestore.
3108 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3109 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
3110 Node->getValueType(0)));
3111 Results.push_back(Results[0].getValue(1));
3113 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
3114 Results.push_back(Node->getOperand(0));
3117 case ISD::STACKRESTORE:
3118 // Expand to CopyToReg if the target set
3119 // StackPointerRegisterToSaveRestore.
3120 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3121 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
3122 Node->getOperand(1)));
3124 Results.push_back(Node->getOperand(0));
3127 case ISD::FCOPYSIGN:
3128 Results.push_back(ExpandFCOPYSIGN(Node));
3131 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3132 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3133 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
3134 Node->getOperand(0));
3135 Results.push_back(Tmp1);
3138 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3139 EVT VT = Node->getValueType(0);
3140 Tmp1 = Node->getOperand(0);
3141 Tmp2 = DAG.getConstantFP(0.0, VT);
3142 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(Tmp1.getValueType()),
3143 Tmp1, Tmp2, ISD::SETUGT);
3144 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
3145 Tmp1 = DAG.getSelect(dl, VT, Tmp2, Tmp1, Tmp3);
3146 Results.push_back(Tmp1);
3150 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3151 RTLIB::SQRT_F80, RTLIB::SQRT_F128,
3152 RTLIB::SQRT_PPCF128));
3156 EVT VT = Node->getValueType(0);
3157 bool isSIN = Node->getOpcode() == ISD::FSIN;
3158 // Turn fsin / fcos into ISD::FSINCOS node if there are a pair of fsin /
3159 // fcos which share the same operand and both are used.
3160 if ((TLI.isOperationLegalOrCustom(ISD::FSINCOS, VT) ||
3161 canCombineSinCosLibcall(Node, TLI, TM))
3162 && useSinCos(Node)) {
3163 SDVTList VTs = DAG.getVTList(VT, VT);
3164 Tmp1 = DAG.getNode(ISD::FSINCOS, dl, VTs, Node->getOperand(0));
3166 Tmp1 = Tmp1.getValue(1);
3167 Results.push_back(Tmp1);
3169 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
3170 RTLIB::SIN_F80, RTLIB::SIN_F128,
3171 RTLIB::SIN_PPCF128));
3173 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
3174 RTLIB::COS_F80, RTLIB::COS_F128,
3175 RTLIB::COS_PPCF128));
3180 // Expand into sincos libcall.
3181 ExpandSinCosLibCall(Node, Results);
3184 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
3185 RTLIB::LOG_F80, RTLIB::LOG_F128,
3186 RTLIB::LOG_PPCF128));
3189 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3190 RTLIB::LOG2_F80, RTLIB::LOG2_F128,
3191 RTLIB::LOG2_PPCF128));
3194 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3195 RTLIB::LOG10_F80, RTLIB::LOG10_F128,
3196 RTLIB::LOG10_PPCF128));
3199 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
3200 RTLIB::EXP_F80, RTLIB::EXP_F128,
3201 RTLIB::EXP_PPCF128));
3204 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3205 RTLIB::EXP2_F80, RTLIB::EXP2_F128,
3206 RTLIB::EXP2_PPCF128));
3209 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3210 RTLIB::TRUNC_F80, RTLIB::TRUNC_F128,
3211 RTLIB::TRUNC_PPCF128));
3214 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3215 RTLIB::FLOOR_F80, RTLIB::FLOOR_F128,
3216 RTLIB::FLOOR_PPCF128));
3219 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3220 RTLIB::CEIL_F80, RTLIB::CEIL_F128,
3221 RTLIB::CEIL_PPCF128));
3224 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
3225 RTLIB::RINT_F80, RTLIB::RINT_F128,
3226 RTLIB::RINT_PPCF128));
3228 case ISD::FNEARBYINT:
3229 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
3230 RTLIB::NEARBYINT_F64,
3231 RTLIB::NEARBYINT_F80,
3232 RTLIB::NEARBYINT_F128,
3233 RTLIB::NEARBYINT_PPCF128));
3236 Results.push_back(ExpandFPLibCall(Node, RTLIB::ROUND_F32,
3240 RTLIB::ROUND_PPCF128));
3243 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
3244 RTLIB::POWI_F80, RTLIB::POWI_F128,
3245 RTLIB::POWI_PPCF128));
3248 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
3249 RTLIB::POW_F80, RTLIB::POW_F128,
3250 RTLIB::POW_PPCF128));
3253 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
3254 RTLIB::DIV_F80, RTLIB::DIV_F128,
3255 RTLIB::DIV_PPCF128));
3258 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
3259 RTLIB::REM_F80, RTLIB::REM_F128,
3260 RTLIB::REM_PPCF128));
3263 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMA_F32, RTLIB::FMA_F64,
3264 RTLIB::FMA_F80, RTLIB::FMA_F128,
3265 RTLIB::FMA_PPCF128));
3267 case ISD::FP16_TO_FP32:
3268 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
3270 case ISD::FP32_TO_FP16:
3271 Results.push_back(ExpandLibCall(RTLIB::FPROUND_F32_F16, Node, false));
3273 case ISD::ConstantFP: {
3274 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
3275 // Check to see if this FP immediate is already legal.
3276 // If this is a legal constant, turn it into a TargetConstantFP node.
3277 if (!TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
3278 Results.push_back(ExpandConstantFP(CFP, true));
3282 EVT VT = Node->getValueType(0);
3283 assert(TLI.isOperationLegalOrCustom(ISD::FADD, VT) &&
3284 TLI.isOperationLegalOrCustom(ISD::FNEG, VT) &&
3285 "Don't know how to expand this FP subtraction!");
3286 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1));
3287 Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1);
3288 Results.push_back(Tmp1);
3292 EVT VT = Node->getValueType(0);
3293 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3294 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3295 "Don't know how to expand this subtraction!");
3296 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3297 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
3298 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, VT));
3299 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3304 EVT VT = Node->getValueType(0);
3305 bool isSigned = Node->getOpcode() == ISD::SREM;
3306 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3307 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3308 Tmp2 = Node->getOperand(0);
3309 Tmp3 = Node->getOperand(1);
3310 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3311 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3312 // If div is legal, it's better to do the normal expansion
3313 !TLI.isOperationLegalOrCustom(DivOpc, Node->getValueType(0)) &&
3314 useDivRem(Node, isSigned, false))) {
3315 SDVTList VTs = DAG.getVTList(VT, VT);
3316 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
3317 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
3319 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
3320 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3321 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3322 } else if (isSigned)
3323 Tmp1 = ExpandIntLibCall(Node, true,
3325 RTLIB::SREM_I16, RTLIB::SREM_I32,
3326 RTLIB::SREM_I64, RTLIB::SREM_I128);
3328 Tmp1 = ExpandIntLibCall(Node, false,
3330 RTLIB::UREM_I16, RTLIB::UREM_I32,
3331 RTLIB::UREM_I64, RTLIB::UREM_I128);
3332 Results.push_back(Tmp1);
3337 bool isSigned = Node->getOpcode() == ISD::SDIV;
3338 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3339 EVT VT = Node->getValueType(0);
3340 SDVTList VTs = DAG.getVTList(VT, VT);
3341 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3342 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3343 useDivRem(Node, isSigned, true)))
3344 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
3345 Node->getOperand(1));
3347 Tmp1 = ExpandIntLibCall(Node, true,
3349 RTLIB::SDIV_I16, RTLIB::SDIV_I32,
3350 RTLIB::SDIV_I64, RTLIB::SDIV_I128);
3352 Tmp1 = ExpandIntLibCall(Node, false,
3354 RTLIB::UDIV_I16, RTLIB::UDIV_I32,
3355 RTLIB::UDIV_I64, RTLIB::UDIV_I128);
3356 Results.push_back(Tmp1);
3361 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
3363 EVT VT = Node->getValueType(0);
3364 SDVTList VTs = DAG.getVTList(VT, VT);
3365 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
3366 "If this wasn't legal, it shouldn't have been created!");
3367 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
3368 Node->getOperand(1));
3369 Results.push_back(Tmp1.getValue(1));
3374 // Expand into divrem libcall
3375 ExpandDivRemLibCall(Node, Results);
3378 EVT VT = Node->getValueType(0);
3379 SDVTList VTs = DAG.getVTList(VT, VT);
3380 // See if multiply or divide can be lowered using two-result operations.
3381 // We just need the low half of the multiply; try both the signed
3382 // and unsigned forms. If the target supports both SMUL_LOHI and
3383 // UMUL_LOHI, form a preference by checking which forms of plain
3384 // MULH it supports.
3385 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3386 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3387 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3388 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3389 unsigned OpToUse = 0;
3390 if (HasSMUL_LOHI && !HasMULHS) {
3391 OpToUse = ISD::SMUL_LOHI;
3392 } else if (HasUMUL_LOHI && !HasMULHU) {
3393 OpToUse = ISD::UMUL_LOHI;
3394 } else if (HasSMUL_LOHI) {
3395 OpToUse = ISD::SMUL_LOHI;
3396 } else if (HasUMUL_LOHI) {
3397 OpToUse = ISD::UMUL_LOHI;
3400 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
3401 Node->getOperand(1)));
3404 Tmp1 = ExpandIntLibCall(Node, false,
3406 RTLIB::MUL_I16, RTLIB::MUL_I32,
3407 RTLIB::MUL_I64, RTLIB::MUL_I128);
3408 Results.push_back(Tmp1);
3413 SDValue LHS = Node->getOperand(0);
3414 SDValue RHS = Node->getOperand(1);
3415 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3416 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3418 Results.push_back(Sum);
3419 EVT OType = Node->getValueType(1);
3421 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
3423 // LHSSign -> LHS >= 0
3424 // RHSSign -> RHS >= 0
3425 // SumSign -> Sum >= 0
3428 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3430 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3432 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3433 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3434 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
3435 Node->getOpcode() == ISD::SADDO ?
3436 ISD::SETEQ : ISD::SETNE);
3438 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3439 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3441 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3442 Results.push_back(Cmp);
3447 SDValue LHS = Node->getOperand(0);
3448 SDValue RHS = Node->getOperand(1);
3449 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
3450 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3452 Results.push_back(Sum);
3453 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS,
3454 Node->getOpcode () == ISD::UADDO ?
3455 ISD::SETULT : ISD::SETUGT));
3460 EVT VT = Node->getValueType(0);
3461 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
3462 SDValue LHS = Node->getOperand(0);
3463 SDValue RHS = Node->getOperand(1);
3466 static const unsigned Ops[2][3] =
3467 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
3468 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
3469 bool isSigned = Node->getOpcode() == ISD::SMULO;
3470 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3471 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3472 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3473 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3474 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3476 TopHalf = BottomHalf.getValue(1);
3477 } else if (TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(),
3478 VT.getSizeInBits() * 2))) {
3479 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
3480 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
3481 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
3482 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3483 DAG.getIntPtrConstant(0));
3484 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3485 DAG.getIntPtrConstant(1));
3487 // We can fall back to a libcall with an illegal type for the MUL if we
3488 // have a libcall big enough.
3489 // Also, we can fall back to a division in some cases, but that's a big
3490 // performance hit in the general case.
3491 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3492 if (WideVT == MVT::i16)
3493 LC = RTLIB::MUL_I16;
3494 else if (WideVT == MVT::i32)
3495 LC = RTLIB::MUL_I32;
3496 else if (WideVT == MVT::i64)
3497 LC = RTLIB::MUL_I64;
3498 else if (WideVT == MVT::i128)
3499 LC = RTLIB::MUL_I128;
3500 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!");
3502 // The high part is obtained by SRA'ing all but one of the bits of low
3504 unsigned LoSize = VT.getSizeInBits();
3505 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, RHS,
3506 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
3507 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, VT, LHS,
3508 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
3510 // Here we're passing the 2 arguments explicitly as 4 arguments that are
3511 // pre-lowered to the correct types. This all depends upon WideVT not
3512 // being a legal type for the architecture and thus has to be split to
3514 SDValue Args[] = { LHS, HiLHS, RHS, HiRHS };
3515 SDValue Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl);
3516 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3517 DAG.getIntPtrConstant(0));
3518 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3519 DAG.getIntPtrConstant(1));
3520 // Ret is a node with an illegal type. Because such things are not
3521 // generally permitted during this phase of legalization, delete the
3522 // node. The above EXTRACT_ELEMENT nodes should have been folded.
3523 DAG.DeleteNode(Ret.getNode());
3527 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1,
3528 TLI.getShiftAmountTy(BottomHalf.getValueType()));
3529 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3530 TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf, Tmp1,
3533 TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf,
3534 DAG.getConstant(0, VT), ISD::SETNE);
3536 Results.push_back(BottomHalf);
3537 Results.push_back(TopHalf);
3540 case ISD::BUILD_PAIR: {
3541 EVT PairTy = Node->getValueType(0);
3542 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3543 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3544 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
3545 DAG.getConstant(PairTy.getSizeInBits()/2,
3546 TLI.getShiftAmountTy(PairTy)));
3547 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3551 Tmp1 = Node->getOperand(0);
3552 Tmp2 = Node->getOperand(1);
3553 Tmp3 = Node->getOperand(2);
3554 if (Tmp1.getOpcode() == ISD::SETCC) {
3555 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3557 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3559 Tmp1 = DAG.getSelectCC(dl, Tmp1,
3560 DAG.getConstant(0, Tmp1.getValueType()),
3561 Tmp2, Tmp3, ISD::SETNE);
3563 Results.push_back(Tmp1);
3566 SDValue Chain = Node->getOperand(0);
3567 SDValue Table = Node->getOperand(1);
3568 SDValue Index = Node->getOperand(2);
3570 EVT PTy = TLI.getPointerTy();
3572 const DataLayout &TD = *TLI.getDataLayout();
3573 unsigned EntrySize =
3574 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
3576 Index = DAG.getNode(ISD::MUL, dl, Index.getValueType(),
3577 Index, DAG.getConstant(EntrySize, Index.getValueType()));
3578 SDValue Addr = DAG.getNode(ISD::ADD, dl, Index.getValueType(),
3581 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
3582 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
3583 MachinePointerInfo::getJumpTable(), MemVT,
3586 if (TM.getRelocationModel() == Reloc::PIC_) {
3587 // For PIC, the sequence is:
3588 // BRIND(load(Jumptable + index) + RelocBase)
3589 // RelocBase can be JumpTable, GOT or some sort of global base.
3590 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3591 TLI.getPICJumpTableRelocBase(Table, DAG));
3593 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
3594 Results.push_back(Tmp1);
3598 // Expand brcond's setcc into its constituent parts and create a BR_CC
3600 Tmp1 = Node->getOperand(0);
3601 Tmp2 = Node->getOperand(1);
3602 if (Tmp2.getOpcode() == ISD::SETCC) {
3603 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3604 Tmp1, Tmp2.getOperand(2),
3605 Tmp2.getOperand(0), Tmp2.getOperand(1),
3606 Node->getOperand(2));
3608 // We test only the i1 bit. Skip the AND if UNDEF.
3609 Tmp3 = (Tmp2.getOpcode() == ISD::UNDEF) ? Tmp2 :
3610 DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2,
3611 DAG.getConstant(1, Tmp2.getValueType()));
3612 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3613 DAG.getCondCode(ISD::SETNE), Tmp3,
3614 DAG.getConstant(0, Tmp3.getValueType()),
3615 Node->getOperand(2));
3617 Results.push_back(Tmp1);
3620 Tmp1 = Node->getOperand(0);
3621 Tmp2 = Node->getOperand(1);
3622 Tmp3 = Node->getOperand(2);
3623 LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl);
3625 // If we expanded the SETCC into an AND/OR, return the new node
3626 if (Tmp2.getNode() == 0) {
3627 Results.push_back(Tmp1);
3631 // Otherwise, SETCC for the given comparison type must be completely
3632 // illegal; expand it into a SELECT_CC.
3633 EVT VT = Node->getValueType(0);
3635 switch (TLI.getBooleanContents(VT.isVector())) {
3636 case TargetLowering::ZeroOrOneBooleanContent:
3637 case TargetLowering::UndefinedBooleanContent:
3640 case TargetLowering::ZeroOrNegativeOneBooleanContent:
3644 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3645 DAG.getConstant(TrueValue, VT), DAG.getConstant(0, VT),
3647 Results.push_back(Tmp1);
3650 case ISD::SELECT_CC: {
3651 Tmp1 = Node->getOperand(0); // LHS
3652 Tmp2 = Node->getOperand(1); // RHS
3653 Tmp3 = Node->getOperand(2); // True
3654 Tmp4 = Node->getOperand(3); // False
3655 SDValue CC = Node->getOperand(4);
3657 LegalizeSetCCCondCode(getSetCCResultType(Tmp1.getValueType()),
3658 Tmp1, Tmp2, CC, dl);
3660 assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!");
3661 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3662 CC = DAG.getCondCode(ISD::SETNE);
3663 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2,
3665 Results.push_back(Tmp1);
3669 Tmp1 = Node->getOperand(0); // Chain
3670 Tmp2 = Node->getOperand(2); // LHS
3671 Tmp3 = Node->getOperand(3); // RHS
3672 Tmp4 = Node->getOperand(1); // CC
3674 LegalizeSetCCCondCode(getSetCCResultType(Tmp2.getValueType()),
3675 Tmp2, Tmp3, Tmp4, dl);
3677 assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!");
3678 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
3679 Tmp4 = DAG.getCondCode(ISD::SETNE);
3680 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2,
3681 Tmp3, Node->getOperand(4));
3682 Results.push_back(Tmp1);
3685 case ISD::BUILD_VECTOR:
3686 Results.push_back(ExpandBUILD_VECTOR(Node));
3691 // Scalarize vector SRA/SRL/SHL.
3692 EVT VT = Node->getValueType(0);
3693 assert(VT.isVector() && "Unable to legalize non-vector shift");
3694 assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
3695 unsigned NumElem = VT.getVectorNumElements();
3697 SmallVector<SDValue, 8> Scalars;
3698 for (unsigned Idx = 0; Idx < NumElem; Idx++) {
3699 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3701 Node->getOperand(0), DAG.getConstant(Idx,
3702 TLI.getVectorIdxTy()));
3703 SDValue Sh = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3705 Node->getOperand(1), DAG.getConstant(Idx,
3706 TLI.getVectorIdxTy()));
3707 Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
3708 VT.getScalarType(), Ex, Sh));
3711 DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0),
3712 &Scalars[0], Scalars.size());
3713 ReplaceNode(SDValue(Node, 0), Result);
3716 case ISD::GLOBAL_OFFSET_TABLE:
3717 case ISD::GlobalAddress:
3718 case ISD::GlobalTLSAddress:
3719 case ISD::ExternalSymbol:
3720 case ISD::ConstantPool:
3721 case ISD::JumpTable:
3722 case ISD::INTRINSIC_W_CHAIN:
3723 case ISD::INTRINSIC_WO_CHAIN:
3724 case ISD::INTRINSIC_VOID:
3725 // FIXME: Custom lowering for these operations shouldn't return null!
3729 // Replace the original node with the legalized result.
3730 if (!Results.empty())
3731 ReplaceNode(Node, Results.data());
3734 void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
3735 SmallVector<SDValue, 8> Results;
3736 MVT OVT = Node->getSimpleValueType(0);
3737 if (Node->getOpcode() == ISD::UINT_TO_FP ||
3738 Node->getOpcode() == ISD::SINT_TO_FP ||
3739 Node->getOpcode() == ISD::SETCC) {
3740 OVT = Node->getOperand(0).getSimpleValueType();
3742 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3744 SDValue Tmp1, Tmp2, Tmp3;
3745 switch (Node->getOpcode()) {
3747 case ISD::CTTZ_ZERO_UNDEF:
3749 case ISD::CTLZ_ZERO_UNDEF:
3751 // Zero extend the argument.
3752 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3753 // Perform the larger operation. For CTPOP and CTTZ_ZERO_UNDEF, this is
3754 // already the correct result.
3755 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
3756 if (Node->getOpcode() == ISD::CTTZ) {
3757 // FIXME: This should set a bit in the zero extended value instead.
3758 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT),
3759 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
3761 Tmp1 = DAG.getSelect(dl, NVT, Tmp2,
3762 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3763 } else if (Node->getOpcode() == ISD::CTLZ ||
3764 Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) {
3765 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3766 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
3767 DAG.getConstant(NVT.getSizeInBits() -
3768 OVT.getSizeInBits(), NVT));
3770 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
3773 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3774 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3775 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
3776 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
3777 DAG.getConstant(DiffBits, TLI.getShiftAmountTy(NVT)));
3778 Results.push_back(Tmp1);
3781 case ISD::FP_TO_UINT:
3782 case ISD::FP_TO_SINT:
3783 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
3784 Node->getOpcode() == ISD::FP_TO_SINT, dl);
3785 Results.push_back(Tmp1);
3787 case ISD::UINT_TO_FP:
3788 case ISD::SINT_TO_FP:
3789 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
3790 Node->getOpcode() == ISD::SINT_TO_FP, dl);
3791 Results.push_back(Tmp1);
3794 SDValue Chain = Node->getOperand(0); // Get the chain.
3795 SDValue Ptr = Node->getOperand(1); // Get the pointer.
3798 if (OVT.isVector()) {
3799 TruncOp = ISD::BITCAST;
3801 assert(OVT.isInteger()
3802 && "VAARG promotion is supported only for vectors or integer types");
3803 TruncOp = ISD::TRUNCATE;
3806 // Perform the larger operation, then convert back
3807 Tmp1 = DAG.getVAArg(NVT, dl, Chain, Ptr, Node->getOperand(2),
3808 Node->getConstantOperandVal(3));
3809 Chain = Tmp1.getValue(1);
3811 Tmp2 = DAG.getNode(TruncOp, dl, OVT, Tmp1);
3813 // Modified the chain result - switch anything that used the old chain to
3815 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp2);
3816 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
3823 unsigned ExtOp, TruncOp;
3824 if (OVT.isVector()) {
3825 ExtOp = ISD::BITCAST;
3826 TruncOp = ISD::BITCAST;
3828 assert(OVT.isInteger() && "Cannot promote logic operation");
3829 ExtOp = ISD::ANY_EXTEND;
3830 TruncOp = ISD::TRUNCATE;
3832 // Promote each of the values to the new type.
3833 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3834 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3835 // Perform the larger operation, then convert back
3836 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3837 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
3841 unsigned ExtOp, TruncOp;
3842 if (Node->getValueType(0).isVector()) {
3843 ExtOp = ISD::BITCAST;
3844 TruncOp = ISD::BITCAST;
3845 } else if (Node->getValueType(0).isInteger()) {
3846 ExtOp = ISD::ANY_EXTEND;
3847 TruncOp = ISD::TRUNCATE;
3849 ExtOp = ISD::FP_EXTEND;
3850 TruncOp = ISD::FP_ROUND;
3852 Tmp1 = Node->getOperand(0);
3853 // Promote each of the values to the new type.
3854 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3855 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
3856 // Perform the larger operation, then round down.
3857 Tmp1 = DAG.getSelect(dl, NVT, Tmp1, Tmp2, Tmp3);
3858 if (TruncOp != ISD::FP_ROUND)
3859 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
3861 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
3862 DAG.getIntPtrConstant(0));
3863 Results.push_back(Tmp1);
3866 case ISD::VECTOR_SHUFFLE: {
3867 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
3869 // Cast the two input vectors.
3870 Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
3871 Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
3873 // Convert the shuffle mask to the right # elements.
3874 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
3875 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
3876 Results.push_back(Tmp1);
3880 unsigned ExtOp = ISD::FP_EXTEND;
3881 if (NVT.isInteger()) {
3882 ISD::CondCode CCCode =
3883 cast<CondCodeSDNode>(Node->getOperand(2))->get();
3884 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3886 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3887 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3888 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3889 Tmp1, Tmp2, Node->getOperand(2)));
3895 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
3896 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
3897 Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3898 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
3899 Tmp3, DAG.getIntPtrConstant(0)));
3906 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
3907 Tmp2 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
3908 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
3909 Tmp2, DAG.getIntPtrConstant(0)));
3914 // Replace the original node with the legalized result.
3915 if (!Results.empty())
3916 ReplaceNode(Node, Results.data());
3919 // SelectionDAG::Legalize - This is the entry point for the file.
3921 void SelectionDAG::Legalize() {
3922 /// run - This is the main entry point to this class.
3924 SelectionDAGLegalize(*this).LegalizeDAG();