1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/ADT/SetVector.h"
16 #include "llvm/ADT/SmallPtrSet.h"
17 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/CodeGen/Analysis.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineJumpTableInfo.h"
23 #include "llvm/IR/CallingConv.h"
24 #include "llvm/IR/Constants.h"
25 #include "llvm/IR/DataLayout.h"
26 #include "llvm/IR/DebugInfo.h"
27 #include "llvm/IR/DerivedTypes.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/LLVMContext.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetFrameLowering.h"
35 #include "llvm/Target/TargetLowering.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetSubtargetInfo.h"
40 #define DEBUG_TYPE "legalizedag"
42 //===----------------------------------------------------------------------===//
43 /// This takes an arbitrary SelectionDAG as input and
44 /// hacks on it until the target machine can handle it. This involves
45 /// eliminating value sizes the machine cannot handle (promoting small sizes to
46 /// large sizes or splitting up large values into small values) as well as
47 /// eliminating operations the machine cannot handle.
49 /// This code also does a small amount of optimization and recognition of idioms
50 /// as part of its processing. For example, if a target does not support a
51 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
52 /// will attempt merge setcc and brc instructions into brcc's.
55 class SelectionDAGLegalize {
56 const TargetMachine &TM;
57 const TargetLowering &TLI;
60 /// \brief The set of nodes which have already been legalized. We hold a
61 /// reference to it in order to update as necessary on node deletion.
62 SmallPtrSetImpl<SDNode *> &LegalizedNodes;
64 /// \brief A set of all the nodes updated during legalization.
65 SmallSetVector<SDNode *, 16> *UpdatedNodes;
67 EVT getSetCCResultType(EVT VT) const {
68 return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
71 // Libcall insertion helpers.
74 SelectionDAGLegalize(SelectionDAG &DAG,
75 SmallPtrSetImpl<SDNode *> &LegalizedNodes,
76 SmallSetVector<SDNode *, 16> *UpdatedNodes = nullptr)
77 : TM(DAG.getTarget()), TLI(DAG.getTargetLoweringInfo()), DAG(DAG),
78 LegalizedNodes(LegalizedNodes), UpdatedNodes(UpdatedNodes) {}
80 /// \brief Legalizes the given operation.
81 void LegalizeOp(SDNode *Node);
84 SDValue OptimizeFloatStore(StoreSDNode *ST);
86 void LegalizeLoadOps(SDNode *Node);
87 void LegalizeStoreOps(SDNode *Node);
89 /// Some targets cannot handle a variable
90 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
91 /// is necessary to spill the vector being inserted into to memory, perform
92 /// the insert there, and then read the result back.
93 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
94 SDValue Idx, SDLoc dl);
95 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
96 SDValue Idx, SDLoc dl);
98 /// Return a vector shuffle operation which
99 /// performs the same shuffe in terms of order or result bytes, but on a type
100 /// whose vector element type is narrower than the original shuffle type.
101 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
102 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl,
103 SDValue N1, SDValue N2,
104 ArrayRef<int> Mask) const;
106 bool LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
107 bool &NeedInvert, SDLoc dl);
109 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
110 SDValue ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops,
111 unsigned NumOps, bool isSigned, SDLoc dl);
113 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
114 SDNode *Node, bool isSigned);
115 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
116 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
117 RTLIB::Libcall Call_F128,
118 RTLIB::Libcall Call_PPCF128);
119 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
120 RTLIB::Libcall Call_I8,
121 RTLIB::Libcall Call_I16,
122 RTLIB::Libcall Call_I32,
123 RTLIB::Libcall Call_I64,
124 RTLIB::Libcall Call_I128);
125 void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
126 void ExpandSinCosLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
128 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, SDLoc dl);
129 SDValue ExpandBUILD_VECTOR(SDNode *Node);
130 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
131 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
132 SmallVectorImpl<SDValue> &Results);
133 SDValue ExpandFCOPYSIGN(SDNode *Node);
134 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
136 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
138 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
141 SDValue ExpandBSWAP(SDValue Op, SDLoc dl);
142 SDValue ExpandBitCount(unsigned Opc, SDValue Op, SDLoc dl);
144 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
145 SDValue ExpandInsertToVectorThroughStack(SDValue Op);
146 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
148 SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP);
150 std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node);
152 void ExpandNode(SDNode *Node);
153 void PromoteNode(SDNode *Node);
156 // Node replacement helpers
157 void ReplacedNode(SDNode *N) {
158 LegalizedNodes.erase(N);
160 UpdatedNodes->insert(N);
162 void ReplaceNode(SDNode *Old, SDNode *New) {
163 DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
164 dbgs() << " with: "; New->dump(&DAG));
166 assert(Old->getNumValues() == New->getNumValues() &&
167 "Replacing one node with another that produces a different number "
169 DAG.ReplaceAllUsesWith(Old, New);
170 for (unsigned i = 0, e = Old->getNumValues(); i != e; ++i)
171 DAG.TransferDbgValues(SDValue(Old, i), SDValue(New, i));
173 UpdatedNodes->insert(New);
176 void ReplaceNode(SDValue Old, SDValue New) {
177 DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
178 dbgs() << " with: "; New->dump(&DAG));
180 DAG.ReplaceAllUsesWith(Old, New);
181 DAG.TransferDbgValues(Old, New);
183 UpdatedNodes->insert(New.getNode());
184 ReplacedNode(Old.getNode());
186 void ReplaceNode(SDNode *Old, const SDValue *New) {
187 DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG));
189 DAG.ReplaceAllUsesWith(Old, New);
190 for (unsigned i = 0, e = Old->getNumValues(); i != e; ++i) {
191 DEBUG(dbgs() << (i == 0 ? " with: "
194 DAG.TransferDbgValues(SDValue(Old, i), New[i]);
196 UpdatedNodes->insert(New[i].getNode());
203 /// Return a vector shuffle operation which
204 /// performs the same shuffe in terms of order or result bytes, but on a type
205 /// whose vector element type is narrower than the original shuffle type.
206 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
208 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl,
209 SDValue N1, SDValue N2,
210 ArrayRef<int> Mask) const {
211 unsigned NumMaskElts = VT.getVectorNumElements();
212 unsigned NumDestElts = NVT.getVectorNumElements();
213 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
215 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
217 if (NumEltsGrowth == 1)
218 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
220 SmallVector<int, 8> NewMask;
221 for (unsigned i = 0; i != NumMaskElts; ++i) {
223 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
225 NewMask.push_back(-1);
227 NewMask.push_back(Idx * NumEltsGrowth + j);
230 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
231 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
232 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
235 /// Expands the ConstantFP node to an integer constant or
236 /// a load from the constant pool.
238 SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) {
242 // If a FP immediate is precise when represented as a float and if the
243 // target can do an extending load from float to double, we put it into
244 // the constant pool as a float, even if it's is statically typed as a
245 // double. This shrinks FP constants and canonicalizes them for targets where
246 // an FP extending load is the same cost as a normal load (such as on the x87
247 // fp stack or PPC FP unit).
248 EVT VT = CFP->getValueType(0);
249 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
251 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
252 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(), dl,
253 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
258 while (SVT != MVT::f32 && SVT != MVT::f16) {
259 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
260 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) &&
261 // Only do this if the target has a native EXTLOAD instruction from
263 TLI.isLoadExtLegal(ISD::EXTLOAD, OrigVT, SVT) &&
264 TLI.ShouldShrinkFPConstant(OrigVT)) {
265 Type *SType = SVT.getTypeForEVT(*DAG.getContext());
266 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
273 DAG.getConstantPool(LLVMC, TLI.getPointerTy(DAG.getDataLayout()));
274 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
277 DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT,
279 CPIdx, MachinePointerInfo::getConstantPool(),
280 VT, false, false, false, Alignment);
284 DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
285 MachinePointerInfo::getConstantPool(), false, false, false,
290 /// Expands an unaligned store to 2 half-size stores.
291 static void ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
292 const TargetLowering &TLI,
293 SelectionDAGLegalize *DAGLegalize) {
294 assert(ST->getAddressingMode() == ISD::UNINDEXED &&
295 "unaligned indexed stores not implemented!");
296 SDValue Chain = ST->getChain();
297 SDValue Ptr = ST->getBasePtr();
298 SDValue Val = ST->getValue();
299 EVT VT = Val.getValueType();
300 int Alignment = ST->getAlignment();
301 unsigned AS = ST->getAddressSpace();
304 if (ST->getMemoryVT().isFloatingPoint() ||
305 ST->getMemoryVT().isVector()) {
306 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
307 if (TLI.isTypeLegal(intVT)) {
308 // Expand to a bitconvert of the value to the integer type of the
309 // same size, then a (misaligned) int store.
310 // FIXME: Does not handle truncating floating point stores!
311 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
312 Result = DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
313 ST->isVolatile(), ST->isNonTemporal(), Alignment);
314 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
317 // Do a (aligned) store to a stack slot, then copy from the stack slot
318 // to the final destination using (unaligned) integer loads and stores.
319 EVT StoredVT = ST->getMemoryVT();
321 TLI.getRegisterType(*DAG.getContext(),
322 EVT::getIntegerVT(*DAG.getContext(),
323 StoredVT.getSizeInBits()));
324 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
325 unsigned RegBytes = RegVT.getSizeInBits() / 8;
326 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
328 // Make sure the stack slot is also aligned for the register type.
329 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
331 // Perform the original store, only redirected to the stack slot.
332 SDValue Store = DAG.getTruncStore(Chain, dl,
333 Val, StackPtr, MachinePointerInfo(),
334 StoredVT, false, false, 0);
335 SDValue Increment = DAG.getConstant(
336 RegBytes, dl, TLI.getPointerTy(DAG.getDataLayout(), AS));
337 SmallVector<SDValue, 8> Stores;
340 // Do all but one copies using the full register width.
341 for (unsigned i = 1; i < NumRegs; i++) {
342 // Load one integer register's worth from the stack slot.
343 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr,
344 MachinePointerInfo(),
345 false, false, false, 0);
346 // Store it to the final location. Remember the store.
347 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
348 ST->getPointerInfo().getWithOffset(Offset),
349 ST->isVolatile(), ST->isNonTemporal(),
350 MinAlign(ST->getAlignment(), Offset)));
351 // Increment the pointers.
353 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
355 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
358 // The last store may be partial. Do a truncating store. On big-endian
359 // machines this requires an extending load from the stack slot to ensure
360 // that the bits are in the right place.
361 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
362 8 * (StoredBytes - Offset));
364 // Load from the stack slot.
365 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
366 MachinePointerInfo(),
367 MemVT, false, false, false, 0);
369 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
371 .getWithOffset(Offset),
372 MemVT, ST->isVolatile(),
374 MinAlign(ST->getAlignment(), Offset),
376 // The order of the stores doesn't matter - say it with a TokenFactor.
377 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
378 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
381 assert(ST->getMemoryVT().isInteger() &&
382 !ST->getMemoryVT().isVector() &&
383 "Unaligned store of unknown type.");
384 // Get the half-size VT
385 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext());
386 int NumBits = NewStoredVT.getSizeInBits();
387 int IncrementSize = NumBits / 8;
389 // Divide the stored value in two parts.
390 SDValue ShiftAmount =
391 DAG.getConstant(NumBits, dl, TLI.getShiftAmountTy(Val.getValueType(),
392 DAG.getDataLayout()));
394 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
396 // Store the two parts
397 SDValue Store1, Store2;
398 Store1 = DAG.getTruncStore(Chain, dl,
399 DAG.getDataLayout().isLittleEndian() ? Lo : Hi,
400 Ptr, ST->getPointerInfo(), NewStoredVT,
401 ST->isVolatile(), ST->isNonTemporal(), Alignment);
403 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
404 DAG.getConstant(IncrementSize, dl,
405 TLI.getPointerTy(DAG.getDataLayout(), AS)));
406 Alignment = MinAlign(Alignment, IncrementSize);
407 Store2 = DAG.getTruncStore(
408 Chain, dl, DAG.getDataLayout().isLittleEndian() ? Hi : Lo, Ptr,
409 ST->getPointerInfo().getWithOffset(IncrementSize), NewStoredVT,
410 ST->isVolatile(), ST->isNonTemporal(), Alignment, ST->getAAInfo());
413 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
414 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
417 /// Expands an unaligned load to 2 half-size loads.
419 ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
420 const TargetLowering &TLI,
421 SDValue &ValResult, SDValue &ChainResult) {
422 assert(LD->getAddressingMode() == ISD::UNINDEXED &&
423 "unaligned indexed loads not implemented!");
424 SDValue Chain = LD->getChain();
425 SDValue Ptr = LD->getBasePtr();
426 EVT VT = LD->getValueType(0);
427 EVT LoadedVT = LD->getMemoryVT();
429 if (VT.isFloatingPoint() || VT.isVector()) {
430 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
431 if (TLI.isTypeLegal(intVT) && TLI.isTypeLegal(LoadedVT)) {
432 // Expand to a (misaligned) integer load of the same size,
433 // then bitconvert to floating point or vector.
434 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr,
435 LD->getMemOperand());
436 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad);
438 Result = DAG.getNode(VT.isFloatingPoint() ? ISD::FP_EXTEND :
439 ISD::ANY_EXTEND, dl, VT, Result);
446 // Copy the value to a (aligned) stack slot using (unaligned) integer
447 // loads and stores, then do a (aligned) load from the stack slot.
448 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
449 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
450 unsigned RegBytes = RegVT.getSizeInBits() / 8;
451 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
453 // Make sure the stack slot is also aligned for the register type.
454 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
457 DAG.getConstant(RegBytes, dl, TLI.getPointerTy(DAG.getDataLayout()));
458 SmallVector<SDValue, 8> Stores;
459 SDValue StackPtr = StackBase;
462 // Do all but one copies using the full register width.
463 for (unsigned i = 1; i < NumRegs; i++) {
464 // Load one integer register's worth from the original location.
465 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr,
466 LD->getPointerInfo().getWithOffset(Offset),
467 LD->isVolatile(), LD->isNonTemporal(),
469 MinAlign(LD->getAlignment(), Offset),
471 // Follow the load with a store to the stack slot. Remember the store.
472 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
473 MachinePointerInfo(), false, false, 0));
474 // Increment the pointers.
476 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
477 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
481 // The last copy may be partial. Do an extending load.
482 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
483 8 * (LoadedBytes - Offset));
484 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
485 LD->getPointerInfo().getWithOffset(Offset),
486 MemVT, LD->isVolatile(),
489 MinAlign(LD->getAlignment(), Offset),
491 // Follow the load with a store to the stack slot. Remember the store.
492 // On big-endian machines this requires a truncating store to ensure
493 // that the bits end up in the right place.
494 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
495 MachinePointerInfo(), MemVT,
498 // The order of the stores doesn't matter - say it with a TokenFactor.
499 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
501 // Finally, perform the original load only redirected to the stack slot.
502 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
503 MachinePointerInfo(), LoadedVT, false,false, false,
506 // Callers expect a MERGE_VALUES node.
511 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
512 "Unaligned load of unsupported type.");
514 // Compute the new VT that is half the size of the old one. This is an
516 unsigned NumBits = LoadedVT.getSizeInBits();
518 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
521 unsigned Alignment = LD->getAlignment();
522 unsigned IncrementSize = NumBits / 8;
523 ISD::LoadExtType HiExtType = LD->getExtensionType();
525 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
526 if (HiExtType == ISD::NON_EXTLOAD)
527 HiExtType = ISD::ZEXTLOAD;
529 // Load the value in two parts
531 if (DAG.getDataLayout().isLittleEndian()) {
532 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
533 NewLoadedVT, LD->isVolatile(),
534 LD->isNonTemporal(), LD->isInvariant(), Alignment,
536 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
537 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
538 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr,
539 LD->getPointerInfo().getWithOffset(IncrementSize),
540 NewLoadedVT, LD->isVolatile(),
541 LD->isNonTemporal(),LD->isInvariant(),
542 MinAlign(Alignment, IncrementSize), LD->getAAInfo());
544 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(),
545 NewLoadedVT, LD->isVolatile(),
546 LD->isNonTemporal(), LD->isInvariant(), Alignment,
548 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
549 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
550 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
551 LD->getPointerInfo().getWithOffset(IncrementSize),
552 NewLoadedVT, LD->isVolatile(),
553 LD->isNonTemporal(), LD->isInvariant(),
554 MinAlign(Alignment, IncrementSize), LD->getAAInfo());
557 // aggregate the two parts
558 SDValue ShiftAmount =
559 DAG.getConstant(NumBits, dl, TLI.getShiftAmountTy(Hi.getValueType(),
560 DAG.getDataLayout()));
561 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
562 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
564 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
571 /// Some target cannot handle a variable insertion index for the
572 /// INSERT_VECTOR_ELT instruction. In this case, it
573 /// is necessary to spill the vector being inserted into to memory, perform
574 /// the insert there, and then read the result back.
575 SDValue SelectionDAGLegalize::
576 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
582 // If the target doesn't support this, we have to spill the input vector
583 // to a temporary stack slot, update the element, then reload it. This is
584 // badness. We could also load the value into a vector register (either
585 // with a "move to register" or "extload into register" instruction, then
586 // permute it into place, if the idx is a constant and if the idx is
587 // supported by the target.
588 EVT VT = Tmp1.getValueType();
589 EVT EltVT = VT.getVectorElementType();
590 EVT IdxVT = Tmp3.getValueType();
591 EVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
592 SDValue StackPtr = DAG.CreateStackTemporary(VT);
594 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
597 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
598 MachinePointerInfo::getFixedStack(SPFI),
601 // Truncate or zero extend offset to target pointer type.
602 Tmp3 = DAG.getZExtOrTrunc(Tmp3, dl, PtrVT);
603 // Add the offset to the index.
604 unsigned EltSize = EltVT.getSizeInBits()/8;
605 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,
606 DAG.getConstant(EltSize, dl, IdxVT));
607 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
608 // Store the scalar value.
609 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT,
611 // Load the updated vector.
612 return DAG.getLoad(VT, dl, Ch, StackPtr,
613 MachinePointerInfo::getFixedStack(SPFI), false, false,
618 SDValue SelectionDAGLegalize::
619 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, SDLoc dl) {
620 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
621 // SCALAR_TO_VECTOR requires that the type of the value being inserted
622 // match the element type of the vector being created, except for
623 // integers in which case the inserted value can be over width.
624 EVT EltVT = Vec.getValueType().getVectorElementType();
625 if (Val.getValueType() == EltVT ||
626 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
627 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
628 Vec.getValueType(), Val);
630 unsigned NumElts = Vec.getValueType().getVectorNumElements();
631 // We generate a shuffle of InVec and ScVec, so the shuffle mask
632 // should be 0,1,2,3,4,5... with the appropriate element replaced with
634 SmallVector<int, 8> ShufOps;
635 for (unsigned i = 0; i != NumElts; ++i)
636 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
638 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
642 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
645 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
646 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
647 // FIXME: We shouldn't do this for TargetConstantFP's.
648 // FIXME: move this to the DAG Combiner! Note that we can't regress due
649 // to phase ordering between legalized code and the dag combiner. This
650 // probably means that we need to integrate dag combiner and legalizer
652 // We generally can't do this one for long doubles.
653 SDValue Chain = ST->getChain();
654 SDValue Ptr = ST->getBasePtr();
655 unsigned Alignment = ST->getAlignment();
656 bool isVolatile = ST->isVolatile();
657 bool isNonTemporal = ST->isNonTemporal();
658 AAMDNodes AAInfo = ST->getAAInfo();
660 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
661 if (CFP->getValueType(0) == MVT::f32 &&
662 TLI.isTypeLegal(MVT::i32)) {
663 SDValue Con = DAG.getConstant(CFP->getValueAPF().
664 bitcastToAPInt().zextOrTrunc(32),
665 SDLoc(CFP), MVT::i32);
666 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
667 isVolatile, isNonTemporal, Alignment, AAInfo);
670 if (CFP->getValueType(0) == MVT::f64) {
671 // If this target supports 64-bit registers, do a single 64-bit store.
672 if (TLI.isTypeLegal(MVT::i64)) {
673 SDValue Con = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
674 zextOrTrunc(64), SDLoc(CFP), MVT::i64);
675 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
676 isVolatile, isNonTemporal, Alignment, AAInfo);
679 if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) {
680 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
681 // stores. If the target supports neither 32- nor 64-bits, this
682 // xform is certainly not worth it.
683 const APInt &IntVal = CFP->getValueAPF().bitcastToAPInt();
684 SDValue Lo = DAG.getConstant(IntVal.trunc(32), dl, MVT::i32);
685 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), dl, MVT::i32);
686 if (DAG.getDataLayout().isBigEndian())
689 Lo = DAG.getStore(Chain, dl, Lo, Ptr, ST->getPointerInfo(), isVolatile,
690 isNonTemporal, Alignment, AAInfo);
691 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
692 DAG.getConstant(4, dl, Ptr.getValueType()));
693 Hi = DAG.getStore(Chain, dl, Hi, Ptr,
694 ST->getPointerInfo().getWithOffset(4),
695 isVolatile, isNonTemporal, MinAlign(Alignment, 4U),
698 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
702 return SDValue(nullptr, 0);
705 void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
706 StoreSDNode *ST = cast<StoreSDNode>(Node);
707 SDValue Chain = ST->getChain();
708 SDValue Ptr = ST->getBasePtr();
711 unsigned Alignment = ST->getAlignment();
712 bool isVolatile = ST->isVolatile();
713 bool isNonTemporal = ST->isNonTemporal();
714 AAMDNodes AAInfo = ST->getAAInfo();
716 if (!ST->isTruncatingStore()) {
717 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
718 ReplaceNode(ST, OptStore);
723 SDValue Value = ST->getValue();
724 MVT VT = Value.getSimpleValueType();
725 switch (TLI.getOperationAction(ISD::STORE, VT)) {
726 default: llvm_unreachable("This action is not supported yet!");
727 case TargetLowering::Legal: {
728 // If this is an unaligned store and the target doesn't support it,
730 EVT MemVT = ST->getMemoryVT();
731 unsigned AS = ST->getAddressSpace();
732 unsigned Align = ST->getAlignment();
733 const DataLayout &DL = DAG.getDataLayout();
734 if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align))
735 ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this);
738 case TargetLowering::Custom: {
739 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
740 if (Res && Res != SDValue(Node, 0))
741 ReplaceNode(SDValue(Node, 0), Res);
744 case TargetLowering::Promote: {
745 MVT NVT = TLI.getTypeToPromoteTo(ISD::STORE, VT);
746 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
747 "Can only promote stores to same size type");
748 Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value);
750 DAG.getStore(Chain, dl, Value, Ptr,
751 ST->getPointerInfo(), isVolatile,
752 isNonTemporal, Alignment, AAInfo);
753 ReplaceNode(SDValue(Node, 0), Result);
760 SDValue Value = ST->getValue();
762 EVT StVT = ST->getMemoryVT();
763 unsigned StWidth = StVT.getSizeInBits();
764 auto &DL = DAG.getDataLayout();
766 if (StWidth != StVT.getStoreSizeInBits()) {
767 // Promote to a byte-sized store with upper bits zero if not
768 // storing an integral number of bytes. For example, promote
769 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
770 EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
771 StVT.getStoreSizeInBits());
772 Value = DAG.getZeroExtendInReg(Value, dl, StVT);
774 DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
775 NVT, isVolatile, isNonTemporal, Alignment, AAInfo);
776 ReplaceNode(SDValue(Node, 0), Result);
777 } else if (StWidth & (StWidth - 1)) {
778 // If not storing a power-of-2 number of bits, expand as two stores.
779 assert(!StVT.isVector() && "Unsupported truncstore!");
780 unsigned RoundWidth = 1 << Log2_32(StWidth);
781 assert(RoundWidth < StWidth);
782 unsigned ExtraWidth = StWidth - RoundWidth;
783 assert(ExtraWidth < RoundWidth);
784 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
785 "Store size not an integral number of bytes!");
786 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
787 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
789 unsigned IncrementSize;
791 if (DL.isLittleEndian()) {
792 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
793 // Store the bottom RoundWidth bits.
794 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
796 isVolatile, isNonTemporal, Alignment,
799 // Store the remaining ExtraWidth bits.
800 IncrementSize = RoundWidth / 8;
801 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
802 DAG.getConstant(IncrementSize, dl,
803 Ptr.getValueType()));
805 ISD::SRL, dl, Value.getValueType(), Value,
806 DAG.getConstant(RoundWidth, dl,
807 TLI.getShiftAmountTy(Value.getValueType(), DL)));
808 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr,
809 ST->getPointerInfo().getWithOffset(IncrementSize),
810 ExtraVT, isVolatile, isNonTemporal,
811 MinAlign(Alignment, IncrementSize), AAInfo);
813 // Big endian - avoid unaligned stores.
814 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
815 // Store the top RoundWidth bits.
817 ISD::SRL, dl, Value.getValueType(), Value,
818 DAG.getConstant(ExtraWidth, dl,
819 TLI.getShiftAmountTy(Value.getValueType(), DL)));
820 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, ST->getPointerInfo(),
821 RoundVT, isVolatile, isNonTemporal, Alignment,
824 // Store the remaining ExtraWidth bits.
825 IncrementSize = RoundWidth / 8;
826 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
827 DAG.getConstant(IncrementSize, dl,
828 Ptr.getValueType()));
829 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr,
830 ST->getPointerInfo().getWithOffset(IncrementSize),
831 ExtraVT, isVolatile, isNonTemporal,
832 MinAlign(Alignment, IncrementSize), AAInfo);
835 // The order of the stores doesn't matter.
836 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
837 ReplaceNode(SDValue(Node, 0), Result);
839 switch (TLI.getTruncStoreAction(ST->getValue().getSimpleValueType(),
840 StVT.getSimpleVT())) {
841 default: llvm_unreachable("This action is not supported yet!");
842 case TargetLowering::Legal: {
843 EVT MemVT = ST->getMemoryVT();
844 unsigned AS = ST->getAddressSpace();
845 unsigned Align = ST->getAlignment();
846 // If this is an unaligned store and the target doesn't support it,
848 if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align))
849 ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this);
852 case TargetLowering::Custom: {
853 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
854 if (Res && Res != SDValue(Node, 0))
855 ReplaceNode(SDValue(Node, 0), Res);
858 case TargetLowering::Expand:
859 assert(!StVT.isVector() &&
860 "Vector Stores are handled in LegalizeVectorOps");
862 // TRUNCSTORE:i16 i32 -> STORE i16
863 assert(TLI.isTypeLegal(StVT) &&
864 "Do not know how to expand this store!");
865 Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value);
867 DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
868 isVolatile, isNonTemporal, Alignment, AAInfo);
869 ReplaceNode(SDValue(Node, 0), Result);
876 void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
877 LoadSDNode *LD = cast<LoadSDNode>(Node);
878 SDValue Chain = LD->getChain(); // The chain.
879 SDValue Ptr = LD->getBasePtr(); // The base pointer.
880 SDValue Value; // The value returned by the load op.
883 ISD::LoadExtType ExtType = LD->getExtensionType();
884 if (ExtType == ISD::NON_EXTLOAD) {
885 MVT VT = Node->getSimpleValueType(0);
886 SDValue RVal = SDValue(Node, 0);
887 SDValue RChain = SDValue(Node, 1);
889 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
890 default: llvm_unreachable("This action is not supported yet!");
891 case TargetLowering::Legal: {
892 EVT MemVT = LD->getMemoryVT();
893 unsigned AS = LD->getAddressSpace();
894 unsigned Align = LD->getAlignment();
895 const DataLayout &DL = DAG.getDataLayout();
896 // If this is an unaligned load and the target doesn't support it,
898 if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align))
899 ExpandUnalignedLoad(cast<LoadSDNode>(Node), DAG, TLI, RVal, RChain);
902 case TargetLowering::Custom: {
903 SDValue Res = TLI.LowerOperation(RVal, DAG);
906 RChain = Res.getValue(1);
910 case TargetLowering::Promote: {
911 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
912 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
913 "Can only promote loads to same size type");
915 SDValue Res = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getMemOperand());
916 RVal = DAG.getNode(ISD::BITCAST, dl, VT, Res);
917 RChain = Res.getValue(1);
921 if (RChain.getNode() != Node) {
922 assert(RVal.getNode() != Node && "Load must be completely replaced");
923 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), RVal);
924 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), RChain);
926 UpdatedNodes->insert(RVal.getNode());
927 UpdatedNodes->insert(RChain.getNode());
934 EVT SrcVT = LD->getMemoryVT();
935 unsigned SrcWidth = SrcVT.getSizeInBits();
936 unsigned Alignment = LD->getAlignment();
937 bool isVolatile = LD->isVolatile();
938 bool isNonTemporal = LD->isNonTemporal();
939 bool isInvariant = LD->isInvariant();
940 AAMDNodes AAInfo = LD->getAAInfo();
942 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
943 // Some targets pretend to have an i1 loading operation, and actually
944 // load an i8. This trick is correct for ZEXTLOAD because the top 7
945 // bits are guaranteed to be zero; it helps the optimizers understand
946 // that these bits are zero. It is also useful for EXTLOAD, since it
947 // tells the optimizers that those bits are undefined. It would be
948 // nice to have an effective generic way of getting these benefits...
949 // Until such a way is found, don't insist on promoting i1 here.
951 TLI.getLoadExtAction(ExtType, Node->getValueType(0), MVT::i1) ==
952 TargetLowering::Promote)) {
953 // Promote to a byte-sized load if not loading an integral number of
954 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
955 unsigned NewWidth = SrcVT.getStoreSizeInBits();
956 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
959 // The extra bits are guaranteed to be zero, since we stored them that
960 // way. A zext load from NVT thus automatically gives zext from SrcVT.
962 ISD::LoadExtType NewExtType =
963 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
966 DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
967 Chain, Ptr, LD->getPointerInfo(),
968 NVT, isVolatile, isNonTemporal, isInvariant, Alignment,
971 Ch = Result.getValue(1); // The chain.
973 if (ExtType == ISD::SEXTLOAD)
974 // Having the top bits zero doesn't help when sign extending.
975 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
976 Result.getValueType(),
977 Result, DAG.getValueType(SrcVT));
978 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
979 // All the top bits are guaranteed to be zero - inform the optimizers.
980 Result = DAG.getNode(ISD::AssertZext, dl,
981 Result.getValueType(), Result,
982 DAG.getValueType(SrcVT));
986 } else if (SrcWidth & (SrcWidth - 1)) {
987 // If not loading a power-of-2 number of bits, expand as two loads.
988 assert(!SrcVT.isVector() && "Unsupported extload!");
989 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
990 assert(RoundWidth < SrcWidth);
991 unsigned ExtraWidth = SrcWidth - RoundWidth;
992 assert(ExtraWidth < RoundWidth);
993 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
994 "Load size not an integral number of bytes!");
995 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
996 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
998 unsigned IncrementSize;
999 auto &DL = DAG.getDataLayout();
1001 if (DL.isLittleEndian()) {
1002 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1003 // Load the bottom RoundWidth bits.
1004 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0),
1006 LD->getPointerInfo(), RoundVT, isVolatile,
1007 isNonTemporal, isInvariant, Alignment, AAInfo);
1009 // Load the remaining ExtraWidth bits.
1010 IncrementSize = RoundWidth / 8;
1011 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1012 DAG.getConstant(IncrementSize, dl,
1013 Ptr.getValueType()));
1014 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
1015 LD->getPointerInfo().getWithOffset(IncrementSize),
1016 ExtraVT, isVolatile, isNonTemporal, isInvariant,
1017 MinAlign(Alignment, IncrementSize), AAInfo);
1019 // Build a factor node to remember that this load is independent of
1021 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1024 // Move the top bits to the right place.
1026 ISD::SHL, dl, Hi.getValueType(), Hi,
1027 DAG.getConstant(RoundWidth, dl,
1028 TLI.getShiftAmountTy(Hi.getValueType(), DL)));
1030 // Join the hi and lo parts.
1031 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1033 // Big endian - avoid unaligned loads.
1034 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1035 // Load the top RoundWidth bits.
1036 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
1037 LD->getPointerInfo(), RoundVT, isVolatile,
1038 isNonTemporal, isInvariant, Alignment, AAInfo);
1040 // Load the remaining ExtraWidth bits.
1041 IncrementSize = RoundWidth / 8;
1042 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1043 DAG.getConstant(IncrementSize, dl,
1044 Ptr.getValueType()));
1045 Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
1046 dl, Node->getValueType(0), Chain, Ptr,
1047 LD->getPointerInfo().getWithOffset(IncrementSize),
1048 ExtraVT, isVolatile, isNonTemporal, isInvariant,
1049 MinAlign(Alignment, IncrementSize), AAInfo);
1051 // Build a factor node to remember that this load is independent of
1053 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1056 // Move the top bits to the right place.
1058 ISD::SHL, dl, Hi.getValueType(), Hi,
1059 DAG.getConstant(ExtraWidth, dl,
1060 TLI.getShiftAmountTy(Hi.getValueType(), DL)));
1062 // Join the hi and lo parts.
1063 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1068 bool isCustom = false;
1069 switch (TLI.getLoadExtAction(ExtType, Node->getValueType(0),
1070 SrcVT.getSimpleVT())) {
1071 default: llvm_unreachable("This action is not supported yet!");
1072 case TargetLowering::Custom:
1075 case TargetLowering::Legal: {
1076 Value = SDValue(Node, 0);
1077 Chain = SDValue(Node, 1);
1080 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1081 if (Res.getNode()) {
1083 Chain = Res.getValue(1);
1086 // If this is an unaligned load and the target doesn't support it,
1088 EVT MemVT = LD->getMemoryVT();
1089 unsigned AS = LD->getAddressSpace();
1090 unsigned Align = LD->getAlignment();
1091 const DataLayout &DL = DAG.getDataLayout();
1092 if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align))
1093 ExpandUnalignedLoad(cast<LoadSDNode>(Node), DAG, TLI, Value, Chain);
1097 case TargetLowering::Expand:
1098 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, Node->getValueType(0), SrcVT)) {
1099 // If the source type is not legal, see if there is a legal extload to
1100 // an intermediate type that we can then extend further.
1101 EVT LoadVT = TLI.getRegisterType(SrcVT.getSimpleVT());
1102 if (TLI.isTypeLegal(SrcVT) || // Same as SrcVT == LoadVT?
1103 TLI.isLoadExtLegal(ExtType, LoadVT, SrcVT)) {
1104 // If we are loading a legal type, this is a non-extload followed by a
1106 ISD::LoadExtType MidExtType =
1107 (LoadVT == SrcVT) ? ISD::NON_EXTLOAD : ExtType;
1109 SDValue Load = DAG.getExtLoad(MidExtType, dl, LoadVT, Chain, Ptr,
1110 SrcVT, LD->getMemOperand());
1112 ISD::getExtForLoadExtType(SrcVT.isFloatingPoint(), ExtType);
1113 Value = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
1114 Chain = Load.getValue(1);
1119 assert(!SrcVT.isVector() &&
1120 "Vector Loads are handled in LegalizeVectorOps");
1122 // FIXME: This does not work for vectors on most targets. Sign-
1123 // and zero-extend operations are currently folded into extending
1124 // loads, whether they are legal or not, and then we end up here
1125 // without any support for legalizing them.
1126 assert(ExtType != ISD::EXTLOAD &&
1127 "EXTLOAD should always be supported!");
1128 // Turn the unsupported load into an EXTLOAD followed by an
1129 // explicit zero/sign extend inreg.
1130 SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl,
1131 Node->getValueType(0),
1133 LD->getMemOperand());
1135 if (ExtType == ISD::SEXTLOAD)
1136 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1137 Result.getValueType(),
1138 Result, DAG.getValueType(SrcVT));
1140 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType());
1142 Chain = Result.getValue(1);
1147 // Since loads produce two values, make sure to remember that we legalized
1149 if (Chain.getNode() != Node) {
1150 assert(Value.getNode() != Node && "Load must be completely replaced");
1151 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Value);
1152 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
1154 UpdatedNodes->insert(Value.getNode());
1155 UpdatedNodes->insert(Chain.getNode());
1161 /// Return a legal replacement for the given operation, with all legal operands.
1162 void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
1163 DEBUG(dbgs() << "\nLegalizing: "; Node->dump(&DAG));
1165 if (Node->getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
1169 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1170 assert(TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) ==
1171 TargetLowering::TypeLegal &&
1172 "Unexpected illegal type!");
1174 for (const SDValue &Op : Node->op_values())
1175 assert((TLI.getTypeAction(*DAG.getContext(),
1176 Op.getValueType()) == TargetLowering::TypeLegal ||
1177 Op.getOpcode() == ISD::TargetConstant) &&
1178 "Unexpected illegal type!");
1181 // Figure out the correct action; the way to query this varies by opcode
1182 TargetLowering::LegalizeAction Action = TargetLowering::Legal;
1183 bool SimpleFinishLegalizing = true;
1184 switch (Node->getOpcode()) {
1185 case ISD::INTRINSIC_W_CHAIN:
1186 case ISD::INTRINSIC_WO_CHAIN:
1187 case ISD::INTRINSIC_VOID:
1188 case ISD::STACKSAVE:
1189 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1192 Action = TLI.getOperationAction(Node->getOpcode(),
1193 Node->getValueType(0));
1194 if (Action != TargetLowering::Promote)
1195 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1197 case ISD::FP_TO_FP16:
1198 case ISD::SINT_TO_FP:
1199 case ISD::UINT_TO_FP:
1200 case ISD::EXTRACT_VECTOR_ELT:
1201 Action = TLI.getOperationAction(Node->getOpcode(),
1202 Node->getOperand(0).getValueType());
1204 case ISD::FP_ROUND_INREG:
1205 case ISD::SIGN_EXTEND_INREG: {
1206 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
1207 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
1210 case ISD::ATOMIC_STORE: {
1211 Action = TLI.getOperationAction(Node->getOpcode(),
1212 Node->getOperand(2).getValueType());
1215 case ISD::SELECT_CC:
1218 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
1219 Node->getOpcode() == ISD::SETCC ? 2 : 1;
1220 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
1221 MVT OpVT = Node->getOperand(CompareOperand).getSimpleValueType();
1222 ISD::CondCode CCCode =
1223 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
1224 Action = TLI.getCondCodeAction(CCCode, OpVT);
1225 if (Action == TargetLowering::Legal) {
1226 if (Node->getOpcode() == ISD::SELECT_CC)
1227 Action = TLI.getOperationAction(Node->getOpcode(),
1228 Node->getValueType(0));
1230 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
1236 // FIXME: Model these properly. LOAD and STORE are complicated, and
1237 // STORE expects the unlegalized operand in some cases.
1238 SimpleFinishLegalizing = false;
1240 case ISD::CALLSEQ_START:
1241 case ISD::CALLSEQ_END:
1242 // FIXME: This shouldn't be necessary. These nodes have special properties
1243 // dealing with the recursive nature of legalization. Removing this
1244 // special case should be done as part of making LegalizeDAG non-recursive.
1245 SimpleFinishLegalizing = false;
1247 case ISD::EXTRACT_ELEMENT:
1248 case ISD::FLT_ROUNDS_:
1250 case ISD::MERGE_VALUES:
1251 case ISD::EH_RETURN:
1252 case ISD::FRAME_TO_ARGS_OFFSET:
1253 case ISD::EH_SJLJ_SETJMP:
1254 case ISD::EH_SJLJ_LONGJMP:
1255 case ISD::EH_SJLJ_SETUP_DISPATCH:
1256 // These operations lie about being legal: when they claim to be legal,
1257 // they should actually be expanded.
1258 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1259 if (Action == TargetLowering::Legal)
1260 Action = TargetLowering::Expand;
1262 case ISD::INIT_TRAMPOLINE:
1263 case ISD::ADJUST_TRAMPOLINE:
1264 case ISD::FRAMEADDR:
1265 case ISD::RETURNADDR:
1266 // These operations lie about being legal: when they claim to be legal,
1267 // they should actually be custom-lowered.
1268 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1269 if (Action == TargetLowering::Legal)
1270 Action = TargetLowering::Custom;
1272 case ISD::READ_REGISTER:
1273 case ISD::WRITE_REGISTER:
1274 // Named register is legal in the DAG, but blocked by register name
1275 // selection if not implemented by target (to chose the correct register)
1276 // They'll be converted to Copy(To/From)Reg.
1277 Action = TargetLowering::Legal;
1279 case ISD::DEBUGTRAP:
1280 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1281 if (Action == TargetLowering::Expand) {
1282 // replace ISD::DEBUGTRAP with ISD::TRAP
1284 NewVal = DAG.getNode(ISD::TRAP, SDLoc(Node), Node->getVTList(),
1285 Node->getOperand(0));
1286 ReplaceNode(Node, NewVal.getNode());
1287 LegalizeOp(NewVal.getNode());
1293 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1294 Action = TargetLowering::Legal;
1296 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1301 if (SimpleFinishLegalizing) {
1302 SDNode *NewNode = Node;
1303 switch (Node->getOpcode()) {
1310 // Legalizing shifts/rotates requires adjusting the shift amount
1311 // to the appropriate width.
1312 if (!Node->getOperand(1).getValueType().isVector()) {
1314 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1315 Node->getOperand(1));
1316 HandleSDNode Handle(SAO);
1317 LegalizeOp(SAO.getNode());
1318 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1322 case ISD::SRL_PARTS:
1323 case ISD::SRA_PARTS:
1324 case ISD::SHL_PARTS:
1325 // Legalizing shifts/rotates requires adjusting the shift amount
1326 // to the appropriate width.
1327 if (!Node->getOperand(2).getValueType().isVector()) {
1329 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1330 Node->getOperand(2));
1331 HandleSDNode Handle(SAO);
1332 LegalizeOp(SAO.getNode());
1333 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1334 Node->getOperand(1),
1340 if (NewNode != Node) {
1341 ReplaceNode(Node, NewNode);
1345 case TargetLowering::Legal:
1347 case TargetLowering::Custom: {
1348 // FIXME: The handling for custom lowering with multiple results is
1350 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1351 if (Res.getNode()) {
1352 if (!(Res.getNode() != Node || Res.getResNo() != 0))
1355 if (Node->getNumValues() == 1) {
1356 // We can just directly replace this node with the lowered value.
1357 ReplaceNode(SDValue(Node, 0), Res);
1361 SmallVector<SDValue, 8> ResultVals;
1362 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1363 ResultVals.push_back(Res.getValue(i));
1364 ReplaceNode(Node, ResultVals.data());
1369 case TargetLowering::Expand:
1372 case TargetLowering::Promote:
1378 switch (Node->getOpcode()) {
1385 llvm_unreachable("Do not know how to legalize this operator!");
1387 case ISD::CALLSEQ_START:
1388 case ISD::CALLSEQ_END:
1391 return LegalizeLoadOps(Node);
1394 return LegalizeStoreOps(Node);
1399 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1400 SDValue Vec = Op.getOperand(0);
1401 SDValue Idx = Op.getOperand(1);
1404 // Before we generate a new store to a temporary stack slot, see if there is
1405 // already one that we can use. There often is because when we scalarize
1406 // vector operations (using SelectionDAG::UnrollVectorOp for example) a whole
1407 // series of EXTRACT_VECTOR_ELT nodes are generated, one for each element in
1408 // the vector. If all are expanded here, we don't want one store per vector
1410 SDValue StackPtr, Ch;
1411 for (SDNode::use_iterator UI = Vec.getNode()->use_begin(),
1412 UE = Vec.getNode()->use_end(); UI != UE; ++UI) {
1414 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(User)) {
1415 if (ST->isIndexed() || ST->isTruncatingStore() ||
1416 ST->getValue() != Vec)
1419 // Make sure that nothing else could have stored into the destination of
1421 if (!ST->getChain().reachesChainWithoutSideEffects(DAG.getEntryNode()))
1424 StackPtr = ST->getBasePtr();
1425 Ch = SDValue(ST, 0);
1430 if (!Ch.getNode()) {
1431 // Store the value to a temporary stack slot, then LOAD the returned part.
1432 StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1433 Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1434 MachinePointerInfo(), false, false, 0);
1437 // Add the offset to the index.
1439 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1440 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1441 DAG.getConstant(EltSize, SDLoc(Vec), Idx.getValueType()));
1443 Idx = DAG.getZExtOrTrunc(Idx, dl, TLI.getPointerTy(DAG.getDataLayout()));
1444 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1448 if (Op.getValueType().isVector())
1449 NewLoad = DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,
1450 MachinePointerInfo(), false, false, false, 0);
1452 NewLoad = DAG.getExtLoad(
1453 ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr, MachinePointerInfo(),
1454 Vec.getValueType().getVectorElementType(), false, false, false, 0);
1456 // Replace the chain going out of the store, by the one out of the load.
1457 DAG.ReplaceAllUsesOfValueWith(Ch, SDValue(NewLoad.getNode(), 1));
1459 // We introduced a cycle though, so update the loads operands, making sure
1460 // to use the original store's chain as an incoming chain.
1461 SmallVector<SDValue, 6> NewLoadOperands(NewLoad->op_begin(),
1463 NewLoadOperands[0] = Ch;
1465 SDValue(DAG.UpdateNodeOperands(NewLoad.getNode(), NewLoadOperands), 0);
1469 SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
1470 assert(Op.getValueType().isVector() && "Non-vector insert subvector!");
1472 SDValue Vec = Op.getOperand(0);
1473 SDValue Part = Op.getOperand(1);
1474 SDValue Idx = Op.getOperand(2);
1477 // Store the value to a temporary stack slot, then LOAD the returned part.
1479 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1480 int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1481 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1483 // First store the whole vector.
1484 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo,
1487 // Then store the inserted part.
1489 // Add the offset to the index.
1491 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1493 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1494 DAG.getConstant(EltSize, SDLoc(Vec), Idx.getValueType()));
1495 Idx = DAG.getZExtOrTrunc(Idx, dl, TLI.getPointerTy(DAG.getDataLayout()));
1497 SDValue SubStackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
1500 // Store the subvector.
1501 Ch = DAG.getStore(Ch, dl, Part, SubStackPtr,
1502 MachinePointerInfo(), false, false, 0);
1504 // Finally, load the updated vector.
1505 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo,
1506 false, false, false, 0);
1509 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1510 // We can't handle this case efficiently. Allocate a sufficiently
1511 // aligned object on the stack, store each element into it, then load
1512 // the result as a vector.
1513 // Create the stack frame object.
1514 EVT VT = Node->getValueType(0);
1515 EVT EltVT = VT.getVectorElementType();
1517 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1518 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1519 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1521 // Emit a store of each element to the stack slot.
1522 SmallVector<SDValue, 8> Stores;
1523 unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1524 // Store (in the right endianness) the elements to memory.
1525 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1526 // Ignore undef elements.
1527 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1529 unsigned Offset = TypeByteSize*i;
1531 SDValue Idx = DAG.getConstant(Offset, dl, FIPtr.getValueType());
1532 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1534 // If the destination vector element type is narrower than the source
1535 // element type, only store the bits necessary.
1536 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1537 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1538 Node->getOperand(i), Idx,
1539 PtrInfo.getWithOffset(Offset),
1540 EltVT, false, false, 0));
1542 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
1543 Node->getOperand(i), Idx,
1544 PtrInfo.getWithOffset(Offset),
1549 if (!Stores.empty()) // Not all undef elements?
1550 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
1552 StoreChain = DAG.getEntryNode();
1554 // Result is a load from the stack slot.
1555 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo,
1556 false, false, false, 0);
1559 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
1561 SDValue Tmp1 = Node->getOperand(0);
1562 SDValue Tmp2 = Node->getOperand(1);
1564 // Get the sign bit of the RHS. First obtain a value that has the same
1565 // sign as the sign bit, i.e. negative if and only if the sign bit is 1.
1567 EVT FloatVT = Tmp2.getValueType();
1568 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits());
1569 if (TLI.isTypeLegal(IVT)) {
1570 // Convert to an integer with the same sign bit.
1571 SignBit = DAG.getNode(ISD::BITCAST, dl, IVT, Tmp2);
1573 auto &DL = DAG.getDataLayout();
1574 // Store the float to memory, then load the sign part out as an integer.
1575 MVT LoadTy = TLI.getPointerTy(DL);
1576 // First create a temporary that is aligned for both the load and store.
1577 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1578 // Then store the float to it.
1580 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, MachinePointerInfo(),
1582 if (DL.isBigEndian()) {
1583 assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1584 // Load out a legal integer with the same sign bit as the float.
1585 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, MachinePointerInfo(),
1586 false, false, false, 0);
1587 } else { // Little endian
1588 SDValue LoadPtr = StackPtr;
1589 // The float may be wider than the integer we are going to load. Advance
1590 // the pointer so that the loaded integer will contain the sign bit.
1591 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits();
1592 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8;
1593 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(), LoadPtr,
1594 DAG.getConstant(ByteOffset, dl,
1595 LoadPtr.getValueType()));
1596 // Load a legal integer containing the sign bit.
1597 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(),
1598 false, false, false, 0);
1599 // Move the sign bit to the top bit of the loaded integer.
1600 unsigned BitShift = LoadTy.getSizeInBits() -
1601 (FloatVT.getSizeInBits() - 8 * ByteOffset);
1602 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?");
1604 SignBit = DAG.getNode(
1605 ISD::SHL, dl, LoadTy, SignBit,
1606 DAG.getConstant(BitShift, dl,
1607 TLI.getShiftAmountTy(SignBit.getValueType(), DL)));
1610 // Now get the sign bit proper, by seeing whether the value is negative.
1611 SignBit = DAG.getSetCC(dl, getSetCCResultType(SignBit.getValueType()),
1613 DAG.getConstant(0, dl, SignBit.getValueType()),
1615 // Get the absolute value of the result.
1616 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1617 // Select between the nabs and abs value based on the sign bit of
1619 return DAG.getSelect(dl, AbsVal.getValueType(), SignBit,
1620 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1624 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1625 SmallVectorImpl<SDValue> &Results) {
1626 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1627 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1628 " not tell us which reg is the stack pointer!");
1630 EVT VT = Node->getValueType(0);
1631 SDValue Tmp1 = SDValue(Node, 0);
1632 SDValue Tmp2 = SDValue(Node, 1);
1633 SDValue Tmp3 = Node->getOperand(2);
1634 SDValue Chain = Tmp1.getOperand(0);
1636 // Chain the dynamic stack allocation so that it doesn't modify the stack
1637 // pointer when other instructions are using the stack.
1638 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true), dl);
1640 SDValue Size = Tmp2.getOperand(1);
1641 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1642 Chain = SP.getValue(1);
1643 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1644 unsigned StackAlign =
1645 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
1646 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1647 if (Align > StackAlign)
1648 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
1649 DAG.getConstant(-(uint64_t)Align, dl, VT));
1650 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1652 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
1653 DAG.getIntPtrConstant(0, dl, true), SDValue(), dl);
1655 Results.push_back(Tmp1);
1656 Results.push_back(Tmp2);
1659 /// Legalize a SETCC with given LHS and RHS and condition code CC on the current
1662 /// If the SETCC has been legalized using AND / OR, then the legalized node
1663 /// will be stored in LHS. RHS and CC will be set to SDValue(). NeedInvert
1664 /// will be set to false.
1666 /// If the SETCC has been legalized by using getSetCCSwappedOperands(),
1667 /// then the values of LHS and RHS will be swapped, CC will be set to the
1668 /// new condition, and NeedInvert will be set to false.
1670 /// If the SETCC has been legalized using the inverse condcode, then LHS and
1671 /// RHS will be unchanged, CC will set to the inverted condcode, and NeedInvert
1672 /// will be set to true. The caller must invert the result of the SETCC with
1673 /// SelectionDAG::getLogicalNOT() or take equivalent action to swap the effect
1674 /// of a true/false result.
1676 /// \returns true if the SetCC has been legalized, false if it hasn't.
1677 bool SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1678 SDValue &LHS, SDValue &RHS,
1682 MVT OpVT = LHS.getSimpleValueType();
1683 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1685 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1686 default: llvm_unreachable("Unknown condition code action!");
1687 case TargetLowering::Legal:
1690 case TargetLowering::Expand: {
1691 ISD::CondCode InvCC = ISD::getSetCCSwappedOperands(CCCode);
1692 if (TLI.isCondCodeLegal(InvCC, OpVT)) {
1693 std::swap(LHS, RHS);
1694 CC = DAG.getCondCode(InvCC);
1697 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1700 default: llvm_unreachable("Don't know how to expand this condition!");
1702 assert(TLI.getCondCodeAction(ISD::SETOEQ, OpVT)
1703 == TargetLowering::Legal
1704 && "If SETO is expanded, SETOEQ must be legal!");
1705 CC1 = ISD::SETOEQ; CC2 = ISD::SETOEQ; Opc = ISD::AND; break;
1707 assert(TLI.getCondCodeAction(ISD::SETUNE, OpVT)
1708 == TargetLowering::Legal
1709 && "If SETUO is expanded, SETUNE must be legal!");
1710 CC1 = ISD::SETUNE; CC2 = ISD::SETUNE; Opc = ISD::OR; break;
1723 // If we are floating point, assign and break, otherwise fall through.
1724 if (!OpVT.isInteger()) {
1725 // We can use the 4th bit to tell if we are the unordered
1726 // or ordered version of the opcode.
1727 CC2 = ((unsigned)CCCode & 0x8U) ? ISD::SETUO : ISD::SETO;
1728 Opc = ((unsigned)CCCode & 0x8U) ? ISD::OR : ISD::AND;
1729 CC1 = (ISD::CondCode)(((int)CCCode & 0x7) | 0x10);
1732 // Fallthrough if we are unsigned integer.
1737 // We only support using the inverted operation, which is computed above
1738 // and not a different manner of supporting expanding these cases.
1739 llvm_unreachable("Don't know how to expand this condition!");
1742 // Try inverting the result of the inverse condition.
1743 InvCC = CCCode == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ;
1744 if (TLI.isCondCodeLegal(InvCC, OpVT)) {
1745 CC = DAG.getCondCode(InvCC);
1749 // If inverting the condition didn't work then we have no means to expand
1751 llvm_unreachable("Don't know how to expand this condition!");
1754 SDValue SetCC1, SetCC2;
1755 if (CCCode != ISD::SETO && CCCode != ISD::SETUO) {
1756 // If we aren't the ordered or unorder operation,
1757 // then the pattern is (LHS CC1 RHS) Opc (LHS CC2 RHS).
1758 SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1759 SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1761 // Otherwise, the pattern is (LHS CC1 LHS) Opc (RHS CC2 RHS)
1762 SetCC1 = DAG.getSetCC(dl, VT, LHS, LHS, CC1);
1763 SetCC2 = DAG.getSetCC(dl, VT, RHS, RHS, CC2);
1765 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1774 /// Emit a store/load combination to the stack. This stores
1775 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1776 /// a load from the stack slot to DestVT, extending it if needed.
1777 /// The resultant code need not be legal.
1778 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
1782 // Create the stack frame object.
1783 unsigned SrcAlign = DAG.getDataLayout().getPrefTypeAlignment(
1784 SrcOp.getValueType().getTypeForEVT(*DAG.getContext()));
1785 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1787 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1788 int SPFI = StackPtrFI->getIndex();
1789 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(SPFI);
1791 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
1792 unsigned SlotSize = SlotVT.getSizeInBits();
1793 unsigned DestSize = DestVT.getSizeInBits();
1794 Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
1795 unsigned DestAlign = DAG.getDataLayout().getPrefTypeAlignment(DestType);
1797 // Emit a store to the stack slot. Use a truncstore if the input value is
1798 // later than DestVT.
1801 if (SrcSize > SlotSize)
1802 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1803 PtrInfo, SlotVT, false, false, SrcAlign);
1805 assert(SrcSize == SlotSize && "Invalid store");
1806 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1807 PtrInfo, false, false, SrcAlign);
1810 // Result is a load from the stack slot.
1811 if (SlotSize == DestSize)
1812 return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo,
1813 false, false, false, DestAlign);
1815 assert(SlotSize < DestSize && "Unknown extension!");
1816 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr,
1817 PtrInfo, SlotVT, false, false, false, DestAlign);
1820 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1822 // Create a vector sized/aligned stack slot, store the value to element #0,
1823 // then load the whole vector back out.
1824 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1826 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1827 int SPFI = StackPtrFI->getIndex();
1829 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0),
1831 MachinePointerInfo::getFixedStack(SPFI),
1832 Node->getValueType(0).getVectorElementType(),
1834 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
1835 MachinePointerInfo::getFixedStack(SPFI),
1836 false, false, false, 0);
1840 ExpandBVWithShuffles(SDNode *Node, SelectionDAG &DAG,
1841 const TargetLowering &TLI, SDValue &Res) {
1842 unsigned NumElems = Node->getNumOperands();
1844 EVT VT = Node->getValueType(0);
1846 // Try to group the scalars into pairs, shuffle the pairs together, then
1847 // shuffle the pairs of pairs together, etc. until the vector has
1848 // been built. This will work only if all of the necessary shuffle masks
1851 // We do this in two phases; first to check the legality of the shuffles,
1852 // and next, assuming that all shuffles are legal, to create the new nodes.
1853 for (int Phase = 0; Phase < 2; ++Phase) {
1854 SmallVector<std::pair<SDValue, SmallVector<int, 16> >, 16> IntermedVals,
1856 for (unsigned i = 0; i < NumElems; ++i) {
1857 SDValue V = Node->getOperand(i);
1858 if (V.getOpcode() == ISD::UNDEF)
1863 Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, V);
1864 IntermedVals.push_back(std::make_pair(Vec, SmallVector<int, 16>(1, i)));
1867 while (IntermedVals.size() > 2) {
1868 NewIntermedVals.clear();
1869 for (unsigned i = 0, e = (IntermedVals.size() & ~1u); i < e; i += 2) {
1870 // This vector and the next vector are shuffled together (simply to
1871 // append the one to the other).
1872 SmallVector<int, 16> ShuffleVec(NumElems, -1);
1874 SmallVector<int, 16> FinalIndices;
1875 FinalIndices.reserve(IntermedVals[i].second.size() +
1876 IntermedVals[i+1].second.size());
1879 for (unsigned j = 0, f = IntermedVals[i].second.size(); j != f;
1882 FinalIndices.push_back(IntermedVals[i].second[j]);
1884 for (unsigned j = 0, f = IntermedVals[i+1].second.size(); j != f;
1886 ShuffleVec[k] = NumElems + j;
1887 FinalIndices.push_back(IntermedVals[i+1].second[j]);
1892 Shuffle = DAG.getVectorShuffle(VT, dl, IntermedVals[i].first,
1893 IntermedVals[i+1].first,
1895 else if (!TLI.isShuffleMaskLegal(ShuffleVec, VT))
1897 NewIntermedVals.push_back(
1898 std::make_pair(Shuffle, std::move(FinalIndices)));
1901 // If we had an odd number of defined values, then append the last
1902 // element to the array of new vectors.
1903 if ((IntermedVals.size() & 1) != 0)
1904 NewIntermedVals.push_back(IntermedVals.back());
1906 IntermedVals.swap(NewIntermedVals);
1909 assert(IntermedVals.size() <= 2 && IntermedVals.size() > 0 &&
1910 "Invalid number of intermediate vectors");
1911 SDValue Vec1 = IntermedVals[0].first;
1913 if (IntermedVals.size() > 1)
1914 Vec2 = IntermedVals[1].first;
1916 Vec2 = DAG.getUNDEF(VT);
1918 SmallVector<int, 16> ShuffleVec(NumElems, -1);
1919 for (unsigned i = 0, e = IntermedVals[0].second.size(); i != e; ++i)
1920 ShuffleVec[IntermedVals[0].second[i]] = i;
1921 for (unsigned i = 0, e = IntermedVals[1].second.size(); i != e; ++i)
1922 ShuffleVec[IntermedVals[1].second[i]] = NumElems + i;
1925 Res = DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
1926 else if (!TLI.isShuffleMaskLegal(ShuffleVec, VT))
1933 /// Expand a BUILD_VECTOR node on targets that don't
1934 /// support the operation, but do support the resultant vector type.
1935 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1936 unsigned NumElems = Node->getNumOperands();
1937 SDValue Value1, Value2;
1939 EVT VT = Node->getValueType(0);
1940 EVT OpVT = Node->getOperand(0).getValueType();
1941 EVT EltVT = VT.getVectorElementType();
1943 // If the only non-undef value is the low element, turn this into a
1944 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1945 bool isOnlyLowElement = true;
1946 bool MoreThanTwoValues = false;
1947 bool isConstant = true;
1948 for (unsigned i = 0; i < NumElems; ++i) {
1949 SDValue V = Node->getOperand(i);
1950 if (V.getOpcode() == ISD::UNDEF)
1953 isOnlyLowElement = false;
1954 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1957 if (!Value1.getNode()) {
1959 } else if (!Value2.getNode()) {
1962 } else if (V != Value1 && V != Value2) {
1963 MoreThanTwoValues = true;
1967 if (!Value1.getNode())
1968 return DAG.getUNDEF(VT);
1970 if (isOnlyLowElement)
1971 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1973 // If all elements are constants, create a load from the constant pool.
1975 SmallVector<Constant*, 16> CV;
1976 for (unsigned i = 0, e = NumElems; i != e; ++i) {
1977 if (ConstantFPSDNode *V =
1978 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1979 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1980 } else if (ConstantSDNode *V =
1981 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1983 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1985 // If OpVT and EltVT don't match, EltVT is not legal and the
1986 // element values have been promoted/truncated earlier. Undo this;
1987 // we don't want a v16i8 to become a v16i32 for example.
1988 const ConstantInt *CI = V->getConstantIntValue();
1989 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
1990 CI->getZExtValue()));
1993 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
1994 Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
1995 CV.push_back(UndefValue::get(OpNTy));
1998 Constant *CP = ConstantVector::get(CV);
2000 DAG.getConstantPool(CP, TLI.getPointerTy(DAG.getDataLayout()));
2001 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2002 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
2003 MachinePointerInfo::getConstantPool(),
2004 false, false, false, Alignment);
2007 SmallSet<SDValue, 16> DefinedValues;
2008 for (unsigned i = 0; i < NumElems; ++i) {
2009 if (Node->getOperand(i).getOpcode() == ISD::UNDEF)
2011 DefinedValues.insert(Node->getOperand(i));
2014 if (TLI.shouldExpandBuildVectorWithShuffles(VT, DefinedValues.size())) {
2015 if (!MoreThanTwoValues) {
2016 SmallVector<int, 8> ShuffleVec(NumElems, -1);
2017 for (unsigned i = 0; i < NumElems; ++i) {
2018 SDValue V = Node->getOperand(i);
2019 if (V.getOpcode() == ISD::UNDEF)
2021 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
2023 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
2024 // Get the splatted value into the low element of a vector register.
2025 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
2027 if (Value2.getNode())
2028 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
2030 Vec2 = DAG.getUNDEF(VT);
2032 // Return shuffle(LowValVec, undef, <0,0,0,0>)
2033 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
2037 if (ExpandBVWithShuffles(Node, DAG, TLI, Res))
2042 // Otherwise, we can't handle this case efficiently.
2043 return ExpandVectorBuildThroughStack(Node);
2046 // Expand a node into a call to a libcall. If the result value
2047 // does not fit into a register, return the lo part and set the hi part to the
2048 // by-reg argument. If it does fit into a single register, return the result
2049 // and leave the Hi part unset.
2050 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
2052 TargetLowering::ArgListTy Args;
2053 TargetLowering::ArgListEntry Entry;
2054 for (const SDValue &Op : Node->op_values()) {
2055 EVT ArgVT = Op.getValueType();
2056 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2059 Entry.isSExt = isSigned;
2060 Entry.isZExt = !isSigned;
2061 Args.push_back(Entry);
2063 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2064 TLI.getPointerTy(DAG.getDataLayout()));
2066 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2068 // By default, the input chain to this libcall is the entry node of the
2069 // function. If the libcall is going to be emitted as a tail call then
2070 // TLI.isUsedByReturnOnly will change it to the right chain if the return
2071 // node which is being folded has a non-entry input chain.
2072 SDValue InChain = DAG.getEntryNode();
2074 // isTailCall may be true since the callee does not reference caller stack
2075 // frame. Check if it's in the right position.
2076 SDValue TCChain = InChain;
2077 bool isTailCall = TLI.isInTailCallPosition(DAG, Node, TCChain);
2081 TargetLowering::CallLoweringInfo CLI(DAG);
2082 CLI.setDebugLoc(SDLoc(Node)).setChain(InChain)
2083 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
2084 .setTailCall(isTailCall).setSExtResult(isSigned).setZExtResult(!isSigned);
2086 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2088 if (!CallInfo.second.getNode())
2089 // It's a tailcall, return the chain (which is the DAG root).
2090 return DAG.getRoot();
2092 return CallInfo.first;
2095 /// Generate a libcall taking the given operands as arguments
2096 /// and returning a result of type RetVT.
2097 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, EVT RetVT,
2098 const SDValue *Ops, unsigned NumOps,
2099 bool isSigned, SDLoc dl) {
2100 TargetLowering::ArgListTy Args;
2101 Args.reserve(NumOps);
2103 TargetLowering::ArgListEntry Entry;
2104 for (unsigned i = 0; i != NumOps; ++i) {
2105 Entry.Node = Ops[i];
2106 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
2107 Entry.isSExt = isSigned;
2108 Entry.isZExt = !isSigned;
2109 Args.push_back(Entry);
2111 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2112 TLI.getPointerTy(DAG.getDataLayout()));
2114 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2116 TargetLowering::CallLoweringInfo CLI(DAG);
2117 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
2118 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
2119 .setSExtResult(isSigned).setZExtResult(!isSigned);
2121 std::pair<SDValue,SDValue> CallInfo = TLI.LowerCallTo(CLI);
2123 return CallInfo.first;
2126 // Expand a node into a call to a libcall. Similar to
2127 // ExpandLibCall except that the first operand is the in-chain.
2128 std::pair<SDValue, SDValue>
2129 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
2132 SDValue InChain = Node->getOperand(0);
2134 TargetLowering::ArgListTy Args;
2135 TargetLowering::ArgListEntry Entry;
2136 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) {
2137 EVT ArgVT = Node->getOperand(i).getValueType();
2138 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2139 Entry.Node = Node->getOperand(i);
2141 Entry.isSExt = isSigned;
2142 Entry.isZExt = !isSigned;
2143 Args.push_back(Entry);
2145 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2146 TLI.getPointerTy(DAG.getDataLayout()));
2148 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2150 TargetLowering::CallLoweringInfo CLI(DAG);
2151 CLI.setDebugLoc(SDLoc(Node)).setChain(InChain)
2152 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
2153 .setSExtResult(isSigned).setZExtResult(!isSigned);
2155 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2160 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
2161 RTLIB::Libcall Call_F32,
2162 RTLIB::Libcall Call_F64,
2163 RTLIB::Libcall Call_F80,
2164 RTLIB::Libcall Call_F128,
2165 RTLIB::Libcall Call_PPCF128) {
2167 switch (Node->getSimpleValueType(0).SimpleTy) {
2168 default: llvm_unreachable("Unexpected request for libcall!");
2169 case MVT::f32: LC = Call_F32; break;
2170 case MVT::f64: LC = Call_F64; break;
2171 case MVT::f80: LC = Call_F80; break;
2172 case MVT::f128: LC = Call_F128; break;
2173 case MVT::ppcf128: LC = Call_PPCF128; break;
2175 return ExpandLibCall(LC, Node, false);
2178 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
2179 RTLIB::Libcall Call_I8,
2180 RTLIB::Libcall Call_I16,
2181 RTLIB::Libcall Call_I32,
2182 RTLIB::Libcall Call_I64,
2183 RTLIB::Libcall Call_I128) {
2185 switch (Node->getSimpleValueType(0).SimpleTy) {
2186 default: llvm_unreachable("Unexpected request for libcall!");
2187 case MVT::i8: LC = Call_I8; break;
2188 case MVT::i16: LC = Call_I16; break;
2189 case MVT::i32: LC = Call_I32; break;
2190 case MVT::i64: LC = Call_I64; break;
2191 case MVT::i128: LC = Call_I128; break;
2193 return ExpandLibCall(LC, Node, isSigned);
2196 /// Return true if divmod libcall is available.
2197 static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
2198 const TargetLowering &TLI) {
2200 switch (Node->getSimpleValueType(0).SimpleTy) {
2201 default: llvm_unreachable("Unexpected request for libcall!");
2202 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2203 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2204 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2205 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2206 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2209 return TLI.getLibcallName(LC) != nullptr;
2212 /// Only issue divrem libcall if both quotient and remainder are needed.
2213 static bool useDivRem(SDNode *Node, bool isSigned, bool isDIV) {
2214 // The other use might have been replaced with a divrem already.
2215 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2216 unsigned OtherOpcode = 0;
2218 OtherOpcode = isDIV ? ISD::SREM : ISD::SDIV;
2220 OtherOpcode = isDIV ? ISD::UREM : ISD::UDIV;
2222 SDValue Op0 = Node->getOperand(0);
2223 SDValue Op1 = Node->getOperand(1);
2224 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2225 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2229 if ((User->getOpcode() == OtherOpcode || User->getOpcode() == DivRemOpc) &&
2230 User->getOperand(0) == Op0 &&
2231 User->getOperand(1) == Op1)
2237 /// Issue libcalls to __{u}divmod to compute div / rem pairs.
2239 SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
2240 SmallVectorImpl<SDValue> &Results) {
2241 unsigned Opcode = Node->getOpcode();
2242 bool isSigned = Opcode == ISD::SDIVREM;
2245 switch (Node->getSimpleValueType(0).SimpleTy) {
2246 default: llvm_unreachable("Unexpected request for libcall!");
2247 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2248 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2249 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2250 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2251 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2254 // The input chain to this libcall is the entry node of the function.
2255 // Legalizing the call will automatically add the previous call to the
2257 SDValue InChain = DAG.getEntryNode();
2259 EVT RetVT = Node->getValueType(0);
2260 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2262 TargetLowering::ArgListTy Args;
2263 TargetLowering::ArgListEntry Entry;
2264 for (const SDValue &Op : Node->op_values()) {
2265 EVT ArgVT = Op.getValueType();
2266 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2269 Entry.isSExt = isSigned;
2270 Entry.isZExt = !isSigned;
2271 Args.push_back(Entry);
2274 // Also pass the return address of the remainder.
2275 SDValue FIPtr = DAG.CreateStackTemporary(RetVT);
2277 Entry.Ty = RetTy->getPointerTo();
2278 Entry.isSExt = isSigned;
2279 Entry.isZExt = !isSigned;
2280 Args.push_back(Entry);
2282 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2283 TLI.getPointerTy(DAG.getDataLayout()));
2286 TargetLowering::CallLoweringInfo CLI(DAG);
2287 CLI.setDebugLoc(dl).setChain(InChain)
2288 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
2289 .setSExtResult(isSigned).setZExtResult(!isSigned);
2291 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2293 // Remainder is loaded back from the stack frame.
2294 SDValue Rem = DAG.getLoad(RetVT, dl, CallInfo.second, FIPtr,
2295 MachinePointerInfo(), false, false, false, 0);
2296 Results.push_back(CallInfo.first);
2297 Results.push_back(Rem);
2300 /// Return true if sincos libcall is available.
2301 static bool isSinCosLibcallAvailable(SDNode *Node, const TargetLowering &TLI) {
2303 switch (Node->getSimpleValueType(0).SimpleTy) {
2304 default: llvm_unreachable("Unexpected request for libcall!");
2305 case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2306 case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2307 case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2308 case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2309 case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2311 return TLI.getLibcallName(LC) != nullptr;
2314 /// Return true if sincos libcall is available and can be used to combine sin
2316 static bool canCombineSinCosLibcall(SDNode *Node, const TargetLowering &TLI,
2317 const TargetMachine &TM) {
2318 if (!isSinCosLibcallAvailable(Node, TLI))
2320 // GNU sin/cos functions set errno while sincos does not. Therefore
2321 // combining sin and cos is only safe if unsafe-fpmath is enabled.
2322 bool isGNU = Triple(TM.getTargetTriple()).getEnvironment() == Triple::GNU;
2323 if (isGNU && !TM.Options.UnsafeFPMath)
2328 /// Only issue sincos libcall if both sin and cos are needed.
2329 static bool useSinCos(SDNode *Node) {
2330 unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN
2331 ? ISD::FCOS : ISD::FSIN;
2333 SDValue Op0 = Node->getOperand(0);
2334 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2335 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2339 // The other user might have been turned into sincos already.
2340 if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS)
2346 /// Issue libcalls to sincos to compute sin / cos pairs.
2348 SelectionDAGLegalize::ExpandSinCosLibCall(SDNode *Node,
2349 SmallVectorImpl<SDValue> &Results) {
2351 switch (Node->getSimpleValueType(0).SimpleTy) {
2352 default: llvm_unreachable("Unexpected request for libcall!");
2353 case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2354 case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2355 case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2356 case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2357 case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2360 // The input chain to this libcall is the entry node of the function.
2361 // Legalizing the call will automatically add the previous call to the
2363 SDValue InChain = DAG.getEntryNode();
2365 EVT RetVT = Node->getValueType(0);
2366 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2368 TargetLowering::ArgListTy Args;
2369 TargetLowering::ArgListEntry Entry;
2371 // Pass the argument.
2372 Entry.Node = Node->getOperand(0);
2374 Entry.isSExt = false;
2375 Entry.isZExt = false;
2376 Args.push_back(Entry);
2378 // Pass the return address of sin.
2379 SDValue SinPtr = DAG.CreateStackTemporary(RetVT);
2380 Entry.Node = SinPtr;
2381 Entry.Ty = RetTy->getPointerTo();
2382 Entry.isSExt = false;
2383 Entry.isZExt = false;
2384 Args.push_back(Entry);
2386 // Also pass the return address of the cos.
2387 SDValue CosPtr = DAG.CreateStackTemporary(RetVT);
2388 Entry.Node = CosPtr;
2389 Entry.Ty = RetTy->getPointerTo();
2390 Entry.isSExt = false;
2391 Entry.isZExt = false;
2392 Args.push_back(Entry);
2394 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2395 TLI.getPointerTy(DAG.getDataLayout()));
2398 TargetLowering::CallLoweringInfo CLI(DAG);
2399 CLI.setDebugLoc(dl).setChain(InChain)
2400 .setCallee(TLI.getLibcallCallingConv(LC),
2401 Type::getVoidTy(*DAG.getContext()), Callee, std::move(Args), 0);
2403 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2405 Results.push_back(DAG.getLoad(RetVT, dl, CallInfo.second, SinPtr,
2406 MachinePointerInfo(), false, false, false, 0));
2407 Results.push_back(DAG.getLoad(RetVT, dl, CallInfo.second, CosPtr,
2408 MachinePointerInfo(), false, false, false, 0));
2411 /// This function is responsible for legalizing a
2412 /// INT_TO_FP operation of the specified operand when the target requests that
2413 /// we expand it. At this point, we know that the result and operand types are
2414 /// legal for the target.
2415 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
2419 if (Op0.getValueType() == MVT::i32 && TLI.isTypeLegal(MVT::f64)) {
2420 // simple 32-bit [signed|unsigned] integer to float/double expansion
2422 // Get the stack frame index of a 8 byte buffer.
2423 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2425 // word offset constant for Hi/Lo address computation
2426 SDValue WordOff = DAG.getConstant(sizeof(int), dl,
2427 StackSlot.getValueType());
2428 // set up Hi and Lo (into buffer) address based on endian
2429 SDValue Hi = StackSlot;
2430 SDValue Lo = DAG.getNode(ISD::ADD, dl, StackSlot.getValueType(),
2431 StackSlot, WordOff);
2432 if (DAG.getDataLayout().isLittleEndian())
2435 // if signed map to unsigned space
2438 // constant used to invert sign bit (signed to unsigned mapping)
2439 SDValue SignBit = DAG.getConstant(0x80000000u, dl, MVT::i32);
2440 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2444 // store the lo of the constructed double - based on integer input
2445 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
2446 Op0Mapped, Lo, MachinePointerInfo(),
2448 // initial hi portion of constructed double
2449 SDValue InitialHi = DAG.getConstant(0x43300000u, dl, MVT::i32);
2450 // store the hi of the constructed double - biased exponent
2451 SDValue Store2 = DAG.getStore(Store1, dl, InitialHi, Hi,
2452 MachinePointerInfo(),
2454 // load the constructed double
2455 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot,
2456 MachinePointerInfo(), false, false, false, 0);
2457 // FP constant to bias correct the final result
2458 SDValue Bias = DAG.getConstantFP(isSigned ?
2459 BitsToDouble(0x4330000080000000ULL) :
2460 BitsToDouble(0x4330000000000000ULL),
2462 // subtract the bias
2463 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2466 // handle final rounding
2467 if (DestVT == MVT::f64) {
2470 } else if (DestVT.bitsLT(MVT::f64)) {
2471 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2472 DAG.getIntPtrConstant(0, dl));
2473 } else if (DestVT.bitsGT(MVT::f64)) {
2474 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2478 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2479 // Code below here assumes !isSigned without checking again.
2481 // Implementation of unsigned i64 to f64 following the algorithm in
2482 // __floatundidf in compiler_rt. This implementation has the advantage
2483 // of performing rounding correctly, both in the default rounding mode
2484 // and in all alternate rounding modes.
2485 // TODO: Generalize this for use with other types.
2486 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
2488 DAG.getConstant(UINT64_C(0x4330000000000000), dl, MVT::i64);
2489 SDValue TwoP84PlusTwoP52 =
2490 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), dl,
2493 DAG.getConstant(UINT64_C(0x4530000000000000), dl, MVT::i64);
2495 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32);
2496 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2497 DAG.getConstant(32, dl, MVT::i64));
2498 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2499 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2500 SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr);
2501 SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr);
2502 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
2504 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
2507 // Implementation of unsigned i64 to f32.
2508 // TODO: Generalize this for use with other types.
2509 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) {
2510 // For unsigned conversions, convert them to signed conversions using the
2511 // algorithm from the x86_64 __floatundidf in compiler_rt.
2513 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0);
2515 SDValue ShiftConst = DAG.getConstant(
2516 1, dl, TLI.getShiftAmountTy(Op0.getValueType(), DAG.getDataLayout()));
2517 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
2518 SDValue AndConst = DAG.getConstant(1, dl, MVT::i64);
2519 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst);
2520 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr);
2522 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or);
2523 SDValue Slow = DAG.getNode(ISD::FADD, dl, MVT::f32, SignCvt, SignCvt);
2525 // TODO: This really should be implemented using a branch rather than a
2526 // select. We happen to get lucky and machinesink does the right
2527 // thing most of the time. This would be a good candidate for a
2528 //pseudo-op, or, even better, for whole-function isel.
2529 SDValue SignBitTest = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
2530 Op0, DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
2531 return DAG.getSelect(dl, MVT::f32, SignBitTest, Slow, Fast);
2534 // Otherwise, implement the fully general conversion.
2536 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2537 DAG.getConstant(UINT64_C(0xfffffffffffff800), dl, MVT::i64));
2538 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
2539 DAG.getConstant(UINT64_C(0x800), dl, MVT::i64));
2540 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2541 DAG.getConstant(UINT64_C(0x7ff), dl, MVT::i64));
2542 SDValue Ne = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), And2,
2543 DAG.getConstant(UINT64_C(0), dl, MVT::i64),
2545 SDValue Sel = DAG.getSelect(dl, MVT::i64, Ne, Or, Op0);
2546 SDValue Ge = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), Op0,
2547 DAG.getConstant(UINT64_C(0x0020000000000000), dl,
2550 SDValue Sel2 = DAG.getSelect(dl, MVT::i64, Ge, Sel, Op0);
2551 EVT SHVT = TLI.getShiftAmountTy(Sel2.getValueType(), DAG.getDataLayout());
2553 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2554 DAG.getConstant(32, dl, SHVT));
2555 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh);
2556 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc);
2558 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), dl,
2560 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt);
2561 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2);
2562 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo);
2563 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2);
2564 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd,
2565 DAG.getIntPtrConstant(0, dl));
2568 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2570 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(Op0.getValueType()),
2572 DAG.getConstant(0, dl, Op0.getValueType()),
2574 SDValue Zero = DAG.getIntPtrConstant(0, dl),
2575 Four = DAG.getIntPtrConstant(4, dl);
2576 SDValue CstOffset = DAG.getSelect(dl, Zero.getValueType(),
2577 SignSet, Four, Zero);
2579 // If the sign bit of the integer is set, the large number will be treated
2580 // as a negative number. To counteract this, the dynamic code adds an
2581 // offset depending on the data type.
2583 switch (Op0.getSimpleValueType().SimpleTy) {
2584 default: llvm_unreachable("Unsupported integer type!");
2585 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2586 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2587 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2588 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2590 if (DAG.getDataLayout().isLittleEndian())
2592 Constant *FudgeFactor = ConstantInt::get(
2593 Type::getInt64Ty(*DAG.getContext()), FF);
2596 DAG.getConstantPool(FudgeFactor, TLI.getPointerTy(DAG.getDataLayout()));
2597 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2598 CPIdx = DAG.getNode(ISD::ADD, dl, CPIdx.getValueType(), CPIdx, CstOffset);
2599 Alignment = std::min(Alignment, 4u);
2601 if (DestVT == MVT::f32)
2602 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2603 MachinePointerInfo::getConstantPool(),
2604 false, false, false, Alignment);
2606 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
2607 DAG.getEntryNode(), CPIdx,
2608 MachinePointerInfo::getConstantPool(),
2609 MVT::f32, false, false, false, Alignment);
2610 HandleSDNode Handle(Load);
2611 LegalizeOp(Load.getNode());
2612 FudgeInReg = Handle.getValue();
2615 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2618 /// This function is responsible for legalizing a
2619 /// *INT_TO_FP operation of the specified operand when the target requests that
2620 /// we promote it. At this point, we know that the result and operand types are
2621 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2622 /// operation that takes a larger input.
2623 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2627 // First step, figure out the appropriate *INT_TO_FP operation to use.
2628 EVT NewInTy = LegalOp.getValueType();
2630 unsigned OpToUse = 0;
2632 // Scan for the appropriate larger type to use.
2634 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2635 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2637 // If the target supports SINT_TO_FP of this type, use it.
2638 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2639 OpToUse = ISD::SINT_TO_FP;
2642 if (isSigned) continue;
2644 // If the target supports UINT_TO_FP of this type, use it.
2645 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2646 OpToUse = ISD::UINT_TO_FP;
2650 // Otherwise, try a larger type.
2653 // Okay, we found the operation and type to use. Zero extend our input to the
2654 // desired type then run the operation on it.
2655 return DAG.getNode(OpToUse, dl, DestVT,
2656 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2657 dl, NewInTy, LegalOp));
2660 /// This function is responsible for legalizing a
2661 /// FP_TO_*INT operation of the specified operand when the target requests that
2662 /// we promote it. At this point, we know that the result and operand types are
2663 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2664 /// operation that returns a larger result.
2665 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2669 // First step, figure out the appropriate FP_TO*INT operation to use.
2670 EVT NewOutTy = DestVT;
2672 unsigned OpToUse = 0;
2674 // Scan for the appropriate larger type to use.
2676 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2677 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2679 // A larger signed type can hold all unsigned values of the requested type,
2680 // so using FP_TO_SINT is valid
2681 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2682 OpToUse = ISD::FP_TO_SINT;
2686 // However, if the value may be < 0.0, we *must* use some FP_TO_SINT.
2687 if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2688 OpToUse = ISD::FP_TO_UINT;
2692 // Otherwise, try a larger type.
2696 // Okay, we found the operation and type to use.
2697 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2699 // Truncate the result of the extended FP_TO_*INT operation to the desired
2701 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2704 /// Open code the operations for BSWAP of the specified operation.
2705 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, SDLoc dl) {
2706 EVT VT = Op.getValueType();
2707 EVT SHVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2708 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2709 switch (VT.getSimpleVT().SimpleTy) {
2710 default: llvm_unreachable("Unhandled Expand type in BSWAP!");
2712 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2713 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2714 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2716 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2717 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2718 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2719 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2720 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3,
2721 DAG.getConstant(0xFF0000, dl, VT));
2722 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, dl, VT));
2723 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2724 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2725 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2727 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, dl, SHVT));
2728 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, dl, SHVT));
2729 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2730 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2731 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2732 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2733 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, dl, SHVT));
2734 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, dl, SHVT));
2735 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7,
2736 DAG.getConstant(255ULL<<48, dl, VT));
2737 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6,
2738 DAG.getConstant(255ULL<<40, dl, VT));
2739 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5,
2740 DAG.getConstant(255ULL<<32, dl, VT));
2741 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4,
2742 DAG.getConstant(255ULL<<24, dl, VT));
2743 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3,
2744 DAG.getConstant(255ULL<<16, dl, VT));
2745 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2,
2746 DAG.getConstant(255ULL<<8 , dl, VT));
2747 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2748 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2749 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2750 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2751 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2752 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2753 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2757 /// Expand the specified bitcount instruction into operations.
2758 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2761 default: llvm_unreachable("Cannot expand this yet!");
2763 EVT VT = Op.getValueType();
2764 EVT ShVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2765 unsigned Len = VT.getSizeInBits();
2767 assert(VT.isInteger() && Len <= 128 && Len % 8 == 0 &&
2768 "CTPOP not implemented for this type.");
2770 // This is the "best" algorithm from
2771 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
2773 SDValue Mask55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)),
2775 SDValue Mask33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)),
2777 SDValue Mask0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)),
2779 SDValue Mask01 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x01)),
2782 // v = v - ((v >> 1) & 0x55555555...)
2783 Op = DAG.getNode(ISD::SUB, dl, VT, Op,
2784 DAG.getNode(ISD::AND, dl, VT,
2785 DAG.getNode(ISD::SRL, dl, VT, Op,
2786 DAG.getConstant(1, dl, ShVT)),
2788 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
2789 Op = DAG.getNode(ISD::ADD, dl, VT,
2790 DAG.getNode(ISD::AND, dl, VT, Op, Mask33),
2791 DAG.getNode(ISD::AND, dl, VT,
2792 DAG.getNode(ISD::SRL, dl, VT, Op,
2793 DAG.getConstant(2, dl, ShVT)),
2795 // v = (v + (v >> 4)) & 0x0F0F0F0F...
2796 Op = DAG.getNode(ISD::AND, dl, VT,
2797 DAG.getNode(ISD::ADD, dl, VT, Op,
2798 DAG.getNode(ISD::SRL, dl, VT, Op,
2799 DAG.getConstant(4, dl, ShVT))),
2801 // v = (v * 0x01010101...) >> (Len - 8)
2802 Op = DAG.getNode(ISD::SRL, dl, VT,
2803 DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
2804 DAG.getConstant(Len - 8, dl, ShVT));
2808 case ISD::CTLZ_ZERO_UNDEF:
2809 // This trivially expands to CTLZ.
2810 return DAG.getNode(ISD::CTLZ, dl, Op.getValueType(), Op);
2812 // for now, we do this:
2813 // x = x | (x >> 1);
2814 // x = x | (x >> 2);
2816 // x = x | (x >>16);
2817 // x = x | (x >>32); // for 64-bit input
2818 // return popcount(~x);
2820 // Ref: "Hacker's Delight" by Henry Warren
2821 EVT VT = Op.getValueType();
2822 EVT ShVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2823 unsigned len = VT.getSizeInBits();
2824 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2825 SDValue Tmp3 = DAG.getConstant(1ULL << i, dl, ShVT);
2826 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2827 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2829 Op = DAG.getNOT(dl, Op, VT);
2830 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2832 case ISD::CTTZ_ZERO_UNDEF:
2833 // This trivially expands to CTTZ.
2834 return DAG.getNode(ISD::CTTZ, dl, Op.getValueType(), Op);
2836 // for now, we use: { return popcount(~x & (x - 1)); }
2837 // unless the target has ctlz but not ctpop, in which case we use:
2838 // { return 32 - nlz(~x & (x-1)); }
2839 // Ref: "Hacker's Delight" by Henry Warren
2840 EVT VT = Op.getValueType();
2841 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2842 DAG.getNOT(dl, Op, VT),
2843 DAG.getNode(ISD::SUB, dl, VT, Op,
2844 DAG.getConstant(1, dl, VT)));
2845 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2846 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2847 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2848 return DAG.getNode(ISD::SUB, dl, VT,
2849 DAG.getConstant(VT.getSizeInBits(), dl, VT),
2850 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2851 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2856 std::pair <SDValue, SDValue> SelectionDAGLegalize::ExpandAtomic(SDNode *Node) {
2857 unsigned Opc = Node->getOpcode();
2858 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
2859 RTLIB::Libcall LC = RTLIB::getATOMIC(Opc, VT);
2860 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected atomic op or value type!");
2862 return ExpandChainLibCall(LC, Node, false);
2865 void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
2866 SmallVector<SDValue, 8> Results;
2868 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2870 switch (Node->getOpcode()) {
2873 case ISD::CTLZ_ZERO_UNDEF:
2875 case ISD::CTTZ_ZERO_UNDEF:
2876 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
2877 Results.push_back(Tmp1);
2880 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2882 case ISD::FRAMEADDR:
2883 case ISD::RETURNADDR:
2884 case ISD::FRAME_TO_ARGS_OFFSET:
2885 Results.push_back(DAG.getConstant(0, dl, Node->getValueType(0)));
2887 case ISD::FLT_ROUNDS_:
2888 Results.push_back(DAG.getConstant(1, dl, Node->getValueType(0)));
2890 case ISD::EH_RETURN:
2894 case ISD::EH_SJLJ_LONGJMP:
2895 // If the target didn't expand these, there's nothing to do, so just
2896 // preserve the chain and be done.
2897 Results.push_back(Node->getOperand(0));
2899 case ISD::EH_SJLJ_SETJMP:
2900 // If the target didn't expand this, just return 'zero' and preserve the
2902 Results.push_back(DAG.getConstant(0, dl, MVT::i32));
2903 Results.push_back(Node->getOperand(0));
2905 case ISD::ATOMIC_FENCE: {
2906 // If the target didn't lower this, lower it to '__sync_synchronize()' call
2907 // FIXME: handle "fence singlethread" more efficiently.
2908 TargetLowering::ArgListTy Args;
2910 TargetLowering::CallLoweringInfo CLI(DAG);
2912 .setChain(Node->getOperand(0))
2913 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
2914 DAG.getExternalSymbol("__sync_synchronize",
2915 TLI.getPointerTy(DAG.getDataLayout())),
2916 std::move(Args), 0);
2918 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
2920 Results.push_back(CallResult.second);
2923 case ISD::ATOMIC_LOAD: {
2924 // There is no libcall for atomic load; fake it with ATOMIC_CMP_SWAP.
2925 SDValue Zero = DAG.getConstant(0, dl, Node->getValueType(0));
2926 SDVTList VTs = DAG.getVTList(Node->getValueType(0), MVT::Other);
2927 SDValue Swap = DAG.getAtomicCmpSwap(
2928 ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
2929 Node->getOperand(0), Node->getOperand(1), Zero, Zero,
2930 cast<AtomicSDNode>(Node)->getMemOperand(),
2931 cast<AtomicSDNode>(Node)->getOrdering(),
2932 cast<AtomicSDNode>(Node)->getOrdering(),
2933 cast<AtomicSDNode>(Node)->getSynchScope());
2934 Results.push_back(Swap.getValue(0));
2935 Results.push_back(Swap.getValue(1));
2938 case ISD::ATOMIC_STORE: {
2939 // There is no libcall for atomic store; fake it with ATOMIC_SWAP.
2940 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
2941 cast<AtomicSDNode>(Node)->getMemoryVT(),
2942 Node->getOperand(0),
2943 Node->getOperand(1), Node->getOperand(2),
2944 cast<AtomicSDNode>(Node)->getMemOperand(),
2945 cast<AtomicSDNode>(Node)->getOrdering(),
2946 cast<AtomicSDNode>(Node)->getSynchScope());
2947 Results.push_back(Swap.getValue(1));
2950 // By default, atomic intrinsics are marked Legal and lowered. Targets
2951 // which don't support them directly, however, may want libcalls, in which
2952 // case they mark them Expand, and we get here.
2953 case ISD::ATOMIC_SWAP:
2954 case ISD::ATOMIC_LOAD_ADD:
2955 case ISD::ATOMIC_LOAD_SUB:
2956 case ISD::ATOMIC_LOAD_AND:
2957 case ISD::ATOMIC_LOAD_OR:
2958 case ISD::ATOMIC_LOAD_XOR:
2959 case ISD::ATOMIC_LOAD_NAND:
2960 case ISD::ATOMIC_LOAD_MIN:
2961 case ISD::ATOMIC_LOAD_MAX:
2962 case ISD::ATOMIC_LOAD_UMIN:
2963 case ISD::ATOMIC_LOAD_UMAX:
2964 case ISD::ATOMIC_CMP_SWAP: {
2965 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node);
2966 Results.push_back(Tmp.first);
2967 Results.push_back(Tmp.second);
2970 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
2971 // Expanding an ATOMIC_CMP_SWAP_WITH_SUCCESS produces an ATOMIC_CMP_SWAP and
2972 // splits out the success value as a comparison. Expanding the resulting
2973 // ATOMIC_CMP_SWAP will produce a libcall.
2974 SDVTList VTs = DAG.getVTList(Node->getValueType(0), MVT::Other);
2975 SDValue Res = DAG.getAtomicCmpSwap(
2976 ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
2977 Node->getOperand(0), Node->getOperand(1), Node->getOperand(2),
2978 Node->getOperand(3), cast<MemSDNode>(Node)->getMemOperand(),
2979 cast<AtomicSDNode>(Node)->getSuccessOrdering(),
2980 cast<AtomicSDNode>(Node)->getFailureOrdering(),
2981 cast<AtomicSDNode>(Node)->getSynchScope());
2983 SDValue Success = DAG.getSetCC(SDLoc(Node), Node->getValueType(1),
2984 Res, Node->getOperand(2), ISD::SETEQ);
2986 Results.push_back(Res.getValue(0));
2987 Results.push_back(Success);
2988 Results.push_back(Res.getValue(1));
2991 case ISD::DYNAMIC_STACKALLOC:
2992 ExpandDYNAMIC_STACKALLOC(Node, Results);
2994 case ISD::MERGE_VALUES:
2995 for (unsigned i = 0; i < Node->getNumValues(); i++)
2996 Results.push_back(Node->getOperand(i));
2999 EVT VT = Node->getValueType(0);
3001 Results.push_back(DAG.getConstant(0, dl, VT));
3003 assert(VT.isFloatingPoint() && "Unknown value type!");
3004 Results.push_back(DAG.getConstantFP(0, dl, VT));
3009 // If this operation is not supported, lower it to 'abort()' call
3010 TargetLowering::ArgListTy Args;
3011 TargetLowering::CallLoweringInfo CLI(DAG);
3013 .setChain(Node->getOperand(0))
3014 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
3015 DAG.getExternalSymbol("abort",
3016 TLI.getPointerTy(DAG.getDataLayout())),
3017 std::move(Args), 0);
3018 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
3020 Results.push_back(CallResult.second);
3025 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3026 Node->getValueType(0), dl);
3027 Results.push_back(Tmp1);
3029 case ISD::FP_EXTEND:
3030 Tmp1 = EmitStackConvert(Node->getOperand(0),
3031 Node->getOperand(0).getValueType(),
3032 Node->getValueType(0), dl);
3033 Results.push_back(Tmp1);
3035 case ISD::SIGN_EXTEND_INREG: {
3036 // NOTE: we could fall back on load/store here too for targets without
3037 // SAR. However, it is doubtful that any exist.
3038 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3039 EVT VT = Node->getValueType(0);
3040 EVT ShiftAmountTy = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
3043 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
3044 ExtraVT.getScalarType().getSizeInBits();
3045 SDValue ShiftCst = DAG.getConstant(BitsDiff, dl, ShiftAmountTy);
3046 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
3047 Node->getOperand(0), ShiftCst);
3048 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
3049 Results.push_back(Tmp1);
3052 case ISD::FP_ROUND_INREG: {
3053 // The only way we can lower this is to turn it into a TRUNCSTORE,
3054 // EXTLOAD pair, targeting a temporary location (a stack slot).
3056 // NOTE: there is a choice here between constantly creating new stack
3057 // slots and always reusing the same one. We currently always create
3058 // new ones, as reuse may inhibit scheduling.
3059 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3060 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
3061 Node->getValueType(0), dl);
3062 Results.push_back(Tmp1);
3065 case ISD::SINT_TO_FP:
3066 case ISD::UINT_TO_FP:
3067 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
3068 Node->getOperand(0), Node->getValueType(0), dl);
3069 Results.push_back(Tmp1);
3071 case ISD::FP_TO_SINT:
3072 if (TLI.expandFP_TO_SINT(Node, Tmp1, DAG))
3073 Results.push_back(Tmp1);
3075 case ISD::FP_TO_UINT: {
3076 SDValue True, False;
3077 EVT VT = Node->getOperand(0).getValueType();
3078 EVT NVT = Node->getValueType(0);
3079 APFloat apf(DAG.EVTToAPFloatSemantics(VT),
3080 APInt::getNullValue(VT.getSizeInBits()));
3081 APInt x = APInt::getSignBit(NVT.getSizeInBits());
3082 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
3083 Tmp1 = DAG.getConstantFP(apf, dl, VT);
3084 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(VT),
3085 Node->getOperand(0),
3087 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
3088 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
3089 DAG.getNode(ISD::FSUB, dl, VT,
3090 Node->getOperand(0), Tmp1));
3091 False = DAG.getNode(ISD::XOR, dl, NVT, False,
3092 DAG.getConstant(x, dl, NVT));
3093 Tmp1 = DAG.getSelect(dl, NVT, Tmp2, True, False);
3094 Results.push_back(Tmp1);
3098 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3099 EVT VT = Node->getValueType(0);
3100 Tmp1 = Node->getOperand(0);
3101 Tmp2 = Node->getOperand(1);
3102 unsigned Align = Node->getConstantOperandVal(3);
3104 SDValue VAListLoad =
3105 DAG.getLoad(TLI.getPointerTy(DAG.getDataLayout()), dl, Tmp1, Tmp2,
3106 MachinePointerInfo(V), false, false, false, 0);
3107 SDValue VAList = VAListLoad;
3109 if (Align > TLI.getMinStackArgumentAlignment()) {
3110 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
3112 VAList = DAG.getNode(ISD::ADD, dl, VAList.getValueType(), VAList,
3113 DAG.getConstant(Align - 1, dl,
3114 VAList.getValueType()));
3116 VAList = DAG.getNode(ISD::AND, dl, VAList.getValueType(), VAList,
3117 DAG.getConstant(-(int64_t)Align, dl,
3118 VAList.getValueType()));
3121 // Increment the pointer, VAList, to the next vaarg
3122 Tmp3 = DAG.getNode(ISD::ADD, dl, VAList.getValueType(), VAList,
3123 DAG.getConstant(DAG.getDataLayout().getTypeAllocSize(
3124 VT.getTypeForEVT(*DAG.getContext())),
3125 dl, VAList.getValueType()));
3126 // Store the incremented VAList to the legalized pointer
3127 Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2,
3128 MachinePointerInfo(V), false, false, 0);
3129 // Load the actual argument out of the pointer VAList
3130 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(),
3131 false, false, false, 0));
3132 Results.push_back(Results[0].getValue(1));
3136 // This defaults to loading a pointer from the input and storing it to the
3137 // output, returning the chain.
3138 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3139 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3140 Tmp1 = DAG.getLoad(TLI.getPointerTy(DAG.getDataLayout()), dl,
3141 Node->getOperand(0), Node->getOperand(2),
3142 MachinePointerInfo(VS), false, false, false, 0);
3143 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1),
3144 MachinePointerInfo(VD), false, false, 0);
3145 Results.push_back(Tmp1);
3148 case ISD::EXTRACT_VECTOR_ELT:
3149 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
3150 // This must be an access of the only element. Return it.
3151 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
3152 Node->getOperand(0));
3154 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
3155 Results.push_back(Tmp1);
3157 case ISD::EXTRACT_SUBVECTOR:
3158 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
3160 case ISD::INSERT_SUBVECTOR:
3161 Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0)));
3163 case ISD::CONCAT_VECTORS: {
3164 Results.push_back(ExpandVectorBuildThroughStack(Node));
3167 case ISD::SCALAR_TO_VECTOR:
3168 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
3170 case ISD::INSERT_VECTOR_ELT:
3171 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
3172 Node->getOperand(1),
3173 Node->getOperand(2), dl));
3175 case ISD::VECTOR_SHUFFLE: {
3176 SmallVector<int, 32> NewMask;
3177 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
3179 EVT VT = Node->getValueType(0);
3180 EVT EltVT = VT.getVectorElementType();
3181 SDValue Op0 = Node->getOperand(0);
3182 SDValue Op1 = Node->getOperand(1);
3183 if (!TLI.isTypeLegal(EltVT)) {
3185 EVT NewEltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
3187 // BUILD_VECTOR operands are allowed to be wider than the element type.
3188 // But if NewEltVT is smaller that EltVT the BUILD_VECTOR does not accept
3190 if (NewEltVT.bitsLT(EltVT)) {
3192 // Convert shuffle node.
3193 // If original node was v4i64 and the new EltVT is i32,
3194 // cast operands to v8i32 and re-build the mask.
3196 // Calculate new VT, the size of the new VT should be equal to original.
3198 EVT::getVectorVT(*DAG.getContext(), NewEltVT,
3199 VT.getSizeInBits() / NewEltVT.getSizeInBits());
3200 assert(NewVT.bitsEq(VT));
3202 // cast operands to new VT
3203 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0);
3204 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1);
3206 // Convert the shuffle mask
3207 unsigned int factor =
3208 NewVT.getVectorNumElements()/VT.getVectorNumElements();
3210 // EltVT gets smaller
3213 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
3215 for (unsigned fi = 0; fi < factor; ++fi)
3216 NewMask.push_back(Mask[i]);
3219 for (unsigned fi = 0; fi < factor; ++fi)
3220 NewMask.push_back(Mask[i]*factor+fi);
3228 unsigned NumElems = VT.getVectorNumElements();
3229 SmallVector<SDValue, 16> Ops;
3230 for (unsigned i = 0; i != NumElems; ++i) {
3232 Ops.push_back(DAG.getUNDEF(EltVT));
3235 unsigned Idx = Mask[i];
3237 Ops.push_back(DAG.getNode(
3238 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0,
3239 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout()))));
3241 Ops.push_back(DAG.getNode(
3242 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op1,
3243 DAG.getConstant(Idx - NumElems, dl,
3244 TLI.getVectorIdxTy(DAG.getDataLayout()))));
3247 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
3248 // We may have changed the BUILD_VECTOR type. Cast it back to the Node type.
3249 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), Tmp1);
3250 Results.push_back(Tmp1);
3253 case ISD::EXTRACT_ELEMENT: {
3254 EVT OpTy = Node->getOperand(0).getValueType();
3255 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
3257 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
3258 DAG.getConstant(OpTy.getSizeInBits() / 2, dl,
3259 TLI.getShiftAmountTy(
3260 Node->getOperand(0).getValueType(),
3261 DAG.getDataLayout())));
3262 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
3265 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
3266 Node->getOperand(0));
3268 Results.push_back(Tmp1);
3271 case ISD::STACKSAVE:
3272 // Expand to CopyFromReg if the target set
3273 // StackPointerRegisterToSaveRestore.
3274 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3275 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
3276 Node->getValueType(0)));
3277 Results.push_back(Results[0].getValue(1));
3279 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
3280 Results.push_back(Node->getOperand(0));
3283 case ISD::STACKRESTORE:
3284 // Expand to CopyToReg if the target set
3285 // StackPointerRegisterToSaveRestore.
3286 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3287 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
3288 Node->getOperand(1)));
3290 Results.push_back(Node->getOperand(0));
3293 case ISD::FCOPYSIGN:
3294 Results.push_back(ExpandFCOPYSIGN(Node));
3297 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3298 Tmp1 = DAG.getConstantFP(-0.0, dl, Node->getValueType(0));
3299 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
3300 Node->getOperand(0));
3301 Results.push_back(Tmp1);
3304 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3305 EVT VT = Node->getValueType(0);
3306 Tmp1 = Node->getOperand(0);
3307 Tmp2 = DAG.getConstantFP(0.0, dl, VT);
3308 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(Tmp1.getValueType()),
3309 Tmp1, Tmp2, ISD::SETUGT);
3310 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
3311 Tmp1 = DAG.getSelect(dl, VT, Tmp2, Tmp1, Tmp3);
3312 Results.push_back(Tmp1);
3319 // Expand Y = MAX(A, B) -> Y = (A > B) ? A : B
3321 switch (Node->getOpcode()) {
3322 default: llvm_unreachable("How did we get here?");
3323 case ISD::SMAX: Pred = ISD::SETGT; break;
3324 case ISD::SMIN: Pred = ISD::SETLT; break;
3325 case ISD::UMAX: Pred = ISD::SETUGT; break;
3326 case ISD::UMIN: Pred = ISD::SETULT; break;
3328 Tmp1 = Node->getOperand(0);
3329 Tmp2 = Node->getOperand(1);
3330 Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp1, Tmp2, Pred);
3331 Results.push_back(Tmp1);
3336 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMIN_F32, RTLIB::FMIN_F64,
3337 RTLIB::FMIN_F80, RTLIB::FMIN_F128,
3338 RTLIB::FMIN_PPCF128));
3341 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMAX_F32, RTLIB::FMAX_F64,
3342 RTLIB::FMAX_F80, RTLIB::FMAX_F128,
3343 RTLIB::FMAX_PPCF128));
3346 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3347 RTLIB::SQRT_F80, RTLIB::SQRT_F128,
3348 RTLIB::SQRT_PPCF128));
3352 EVT VT = Node->getValueType(0);
3353 bool isSIN = Node->getOpcode() == ISD::FSIN;
3354 // Turn fsin / fcos into ISD::FSINCOS node if there are a pair of fsin /
3355 // fcos which share the same operand and both are used.
3356 if ((TLI.isOperationLegalOrCustom(ISD::FSINCOS, VT) ||
3357 canCombineSinCosLibcall(Node, TLI, TM))
3358 && useSinCos(Node)) {
3359 SDVTList VTs = DAG.getVTList(VT, VT);
3360 Tmp1 = DAG.getNode(ISD::FSINCOS, dl, VTs, Node->getOperand(0));
3362 Tmp1 = Tmp1.getValue(1);
3363 Results.push_back(Tmp1);
3365 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
3366 RTLIB::SIN_F80, RTLIB::SIN_F128,
3367 RTLIB::SIN_PPCF128));
3369 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
3370 RTLIB::COS_F80, RTLIB::COS_F128,
3371 RTLIB::COS_PPCF128));
3376 // Expand into sincos libcall.
3377 ExpandSinCosLibCall(Node, Results);
3380 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
3381 RTLIB::LOG_F80, RTLIB::LOG_F128,
3382 RTLIB::LOG_PPCF128));
3385 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3386 RTLIB::LOG2_F80, RTLIB::LOG2_F128,
3387 RTLIB::LOG2_PPCF128));
3390 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3391 RTLIB::LOG10_F80, RTLIB::LOG10_F128,
3392 RTLIB::LOG10_PPCF128));
3395 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
3396 RTLIB::EXP_F80, RTLIB::EXP_F128,
3397 RTLIB::EXP_PPCF128));
3400 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3401 RTLIB::EXP2_F80, RTLIB::EXP2_F128,
3402 RTLIB::EXP2_PPCF128));
3405 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3406 RTLIB::TRUNC_F80, RTLIB::TRUNC_F128,
3407 RTLIB::TRUNC_PPCF128));
3410 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3411 RTLIB::FLOOR_F80, RTLIB::FLOOR_F128,
3412 RTLIB::FLOOR_PPCF128));
3415 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3416 RTLIB::CEIL_F80, RTLIB::CEIL_F128,
3417 RTLIB::CEIL_PPCF128));
3420 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
3421 RTLIB::RINT_F80, RTLIB::RINT_F128,
3422 RTLIB::RINT_PPCF128));
3424 case ISD::FNEARBYINT:
3425 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
3426 RTLIB::NEARBYINT_F64,
3427 RTLIB::NEARBYINT_F80,
3428 RTLIB::NEARBYINT_F128,
3429 RTLIB::NEARBYINT_PPCF128));
3432 Results.push_back(ExpandFPLibCall(Node, RTLIB::ROUND_F32,
3436 RTLIB::ROUND_PPCF128));
3439 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
3440 RTLIB::POWI_F80, RTLIB::POWI_F128,
3441 RTLIB::POWI_PPCF128));
3444 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
3445 RTLIB::POW_F80, RTLIB::POW_F128,
3446 RTLIB::POW_PPCF128));
3449 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
3450 RTLIB::DIV_F80, RTLIB::DIV_F128,
3451 RTLIB::DIV_PPCF128));
3454 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
3455 RTLIB::REM_F80, RTLIB::REM_F128,
3456 RTLIB::REM_PPCF128));
3459 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMA_F32, RTLIB::FMA_F64,
3460 RTLIB::FMA_F80, RTLIB::FMA_F128,
3461 RTLIB::FMA_PPCF128));
3464 llvm_unreachable("Illegal fmad should never be formed");
3467 Results.push_back(ExpandFPLibCall(Node, RTLIB::ADD_F32, RTLIB::ADD_F64,
3468 RTLIB::ADD_F80, RTLIB::ADD_F128,
3469 RTLIB::ADD_PPCF128));
3472 Results.push_back(ExpandFPLibCall(Node, RTLIB::MUL_F32, RTLIB::MUL_F64,
3473 RTLIB::MUL_F80, RTLIB::MUL_F128,
3474 RTLIB::MUL_PPCF128));
3476 case ISD::FP16_TO_FP: {
3477 if (Node->getValueType(0) == MVT::f32) {
3478 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
3482 // We can extend to types bigger than f32 in two steps without changing the
3483 // result. Since "f16 -> f32" is much more commonly available, give CodeGen
3484 // the option of emitting that before resorting to a libcall.
3486 DAG.getNode(ISD::FP16_TO_FP, dl, MVT::f32, Node->getOperand(0));
3488 DAG.getNode(ISD::FP_EXTEND, dl, Node->getValueType(0), Res));
3491 case ISD::FP_TO_FP16: {
3492 if (!TLI.useSoftFloat() && TM.Options.UnsafeFPMath) {
3493 SDValue Op = Node->getOperand(0);
3494 MVT SVT = Op.getSimpleValueType();
3495 if ((SVT == MVT::f64 || SVT == MVT::f80) &&
3496 TLI.isOperationLegalOrCustom(ISD::FP_TO_FP16, MVT::f32)) {
3497 // Under fastmath, we can expand this node into a fround followed by
3498 // a float-half conversion.
3499 SDValue FloatVal = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Op,
3500 DAG.getIntPtrConstant(0, dl));
3502 DAG.getNode(ISD::FP_TO_FP16, dl, MVT::i16, FloatVal));
3508 RTLIB::getFPROUND(Node->getOperand(0).getValueType(), MVT::f16);
3509 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unable to expand fp_to_fp16");
3510 Results.push_back(ExpandLibCall(LC, Node, false));
3513 case ISD::ConstantFP: {
3514 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
3515 // Check to see if this FP immediate is already legal.
3516 // If this is a legal constant, turn it into a TargetConstantFP node.
3517 if (!TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
3518 Results.push_back(ExpandConstantFP(CFP, true));
3522 EVT VT = Node->getValueType(0);
3523 if (TLI.isOperationLegalOrCustom(ISD::FADD, VT) &&
3524 TLI.isOperationLegalOrCustom(ISD::FNEG, VT)) {
3525 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1));
3526 Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1);
3527 Results.push_back(Tmp1);
3529 Results.push_back(ExpandFPLibCall(Node, RTLIB::SUB_F32, RTLIB::SUB_F64,
3530 RTLIB::SUB_F80, RTLIB::SUB_F128,
3531 RTLIB::SUB_PPCF128));
3536 EVT VT = Node->getValueType(0);
3537 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3538 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3539 "Don't know how to expand this subtraction!");
3540 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3541 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), dl,
3543 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, dl, VT));
3544 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3549 EVT VT = Node->getValueType(0);
3550 bool isSigned = Node->getOpcode() == ISD::SREM;
3551 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3552 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3553 Tmp2 = Node->getOperand(0);
3554 Tmp3 = Node->getOperand(1);
3555 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3556 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3557 // If div is legal, it's better to do the normal expansion
3558 !TLI.isOperationLegalOrCustom(DivOpc, Node->getValueType(0)) &&
3559 useDivRem(Node, isSigned, false))) {
3560 SDVTList VTs = DAG.getVTList(VT, VT);
3561 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
3562 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
3564 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
3565 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3566 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3567 } else if (isSigned)
3568 Tmp1 = ExpandIntLibCall(Node, true,
3570 RTLIB::SREM_I16, RTLIB::SREM_I32,
3571 RTLIB::SREM_I64, RTLIB::SREM_I128);
3573 Tmp1 = ExpandIntLibCall(Node, false,
3575 RTLIB::UREM_I16, RTLIB::UREM_I32,
3576 RTLIB::UREM_I64, RTLIB::UREM_I128);
3577 Results.push_back(Tmp1);
3582 bool isSigned = Node->getOpcode() == ISD::SDIV;
3583 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3584 EVT VT = Node->getValueType(0);
3585 SDVTList VTs = DAG.getVTList(VT, VT);
3586 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3587 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3588 useDivRem(Node, isSigned, true)))
3589 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
3590 Node->getOperand(1));
3592 Tmp1 = ExpandIntLibCall(Node, true,
3594 RTLIB::SDIV_I16, RTLIB::SDIV_I32,
3595 RTLIB::SDIV_I64, RTLIB::SDIV_I128);
3597 Tmp1 = ExpandIntLibCall(Node, false,
3599 RTLIB::UDIV_I16, RTLIB::UDIV_I32,
3600 RTLIB::UDIV_I64, RTLIB::UDIV_I128);
3601 Results.push_back(Tmp1);
3606 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
3608 EVT VT = Node->getValueType(0);
3609 SDVTList VTs = DAG.getVTList(VT, VT);
3610 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
3611 "If this wasn't legal, it shouldn't have been created!");
3612 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
3613 Node->getOperand(1));
3614 Results.push_back(Tmp1.getValue(1));
3619 // Expand into divrem libcall
3620 ExpandDivRemLibCall(Node, Results);
3623 EVT VT = Node->getValueType(0);
3624 SDVTList VTs = DAG.getVTList(VT, VT);
3625 // See if multiply or divide can be lowered using two-result operations.
3626 // We just need the low half of the multiply; try both the signed
3627 // and unsigned forms. If the target supports both SMUL_LOHI and
3628 // UMUL_LOHI, form a preference by checking which forms of plain
3629 // MULH it supports.
3630 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3631 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3632 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3633 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3634 unsigned OpToUse = 0;
3635 if (HasSMUL_LOHI && !HasMULHS) {
3636 OpToUse = ISD::SMUL_LOHI;
3637 } else if (HasUMUL_LOHI && !HasMULHU) {
3638 OpToUse = ISD::UMUL_LOHI;
3639 } else if (HasSMUL_LOHI) {
3640 OpToUse = ISD::SMUL_LOHI;
3641 } else if (HasUMUL_LOHI) {
3642 OpToUse = ISD::UMUL_LOHI;
3645 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
3646 Node->getOperand(1)));
3651 EVT HalfType = VT.getHalfSizedIntegerVT(*DAG.getContext());
3652 if (TLI.isOperationLegalOrCustom(ISD::ZERO_EXTEND, VT) &&
3653 TLI.isOperationLegalOrCustom(ISD::ANY_EXTEND, VT) &&
3654 TLI.isOperationLegalOrCustom(ISD::SHL, VT) &&
3655 TLI.isOperationLegalOrCustom(ISD::OR, VT) &&
3656 TLI.expandMUL(Node, Lo, Hi, HalfType, DAG)) {
3657 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Lo);
3658 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Hi);
3660 DAG.getConstant(HalfType.getSizeInBits(), dl,
3661 TLI.getShiftAmountTy(HalfType, DAG.getDataLayout()));
3662 Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift);
3663 Results.push_back(DAG.getNode(ISD::OR, dl, VT, Lo, Hi));
3667 Tmp1 = ExpandIntLibCall(Node, false,
3669 RTLIB::MUL_I16, RTLIB::MUL_I32,
3670 RTLIB::MUL_I64, RTLIB::MUL_I128);
3671 Results.push_back(Tmp1);
3676 SDValue LHS = Node->getOperand(0);
3677 SDValue RHS = Node->getOperand(1);
3678 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3679 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3681 Results.push_back(Sum);
3682 EVT ResultType = Node->getValueType(1);
3683 EVT OType = getSetCCResultType(Node->getValueType(0));
3685 SDValue Zero = DAG.getConstant(0, dl, LHS.getValueType());
3687 // LHSSign -> LHS >= 0
3688 // RHSSign -> RHS >= 0
3689 // SumSign -> Sum >= 0
3692 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3694 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3696 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3697 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3698 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
3699 Node->getOpcode() == ISD::SADDO ?
3700 ISD::SETEQ : ISD::SETNE);
3702 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3703 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3705 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3706 Results.push_back(DAG.getBoolExtOrTrunc(Cmp, dl, ResultType, ResultType));
3711 SDValue LHS = Node->getOperand(0);
3712 SDValue RHS = Node->getOperand(1);
3713 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
3714 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3716 Results.push_back(Sum);
3718 EVT ResultType = Node->getValueType(1);
3719 EVT SetCCType = getSetCCResultType(Node->getValueType(0));
3721 = Node->getOpcode() == ISD::UADDO ? ISD::SETULT : ISD::SETUGT;
3722 SDValue SetCC = DAG.getSetCC(dl, SetCCType, Sum, LHS, CC);
3724 Results.push_back(DAG.getBoolExtOrTrunc(SetCC, dl, ResultType, ResultType));
3729 EVT VT = Node->getValueType(0);
3730 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
3731 SDValue LHS = Node->getOperand(0);
3732 SDValue RHS = Node->getOperand(1);
3735 static const unsigned Ops[2][3] =
3736 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
3737 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
3738 bool isSigned = Node->getOpcode() == ISD::SMULO;
3739 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3740 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3741 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3742 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3743 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3745 TopHalf = BottomHalf.getValue(1);
3746 } else if (TLI.isTypeLegal(WideVT)) {
3747 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
3748 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
3749 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
3750 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3751 DAG.getIntPtrConstant(0, dl));
3752 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3753 DAG.getIntPtrConstant(1, dl));
3755 // We can fall back to a libcall with an illegal type for the MUL if we
3756 // have a libcall big enough.
3757 // Also, we can fall back to a division in some cases, but that's a big
3758 // performance hit in the general case.
3759 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3760 if (WideVT == MVT::i16)
3761 LC = RTLIB::MUL_I16;
3762 else if (WideVT == MVT::i32)
3763 LC = RTLIB::MUL_I32;
3764 else if (WideVT == MVT::i64)
3765 LC = RTLIB::MUL_I64;
3766 else if (WideVT == MVT::i128)
3767 LC = RTLIB::MUL_I128;
3768 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!");
3770 // The high part is obtained by SRA'ing all but one of the bits of low
3772 unsigned LoSize = VT.getSizeInBits();
3774 DAG.getNode(ISD::SRA, dl, VT, RHS,
3775 DAG.getConstant(LoSize - 1, dl,
3776 TLI.getPointerTy(DAG.getDataLayout())));
3778 DAG.getNode(ISD::SRA, dl, VT, LHS,
3779 DAG.getConstant(LoSize - 1, dl,
3780 TLI.getPointerTy(DAG.getDataLayout())));
3782 // Here we're passing the 2 arguments explicitly as 4 arguments that are
3783 // pre-lowered to the correct types. This all depends upon WideVT not
3784 // being a legal type for the architecture and thus has to be split to
3786 SDValue Args[] = { LHS, HiLHS, RHS, HiRHS };
3787 SDValue Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl);
3788 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3789 DAG.getIntPtrConstant(0, dl));
3790 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3791 DAG.getIntPtrConstant(1, dl));
3792 // Ret is a node with an illegal type. Because such things are not
3793 // generally permitted during this phase of legalization, make sure the
3794 // node has no more uses. The above EXTRACT_ELEMENT nodes should have been
3796 assert(Ret->use_empty() &&
3797 "Unexpected uses of illegally type from expanded lib call.");
3801 Tmp1 = DAG.getConstant(
3802 VT.getSizeInBits() - 1, dl,
3803 TLI.getShiftAmountTy(BottomHalf.getValueType(), DAG.getDataLayout()));
3804 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3805 TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf, Tmp1,
3808 TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf,
3809 DAG.getConstant(0, dl, VT), ISD::SETNE);
3811 Results.push_back(BottomHalf);
3812 Results.push_back(TopHalf);
3815 case ISD::BUILD_PAIR: {
3816 EVT PairTy = Node->getValueType(0);
3817 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3818 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3820 ISD::SHL, dl, PairTy, Tmp2,
3821 DAG.getConstant(PairTy.getSizeInBits() / 2, dl,
3822 TLI.getShiftAmountTy(PairTy, DAG.getDataLayout())));
3823 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3827 Tmp1 = Node->getOperand(0);
3828 Tmp2 = Node->getOperand(1);
3829 Tmp3 = Node->getOperand(2);
3830 if (Tmp1.getOpcode() == ISD::SETCC) {
3831 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3833 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3835 Tmp1 = DAG.getSelectCC(dl, Tmp1,
3836 DAG.getConstant(0, dl, Tmp1.getValueType()),
3837 Tmp2, Tmp3, ISD::SETNE);
3839 Results.push_back(Tmp1);
3842 SDValue Chain = Node->getOperand(0);
3843 SDValue Table = Node->getOperand(1);
3844 SDValue Index = Node->getOperand(2);
3846 EVT PTy = TLI.getPointerTy(DAG.getDataLayout());
3848 const DataLayout &TD = DAG.getDataLayout();
3849 unsigned EntrySize =
3850 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
3852 Index = DAG.getNode(ISD::MUL, dl, Index.getValueType(), Index,
3853 DAG.getConstant(EntrySize, dl, Index.getValueType()));
3854 SDValue Addr = DAG.getNode(ISD::ADD, dl, Index.getValueType(),
3857 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
3858 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
3859 MachinePointerInfo::getJumpTable(), MemVT,
3860 false, false, false, 0);
3862 if (TM.getRelocationModel() == Reloc::PIC_) {
3863 // For PIC, the sequence is:
3864 // BRIND(load(Jumptable + index) + RelocBase)
3865 // RelocBase can be JumpTable, GOT or some sort of global base.
3866 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3867 TLI.getPICJumpTableRelocBase(Table, DAG));
3869 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
3870 Results.push_back(Tmp1);
3874 // Expand brcond's setcc into its constituent parts and create a BR_CC
3876 Tmp1 = Node->getOperand(0);
3877 Tmp2 = Node->getOperand(1);
3878 if (Tmp2.getOpcode() == ISD::SETCC) {
3879 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3880 Tmp1, Tmp2.getOperand(2),
3881 Tmp2.getOperand(0), Tmp2.getOperand(1),
3882 Node->getOperand(2));
3884 // We test only the i1 bit. Skip the AND if UNDEF.
3885 Tmp3 = (Tmp2.getOpcode() == ISD::UNDEF) ? Tmp2 :
3886 DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2,
3887 DAG.getConstant(1, dl, Tmp2.getValueType()));
3888 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3889 DAG.getCondCode(ISD::SETNE), Tmp3,
3890 DAG.getConstant(0, dl, Tmp3.getValueType()),
3891 Node->getOperand(2));
3893 Results.push_back(Tmp1);
3896 Tmp1 = Node->getOperand(0);
3897 Tmp2 = Node->getOperand(1);
3898 Tmp3 = Node->getOperand(2);
3899 bool Legalized = LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2,
3900 Tmp3, NeedInvert, dl);
3903 // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3904 // condition code, create a new SETCC node.
3906 Tmp1 = DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3909 // If we expanded the SETCC by inverting the condition code, then wrap
3910 // the existing SETCC in a NOT to restore the intended condition.
3912 Tmp1 = DAG.getLogicalNOT(dl, Tmp1, Tmp1->getValueType(0));
3914 Results.push_back(Tmp1);
3918 // Otherwise, SETCC for the given comparison type must be completely
3919 // illegal; expand it into a SELECT_CC.
3920 EVT VT = Node->getValueType(0);
3922 switch (TLI.getBooleanContents(Tmp1->getValueType(0))) {
3923 case TargetLowering::ZeroOrOneBooleanContent:
3924 case TargetLowering::UndefinedBooleanContent:
3927 case TargetLowering::ZeroOrNegativeOneBooleanContent:
3931 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3932 DAG.getConstant(TrueValue, dl, VT),
3933 DAG.getConstant(0, dl, VT),
3935 Results.push_back(Tmp1);
3938 case ISD::SELECT_CC: {
3939 Tmp1 = Node->getOperand(0); // LHS
3940 Tmp2 = Node->getOperand(1); // RHS
3941 Tmp3 = Node->getOperand(2); // True
3942 Tmp4 = Node->getOperand(3); // False
3943 EVT VT = Node->getValueType(0);
3944 SDValue CC = Node->getOperand(4);
3945 ISD::CondCode CCOp = cast<CondCodeSDNode>(CC)->get();
3947 if (TLI.isCondCodeLegal(CCOp, Tmp1.getSimpleValueType())) {
3948 // If the condition code is legal, then we need to expand this
3949 // node using SETCC and SELECT.
3950 EVT CmpVT = Tmp1.getValueType();
3951 assert(!TLI.isOperationExpand(ISD::SELECT, VT) &&
3952 "Cannot expand ISD::SELECT_CC when ISD::SELECT also needs to be "
3955 TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), CmpVT);
3956 SDValue Cond = DAG.getNode(ISD::SETCC, dl, CCVT, Tmp1, Tmp2, CC);
3957 Results.push_back(DAG.getSelect(dl, VT, Cond, Tmp3, Tmp4));
3961 // SELECT_CC is legal, so the condition code must not be.
3962 bool Legalized = false;
3963 // Try to legalize by inverting the condition. This is for targets that
3964 // might support an ordered version of a condition, but not the unordered
3965 // version (or vice versa).
3966 ISD::CondCode InvCC = ISD::getSetCCInverse(CCOp,
3967 Tmp1.getValueType().isInteger());
3968 if (TLI.isCondCodeLegal(InvCC, Tmp1.getSimpleValueType())) {
3969 // Use the new condition code and swap true and false
3971 Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp4, Tmp3, InvCC);
3973 // If The inverse is not legal, then try to swap the arguments using
3974 // the inverse condition code.
3975 ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(InvCC);
3976 if (TLI.isCondCodeLegal(SwapInvCC, Tmp1.getSimpleValueType())) {
3977 // The swapped inverse condition is legal, so swap true and false,
3980 Tmp1 = DAG.getSelectCC(dl, Tmp2, Tmp1, Tmp4, Tmp3, SwapInvCC);
3985 Legalized = LegalizeSetCCCondCode(
3986 getSetCCResultType(Tmp1.getValueType()), Tmp1, Tmp2, CC, NeedInvert,
3989 assert(Legalized && "Can't legalize SELECT_CC with legal condition!");
3991 // If we expanded the SETCC by inverting the condition code, then swap
3992 // the True/False operands to match.
3994 std::swap(Tmp3, Tmp4);
3996 // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3997 // condition code, create a new SELECT_CC node.
3999 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0),
4000 Tmp1, Tmp2, Tmp3, Tmp4, CC);
4002 Tmp2 = DAG.getConstant(0, dl, Tmp1.getValueType());
4003 CC = DAG.getCondCode(ISD::SETNE);
4004 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1,
4005 Tmp2, Tmp3, Tmp4, CC);
4008 Results.push_back(Tmp1);
4012 Tmp1 = Node->getOperand(0); // Chain
4013 Tmp2 = Node->getOperand(2); // LHS
4014 Tmp3 = Node->getOperand(3); // RHS
4015 Tmp4 = Node->getOperand(1); // CC
4017 bool Legalized = LegalizeSetCCCondCode(getSetCCResultType(
4018 Tmp2.getValueType()), Tmp2, Tmp3, Tmp4, NeedInvert, dl);
4020 assert(Legalized && "Can't legalize BR_CC with legal condition!");
4022 // If we expanded the SETCC by inverting the condition code, then wrap
4023 // the existing SETCC in a NOT to restore the intended condition.
4025 Tmp4 = DAG.getNOT(dl, Tmp4, Tmp4->getValueType(0));
4027 // If we expanded the SETCC by swapping LHS and RHS, create a new BR_CC
4029 if (Tmp4.getNode()) {
4030 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1,
4031 Tmp4, Tmp2, Tmp3, Node->getOperand(4));
4033 Tmp3 = DAG.getConstant(0, dl, Tmp2.getValueType());
4034 Tmp4 = DAG.getCondCode(ISD::SETNE);
4035 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4,
4036 Tmp2, Tmp3, Node->getOperand(4));
4038 Results.push_back(Tmp1);
4041 case ISD::BUILD_VECTOR:
4042 Results.push_back(ExpandBUILD_VECTOR(Node));
4047 // Scalarize vector SRA/SRL/SHL.
4048 EVT VT = Node->getValueType(0);
4049 assert(VT.isVector() && "Unable to legalize non-vector shift");
4050 assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
4051 unsigned NumElem = VT.getVectorNumElements();
4053 SmallVector<SDValue, 8> Scalars;
4054 for (unsigned Idx = 0; Idx < NumElem; Idx++) {
4055 SDValue Ex = DAG.getNode(
4056 ISD::EXTRACT_VECTOR_ELT, dl, VT.getScalarType(), Node->getOperand(0),
4057 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
4058 SDValue Sh = DAG.getNode(
4059 ISD::EXTRACT_VECTOR_ELT, dl, VT.getScalarType(), Node->getOperand(1),
4060 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
4061 Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
4062 VT.getScalarType(), Ex, Sh));
4065 DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0), Scalars);
4066 ReplaceNode(SDValue(Node, 0), Result);
4069 case ISD::GLOBAL_OFFSET_TABLE:
4070 case ISD::GlobalAddress:
4071 case ISD::GlobalTLSAddress:
4072 case ISD::ExternalSymbol:
4073 case ISD::ConstantPool:
4074 case ISD::JumpTable:
4075 case ISD::INTRINSIC_W_CHAIN:
4076 case ISD::INTRINSIC_WO_CHAIN:
4077 case ISD::INTRINSIC_VOID:
4078 // FIXME: Custom lowering for these operations shouldn't return null!
4082 // Replace the original node with the legalized result.
4083 if (!Results.empty())
4084 ReplaceNode(Node, Results.data());
4087 void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
4088 SmallVector<SDValue, 8> Results;
4089 MVT OVT = Node->getSimpleValueType(0);
4090 if (Node->getOpcode() == ISD::UINT_TO_FP ||
4091 Node->getOpcode() == ISD::SINT_TO_FP ||
4092 Node->getOpcode() == ISD::SETCC) {
4093 OVT = Node->getOperand(0).getSimpleValueType();
4095 if (Node->getOpcode() == ISD::BR_CC)
4096 OVT = Node->getOperand(2).getSimpleValueType();
4097 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
4099 SDValue Tmp1, Tmp2, Tmp3;
4100 switch (Node->getOpcode()) {
4102 case ISD::CTTZ_ZERO_UNDEF:
4104 case ISD::CTLZ_ZERO_UNDEF:
4106 // Zero extend the argument.
4107 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4108 // Perform the larger operation. For CTPOP and CTTZ_ZERO_UNDEF, this is
4109 // already the correct result.
4110 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4111 if (Node->getOpcode() == ISD::CTTZ) {
4112 // FIXME: This should set a bit in the zero extended value instead.
4113 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT),
4114 Tmp1, DAG.getConstant(NVT.getSizeInBits(), dl, NVT),
4116 Tmp1 = DAG.getSelect(dl, NVT, Tmp2,
4117 DAG.getConstant(OVT.getSizeInBits(), dl, NVT), Tmp1);
4118 } else if (Node->getOpcode() == ISD::CTLZ ||
4119 Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) {
4120 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4121 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
4122 DAG.getConstant(NVT.getSizeInBits() -
4123 OVT.getSizeInBits(), dl, NVT));
4125 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
4128 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
4129 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4130 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
4132 ISD::SRL, dl, NVT, Tmp1,
4133 DAG.getConstant(DiffBits, dl,
4134 TLI.getShiftAmountTy(NVT, DAG.getDataLayout())));
4135 Results.push_back(Tmp1);
4138 case ISD::FP_TO_UINT:
4139 case ISD::FP_TO_SINT:
4140 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
4141 Node->getOpcode() == ISD::FP_TO_SINT, dl);
4142 Results.push_back(Tmp1);
4144 case ISD::UINT_TO_FP:
4145 case ISD::SINT_TO_FP:
4146 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
4147 Node->getOpcode() == ISD::SINT_TO_FP, dl);
4148 Results.push_back(Tmp1);
4151 SDValue Chain = Node->getOperand(0); // Get the chain.
4152 SDValue Ptr = Node->getOperand(1); // Get the pointer.
4155 if (OVT.isVector()) {
4156 TruncOp = ISD::BITCAST;
4158 assert(OVT.isInteger()
4159 && "VAARG promotion is supported only for vectors or integer types");
4160 TruncOp = ISD::TRUNCATE;
4163 // Perform the larger operation, then convert back
4164 Tmp1 = DAG.getVAArg(NVT, dl, Chain, Ptr, Node->getOperand(2),
4165 Node->getConstantOperandVal(3));
4166 Chain = Tmp1.getValue(1);
4168 Tmp2 = DAG.getNode(TruncOp, dl, OVT, Tmp1);
4170 // Modified the chain result - switch anything that used the old chain to
4172 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp2);
4173 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
4175 UpdatedNodes->insert(Tmp2.getNode());
4176 UpdatedNodes->insert(Chain.getNode());
4184 unsigned ExtOp, TruncOp;
4185 if (OVT.isVector()) {
4186 ExtOp = ISD::BITCAST;
4187 TruncOp = ISD::BITCAST;
4189 assert(OVT.isInteger() && "Cannot promote logic operation");
4190 ExtOp = ISD::ANY_EXTEND;
4191 TruncOp = ISD::TRUNCATE;
4193 // Promote each of the values to the new type.
4194 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4195 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4196 // Perform the larger operation, then convert back
4197 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4198 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
4202 unsigned ExtOp, TruncOp;
4203 if (Node->getValueType(0).isVector() ||
4204 Node->getValueType(0).getSizeInBits() == NVT.getSizeInBits()) {
4205 ExtOp = ISD::BITCAST;
4206 TruncOp = ISD::BITCAST;
4207 } else if (Node->getValueType(0).isInteger()) {
4208 ExtOp = ISD::ANY_EXTEND;
4209 TruncOp = ISD::TRUNCATE;
4211 ExtOp = ISD::FP_EXTEND;
4212 TruncOp = ISD::FP_ROUND;
4214 Tmp1 = Node->getOperand(0);
4215 // Promote each of the values to the new type.
4216 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4217 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
4218 // Perform the larger operation, then round down.
4219 Tmp1 = DAG.getSelect(dl, NVT, Tmp1, Tmp2, Tmp3);
4220 if (TruncOp != ISD::FP_ROUND)
4221 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
4223 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
4224 DAG.getIntPtrConstant(0, dl));
4225 Results.push_back(Tmp1);
4228 case ISD::VECTOR_SHUFFLE: {
4229 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
4231 // Cast the two input vectors.
4232 Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
4233 Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
4235 // Convert the shuffle mask to the right # elements.
4236 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
4237 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
4238 Results.push_back(Tmp1);
4242 unsigned ExtOp = ISD::FP_EXTEND;
4243 if (NVT.isInteger()) {
4244 ISD::CondCode CCCode =
4245 cast<CondCodeSDNode>(Node->getOperand(2))->get();
4246 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4248 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4249 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4250 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
4251 Tmp1, Tmp2, Node->getOperand(2)));
4255 unsigned ExtOp = ISD::FP_EXTEND;
4256 if (NVT.isInteger()) {
4257 ISD::CondCode CCCode =
4258 cast<CondCodeSDNode>(Node->getOperand(1))->get();
4259 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4261 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
4262 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(3));
4263 Results.push_back(DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0),
4264 Node->getOperand(0), Node->getOperand(1),
4265 Tmp1, Tmp2, Node->getOperand(4)));
4275 case ISD::FCOPYSIGN:
4277 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4278 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
4279 Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4280 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4281 Tmp3, DAG.getIntPtrConstant(0, dl)));
4285 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4286 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
4287 Tmp3 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(2));
4289 DAG.getNode(ISD::FP_ROUND, dl, OVT,
4290 DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2, Tmp3),
4291 DAG.getIntPtrConstant(0, dl)));
4295 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4296 Tmp2 = Node->getOperand(1);
4297 Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4298 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4299 Tmp3, DAG.getIntPtrConstant(0, dl)));
4305 case ISD::FNEARBYINT:
4318 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4319 Tmp2 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4320 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4321 Tmp2, DAG.getIntPtrConstant(0, dl)));
4326 // Replace the original node with the legalized result.
4327 if (!Results.empty())
4328 ReplaceNode(Node, Results.data());
4331 /// This is the entry point for the file.
4332 void SelectionDAG::Legalize() {
4333 AssignTopologicalOrder();
4335 SmallPtrSet<SDNode *, 16> LegalizedNodes;
4336 SelectionDAGLegalize Legalizer(*this, LegalizedNodes);
4338 // Visit all the nodes. We start in topological order, so that we see
4339 // nodes with their original operands intact. Legalization can produce
4340 // new nodes which may themselves need to be legalized. Iterate until all
4341 // nodes have been legalized.
4343 bool AnyLegalized = false;
4344 for (auto NI = allnodes_end(); NI != allnodes_begin();) {
4348 if (N->use_empty() && N != getRoot().getNode()) {
4354 if (LegalizedNodes.insert(N).second) {
4355 AnyLegalized = true;
4356 Legalizer.LegalizeOp(N);
4358 if (N->use_empty() && N != getRoot().getNode()) {
4369 // Remove dead nodes now.
4373 bool SelectionDAG::LegalizeOp(SDNode *N,
4374 SmallSetVector<SDNode *, 16> &UpdatedNodes) {
4375 SmallPtrSet<SDNode *, 16> LegalizedNodes;
4376 SelectionDAGLegalize Legalizer(*this, LegalizedNodes, &UpdatedNodes);
4378 // Directly insert the node in question, and legalize it. This will recurse
4379 // as needed through operands.
4380 LegalizedNodes.insert(N);
4381 Legalizer.LegalizeOp(N);
4383 return LegalizedNodes.count(N);