1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/CodeGen/PseudoSourceValue.h"
20 #include "llvm/Target/TargetFrameInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/Target/TargetData.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/Target/TargetSubtarget.h"
26 #include "llvm/CallingConv.h"
27 #include "llvm/Constants.h"
28 #include "llvm/DerivedTypes.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Compiler.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/ADT/DenseMap.h"
33 #include "llvm/ADT/SmallVector.h"
34 #include "llvm/ADT/SmallPtrSet.h"
40 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
41 cl::desc("Pop up a window to show dags before legalize"));
43 static const bool ViewLegalizeDAGs = 0;
46 //===----------------------------------------------------------------------===//
47 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
48 /// hacks on it until the target machine can handle it. This involves
49 /// eliminating value sizes the machine cannot handle (promoting small sizes to
50 /// large sizes or splitting up large values into small values) as well as
51 /// eliminating operations the machine cannot handle.
53 /// This code also does a small amount of optimization and recognition of idioms
54 /// as part of its processing. For example, if a target does not support a
55 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
56 /// will attempt merge setcc and brc instructions into brcc's.
59 class VISIBILITY_HIDDEN SelectionDAGLegalize {
63 // Libcall insertion helpers.
65 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
66 /// legalized. We use this to ensure that calls are properly serialized
67 /// against each other, including inserted libcalls.
68 SDOperand LastCALLSEQ_END;
70 /// IsLegalizingCall - This member is used *only* for purposes of providing
71 /// helpful assertions that a libcall isn't created while another call is
72 /// being legalized (which could lead to non-serialized call sequences).
73 bool IsLegalizingCall;
76 Legal, // The target natively supports this operation.
77 Promote, // This operation should be executed in a larger type.
78 Expand // Try to expand this to other ops, otherwise use a libcall.
81 /// ValueTypeActions - This is a bitvector that contains two bits for each
82 /// value type, where the two bits correspond to the LegalizeAction enum.
83 /// This can be queried with "getTypeAction(VT)".
84 TargetLowering::ValueTypeActionImpl ValueTypeActions;
86 /// LegalizedNodes - For nodes that are of legal width, and that have more
87 /// than one use, this map indicates what regularized operand to use. This
88 /// allows us to avoid legalizing the same thing more than once.
89 DenseMap<SDOperand, SDOperand> LegalizedNodes;
91 /// PromotedNodes - For nodes that are below legal width, and that have more
92 /// than one use, this map indicates what promoted value to use. This allows
93 /// us to avoid promoting the same thing more than once.
94 DenseMap<SDOperand, SDOperand> PromotedNodes;
96 /// ExpandedNodes - For nodes that need to be expanded this map indicates
97 /// which which operands are the expanded version of the input. This allows
98 /// us to avoid expanding the same node more than once.
99 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
101 /// SplitNodes - For vector nodes that need to be split, this map indicates
102 /// which which operands are the split version of the input. This allows us
103 /// to avoid splitting the same node more than once.
104 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
106 /// ScalarizedNodes - For nodes that need to be converted from vector types to
107 /// scalar types, this contains the mapping of ones we have already
108 /// processed to the result.
109 std::map<SDOperand, SDOperand> ScalarizedNodes;
111 void AddLegalizedOperand(SDOperand From, SDOperand To) {
112 LegalizedNodes.insert(std::make_pair(From, To));
113 // If someone requests legalization of the new node, return itself.
115 LegalizedNodes.insert(std::make_pair(To, To));
117 void AddPromotedOperand(SDOperand From, SDOperand To) {
118 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
119 assert(isNew && "Got into the map somehow?");
120 // If someone requests legalization of the new node, return itself.
121 LegalizedNodes.insert(std::make_pair(To, To));
125 explicit SelectionDAGLegalize(SelectionDAG &DAG);
127 /// getTypeAction - Return how we should legalize values of this type, either
128 /// it is already legal or we need to expand it into multiple registers of
129 /// smaller integer type, or we need to promote it to a larger type.
130 LegalizeAction getTypeAction(MVT VT) const {
131 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
134 /// isTypeLegal - Return true if this type is legal on this target.
136 bool isTypeLegal(MVT VT) const {
137 return getTypeAction(VT) == Legal;
143 /// HandleOp - Legalize, Promote, or Expand the specified operand as
144 /// appropriate for its type.
145 void HandleOp(SDOperand Op);
147 /// LegalizeOp - We know that the specified value has a legal type.
148 /// Recursively ensure that the operands have legal types, then return the
150 SDOperand LegalizeOp(SDOperand O);
152 /// UnrollVectorOp - We know that the given vector has a legal type, however
153 /// the operation it performs is not legal and is an operation that we have
154 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
155 /// operating on each element individually.
156 SDOperand UnrollVectorOp(SDOperand O);
158 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
159 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
160 /// is necessary to spill the vector being inserted into to memory, perform
161 /// the insert there, and then read the result back.
162 SDOperand PerformInsertVectorEltInMemory(SDOperand Vec, SDOperand Val,
165 /// PromoteOp - Given an operation that produces a value in an invalid type,
166 /// promote it to compute the value into a larger type. The produced value
167 /// will have the correct bits for the low portion of the register, but no
168 /// guarantee is made about the top bits: it may be zero, sign-extended, or
170 SDOperand PromoteOp(SDOperand O);
172 /// ExpandOp - Expand the specified SDOperand into its two component pieces
173 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
174 /// the LegalizeNodes map is filled in for any results that are not expanded,
175 /// the ExpandedNodes map is filled in for any results that are expanded, and
176 /// the Lo/Hi values are returned. This applies to integer types and Vector
178 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
180 /// SplitVectorOp - Given an operand of vector type, break it down into
181 /// two smaller values.
182 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
184 /// ScalarizeVectorOp - Given an operand of single-element vector type
185 /// (e.g. v1f32), convert it into the equivalent operation that returns a
186 /// scalar (e.g. f32) value.
187 SDOperand ScalarizeVectorOp(SDOperand O);
189 /// isShuffleLegal - Return non-null if a vector shuffle is legal with the
190 /// specified mask and type. Targets can specify exactly which masks they
191 /// support and the code generator is tasked with not creating illegal masks.
193 /// Note that this will also return true for shuffles that are promoted to a
196 /// If this is a legal shuffle, this method returns the (possibly promoted)
197 /// build_vector Mask. If it's not a legal shuffle, it returns null.
198 SDNode *isShuffleLegal(MVT VT, SDOperand Mask) const;
200 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
201 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
203 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
205 SDOperand ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned,
207 SDOperand ExpandIntToFP(bool isSigned, MVT DestTy, SDOperand Source);
209 SDOperand EmitStackConvert(SDOperand SrcOp, MVT SlotVT, MVT DestVT);
210 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
211 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
212 SDOperand ExpandLegalINT_TO_FP(bool isSigned, SDOperand LegalOp, MVT DestVT);
213 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT DestVT, bool isSigned);
214 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT DestVT, bool isSigned);
216 SDOperand ExpandBSWAP(SDOperand Op);
217 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
218 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
219 SDOperand &Lo, SDOperand &Hi);
220 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
221 SDOperand &Lo, SDOperand &Hi);
223 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op);
224 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
228 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
229 /// specified mask and type. Targets can specify exactly which masks they
230 /// support and the code generator is tasked with not creating illegal masks.
232 /// Note that this will also return true for shuffles that are promoted to a
234 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDOperand Mask) const {
235 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
237 case TargetLowering::Legal:
238 case TargetLowering::Custom:
240 case TargetLowering::Promote: {
241 // If this is promoted to a different type, convert the shuffle mask and
242 // ask if it is legal in the promoted type!
243 MVT NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
244 MVT EltVT = NVT.getVectorElementType();
246 // If we changed # elements, change the shuffle mask.
247 unsigned NumEltsGrowth =
248 NVT.getVectorNumElements() / VT.getVectorNumElements();
249 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
250 if (NumEltsGrowth > 1) {
251 // Renumber the elements.
252 SmallVector<SDOperand, 8> Ops;
253 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
254 SDOperand InOp = Mask.getOperand(i);
255 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
256 if (InOp.getOpcode() == ISD::UNDEF)
257 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
259 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
260 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, EltVT));
264 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
270 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
273 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
274 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
275 ValueTypeActions(TLI.getValueTypeActions()) {
276 assert(MVT::LAST_VALUETYPE <= 32 &&
277 "Too many value types for ValueTypeActions to hold!");
280 /// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order
281 /// contains all of a nodes operands before it contains the node.
282 static void ComputeTopDownOrdering(SelectionDAG &DAG,
283 SmallVector<SDNode*, 64> &Order) {
285 DenseMap<SDNode*, unsigned> Visited;
286 std::vector<SDNode*> Worklist;
287 Worklist.reserve(128);
289 // Compute ordering from all of the leaves in the graphs, those (like the
290 // entry node) that have no operands.
291 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
292 E = DAG.allnodes_end(); I != E; ++I) {
293 if (I->getNumOperands() == 0) {
295 Worklist.push_back(I);
299 while (!Worklist.empty()) {
300 SDNode *N = Worklist.back();
303 if (++Visited[N] != N->getNumOperands())
304 continue; // Haven't visited all operands yet
308 // Now that we have N in, add anything that uses it if all of their operands
310 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
312 Worklist.push_back(UI->getUser());
315 assert(Order.size() == Visited.size() &&
316 Order.size() == DAG.allnodes_size() &&
317 "Error: DAG is cyclic!");
321 void SelectionDAGLegalize::LegalizeDAG() {
322 LastCALLSEQ_END = DAG.getEntryNode();
323 IsLegalizingCall = false;
325 // The legalize process is inherently a bottom-up recursive process (users
326 // legalize their uses before themselves). Given infinite stack space, we
327 // could just start legalizing on the root and traverse the whole graph. In
328 // practice however, this causes us to run out of stack space on large basic
329 // blocks. To avoid this problem, compute an ordering of the nodes where each
330 // node is only legalized after all of its operands are legalized.
331 SmallVector<SDNode*, 64> Order;
332 ComputeTopDownOrdering(DAG, Order);
334 for (unsigned i = 0, e = Order.size(); i != e; ++i)
335 HandleOp(SDOperand(Order[i], 0));
337 // Finally, it's possible the root changed. Get the new root.
338 SDOperand OldRoot = DAG.getRoot();
339 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
340 DAG.setRoot(LegalizedNodes[OldRoot]);
342 ExpandedNodes.clear();
343 LegalizedNodes.clear();
344 PromotedNodes.clear();
346 ScalarizedNodes.clear();
348 // Remove dead nodes now.
349 DAG.RemoveDeadNodes();
353 /// FindCallEndFromCallStart - Given a chained node that is part of a call
354 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
355 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
356 if (Node->getOpcode() == ISD::CALLSEQ_END)
358 if (Node->use_empty())
359 return 0; // No CallSeqEnd
361 // The chain is usually at the end.
362 SDOperand TheChain(Node, Node->getNumValues()-1);
363 if (TheChain.getValueType() != MVT::Other) {
364 // Sometimes it's at the beginning.
365 TheChain = SDOperand(Node, 0);
366 if (TheChain.getValueType() != MVT::Other) {
367 // Otherwise, hunt for it.
368 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
369 if (Node->getValueType(i) == MVT::Other) {
370 TheChain = SDOperand(Node, i);
374 // Otherwise, we walked into a node without a chain.
375 if (TheChain.getValueType() != MVT::Other)
380 for (SDNode::use_iterator UI = Node->use_begin(),
381 E = Node->use_end(); UI != E; ++UI) {
383 // Make sure to only follow users of our token chain.
384 SDNode *User = UI->getUser();
385 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
386 if (User->getOperand(i) == TheChain)
387 if (SDNode *Result = FindCallEndFromCallStart(User))
393 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
394 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
395 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
396 assert(Node && "Didn't find callseq_start for a call??");
397 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
399 assert(Node->getOperand(0).getValueType() == MVT::Other &&
400 "Node doesn't have a token chain argument!");
401 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
404 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
405 /// see if any uses can reach Dest. If no dest operands can get to dest,
406 /// legalize them, legalize ourself, and return false, otherwise, return true.
408 /// Keep track of the nodes we fine that actually do lead to Dest in
409 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
411 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
412 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
413 if (N == Dest) return true; // N certainly leads to Dest :)
415 // If we've already processed this node and it does lead to Dest, there is no
416 // need to reprocess it.
417 if (NodesLeadingTo.count(N)) return true;
419 // If the first result of this node has been already legalized, then it cannot
421 switch (getTypeAction(N->getValueType(0))) {
423 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
426 if (PromotedNodes.count(SDOperand(N, 0))) return false;
429 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
433 // Okay, this node has not already been legalized. Check and legalize all
434 // operands. If none lead to Dest, then we can legalize this node.
435 bool OperandsLeadToDest = false;
436 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
437 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
438 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
440 if (OperandsLeadToDest) {
441 NodesLeadingTo.insert(N);
445 // Okay, this node looks safe, legalize it and return false.
446 HandleOp(SDOperand(N, 0));
450 /// HandleOp - Legalize, Promote, or Expand the specified operand as
451 /// appropriate for its type.
452 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
453 MVT VT = Op.getValueType();
454 switch (getTypeAction(VT)) {
455 default: assert(0 && "Bad type action!");
456 case Legal: (void)LegalizeOp(Op); break;
457 case Promote: (void)PromoteOp(Op); break;
459 if (!VT.isVector()) {
460 // If this is an illegal scalar, expand it into its two component
463 if (Op.getOpcode() == ISD::TargetConstant)
464 break; // Allow illegal target nodes.
466 } else if (VT.getVectorNumElements() == 1) {
467 // If this is an illegal single element vector, convert it to a
469 (void)ScalarizeVectorOp(Op);
471 // Otherwise, this is an illegal multiple element vector.
472 // Split it in half and legalize both parts.
474 SplitVectorOp(Op, X, Y);
480 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
481 /// a load from the constant pool.
482 static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
483 SelectionDAG &DAG, TargetLowering &TLI) {
486 // If a FP immediate is precise when represented as a float and if the
487 // target can do an extending load from float to double, we put it into
488 // the constant pool as a float, even if it's is statically typed as a
489 // double. This shrinks FP constants and canonicalizes them for targets where
490 // an FP extending load is the same cost as a normal load (such as on the x87
491 // fp stack or PPC FP unit).
492 MVT VT = CFP->getValueType(0);
493 ConstantFP *LLVMC = ConstantFP::get(CFP->getValueAPF());
495 if (VT!=MVT::f64 && VT!=MVT::f32)
496 assert(0 && "Invalid type expansion");
497 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt(),
498 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
503 while (SVT != MVT::f32) {
504 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1);
505 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
506 // Only do this if the target has a native EXTLOAD instruction from
508 TLI.isLoadXLegal(ISD::EXTLOAD, SVT) &&
509 TLI.ShouldShrinkFPConstant(OrigVT)) {
510 const Type *SType = SVT.getTypeForMVT();
511 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
517 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
519 return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, DAG.getEntryNode(),
520 CPIdx, PseudoSourceValue::getConstantPool(),
522 return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx,
523 PseudoSourceValue::getConstantPool(), 0);
527 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
530 SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT,
531 SelectionDAG &DAG, TargetLowering &TLI) {
532 MVT VT = Node->getValueType(0);
533 MVT SrcVT = Node->getOperand(1).getValueType();
534 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
535 "fcopysign expansion only supported for f32 and f64");
536 MVT SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
538 // First get the sign bit of second operand.
539 SDOperand Mask1 = (SrcVT == MVT::f64)
540 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
541 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
542 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
543 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
544 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
545 // Shift right or sign-extend it if the two operands have different types.
546 int SizeDiff = SrcNVT.getSizeInBits() - NVT.getSizeInBits();
548 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
549 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
550 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
551 } else if (SizeDiff < 0) {
552 SignBit = DAG.getNode(ISD::ZERO_EXTEND, NVT, SignBit);
553 SignBit = DAG.getNode(ISD::SHL, NVT, SignBit,
554 DAG.getConstant(-SizeDiff, TLI.getShiftAmountTy()));
557 // Clear the sign bit of first operand.
558 SDOperand Mask2 = (VT == MVT::f64)
559 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
560 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
561 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
562 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
563 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
565 // Or the value with the sign bit.
566 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
570 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
572 SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
573 TargetLowering &TLI) {
574 SDOperand Chain = ST->getChain();
575 SDOperand Ptr = ST->getBasePtr();
576 SDOperand Val = ST->getValue();
577 MVT VT = Val.getValueType();
578 int Alignment = ST->getAlignment();
579 int SVOffset = ST->getSrcValueOffset();
580 if (ST->getMemoryVT().isFloatingPoint() ||
581 ST->getMemoryVT().isVector()) {
582 // Expand to a bitconvert of the value to the integer type of the
583 // same size, then a (misaligned) int store.
585 if (VT.is128BitVector() || VT == MVT::ppcf128 || VT == MVT::f128)
587 else if (VT.is64BitVector() || VT==MVT::f64)
589 else if (VT==MVT::f32)
592 assert(0 && "Unaligned store of unsupported type");
594 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val);
595 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(),
596 SVOffset, ST->isVolatile(), Alignment);
598 assert(ST->getMemoryVT().isInteger() &&
599 !ST->getMemoryVT().isVector() &&
600 "Unaligned store of unknown type.");
601 // Get the half-size VT
603 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1);
604 int NumBits = NewStoredVT.getSizeInBits();
605 int IncrementSize = NumBits / 8;
607 // Divide the stored value in two parts.
608 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
610 SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
612 // Store the two parts
613 SDOperand Store1, Store2;
614 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr,
615 ST->getSrcValue(), SVOffset, NewStoredVT,
616 ST->isVolatile(), Alignment);
617 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
618 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
619 Alignment = MinAlign(Alignment, IncrementSize);
620 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr,
621 ST->getSrcValue(), SVOffset + IncrementSize,
622 NewStoredVT, ST->isVolatile(), Alignment);
624 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2);
627 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
629 SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
630 TargetLowering &TLI) {
631 int SVOffset = LD->getSrcValueOffset();
632 SDOperand Chain = LD->getChain();
633 SDOperand Ptr = LD->getBasePtr();
634 MVT VT = LD->getValueType(0);
635 MVT LoadedVT = LD->getMemoryVT();
636 if (VT.isFloatingPoint() || VT.isVector()) {
637 // Expand to a (misaligned) integer load of the same size,
638 // then bitconvert to floating point or vector.
640 if (LoadedVT.is128BitVector() ||
641 LoadedVT == MVT::ppcf128 || LoadedVT == MVT::f128)
643 else if (LoadedVT.is64BitVector() || LoadedVT == MVT::f64)
645 else if (LoadedVT == MVT::f32)
648 assert(0 && "Unaligned load of unsupported type");
650 SDOperand newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(),
651 SVOffset, LD->isVolatile(),
653 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad);
654 if (VT.isFloatingPoint() && LoadedVT != VT)
655 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result);
657 SDOperand Ops[] = { Result, Chain };
658 return DAG.getMergeValues(Ops, 2);
660 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
661 "Unaligned load of unsupported type.");
663 // Compute the new VT that is half the size of the old one. This is an
665 unsigned NumBits = LoadedVT.getSizeInBits();
667 NewLoadedVT = MVT::getIntegerVT(NumBits/2);
670 unsigned Alignment = LD->getAlignment();
671 unsigned IncrementSize = NumBits / 8;
672 ISD::LoadExtType HiExtType = LD->getExtensionType();
674 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
675 if (HiExtType == ISD::NON_EXTLOAD)
676 HiExtType = ISD::ZEXTLOAD;
678 // Load the value in two parts
680 if (TLI.isLittleEndian()) {
681 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
682 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
683 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
684 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
685 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(),
686 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
687 MinAlign(Alignment, IncrementSize));
689 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset,
690 NewLoadedVT,LD->isVolatile(), Alignment);
691 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
692 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
693 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
694 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
695 MinAlign(Alignment, IncrementSize));
698 // aggregate the two parts
699 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
700 SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
701 Result = DAG.getNode(ISD::OR, VT, Result, Lo);
703 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
706 SDOperand Ops[] = { Result, TF };
707 return DAG.getMergeValues(Ops, 2);
710 /// UnrollVectorOp - We know that the given vector has a legal type, however
711 /// the operation it performs is not legal and is an operation that we have
712 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
713 /// operating on each element individually.
714 SDOperand SelectionDAGLegalize::UnrollVectorOp(SDOperand Op) {
715 MVT VT = Op.getValueType();
716 assert(isTypeLegal(VT) &&
717 "Caller should expand or promote operands that are not legal!");
718 assert(Op.Val->getNumValues() == 1 &&
719 "Can't unroll a vector with multiple results!");
720 unsigned NE = VT.getVectorNumElements();
721 MVT EltVT = VT.getVectorElementType();
723 SmallVector<SDOperand, 8> Scalars;
724 SmallVector<SDOperand, 4> Operands(Op.getNumOperands());
725 for (unsigned i = 0; i != NE; ++i) {
726 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
727 SDOperand Operand = Op.getOperand(j);
728 MVT OperandVT = Operand.getValueType();
729 if (OperandVT.isVector()) {
730 // A vector operand; extract a single element.
731 MVT OperandEltVT = OperandVT.getVectorElementType();
732 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
735 DAG.getConstant(i, MVT::i32));
737 // A scalar operand; just use it as is.
738 Operands[j] = Operand;
741 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT,
742 &Operands[0], Operands.size()));
745 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size());
748 /// GetFPLibCall - Return the right libcall for the given floating point type.
749 static RTLIB::Libcall GetFPLibCall(MVT VT,
750 RTLIB::Libcall Call_F32,
751 RTLIB::Libcall Call_F64,
752 RTLIB::Libcall Call_F80,
753 RTLIB::Libcall Call_PPCF128) {
755 VT == MVT::f32 ? Call_F32 :
756 VT == MVT::f64 ? Call_F64 :
757 VT == MVT::f80 ? Call_F80 :
758 VT == MVT::ppcf128 ? Call_PPCF128 :
759 RTLIB::UNKNOWN_LIBCALL;
762 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
763 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
764 /// is necessary to spill the vector being inserted into to memory, perform
765 /// the insert there, and then read the result back.
766 SDOperand SelectionDAGLegalize::
767 PerformInsertVectorEltInMemory(SDOperand Vec, SDOperand Val, SDOperand Idx) {
768 SDOperand Tmp1 = Vec;
769 SDOperand Tmp2 = Val;
770 SDOperand Tmp3 = Idx;
772 // If the target doesn't support this, we have to spill the input vector
773 // to a temporary stack slot, update the element, then reload it. This is
774 // badness. We could also load the value into a vector register (either
775 // with a "move to register" or "extload into register" instruction, then
776 // permute it into place, if the idx is a constant and if the idx is
777 // supported by the target.
778 MVT VT = Tmp1.getValueType();
779 MVT EltVT = VT.getVectorElementType();
780 MVT IdxVT = Tmp3.getValueType();
781 MVT PtrVT = TLI.getPointerTy();
782 SDOperand StackPtr = DAG.CreateStackTemporary(VT);
784 int SPFI = cast<FrameIndexSDNode>(StackPtr.Val)->getIndex();
787 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr,
788 PseudoSourceValue::getFixedStack(SPFI), 0);
790 // Truncate or zero extend offset to target pointer type.
791 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
792 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
793 // Add the offset to the index.
794 unsigned EltSize = EltVT.getSizeInBits()/8;
795 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
796 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
797 // Store the scalar value.
798 Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2,
799 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT);
800 // Load the updated vector.
801 return DAG.getLoad(VT, Ch, StackPtr,
802 PseudoSourceValue::getFixedStack(SPFI), 0);
805 /// LegalizeOp - We know that the specified value has a legal type, and
806 /// that its operands are legal. Now ensure that the operation itself
807 /// is legal, recursively ensuring that the operands' operations remain
809 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
810 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
813 assert(isTypeLegal(Op.getValueType()) &&
814 "Caller should expand or promote operands that are not legal!");
815 SDNode *Node = Op.Val;
817 // If this operation defines any values that cannot be represented in a
818 // register on this target, make sure to expand or promote them.
819 if (Node->getNumValues() > 1) {
820 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
821 if (getTypeAction(Node->getValueType(i)) != Legal) {
822 HandleOp(Op.getValue(i));
823 assert(LegalizedNodes.count(Op) &&
824 "Handling didn't add legal operands!");
825 return LegalizedNodes[Op];
829 // Note that LegalizeOp may be reentered even from single-use nodes, which
830 // means that we always must cache transformed nodes.
831 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
832 if (I != LegalizedNodes.end()) return I->second;
834 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
835 SDOperand Result = Op;
836 bool isCustom = false;
838 switch (Node->getOpcode()) {
839 case ISD::FrameIndex:
840 case ISD::EntryToken:
842 case ISD::BasicBlock:
843 case ISD::TargetFrameIndex:
844 case ISD::TargetJumpTable:
845 case ISD::TargetConstant:
846 case ISD::TargetConstantFP:
847 case ISD::TargetConstantPool:
848 case ISD::TargetGlobalAddress:
849 case ISD::TargetGlobalTLSAddress:
850 case ISD::TargetExternalSymbol:
853 case ISD::MEMOPERAND:
856 // Primitives must all be legal.
857 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
858 "This must be legal!");
861 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
862 // If this is a target node, legalize it by legalizing the operands then
863 // passing it through.
864 SmallVector<SDOperand, 8> Ops;
865 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
866 Ops.push_back(LegalizeOp(Node->getOperand(i)));
868 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
870 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
871 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
872 return Result.getValue(Op.ResNo);
874 // Otherwise this is an unhandled builtin node. splat.
876 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
878 assert(0 && "Do not know how to legalize this operator!");
880 case ISD::GLOBAL_OFFSET_TABLE:
881 case ISD::GlobalAddress:
882 case ISD::GlobalTLSAddress:
883 case ISD::ExternalSymbol:
884 case ISD::ConstantPool:
885 case ISD::JumpTable: // Nothing to do.
886 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
887 default: assert(0 && "This action is not supported yet!");
888 case TargetLowering::Custom:
889 Tmp1 = TLI.LowerOperation(Op, DAG);
890 if (Tmp1.Val) Result = Tmp1;
891 // FALLTHROUGH if the target doesn't want to lower this op after all.
892 case TargetLowering::Legal:
897 case ISD::RETURNADDR:
898 // The only option for these nodes is to custom lower them. If the target
899 // does not custom lower them, then return zero.
900 Tmp1 = TLI.LowerOperation(Op, DAG);
904 Result = DAG.getConstant(0, TLI.getPointerTy());
906 case ISD::FRAME_TO_ARGS_OFFSET: {
907 MVT VT = Node->getValueType(0);
908 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
909 default: assert(0 && "This action is not supported yet!");
910 case TargetLowering::Custom:
911 Result = TLI.LowerOperation(Op, DAG);
912 if (Result.Val) break;
914 case TargetLowering::Legal:
915 Result = DAG.getConstant(0, VT);
920 case ISD::EXCEPTIONADDR: {
921 Tmp1 = LegalizeOp(Node->getOperand(0));
922 MVT VT = Node->getValueType(0);
923 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
924 default: assert(0 && "This action is not supported yet!");
925 case TargetLowering::Expand: {
926 unsigned Reg = TLI.getExceptionAddressRegister();
927 Result = DAG.getCopyFromReg(Tmp1, Reg, VT);
930 case TargetLowering::Custom:
931 Result = TLI.LowerOperation(Op, DAG);
932 if (Result.Val) break;
934 case TargetLowering::Legal: {
935 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 };
936 Result = DAG.getMergeValues(Ops, 2);
941 if (Result.Val->getNumValues() == 1) break;
943 assert(Result.Val->getNumValues() == 2 &&
944 "Cannot return more than two values!");
946 // Since we produced two values, make sure to remember that we
947 // legalized both of them.
948 Tmp1 = LegalizeOp(Result);
949 Tmp2 = LegalizeOp(Result.getValue(1));
950 AddLegalizedOperand(Op.getValue(0), Tmp1);
951 AddLegalizedOperand(Op.getValue(1), Tmp2);
952 return Op.ResNo ? Tmp2 : Tmp1;
953 case ISD::EHSELECTION: {
954 Tmp1 = LegalizeOp(Node->getOperand(0));
955 Tmp2 = LegalizeOp(Node->getOperand(1));
956 MVT VT = Node->getValueType(0);
957 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
958 default: assert(0 && "This action is not supported yet!");
959 case TargetLowering::Expand: {
960 unsigned Reg = TLI.getExceptionSelectorRegister();
961 Result = DAG.getCopyFromReg(Tmp2, Reg, VT);
964 case TargetLowering::Custom:
965 Result = TLI.LowerOperation(Op, DAG);
966 if (Result.Val) break;
968 case TargetLowering::Legal: {
969 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 };
970 Result = DAG.getMergeValues(Ops, 2);
975 if (Result.Val->getNumValues() == 1) break;
977 assert(Result.Val->getNumValues() == 2 &&
978 "Cannot return more than two values!");
980 // Since we produced two values, make sure to remember that we
981 // legalized both of them.
982 Tmp1 = LegalizeOp(Result);
983 Tmp2 = LegalizeOp(Result.getValue(1));
984 AddLegalizedOperand(Op.getValue(0), Tmp1);
985 AddLegalizedOperand(Op.getValue(1), Tmp2);
986 return Op.ResNo ? Tmp2 : Tmp1;
987 case ISD::EH_RETURN: {
988 MVT VT = Node->getValueType(0);
989 // The only "good" option for this node is to custom lower it.
990 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
991 default: assert(0 && "This action is not supported at all!");
992 case TargetLowering::Custom:
993 Result = TLI.LowerOperation(Op, DAG);
994 if (Result.Val) break;
996 case TargetLowering::Legal:
997 // Target does not know, how to lower this, lower to noop
998 Result = LegalizeOp(Node->getOperand(0));
1003 case ISD::AssertSext:
1004 case ISD::AssertZext:
1005 Tmp1 = LegalizeOp(Node->getOperand(0));
1006 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1008 case ISD::MERGE_VALUES:
1009 // Legalize eliminates MERGE_VALUES nodes.
1010 Result = Node->getOperand(Op.ResNo);
1012 case ISD::CopyFromReg:
1013 Tmp1 = LegalizeOp(Node->getOperand(0));
1014 Result = Op.getValue(0);
1015 if (Node->getNumValues() == 2) {
1016 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1018 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
1019 if (Node->getNumOperands() == 3) {
1020 Tmp2 = LegalizeOp(Node->getOperand(2));
1021 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1023 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1025 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
1027 // Since CopyFromReg produces two values, make sure to remember that we
1028 // legalized both of them.
1029 AddLegalizedOperand(Op.getValue(0), Result);
1030 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1031 return Result.getValue(Op.ResNo);
1033 MVT VT = Op.getValueType();
1034 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
1035 default: assert(0 && "This action is not supported yet!");
1036 case TargetLowering::Expand:
1038 Result = DAG.getConstant(0, VT);
1039 else if (VT.isFloatingPoint())
1040 Result = DAG.getConstantFP(APFloat(APInt(VT.getSizeInBits(), 0)),
1043 assert(0 && "Unknown value type!");
1045 case TargetLowering::Legal:
1051 case ISD::INTRINSIC_W_CHAIN:
1052 case ISD::INTRINSIC_WO_CHAIN:
1053 case ISD::INTRINSIC_VOID: {
1054 SmallVector<SDOperand, 8> Ops;
1055 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1056 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1057 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1059 // Allow the target to custom lower its intrinsics if it wants to.
1060 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
1061 TargetLowering::Custom) {
1062 Tmp3 = TLI.LowerOperation(Result, DAG);
1063 if (Tmp3.Val) Result = Tmp3;
1066 if (Result.Val->getNumValues() == 1) break;
1068 // Must have return value and chain result.
1069 assert(Result.Val->getNumValues() == 2 &&
1070 "Cannot return more than two values!");
1072 // Since loads produce two values, make sure to remember that we
1073 // legalized both of them.
1074 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1075 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1076 return Result.getValue(Op.ResNo);
1079 case ISD::DBG_STOPPOINT:
1080 assert(Node->getNumOperands() == 1 && "Invalid DBG_STOPPOINT node!");
1081 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
1083 switch (TLI.getOperationAction(ISD::DBG_STOPPOINT, MVT::Other)) {
1084 case TargetLowering::Promote:
1085 default: assert(0 && "This action is not supported yet!");
1086 case TargetLowering::Expand: {
1087 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
1088 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
1089 bool useLABEL = TLI.isOperationLegal(ISD::DBG_LABEL, MVT::Other);
1091 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node);
1092 if (MMI && (useDEBUG_LOC || useLABEL)) {
1093 const CompileUnitDesc *CompileUnit = DSP->getCompileUnit();
1094 unsigned SrcFile = MMI->RecordSource(CompileUnit);
1096 unsigned Line = DSP->getLine();
1097 unsigned Col = DSP->getColumn();
1100 SDOperand Ops[] = { Tmp1, DAG.getConstant(Line, MVT::i32),
1101 DAG.getConstant(Col, MVT::i32),
1102 DAG.getConstant(SrcFile, MVT::i32) };
1103 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops, 4);
1105 unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile);
1106 Result = DAG.getLabel(ISD::DBG_LABEL, Tmp1, ID);
1109 Result = Tmp1; // chain
1113 case TargetLowering::Legal: {
1114 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1115 if (Action == Legal && Tmp1 == Node->getOperand(0))
1118 SmallVector<SDOperand, 8> Ops;
1119 Ops.push_back(Tmp1);
1120 if (Action == Legal) {
1121 Ops.push_back(Node->getOperand(1)); // line # must be legal.
1122 Ops.push_back(Node->getOperand(2)); // col # must be legal.
1124 // Otherwise promote them.
1125 Ops.push_back(PromoteOp(Node->getOperand(1)));
1126 Ops.push_back(PromoteOp(Node->getOperand(2)));
1128 Ops.push_back(Node->getOperand(3)); // filename must be legal.
1129 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
1130 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1137 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!");
1138 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) {
1139 default: assert(0 && "This action is not supported yet!");
1140 case TargetLowering::Legal:
1141 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1142 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1143 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable.
1144 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1146 case TargetLowering::Expand:
1147 Result = LegalizeOp(Node->getOperand(0));
1152 case ISD::DEBUG_LOC:
1153 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
1154 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
1155 default: assert(0 && "This action is not supported yet!");
1156 case TargetLowering::Legal: {
1157 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1158 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1159 if (Action == Legal && Tmp1 == Node->getOperand(0))
1161 if (Action == Legal) {
1162 Tmp2 = Node->getOperand(1);
1163 Tmp3 = Node->getOperand(2);
1164 Tmp4 = Node->getOperand(3);
1166 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1167 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1168 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1170 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1176 case ISD::DBG_LABEL:
1178 assert(Node->getNumOperands() == 1 && "Invalid LABEL node!");
1179 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
1180 default: assert(0 && "This action is not supported yet!");
1181 case TargetLowering::Legal:
1182 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1183 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1185 case TargetLowering::Expand:
1186 Result = LegalizeOp(Node->getOperand(0));
1192 assert(Node->getNumOperands() == 4 && "Invalid Prefetch node!");
1193 switch (TLI.getOperationAction(ISD::PREFETCH, MVT::Other)) {
1194 default: assert(0 && "This action is not supported yet!");
1195 case TargetLowering::Legal:
1196 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1197 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1198 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the rw specifier.
1199 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize locality specifier.
1200 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1202 case TargetLowering::Expand:
1204 Result = LegalizeOp(Node->getOperand(0));
1209 case ISD::MEMBARRIER: {
1210 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!");
1211 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) {
1212 default: assert(0 && "This action is not supported yet!");
1213 case TargetLowering::Legal: {
1215 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1216 for (int x = 1; x < 6; ++x) {
1217 Ops[x] = Node->getOperand(x);
1218 if (!isTypeLegal(Ops[x].getValueType()))
1219 Ops[x] = PromoteOp(Ops[x]);
1221 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6);
1224 case TargetLowering::Expand:
1225 //There is no libgcc call for this op
1226 Result = Node->getOperand(0); // Noop
1232 case ISD::ATOMIC_CMP_SWAP: {
1233 unsigned int num_operands = 4;
1234 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1236 for (unsigned int x = 0; x < num_operands; ++x)
1237 Ops[x] = LegalizeOp(Node->getOperand(x));
1238 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1240 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1241 default: assert(0 && "This action is not supported yet!");
1242 case TargetLowering::Custom:
1243 Result = TLI.LowerOperation(Result, DAG);
1245 case TargetLowering::Legal:
1248 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1249 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1250 return Result.getValue(Op.ResNo);
1252 case ISD::ATOMIC_LOAD_ADD:
1253 case ISD::ATOMIC_LOAD_SUB:
1254 case ISD::ATOMIC_LOAD_AND:
1255 case ISD::ATOMIC_LOAD_OR:
1256 case ISD::ATOMIC_LOAD_XOR:
1257 case ISD::ATOMIC_LOAD_NAND:
1258 case ISD::ATOMIC_LOAD_MIN:
1259 case ISD::ATOMIC_LOAD_MAX:
1260 case ISD::ATOMIC_LOAD_UMIN:
1261 case ISD::ATOMIC_LOAD_UMAX:
1262 case ISD::ATOMIC_SWAP: {
1263 unsigned int num_operands = 3;
1264 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1266 for (unsigned int x = 0; x < num_operands; ++x)
1267 Ops[x] = LegalizeOp(Node->getOperand(x));
1268 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1270 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1271 default: assert(0 && "This action is not supported yet!");
1272 case TargetLowering::Custom:
1273 Result = TLI.LowerOperation(Result, DAG);
1275 case TargetLowering::Expand:
1276 Result = SDOperand(TLI.ReplaceNodeResults(Op.Val, DAG),0);
1278 case TargetLowering::Legal:
1281 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1282 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1283 return Result.getValue(Op.ResNo);
1285 case ISD::Constant: {
1286 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1288 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1290 // We know we don't need to expand constants here, constants only have one
1291 // value and we check that it is fine above.
1293 if (opAction == TargetLowering::Custom) {
1294 Tmp1 = TLI.LowerOperation(Result, DAG);
1300 case ISD::ConstantFP: {
1301 // Spill FP immediates to the constant pool if the target cannot directly
1302 // codegen them. Targets often have some immediate values that can be
1303 // efficiently generated into an FP register without a load. We explicitly
1304 // leave these constants as ConstantFP nodes for the target to deal with.
1305 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1307 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1308 default: assert(0 && "This action is not supported yet!");
1309 case TargetLowering::Legal:
1311 case TargetLowering::Custom:
1312 Tmp3 = TLI.LowerOperation(Result, DAG);
1318 case TargetLowering::Expand: {
1319 // Check to see if this FP immediate is already legal.
1320 bool isLegal = false;
1321 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1322 E = TLI.legal_fpimm_end(); I != E; ++I) {
1323 if (CFP->isExactlyValue(*I)) {
1328 // If this is a legal constant, turn it into a TargetConstantFP node.
1331 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1336 case ISD::TokenFactor:
1337 if (Node->getNumOperands() == 2) {
1338 Tmp1 = LegalizeOp(Node->getOperand(0));
1339 Tmp2 = LegalizeOp(Node->getOperand(1));
1340 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1341 } else if (Node->getNumOperands() == 3) {
1342 Tmp1 = LegalizeOp(Node->getOperand(0));
1343 Tmp2 = LegalizeOp(Node->getOperand(1));
1344 Tmp3 = LegalizeOp(Node->getOperand(2));
1345 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1347 SmallVector<SDOperand, 8> Ops;
1348 // Legalize the operands.
1349 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1350 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1351 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1355 case ISD::FORMAL_ARGUMENTS:
1357 // The only option for this is to custom lower it.
1358 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1359 assert(Tmp3.Val && "Target didn't custom lower this node!");
1360 // A call within a calling sequence must be legalized to something
1361 // other than the normal CALLSEQ_END. Violating this gets Legalize
1362 // into an infinite loop.
1363 assert ((!IsLegalizingCall ||
1364 Node->getOpcode() != ISD::CALL ||
1365 Tmp3.Val->getOpcode() != ISD::CALLSEQ_END) &&
1366 "Nested CALLSEQ_START..CALLSEQ_END not supported.");
1368 // The number of incoming and outgoing values should match; unless the final
1369 // outgoing value is a flag.
1370 assert((Tmp3.Val->getNumValues() == Result.Val->getNumValues() ||
1371 (Tmp3.Val->getNumValues() == Result.Val->getNumValues() + 1 &&
1372 Tmp3.Val->getValueType(Tmp3.Val->getNumValues() - 1) ==
1374 "Lowering call/formal_arguments produced unexpected # results!");
1376 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1377 // remember that we legalized all of them, so it doesn't get relegalized.
1378 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
1379 if (Tmp3.Val->getValueType(i) == MVT::Flag)
1381 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1384 AddLegalizedOperand(SDOperand(Node, i), Tmp1);
1387 case ISD::EXTRACT_SUBREG: {
1388 Tmp1 = LegalizeOp(Node->getOperand(0));
1389 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1390 assert(idx && "Operand must be a constant");
1391 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1392 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1395 case ISD::INSERT_SUBREG: {
1396 Tmp1 = LegalizeOp(Node->getOperand(0));
1397 Tmp2 = LegalizeOp(Node->getOperand(1));
1398 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1399 assert(idx && "Operand must be a constant");
1400 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1401 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1404 case ISD::BUILD_VECTOR:
1405 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1406 default: assert(0 && "This action is not supported yet!");
1407 case TargetLowering::Custom:
1408 Tmp3 = TLI.LowerOperation(Result, DAG);
1414 case TargetLowering::Expand:
1415 Result = ExpandBUILD_VECTOR(Result.Val);
1419 case ISD::INSERT_VECTOR_ELT:
1420 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1421 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1423 // The type of the value to insert may not be legal, even though the vector
1424 // type is legal. Legalize/Promote accordingly. We do not handle Expand
1426 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1427 default: assert(0 && "Cannot expand insert element operand");
1428 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
1429 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
1431 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1433 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1434 Node->getValueType(0))) {
1435 default: assert(0 && "This action is not supported yet!");
1436 case TargetLowering::Legal:
1438 case TargetLowering::Custom:
1439 Tmp4 = TLI.LowerOperation(Result, DAG);
1445 case TargetLowering::Expand: {
1446 // If the insert index is a constant, codegen this as a scalar_to_vector,
1447 // then a shuffle that inserts it into the right position in the vector.
1448 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1449 // SCALAR_TO_VECTOR requires that the type of the value being inserted
1450 // match the element type of the vector being created.
1451 if (Tmp2.getValueType() ==
1452 Op.getValueType().getVectorElementType()) {
1453 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
1454 Tmp1.getValueType(), Tmp2);
1456 unsigned NumElts = Tmp1.getValueType().getVectorNumElements();
1458 MVT::getIntVectorWithNumElements(NumElts);
1459 MVT ShufMaskEltVT = ShufMaskVT.getVectorElementType();
1461 // We generate a shuffle of InVec and ScVec, so the shuffle mask
1462 // should be 0,1,2,3,4,5... with the appropriate element replaced with
1463 // elt 0 of the RHS.
1464 SmallVector<SDOperand, 8> ShufOps;
1465 for (unsigned i = 0; i != NumElts; ++i) {
1466 if (i != InsertPos->getValue())
1467 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1469 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1471 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1472 &ShufOps[0], ShufOps.size());
1474 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1475 Tmp1, ScVec, ShufMask);
1476 Result = LegalizeOp(Result);
1480 Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3);
1485 case ISD::SCALAR_TO_VECTOR:
1486 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1487 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1491 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1492 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1493 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1494 Node->getValueType(0))) {
1495 default: assert(0 && "This action is not supported yet!");
1496 case TargetLowering::Legal:
1498 case TargetLowering::Custom:
1499 Tmp3 = TLI.LowerOperation(Result, DAG);
1505 case TargetLowering::Expand:
1506 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1510 case ISD::VECTOR_SHUFFLE:
1511 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1512 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1513 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1515 // Allow targets to custom lower the SHUFFLEs they support.
1516 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1517 default: assert(0 && "Unknown operation action!");
1518 case TargetLowering::Legal:
1519 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1520 "vector shuffle should not be created if not legal!");
1522 case TargetLowering::Custom:
1523 Tmp3 = TLI.LowerOperation(Result, DAG);
1529 case TargetLowering::Expand: {
1530 MVT VT = Node->getValueType(0);
1531 MVT EltVT = VT.getVectorElementType();
1532 MVT PtrVT = TLI.getPointerTy();
1533 SDOperand Mask = Node->getOperand(2);
1534 unsigned NumElems = Mask.getNumOperands();
1535 SmallVector<SDOperand,8> Ops;
1536 for (unsigned i = 0; i != NumElems; ++i) {
1537 SDOperand Arg = Mask.getOperand(i);
1538 if (Arg.getOpcode() == ISD::UNDEF) {
1539 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1541 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1542 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
1544 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1545 DAG.getConstant(Idx, PtrVT)));
1547 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1548 DAG.getConstant(Idx - NumElems, PtrVT)));
1551 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1554 case TargetLowering::Promote: {
1555 // Change base type to a different vector type.
1556 MVT OVT = Node->getValueType(0);
1557 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1559 // Cast the two input vectors.
1560 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1561 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1563 // Convert the shuffle mask to the right # elements.
1564 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1565 assert(Tmp3.Val && "Shuffle not legal?");
1566 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1567 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1573 case ISD::EXTRACT_VECTOR_ELT:
1574 Tmp1 = Node->getOperand(0);
1575 Tmp2 = LegalizeOp(Node->getOperand(1));
1576 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1577 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1580 case ISD::EXTRACT_SUBVECTOR:
1581 Tmp1 = Node->getOperand(0);
1582 Tmp2 = LegalizeOp(Node->getOperand(1));
1583 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1584 Result = ExpandEXTRACT_SUBVECTOR(Result);
1587 case ISD::CALLSEQ_START: {
1588 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1590 // Recursively Legalize all of the inputs of the call end that do not lead
1591 // to this call start. This ensures that any libcalls that need be inserted
1592 // are inserted *before* the CALLSEQ_START.
1593 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1594 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1595 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
1599 // Now that we legalized all of the inputs (which may have inserted
1600 // libcalls) create the new CALLSEQ_START node.
1601 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1603 // Merge in the last call, to ensure that this call start after the last
1605 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1606 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1607 Tmp1 = LegalizeOp(Tmp1);
1610 // Do not try to legalize the target-specific arguments (#1+).
1611 if (Tmp1 != Node->getOperand(0)) {
1612 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1614 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1617 // Remember that the CALLSEQ_START is legalized.
1618 AddLegalizedOperand(Op.getValue(0), Result);
1619 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1620 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1622 // Now that the callseq_start and all of the non-call nodes above this call
1623 // sequence have been legalized, legalize the call itself. During this
1624 // process, no libcalls can/will be inserted, guaranteeing that no calls
1626 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1627 // Note that we are selecting this call!
1628 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1629 IsLegalizingCall = true;
1631 // Legalize the call, starting from the CALLSEQ_END.
1632 LegalizeOp(LastCALLSEQ_END);
1633 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1636 case ISD::CALLSEQ_END:
1637 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1638 // will cause this node to be legalized as well as handling libcalls right.
1639 if (LastCALLSEQ_END.Val != Node) {
1640 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1641 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1642 assert(I != LegalizedNodes.end() &&
1643 "Legalizing the call start should have legalized this node!");
1647 // Otherwise, the call start has been legalized and everything is going
1648 // according to plan. Just legalize ourselves normally here.
1649 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1650 // Do not try to legalize the target-specific arguments (#1+), except for
1651 // an optional flag input.
1652 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1653 if (Tmp1 != Node->getOperand(0)) {
1654 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1656 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1659 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1660 if (Tmp1 != Node->getOperand(0) ||
1661 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1662 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1665 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1668 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1669 // This finishes up call legalization.
1670 IsLegalizingCall = false;
1672 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1673 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1674 if (Node->getNumValues() == 2)
1675 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1676 return Result.getValue(Op.ResNo);
1677 case ISD::DYNAMIC_STACKALLOC: {
1678 MVT VT = Node->getValueType(0);
1679 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1680 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1681 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1682 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1684 Tmp1 = Result.getValue(0);
1685 Tmp2 = Result.getValue(1);
1686 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1687 default: assert(0 && "This action is not supported yet!");
1688 case TargetLowering::Expand: {
1689 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1690 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1691 " not tell us which reg is the stack pointer!");
1692 SDOperand Chain = Tmp1.getOperand(0);
1694 // Chain the dynamic stack allocation so that it doesn't modify the stack
1695 // pointer when other instructions are using the stack.
1696 Chain = DAG.getCALLSEQ_START(Chain,
1697 DAG.getConstant(0, TLI.getPointerTy()));
1699 SDOperand Size = Tmp2.getOperand(1);
1700 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT);
1701 Chain = SP.getValue(1);
1702 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue();
1703 unsigned StackAlign =
1704 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1705 if (Align > StackAlign)
1706 SP = DAG.getNode(ISD::AND, VT, SP,
1707 DAG.getConstant(-(uint64_t)Align, VT));
1708 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value
1709 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
1712 DAG.getCALLSEQ_END(Chain,
1713 DAG.getConstant(0, TLI.getPointerTy()),
1714 DAG.getConstant(0, TLI.getPointerTy()),
1717 Tmp1 = LegalizeOp(Tmp1);
1718 Tmp2 = LegalizeOp(Tmp2);
1721 case TargetLowering::Custom:
1722 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1724 Tmp1 = LegalizeOp(Tmp3);
1725 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1728 case TargetLowering::Legal:
1731 // Since this op produce two values, make sure to remember that we
1732 // legalized both of them.
1733 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1734 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1735 return Op.ResNo ? Tmp2 : Tmp1;
1737 case ISD::INLINEASM: {
1738 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1739 bool Changed = false;
1740 // Legalize all of the operands of the inline asm, in case they are nodes
1741 // that need to be expanded or something. Note we skip the asm string and
1742 // all of the TargetConstant flags.
1743 SDOperand Op = LegalizeOp(Ops[0]);
1744 Changed = Op != Ops[0];
1747 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1748 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1749 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1750 for (++i; NumVals; ++i, --NumVals) {
1751 SDOperand Op = LegalizeOp(Ops[i]);
1760 Op = LegalizeOp(Ops.back());
1761 Changed |= Op != Ops.back();
1766 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1768 // INLINE asm returns a chain and flag, make sure to add both to the map.
1769 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1770 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1771 return Result.getValue(Op.ResNo);
1774 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1775 // Ensure that libcalls are emitted before a branch.
1776 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1777 Tmp1 = LegalizeOp(Tmp1);
1778 LastCALLSEQ_END = DAG.getEntryNode();
1780 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1783 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1784 // Ensure that libcalls are emitted before a branch.
1785 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1786 Tmp1 = LegalizeOp(Tmp1);
1787 LastCALLSEQ_END = DAG.getEntryNode();
1789 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1790 default: assert(0 && "Indirect target must be legal type (pointer)!");
1792 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1795 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1798 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1799 // Ensure that libcalls are emitted before a branch.
1800 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1801 Tmp1 = LegalizeOp(Tmp1);
1802 LastCALLSEQ_END = DAG.getEntryNode();
1804 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1805 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1807 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1808 default: assert(0 && "This action is not supported yet!");
1809 case TargetLowering::Legal: break;
1810 case TargetLowering::Custom:
1811 Tmp1 = TLI.LowerOperation(Result, DAG);
1812 if (Tmp1.Val) Result = Tmp1;
1814 case TargetLowering::Expand: {
1815 SDOperand Chain = Result.getOperand(0);
1816 SDOperand Table = Result.getOperand(1);
1817 SDOperand Index = Result.getOperand(2);
1819 MVT PTy = TLI.getPointerTy();
1820 MachineFunction &MF = DAG.getMachineFunction();
1821 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
1822 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1823 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1826 switch (EntrySize) {
1827 default: assert(0 && "Size of jump table not supported yet."); break;
1828 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr,
1829 PseudoSourceValue::getJumpTable(), 0); break;
1830 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr,
1831 PseudoSourceValue::getJumpTable(), 0); break;
1835 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1836 // For PIC, the sequence is:
1837 // BRIND(load(Jumptable + index) + RelocBase)
1838 // RelocBase can be JumpTable, GOT or some sort of global base.
1839 if (PTy != MVT::i32)
1840 Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr);
1841 Addr = DAG.getNode(ISD::ADD, PTy, Addr,
1842 TLI.getPICJumpTableRelocBase(Table, DAG));
1844 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1849 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1850 // Ensure that libcalls are emitted before a return.
1851 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1852 Tmp1 = LegalizeOp(Tmp1);
1853 LastCALLSEQ_END = DAG.getEntryNode();
1855 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1856 case Expand: assert(0 && "It's impossible to expand bools");
1858 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1861 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1863 // The top bits of the promoted condition are not necessarily zero, ensure
1864 // that the value is properly zero extended.
1865 unsigned BitWidth = Tmp2.getValueSizeInBits();
1866 if (!DAG.MaskedValueIsZero(Tmp2,
1867 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
1868 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1873 // Basic block destination (Op#2) is always legal.
1874 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1876 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1877 default: assert(0 && "This action is not supported yet!");
1878 case TargetLowering::Legal: break;
1879 case TargetLowering::Custom:
1880 Tmp1 = TLI.LowerOperation(Result, DAG);
1881 if (Tmp1.Val) Result = Tmp1;
1883 case TargetLowering::Expand:
1884 // Expand brcond's setcc into its constituent parts and create a BR_CC
1886 if (Tmp2.getOpcode() == ISD::SETCC) {
1887 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1888 Tmp2.getOperand(0), Tmp2.getOperand(1),
1889 Node->getOperand(2));
1891 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1892 DAG.getCondCode(ISD::SETNE), Tmp2,
1893 DAG.getConstant(0, Tmp2.getValueType()),
1894 Node->getOperand(2));
1900 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1901 // Ensure that libcalls are emitted before a branch.
1902 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1903 Tmp1 = LegalizeOp(Tmp1);
1904 Tmp2 = Node->getOperand(2); // LHS
1905 Tmp3 = Node->getOperand(3); // RHS
1906 Tmp4 = Node->getOperand(1); // CC
1908 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1909 LastCALLSEQ_END = DAG.getEntryNode();
1911 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1912 // the LHS is a legal SETCC itself. In this case, we need to compare
1913 // the result against zero to select between true and false values.
1914 if (Tmp3.Val == 0) {
1915 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1916 Tmp4 = DAG.getCondCode(ISD::SETNE);
1919 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1920 Node->getOperand(4));
1922 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1923 default: assert(0 && "Unexpected action for BR_CC!");
1924 case TargetLowering::Legal: break;
1925 case TargetLowering::Custom:
1926 Tmp4 = TLI.LowerOperation(Result, DAG);
1927 if (Tmp4.Val) Result = Tmp4;
1932 LoadSDNode *LD = cast<LoadSDNode>(Node);
1933 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1934 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1936 ISD::LoadExtType ExtType = LD->getExtensionType();
1937 if (ExtType == ISD::NON_EXTLOAD) {
1938 MVT VT = Node->getValueType(0);
1939 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1940 Tmp3 = Result.getValue(0);
1941 Tmp4 = Result.getValue(1);
1943 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1944 default: assert(0 && "This action is not supported yet!");
1945 case TargetLowering::Legal:
1946 // If this is an unaligned load and the target doesn't support it,
1948 if (!TLI.allowsUnalignedMemoryAccesses()) {
1949 unsigned ABIAlignment = TLI.getTargetData()->
1950 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
1951 if (LD->getAlignment() < ABIAlignment){
1952 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
1954 Tmp3 = Result.getOperand(0);
1955 Tmp4 = Result.getOperand(1);
1956 Tmp3 = LegalizeOp(Tmp3);
1957 Tmp4 = LegalizeOp(Tmp4);
1961 case TargetLowering::Custom:
1962 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1964 Tmp3 = LegalizeOp(Tmp1);
1965 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1968 case TargetLowering::Promote: {
1969 // Only promote a load of vector type to another.
1970 assert(VT.isVector() && "Cannot promote this load!");
1971 // Change base type to a different vector type.
1972 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1974 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1975 LD->getSrcValueOffset(),
1976 LD->isVolatile(), LD->getAlignment());
1977 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1978 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1982 // Since loads produce two values, make sure to remember that we
1983 // legalized both of them.
1984 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1985 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1986 return Op.ResNo ? Tmp4 : Tmp3;
1988 MVT SrcVT = LD->getMemoryVT();
1989 unsigned SrcWidth = SrcVT.getSizeInBits();
1990 int SVOffset = LD->getSrcValueOffset();
1991 unsigned Alignment = LD->getAlignment();
1992 bool isVolatile = LD->isVolatile();
1994 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
1995 // Some targets pretend to have an i1 loading operation, and actually
1996 // load an i8. This trick is correct for ZEXTLOAD because the top 7
1997 // bits are guaranteed to be zero; it helps the optimizers understand
1998 // that these bits are zero. It is also useful for EXTLOAD, since it
1999 // tells the optimizers that those bits are undefined. It would be
2000 // nice to have an effective generic way of getting these benefits...
2001 // Until such a way is found, don't insist on promoting i1 here.
2002 (SrcVT != MVT::i1 ||
2003 TLI.getLoadXAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
2004 // Promote to a byte-sized load if not loading an integral number of
2005 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
2006 unsigned NewWidth = SrcVT.getStoreSizeInBits();
2007 MVT NVT = MVT::getIntegerVT(NewWidth);
2010 // The extra bits are guaranteed to be zero, since we stored them that
2011 // way. A zext load from NVT thus automatically gives zext from SrcVT.
2013 ISD::LoadExtType NewExtType =
2014 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
2016 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0),
2017 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
2018 NVT, isVolatile, Alignment);
2020 Ch = Result.getValue(1); // The chain.
2022 if (ExtType == ISD::SEXTLOAD)
2023 // Having the top bits zero doesn't help when sign extending.
2024 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2025 Result, DAG.getValueType(SrcVT));
2026 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
2027 // All the top bits are guaranteed to be zero - inform the optimizers.
2028 Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result,
2029 DAG.getValueType(SrcVT));
2031 Tmp1 = LegalizeOp(Result);
2032 Tmp2 = LegalizeOp(Ch);
2033 } else if (SrcWidth & (SrcWidth - 1)) {
2034 // If not loading a power-of-2 number of bits, expand as two loads.
2035 assert(SrcVT.isExtended() && !SrcVT.isVector() &&
2036 "Unsupported extload!");
2037 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
2038 assert(RoundWidth < SrcWidth);
2039 unsigned ExtraWidth = SrcWidth - RoundWidth;
2040 assert(ExtraWidth < RoundWidth);
2041 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2042 "Load size not an integral number of bytes!");
2043 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2044 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2045 SDOperand Lo, Hi, Ch;
2046 unsigned IncrementSize;
2048 if (TLI.isLittleEndian()) {
2049 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
2050 // Load the bottom RoundWidth bits.
2051 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2052 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2055 // Load the remaining ExtraWidth bits.
2056 IncrementSize = RoundWidth / 8;
2057 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2058 DAG.getIntPtrConstant(IncrementSize));
2059 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2060 LD->getSrcValue(), SVOffset + IncrementSize,
2061 ExtraVT, isVolatile,
2062 MinAlign(Alignment, IncrementSize));
2064 // Build a factor node to remember that this load is independent of the
2066 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2069 // Move the top bits to the right place.
2070 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2071 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2073 // Join the hi and lo parts.
2074 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2076 // Big endian - avoid unaligned loads.
2077 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
2078 // Load the top RoundWidth bits.
2079 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2080 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2083 // Load the remaining ExtraWidth bits.
2084 IncrementSize = RoundWidth / 8;
2085 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2086 DAG.getIntPtrConstant(IncrementSize));
2087 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2088 LD->getSrcValue(), SVOffset + IncrementSize,
2089 ExtraVT, isVolatile,
2090 MinAlign(Alignment, IncrementSize));
2092 // Build a factor node to remember that this load is independent of the
2094 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2097 // Move the top bits to the right place.
2098 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2099 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2101 // Join the hi and lo parts.
2102 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2105 Tmp1 = LegalizeOp(Result);
2106 Tmp2 = LegalizeOp(Ch);
2108 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
2109 default: assert(0 && "This action is not supported yet!");
2110 case TargetLowering::Custom:
2113 case TargetLowering::Legal:
2114 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2115 Tmp1 = Result.getValue(0);
2116 Tmp2 = Result.getValue(1);
2119 Tmp3 = TLI.LowerOperation(Result, DAG);
2121 Tmp1 = LegalizeOp(Tmp3);
2122 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2125 // If this is an unaligned load and the target doesn't support it,
2127 if (!TLI.allowsUnalignedMemoryAccesses()) {
2128 unsigned ABIAlignment = TLI.getTargetData()->
2129 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
2130 if (LD->getAlignment() < ABIAlignment){
2131 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
2133 Tmp1 = Result.getOperand(0);
2134 Tmp2 = Result.getOperand(1);
2135 Tmp1 = LegalizeOp(Tmp1);
2136 Tmp2 = LegalizeOp(Tmp2);
2141 case TargetLowering::Expand:
2142 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
2143 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
2144 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
2145 LD->getSrcValueOffset(),
2146 LD->isVolatile(), LD->getAlignment());
2147 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
2148 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
2149 Tmp2 = LegalizeOp(Load.getValue(1));
2152 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
2153 // Turn the unsupported load into an EXTLOAD followed by an explicit
2154 // zero/sign extend inreg.
2155 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2156 Tmp1, Tmp2, LD->getSrcValue(),
2157 LD->getSrcValueOffset(), SrcVT,
2158 LD->isVolatile(), LD->getAlignment());
2160 if (ExtType == ISD::SEXTLOAD)
2161 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2162 Result, DAG.getValueType(SrcVT));
2164 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
2165 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
2166 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
2171 // Since loads produce two values, make sure to remember that we legalized
2173 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2174 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2175 return Op.ResNo ? Tmp2 : Tmp1;
2178 case ISD::EXTRACT_ELEMENT: {
2179 MVT OpTy = Node->getOperand(0).getValueType();
2180 switch (getTypeAction(OpTy)) {
2181 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
2183 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
2185 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
2186 DAG.getConstant(OpTy.getSizeInBits()/2,
2187 TLI.getShiftAmountTy()));
2188 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
2191 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
2192 Node->getOperand(0));
2196 // Get both the low and high parts.
2197 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2198 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
2199 Result = Tmp2; // 1 -> Hi
2201 Result = Tmp1; // 0 -> Lo
2207 case ISD::CopyToReg:
2208 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2210 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
2211 "Register type must be legal!");
2212 // Legalize the incoming value (must be a legal type).
2213 Tmp2 = LegalizeOp(Node->getOperand(2));
2214 if (Node->getNumValues() == 1) {
2215 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
2217 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
2218 if (Node->getNumOperands() == 4) {
2219 Tmp3 = LegalizeOp(Node->getOperand(3));
2220 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
2223 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
2226 // Since this produces two values, make sure to remember that we legalized
2228 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2229 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2235 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2237 // Ensure that libcalls are emitted before a return.
2238 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2239 Tmp1 = LegalizeOp(Tmp1);
2240 LastCALLSEQ_END = DAG.getEntryNode();
2242 switch (Node->getNumOperands()) {
2244 Tmp2 = Node->getOperand(1);
2245 Tmp3 = Node->getOperand(2); // Signness
2246 switch (getTypeAction(Tmp2.getValueType())) {
2248 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
2251 if (!Tmp2.getValueType().isVector()) {
2253 ExpandOp(Tmp2, Lo, Hi);
2255 // Big endian systems want the hi reg first.
2256 if (TLI.isBigEndian())
2260 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2262 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
2263 Result = LegalizeOp(Result);
2265 SDNode *InVal = Tmp2.Val;
2266 int InIx = Tmp2.ResNo;
2267 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
2268 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
2270 // Figure out if there is a simple type corresponding to this Vector
2271 // type. If so, convert to the vector type.
2272 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2273 if (TLI.isTypeLegal(TVT)) {
2274 // Turn this into a return of the vector type.
2275 Tmp2 = LegalizeOp(Tmp2);
2276 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2277 } else if (NumElems == 1) {
2278 // Turn this into a return of the scalar type.
2279 Tmp2 = ScalarizeVectorOp(Tmp2);
2280 Tmp2 = LegalizeOp(Tmp2);
2281 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2283 // FIXME: Returns of gcc generic vectors smaller than a legal type
2284 // should be returned in integer registers!
2286 // The scalarized value type may not be legal, e.g. it might require
2287 // promotion or expansion. Relegalize the return.
2288 Result = LegalizeOp(Result);
2290 // FIXME: Returns of gcc generic vectors larger than a legal vector
2291 // type should be returned by reference!
2293 SplitVectorOp(Tmp2, Lo, Hi);
2294 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2295 Result = LegalizeOp(Result);
2300 Tmp2 = PromoteOp(Node->getOperand(1));
2301 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2302 Result = LegalizeOp(Result);
2307 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2309 default: { // ret <values>
2310 SmallVector<SDOperand, 8> NewValues;
2311 NewValues.push_back(Tmp1);
2312 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
2313 switch (getTypeAction(Node->getOperand(i).getValueType())) {
2315 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
2316 NewValues.push_back(Node->getOperand(i+1));
2320 assert(!Node->getOperand(i).getValueType().isExtended() &&
2321 "FIXME: TODO: implement returning non-legal vector types!");
2322 ExpandOp(Node->getOperand(i), Lo, Hi);
2323 NewValues.push_back(Lo);
2324 NewValues.push_back(Node->getOperand(i+1));
2326 NewValues.push_back(Hi);
2327 NewValues.push_back(Node->getOperand(i+1));
2332 assert(0 && "Can't promote multiple return value yet!");
2335 if (NewValues.size() == Node->getNumOperands())
2336 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
2338 Result = DAG.getNode(ISD::RET, MVT::Other,
2339 &NewValues[0], NewValues.size());
2344 if (Result.getOpcode() == ISD::RET) {
2345 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
2346 default: assert(0 && "This action is not supported yet!");
2347 case TargetLowering::Legal: break;
2348 case TargetLowering::Custom:
2349 Tmp1 = TLI.LowerOperation(Result, DAG);
2350 if (Tmp1.Val) Result = Tmp1;
2356 StoreSDNode *ST = cast<StoreSDNode>(Node);
2357 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
2358 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
2359 int SVOffset = ST->getSrcValueOffset();
2360 unsigned Alignment = ST->getAlignment();
2361 bool isVolatile = ST->isVolatile();
2363 if (!ST->isTruncatingStore()) {
2364 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
2365 // FIXME: We shouldn't do this for TargetConstantFP's.
2366 // FIXME: move this to the DAG Combiner! Note that we can't regress due
2367 // to phase ordering between legalized code and the dag combiner. This
2368 // probably means that we need to integrate dag combiner and legalizer
2370 // We generally can't do this one for long doubles.
2371 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
2372 if (CFP->getValueType(0) == MVT::f32 &&
2373 getTypeAction(MVT::i32) == Legal) {
2374 Tmp3 = DAG.getConstant(CFP->getValueAPF().
2375 convertToAPInt().zextOrTrunc(32),
2377 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2378 SVOffset, isVolatile, Alignment);
2380 } else if (CFP->getValueType(0) == MVT::f64) {
2381 // If this target supports 64-bit registers, do a single 64-bit store.
2382 if (getTypeAction(MVT::i64) == Legal) {
2383 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt().
2384 zextOrTrunc(64), MVT::i64);
2385 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2386 SVOffset, isVolatile, Alignment);
2388 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
2389 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
2390 // stores. If the target supports neither 32- nor 64-bits, this
2391 // xform is certainly not worth it.
2392 const APInt &IntVal =CFP->getValueAPF().convertToAPInt();
2393 SDOperand Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
2394 SDOperand Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
2395 if (TLI.isBigEndian()) std::swap(Lo, Hi);
2397 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2398 SVOffset, isVolatile, Alignment);
2399 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2400 DAG.getIntPtrConstant(4));
2401 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
2402 isVolatile, MinAlign(Alignment, 4U));
2404 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2410 switch (getTypeAction(ST->getMemoryVT())) {
2412 Tmp3 = LegalizeOp(ST->getValue());
2413 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2416 MVT VT = Tmp3.getValueType();
2417 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2418 default: assert(0 && "This action is not supported yet!");
2419 case TargetLowering::Legal:
2420 // If this is an unaligned store and the target doesn't support it,
2422 if (!TLI.allowsUnalignedMemoryAccesses()) {
2423 unsigned ABIAlignment = TLI.getTargetData()->
2424 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2425 if (ST->getAlignment() < ABIAlignment)
2426 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2430 case TargetLowering::Custom:
2431 Tmp1 = TLI.LowerOperation(Result, DAG);
2432 if (Tmp1.Val) Result = Tmp1;
2434 case TargetLowering::Promote:
2435 assert(VT.isVector() && "Unknown legal promote case!");
2436 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
2437 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2438 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
2439 ST->getSrcValue(), SVOffset, isVolatile,
2446 // Truncate the value and store the result.
2447 Tmp3 = PromoteOp(ST->getValue());
2448 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2449 SVOffset, ST->getMemoryVT(),
2450 isVolatile, Alignment);
2454 unsigned IncrementSize = 0;
2457 // If this is a vector type, then we have to calculate the increment as
2458 // the product of the element size in bytes, and the number of elements
2459 // in the high half of the vector.
2460 if (ST->getValue().getValueType().isVector()) {
2461 SDNode *InVal = ST->getValue().Val;
2462 int InIx = ST->getValue().ResNo;
2463 MVT InVT = InVal->getValueType(InIx);
2464 unsigned NumElems = InVT.getVectorNumElements();
2465 MVT EVT = InVT.getVectorElementType();
2467 // Figure out if there is a simple type corresponding to this Vector
2468 // type. If so, convert to the vector type.
2469 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2470 if (TLI.isTypeLegal(TVT)) {
2471 // Turn this into a normal store of the vector type.
2472 Tmp3 = LegalizeOp(ST->getValue());
2473 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2474 SVOffset, isVolatile, Alignment);
2475 Result = LegalizeOp(Result);
2477 } else if (NumElems == 1) {
2478 // Turn this into a normal store of the scalar type.
2479 Tmp3 = ScalarizeVectorOp(ST->getValue());
2480 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2481 SVOffset, isVolatile, Alignment);
2482 // The scalarized value type may not be legal, e.g. it might require
2483 // promotion or expansion. Relegalize the scalar store.
2484 Result = LegalizeOp(Result);
2487 SplitVectorOp(ST->getValue(), Lo, Hi);
2488 IncrementSize = Lo.Val->getValueType(0).getVectorNumElements() *
2489 EVT.getSizeInBits()/8;
2492 ExpandOp(ST->getValue(), Lo, Hi);
2493 IncrementSize = Hi.Val ? Hi.getValueType().getSizeInBits()/8 : 0;
2495 if (TLI.isBigEndian())
2499 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2500 SVOffset, isVolatile, Alignment);
2502 if (Hi.Val == NULL) {
2503 // Must be int <-> float one-to-one expansion.
2508 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2509 DAG.getIntPtrConstant(IncrementSize));
2510 assert(isTypeLegal(Tmp2.getValueType()) &&
2511 "Pointers must be legal!");
2512 SVOffset += IncrementSize;
2513 Alignment = MinAlign(Alignment, IncrementSize);
2514 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2515 SVOffset, isVolatile, Alignment);
2516 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2520 switch (getTypeAction(ST->getValue().getValueType())) {
2522 Tmp3 = LegalizeOp(ST->getValue());
2525 // We can promote the value, the truncstore will still take care of it.
2526 Tmp3 = PromoteOp(ST->getValue());
2529 // Just store the low part. This may become a non-trunc store, so make
2530 // sure to use getTruncStore, not UpdateNodeOperands below.
2531 ExpandOp(ST->getValue(), Tmp3, Tmp4);
2532 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2533 SVOffset, MVT::i8, isVolatile, Alignment);
2536 MVT StVT = ST->getMemoryVT();
2537 unsigned StWidth = StVT.getSizeInBits();
2539 if (StWidth != StVT.getStoreSizeInBits()) {
2540 // Promote to a byte-sized store with upper bits zero if not
2541 // storing an integral number of bytes. For example, promote
2542 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
2543 MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits());
2544 Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT);
2545 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2546 SVOffset, NVT, isVolatile, Alignment);
2547 } else if (StWidth & (StWidth - 1)) {
2548 // If not storing a power-of-2 number of bits, expand as two stores.
2549 assert(StVT.isExtended() && !StVT.isVector() &&
2550 "Unsupported truncstore!");
2551 unsigned RoundWidth = 1 << Log2_32(StWidth);
2552 assert(RoundWidth < StWidth);
2553 unsigned ExtraWidth = StWidth - RoundWidth;
2554 assert(ExtraWidth < RoundWidth);
2555 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2556 "Store size not an integral number of bytes!");
2557 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2558 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2560 unsigned IncrementSize;
2562 if (TLI.isLittleEndian()) {
2563 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
2564 // Store the bottom RoundWidth bits.
2565 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2567 isVolatile, Alignment);
2569 // Store the remaining ExtraWidth bits.
2570 IncrementSize = RoundWidth / 8;
2571 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2572 DAG.getIntPtrConstant(IncrementSize));
2573 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2574 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2575 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2576 SVOffset + IncrementSize, ExtraVT, isVolatile,
2577 MinAlign(Alignment, IncrementSize));
2579 // Big endian - avoid unaligned stores.
2580 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
2581 // Store the top RoundWidth bits.
2582 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2583 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2584 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset,
2585 RoundVT, isVolatile, Alignment);
2587 // Store the remaining ExtraWidth bits.
2588 IncrementSize = RoundWidth / 8;
2589 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2590 DAG.getIntPtrConstant(IncrementSize));
2591 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2592 SVOffset + IncrementSize, ExtraVT, isVolatile,
2593 MinAlign(Alignment, IncrementSize));
2596 // The order of the stores doesn't matter.
2597 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2599 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2600 Tmp2 != ST->getBasePtr())
2601 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2604 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
2605 default: assert(0 && "This action is not supported yet!");
2606 case TargetLowering::Legal:
2607 // If this is an unaligned store and the target doesn't support it,
2609 if (!TLI.allowsUnalignedMemoryAccesses()) {
2610 unsigned ABIAlignment = TLI.getTargetData()->
2611 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2612 if (ST->getAlignment() < ABIAlignment)
2613 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2617 case TargetLowering::Custom:
2618 Result = TLI.LowerOperation(Result, DAG);
2621 // TRUNCSTORE:i16 i32 -> STORE i16
2622 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
2623 Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3);
2624 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset,
2625 isVolatile, Alignment);
2633 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2634 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2636 case ISD::STACKSAVE:
2637 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2638 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2639 Tmp1 = Result.getValue(0);
2640 Tmp2 = Result.getValue(1);
2642 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2643 default: assert(0 && "This action is not supported yet!");
2644 case TargetLowering::Legal: break;
2645 case TargetLowering::Custom:
2646 Tmp3 = TLI.LowerOperation(Result, DAG);
2648 Tmp1 = LegalizeOp(Tmp3);
2649 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2652 case TargetLowering::Expand:
2653 // Expand to CopyFromReg if the target set
2654 // StackPointerRegisterToSaveRestore.
2655 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2656 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
2657 Node->getValueType(0));
2658 Tmp2 = Tmp1.getValue(1);
2660 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
2661 Tmp2 = Node->getOperand(0);
2666 // Since stacksave produce two values, make sure to remember that we
2667 // legalized both of them.
2668 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2669 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2670 return Op.ResNo ? Tmp2 : Tmp1;
2672 case ISD::STACKRESTORE:
2673 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2674 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2675 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2677 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2678 default: assert(0 && "This action is not supported yet!");
2679 case TargetLowering::Legal: break;
2680 case TargetLowering::Custom:
2681 Tmp1 = TLI.LowerOperation(Result, DAG);
2682 if (Tmp1.Val) Result = Tmp1;
2684 case TargetLowering::Expand:
2685 // Expand to CopyToReg if the target set
2686 // StackPointerRegisterToSaveRestore.
2687 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2688 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
2696 case ISD::READCYCLECOUNTER:
2697 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2698 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2699 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2700 Node->getValueType(0))) {
2701 default: assert(0 && "This action is not supported yet!");
2702 case TargetLowering::Legal:
2703 Tmp1 = Result.getValue(0);
2704 Tmp2 = Result.getValue(1);
2706 case TargetLowering::Custom:
2707 Result = TLI.LowerOperation(Result, DAG);
2708 Tmp1 = LegalizeOp(Result.getValue(0));
2709 Tmp2 = LegalizeOp(Result.getValue(1));
2713 // Since rdcc produce two values, make sure to remember that we legalized
2715 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2716 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2720 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2721 case Expand: assert(0 && "It's impossible to expand bools");
2723 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2726 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2727 // Make sure the condition is either zero or one.
2728 unsigned BitWidth = Tmp1.getValueSizeInBits();
2729 if (!DAG.MaskedValueIsZero(Tmp1,
2730 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2731 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2735 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2736 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2738 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2740 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2741 default: assert(0 && "This action is not supported yet!");
2742 case TargetLowering::Legal: break;
2743 case TargetLowering::Custom: {
2744 Tmp1 = TLI.LowerOperation(Result, DAG);
2745 if (Tmp1.Val) Result = Tmp1;
2748 case TargetLowering::Expand:
2749 if (Tmp1.getOpcode() == ISD::SETCC) {
2750 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2752 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2754 Result = DAG.getSelectCC(Tmp1,
2755 DAG.getConstant(0, Tmp1.getValueType()),
2756 Tmp2, Tmp3, ISD::SETNE);
2759 case TargetLowering::Promote: {
2761 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2762 unsigned ExtOp, TruncOp;
2763 if (Tmp2.getValueType().isVector()) {
2764 ExtOp = ISD::BIT_CONVERT;
2765 TruncOp = ISD::BIT_CONVERT;
2766 } else if (Tmp2.getValueType().isInteger()) {
2767 ExtOp = ISD::ANY_EXTEND;
2768 TruncOp = ISD::TRUNCATE;
2770 ExtOp = ISD::FP_EXTEND;
2771 TruncOp = ISD::FP_ROUND;
2773 // Promote each of the values to the new type.
2774 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2775 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2776 // Perform the larger operation, then round down.
2777 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2778 if (TruncOp != ISD::FP_ROUND)
2779 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2781 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result,
2782 DAG.getIntPtrConstant(0));
2787 case ISD::SELECT_CC: {
2788 Tmp1 = Node->getOperand(0); // LHS
2789 Tmp2 = Node->getOperand(1); // RHS
2790 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2791 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2792 SDOperand CC = Node->getOperand(4);
2794 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
2796 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
2797 // the LHS is a legal SETCC itself. In this case, we need to compare
2798 // the result against zero to select between true and false values.
2799 if (Tmp2.Val == 0) {
2800 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2801 CC = DAG.getCondCode(ISD::SETNE);
2803 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
2805 // Everything is legal, see if we should expand this op or something.
2806 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
2807 default: assert(0 && "This action is not supported yet!");
2808 case TargetLowering::Legal: break;
2809 case TargetLowering::Custom:
2810 Tmp1 = TLI.LowerOperation(Result, DAG);
2811 if (Tmp1.Val) Result = Tmp1;
2817 Tmp1 = Node->getOperand(0);
2818 Tmp2 = Node->getOperand(1);
2819 Tmp3 = Node->getOperand(2);
2820 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
2822 // If we had to Expand the SetCC operands into a SELECT node, then it may
2823 // not always be possible to return a true LHS & RHS. In this case, just
2824 // return the value we legalized, returned in the LHS
2825 if (Tmp2.Val == 0) {
2830 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
2831 default: assert(0 && "Cannot handle this action for SETCC yet!");
2832 case TargetLowering::Custom:
2835 case TargetLowering::Legal:
2836 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2838 Tmp4 = TLI.LowerOperation(Result, DAG);
2839 if (Tmp4.Val) Result = Tmp4;
2842 case TargetLowering::Promote: {
2843 // First step, figure out the appropriate operation to use.
2844 // Allow SETCC to not be supported for all legal data types
2845 // Mostly this targets FP
2846 MVT NewInTy = Node->getOperand(0).getValueType();
2847 MVT OldVT = NewInTy; OldVT = OldVT;
2849 // Scan for the appropriate larger type to use.
2851 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
2853 assert(NewInTy.isInteger() == OldVT.isInteger() &&
2854 "Fell off of the edge of the integer world");
2855 assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() &&
2856 "Fell off of the edge of the floating point world");
2858 // If the target supports SETCC of this type, use it.
2859 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2862 if (NewInTy.isInteger())
2863 assert(0 && "Cannot promote Legal Integer SETCC yet");
2865 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2866 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2868 Tmp1 = LegalizeOp(Tmp1);
2869 Tmp2 = LegalizeOp(Tmp2);
2870 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2871 Result = LegalizeOp(Result);
2874 case TargetLowering::Expand:
2875 // Expand a setcc node into a select_cc of the same condition, lhs, and
2876 // rhs that selects between const 1 (true) and const 0 (false).
2877 MVT VT = Node->getValueType(0);
2878 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2879 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2885 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2886 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2887 SDOperand CC = Node->getOperand(2);
2889 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, CC);
2891 // Everything is legal, see if we should expand this op or something.
2892 switch (TLI.getOperationAction(ISD::VSETCC, Tmp1.getValueType())) {
2893 default: assert(0 && "This action is not supported yet!");
2894 case TargetLowering::Legal: break;
2895 case TargetLowering::Custom:
2896 Tmp1 = TLI.LowerOperation(Result, DAG);
2897 if (Tmp1.Val) Result = Tmp1;
2903 case ISD::SHL_PARTS:
2904 case ISD::SRA_PARTS:
2905 case ISD::SRL_PARTS: {
2906 SmallVector<SDOperand, 8> Ops;
2907 bool Changed = false;
2908 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2909 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2910 Changed |= Ops.back() != Node->getOperand(i);
2913 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2915 switch (TLI.getOperationAction(Node->getOpcode(),
2916 Node->getValueType(0))) {
2917 default: assert(0 && "This action is not supported yet!");
2918 case TargetLowering::Legal: break;
2919 case TargetLowering::Custom:
2920 Tmp1 = TLI.LowerOperation(Result, DAG);
2922 SDOperand Tmp2, RetVal(0, 0);
2923 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2924 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2925 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2929 assert(RetVal.Val && "Illegal result number");
2935 // Since these produce multiple values, make sure to remember that we
2936 // legalized all of them.
2937 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2938 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2939 return Result.getValue(Op.ResNo);
2961 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2962 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2963 case Expand: assert(0 && "Not possible");
2965 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2968 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2972 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2974 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2975 default: assert(0 && "BinOp legalize operation not supported");
2976 case TargetLowering::Legal: break;
2977 case TargetLowering::Custom:
2978 Tmp1 = TLI.LowerOperation(Result, DAG);
2979 if (Tmp1.Val) Result = Tmp1;
2981 case TargetLowering::Expand: {
2982 MVT VT = Op.getValueType();
2984 // See if multiply or divide can be lowered using two-result operations.
2985 SDVTList VTs = DAG.getVTList(VT, VT);
2986 if (Node->getOpcode() == ISD::MUL) {
2987 // We just need the low half of the multiply; try both the signed
2988 // and unsigned forms. If the target supports both SMUL_LOHI and
2989 // UMUL_LOHI, form a preference by checking which forms of plain
2990 // MULH it supports.
2991 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT);
2992 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT);
2993 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT);
2994 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT);
2995 unsigned OpToUse = 0;
2996 if (HasSMUL_LOHI && !HasMULHS) {
2997 OpToUse = ISD::SMUL_LOHI;
2998 } else if (HasUMUL_LOHI && !HasMULHU) {
2999 OpToUse = ISD::UMUL_LOHI;
3000 } else if (HasSMUL_LOHI) {
3001 OpToUse = ISD::SMUL_LOHI;
3002 } else if (HasUMUL_LOHI) {
3003 OpToUse = ISD::UMUL_LOHI;
3006 Result = SDOperand(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).Val, 0);
3010 if (Node->getOpcode() == ISD::MULHS &&
3011 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) {
3012 Result = SDOperand(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
3015 if (Node->getOpcode() == ISD::MULHU &&
3016 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) {
3017 Result = SDOperand(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
3020 if (Node->getOpcode() == ISD::SDIV &&
3021 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3022 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 0);
3025 if (Node->getOpcode() == ISD::UDIV &&
3026 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3027 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 0);
3031 // Check to see if we have a libcall for this operator.
3032 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3033 bool isSigned = false;
3034 switch (Node->getOpcode()) {
3037 if (VT == MVT::i32) {
3038 LC = Node->getOpcode() == ISD::UDIV
3039 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
3040 isSigned = Node->getOpcode() == ISD::SDIV;
3044 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
3045 RTLIB::POW_PPCF128);
3049 if (LC != RTLIB::UNKNOWN_LIBCALL) {
3051 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3055 assert(Node->getValueType(0).isVector() &&
3056 "Cannot expand this binary operator!");
3057 // Expand the operation into a bunch of nasty scalar code.
3058 Result = LegalizeOp(UnrollVectorOp(Op));
3061 case TargetLowering::Promote: {
3062 switch (Node->getOpcode()) {
3063 default: assert(0 && "Do not know how to promote this BinOp!");
3067 MVT OVT = Node->getValueType(0);
3068 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3069 assert(OVT.isVector() && "Cannot promote this BinOp!");
3070 // Bit convert each of the values to the new type.
3071 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
3072 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
3073 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3074 // Bit convert the result back the original type.
3075 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
3083 case ISD::SMUL_LOHI:
3084 case ISD::UMUL_LOHI:
3087 // These nodes will only be produced by target-specific lowering, so
3088 // they shouldn't be here if they aren't legal.
3089 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
3090 "This must be legal!");
3092 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3093 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3094 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3097 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
3098 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3099 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3100 case Expand: assert(0 && "Not possible");
3102 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3105 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3109 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3111 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3112 default: assert(0 && "Operation not supported");
3113 case TargetLowering::Custom:
3114 Tmp1 = TLI.LowerOperation(Result, DAG);
3115 if (Tmp1.Val) Result = Tmp1;
3117 case TargetLowering::Legal: break;
3118 case TargetLowering::Expand: {
3119 // If this target supports fabs/fneg natively and select is cheap,
3120 // do this efficiently.
3121 if (!TLI.isSelectExpensive() &&
3122 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
3123 TargetLowering::Legal &&
3124 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
3125 TargetLowering::Legal) {
3126 // Get the sign bit of the RHS.
3128 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
3129 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
3130 SignBit = DAG.getSetCC(TLI.getSetCCResultType(SignBit),
3131 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
3132 // Get the absolute value of the result.
3133 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
3134 // Select between the nabs and abs value based on the sign bit of
3136 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
3137 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
3140 Result = LegalizeOp(Result);
3144 // Otherwise, do bitwise ops!
3146 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
3147 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
3148 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
3149 Result = LegalizeOp(Result);
3157 Tmp1 = LegalizeOp(Node->getOperand(0));
3158 Tmp2 = LegalizeOp(Node->getOperand(1));
3159 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3160 // Since this produces two values, make sure to remember that we legalized
3162 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
3163 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
3168 Tmp1 = LegalizeOp(Node->getOperand(0));
3169 Tmp2 = LegalizeOp(Node->getOperand(1));
3170 Tmp3 = LegalizeOp(Node->getOperand(2));
3171 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3172 // Since this produces two values, make sure to remember that we legalized
3174 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
3175 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
3178 case ISD::BUILD_PAIR: {
3179 MVT PairTy = Node->getValueType(0);
3180 // TODO: handle the case where the Lo and Hi operands are not of legal type
3181 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
3182 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
3183 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
3184 case TargetLowering::Promote:
3185 case TargetLowering::Custom:
3186 assert(0 && "Cannot promote/custom this yet!");
3187 case TargetLowering::Legal:
3188 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
3189 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
3191 case TargetLowering::Expand:
3192 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
3193 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
3194 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
3195 DAG.getConstant(PairTy.getSizeInBits()/2,
3196 TLI.getShiftAmountTy()));
3197 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
3206 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3207 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3209 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3210 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
3211 case TargetLowering::Custom:
3214 case TargetLowering::Legal:
3215 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3217 Tmp1 = TLI.LowerOperation(Result, DAG);
3218 if (Tmp1.Val) Result = Tmp1;
3221 case TargetLowering::Expand: {
3222 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
3223 bool isSigned = DivOpc == ISD::SDIV;
3224 MVT VT = Node->getValueType(0);
3226 // See if remainder can be lowered using two-result operations.
3227 SDVTList VTs = DAG.getVTList(VT, VT);
3228 if (Node->getOpcode() == ISD::SREM &&
3229 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3230 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 1);
3233 if (Node->getOpcode() == ISD::UREM &&
3234 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3235 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 1);
3239 if (VT.isInteger()) {
3240 if (TLI.getOperationAction(DivOpc, VT) ==
3241 TargetLowering::Legal) {
3243 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
3244 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
3245 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
3246 } else if (VT.isVector()) {
3247 Result = LegalizeOp(UnrollVectorOp(Op));
3249 assert(VT == MVT::i32 &&
3250 "Cannot expand this binary operator!");
3251 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
3252 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
3254 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3257 assert(VT.isFloatingPoint() &&
3258 "remainder op must have integer or floating-point type");
3259 if (VT.isVector()) {
3260 Result = LegalizeOp(UnrollVectorOp(Op));
3262 // Floating point mod -> fmod libcall.
3263 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
3264 RTLIB::REM_F80, RTLIB::REM_PPCF128);
3266 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3274 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3275 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3277 MVT VT = Node->getValueType(0);
3278 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
3279 default: assert(0 && "This action is not supported yet!");
3280 case TargetLowering::Custom:
3283 case TargetLowering::Legal:
3284 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3285 Result = Result.getValue(0);
3286 Tmp1 = Result.getValue(1);
3289 Tmp2 = TLI.LowerOperation(Result, DAG);
3291 Result = LegalizeOp(Tmp2);
3292 Tmp1 = LegalizeOp(Tmp2.getValue(1));
3296 case TargetLowering::Expand: {
3297 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3298 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
3299 // Increment the pointer, VAList, to the next vaarg
3300 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3301 DAG.getConstant(VT.getSizeInBits()/8,
3302 TLI.getPointerTy()));
3303 // Store the incremented VAList to the legalized pointer
3304 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
3305 // Load the actual argument out of the pointer VAList
3306 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
3307 Tmp1 = LegalizeOp(Result.getValue(1));
3308 Result = LegalizeOp(Result);
3312 // Since VAARG produces two values, make sure to remember that we
3313 // legalized both of them.
3314 AddLegalizedOperand(SDOperand(Node, 0), Result);
3315 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
3316 return Op.ResNo ? Tmp1 : Result;
3320 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3321 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
3322 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
3324 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
3325 default: assert(0 && "This action is not supported yet!");
3326 case TargetLowering::Custom:
3329 case TargetLowering::Legal:
3330 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
3331 Node->getOperand(3), Node->getOperand(4));
3333 Tmp1 = TLI.LowerOperation(Result, DAG);
3334 if (Tmp1.Val) Result = Tmp1;
3337 case TargetLowering::Expand:
3338 // This defaults to loading a pointer from the input and storing it to the
3339 // output, returning the chain.
3340 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3341 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3342 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VS, 0);
3343 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VD, 0);
3349 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3350 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3352 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
3353 default: assert(0 && "This action is not supported yet!");
3354 case TargetLowering::Custom:
3357 case TargetLowering::Legal:
3358 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3360 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
3361 if (Tmp1.Val) Result = Tmp1;
3364 case TargetLowering::Expand:
3365 Result = Tmp1; // Default to a no-op, return the chain
3371 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3372 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3374 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3376 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
3377 default: assert(0 && "This action is not supported yet!");
3378 case TargetLowering::Legal: break;
3379 case TargetLowering::Custom:
3380 Tmp1 = TLI.LowerOperation(Result, DAG);
3381 if (Tmp1.Val) Result = Tmp1;
3388 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3389 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3390 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3391 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3393 assert(0 && "ROTL/ROTR legalize operation not supported");
3395 case TargetLowering::Legal:
3397 case TargetLowering::Custom:
3398 Tmp1 = TLI.LowerOperation(Result, DAG);
3399 if (Tmp1.Val) Result = Tmp1;
3401 case TargetLowering::Promote:
3402 assert(0 && "Do not know how to promote ROTL/ROTR");
3404 case TargetLowering::Expand:
3405 assert(0 && "Do not know how to expand ROTL/ROTR");
3411 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3412 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3413 case TargetLowering::Custom:
3414 assert(0 && "Cannot custom legalize this yet!");
3415 case TargetLowering::Legal:
3416 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3418 case TargetLowering::Promote: {
3419 MVT OVT = Tmp1.getValueType();
3420 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3421 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3423 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3424 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3425 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3426 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3429 case TargetLowering::Expand:
3430 Result = ExpandBSWAP(Tmp1);
3438 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3439 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3440 case TargetLowering::Custom:
3441 case TargetLowering::Legal:
3442 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3443 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3444 TargetLowering::Custom) {
3445 Tmp1 = TLI.LowerOperation(Result, DAG);
3451 case TargetLowering::Promote: {
3452 MVT OVT = Tmp1.getValueType();
3453 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3455 // Zero extend the argument.
3456 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3457 // Perform the larger operation, then subtract if needed.
3458 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
3459 switch (Node->getOpcode()) {
3464 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3465 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
3466 DAG.getConstant(NVT.getSizeInBits(), NVT),
3468 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3469 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3472 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3473 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3474 DAG.getConstant(NVT.getSizeInBits() -
3475 OVT.getSizeInBits(), NVT));
3480 case TargetLowering::Expand:
3481 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
3492 Tmp1 = LegalizeOp(Node->getOperand(0));
3493 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3494 case TargetLowering::Promote:
3495 case TargetLowering::Custom:
3498 case TargetLowering::Legal:
3499 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3501 Tmp1 = TLI.LowerOperation(Result, DAG);
3502 if (Tmp1.Val) Result = Tmp1;
3505 case TargetLowering::Expand:
3506 switch (Node->getOpcode()) {
3507 default: assert(0 && "Unreachable!");
3509 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3510 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3511 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
3514 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3515 MVT VT = Node->getValueType(0);
3516 Tmp2 = DAG.getConstantFP(0.0, VT);
3517 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
3519 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
3520 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
3526 MVT VT = Node->getValueType(0);
3528 // Expand unsupported unary vector operators by unrolling them.
3529 if (VT.isVector()) {
3530 Result = LegalizeOp(UnrollVectorOp(Op));
3534 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3535 switch(Node->getOpcode()) {
3537 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3538 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
3541 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
3542 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
3545 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
3546 RTLIB::COS_F80, RTLIB::COS_PPCF128);
3548 default: assert(0 && "Unreachable!");
3551 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3559 MVT VT = Node->getValueType(0);
3561 // Expand unsupported unary vector operators by unrolling them.
3562 if (VT.isVector()) {
3563 Result = LegalizeOp(UnrollVectorOp(Op));
3567 // We always lower FPOWI into a libcall. No target support for it yet.
3568 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
3569 RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
3571 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3574 case ISD::BIT_CONVERT:
3575 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3576 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3577 Node->getValueType(0));
3578 } else if (Op.getOperand(0).getValueType().isVector()) {
3579 // The input has to be a vector type, we have to either scalarize it, pack
3580 // it, or convert it based on whether the input vector type is legal.
3581 SDNode *InVal = Node->getOperand(0).Val;
3582 int InIx = Node->getOperand(0).ResNo;
3583 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
3584 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
3586 // Figure out if there is a simple type corresponding to this Vector
3587 // type. If so, convert to the vector type.
3588 MVT TVT = MVT::getVectorVT(EVT, NumElems);
3589 if (TLI.isTypeLegal(TVT)) {
3590 // Turn this into a bit convert of the vector input.
3591 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3592 LegalizeOp(Node->getOperand(0)));
3594 } else if (NumElems == 1) {
3595 // Turn this into a bit convert of the scalar input.
3596 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3597 ScalarizeVectorOp(Node->getOperand(0)));
3600 // FIXME: UNIMP! Store then reload
3601 assert(0 && "Cast from unsupported vector type not implemented yet!");
3604 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3605 Node->getOperand(0).getValueType())) {
3606 default: assert(0 && "Unknown operation action!");
3607 case TargetLowering::Expand:
3608 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3609 Node->getValueType(0));
3611 case TargetLowering::Legal:
3612 Tmp1 = LegalizeOp(Node->getOperand(0));
3613 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3619 // Conversion operators. The source and destination have different types.
3620 case ISD::SINT_TO_FP:
3621 case ISD::UINT_TO_FP: {
3622 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
3623 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3625 switch (TLI.getOperationAction(Node->getOpcode(),
3626 Node->getOperand(0).getValueType())) {
3627 default: assert(0 && "Unknown operation action!");
3628 case TargetLowering::Custom:
3631 case TargetLowering::Legal:
3632 Tmp1 = LegalizeOp(Node->getOperand(0));
3633 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3635 Tmp1 = TLI.LowerOperation(Result, DAG);
3636 if (Tmp1.Val) Result = Tmp1;
3639 case TargetLowering::Expand:
3640 Result = ExpandLegalINT_TO_FP(isSigned,
3641 LegalizeOp(Node->getOperand(0)),
3642 Node->getValueType(0));
3644 case TargetLowering::Promote:
3645 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
3646 Node->getValueType(0),
3652 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
3653 Node->getValueType(0), Node->getOperand(0));
3656 Tmp1 = PromoteOp(Node->getOperand(0));
3658 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
3659 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
3661 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
3662 Node->getOperand(0).getValueType());
3664 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3665 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
3671 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3673 Tmp1 = LegalizeOp(Node->getOperand(0));
3674 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3677 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3679 // Since the result is legal, we should just be able to truncate the low
3680 // part of the source.
3681 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
3684 Result = PromoteOp(Node->getOperand(0));
3685 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
3690 case ISD::FP_TO_SINT:
3691 case ISD::FP_TO_UINT:
3692 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3694 Tmp1 = LegalizeOp(Node->getOperand(0));
3696 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
3697 default: assert(0 && "Unknown operation action!");
3698 case TargetLowering::Custom:
3701 case TargetLowering::Legal:
3702 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3704 Tmp1 = TLI.LowerOperation(Result, DAG);
3705 if (Tmp1.Val) Result = Tmp1;
3708 case TargetLowering::Promote:
3709 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
3710 Node->getOpcode() == ISD::FP_TO_SINT);
3712 case TargetLowering::Expand:
3713 if (Node->getOpcode() == ISD::FP_TO_UINT) {
3714 SDOperand True, False;
3715 MVT VT = Node->getOperand(0).getValueType();
3716 MVT NVT = Node->getValueType(0);
3717 const uint64_t zero[] = {0, 0};
3718 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero));
3719 APInt x = APInt::getSignBit(NVT.getSizeInBits());
3720 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
3721 Tmp2 = DAG.getConstantFP(apf, VT);
3722 Tmp3 = DAG.getSetCC(TLI.getSetCCResultType(Node->getOperand(0)),
3723 Node->getOperand(0), Tmp2, ISD::SETLT);
3724 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
3725 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
3726 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
3728 False = DAG.getNode(ISD::XOR, NVT, False,
3729 DAG.getConstant(x, NVT));
3730 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
3733 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
3739 MVT VT = Op.getValueType();
3740 MVT OVT = Node->getOperand(0).getValueType();
3741 // Convert ppcf128 to i32
3742 if (OVT == MVT::ppcf128 && VT == MVT::i32) {
3743 if (Node->getOpcode() == ISD::FP_TO_SINT) {
3744 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128,
3745 Node->getOperand(0), DAG.getValueType(MVT::f64));
3746 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result,
3747 DAG.getIntPtrConstant(1));
3748 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result);
3750 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
3751 APFloat apf = APFloat(APInt(128, 2, TwoE31));
3752 Tmp2 = DAG.getConstantFP(apf, OVT);
3753 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
3754 // FIXME: generated code sucks.
3755 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2,
3756 DAG.getNode(ISD::ADD, MVT::i32,
3757 DAG.getNode(ISD::FP_TO_SINT, VT,
3758 DAG.getNode(ISD::FSUB, OVT,
3759 Node->getOperand(0), Tmp2)),
3760 DAG.getConstant(0x80000000, MVT::i32)),
3761 DAG.getNode(ISD::FP_TO_SINT, VT,
3762 Node->getOperand(0)),
3763 DAG.getCondCode(ISD::SETGE));
3767 // Convert f32 / f64 to i32 / i64 / i128.
3768 RTLIB::Libcall LC = (Node->getOpcode() == ISD::FP_TO_SINT) ?
3769 RTLIB::getFPTOSINT(OVT, VT) : RTLIB::getFPTOUINT(OVT, VT);
3770 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpectd fp-to-int conversion!");
3772 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3776 Tmp1 = PromoteOp(Node->getOperand(0));
3777 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
3778 Result = LegalizeOp(Result);
3783 case ISD::FP_EXTEND: {
3784 MVT DstVT = Op.getValueType();
3785 MVT SrcVT = Op.getOperand(0).getValueType();
3786 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3787 // The only other way we can lower this is to turn it into a STORE,
3788 // LOAD pair, targetting a temporary location (a stack slot).
3789 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT);
3792 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3793 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3795 Tmp1 = LegalizeOp(Node->getOperand(0));
3796 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3799 Tmp1 = PromoteOp(Node->getOperand(0));
3800 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1);
3805 case ISD::FP_ROUND: {
3806 MVT DstVT = Op.getValueType();
3807 MVT SrcVT = Op.getOperand(0).getValueType();
3808 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3809 if (SrcVT == MVT::ppcf128) {
3811 ExpandOp(Node->getOperand(0), Lo, Result);
3812 // Round it the rest of the way (e.g. to f32) if needed.
3813 if (DstVT!=MVT::f64)
3814 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1));
3817 // The only other way we can lower this is to turn it into a STORE,
3818 // LOAD pair, targetting a temporary location (a stack slot).
3819 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT);
3822 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3823 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3825 Tmp1 = LegalizeOp(Node->getOperand(0));
3826 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3829 Tmp1 = PromoteOp(Node->getOperand(0));
3830 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1,
3831 Node->getOperand(1));
3836 case ISD::ANY_EXTEND:
3837 case ISD::ZERO_EXTEND:
3838 case ISD::SIGN_EXTEND:
3839 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3840 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3842 Tmp1 = LegalizeOp(Node->getOperand(0));
3843 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3844 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3845 TargetLowering::Custom) {
3846 Tmp1 = TLI.LowerOperation(Result, DAG);
3847 if (Tmp1.Val) Result = Tmp1;
3851 switch (Node->getOpcode()) {
3852 case ISD::ANY_EXTEND:
3853 Tmp1 = PromoteOp(Node->getOperand(0));
3854 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
3856 case ISD::ZERO_EXTEND:
3857 Result = PromoteOp(Node->getOperand(0));
3858 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3859 Result = DAG.getZeroExtendInReg(Result,
3860 Node->getOperand(0).getValueType());
3862 case ISD::SIGN_EXTEND:
3863 Result = PromoteOp(Node->getOperand(0));
3864 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3865 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3867 DAG.getValueType(Node->getOperand(0).getValueType()));
3872 case ISD::FP_ROUND_INREG:
3873 case ISD::SIGN_EXTEND_INREG: {
3874 Tmp1 = LegalizeOp(Node->getOperand(0));
3875 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3877 // If this operation is not supported, convert it to a shl/shr or load/store
3879 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
3880 default: assert(0 && "This action not supported for this op yet!");
3881 case TargetLowering::Legal:
3882 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3884 case TargetLowering::Expand:
3885 // If this is an integer extend and shifts are supported, do that.
3886 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
3887 // NOTE: we could fall back on load/store here too for targets without
3888 // SAR. However, it is doubtful that any exist.
3889 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() -
3890 ExtraVT.getSizeInBits();
3891 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
3892 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
3893 Node->getOperand(0), ShiftCst);
3894 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
3896 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
3897 // The only way we can lower this is to turn it into a TRUNCSTORE,
3898 // EXTLOAD pair, targetting a temporary location (a stack slot).
3900 // NOTE: there is a choice here between constantly creating new stack
3901 // slots and always reusing the same one. We currently always create
3902 // new ones, as reuse may inhibit scheduling.
3903 Result = EmitStackConvert(Node->getOperand(0), ExtraVT,
3904 Node->getValueType(0));
3906 assert(0 && "Unknown op");
3912 case ISD::TRAMPOLINE: {
3914 for (unsigned i = 0; i != 6; ++i)
3915 Ops[i] = LegalizeOp(Node->getOperand(i));
3916 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
3917 // The only option for this node is to custom lower it.
3918 Result = TLI.LowerOperation(Result, DAG);
3919 assert(Result.Val && "Should always custom lower!");
3921 // Since trampoline produces two values, make sure to remember that we
3922 // legalized both of them.
3923 Tmp1 = LegalizeOp(Result.getValue(1));
3924 Result = LegalizeOp(Result);
3925 AddLegalizedOperand(SDOperand(Node, 0), Result);
3926 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
3927 return Op.ResNo ? Tmp1 : Result;
3929 case ISD::FLT_ROUNDS_: {
3930 MVT VT = Node->getValueType(0);
3931 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
3932 default: assert(0 && "This action not supported for this op yet!");
3933 case TargetLowering::Custom:
3934 Result = TLI.LowerOperation(Op, DAG);
3935 if (Result.Val) break;
3937 case TargetLowering::Legal:
3938 // If this operation is not supported, lower it to constant 1
3939 Result = DAG.getConstant(1, VT);
3945 MVT VT = Node->getValueType(0);
3946 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
3947 default: assert(0 && "This action not supported for this op yet!");
3948 case TargetLowering::Legal:
3949 Tmp1 = LegalizeOp(Node->getOperand(0));
3950 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3952 case TargetLowering::Custom:
3953 Result = TLI.LowerOperation(Op, DAG);
3954 if (Result.Val) break;
3956 case TargetLowering::Expand:
3957 // If this operation is not supported, lower it to 'abort()' call
3958 Tmp1 = LegalizeOp(Node->getOperand(0));
3959 TargetLowering::ArgListTy Args;
3960 std::pair<SDOperand,SDOperand> CallResult =
3961 TLI.LowerCallTo(Tmp1, Type::VoidTy,
3962 false, false, false, CallingConv::C, false,
3963 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
3965 Result = CallResult.second;
3972 assert(Result.getValueType() == Op.getValueType() &&
3973 "Bad legalization!");
3975 // Make sure that the generated code is itself legal.
3977 Result = LegalizeOp(Result);
3979 // Note that LegalizeOp may be reentered even from single-use nodes, which
3980 // means that we always must cache transformed nodes.
3981 AddLegalizedOperand(Op, Result);
3985 /// PromoteOp - Given an operation that produces a value in an invalid type,
3986 /// promote it to compute the value into a larger type. The produced value will
3987 /// have the correct bits for the low portion of the register, but no guarantee
3988 /// is made about the top bits: it may be zero, sign-extended, or garbage.
3989 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
3990 MVT VT = Op.getValueType();
3991 MVT NVT = TLI.getTypeToTransformTo(VT);
3992 assert(getTypeAction(VT) == Promote &&
3993 "Caller should expand or legalize operands that are not promotable!");
3994 assert(NVT.bitsGT(VT) && NVT.isInteger() == VT.isInteger() &&
3995 "Cannot promote to smaller type!");
3997 SDOperand Tmp1, Tmp2, Tmp3;
3999 SDNode *Node = Op.Val;
4001 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
4002 if (I != PromotedNodes.end()) return I->second;
4004 switch (Node->getOpcode()) {
4005 case ISD::CopyFromReg:
4006 assert(0 && "CopyFromReg must be legal!");
4009 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
4011 assert(0 && "Do not know how to promote this operator!");
4014 Result = DAG.getNode(ISD::UNDEF, NVT);
4018 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
4020 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
4021 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
4023 case ISD::ConstantFP:
4024 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
4025 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
4029 assert(isTypeLegal(TLI.getSetCCResultType(Node->getOperand(0)))
4030 && "SetCC type is not legal??");
4031 Result = DAG.getNode(ISD::SETCC,
4032 TLI.getSetCCResultType(Node->getOperand(0)),
4033 Node->getOperand(0), Node->getOperand(1),
4034 Node->getOperand(2));
4038 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4040 Result = LegalizeOp(Node->getOperand(0));
4041 assert(Result.getValueType().bitsGE(NVT) &&
4042 "This truncation doesn't make sense!");
4043 if (Result.getValueType().bitsGT(NVT)) // Truncate to NVT instead of VT
4044 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
4047 // The truncation is not required, because we don't guarantee anything
4048 // about high bits anyway.
4049 Result = PromoteOp(Node->getOperand(0));
4052 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4053 // Truncate the low part of the expanded value to the result type
4054 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
4057 case ISD::SIGN_EXTEND:
4058 case ISD::ZERO_EXTEND:
4059 case ISD::ANY_EXTEND:
4060 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4061 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
4063 // Input is legal? Just do extend all the way to the larger type.
4064 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4067 // Promote the reg if it's smaller.
4068 Result = PromoteOp(Node->getOperand(0));
4069 // The high bits are not guaranteed to be anything. Insert an extend.
4070 if (Node->getOpcode() == ISD::SIGN_EXTEND)
4071 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4072 DAG.getValueType(Node->getOperand(0).getValueType()));
4073 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
4074 Result = DAG.getZeroExtendInReg(Result,
4075 Node->getOperand(0).getValueType());
4079 case ISD::BIT_CONVERT:
4080 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
4081 Node->getValueType(0));
4082 Result = PromoteOp(Result);
4085 case ISD::FP_EXTEND:
4086 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
4088 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4089 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
4090 case Promote: assert(0 && "Unreachable with 2 FP types!");
4092 if (Node->getConstantOperandVal(1) == 0) {
4093 // Input is legal? Do an FP_ROUND_INREG.
4094 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
4095 DAG.getValueType(VT));
4097 // Just remove the truncate, it isn't affecting the value.
4098 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0),
4099 Node->getOperand(1));
4104 case ISD::SINT_TO_FP:
4105 case ISD::UINT_TO_FP:
4106 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4108 // No extra round required here.
4109 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4113 Result = PromoteOp(Node->getOperand(0));
4114 if (Node->getOpcode() == ISD::SINT_TO_FP)
4115 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
4117 DAG.getValueType(Node->getOperand(0).getValueType()));
4119 Result = DAG.getZeroExtendInReg(Result,
4120 Node->getOperand(0).getValueType());
4121 // No extra round required here.
4122 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
4125 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
4126 Node->getOperand(0));
4127 // Round if we cannot tolerate excess precision.
4128 if (NoExcessFPPrecision)
4129 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4130 DAG.getValueType(VT));
4135 case ISD::SIGN_EXTEND_INREG:
4136 Result = PromoteOp(Node->getOperand(0));
4137 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4138 Node->getOperand(1));
4140 case ISD::FP_TO_SINT:
4141 case ISD::FP_TO_UINT:
4142 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4145 Tmp1 = Node->getOperand(0);
4148 // The input result is prerounded, so we don't have to do anything
4150 Tmp1 = PromoteOp(Node->getOperand(0));
4153 // If we're promoting a UINT to a larger size, check to see if the new node
4154 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
4155 // we can use that instead. This allows us to generate better code for
4156 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
4157 // legal, such as PowerPC.
4158 if (Node->getOpcode() == ISD::FP_TO_UINT &&
4159 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
4160 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
4161 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
4162 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
4164 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4170 Tmp1 = PromoteOp(Node->getOperand(0));
4171 assert(Tmp1.getValueType() == NVT);
4172 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4173 // NOTE: we do not have to do any extra rounding here for
4174 // NoExcessFPPrecision, because we know the input will have the appropriate
4175 // precision, and these operations don't modify precision at all.
4181 Tmp1 = PromoteOp(Node->getOperand(0));
4182 assert(Tmp1.getValueType() == NVT);
4183 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4184 if (NoExcessFPPrecision)
4185 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4186 DAG.getValueType(VT));
4190 // Promote f32 powi to f64 powi. Note that this could insert a libcall
4191 // directly as well, which may be better.
4192 Tmp1 = PromoteOp(Node->getOperand(0));
4193 assert(Tmp1.getValueType() == NVT);
4194 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1));
4195 if (NoExcessFPPrecision)
4196 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4197 DAG.getValueType(VT));
4201 case ISD::ATOMIC_CMP_SWAP: {
4202 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4203 Tmp2 = PromoteOp(Node->getOperand(2));
4204 Tmp3 = PromoteOp(Node->getOperand(3));
4205 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(),
4206 AtomNode->getBasePtr(), Tmp2, Tmp3,
4207 AtomNode->getSrcValue(),
4208 AtomNode->getAlignment());
4209 // Remember that we legalized the chain.
4210 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4213 case ISD::ATOMIC_LOAD_ADD:
4214 case ISD::ATOMIC_LOAD_SUB:
4215 case ISD::ATOMIC_LOAD_AND:
4216 case ISD::ATOMIC_LOAD_OR:
4217 case ISD::ATOMIC_LOAD_XOR:
4218 case ISD::ATOMIC_LOAD_NAND:
4219 case ISD::ATOMIC_LOAD_MIN:
4220 case ISD::ATOMIC_LOAD_MAX:
4221 case ISD::ATOMIC_LOAD_UMIN:
4222 case ISD::ATOMIC_LOAD_UMAX:
4223 case ISD::ATOMIC_SWAP: {
4224 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4225 Tmp2 = PromoteOp(Node->getOperand(2));
4226 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(),
4227 AtomNode->getBasePtr(), Tmp2,
4228 AtomNode->getSrcValue(),
4229 AtomNode->getAlignment());
4230 // Remember that we legalized the chain.
4231 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4241 // The input may have strange things in the top bits of the registers, but
4242 // these operations don't care. They may have weird bits going out, but
4243 // that too is okay if they are integer operations.
4244 Tmp1 = PromoteOp(Node->getOperand(0));
4245 Tmp2 = PromoteOp(Node->getOperand(1));
4246 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4247 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4252 Tmp1 = PromoteOp(Node->getOperand(0));
4253 Tmp2 = PromoteOp(Node->getOperand(1));
4254 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4255 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4257 // Floating point operations will give excess precision that we may not be
4258 // able to tolerate. If we DO allow excess precision, just leave it,
4259 // otherwise excise it.
4260 // FIXME: Why would we need to round FP ops more than integer ones?
4261 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
4262 if (NoExcessFPPrecision)
4263 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4264 DAG.getValueType(VT));
4269 // These operators require that their input be sign extended.
4270 Tmp1 = PromoteOp(Node->getOperand(0));
4271 Tmp2 = PromoteOp(Node->getOperand(1));
4272 if (NVT.isInteger()) {
4273 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4274 DAG.getValueType(VT));
4275 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4276 DAG.getValueType(VT));
4278 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4280 // Perform FP_ROUND: this is probably overly pessimistic.
4281 if (NVT.isFloatingPoint() && NoExcessFPPrecision)
4282 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4283 DAG.getValueType(VT));
4287 case ISD::FCOPYSIGN:
4288 // These operators require that their input be fp extended.
4289 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4290 case Expand: assert(0 && "not implemented");
4291 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break;
4292 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break;
4294 switch (getTypeAction(Node->getOperand(1).getValueType())) {
4295 case Expand: assert(0 && "not implemented");
4296 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
4297 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
4299 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4301 // Perform FP_ROUND: this is probably overly pessimistic.
4302 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
4303 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4304 DAG.getValueType(VT));
4309 // These operators require that their input be zero extended.
4310 Tmp1 = PromoteOp(Node->getOperand(0));
4311 Tmp2 = PromoteOp(Node->getOperand(1));
4312 assert(NVT.isInteger() && "Operators don't apply to FP!");
4313 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4314 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4315 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4319 Tmp1 = PromoteOp(Node->getOperand(0));
4320 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
4323 // The input value must be properly sign extended.
4324 Tmp1 = PromoteOp(Node->getOperand(0));
4325 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4326 DAG.getValueType(VT));
4327 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
4330 // The input value must be properly zero extended.
4331 Tmp1 = PromoteOp(Node->getOperand(0));
4332 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4333 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
4337 Tmp1 = Node->getOperand(0); // Get the chain.
4338 Tmp2 = Node->getOperand(1); // Get the pointer.
4339 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
4340 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
4341 Result = TLI.LowerOperation(Tmp3, DAG);
4343 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
4344 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
4345 // Increment the pointer, VAList, to the next vaarg
4346 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
4347 DAG.getConstant(VT.getSizeInBits()/8,
4348 TLI.getPointerTy()));
4349 // Store the incremented VAList to the legalized pointer
4350 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
4351 // Load the actual argument out of the pointer VAList
4352 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
4354 // Remember that we legalized the chain.
4355 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4359 LoadSDNode *LD = cast<LoadSDNode>(Node);
4360 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
4361 ? ISD::EXTLOAD : LD->getExtensionType();
4362 Result = DAG.getExtLoad(ExtType, NVT,
4363 LD->getChain(), LD->getBasePtr(),
4364 LD->getSrcValue(), LD->getSrcValueOffset(),
4367 LD->getAlignment());
4368 // Remember that we legalized the chain.
4369 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4373 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
4374 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
4376 MVT VT2 = Tmp2.getValueType();
4377 assert(VT2 == Tmp3.getValueType()
4378 && "PromoteOp SELECT: Operands 2 and 3 ValueTypes don't match");
4379 // Ensure that the resulting node is at least the same size as the operands'
4380 // value types, because we cannot assume that TLI.getSetCCValueType() is
4382 Result = DAG.getNode(ISD::SELECT, VT2, Node->getOperand(0), Tmp2, Tmp3);
4385 case ISD::SELECT_CC:
4386 Tmp2 = PromoteOp(Node->getOperand(2)); // True
4387 Tmp3 = PromoteOp(Node->getOperand(3)); // False
4388 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4389 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
4392 Tmp1 = Node->getOperand(0);
4393 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
4394 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
4395 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
4396 DAG.getConstant(NVT.getSizeInBits() -
4398 TLI.getShiftAmountTy()));
4403 // Zero extend the argument
4404 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4405 // Perform the larger operation, then subtract if needed.
4406 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4407 switch(Node->getOpcode()) {
4412 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
4413 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
4414 DAG.getConstant(NVT.getSizeInBits(), NVT),
4416 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
4417 DAG.getConstant(VT.getSizeInBits(), NVT), Tmp1);
4420 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4421 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
4422 DAG.getConstant(NVT.getSizeInBits() -
4423 VT.getSizeInBits(), NVT));
4427 case ISD::EXTRACT_SUBVECTOR:
4428 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
4430 case ISD::EXTRACT_VECTOR_ELT:
4431 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
4435 assert(Result.Val && "Didn't set a result!");
4437 // Make sure the result is itself legal.
4438 Result = LegalizeOp(Result);
4440 // Remember that we promoted this!
4441 AddPromotedOperand(Op, Result);
4445 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
4446 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
4447 /// based on the vector type. The return type of this matches the element type
4448 /// of the vector, which may not be legal for the target.
4449 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
4450 // We know that operand #0 is the Vec vector. If the index is a constant
4451 // or if the invec is a supported hardware type, we can use it. Otherwise,
4452 // lower to a store then an indexed load.
4453 SDOperand Vec = Op.getOperand(0);
4454 SDOperand Idx = Op.getOperand(1);
4456 MVT TVT = Vec.getValueType();
4457 unsigned NumElems = TVT.getVectorNumElements();
4459 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
4460 default: assert(0 && "This action is not supported yet!");
4461 case TargetLowering::Custom: {
4462 Vec = LegalizeOp(Vec);
4463 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4464 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG);
4469 case TargetLowering::Legal:
4470 if (isTypeLegal(TVT)) {
4471 Vec = LegalizeOp(Vec);
4472 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4476 case TargetLowering::Expand:
4480 if (NumElems == 1) {
4481 // This must be an access of the only element. Return it.
4482 Op = ScalarizeVectorOp(Vec);
4483 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
4484 unsigned NumLoElts = 1 << Log2_32(NumElems-1);
4485 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4487 SplitVectorOp(Vec, Lo, Hi);
4488 if (CIdx->getValue() < NumLoElts) {
4492 Idx = DAG.getConstant(CIdx->getValue() - NumLoElts,
4493 Idx.getValueType());
4496 // It's now an extract from the appropriate high or low part. Recurse.
4497 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4498 Op = ExpandEXTRACT_VECTOR_ELT(Op);
4500 // Store the value to a temporary stack slot, then LOAD the scalar
4501 // element back out.
4502 SDOperand StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
4503 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
4505 // Add the offset to the index.
4506 unsigned EltSize = Op.getValueType().getSizeInBits()/8;
4507 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
4508 DAG.getConstant(EltSize, Idx.getValueType()));
4510 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
4511 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx);
4513 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
4515 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
4517 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
4522 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
4523 /// we assume the operation can be split if it is not already legal.
4524 SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) {
4525 // We know that operand #0 is the Vec vector. For now we assume the index
4526 // is a constant and that the extracted result is a supported hardware type.
4527 SDOperand Vec = Op.getOperand(0);
4528 SDOperand Idx = LegalizeOp(Op.getOperand(1));
4530 unsigned NumElems = Vec.getValueType().getVectorNumElements();
4532 if (NumElems == Op.getValueType().getVectorNumElements()) {
4533 // This must be an access of the desired vector length. Return it.
4537 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4539 SplitVectorOp(Vec, Lo, Hi);
4540 if (CIdx->getValue() < NumElems/2) {
4544 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
4547 // It's now an extract from the appropriate high or low part. Recurse.
4548 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4549 return ExpandEXTRACT_SUBVECTOR(Op);
4552 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
4553 /// with condition CC on the current target. This usually involves legalizing
4554 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
4555 /// there may be no choice but to create a new SetCC node to represent the
4556 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
4557 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
4558 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
4561 SDOperand Tmp1, Tmp2, Tmp3, Result;
4563 switch (getTypeAction(LHS.getValueType())) {
4565 Tmp1 = LegalizeOp(LHS); // LHS
4566 Tmp2 = LegalizeOp(RHS); // RHS
4569 Tmp1 = PromoteOp(LHS); // LHS
4570 Tmp2 = PromoteOp(RHS); // RHS
4572 // If this is an FP compare, the operands have already been extended.
4573 if (LHS.getValueType().isInteger()) {
4574 MVT VT = LHS.getValueType();
4575 MVT NVT = TLI.getTypeToTransformTo(VT);
4577 // Otherwise, we have to insert explicit sign or zero extends. Note
4578 // that we could insert sign extends for ALL conditions, but zero extend
4579 // is cheaper on many machines (an AND instead of two shifts), so prefer
4581 switch (cast<CondCodeSDNode>(CC)->get()) {
4582 default: assert(0 && "Unknown integer comparison!");
4589 // ALL of these operations will work if we either sign or zero extend
4590 // the operands (including the unsigned comparisons!). Zero extend is
4591 // usually a simpler/cheaper operation, so prefer it.
4592 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4593 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4599 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4600 DAG.getValueType(VT));
4601 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4602 DAG.getValueType(VT));
4608 MVT VT = LHS.getValueType();
4609 if (VT == MVT::f32 || VT == MVT::f64) {
4610 // Expand into one or more soft-fp libcall(s).
4611 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
4612 switch (cast<CondCodeSDNode>(CC)->get()) {
4615 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4619 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
4623 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4627 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4631 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4635 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4638 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4641 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
4644 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4645 switch (cast<CondCodeSDNode>(CC)->get()) {
4647 // SETONE = SETOLT | SETOGT
4648 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4651 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4654 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4657 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4660 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4663 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4665 default: assert(0 && "Unsupported FP setcc!");
4670 SDOperand Ops[2] = { LHS, RHS };
4671 Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2).Val,
4672 false /*sign irrelevant*/, Dummy);
4673 Tmp2 = DAG.getConstant(0, MVT::i32);
4674 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
4675 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
4676 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
4678 LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2).Val,
4679 false /*sign irrelevant*/, Dummy);
4680 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, Tmp2,
4681 DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
4682 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4685 LHS = LegalizeOp(Tmp1);
4690 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
4691 ExpandOp(LHS, LHSLo, LHSHi);
4692 ExpandOp(RHS, RHSLo, RHSHi);
4693 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
4695 if (VT==MVT::ppcf128) {
4696 // FIXME: This generated code sucks. We want to generate
4697 // FCMP crN, hi1, hi2
4699 // FCMP crN, lo1, lo2
4700 // The following can be improved, but not that much.
4701 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETEQ);
4702 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, CCCode);
4703 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4704 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETNE);
4705 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode);
4706 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4707 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
4716 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
4717 if (RHSCST->isAllOnesValue()) {
4718 // Comparison to -1.
4719 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
4724 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
4725 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
4726 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4727 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
4730 // If this is a comparison of the sign bit, just look at the top part.
4732 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
4733 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
4734 CST->isNullValue()) || // X < 0
4735 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
4736 CST->isAllOnesValue())) { // X > -1
4742 // FIXME: This generated code sucks.
4743 ISD::CondCode LowCC;
4745 default: assert(0 && "Unknown integer setcc!");
4747 case ISD::SETULT: LowCC = ISD::SETULT; break;
4749 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
4751 case ISD::SETULE: LowCC = ISD::SETULE; break;
4753 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
4756 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
4757 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
4758 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
4760 // NOTE: on targets without efficient SELECT of bools, we can always use
4761 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
4762 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
4763 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo,
4764 LowCC, false, DagCombineInfo);
4766 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC);
4767 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4768 CCCode, false, DagCombineInfo);
4770 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi,
4773 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
4774 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
4775 if ((Tmp1C && Tmp1C->isNullValue()) ||
4776 (Tmp2C && Tmp2C->isNullValue() &&
4777 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
4778 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
4779 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
4780 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
4781 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
4782 // low part is known false, returns high part.
4783 // For LE / GE, if high part is known false, ignore the low part.
4784 // For LT / GT, if high part is known true, ignore the low part.
4788 Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4789 ISD::SETEQ, false, DagCombineInfo);
4791 Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4793 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
4794 Result, Tmp1, Tmp2));
4805 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
4806 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
4807 /// a load from the stack slot to DestVT, extending it if needed.
4808 /// The resultant code need not be legal.
4809 SDOperand SelectionDAGLegalize::EmitStackConvert(SDOperand SrcOp,
4812 // Create the stack frame object.
4813 unsigned SrcAlign = TLI.getTargetData()->getPrefTypeAlignment(
4814 SrcOp.getValueType().getTypeForMVT());
4815 SDOperand FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
4817 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
4818 int SPFI = StackPtrFI->getIndex();
4820 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
4821 unsigned SlotSize = SlotVT.getSizeInBits();
4822 unsigned DestSize = DestVT.getSizeInBits();
4823 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(
4824 DestVT.getTypeForMVT());
4826 // Emit a store to the stack slot. Use a truncstore if the input value is
4827 // later than DestVT.
4830 if (SrcSize > SlotSize)
4831 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr,
4832 PseudoSourceValue::getFixedStack(SPFI), 0,
4833 SlotVT, false, SrcAlign);
4835 assert(SrcSize == SlotSize && "Invalid store");
4836 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr,
4837 PseudoSourceValue::getFixedStack(SPFI), 0,
4841 // Result is a load from the stack slot.
4842 if (SlotSize == DestSize)
4843 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0, false, DestAlign);
4845 assert(SlotSize < DestSize && "Unknown extension!");
4846 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT,
4850 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
4851 // Create a vector sized/aligned stack slot, store the value to element #0,
4852 // then load the whole vector back out.
4853 SDOperand StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
4855 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
4856 int SPFI = StackPtrFI->getIndex();
4858 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
4859 PseudoSourceValue::getFixedStack(SPFI), 0);
4860 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,
4861 PseudoSourceValue::getFixedStack(SPFI), 0);
4865 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
4866 /// support the operation, but do support the resultant vector type.
4867 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
4869 // If the only non-undef value is the low element, turn this into a
4870 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
4871 unsigned NumElems = Node->getNumOperands();
4872 bool isOnlyLowElement = true;
4873 SDOperand SplatValue = Node->getOperand(0);
4875 // FIXME: it would be far nicer to change this into map<SDOperand,uint64_t>
4876 // and use a bitmask instead of a list of elements.
4877 std::map<SDOperand, std::vector<unsigned> > Values;
4878 Values[SplatValue].push_back(0);
4879 bool isConstant = true;
4880 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
4881 SplatValue.getOpcode() != ISD::UNDEF)
4884 for (unsigned i = 1; i < NumElems; ++i) {
4885 SDOperand V = Node->getOperand(i);
4886 Values[V].push_back(i);
4887 if (V.getOpcode() != ISD::UNDEF)
4888 isOnlyLowElement = false;
4889 if (SplatValue != V)
4890 SplatValue = SDOperand(0,0);
4892 // If this isn't a constant element or an undef, we can't use a constant
4894 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
4895 V.getOpcode() != ISD::UNDEF)
4899 if (isOnlyLowElement) {
4900 // If the low element is an undef too, then this whole things is an undef.
4901 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
4902 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
4903 // Otherwise, turn this into a scalar_to_vector node.
4904 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4905 Node->getOperand(0));
4908 // If all elements are constants, create a load from the constant pool.
4910 MVT VT = Node->getValueType(0);
4911 std::vector<Constant*> CV;
4912 for (unsigned i = 0, e = NumElems; i != e; ++i) {
4913 if (ConstantFPSDNode *V =
4914 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
4915 CV.push_back(ConstantFP::get(V->getValueAPF()));
4916 } else if (ConstantSDNode *V =
4917 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
4918 CV.push_back(ConstantInt::get(V->getAPIntValue()));
4920 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
4922 Node->getOperand(0).getValueType().getTypeForMVT();
4923 CV.push_back(UndefValue::get(OpNTy));
4926 Constant *CP = ConstantVector::get(CV);
4927 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
4928 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4929 PseudoSourceValue::getConstantPool(), 0);
4932 if (SplatValue.Val) { // Splat of one value?
4933 // Build the shuffle constant vector: <0, 0, 0, 0>
4934 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
4935 SDOperand Zero = DAG.getConstant(0, MaskVT.getVectorElementType());
4936 std::vector<SDOperand> ZeroVec(NumElems, Zero);
4937 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4938 &ZeroVec[0], ZeroVec.size());
4940 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4941 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
4942 // Get the splatted value into the low element of a vector register.
4943 SDOperand LowValVec =
4944 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
4946 // Return shuffle(LowValVec, undef, <0,0,0,0>)
4947 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
4948 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
4953 // If there are only two unique elements, we may be able to turn this into a
4955 if (Values.size() == 2) {
4956 // Get the two values in deterministic order.
4957 SDOperand Val1 = Node->getOperand(1);
4959 std::map<SDOperand, std::vector<unsigned> >::iterator MI = Values.begin();
4960 if (MI->first != Val1)
4963 Val2 = (++MI)->first;
4965 // If Val1 is an undef, make sure end ends up as Val2, to ensure that our
4966 // vector shuffle has the undef vector on the RHS.
4967 if (Val1.getOpcode() == ISD::UNDEF)
4968 std::swap(Val1, Val2);
4970 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
4971 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
4972 MVT MaskEltVT = MaskVT.getVectorElementType();
4973 std::vector<SDOperand> MaskVec(NumElems);
4975 // Set elements of the shuffle mask for Val1.
4976 std::vector<unsigned> &Val1Elts = Values[Val1];
4977 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i)
4978 MaskVec[Val1Elts[i]] = DAG.getConstant(0, MaskEltVT);
4980 // Set elements of the shuffle mask for Val2.
4981 std::vector<unsigned> &Val2Elts = Values[Val2];
4982 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i)
4983 if (Val2.getOpcode() != ISD::UNDEF)
4984 MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT);
4986 MaskVec[Val2Elts[i]] = DAG.getNode(ISD::UNDEF, MaskEltVT);
4988 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4989 &MaskVec[0], MaskVec.size());
4991 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it.
4992 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
4993 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
4994 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val1);
4995 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val2);
4996 SDOperand Ops[] = { Val1, Val2, ShuffleMask };
4998 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
4999 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops, 3);
5003 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
5004 // aligned object on the stack, store each element into it, then load
5005 // the result as a vector.
5006 MVT VT = Node->getValueType(0);
5007 // Create the stack frame object.
5008 SDOperand FIPtr = DAG.CreateStackTemporary(VT);
5010 // Emit a store of each element to the stack slot.
5011 SmallVector<SDOperand, 8> Stores;
5012 unsigned TypeByteSize = Node->getOperand(0).getValueType().getSizeInBits()/8;
5013 // Store (in the right endianness) the elements to memory.
5014 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5015 // Ignore undef elements.
5016 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
5018 unsigned Offset = TypeByteSize*i;
5020 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
5021 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
5023 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
5027 SDOperand StoreChain;
5028 if (!Stores.empty()) // Not all undef elements?
5029 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
5030 &Stores[0], Stores.size());
5032 StoreChain = DAG.getEntryNode();
5034 // Result is a load from the stack slot.
5035 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
5038 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
5039 SDOperand Op, SDOperand Amt,
5040 SDOperand &Lo, SDOperand &Hi) {
5041 // Expand the subcomponents.
5042 SDOperand LHSL, LHSH;
5043 ExpandOp(Op, LHSL, LHSH);
5045 SDOperand Ops[] = { LHSL, LHSH, Amt };
5046 MVT VT = LHSL.getValueType();
5047 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
5048 Hi = Lo.getValue(1);
5052 /// ExpandShift - Try to find a clever way to expand this shift operation out to
5053 /// smaller elements. If we can't find a way that is more efficient than a
5054 /// libcall on this target, return false. Otherwise, return true with the
5055 /// low-parts expanded into Lo and Hi.
5056 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
5057 SDOperand &Lo, SDOperand &Hi) {
5058 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
5059 "This is not a shift!");
5061 MVT NVT = TLI.getTypeToTransformTo(Op.getValueType());
5062 SDOperand ShAmt = LegalizeOp(Amt);
5063 MVT ShTy = ShAmt.getValueType();
5064 unsigned ShBits = ShTy.getSizeInBits();
5065 unsigned VTBits = Op.getValueType().getSizeInBits();
5066 unsigned NVTBits = NVT.getSizeInBits();
5068 // Handle the case when Amt is an immediate.
5069 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
5070 unsigned Cst = CN->getValue();
5071 // Expand the incoming operand to be shifted, so that we have its parts
5073 ExpandOp(Op, InL, InH);
5077 Lo = DAG.getConstant(0, NVT);
5078 Hi = DAG.getConstant(0, NVT);
5079 } else if (Cst > NVTBits) {
5080 Lo = DAG.getConstant(0, NVT);
5081 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
5082 } else if (Cst == NVTBits) {
5083 Lo = DAG.getConstant(0, NVT);
5086 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
5087 Hi = DAG.getNode(ISD::OR, NVT,
5088 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
5089 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
5094 Lo = DAG.getConstant(0, NVT);
5095 Hi = DAG.getConstant(0, NVT);
5096 } else if (Cst > NVTBits) {
5097 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
5098 Hi = DAG.getConstant(0, NVT);
5099 } else if (Cst == NVTBits) {
5101 Hi = DAG.getConstant(0, NVT);
5103 Lo = DAG.getNode(ISD::OR, NVT,
5104 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5105 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5106 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
5111 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
5112 DAG.getConstant(NVTBits-1, ShTy));
5113 } else if (Cst > NVTBits) {
5114 Lo = DAG.getNode(ISD::SRA, NVT, InH,
5115 DAG.getConstant(Cst-NVTBits, ShTy));
5116 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5117 DAG.getConstant(NVTBits-1, ShTy));
5118 } else if (Cst == NVTBits) {
5120 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5121 DAG.getConstant(NVTBits-1, ShTy));
5123 Lo = DAG.getNode(ISD::OR, NVT,
5124 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5125 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5126 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
5132 // Okay, the shift amount isn't constant. However, if we can tell that it is
5133 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
5134 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
5135 APInt KnownZero, KnownOne;
5136 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
5138 // If we know that if any of the high bits of the shift amount are one, then
5139 // we can do this as a couple of simple shifts.
5140 if (KnownOne.intersects(Mask)) {
5141 // Mask out the high bit, which we know is set.
5142 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
5143 DAG.getConstant(~Mask, Amt.getValueType()));
5145 // Expand the incoming operand to be shifted, so that we have its parts
5147 ExpandOp(Op, InL, InH);
5150 Lo = DAG.getConstant(0, NVT); // Low part is zero.
5151 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
5154 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
5155 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
5158 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
5159 DAG.getConstant(NVTBits-1, Amt.getValueType()));
5160 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
5165 // If we know that the high bits of the shift amount are all zero, then we can
5166 // do this as a couple of simple shifts.
5167 if ((KnownZero & Mask) == Mask) {
5169 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
5170 DAG.getConstant(NVTBits, Amt.getValueType()),
5173 // Expand the incoming operand to be shifted, so that we have its parts
5175 ExpandOp(Op, InL, InH);
5178 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
5179 Hi = DAG.getNode(ISD::OR, NVT,
5180 DAG.getNode(ISD::SHL, NVT, InH, Amt),
5181 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
5184 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
5185 Lo = DAG.getNode(ISD::OR, NVT,
5186 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5187 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5190 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
5191 Lo = DAG.getNode(ISD::OR, NVT,
5192 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5193 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5202 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
5203 // does not fit into a register, return the lo part and set the hi part to the
5204 // by-reg argument. If it does fit into a single register, return the result
5205 // and leave the Hi part unset.
5206 SDOperand SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
5207 bool isSigned, SDOperand &Hi) {
5208 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
5209 // The input chain to this libcall is the entry node of the function.
5210 // Legalizing the call will automatically add the previous call to the
5212 SDOperand InChain = DAG.getEntryNode();
5214 TargetLowering::ArgListTy Args;
5215 TargetLowering::ArgListEntry Entry;
5216 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5217 MVT ArgVT = Node->getOperand(i).getValueType();
5218 const Type *ArgTy = ArgVT.getTypeForMVT();
5219 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
5220 Entry.isSExt = isSigned;
5221 Entry.isZExt = !isSigned;
5222 Args.push_back(Entry);
5224 SDOperand Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
5225 TLI.getPointerTy());
5227 // Splice the libcall in wherever FindInputOutputChains tells us to.
5228 const Type *RetTy = Node->getValueType(0).getTypeForMVT();
5229 std::pair<SDOperand,SDOperand> CallInfo =
5230 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, CallingConv::C,
5231 false, Callee, Args, DAG);
5233 // Legalize the call sequence, starting with the chain. This will advance
5234 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
5235 // was added by LowerCallTo (guaranteeing proper serialization of calls).
5236 LegalizeOp(CallInfo.second);
5238 switch (getTypeAction(CallInfo.first.getValueType())) {
5239 default: assert(0 && "Unknown thing");
5241 Result = CallInfo.first;
5244 ExpandOp(CallInfo.first, Result, Hi);
5251 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
5253 SDOperand SelectionDAGLegalize::
5254 ExpandIntToFP(bool isSigned, MVT DestTy, SDOperand Source) {
5255 MVT SourceVT = Source.getValueType();
5256 bool ExpandSource = getTypeAction(SourceVT) == Expand;
5258 // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc.
5259 if (!isSigned && SourceVT != MVT::i32) {
5260 // The integer value loaded will be incorrectly if the 'sign bit' of the
5261 // incoming integer is set. To handle this, we dynamically test to see if
5262 // it is set, and, if so, add a fudge factor.
5266 ExpandOp(Source, Lo, Hi);
5267 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi);
5269 // The comparison for the sign bit will use the entire operand.
5273 // If this is unsigned, and not supported, first perform the conversion to
5274 // signed, then adjust the result if the sign bit is set.
5275 SDOperand SignedConv = ExpandIntToFP(true, DestTy, Source);
5277 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
5278 DAG.getConstant(0, Hi.getValueType()),
5280 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5281 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5282 SignSet, Four, Zero);
5283 uint64_t FF = 0x5f800000ULL;
5284 if (TLI.isLittleEndian()) FF <<= 32;
5285 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5287 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5288 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5289 SDOperand FudgeInReg;
5290 if (DestTy == MVT::f32)
5291 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5292 PseudoSourceValue::getConstantPool(), 0);
5293 else if (DestTy.bitsGT(MVT::f32))
5294 // FIXME: Avoid the extend by construction the right constantpool?
5295 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
5297 PseudoSourceValue::getConstantPool(), 0,
5300 assert(0 && "Unexpected conversion");
5302 MVT SCVT = SignedConv.getValueType();
5303 if (SCVT != DestTy) {
5304 // Destination type needs to be expanded as well. The FADD now we are
5305 // constructing will be expanded into a libcall.
5306 if (SCVT.getSizeInBits() != DestTy.getSizeInBits()) {
5307 assert(SCVT.getSizeInBits() * 2 == DestTy.getSizeInBits());
5308 SignedConv = DAG.getNode(ISD::BUILD_PAIR, DestTy,
5309 SignedConv, SignedConv.getValue(1));
5311 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
5313 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
5316 // Check to see if the target has a custom way to lower this. If so, use it.
5317 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) {
5318 default: assert(0 && "This action not implemented for this operation!");
5319 case TargetLowering::Legal:
5320 case TargetLowering::Expand:
5321 break; // This case is handled below.
5322 case TargetLowering::Custom: {
5323 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
5326 return LegalizeOp(NV);
5327 break; // The target decided this was legal after all
5331 // Expand the source, then glue it back together for the call. We must expand
5332 // the source in case it is shared (this pass of legalize must traverse it).
5334 SDOperand SrcLo, SrcHi;
5335 ExpandOp(Source, SrcLo, SrcHi);
5336 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, SrcLo, SrcHi);
5339 RTLIB::Libcall LC = isSigned ?
5340 RTLIB::getSINTTOFP(SourceVT, DestTy) :
5341 RTLIB::getUINTTOFP(SourceVT, DestTy);
5342 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unknown int value type");
5344 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
5346 SDOperand Result = ExpandLibCall(LC, Source.Val, isSigned, HiPart);
5347 if (Result.getValueType() != DestTy && HiPart.Val)
5348 Result = DAG.getNode(ISD::BUILD_PAIR, DestTy, Result, HiPart);
5352 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
5353 /// INT_TO_FP operation of the specified operand when the target requests that
5354 /// we expand it. At this point, we know that the result and operand types are
5355 /// legal for the target.
5356 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
5359 if (Op0.getValueType() == MVT::i32) {
5360 // simple 32-bit [signed|unsigned] integer to float/double expansion
5362 // Get the stack frame index of a 8 byte buffer.
5363 SDOperand StackSlot = DAG.CreateStackTemporary(MVT::f64);
5365 // word offset constant for Hi/Lo address computation
5366 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
5367 // set up Hi and Lo (into buffer) address based on endian
5368 SDOperand Hi = StackSlot;
5369 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
5370 if (TLI.isLittleEndian())
5373 // if signed map to unsigned space
5374 SDOperand Op0Mapped;
5376 // constant used to invert sign bit (signed to unsigned mapping)
5377 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
5378 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
5382 // store the lo of the constructed double - based on integer input
5383 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(),
5384 Op0Mapped, Lo, NULL, 0);
5385 // initial hi portion of constructed double
5386 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
5387 // store the hi of the constructed double - biased exponent
5388 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
5389 // load the constructed double
5390 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
5391 // FP constant to bias correct the final result
5392 SDOperand Bias = DAG.getConstantFP(isSigned ?
5393 BitsToDouble(0x4330000080000000ULL)
5394 : BitsToDouble(0x4330000000000000ULL),
5396 // subtract the bias
5397 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
5400 // handle final rounding
5401 if (DestVT == MVT::f64) {
5404 } else if (DestVT.bitsLT(MVT::f64)) {
5405 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub,
5406 DAG.getIntPtrConstant(0));
5407 } else if (DestVT.bitsGT(MVT::f64)) {
5408 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
5412 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
5413 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
5415 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Op0), Op0,
5416 DAG.getConstant(0, Op0.getValueType()),
5418 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5419 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5420 SignSet, Four, Zero);
5422 // If the sign bit of the integer is set, the large number will be treated
5423 // as a negative number. To counteract this, the dynamic code adds an
5424 // offset depending on the data type.
5426 switch (Op0.getValueType().getSimpleVT()) {
5427 default: assert(0 && "Unsupported integer type!");
5428 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
5429 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
5430 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
5431 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
5433 if (TLI.isLittleEndian()) FF <<= 32;
5434 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5436 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5437 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5438 SDOperand FudgeInReg;
5439 if (DestVT == MVT::f32)
5440 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5441 PseudoSourceValue::getConstantPool(), 0);
5444 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT,
5445 DAG.getEntryNode(), CPIdx,
5446 PseudoSourceValue::getConstantPool(), 0,
5450 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
5453 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
5454 /// *INT_TO_FP operation of the specified operand when the target requests that
5455 /// we promote it. At this point, we know that the result and operand types are
5456 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
5457 /// operation that takes a larger input.
5458 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
5461 // First step, figure out the appropriate *INT_TO_FP operation to use.
5462 MVT NewInTy = LegalOp.getValueType();
5464 unsigned OpToUse = 0;
5466 // Scan for the appropriate larger type to use.
5468 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
5469 assert(NewInTy.isInteger() && "Ran out of possibilities!");
5471 // If the target supports SINT_TO_FP of this type, use it.
5472 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
5474 case TargetLowering::Legal:
5475 if (!TLI.isTypeLegal(NewInTy))
5476 break; // Can't use this datatype.
5478 case TargetLowering::Custom:
5479 OpToUse = ISD::SINT_TO_FP;
5483 if (isSigned) continue;
5485 // If the target supports UINT_TO_FP of this type, use it.
5486 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
5488 case TargetLowering::Legal:
5489 if (!TLI.isTypeLegal(NewInTy))
5490 break; // Can't use this datatype.
5492 case TargetLowering::Custom:
5493 OpToUse = ISD::UINT_TO_FP;
5498 // Otherwise, try a larger type.
5501 // Okay, we found the operation and type to use. Zero extend our input to the
5502 // desired type then run the operation on it.
5503 return DAG.getNode(OpToUse, DestVT,
5504 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
5508 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
5509 /// FP_TO_*INT operation of the specified operand when the target requests that
5510 /// we promote it. At this point, we know that the result and operand types are
5511 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
5512 /// operation that returns a larger result.
5513 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
5516 // First step, figure out the appropriate FP_TO*INT operation to use.
5517 MVT NewOutTy = DestVT;
5519 unsigned OpToUse = 0;
5521 // Scan for the appropriate larger type to use.
5523 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1);
5524 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
5526 // If the target supports FP_TO_SINT returning this type, use it.
5527 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
5529 case TargetLowering::Legal:
5530 if (!TLI.isTypeLegal(NewOutTy))
5531 break; // Can't use this datatype.
5533 case TargetLowering::Custom:
5534 OpToUse = ISD::FP_TO_SINT;
5539 // If the target supports FP_TO_UINT of this type, use it.
5540 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
5542 case TargetLowering::Legal:
5543 if (!TLI.isTypeLegal(NewOutTy))
5544 break; // Can't use this datatype.
5546 case TargetLowering::Custom:
5547 OpToUse = ISD::FP_TO_UINT;
5552 // Otherwise, try a larger type.
5556 // Okay, we found the operation and type to use.
5557 SDOperand Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp);
5559 // If the operation produces an invalid type, it must be custom lowered. Use
5560 // the target lowering hooks to expand it. Just keep the low part of the
5561 // expanded operation, we know that we're truncating anyway.
5562 if (getTypeAction(NewOutTy) == Expand) {
5563 Operation = SDOperand(TLI.ReplaceNodeResults(Operation.Val, DAG), 0);
5564 assert(Operation.Val && "Didn't return anything");
5567 // Truncate the result of the extended FP_TO_*INT operation to the desired
5569 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation);
5572 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
5574 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
5575 MVT VT = Op.getValueType();
5576 MVT SHVT = TLI.getShiftAmountTy();
5577 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
5578 switch (VT.getSimpleVT()) {
5579 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
5581 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5582 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5583 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
5585 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5586 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5587 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5588 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5589 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
5590 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
5591 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5592 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5593 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5595 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
5596 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
5597 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5598 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5599 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5600 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5601 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
5602 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
5603 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
5604 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
5605 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
5606 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
5607 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
5608 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
5609 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
5610 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
5611 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5612 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5613 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
5614 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5615 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
5619 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
5621 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
5623 default: assert(0 && "Cannot expand this yet!");
5625 static const uint64_t mask[6] = {
5626 0x5555555555555555ULL, 0x3333333333333333ULL,
5627 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
5628 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
5630 MVT VT = Op.getValueType();
5631 MVT ShVT = TLI.getShiftAmountTy();
5632 unsigned len = VT.getSizeInBits();
5633 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5634 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
5635 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
5636 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5637 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
5638 DAG.getNode(ISD::AND, VT,
5639 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
5644 // for now, we do this:
5645 // x = x | (x >> 1);
5646 // x = x | (x >> 2);
5648 // x = x | (x >>16);
5649 // x = x | (x >>32); // for 64-bit input
5650 // return popcount(~x);
5652 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
5653 MVT VT = Op.getValueType();
5654 MVT ShVT = TLI.getShiftAmountTy();
5655 unsigned len = VT.getSizeInBits();
5656 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5657 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5658 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
5660 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
5661 return DAG.getNode(ISD::CTPOP, VT, Op);
5664 // for now, we use: { return popcount(~x & (x - 1)); }
5665 // unless the target has ctlz but not ctpop, in which case we use:
5666 // { return 32 - nlz(~x & (x-1)); }
5667 // see also http://www.hackersdelight.org/HDcode/ntz.cc
5668 MVT VT = Op.getValueType();
5669 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
5670 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
5671 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
5672 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
5673 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
5674 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
5675 TLI.isOperationLegal(ISD::CTLZ, VT))
5676 return DAG.getNode(ISD::SUB, VT,
5677 DAG.getConstant(VT.getSizeInBits(), VT),
5678 DAG.getNode(ISD::CTLZ, VT, Tmp3));
5679 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
5684 /// ExpandOp - Expand the specified SDOperand into its two component pieces
5685 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
5686 /// LegalizeNodes map is filled in for any results that are not expanded, the
5687 /// ExpandedNodes map is filled in for any results that are expanded, and the
5688 /// Lo/Hi values are returned.
5689 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
5690 MVT VT = Op.getValueType();
5691 MVT NVT = TLI.getTypeToTransformTo(VT);
5692 SDNode *Node = Op.Val;
5693 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
5694 assert(((NVT.isInteger() && NVT.bitsLT(VT)) || VT.isFloatingPoint() ||
5695 VT.isVector()) && "Cannot expand to FP value or to larger int value!");
5697 // See if we already expanded it.
5698 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
5699 = ExpandedNodes.find(Op);
5700 if (I != ExpandedNodes.end()) {
5701 Lo = I->second.first;
5702 Hi = I->second.second;
5706 switch (Node->getOpcode()) {
5707 case ISD::CopyFromReg:
5708 assert(0 && "CopyFromReg must be legal!");
5709 case ISD::FP_ROUND_INREG:
5710 if (VT == MVT::ppcf128 &&
5711 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
5712 TargetLowering::Custom) {
5713 SDOperand SrcLo, SrcHi, Src;
5714 ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
5715 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi);
5716 SDOperand Result = TLI.LowerOperation(
5717 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG);
5718 assert(Result.Val->getOpcode() == ISD::BUILD_PAIR);
5719 Lo = Result.Val->getOperand(0);
5720 Hi = Result.Val->getOperand(1);
5726 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
5728 assert(0 && "Do not know how to expand this operator!");
5730 case ISD::EXTRACT_ELEMENT:
5731 ExpandOp(Node->getOperand(0), Lo, Hi);
5732 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
5733 return ExpandOp(Hi, Lo, Hi);
5734 return ExpandOp(Lo, Lo, Hi);
5735 case ISD::EXTRACT_VECTOR_ELT:
5736 assert(VT==MVT::i64 && "Do not know how to expand this operator!");
5737 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types.
5738 Lo = ExpandEXTRACT_VECTOR_ELT(Op);
5739 return ExpandOp(Lo, Lo, Hi);
5741 Lo = DAG.getNode(ISD::UNDEF, NVT);
5742 Hi = DAG.getNode(ISD::UNDEF, NVT);
5744 case ISD::Constant: {
5745 unsigned NVTBits = NVT.getSizeInBits();
5746 const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue();
5747 Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT);
5748 Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT);
5751 case ISD::ConstantFP: {
5752 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
5753 if (CFP->getValueType(0) == MVT::ppcf128) {
5754 APInt api = CFP->getValueAPF().convertToAPInt();
5755 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
5757 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
5761 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
5762 if (getTypeAction(Lo.getValueType()) == Expand)
5763 ExpandOp(Lo, Lo, Hi);
5766 case ISD::BUILD_PAIR:
5767 // Return the operands.
5768 Lo = Node->getOperand(0);
5769 Hi = Node->getOperand(1);
5772 case ISD::MERGE_VALUES:
5773 if (Node->getNumValues() == 1) {
5774 ExpandOp(Op.getOperand(0), Lo, Hi);
5777 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y)
5778 assert(Op.ResNo == 0 && Node->getNumValues() == 2 &&
5779 Op.getValue(1).getValueType() == MVT::Other &&
5780 "unhandled MERGE_VALUES");
5781 ExpandOp(Op.getOperand(0), Lo, Hi);
5782 // Remember that we legalized the chain.
5783 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1)));
5786 case ISD::SIGN_EXTEND_INREG:
5787 ExpandOp(Node->getOperand(0), Lo, Hi);
5788 // sext_inreg the low part if needed.
5789 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
5791 // The high part gets the sign extension from the lo-part. This handles
5792 // things like sextinreg V:i64 from i8.
5793 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5794 DAG.getConstant(NVT.getSizeInBits()-1,
5795 TLI.getShiftAmountTy()));
5799 ExpandOp(Node->getOperand(0), Lo, Hi);
5800 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
5801 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
5807 ExpandOp(Node->getOperand(0), Lo, Hi);
5808 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
5809 DAG.getNode(ISD::CTPOP, NVT, Lo),
5810 DAG.getNode(ISD::CTPOP, NVT, Hi));
5811 Hi = DAG.getConstant(0, NVT);
5815 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
5816 ExpandOp(Node->getOperand(0), Lo, Hi);
5817 SDOperand BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
5818 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
5819 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(HLZ), HLZ, BitsC,
5821 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
5822 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
5824 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
5825 Hi = DAG.getConstant(0, NVT);
5830 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
5831 ExpandOp(Node->getOperand(0), Lo, Hi);
5832 SDOperand BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
5833 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
5834 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(LTZ), LTZ, BitsC,
5836 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
5837 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
5839 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
5840 Hi = DAG.getConstant(0, NVT);
5845 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
5846 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
5847 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
5848 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
5850 // Remember that we legalized the chain.
5851 Hi = LegalizeOp(Hi);
5852 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
5853 if (TLI.isBigEndian())
5859 LoadSDNode *LD = cast<LoadSDNode>(Node);
5860 SDOperand Ch = LD->getChain(); // Legalize the chain.
5861 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer.
5862 ISD::LoadExtType ExtType = LD->getExtensionType();
5863 int SVOffset = LD->getSrcValueOffset();
5864 unsigned Alignment = LD->getAlignment();
5865 bool isVolatile = LD->isVolatile();
5867 if (ExtType == ISD::NON_EXTLOAD) {
5868 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5869 isVolatile, Alignment);
5870 if (VT == MVT::f32 || VT == MVT::f64) {
5871 // f32->i32 or f64->i64 one to one expansion.
5872 // Remember that we legalized the chain.
5873 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5874 // Recursively expand the new load.
5875 if (getTypeAction(NVT) == Expand)
5876 ExpandOp(Lo, Lo, Hi);
5880 // Increment the pointer to the other half.
5881 unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8;
5882 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
5883 DAG.getIntPtrConstant(IncrementSize));
5884 SVOffset += IncrementSize;
5885 Alignment = MinAlign(Alignment, IncrementSize);
5886 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5887 isVolatile, Alignment);
5889 // Build a factor node to remember that this load is independent of the
5891 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
5894 // Remember that we legalized the chain.
5895 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
5896 if (TLI.isBigEndian())
5899 MVT EVT = LD->getMemoryVT();
5901 if ((VT == MVT::f64 && EVT == MVT::f32) ||
5902 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
5903 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
5904 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(),
5905 SVOffset, isVolatile, Alignment);
5906 // Remember that we legalized the chain.
5907 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1)));
5908 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
5913 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),
5914 SVOffset, isVolatile, Alignment);
5916 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(),
5917 SVOffset, EVT, isVolatile,
5920 // Remember that we legalized the chain.
5921 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5923 if (ExtType == ISD::SEXTLOAD) {
5924 // The high part is obtained by SRA'ing all but one of the bits of the
5926 unsigned LoSize = Lo.getValueType().getSizeInBits();
5927 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5928 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5929 } else if (ExtType == ISD::ZEXTLOAD) {
5930 // The high part is just a zero.
5931 Hi = DAG.getConstant(0, NVT);
5932 } else /* if (ExtType == ISD::EXTLOAD) */ {
5933 // The high part is undefined.
5934 Hi = DAG.getNode(ISD::UNDEF, NVT);
5941 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
5942 SDOperand LL, LH, RL, RH;
5943 ExpandOp(Node->getOperand(0), LL, LH);
5944 ExpandOp(Node->getOperand(1), RL, RH);
5945 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
5946 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
5950 SDOperand LL, LH, RL, RH;
5951 ExpandOp(Node->getOperand(1), LL, LH);
5952 ExpandOp(Node->getOperand(2), RL, RH);
5953 if (getTypeAction(NVT) == Expand)
5954 NVT = TLI.getTypeToExpandTo(NVT);
5955 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
5957 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
5960 case ISD::SELECT_CC: {
5961 SDOperand TL, TH, FL, FH;
5962 ExpandOp(Node->getOperand(2), TL, TH);
5963 ExpandOp(Node->getOperand(3), FL, FH);
5964 if (getTypeAction(NVT) == Expand)
5965 NVT = TLI.getTypeToExpandTo(NVT);
5966 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
5967 Node->getOperand(1), TL, FL, Node->getOperand(4));
5969 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
5970 Node->getOperand(1), TH, FH, Node->getOperand(4));
5973 case ISD::ANY_EXTEND:
5974 // The low part is any extension of the input (which degenerates to a copy).
5975 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
5976 // The high part is undefined.
5977 Hi = DAG.getNode(ISD::UNDEF, NVT);
5979 case ISD::SIGN_EXTEND: {
5980 // The low part is just a sign extension of the input (which degenerates to
5982 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
5984 // The high part is obtained by SRA'ing all but one of the bits of the lo
5986 unsigned LoSize = Lo.getValueType().getSizeInBits();
5987 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5988 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5991 case ISD::ZERO_EXTEND:
5992 // The low part is just a zero extension of the input (which degenerates to
5994 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
5996 // The high part is just a zero.
5997 Hi = DAG.getConstant(0, NVT);
6000 case ISD::TRUNCATE: {
6001 // The input value must be larger than this value. Expand *it*.
6003 ExpandOp(Node->getOperand(0), NewLo, Hi);
6005 // The low part is now either the right size, or it is closer. If not the
6006 // right size, make an illegal truncate so we recursively expand it.
6007 if (NewLo.getValueType() != Node->getValueType(0))
6008 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
6009 ExpandOp(NewLo, Lo, Hi);
6013 case ISD::BIT_CONVERT: {
6015 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
6016 // If the target wants to, allow it to lower this itself.
6017 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6018 case Expand: assert(0 && "cannot expand FP!");
6019 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
6020 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
6022 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
6025 // f32 / f64 must be expanded to i32 / i64.
6026 if (VT == MVT::f32 || VT == MVT::f64) {
6027 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6028 if (getTypeAction(NVT) == Expand)
6029 ExpandOp(Lo, Lo, Hi);
6033 // If source operand will be expanded to the same type as VT, i.e.
6034 // i64 <- f64, i32 <- f32, expand the source operand instead.
6035 MVT VT0 = Node->getOperand(0).getValueType();
6036 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
6037 ExpandOp(Node->getOperand(0), Lo, Hi);
6041 // Turn this into a load/store pair by default.
6043 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT);
6045 ExpandOp(Tmp, Lo, Hi);
6049 case ISD::READCYCLECOUNTER: {
6050 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
6051 TargetLowering::Custom &&
6052 "Must custom expand ReadCycleCounter");
6053 SDOperand Tmp = TLI.LowerOperation(Op, DAG);
6054 assert(Tmp.Val && "Node must be custom expanded!");
6055 ExpandOp(Tmp.getValue(0), Lo, Hi);
6056 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
6057 LegalizeOp(Tmp.getValue(1)));
6061 case ISD::ATOMIC_CMP_SWAP: {
6062 SDOperand Tmp = TLI.LowerOperation(Op, DAG);
6063 assert(Tmp.Val && "Node must be custom expanded!");
6064 ExpandOp(Tmp.getValue(0), Lo, Hi);
6065 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
6066 LegalizeOp(Tmp.getValue(1)));
6072 // These operators cannot be expanded directly, emit them as calls to
6073 // library functions.
6074 case ISD::FP_TO_SINT: {
6075 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
6077 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6078 case Expand: assert(0 && "cannot expand FP!");
6079 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6080 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6083 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
6085 // Now that the custom expander is done, expand the result, which is still
6088 ExpandOp(Op, Lo, Hi);
6093 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Node->getOperand(0).getValueType(),
6095 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected uint-to-fp conversion!");
6096 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6100 case ISD::FP_TO_UINT: {
6101 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
6103 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6104 case Expand: assert(0 && "cannot expand FP!");
6105 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6106 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6109 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
6111 // Now that the custom expander is done, expand the result.
6113 ExpandOp(Op, Lo, Hi);
6118 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Node->getOperand(0).getValueType(),
6120 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
6121 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6126 // If the target wants custom lowering, do so.
6127 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6128 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
6129 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
6130 Op = TLI.LowerOperation(Op, DAG);
6132 // Now that the custom expander is done, expand the result, which is
6134 ExpandOp(Op, Lo, Hi);
6139 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
6140 // this X << 1 as X+X.
6141 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
6142 if (ShAmt->getAPIntValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
6143 TLI.isOperationLegal(ISD::ADDE, NVT)) {
6144 SDOperand LoOps[2], HiOps[3];
6145 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
6146 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
6147 LoOps[1] = LoOps[0];
6148 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6150 HiOps[1] = HiOps[0];
6151 HiOps[2] = Lo.getValue(1);
6152 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6157 // If we can emit an efficient shift operation, do so now.
6158 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6161 // If this target supports SHL_PARTS, use it.
6162 TargetLowering::LegalizeAction Action =
6163 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
6164 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6165 Action == TargetLowering::Custom) {
6166 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6170 // Otherwise, emit a libcall.
6171 Lo = ExpandLibCall(RTLIB::SHL_I64, Node, false/*left shift=unsigned*/, Hi);
6176 // If the target wants custom lowering, do so.
6177 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6178 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
6179 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
6180 Op = TLI.LowerOperation(Op, DAG);
6182 // Now that the custom expander is done, expand the result, which is
6184 ExpandOp(Op, Lo, Hi);
6189 // If we can emit an efficient shift operation, do so now.
6190 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
6193 // If this target supports SRA_PARTS, use it.
6194 TargetLowering::LegalizeAction Action =
6195 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
6196 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6197 Action == TargetLowering::Custom) {
6198 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6202 // Otherwise, emit a libcall.
6203 Lo = ExpandLibCall(RTLIB::SRA_I64, Node, true/*ashr is signed*/, Hi);
6208 // If the target wants custom lowering, do so.
6209 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6210 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
6211 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
6212 Op = TLI.LowerOperation(Op, DAG);
6214 // Now that the custom expander is done, expand the result, which is
6216 ExpandOp(Op, Lo, Hi);
6221 // If we can emit an efficient shift operation, do so now.
6222 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6225 // If this target supports SRL_PARTS, use it.
6226 TargetLowering::LegalizeAction Action =
6227 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
6228 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6229 Action == TargetLowering::Custom) {
6230 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6234 // Otherwise, emit a libcall.
6235 Lo = ExpandLibCall(RTLIB::SRL_I64, Node, false/*lshr is unsigned*/, Hi);
6241 // If the target wants to custom expand this, let them.
6242 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
6243 TargetLowering::Custom) {
6244 SDOperand Result = TLI.LowerOperation(Op, DAG);
6246 ExpandOp(Result, Lo, Hi);
6251 // Expand the subcomponents.
6252 SDOperand LHSL, LHSH, RHSL, RHSH;
6253 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6254 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6255 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6256 SDOperand LoOps[2], HiOps[3];
6261 if (Node->getOpcode() == ISD::ADD) {
6262 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6263 HiOps[2] = Lo.getValue(1);
6264 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6266 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6267 HiOps[2] = Lo.getValue(1);
6268 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6275 // Expand the subcomponents.
6276 SDOperand LHSL, LHSH, RHSL, RHSH;
6277 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6278 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6279 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6280 SDOperand LoOps[2] = { LHSL, RHSL };
6281 SDOperand HiOps[3] = { LHSH, RHSH };
6283 if (Node->getOpcode() == ISD::ADDC) {
6284 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6285 HiOps[2] = Lo.getValue(1);
6286 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6288 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6289 HiOps[2] = Lo.getValue(1);
6290 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6292 // Remember that we legalized the flag.
6293 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6298 // Expand the subcomponents.
6299 SDOperand LHSL, LHSH, RHSL, RHSH;
6300 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6301 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6302 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6303 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
6304 SDOperand HiOps[3] = { LHSH, RHSH };
6306 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
6307 HiOps[2] = Lo.getValue(1);
6308 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
6310 // Remember that we legalized the flag.
6311 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6315 // If the target wants to custom expand this, let them.
6316 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
6317 SDOperand New = TLI.LowerOperation(Op, DAG);
6319 ExpandOp(New, Lo, Hi);
6324 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
6325 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
6326 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
6327 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
6328 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
6329 SDOperand LL, LH, RL, RH;
6330 ExpandOp(Node->getOperand(0), LL, LH);
6331 ExpandOp(Node->getOperand(1), RL, RH);
6332 unsigned OuterBitSize = Op.getValueSizeInBits();
6333 unsigned InnerBitSize = RH.getValueSizeInBits();
6334 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
6335 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
6336 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
6337 if (DAG.MaskedValueIsZero(Node->getOperand(0), HighMask) &&
6338 DAG.MaskedValueIsZero(Node->getOperand(1), HighMask)) {
6339 // The inputs are both zero-extended.
6341 // We can emit a umul_lohi.
6342 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6343 Hi = SDOperand(Lo.Val, 1);
6347 // We can emit a mulhu+mul.
6348 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6349 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6353 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
6354 // The input values are both sign-extended.
6356 // We can emit a smul_lohi.
6357 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6358 Hi = SDOperand(Lo.Val, 1);
6362 // We can emit a mulhs+mul.
6363 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6364 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
6369 // Lo,Hi = umul LHS, RHS.
6370 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
6371 DAG.getVTList(NVT, NVT), LL, RL);
6373 Hi = UMulLOHI.getValue(1);
6374 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6375 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6376 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6377 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6381 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6382 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6383 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6384 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6385 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6386 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6391 // If nothing else, we can make a libcall.
6392 Lo = ExpandLibCall(RTLIB::MUL_I64, Node, false/*sign irrelevant*/, Hi);
6396 Lo = ExpandLibCall(RTLIB::SDIV_I64, Node, true, Hi);
6399 Lo = ExpandLibCall(RTLIB::UDIV_I64, Node, true, Hi);
6402 Lo = ExpandLibCall(RTLIB::SREM_I64, Node, true, Hi);
6405 Lo = ExpandLibCall(RTLIB::UREM_I64, Node, true, Hi);
6409 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::ADD_F32,
6412 RTLIB::ADD_PPCF128),
6416 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::SUB_F32,
6419 RTLIB::SUB_PPCF128),
6423 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::MUL_F32,
6426 RTLIB::MUL_PPCF128),
6430 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::DIV_F32,
6433 RTLIB::DIV_PPCF128),
6436 case ISD::FP_EXTEND: {
6437 if (VT == MVT::ppcf128) {
6438 assert(Node->getOperand(0).getValueType()==MVT::f32 ||
6439 Node->getOperand(0).getValueType()==MVT::f64);
6440 const uint64_t zero = 0;
6441 if (Node->getOperand(0).getValueType()==MVT::f32)
6442 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0));
6444 Hi = Node->getOperand(0);
6445 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6448 RTLIB::Libcall LC = RTLIB::getFPEXT(Node->getOperand(0).getValueType(), VT);
6449 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!");
6450 Lo = ExpandLibCall(LC, Node, true, Hi);
6453 case ISD::FP_ROUND: {
6454 RTLIB::Libcall LC = RTLIB::getFPROUND(Node->getOperand(0).getValueType(),
6456 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!");
6457 Lo = ExpandLibCall(LC, Node, true, Hi);
6461 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::POWI_F32,
6464 RTLIB::POWI_PPCF128),
6470 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6471 switch(Node->getOpcode()) {
6473 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
6474 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
6477 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
6478 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
6481 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
6482 RTLIB::COS_F80, RTLIB::COS_PPCF128);
6484 default: assert(0 && "Unreachable!");
6486 Lo = ExpandLibCall(LC, Node, false, Hi);
6490 if (VT == MVT::ppcf128) {
6492 ExpandOp(Node->getOperand(0), Lo, Tmp);
6493 Hi = DAG.getNode(ISD::FABS, NVT, Tmp);
6494 // lo = hi==fabs(hi) ? lo : -lo;
6495 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp,
6496 Lo, DAG.getNode(ISD::FNEG, NVT, Lo),
6497 DAG.getCondCode(ISD::SETEQ));
6500 SDOperand Mask = (VT == MVT::f64)
6501 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
6502 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
6503 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6504 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6505 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
6506 if (getTypeAction(NVT) == Expand)
6507 ExpandOp(Lo, Lo, Hi);
6511 if (VT == MVT::ppcf128) {
6512 ExpandOp(Node->getOperand(0), Lo, Hi);
6513 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo);
6514 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi);
6517 SDOperand Mask = (VT == MVT::f64)
6518 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
6519 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
6520 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6521 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6522 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
6523 if (getTypeAction(NVT) == Expand)
6524 ExpandOp(Lo, Lo, Hi);
6527 case ISD::FCOPYSIGN: {
6528 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
6529 if (getTypeAction(NVT) == Expand)
6530 ExpandOp(Lo, Lo, Hi);
6533 case ISD::SINT_TO_FP:
6534 case ISD::UINT_TO_FP: {
6535 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
6536 MVT SrcVT = Node->getOperand(0).getValueType();
6538 // Promote the operand if needed. Do this before checking for
6539 // ppcf128 so conversions of i16 and i8 work.
6540 if (getTypeAction(SrcVT) == Promote) {
6541 SDOperand Tmp = PromoteOp(Node->getOperand(0));
6543 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
6544 DAG.getValueType(SrcVT))
6545 : DAG.getZeroExtendInReg(Tmp, SrcVT);
6546 Node = DAG.UpdateNodeOperands(Op, Tmp).Val;
6547 SrcVT = Node->getOperand(0).getValueType();
6550 if (VT == MVT::ppcf128 && SrcVT == MVT::i32) {
6551 static const uint64_t zero = 0;
6553 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6554 Node->getOperand(0)));
6555 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6557 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
6558 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6559 Node->getOperand(0)));
6560 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6561 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6562 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
6563 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6564 DAG.getConstant(0, MVT::i32),
6565 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6567 APFloat(APInt(128, 2, TwoE32)),
6570 DAG.getCondCode(ISD::SETLT)),
6575 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) {
6576 // si64->ppcf128 done by libcall, below
6577 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
6578 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)),
6580 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6581 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
6582 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6583 DAG.getConstant(0, MVT::i64),
6584 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6586 APFloat(APInt(128, 2, TwoE64)),
6589 DAG.getCondCode(ISD::SETLT)),
6594 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
6595 Node->getOperand(0));
6596 if (getTypeAction(Lo.getValueType()) == Expand)
6597 // float to i32 etc. can be 'expanded' to a single node.
6598 ExpandOp(Lo, Lo, Hi);
6603 // Make sure the resultant values have been legalized themselves, unless this
6604 // is a type that requires multi-step expansion.
6605 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
6606 Lo = LegalizeOp(Lo);
6608 // Don't legalize the high part if it is expanded to a single node.
6609 Hi = LegalizeOp(Hi);
6612 // Remember in a map if the values will be reused later.
6614 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
6615 assert(isNew && "Value already expanded?!?");
6618 /// SplitVectorOp - Given an operand of vector type, break it down into
6619 /// two smaller values, still of vector type.
6620 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
6622 assert(Op.getValueType().isVector() && "Cannot split non-vector type!");
6623 SDNode *Node = Op.Val;
6624 unsigned NumElements = Op.getValueType().getVectorNumElements();
6625 assert(NumElements > 1 && "Cannot split a single element vector!");
6627 MVT NewEltVT = Op.getValueType().getVectorElementType();
6629 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
6630 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
6632 MVT NewVT_Lo = MVT::getVectorVT(NewEltVT, NewNumElts_Lo);
6633 MVT NewVT_Hi = MVT::getVectorVT(NewEltVT, NewNumElts_Hi);
6635 // See if we already split it.
6636 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
6637 = SplitNodes.find(Op);
6638 if (I != SplitNodes.end()) {
6639 Lo = I->second.first;
6640 Hi = I->second.second;
6644 switch (Node->getOpcode()) {
6649 assert(0 && "Unhandled operation in SplitVectorOp!");
6651 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo);
6652 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi);
6654 case ISD::BUILD_PAIR:
6655 Lo = Node->getOperand(0);
6656 Hi = Node->getOperand(1);
6658 case ISD::INSERT_VECTOR_ELT: {
6659 if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) {
6660 SplitVectorOp(Node->getOperand(0), Lo, Hi);
6661 unsigned Index = Idx->getValue();
6662 SDOperand ScalarOp = Node->getOperand(1);
6663 if (Index < NewNumElts_Lo)
6664 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp,
6665 DAG.getIntPtrConstant(Index));
6667 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp,
6668 DAG.getIntPtrConstant(Index - NewNumElts_Lo));
6671 SDOperand Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0),
6672 Node->getOperand(1),
6673 Node->getOperand(2));
6674 SplitVectorOp(Tmp, Lo, Hi);
6677 case ISD::VECTOR_SHUFFLE: {
6678 // Build the low part.
6679 SDOperand Mask = Node->getOperand(2);
6680 SmallVector<SDOperand, 8> Ops;
6681 MVT PtrVT = TLI.getPointerTy();
6683 // Insert all of the elements from the input that are needed. We use
6684 // buildvector of extractelement here because the input vectors will have
6685 // to be legalized, so this makes the code simpler.
6686 for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
6687 SDOperand IdxNode = Mask.getOperand(i);
6688 if (IdxNode.getOpcode() == ISD::UNDEF) {
6689 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
6692 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getValue();
6693 SDOperand InVec = Node->getOperand(0);
6694 if (Idx >= NumElements) {
6695 InVec = Node->getOperand(1);
6698 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6699 DAG.getConstant(Idx, PtrVT)));
6701 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6704 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
6705 SDOperand IdxNode = Mask.getOperand(i);
6706 if (IdxNode.getOpcode() == ISD::UNDEF) {
6707 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
6710 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getValue();
6711 SDOperand InVec = Node->getOperand(0);
6712 if (Idx >= NumElements) {
6713 InVec = Node->getOperand(1);
6716 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6717 DAG.getConstant(Idx, PtrVT)));
6719 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6722 case ISD::BUILD_VECTOR: {
6723 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
6724 Node->op_begin()+NewNumElts_Lo);
6725 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size());
6727 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
6729 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size());
6732 case ISD::CONCAT_VECTORS: {
6733 // FIXME: Handle non-power-of-two vectors?
6734 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
6735 if (NewNumSubvectors == 1) {
6736 Lo = Node->getOperand(0);
6737 Hi = Node->getOperand(1);
6739 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
6740 Node->op_begin()+NewNumSubvectors);
6741 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size());
6743 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors,
6745 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size());
6750 SDOperand Cond = Node->getOperand(0);
6752 SDOperand LL, LH, RL, RH;
6753 SplitVectorOp(Node->getOperand(1), LL, LH);
6754 SplitVectorOp(Node->getOperand(2), RL, RH);
6756 if (Cond.getValueType().isVector()) {
6757 // Handle a vector merge.
6759 SplitVectorOp(Cond, CL, CH);
6760 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL);
6761 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH);
6763 // Handle a simple select with vector operands.
6764 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL);
6765 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH);
6769 case ISD::SELECT_CC: {
6770 SDOperand CondLHS = Node->getOperand(0);
6771 SDOperand CondRHS = Node->getOperand(1);
6772 SDOperand CondCode = Node->getOperand(4);
6774 SDOperand LL, LH, RL, RH;
6775 SplitVectorOp(Node->getOperand(2), LL, LH);
6776 SplitVectorOp(Node->getOperand(3), RL, RH);
6778 // Handle a simple select with vector operands.
6779 Lo = DAG.getNode(ISD::SELECT_CC, NewVT_Lo, CondLHS, CondRHS,
6781 Hi = DAG.getNode(ISD::SELECT_CC, NewVT_Hi, CondLHS, CondRHS,
6786 SDOperand LL, LH, RL, RH;
6787 SplitVectorOp(Node->getOperand(0), LL, LH);
6788 SplitVectorOp(Node->getOperand(1), RL, RH);
6789 Lo = DAG.getNode(ISD::VSETCC, NewVT_Lo, LL, RL, Node->getOperand(2));
6790 Hi = DAG.getNode(ISD::VSETCC, NewVT_Hi, LH, RH, Node->getOperand(2));
6809 SDOperand LL, LH, RL, RH;
6810 SplitVectorOp(Node->getOperand(0), LL, LH);
6811 SplitVectorOp(Node->getOperand(1), RL, RH);
6813 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL);
6814 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH);
6819 SplitVectorOp(Node->getOperand(0), L, H);
6821 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1));
6822 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1));
6833 case ISD::FP_TO_SINT:
6834 case ISD::FP_TO_UINT:
6835 case ISD::SINT_TO_FP:
6836 case ISD::UINT_TO_FP: {
6838 SplitVectorOp(Node->getOperand(0), L, H);
6840 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L);
6841 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H);
6845 LoadSDNode *LD = cast<LoadSDNode>(Node);
6846 SDOperand Ch = LD->getChain();
6847 SDOperand Ptr = LD->getBasePtr();
6848 const Value *SV = LD->getSrcValue();
6849 int SVOffset = LD->getSrcValueOffset();
6850 unsigned Alignment = LD->getAlignment();
6851 bool isVolatile = LD->isVolatile();
6853 Lo = DAG.getLoad(NewVT_Lo, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
6854 unsigned IncrementSize = NewNumElts_Lo * NewEltVT.getSizeInBits()/8;
6855 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
6856 DAG.getIntPtrConstant(IncrementSize));
6857 SVOffset += IncrementSize;
6858 Alignment = MinAlign(Alignment, IncrementSize);
6859 Hi = DAG.getLoad(NewVT_Hi, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
6861 // Build a factor node to remember that this load is independent of the
6863 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
6866 // Remember that we legalized the chain.
6867 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
6870 case ISD::BIT_CONVERT: {
6871 // We know the result is a vector. The input may be either a vector or a
6873 SDOperand InOp = Node->getOperand(0);
6874 if (!InOp.getValueType().isVector() ||
6875 InOp.getValueType().getVectorNumElements() == 1) {
6876 // The input is a scalar or single-element vector.
6877 // Lower to a store/load so that it can be split.
6878 // FIXME: this could be improved probably.
6879 unsigned LdAlign = TLI.getTargetData()->getPrefTypeAlignment(
6880 Op.getValueType().getTypeForMVT());
6881 SDOperand Ptr = DAG.CreateStackTemporary(InOp.getValueType(), LdAlign);
6882 int FI = cast<FrameIndexSDNode>(Ptr.Val)->getIndex();
6884 SDOperand St = DAG.getStore(DAG.getEntryNode(),
6886 PseudoSourceValue::getFixedStack(FI), 0);
6887 InOp = DAG.getLoad(Op.getValueType(), St, Ptr,
6888 PseudoSourceValue::getFixedStack(FI), 0);
6890 // Split the vector and convert each of the pieces now.
6891 SplitVectorOp(InOp, Lo, Hi);
6892 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo);
6893 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi);
6898 // Remember in a map if the values will be reused later.
6900 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
6901 assert(isNew && "Value already split?!?");
6905 /// ScalarizeVectorOp - Given an operand of single-element vector type
6906 /// (e.g. v1f32), convert it into the equivalent operation that returns a
6907 /// scalar (e.g. f32) value.
6908 SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) {
6909 assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!");
6910 SDNode *Node = Op.Val;
6911 MVT NewVT = Op.getValueType().getVectorElementType();
6912 assert(Op.getValueType().getVectorNumElements() == 1);
6914 // See if we already scalarized it.
6915 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op);
6916 if (I != ScalarizedNodes.end()) return I->second;
6919 switch (Node->getOpcode()) {
6922 Node->dump(&DAG); cerr << "\n";
6924 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
6941 Result = DAG.getNode(Node->getOpcode(),
6943 ScalarizeVectorOp(Node->getOperand(0)),
6944 ScalarizeVectorOp(Node->getOperand(1)));
6951 Result = DAG.getNode(Node->getOpcode(),
6953 ScalarizeVectorOp(Node->getOperand(0)));
6956 Result = DAG.getNode(Node->getOpcode(),
6958 ScalarizeVectorOp(Node->getOperand(0)),
6959 Node->getOperand(1));
6962 LoadSDNode *LD = cast<LoadSDNode>(Node);
6963 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
6964 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
6966 const Value *SV = LD->getSrcValue();
6967 int SVOffset = LD->getSrcValueOffset();
6968 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset,
6969 LD->isVolatile(), LD->getAlignment());
6971 // Remember that we legalized the chain.
6972 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
6975 case ISD::BUILD_VECTOR:
6976 Result = Node->getOperand(0);
6978 case ISD::INSERT_VECTOR_ELT:
6979 // Returning the inserted scalar element.
6980 Result = Node->getOperand(1);
6982 case ISD::CONCAT_VECTORS:
6983 assert(Node->getOperand(0).getValueType() == NewVT &&
6984 "Concat of non-legal vectors not yet supported!");
6985 Result = Node->getOperand(0);
6987 case ISD::VECTOR_SHUFFLE: {
6988 // Figure out if the scalar is the LHS or RHS and return it.
6989 SDOperand EltNum = Node->getOperand(2).getOperand(0);
6990 if (cast<ConstantSDNode>(EltNum)->getValue())
6991 Result = ScalarizeVectorOp(Node->getOperand(1));
6993 Result = ScalarizeVectorOp(Node->getOperand(0));
6996 case ISD::EXTRACT_SUBVECTOR:
6997 Result = Node->getOperand(0);
6998 assert(Result.getValueType() == NewVT);
7000 case ISD::BIT_CONVERT: {
7001 SDOperand Op0 = Op.getOperand(0);
7002 if (Op0.getValueType().getVectorNumElements() == 1)
7003 Op0 = ScalarizeVectorOp(Op0);
7004 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op0);
7008 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
7009 ScalarizeVectorOp(Op.getOperand(1)),
7010 ScalarizeVectorOp(Op.getOperand(2)));
7012 case ISD::SELECT_CC:
7013 Result = DAG.getNode(ISD::SELECT_CC, NewVT, Node->getOperand(0),
7014 Node->getOperand(1),
7015 ScalarizeVectorOp(Op.getOperand(2)),
7016 ScalarizeVectorOp(Op.getOperand(3)),
7017 Node->getOperand(4));
7020 SDOperand Op0 = ScalarizeVectorOp(Op.getOperand(0));
7021 SDOperand Op1 = ScalarizeVectorOp(Op.getOperand(1));
7022 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Op0), Op0, Op1,
7024 Result = DAG.getNode(ISD::SELECT, NewVT, Result,
7025 DAG.getConstant(-1ULL, NewVT),
7026 DAG.getConstant(0ULL, NewVT));
7031 if (TLI.isTypeLegal(NewVT))
7032 Result = LegalizeOp(Result);
7033 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
7034 assert(isNew && "Value already scalarized?");
7039 // SelectionDAG::Legalize - This is the entry point for the file.
7041 void SelectionDAG::Legalize() {
7042 if (ViewLegalizeDAGs) viewGraph();
7044 /// run - This is the main entry point to this class.
7046 SelectionDAGLegalize(*this).LegalizeDAG();