1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/CodeGen/DwarfWriter.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/CodeGen/PseudoSourceValue.h"
22 #include "llvm/Target/TargetFrameInfo.h"
23 #include "llvm/Target/TargetLowering.h"
24 #include "llvm/Target/TargetData.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Target/TargetSubtarget.h"
28 #include "llvm/CallingConv.h"
29 #include "llvm/Constants.h"
30 #include "llvm/DerivedTypes.h"
31 #include "llvm/GlobalVariable.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Compiler.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/ADT/DenseMap.h"
36 #include "llvm/ADT/SmallVector.h"
37 #include "llvm/ADT/SmallPtrSet.h"
41 //===----------------------------------------------------------------------===//
42 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
43 /// hacks on it until the target machine can handle it. This involves
44 /// eliminating value sizes the machine cannot handle (promoting small sizes to
45 /// large sizes or splitting up large values into small values) as well as
46 /// eliminating operations the machine cannot handle.
48 /// This code also does a small amount of optimization and recognition of idioms
49 /// as part of its processing. For example, if a target does not support a
50 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
51 /// will attempt merge setcc and brc instructions into brcc's.
54 class VISIBILITY_HIDDEN SelectionDAGLegalize {
57 bool TypesNeedLegalizing;
59 // Libcall insertion helpers.
61 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
62 /// legalized. We use this to ensure that calls are properly serialized
63 /// against each other, including inserted libcalls.
64 SDValue LastCALLSEQ_END;
66 /// IsLegalizingCall - This member is used *only* for purposes of providing
67 /// helpful assertions that a libcall isn't created while another call is
68 /// being legalized (which could lead to non-serialized call sequences).
69 bool IsLegalizingCall;
72 Legal, // The target natively supports this operation.
73 Promote, // This operation should be executed in a larger type.
74 Expand // Try to expand this to other ops, otherwise use a libcall.
77 /// ValueTypeActions - This is a bitvector that contains two bits for each
78 /// value type, where the two bits correspond to the LegalizeAction enum.
79 /// This can be queried with "getTypeAction(VT)".
80 TargetLowering::ValueTypeActionImpl ValueTypeActions;
82 /// LegalizedNodes - For nodes that are of legal width, and that have more
83 /// than one use, this map indicates what regularized operand to use. This
84 /// allows us to avoid legalizing the same thing more than once.
85 DenseMap<SDValue, SDValue> LegalizedNodes;
87 /// PromotedNodes - For nodes that are below legal width, and that have more
88 /// than one use, this map indicates what promoted value to use. This allows
89 /// us to avoid promoting the same thing more than once.
90 DenseMap<SDValue, SDValue> PromotedNodes;
92 /// ExpandedNodes - For nodes that need to be expanded this map indicates
93 /// which operands are the expanded version of the input. This allows
94 /// us to avoid expanding the same node more than once.
95 DenseMap<SDValue, std::pair<SDValue, SDValue> > ExpandedNodes;
97 /// SplitNodes - For vector nodes that need to be split, this map indicates
98 /// which operands are the split version of the input. This allows us
99 /// to avoid splitting the same node more than once.
100 std::map<SDValue, std::pair<SDValue, SDValue> > SplitNodes;
102 /// ScalarizedNodes - For nodes that need to be converted from vector types to
103 /// scalar types, this contains the mapping of ones we have already
104 /// processed to the result.
105 std::map<SDValue, SDValue> ScalarizedNodes;
107 /// WidenNodes - For nodes that need to be widened from one vector type to
108 /// another, this contains the mapping of those that we have already widen.
109 /// This allows us to avoid widening more than once.
110 std::map<SDValue, SDValue> WidenNodes;
112 void AddLegalizedOperand(SDValue From, SDValue To) {
113 LegalizedNodes.insert(std::make_pair(From, To));
114 // If someone requests legalization of the new node, return itself.
116 LegalizedNodes.insert(std::make_pair(To, To));
118 void AddPromotedOperand(SDValue From, SDValue To) {
119 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
120 assert(isNew && "Got into the map somehow?");
122 // If someone requests legalization of the new node, return itself.
123 LegalizedNodes.insert(std::make_pair(To, To));
125 void AddWidenedOperand(SDValue From, SDValue To) {
126 bool isNew = WidenNodes.insert(std::make_pair(From, To)).second;
127 assert(isNew && "Got into the map somehow?");
129 // If someone requests legalization of the new node, return itself.
130 LegalizedNodes.insert(std::make_pair(To, To));
134 explicit SelectionDAGLegalize(SelectionDAG &DAG, bool TypesNeedLegalizing);
136 /// getTypeAction - Return how we should legalize values of this type, either
137 /// it is already legal or we need to expand it into multiple registers of
138 /// smaller integer type, or we need to promote it to a larger type.
139 LegalizeAction getTypeAction(MVT VT) const {
140 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
143 /// isTypeLegal - Return true if this type is legal on this target.
145 bool isTypeLegal(MVT VT) const {
146 return getTypeAction(VT) == Legal;
152 /// HandleOp - Legalize, Promote, or Expand the specified operand as
153 /// appropriate for its type.
154 void HandleOp(SDValue Op);
156 /// LegalizeOp - We know that the specified value has a legal type.
157 /// Recursively ensure that the operands have legal types, then return the
159 SDValue LegalizeOp(SDValue O);
161 /// UnrollVectorOp - We know that the given vector has a legal type, however
162 /// the operation it performs is not legal and is an operation that we have
163 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
164 /// operating on each element individually.
165 SDValue UnrollVectorOp(SDValue O);
167 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
168 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
169 /// is necessary to spill the vector being inserted into to memory, perform
170 /// the insert there, and then read the result back.
171 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
172 SDValue Idx, DebugLoc dl);
174 /// PromoteOp - Given an operation that produces a value in an invalid type,
175 /// promote it to compute the value into a larger type. The produced value
176 /// will have the correct bits for the low portion of the register, but no
177 /// guarantee is made about the top bits: it may be zero, sign-extended, or
179 SDValue PromoteOp(SDValue O);
181 /// ExpandOp - Expand the specified SDValue into its two component pieces
182 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
183 /// the LegalizedNodes map is filled in for any results that are not expanded,
184 /// the ExpandedNodes map is filled in for any results that are expanded, and
185 /// the Lo/Hi values are returned. This applies to integer types and Vector
187 void ExpandOp(SDValue O, SDValue &Lo, SDValue &Hi);
189 /// WidenVectorOp - Widen a vector operation to a wider type given by WidenVT
190 /// (e.g., v3i32 to v4i32). The produced value will have the correct value
191 /// for the existing elements but no guarantee is made about the new elements
192 /// at the end of the vector: it may be zero, ones, or garbage. This is useful
193 /// when we have an instruction operating on an illegal vector type and we
194 /// want to widen it to do the computation on a legal wider vector type.
195 SDValue WidenVectorOp(SDValue Op, MVT WidenVT);
197 /// SplitVectorOp - Given an operand of vector type, break it down into
198 /// two smaller values.
199 void SplitVectorOp(SDValue O, SDValue &Lo, SDValue &Hi);
201 /// ScalarizeVectorOp - Given an operand of single-element vector type
202 /// (e.g. v1f32), convert it into the equivalent operation that returns a
203 /// scalar (e.g. f32) value.
204 SDValue ScalarizeVectorOp(SDValue O);
206 /// Useful 16 element vector type that is used to pass operands for widening.
207 typedef SmallVector<SDValue, 16> SDValueVector;
209 /// LoadWidenVectorOp - Load a vector for a wider type. Returns true if
210 /// the LdChain contains a single load and false if it contains a token
211 /// factor for multiple loads. It takes
212 /// Result: location to return the result
213 /// LdChain: location to return the load chain
214 /// Op: load operation to widen
215 /// NVT: widen vector result type we want for the load
216 bool LoadWidenVectorOp(SDValue& Result, SDValue& LdChain,
217 SDValue Op, MVT NVT);
219 /// Helper genWidenVectorLoads - Helper function to generate a set of
220 /// loads to load a vector with a resulting wider type. It takes
221 /// LdChain: list of chains for the load we have generated
222 /// Chain: incoming chain for the ld vector
223 /// BasePtr: base pointer to load from
224 /// SV: memory disambiguation source value
225 /// SVOffset: memory disambiugation offset
226 /// Alignment: alignment of the memory
227 /// isVolatile: volatile load
228 /// LdWidth: width of memory that we want to load
229 /// ResType: the wider result result type for the resulting loaded vector
230 SDValue genWidenVectorLoads(SDValueVector& LdChain, SDValue Chain,
231 SDValue BasePtr, const Value *SV,
232 int SVOffset, unsigned Alignment,
233 bool isVolatile, unsigned LdWidth,
234 MVT ResType, DebugLoc dl);
236 /// StoreWidenVectorOp - Stores a widen vector into non widen memory
237 /// location. It takes
238 /// ST: store node that we want to replace
239 /// Chain: incoming store chain
240 /// BasePtr: base address of where we want to store into
241 SDValue StoreWidenVectorOp(StoreSDNode *ST, SDValue Chain,
244 /// Helper genWidenVectorStores - Helper function to generate a set of
245 /// stores to store a widen vector into non widen memory
247 // StChain: list of chains for the stores we have generated
248 // Chain: incoming chain for the ld vector
249 // BasePtr: base pointer to load from
250 // SV: memory disambiguation source value
251 // SVOffset: memory disambiugation offset
252 // Alignment: alignment of the memory
253 // isVolatile: volatile lod
254 // ValOp: value to store
255 // StWidth: width of memory that we want to store
256 void genWidenVectorStores(SDValueVector& StChain, SDValue Chain,
257 SDValue BasePtr, const Value *SV,
258 int SVOffset, unsigned Alignment,
259 bool isVolatile, SDValue ValOp,
260 unsigned StWidth, DebugLoc dl);
262 /// isShuffleLegal - Return non-null if a vector shuffle is legal with the
263 /// specified mask and type. Targets can specify exactly which masks they
264 /// support and the code generator is tasked with not creating illegal masks.
266 /// Note that this will also return true for shuffles that are promoted to a
269 /// If this is a legal shuffle, this method returns the (possibly promoted)
270 /// build_vector Mask. If it's not a legal shuffle, it returns null.
271 SDNode *isShuffleLegal(MVT VT, SDValue Mask) const;
273 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
274 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
276 void LegalizeSetCCOperands(SDValue &LHS, SDValue &RHS, SDValue &CC,
278 void LegalizeSetCCCondCode(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
280 void LegalizeSetCC(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
282 LegalizeSetCCOperands(LHS, RHS, CC, dl);
283 LegalizeSetCCCondCode(VT, LHS, RHS, CC, dl);
286 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned,
288 SDValue ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source, DebugLoc dl);
290 SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT, DebugLoc dl);
291 SDValue ExpandBUILD_VECTOR(SDNode *Node);
292 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
293 SDValue LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy,
294 SDValue Op, DebugLoc dl);
295 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT,
297 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, bool isSigned,
299 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned,
302 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl);
303 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl);
304 bool ExpandShift(unsigned Opc, SDValue Op, SDValue Amt,
305 SDValue &Lo, SDValue &Hi, DebugLoc dl);
306 void ExpandShiftParts(unsigned NodeOp, SDValue Op, SDValue Amt,
307 SDValue &Lo, SDValue &Hi, DebugLoc dl);
309 SDValue ExpandEXTRACT_SUBVECTOR(SDValue Op);
310 SDValue ExpandEXTRACT_VECTOR_ELT(SDValue Op);
314 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
315 /// specified mask and type. Targets can specify exactly which masks they
316 /// support and the code generator is tasked with not creating illegal masks.
318 /// Note that this will also return true for shuffles that are promoted to a
320 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDValue Mask) const {
321 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
323 case TargetLowering::Legal:
324 case TargetLowering::Custom:
326 case TargetLowering::Promote: {
327 // If this is promoted to a different type, convert the shuffle mask and
328 // ask if it is legal in the promoted type!
329 MVT NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
330 MVT EltVT = NVT.getVectorElementType();
332 // If we changed # elements, change the shuffle mask.
333 unsigned NumEltsGrowth =
334 NVT.getVectorNumElements() / VT.getVectorNumElements();
335 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
336 if (NumEltsGrowth > 1) {
337 // Renumber the elements.
338 SmallVector<SDValue, 8> Ops;
339 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
340 SDValue InOp = Mask.getOperand(i);
341 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
342 if (InOp.getOpcode() == ISD::UNDEF)
343 Ops.push_back(DAG.getNode(ISD::UNDEF,
344 InOp.getNode()->getDebugLoc(), EltVT));
346 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getZExtValue();
347 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, EltVT));
351 Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getNode()->getDebugLoc(),
352 NVT, &Ops[0], Ops.size());
358 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.getNode() : 0;
361 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag, bool types)
362 : TLI(dag.getTargetLoweringInfo()), DAG(dag), TypesNeedLegalizing(types),
363 ValueTypeActions(TLI.getValueTypeActions()) {
364 assert(MVT::LAST_VALUETYPE <= 32 &&
365 "Too many value types for ValueTypeActions to hold!");
368 void SelectionDAGLegalize::LegalizeDAG() {
369 LastCALLSEQ_END = DAG.getEntryNode();
370 IsLegalizingCall = false;
372 // The legalize process is inherently a bottom-up recursive process (users
373 // legalize their uses before themselves). Given infinite stack space, we
374 // could just start legalizing on the root and traverse the whole graph. In
375 // practice however, this causes us to run out of stack space on large basic
376 // blocks. To avoid this problem, compute an ordering of the nodes where each
377 // node is only legalized after all of its operands are legalized.
378 DAG.AssignTopologicalOrder();
379 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
380 E = prior(DAG.allnodes_end()); I != next(E); ++I)
381 HandleOp(SDValue(I, 0));
383 // Finally, it's possible the root changed. Get the new root.
384 SDValue OldRoot = DAG.getRoot();
385 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
386 DAG.setRoot(LegalizedNodes[OldRoot]);
388 ExpandedNodes.clear();
389 LegalizedNodes.clear();
390 PromotedNodes.clear();
392 ScalarizedNodes.clear();
395 // Remove dead nodes now.
396 DAG.RemoveDeadNodes();
400 /// FindCallEndFromCallStart - Given a chained node that is part of a call
401 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
402 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
403 if (Node->getOpcode() == ISD::CALLSEQ_END)
405 if (Node->use_empty())
406 return 0; // No CallSeqEnd
408 // The chain is usually at the end.
409 SDValue TheChain(Node, Node->getNumValues()-1);
410 if (TheChain.getValueType() != MVT::Other) {
411 // Sometimes it's at the beginning.
412 TheChain = SDValue(Node, 0);
413 if (TheChain.getValueType() != MVT::Other) {
414 // Otherwise, hunt for it.
415 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
416 if (Node->getValueType(i) == MVT::Other) {
417 TheChain = SDValue(Node, i);
421 // Otherwise, we walked into a node without a chain.
422 if (TheChain.getValueType() != MVT::Other)
427 for (SDNode::use_iterator UI = Node->use_begin(),
428 E = Node->use_end(); UI != E; ++UI) {
430 // Make sure to only follow users of our token chain.
432 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
433 if (User->getOperand(i) == TheChain)
434 if (SDNode *Result = FindCallEndFromCallStart(User))
440 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
441 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
442 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
443 assert(Node && "Didn't find callseq_start for a call??");
444 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
446 assert(Node->getOperand(0).getValueType() == MVT::Other &&
447 "Node doesn't have a token chain argument!");
448 return FindCallStartFromCallEnd(Node->getOperand(0).getNode());
451 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
452 /// see if any uses can reach Dest. If no dest operands can get to dest,
453 /// legalize them, legalize ourself, and return false, otherwise, return true.
455 /// Keep track of the nodes we fine that actually do lead to Dest in
456 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
458 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
459 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
460 if (N == Dest) return true; // N certainly leads to Dest :)
462 // If we've already processed this node and it does lead to Dest, there is no
463 // need to reprocess it.
464 if (NodesLeadingTo.count(N)) return true;
466 // If the first result of this node has been already legalized, then it cannot
468 switch (getTypeAction(N->getValueType(0))) {
470 if (LegalizedNodes.count(SDValue(N, 0))) return false;
473 if (PromotedNodes.count(SDValue(N, 0))) return false;
476 if (ExpandedNodes.count(SDValue(N, 0))) return false;
480 // Okay, this node has not already been legalized. Check and legalize all
481 // operands. If none lead to Dest, then we can legalize this node.
482 bool OperandsLeadToDest = false;
483 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
484 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
485 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo);
487 if (OperandsLeadToDest) {
488 NodesLeadingTo.insert(N);
492 // Okay, this node looks safe, legalize it and return false.
493 HandleOp(SDValue(N, 0));
497 /// HandleOp - Legalize, Promote, Widen, or Expand the specified operand as
498 /// appropriate for its type.
499 void SelectionDAGLegalize::HandleOp(SDValue Op) {
500 MVT VT = Op.getValueType();
501 // If the type legalizer was run then we should never see any illegal result
502 // types here except for target constants (the type legalizer does not touch
503 // those) or for build vector used as a mask for a vector shuffle.
504 // FIXME: We can removed the BUILD_VECTOR case when we fix PR2957.
505 assert((TypesNeedLegalizing || getTypeAction(VT) == Legal ||
506 Op.getOpcode() == ISD::TargetConstant ||
507 Op.getOpcode() == ISD::BUILD_VECTOR) &&
508 "Illegal type introduced after type legalization?");
509 switch (getTypeAction(VT)) {
510 default: assert(0 && "Bad type action!");
511 case Legal: (void)LegalizeOp(Op); break;
513 if (!VT.isVector()) {
518 // See if we can widen otherwise use Expand to either scalarize or split
519 MVT WidenVT = TLI.getWidenVectorType(VT);
520 if (WidenVT != MVT::Other) {
521 (void) WidenVectorOp(Op, WidenVT);
524 // else fall thru to expand since we can't widen the vector
527 if (!VT.isVector()) {
528 // If this is an illegal scalar, expand it into its two component
531 if (Op.getOpcode() == ISD::TargetConstant)
532 break; // Allow illegal target nodes.
534 } else if (VT.getVectorNumElements() == 1) {
535 // If this is an illegal single element vector, convert it to a
537 (void)ScalarizeVectorOp(Op);
539 // This is an illegal multiple element vector.
540 // Split it in half and legalize both parts.
542 SplitVectorOp(Op, X, Y);
548 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
549 /// a load from the constant pool.
550 static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
551 SelectionDAG &DAG, const TargetLowering &TLI) {
554 // If a FP immediate is precise when represented as a float and if the
555 // target can do an extending load from float to double, we put it into
556 // the constant pool as a float, even if it's is statically typed as a
557 // double. This shrinks FP constants and canonicalizes them for targets where
558 // an FP extending load is the same cost as a normal load (such as on the x87
559 // fp stack or PPC FP unit).
560 MVT VT = CFP->getValueType(0);
561 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
563 if (VT!=MVT::f64 && VT!=MVT::f32)
564 assert(0 && "Invalid type expansion");
565 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
566 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
571 while (SVT != MVT::f32) {
572 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1);
573 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
574 // Only do this if the target has a native EXTLOAD instruction from
576 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
577 TLI.ShouldShrinkFPConstant(OrigVT)) {
578 const Type *SType = SVT.getTypeForMVT();
579 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
585 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
586 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
588 return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, DAG.getEntryNode(),
589 CPIdx, PseudoSourceValue::getConstantPool(),
590 0, VT, false, Alignment);
591 return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx,
592 PseudoSourceValue::getConstantPool(), 0, false, Alignment);
596 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
599 SDValue ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT,
601 const TargetLowering &TLI) {
602 DebugLoc dl = Node->getDebugLoc();
603 MVT VT = Node->getValueType(0);
604 MVT SrcVT = Node->getOperand(1).getValueType();
605 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
606 "fcopysign expansion only supported for f32 and f64");
607 MVT SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
609 // First get the sign bit of second operand.
610 SDValue Mask1 = (SrcVT == MVT::f64)
611 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
612 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
613 Mask1 = DAG.getNode(ISD::BIT_CONVERT, dl, SrcNVT, Mask1);
614 SDValue SignBit= DAG.getNode(ISD::BIT_CONVERT, dl, SrcNVT,
615 Node->getOperand(1));
616 SignBit = DAG.getNode(ISD::AND, dl, SrcNVT, SignBit, Mask1);
617 // Shift right or sign-extend it if the two operands have different types.
618 int SizeDiff = SrcNVT.getSizeInBits() - NVT.getSizeInBits();
620 SignBit = DAG.getNode(ISD::SRL, dl, SrcNVT, SignBit,
621 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
622 SignBit = DAG.getNode(ISD::TRUNCATE, dl, NVT, SignBit);
623 } else if (SizeDiff < 0) {
624 SignBit = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, SignBit);
625 SignBit = DAG.getNode(ISD::SHL, dl, NVT, SignBit,
626 DAG.getConstant(-SizeDiff, TLI.getShiftAmountTy()));
629 // Clear the sign bit of first operand.
630 SDValue Mask2 = (VT == MVT::f64)
631 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
632 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
633 Mask2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Mask2);
634 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
635 Result = DAG.getNode(ISD::AND, dl, NVT, Result, Mask2);
637 // Or the value with the sign bit.
638 Result = DAG.getNode(ISD::OR, dl, NVT, Result, SignBit);
642 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
644 SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
645 const TargetLowering &TLI) {
646 SDValue Chain = ST->getChain();
647 SDValue Ptr = ST->getBasePtr();
648 SDValue Val = ST->getValue();
649 MVT VT = Val.getValueType();
650 int Alignment = ST->getAlignment();
651 int SVOffset = ST->getSrcValueOffset();
652 DebugLoc dl = ST->getDebugLoc();
653 if (ST->getMemoryVT().isFloatingPoint() ||
654 ST->getMemoryVT().isVector()) {
655 MVT intVT = MVT::getIntegerVT(VT.getSizeInBits());
656 if (TLI.isTypeLegal(intVT)) {
657 // Expand to a bitconvert of the value to the integer type of the
658 // same size, then a (misaligned) int store.
659 // FIXME: Does not handle truncating floating point stores!
660 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, intVT, Val);
661 return DAG.getStore(Chain, dl, Result, Ptr, ST->getSrcValue(),
662 SVOffset, ST->isVolatile(), Alignment);
664 // Do a (aligned) store to a stack slot, then copy from the stack slot
665 // to the final destination using (unaligned) integer loads and stores.
666 MVT StoredVT = ST->getMemoryVT();
668 TLI.getRegisterType(MVT::getIntegerVT(StoredVT.getSizeInBits()));
669 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
670 unsigned RegBytes = RegVT.getSizeInBits() / 8;
671 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
673 // Make sure the stack slot is also aligned for the register type.
674 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
676 // Perform the original store, only redirected to the stack slot.
677 SDValue Store = DAG.getTruncStore(Chain, dl,
678 Val, StackPtr, NULL, 0,StoredVT);
679 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
680 SmallVector<SDValue, 8> Stores;
683 // Do all but one copies using the full register width.
684 for (unsigned i = 1; i < NumRegs; i++) {
685 // Load one integer register's worth from the stack slot.
686 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, NULL, 0);
687 // Store it to the final location. Remember the store.
688 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
689 ST->getSrcValue(), SVOffset + Offset,
691 MinAlign(ST->getAlignment(), Offset)));
692 // Increment the pointers.
694 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
696 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
699 // The last store may be partial. Do a truncating store. On big-endian
700 // machines this requires an extending load from the stack slot to ensure
701 // that the bits are in the right place.
702 MVT MemVT = MVT::getIntegerVT(8 * (StoredBytes - Offset));
704 // Load from the stack slot.
705 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
708 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
709 ST->getSrcValue(), SVOffset + Offset,
710 MemVT, ST->isVolatile(),
711 MinAlign(ST->getAlignment(), Offset)));
712 // The order of the stores doesn't matter - say it with a TokenFactor.
713 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
717 assert(ST->getMemoryVT().isInteger() &&
718 !ST->getMemoryVT().isVector() &&
719 "Unaligned store of unknown type.");
720 // Get the half-size VT
722 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1);
723 int NumBits = NewStoredVT.getSizeInBits();
724 int IncrementSize = NumBits / 8;
726 // Divide the stored value in two parts.
727 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
729 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
731 // Store the two parts
732 SDValue Store1, Store2;
733 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
734 ST->getSrcValue(), SVOffset, NewStoredVT,
735 ST->isVolatile(), Alignment);
736 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
737 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
738 Alignment = MinAlign(Alignment, IncrementSize);
739 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
740 ST->getSrcValue(), SVOffset + IncrementSize,
741 NewStoredVT, ST->isVolatile(), Alignment);
743 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
746 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
748 SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
749 const TargetLowering &TLI) {
750 int SVOffset = LD->getSrcValueOffset();
751 SDValue Chain = LD->getChain();
752 SDValue Ptr = LD->getBasePtr();
753 MVT VT = LD->getValueType(0);
754 MVT LoadedVT = LD->getMemoryVT();
755 DebugLoc dl = LD->getDebugLoc();
756 if (VT.isFloatingPoint() || VT.isVector()) {
757 MVT intVT = MVT::getIntegerVT(LoadedVT.getSizeInBits());
758 if (TLI.isTypeLegal(intVT)) {
759 // Expand to a (misaligned) integer load of the same size,
760 // then bitconvert to floating point or vector.
761 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getSrcValue(),
762 SVOffset, LD->isVolatile(),
764 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, LoadedVT, newLoad);
765 if (VT.isFloatingPoint() && LoadedVT != VT)
766 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result);
768 SDValue Ops[] = { Result, Chain };
769 return DAG.getMergeValues(Ops, 2, dl);
771 // Copy the value to a (aligned) stack slot using (unaligned) integer
772 // loads and stores, then do a (aligned) load from the stack slot.
773 MVT RegVT = TLI.getRegisterType(intVT);
774 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
775 unsigned RegBytes = RegVT.getSizeInBits() / 8;
776 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
778 // Make sure the stack slot is also aligned for the register type.
779 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
781 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
782 SmallVector<SDValue, 8> Stores;
783 SDValue StackPtr = StackBase;
786 // Do all but one copies using the full register width.
787 for (unsigned i = 1; i < NumRegs; i++) {
788 // Load one integer register's worth from the original location.
789 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, LD->getSrcValue(),
790 SVOffset + Offset, LD->isVolatile(),
791 MinAlign(LD->getAlignment(), Offset));
792 // Follow the load with a store to the stack slot. Remember the store.
793 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
795 // Increment the pointers.
797 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
798 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
802 // The last copy may be partial. Do an extending load.
803 MVT MemVT = MVT::getIntegerVT(8 * (LoadedBytes - Offset));
804 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
805 LD->getSrcValue(), SVOffset + Offset,
806 MemVT, LD->isVolatile(),
807 MinAlign(LD->getAlignment(), Offset));
808 // Follow the load with a store to the stack slot. Remember the store.
809 // On big-endian machines this requires a truncating store to ensure
810 // that the bits end up in the right place.
811 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
814 // The order of the stores doesn't matter - say it with a TokenFactor.
815 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
818 // Finally, perform the original load only redirected to the stack slot.
819 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
822 // Callers expect a MERGE_VALUES node.
823 SDValue Ops[] = { Load, TF };
824 return DAG.getMergeValues(Ops, 2, dl);
827 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
828 "Unaligned load of unsupported type.");
830 // Compute the new VT that is half the size of the old one. This is an
832 unsigned NumBits = LoadedVT.getSizeInBits();
834 NewLoadedVT = MVT::getIntegerVT(NumBits/2);
837 unsigned Alignment = LD->getAlignment();
838 unsigned IncrementSize = NumBits / 8;
839 ISD::LoadExtType HiExtType = LD->getExtensionType();
841 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
842 if (HiExtType == ISD::NON_EXTLOAD)
843 HiExtType = ISD::ZEXTLOAD;
845 // Load the value in two parts
847 if (TLI.isLittleEndian()) {
848 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(),
849 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
850 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
851 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
852 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(),
853 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
854 MinAlign(Alignment, IncrementSize));
856 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(),
857 SVOffset, NewLoadedVT,LD->isVolatile(), Alignment);
858 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
859 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
860 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(),
861 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
862 MinAlign(Alignment, IncrementSize));
865 // aggregate the two parts
866 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
867 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
868 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
870 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
873 SDValue Ops[] = { Result, TF };
874 return DAG.getMergeValues(Ops, 2, dl);
877 /// UnrollVectorOp - We know that the given vector has a legal type, however
878 /// the operation it performs is not legal and is an operation that we have
879 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
880 /// operating on each element individually.
881 SDValue SelectionDAGLegalize::UnrollVectorOp(SDValue Op) {
882 MVT VT = Op.getValueType();
883 assert(isTypeLegal(VT) &&
884 "Caller should expand or promote operands that are not legal!");
885 assert(Op.getNode()->getNumValues() == 1 &&
886 "Can't unroll a vector with multiple results!");
887 unsigned NE = VT.getVectorNumElements();
888 MVT EltVT = VT.getVectorElementType();
889 DebugLoc dl = Op.getNode()->getDebugLoc();
891 SmallVector<SDValue, 8> Scalars;
892 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
893 for (unsigned i = 0; i != NE; ++i) {
894 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
895 SDValue Operand = Op.getOperand(j);
896 MVT OperandVT = Operand.getValueType();
897 if (OperandVT.isVector()) {
898 // A vector operand; extract a single element.
899 MVT OperandEltVT = OperandVT.getVectorElementType();
900 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
903 DAG.getConstant(i, MVT::i32));
905 // A scalar operand; just use it as is.
906 Operands[j] = Operand;
910 switch (Op.getOpcode()) {
912 Scalars.push_back(DAG.getNode(Op.getOpcode(), dl, EltVT,
913 &Operands[0], Operands.size()));
920 Scalars.push_back(DAG.getNode(Op.getOpcode(), dl, EltVT, Operands[0],
921 DAG.getShiftAmountOperand(Operands[1])));
926 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Scalars[0], Scalars.size());
929 /// GetFPLibCall - Return the right libcall for the given floating point type.
930 static RTLIB::Libcall GetFPLibCall(MVT VT,
931 RTLIB::Libcall Call_F32,
932 RTLIB::Libcall Call_F64,
933 RTLIB::Libcall Call_F80,
934 RTLIB::Libcall Call_PPCF128) {
936 VT == MVT::f32 ? Call_F32 :
937 VT == MVT::f64 ? Call_F64 :
938 VT == MVT::f80 ? Call_F80 :
939 VT == MVT::ppcf128 ? Call_PPCF128 :
940 RTLIB::UNKNOWN_LIBCALL;
943 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
944 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
945 /// is necessary to spill the vector being inserted into to memory, perform
946 /// the insert there, and then read the result back.
947 SDValue SelectionDAGLegalize::
948 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
954 // If the target doesn't support this, we have to spill the input vector
955 // to a temporary stack slot, update the element, then reload it. This is
956 // badness. We could also load the value into a vector register (either
957 // with a "move to register" or "extload into register" instruction, then
958 // permute it into place, if the idx is a constant and if the idx is
959 // supported by the target.
960 MVT VT = Tmp1.getValueType();
961 MVT EltVT = VT.getVectorElementType();
962 MVT IdxVT = Tmp3.getValueType();
963 MVT PtrVT = TLI.getPointerTy();
964 SDValue StackPtr = DAG.CreateStackTemporary(VT);
966 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
969 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
970 PseudoSourceValue::getFixedStack(SPFI), 0);
972 // Truncate or zero extend offset to target pointer type.
973 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
974 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
975 // Add the offset to the index.
976 unsigned EltSize = EltVT.getSizeInBits()/8;
977 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
978 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
979 // Store the scalar value.
980 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2,
981 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT);
982 // Load the updated vector.
983 return DAG.getLoad(VT, dl, Ch, StackPtr,
984 PseudoSourceValue::getFixedStack(SPFI), 0);
988 /// LegalizeOp - We know that the specified value has a legal type, and
989 /// that its operands are legal. Now ensure that the operation itself
990 /// is legal, recursively ensuring that the operands' operations remain
992 SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
993 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
996 assert(isTypeLegal(Op.getValueType()) &&
997 "Caller should expand or promote operands that are not legal!");
998 SDNode *Node = Op.getNode();
999 DebugLoc dl = Node->getDebugLoc();
1001 // If this operation defines any values that cannot be represented in a
1002 // register on this target, make sure to expand or promote them.
1003 if (Node->getNumValues() > 1) {
1004 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1005 if (getTypeAction(Node->getValueType(i)) != Legal) {
1006 HandleOp(Op.getValue(i));
1007 assert(LegalizedNodes.count(Op) &&
1008 "Handling didn't add legal operands!");
1009 return LegalizedNodes[Op];
1013 // Note that LegalizeOp may be reentered even from single-use nodes, which
1014 // means that we always must cache transformed nodes.
1015 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1016 if (I != LegalizedNodes.end()) return I->second;
1018 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
1019 SDValue Result = Op;
1020 bool isCustom = false;
1022 switch (Node->getOpcode()) {
1023 case ISD::FrameIndex:
1024 case ISD::EntryToken:
1026 case ISD::BasicBlock:
1027 case ISD::TargetFrameIndex:
1028 case ISD::TargetJumpTable:
1029 case ISD::TargetConstant:
1030 case ISD::TargetConstantFP:
1031 case ISD::TargetConstantPool:
1032 case ISD::TargetGlobalAddress:
1033 case ISD::TargetGlobalTLSAddress:
1034 case ISD::TargetExternalSymbol:
1035 case ISD::VALUETYPE:
1037 case ISD::MEMOPERAND:
1039 case ISD::ARG_FLAGS:
1040 // Primitives must all be legal.
1041 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
1042 "This must be legal!");
1045 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1046 // If this is a target node, legalize it by legalizing the operands then
1047 // passing it through.
1048 SmallVector<SDValue, 8> Ops;
1049 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1050 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1052 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
1054 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1055 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
1056 return Result.getValue(Op.getResNo());
1058 // Otherwise this is an unhandled builtin node. splat.
1060 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
1062 assert(0 && "Do not know how to legalize this operator!");
1064 case ISD::GLOBAL_OFFSET_TABLE:
1065 case ISD::GlobalAddress:
1066 case ISD::GlobalTLSAddress:
1067 case ISD::ExternalSymbol:
1068 case ISD::ConstantPool:
1069 case ISD::JumpTable: // Nothing to do.
1070 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1071 default: assert(0 && "This action is not supported yet!");
1072 case TargetLowering::Custom:
1073 Tmp1 = TLI.LowerOperation(Op, DAG);
1074 if (Tmp1.getNode()) Result = Tmp1;
1075 // FALLTHROUGH if the target doesn't want to lower this op after all.
1076 case TargetLowering::Legal:
1080 case ISD::FRAMEADDR:
1081 case ISD::RETURNADDR:
1082 // The only option for these nodes is to custom lower them. If the target
1083 // does not custom lower them, then return zero.
1084 Tmp1 = TLI.LowerOperation(Op, DAG);
1088 Result = DAG.getConstant(0, TLI.getPointerTy());
1090 case ISD::FRAME_TO_ARGS_OFFSET: {
1091 MVT VT = Node->getValueType(0);
1092 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1093 default: assert(0 && "This action is not supported yet!");
1094 case TargetLowering::Custom:
1095 Result = TLI.LowerOperation(Op, DAG);
1096 if (Result.getNode()) break;
1098 case TargetLowering::Legal:
1099 Result = DAG.getConstant(0, VT);
1104 case ISD::EXCEPTIONADDR: {
1105 Tmp1 = LegalizeOp(Node->getOperand(0));
1106 MVT VT = Node->getValueType(0);
1107 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1108 default: assert(0 && "This action is not supported yet!");
1109 case TargetLowering::Expand: {
1110 unsigned Reg = TLI.getExceptionAddressRegister();
1111 Result = DAG.getCopyFromReg(Tmp1, Reg, VT);
1114 case TargetLowering::Custom:
1115 Result = TLI.LowerOperation(Op, DAG);
1116 if (Result.getNode()) break;
1118 case TargetLowering::Legal: {
1119 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp1 };
1120 Result = DAG.getMergeValues(Ops, 2, dl);
1125 if (Result.getNode()->getNumValues() == 1) break;
1127 assert(Result.getNode()->getNumValues() == 2 &&
1128 "Cannot return more than two values!");
1130 // Since we produced two values, make sure to remember that we
1131 // legalized both of them.
1132 Tmp1 = LegalizeOp(Result);
1133 Tmp2 = LegalizeOp(Result.getValue(1));
1134 AddLegalizedOperand(Op.getValue(0), Tmp1);
1135 AddLegalizedOperand(Op.getValue(1), Tmp2);
1136 return Op.getResNo() ? Tmp2 : Tmp1;
1137 case ISD::EHSELECTION: {
1138 Tmp1 = LegalizeOp(Node->getOperand(0));
1139 Tmp2 = LegalizeOp(Node->getOperand(1));
1140 MVT VT = Node->getValueType(0);
1141 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1142 default: assert(0 && "This action is not supported yet!");
1143 case TargetLowering::Expand: {
1144 unsigned Reg = TLI.getExceptionSelectorRegister();
1145 Result = DAG.getCopyFromReg(Tmp2, Reg, VT);
1148 case TargetLowering::Custom:
1149 Result = TLI.LowerOperation(Op, DAG);
1150 if (Result.getNode()) break;
1152 case TargetLowering::Legal: {
1153 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp2 };
1154 Result = DAG.getMergeValues(Ops, 2, dl);
1159 if (Result.getNode()->getNumValues() == 1) break;
1161 assert(Result.getNode()->getNumValues() == 2 &&
1162 "Cannot return more than two values!");
1164 // Since we produced two values, make sure to remember that we
1165 // legalized both of them.
1166 Tmp1 = LegalizeOp(Result);
1167 Tmp2 = LegalizeOp(Result.getValue(1));
1168 AddLegalizedOperand(Op.getValue(0), Tmp1);
1169 AddLegalizedOperand(Op.getValue(1), Tmp2);
1170 return Op.getResNo() ? Tmp2 : Tmp1;
1171 case ISD::EH_RETURN: {
1172 MVT VT = Node->getValueType(0);
1173 // The only "good" option for this node is to custom lower it.
1174 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1175 default: assert(0 && "This action is not supported at all!");
1176 case TargetLowering::Custom:
1177 Result = TLI.LowerOperation(Op, DAG);
1178 if (Result.getNode()) break;
1180 case TargetLowering::Legal:
1181 // Target does not know, how to lower this, lower to noop
1182 Result = LegalizeOp(Node->getOperand(0));
1187 case ISD::AssertSext:
1188 case ISD::AssertZext:
1189 Tmp1 = LegalizeOp(Node->getOperand(0));
1190 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1192 case ISD::MERGE_VALUES:
1193 // Legalize eliminates MERGE_VALUES nodes.
1194 Result = Node->getOperand(Op.getResNo());
1196 case ISD::CopyFromReg:
1197 Tmp1 = LegalizeOp(Node->getOperand(0));
1198 Result = Op.getValue(0);
1199 if (Node->getNumValues() == 2) {
1200 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1202 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
1203 if (Node->getNumOperands() == 3) {
1204 Tmp2 = LegalizeOp(Node->getOperand(2));
1205 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1207 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1209 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
1211 // Since CopyFromReg produces two values, make sure to remember that we
1212 // legalized both of them.
1213 AddLegalizedOperand(Op.getValue(0), Result);
1214 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1215 return Result.getValue(Op.getResNo());
1217 MVT VT = Op.getValueType();
1218 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
1219 default: assert(0 && "This action is not supported yet!");
1220 case TargetLowering::Expand:
1222 Result = DAG.getConstant(0, VT);
1223 else if (VT.isFloatingPoint())
1224 Result = DAG.getConstantFP(APFloat(APInt(VT.getSizeInBits(), 0)),
1227 assert(0 && "Unknown value type!");
1229 case TargetLowering::Legal:
1235 case ISD::INTRINSIC_W_CHAIN:
1236 case ISD::INTRINSIC_WO_CHAIN:
1237 case ISD::INTRINSIC_VOID: {
1238 SmallVector<SDValue, 8> Ops;
1239 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1240 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1241 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1243 // Allow the target to custom lower its intrinsics if it wants to.
1244 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
1245 TargetLowering::Custom) {
1246 Tmp3 = TLI.LowerOperation(Result, DAG);
1247 if (Tmp3.getNode()) Result = Tmp3;
1250 if (Result.getNode()->getNumValues() == 1) break;
1252 // Must have return value and chain result.
1253 assert(Result.getNode()->getNumValues() == 2 &&
1254 "Cannot return more than two values!");
1256 // Since loads produce two values, make sure to remember that we
1257 // legalized both of them.
1258 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1259 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1260 return Result.getValue(Op.getResNo());
1263 case ISD::DBG_STOPPOINT:
1264 assert(Node->getNumOperands() == 1 && "Invalid DBG_STOPPOINT node!");
1265 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
1267 switch (TLI.getOperationAction(ISD::DBG_STOPPOINT, MVT::Other)) {
1268 case TargetLowering::Promote:
1269 default: assert(0 && "This action is not supported yet!");
1270 case TargetLowering::Expand: {
1271 DwarfWriter *DW = DAG.getDwarfWriter();
1272 bool useDEBUG_LOC = TLI.isOperationLegalOrCustom(ISD::DEBUG_LOC,
1274 bool useLABEL = TLI.isOperationLegalOrCustom(ISD::DBG_LABEL, MVT::Other);
1276 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node);
1277 GlobalVariable *CU_GV = cast<GlobalVariable>(DSP->getCompileUnit());
1278 if (DW && (useDEBUG_LOC || useLABEL) && !CU_GV->isDeclaration()) {
1279 DICompileUnit CU(cast<GlobalVariable>(DSP->getCompileUnit()));
1280 unsigned SrcFile = DW->RecordSource(CU.getDirectory(),
1283 unsigned Line = DSP->getLine();
1284 unsigned Col = DSP->getColumn();
1286 // A bit self-referential to have DebugLoc on Debug_Loc nodes, but
1287 // it won't hurt anything.
1289 SDValue Ops[] = { Tmp1, DAG.getConstant(Line, MVT::i32),
1290 DAG.getConstant(Col, MVT::i32),
1291 DAG.getConstant(SrcFile, MVT::i32) };
1292 Result = DAG.getNode(ISD::DEBUG_LOC, dl, MVT::Other, Ops, 4);
1294 unsigned ID = DW->RecordSourceLine(Line, Col, SrcFile);
1295 Result = DAG.getLabel(ISD::DBG_LABEL, dl, Tmp1, ID);
1298 Result = Tmp1; // chain
1302 case TargetLowering::Legal: {
1303 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1304 if (Action == Legal && Tmp1 == Node->getOperand(0))
1307 SmallVector<SDValue, 8> Ops;
1308 Ops.push_back(Tmp1);
1309 if (Action == Legal) {
1310 Ops.push_back(Node->getOperand(1)); // line # must be legal.
1311 Ops.push_back(Node->getOperand(2)); // col # must be legal.
1313 // Otherwise promote them.
1314 Ops.push_back(PromoteOp(Node->getOperand(1)));
1315 Ops.push_back(PromoteOp(Node->getOperand(2)));
1317 Ops.push_back(Node->getOperand(3)); // filename must be legal.
1318 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
1319 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1326 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!");
1327 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) {
1328 default: assert(0 && "This action is not supported yet!");
1329 case TargetLowering::Legal:
1330 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1331 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1332 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable.
1333 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1335 case TargetLowering::Expand:
1336 Result = LegalizeOp(Node->getOperand(0));
1341 case ISD::DEBUG_LOC:
1342 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
1343 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
1344 default: assert(0 && "This action is not supported yet!");
1345 case TargetLowering::Legal: {
1346 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1347 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1348 if (Action == Legal && Tmp1 == Node->getOperand(0))
1350 if (Action == Legal) {
1351 Tmp2 = Node->getOperand(1);
1352 Tmp3 = Node->getOperand(2);
1353 Tmp4 = Node->getOperand(3);
1355 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1356 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1357 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1359 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1365 case ISD::DBG_LABEL:
1367 assert(Node->getNumOperands() == 1 && "Invalid LABEL node!");
1368 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
1369 default: assert(0 && "This action is not supported yet!");
1370 case TargetLowering::Legal:
1371 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1372 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1374 case TargetLowering::Expand:
1375 Result = LegalizeOp(Node->getOperand(0));
1381 assert(Node->getNumOperands() == 4 && "Invalid Prefetch node!");
1382 switch (TLI.getOperationAction(ISD::PREFETCH, MVT::Other)) {
1383 default: assert(0 && "This action is not supported yet!");
1384 case TargetLowering::Legal:
1385 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1386 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1387 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the rw specifier.
1388 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize locality specifier.
1389 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1391 case TargetLowering::Expand:
1393 Result = LegalizeOp(Node->getOperand(0));
1398 case ISD::MEMBARRIER: {
1399 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!");
1400 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) {
1401 default: assert(0 && "This action is not supported yet!");
1402 case TargetLowering::Legal: {
1404 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1405 for (int x = 1; x < 6; ++x) {
1406 Ops[x] = Node->getOperand(x);
1407 if (!isTypeLegal(Ops[x].getValueType()))
1408 Ops[x] = PromoteOp(Ops[x]);
1410 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6);
1413 case TargetLowering::Expand:
1414 //There is no libgcc call for this op
1415 Result = Node->getOperand(0); // Noop
1421 case ISD::ATOMIC_CMP_SWAP: {
1422 unsigned int num_operands = 4;
1423 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1425 for (unsigned int x = 0; x < num_operands; ++x)
1426 Ops[x] = LegalizeOp(Node->getOperand(x));
1427 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1429 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1430 default: assert(0 && "This action is not supported yet!");
1431 case TargetLowering::Custom:
1432 Result = TLI.LowerOperation(Result, DAG);
1434 case TargetLowering::Legal:
1437 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1438 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1439 return Result.getValue(Op.getResNo());
1441 case ISD::ATOMIC_LOAD_ADD:
1442 case ISD::ATOMIC_LOAD_SUB:
1443 case ISD::ATOMIC_LOAD_AND:
1444 case ISD::ATOMIC_LOAD_OR:
1445 case ISD::ATOMIC_LOAD_XOR:
1446 case ISD::ATOMIC_LOAD_NAND:
1447 case ISD::ATOMIC_LOAD_MIN:
1448 case ISD::ATOMIC_LOAD_MAX:
1449 case ISD::ATOMIC_LOAD_UMIN:
1450 case ISD::ATOMIC_LOAD_UMAX:
1451 case ISD::ATOMIC_SWAP: {
1452 unsigned int num_operands = 3;
1453 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1455 for (unsigned int x = 0; x < num_operands; ++x)
1456 Ops[x] = LegalizeOp(Node->getOperand(x));
1457 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1459 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1460 default: assert(0 && "This action is not supported yet!");
1461 case TargetLowering::Custom:
1462 Result = TLI.LowerOperation(Result, DAG);
1464 case TargetLowering::Legal:
1467 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1468 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1469 return Result.getValue(Op.getResNo());
1471 case ISD::Constant: {
1472 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1474 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1476 // We know we don't need to expand constants here, constants only have one
1477 // value and we check that it is fine above.
1479 if (opAction == TargetLowering::Custom) {
1480 Tmp1 = TLI.LowerOperation(Result, DAG);
1486 case ISD::ConstantFP: {
1487 // Spill FP immediates to the constant pool if the target cannot directly
1488 // codegen them. Targets often have some immediate values that can be
1489 // efficiently generated into an FP register without a load. We explicitly
1490 // leave these constants as ConstantFP nodes for the target to deal with.
1491 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1493 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1494 default: assert(0 && "This action is not supported yet!");
1495 case TargetLowering::Legal:
1497 case TargetLowering::Custom:
1498 Tmp3 = TLI.LowerOperation(Result, DAG);
1499 if (Tmp3.getNode()) {
1504 case TargetLowering::Expand: {
1505 // Check to see if this FP immediate is already legal.
1506 bool isLegal = false;
1507 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1508 E = TLI.legal_fpimm_end(); I != E; ++I) {
1509 if (CFP->isExactlyValue(*I)) {
1514 // If this is a legal constant, turn it into a TargetConstantFP node.
1517 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1522 case ISD::TokenFactor:
1523 if (Node->getNumOperands() == 2) {
1524 Tmp1 = LegalizeOp(Node->getOperand(0));
1525 Tmp2 = LegalizeOp(Node->getOperand(1));
1526 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1527 } else if (Node->getNumOperands() == 3) {
1528 Tmp1 = LegalizeOp(Node->getOperand(0));
1529 Tmp2 = LegalizeOp(Node->getOperand(1));
1530 Tmp3 = LegalizeOp(Node->getOperand(2));
1531 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1533 SmallVector<SDValue, 8> Ops;
1534 // Legalize the operands.
1535 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1536 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1537 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1541 case ISD::FORMAL_ARGUMENTS:
1543 // The only option for this is to custom lower it.
1544 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1545 assert(Tmp3.getNode() && "Target didn't custom lower this node!");
1546 // A call within a calling sequence must be legalized to something
1547 // other than the normal CALLSEQ_END. Violating this gets Legalize
1548 // into an infinite loop.
1549 assert ((!IsLegalizingCall ||
1550 Node->getOpcode() != ISD::CALL ||
1551 Tmp3.getNode()->getOpcode() != ISD::CALLSEQ_END) &&
1552 "Nested CALLSEQ_START..CALLSEQ_END not supported.");
1554 // The number of incoming and outgoing values should match; unless the final
1555 // outgoing value is a flag.
1556 assert((Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() ||
1557 (Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() + 1 &&
1558 Tmp3.getNode()->getValueType(Tmp3.getNode()->getNumValues() - 1) ==
1560 "Lowering call/formal_arguments produced unexpected # results!");
1562 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1563 // remember that we legalized all of them, so it doesn't get relegalized.
1564 for (unsigned i = 0, e = Tmp3.getNode()->getNumValues(); i != e; ++i) {
1565 if (Tmp3.getNode()->getValueType(i) == MVT::Flag)
1567 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1568 if (Op.getResNo() == i)
1570 AddLegalizedOperand(SDValue(Node, i), Tmp1);
1573 case ISD::EXTRACT_SUBREG: {
1574 Tmp1 = LegalizeOp(Node->getOperand(0));
1575 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1576 assert(idx && "Operand must be a constant");
1577 Tmp2 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0));
1578 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1581 case ISD::INSERT_SUBREG: {
1582 Tmp1 = LegalizeOp(Node->getOperand(0));
1583 Tmp2 = LegalizeOp(Node->getOperand(1));
1584 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1585 assert(idx && "Operand must be a constant");
1586 Tmp3 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0));
1587 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1590 case ISD::BUILD_VECTOR:
1591 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1592 default: assert(0 && "This action is not supported yet!");
1593 case TargetLowering::Custom:
1594 Tmp3 = TLI.LowerOperation(Result, DAG);
1595 if (Tmp3.getNode()) {
1600 case TargetLowering::Expand:
1601 Result = ExpandBUILD_VECTOR(Result.getNode());
1605 case ISD::INSERT_VECTOR_ELT:
1606 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1607 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1609 // The type of the value to insert may not be legal, even though the vector
1610 // type is legal. Legalize/Promote accordingly. We do not handle Expand
1612 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1613 default: assert(0 && "Cannot expand insert element operand");
1614 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
1615 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
1617 // FIXME: An alternative would be to check to see if the target is not
1618 // going to custom lower this operation, we could bitcast to half elt
1619 // width and perform two inserts at that width, if that is legal.
1620 Tmp2 = Node->getOperand(1);
1623 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1625 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1626 Node->getValueType(0))) {
1627 default: assert(0 && "This action is not supported yet!");
1628 case TargetLowering::Legal:
1630 case TargetLowering::Custom:
1631 Tmp4 = TLI.LowerOperation(Result, DAG);
1632 if (Tmp4.getNode()) {
1637 case TargetLowering::Promote:
1638 // Fall thru for vector case
1639 case TargetLowering::Expand: {
1640 // If the insert index is a constant, codegen this as a scalar_to_vector,
1641 // then a shuffle that inserts it into the right position in the vector.
1642 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1643 // SCALAR_TO_VECTOR requires that the type of the value being inserted
1644 // match the element type of the vector being created.
1645 if (Tmp2.getValueType() ==
1646 Op.getValueType().getVectorElementType()) {
1647 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
1648 Tmp1.getValueType(), Tmp2);
1650 unsigned NumElts = Tmp1.getValueType().getVectorNumElements();
1652 MVT::getIntVectorWithNumElements(NumElts);
1653 MVT ShufMaskEltVT = ShufMaskVT.getVectorElementType();
1655 // We generate a shuffle of InVec and ScVec, so the shuffle mask
1656 // should be 0,1,2,3,4,5... with the appropriate element replaced with
1657 // elt 0 of the RHS.
1658 SmallVector<SDValue, 8> ShufOps;
1659 for (unsigned i = 0; i != NumElts; ++i) {
1660 if (i != InsertPos->getZExtValue())
1661 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1663 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1665 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, dl, ShufMaskVT,
1666 &ShufOps[0], ShufOps.size());
1668 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, Tmp1.getValueType(),
1669 Tmp1, ScVec, ShufMask);
1670 Result = LegalizeOp(Result);
1674 Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3, dl);
1679 case ISD::SCALAR_TO_VECTOR:
1680 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1681 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1685 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1686 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1687 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1688 Node->getValueType(0))) {
1689 default: assert(0 && "This action is not supported yet!");
1690 case TargetLowering::Legal:
1692 case TargetLowering::Custom:
1693 Tmp3 = TLI.LowerOperation(Result, DAG);
1694 if (Tmp3.getNode()) {
1699 case TargetLowering::Expand:
1700 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1704 case ISD::VECTOR_SHUFFLE:
1705 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1706 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1707 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1709 // Allow targets to custom lower the SHUFFLEs they support.
1710 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1711 default: assert(0 && "Unknown operation action!");
1712 case TargetLowering::Legal:
1713 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1714 "vector shuffle should not be created if not legal!");
1716 case TargetLowering::Custom:
1717 Tmp3 = TLI.LowerOperation(Result, DAG);
1718 if (Tmp3.getNode()) {
1723 case TargetLowering::Expand: {
1724 MVT VT = Node->getValueType(0);
1725 MVT EltVT = VT.getVectorElementType();
1726 MVT PtrVT = TLI.getPointerTy();
1727 SDValue Mask = Node->getOperand(2);
1728 unsigned NumElems = Mask.getNumOperands();
1729 SmallVector<SDValue,8> Ops;
1730 for (unsigned i = 0; i != NumElems; ++i) {
1731 SDValue Arg = Mask.getOperand(i);
1732 if (Arg.getOpcode() == ISD::UNDEF) {
1733 Ops.push_back(DAG.getNode(ISD::UNDEF, dl, EltVT));
1735 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1736 unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
1738 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Tmp1,
1739 DAG.getConstant(Idx, PtrVT)));
1741 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Tmp2,
1742 DAG.getConstant(Idx - NumElems, PtrVT)));
1745 Result = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
1748 case TargetLowering::Promote: {
1749 // Change base type to a different vector type.
1750 MVT OVT = Node->getValueType(0);
1751 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1753 // Cast the two input vectors.
1754 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp1);
1755 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp2);
1757 // Convert the shuffle mask to the right # elements.
1758 Tmp3 = SDValue(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1759 assert(Tmp3.getNode() && "Shuffle not legal?");
1760 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, NVT, Tmp1, Tmp2, Tmp3);
1761 Result = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Result);
1767 case ISD::EXTRACT_VECTOR_ELT:
1768 Tmp1 = Node->getOperand(0);
1769 Tmp2 = LegalizeOp(Node->getOperand(1));
1770 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1771 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1774 case ISD::EXTRACT_SUBVECTOR:
1775 Tmp1 = Node->getOperand(0);
1776 Tmp2 = LegalizeOp(Node->getOperand(1));
1777 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1778 Result = ExpandEXTRACT_SUBVECTOR(Result);
1781 case ISD::CONCAT_VECTORS: {
1782 // Use extract/insert/build vector for now. We might try to be
1783 // more clever later.
1784 MVT PtrVT = TLI.getPointerTy();
1785 SmallVector<SDValue, 8> Ops;
1786 unsigned NumOperands = Node->getNumOperands();
1787 for (unsigned i=0; i < NumOperands; ++i) {
1788 SDValue SubOp = Node->getOperand(i);
1789 MVT VVT = SubOp.getNode()->getValueType(0);
1790 MVT EltVT = VVT.getVectorElementType();
1791 unsigned NumSubElem = VVT.getVectorNumElements();
1792 for (unsigned j=0; j < NumSubElem; ++j) {
1793 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp,
1794 DAG.getConstant(j, PtrVT)));
1797 return LegalizeOp(DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0),
1798 &Ops[0], Ops.size()));
1801 case ISD::CALLSEQ_START: {
1802 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1804 // Recursively Legalize all of the inputs of the call end that do not lead
1805 // to this call start. This ensures that any libcalls that need be inserted
1806 // are inserted *before* the CALLSEQ_START.
1807 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1808 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1809 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
1813 // Now that we legalized all of the inputs (which may have inserted
1814 // libcalls) create the new CALLSEQ_START node.
1815 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1817 // Merge in the last call, to ensure that this call start after the last
1819 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1820 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1821 Tmp1, LastCALLSEQ_END);
1822 Tmp1 = LegalizeOp(Tmp1);
1825 // Do not try to legalize the target-specific arguments (#1+).
1826 if (Tmp1 != Node->getOperand(0)) {
1827 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1829 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1832 // Remember that the CALLSEQ_START is legalized.
1833 AddLegalizedOperand(Op.getValue(0), Result);
1834 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1835 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1837 // Now that the callseq_start and all of the non-call nodes above this call
1838 // sequence have been legalized, legalize the call itself. During this
1839 // process, no libcalls can/will be inserted, guaranteeing that no calls
1841 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1842 // Note that we are selecting this call!
1843 LastCALLSEQ_END = SDValue(CallEnd, 0);
1844 IsLegalizingCall = true;
1846 // Legalize the call, starting from the CALLSEQ_END.
1847 LegalizeOp(LastCALLSEQ_END);
1848 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1851 case ISD::CALLSEQ_END:
1852 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1853 // will cause this node to be legalized as well as handling libcalls right.
1854 if (LastCALLSEQ_END.getNode() != Node) {
1855 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
1856 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1857 assert(I != LegalizedNodes.end() &&
1858 "Legalizing the call start should have legalized this node!");
1862 // Otherwise, the call start has been legalized and everything is going
1863 // according to plan. Just legalize ourselves normally here.
1864 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1865 // Do not try to legalize the target-specific arguments (#1+), except for
1866 // an optional flag input.
1867 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1868 if (Tmp1 != Node->getOperand(0)) {
1869 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1871 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1874 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1875 if (Tmp1 != Node->getOperand(0) ||
1876 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1877 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1880 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1883 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1884 // This finishes up call legalization.
1885 IsLegalizingCall = false;
1887 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1888 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1889 if (Node->getNumValues() == 2)
1890 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1891 return Result.getValue(Op.getResNo());
1892 case ISD::DYNAMIC_STACKALLOC: {
1893 MVT VT = Node->getValueType(0);
1894 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1895 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1896 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1897 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1899 Tmp1 = Result.getValue(0);
1900 Tmp2 = Result.getValue(1);
1901 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1902 default: assert(0 && "This action is not supported yet!");
1903 case TargetLowering::Expand: {
1904 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1905 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1906 " not tell us which reg is the stack pointer!");
1907 SDValue Chain = Tmp1.getOperand(0);
1909 // Chain the dynamic stack allocation so that it doesn't modify the stack
1910 // pointer when other instructions are using the stack.
1911 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1913 SDValue Size = Tmp2.getOperand(1);
1914 SDValue SP = DAG.getCopyFromReg(Chain, SPReg, VT);
1915 Chain = SP.getValue(1);
1916 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1917 unsigned StackAlign =
1918 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1919 if (Align > StackAlign)
1920 SP = DAG.getNode(ISD::AND, dl, VT, SP,
1921 DAG.getConstant(-(uint64_t)Align, VT));
1922 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1923 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
1925 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1926 DAG.getIntPtrConstant(0, true), SDValue());
1928 Tmp1 = LegalizeOp(Tmp1);
1929 Tmp2 = LegalizeOp(Tmp2);
1932 case TargetLowering::Custom:
1933 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1934 if (Tmp3.getNode()) {
1935 Tmp1 = LegalizeOp(Tmp3);
1936 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1939 case TargetLowering::Legal:
1942 // Since this op produce two values, make sure to remember that we
1943 // legalized both of them.
1944 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
1945 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
1946 return Op.getResNo() ? Tmp2 : Tmp1;
1948 case ISD::INLINEASM: {
1949 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1950 bool Changed = false;
1951 // Legalize all of the operands of the inline asm, in case they are nodes
1952 // that need to be expanded or something. Note we skip the asm string and
1953 // all of the TargetConstant flags.
1954 SDValue Op = LegalizeOp(Ops[0]);
1955 Changed = Op != Ops[0];
1958 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1959 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1960 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getZExtValue() >> 3;
1961 for (++i; NumVals; ++i, --NumVals) {
1962 SDValue Op = LegalizeOp(Ops[i]);
1971 Op = LegalizeOp(Ops.back());
1972 Changed |= Op != Ops.back();
1977 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1979 // INLINE asm returns a chain and flag, make sure to add both to the map.
1980 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1981 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1982 return Result.getValue(Op.getResNo());
1985 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1986 // Ensure that libcalls are emitted before a branch.
1987 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
1988 Tmp1 = LegalizeOp(Tmp1);
1989 LastCALLSEQ_END = DAG.getEntryNode();
1991 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1994 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1995 // Ensure that libcalls are emitted before a branch.
1996 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
1997 Tmp1 = LegalizeOp(Tmp1);
1998 LastCALLSEQ_END = DAG.getEntryNode();
2000 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2001 default: assert(0 && "Indirect target must be legal type (pointer)!");
2003 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
2006 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2009 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2010 // Ensure that libcalls are emitted before a branch.
2011 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
2012 Tmp1 = LegalizeOp(Tmp1);
2013 LastCALLSEQ_END = DAG.getEntryNode();
2015 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
2016 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2018 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
2019 default: assert(0 && "This action is not supported yet!");
2020 case TargetLowering::Legal: break;
2021 case TargetLowering::Custom:
2022 Tmp1 = TLI.LowerOperation(Result, DAG);
2023 if (Tmp1.getNode()) Result = Tmp1;
2025 case TargetLowering::Expand: {
2026 SDValue Chain = Result.getOperand(0);
2027 SDValue Table = Result.getOperand(1);
2028 SDValue Index = Result.getOperand(2);
2030 MVT PTy = TLI.getPointerTy();
2031 MachineFunction &MF = DAG.getMachineFunction();
2032 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
2033 Index= DAG.getNode(ISD::MUL, dl, PTy,
2034 Index, DAG.getConstant(EntrySize, PTy));
2035 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2037 MVT MemVT = MVT::getIntegerVT(EntrySize * 8);
2038 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
2039 PseudoSourceValue::getJumpTable(), 0, MemVT);
2041 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2042 // For PIC, the sequence is:
2043 // BRIND(load(Jumptable + index) + RelocBase)
2044 // RelocBase can be JumpTable, GOT or some sort of global base.
2045 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
2046 TLI.getPICJumpTableRelocBase(Table, DAG));
2048 Result = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
2053 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2054 // Ensure that libcalls are emitted before a return.
2055 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
2056 Tmp1 = LegalizeOp(Tmp1);
2057 LastCALLSEQ_END = DAG.getEntryNode();
2059 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2060 case Expand: assert(0 && "It's impossible to expand bools");
2062 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
2065 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
2067 // The top bits of the promoted condition are not necessarily zero, ensure
2068 // that the value is properly zero extended.
2069 unsigned BitWidth = Tmp2.getValueSizeInBits();
2070 if (!DAG.MaskedValueIsZero(Tmp2,
2071 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2072 Tmp2 = DAG.getZeroExtendInReg(Tmp2, dl, MVT::i1);
2077 // Basic block destination (Op#2) is always legal.
2078 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2080 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
2081 default: assert(0 && "This action is not supported yet!");
2082 case TargetLowering::Legal: break;
2083 case TargetLowering::Custom:
2084 Tmp1 = TLI.LowerOperation(Result, DAG);
2085 if (Tmp1.getNode()) Result = Tmp1;
2087 case TargetLowering::Expand:
2088 // Expand brcond's setcc into its constituent parts and create a BR_CC
2090 if (Tmp2.getOpcode() == ISD::SETCC) {
2091 Result = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
2092 Tmp1, Tmp2.getOperand(2),
2093 Tmp2.getOperand(0), Tmp2.getOperand(1),
2094 Node->getOperand(2));
2096 Result = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
2097 DAG.getCondCode(ISD::SETNE), Tmp2,
2098 DAG.getConstant(0, Tmp2.getValueType()),
2099 Node->getOperand(2));
2105 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2106 // Ensure that libcalls are emitted before a branch.
2107 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
2108 Tmp1 = LegalizeOp(Tmp1);
2109 Tmp2 = Node->getOperand(2); // LHS
2110 Tmp3 = Node->getOperand(3); // RHS
2111 Tmp4 = Node->getOperand(1); // CC
2113 LegalizeSetCC(TLI.getSetCCResultType(Tmp2.getValueType()),
2114 Tmp2, Tmp3, Tmp4, dl);
2115 LastCALLSEQ_END = DAG.getEntryNode();
2117 // If we didn't get both a LHS and RHS back from LegalizeSetCC,
2118 // the LHS is a legal SETCC itself. In this case, we need to compare
2119 // the result against zero to select between true and false values.
2120 if (Tmp3.getNode() == 0) {
2121 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
2122 Tmp4 = DAG.getCondCode(ISD::SETNE);
2125 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
2126 Node->getOperand(4));
2128 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
2129 default: assert(0 && "Unexpected action for BR_CC!");
2130 case TargetLowering::Legal: break;
2131 case TargetLowering::Custom:
2132 Tmp4 = TLI.LowerOperation(Result, DAG);
2133 if (Tmp4.getNode()) Result = Tmp4;
2138 LoadSDNode *LD = cast<LoadSDNode>(Node);
2139 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
2140 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
2142 ISD::LoadExtType ExtType = LD->getExtensionType();
2143 if (ExtType == ISD::NON_EXTLOAD) {
2144 MVT VT = Node->getValueType(0);
2145 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2146 Tmp3 = Result.getValue(0);
2147 Tmp4 = Result.getValue(1);
2149 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
2150 default: assert(0 && "This action is not supported yet!");
2151 case TargetLowering::Legal:
2152 // If this is an unaligned load and the target doesn't support it,
2154 if (!TLI.allowsUnalignedMemoryAccesses()) {
2155 unsigned ABIAlignment = TLI.getTargetData()->
2156 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
2157 if (LD->getAlignment() < ABIAlignment){
2158 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
2160 Tmp3 = Result.getOperand(0);
2161 Tmp4 = Result.getOperand(1);
2162 Tmp3 = LegalizeOp(Tmp3);
2163 Tmp4 = LegalizeOp(Tmp4);
2167 case TargetLowering::Custom:
2168 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
2169 if (Tmp1.getNode()) {
2170 Tmp3 = LegalizeOp(Tmp1);
2171 Tmp4 = LegalizeOp(Tmp1.getValue(1));
2174 case TargetLowering::Promote: {
2175 // Only promote a load of vector type to another.
2176 assert(VT.isVector() && "Cannot promote this load!");
2177 // Change base type to a different vector type.
2178 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
2180 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
2181 LD->getSrcValueOffset(),
2182 LD->isVolatile(), LD->getAlignment());
2183 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
2184 Tmp4 = LegalizeOp(Tmp1.getValue(1));
2188 // Since loads produce two values, make sure to remember that we
2189 // legalized both of them.
2190 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
2191 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
2192 return Op.getResNo() ? Tmp4 : Tmp3;
2194 MVT SrcVT = LD->getMemoryVT();
2195 unsigned SrcWidth = SrcVT.getSizeInBits();
2196 int SVOffset = LD->getSrcValueOffset();
2197 unsigned Alignment = LD->getAlignment();
2198 bool isVolatile = LD->isVolatile();
2200 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
2201 // Some targets pretend to have an i1 loading operation, and actually
2202 // load an i8. This trick is correct for ZEXTLOAD because the top 7
2203 // bits are guaranteed to be zero; it helps the optimizers understand
2204 // that these bits are zero. It is also useful for EXTLOAD, since it
2205 // tells the optimizers that those bits are undefined. It would be
2206 // nice to have an effective generic way of getting these benefits...
2207 // Until such a way is found, don't insist on promoting i1 here.
2208 (SrcVT != MVT::i1 ||
2209 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
2210 // Promote to a byte-sized load if not loading an integral number of
2211 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
2212 unsigned NewWidth = SrcVT.getStoreSizeInBits();
2213 MVT NVT = MVT::getIntegerVT(NewWidth);
2216 // The extra bits are guaranteed to be zero, since we stored them that
2217 // way. A zext load from NVT thus automatically gives zext from SrcVT.
2219 ISD::LoadExtType NewExtType =
2220 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
2222 Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
2223 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
2224 NVT, isVolatile, Alignment);
2226 Ch = Result.getValue(1); // The chain.
2228 if (ExtType == ISD::SEXTLOAD)
2229 // Having the top bits zero doesn't help when sign extending.
2230 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
2231 Result.getValueType(),
2232 Result, DAG.getValueType(SrcVT));
2233 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
2234 // All the top bits are guaranteed to be zero - inform the optimizers.
2235 Result = DAG.getNode(ISD::AssertZext, dl,
2236 Result.getValueType(), Result,
2237 DAG.getValueType(SrcVT));
2239 Tmp1 = LegalizeOp(Result);
2240 Tmp2 = LegalizeOp(Ch);
2241 } else if (SrcWidth & (SrcWidth - 1)) {
2242 // If not loading a power-of-2 number of bits, expand as two loads.
2243 assert(SrcVT.isExtended() && !SrcVT.isVector() &&
2244 "Unsupported extload!");
2245 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
2246 assert(RoundWidth < SrcWidth);
2247 unsigned ExtraWidth = SrcWidth - RoundWidth;
2248 assert(ExtraWidth < RoundWidth);
2249 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2250 "Load size not an integral number of bytes!");
2251 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2252 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2254 unsigned IncrementSize;
2256 if (TLI.isLittleEndian()) {
2257 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
2258 // Load the bottom RoundWidth bits.
2259 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl,
2260 Node->getValueType(0), Tmp1, Tmp2,
2261 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2264 // Load the remaining ExtraWidth bits.
2265 IncrementSize = RoundWidth / 8;
2266 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
2267 DAG.getIntPtrConstant(IncrementSize));
2268 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
2269 LD->getSrcValue(), SVOffset + IncrementSize,
2270 ExtraVT, isVolatile,
2271 MinAlign(Alignment, IncrementSize));
2273 // Build a factor node to remember that this load is independent of the
2275 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
2278 // Move the top bits to the right place.
2279 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
2280 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2282 // Join the hi and lo parts.
2283 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
2285 // Big endian - avoid unaligned loads.
2286 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
2287 // Load the top RoundWidth bits.
2288 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
2289 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2292 // Load the remaining ExtraWidth bits.
2293 IncrementSize = RoundWidth / 8;
2294 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
2295 DAG.getIntPtrConstant(IncrementSize));
2296 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl,
2297 Node->getValueType(0), Tmp1, Tmp2,
2298 LD->getSrcValue(), SVOffset + IncrementSize,
2299 ExtraVT, isVolatile,
2300 MinAlign(Alignment, IncrementSize));
2302 // Build a factor node to remember that this load is independent of the
2304 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
2307 // Move the top bits to the right place.
2308 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
2309 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2311 // Join the hi and lo parts.
2312 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
2315 Tmp1 = LegalizeOp(Result);
2316 Tmp2 = LegalizeOp(Ch);
2318 switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
2319 default: assert(0 && "This action is not supported yet!");
2320 case TargetLowering::Custom:
2323 case TargetLowering::Legal:
2324 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2325 Tmp1 = Result.getValue(0);
2326 Tmp2 = Result.getValue(1);
2329 Tmp3 = TLI.LowerOperation(Result, DAG);
2330 if (Tmp3.getNode()) {
2331 Tmp1 = LegalizeOp(Tmp3);
2332 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2335 // If this is an unaligned load and the target doesn't support it,
2337 if (!TLI.allowsUnalignedMemoryAccesses()) {
2338 unsigned ABIAlignment = TLI.getTargetData()->
2339 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
2340 if (LD->getAlignment() < ABIAlignment){
2341 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
2343 Tmp1 = Result.getOperand(0);
2344 Tmp2 = Result.getOperand(1);
2345 Tmp1 = LegalizeOp(Tmp1);
2346 Tmp2 = LegalizeOp(Tmp2);
2351 case TargetLowering::Expand:
2352 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
2353 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
2354 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
2355 LD->getSrcValueOffset(),
2356 LD->isVolatile(), LD->getAlignment());
2357 Result = DAG.getNode(ISD::FP_EXTEND, dl,
2358 Node->getValueType(0), Load);
2359 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
2360 Tmp2 = LegalizeOp(Load.getValue(1));
2363 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
2364 // Turn the unsupported load into an EXTLOAD followed by an explicit
2365 // zero/sign extend inreg.
2366 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
2367 Tmp1, Tmp2, LD->getSrcValue(),
2368 LD->getSrcValueOffset(), SrcVT,
2369 LD->isVolatile(), LD->getAlignment());
2371 if (ExtType == ISD::SEXTLOAD)
2372 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
2373 Result.getValueType(),
2374 Result, DAG.getValueType(SrcVT));
2376 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT);
2377 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
2378 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
2383 // Since loads produce two values, make sure to remember that we legalized
2385 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2386 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2387 return Op.getResNo() ? Tmp2 : Tmp1;
2390 case ISD::EXTRACT_ELEMENT: {
2391 MVT OpTy = Node->getOperand(0).getValueType();
2392 switch (getTypeAction(OpTy)) {
2393 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
2395 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
2397 Result = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
2398 DAG.getConstant(OpTy.getSizeInBits()/2,
2399 TLI.getShiftAmountTy()));
2400 Result = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Result);
2403 Result = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
2404 Node->getOperand(0));
2408 // Get both the low and high parts.
2409 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2410 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
2411 Result = Tmp2; // 1 -> Hi
2413 Result = Tmp1; // 0 -> Lo
2419 case ISD::CopyToReg:
2420 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2422 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
2423 "Register type must be legal!");
2424 // Legalize the incoming value (must be a legal type).
2425 Tmp2 = LegalizeOp(Node->getOperand(2));
2426 if (Node->getNumValues() == 1) {
2427 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
2429 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
2430 if (Node->getNumOperands() == 4) {
2431 Tmp3 = LegalizeOp(Node->getOperand(3));
2432 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
2435 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
2438 // Since this produces two values, make sure to remember that we legalized
2440 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
2441 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
2447 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2449 // Ensure that libcalls are emitted before a return.
2450 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
2451 Tmp1 = LegalizeOp(Tmp1);
2452 LastCALLSEQ_END = DAG.getEntryNode();
2454 switch (Node->getNumOperands()) {
2456 Tmp2 = Node->getOperand(1);
2457 Tmp3 = Node->getOperand(2); // Signness
2458 switch (getTypeAction(Tmp2.getValueType())) {
2460 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
2463 if (!Tmp2.getValueType().isVector()) {
2465 ExpandOp(Tmp2, Lo, Hi);
2467 // Big endian systems want the hi reg first.
2468 if (TLI.isBigEndian())
2472 Result = DAG.getNode(ISD::RET, dl, MVT::Other,
2473 Tmp1, Lo, Tmp3, Hi,Tmp3);
2475 Result = DAG.getNode(ISD::RET, dl, MVT::Other, Tmp1, Lo, Tmp3);
2476 Result = LegalizeOp(Result);
2478 SDNode *InVal = Tmp2.getNode();
2479 int InIx = Tmp2.getResNo();
2480 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
2481 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
2483 // Figure out if there is a simple type corresponding to this Vector
2484 // type. If so, convert to the vector type.
2485 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2486 if (TLI.isTypeLegal(TVT)) {
2487 // Turn this into a return of the vector type.
2488 Tmp2 = LegalizeOp(Tmp2);
2489 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2490 } else if (NumElems == 1) {
2491 // Turn this into a return of the scalar type.
2492 Tmp2 = ScalarizeVectorOp(Tmp2);
2493 Tmp2 = LegalizeOp(Tmp2);
2494 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2496 // FIXME: Returns of gcc generic vectors smaller than a legal type
2497 // should be returned in integer registers!
2499 // The scalarized value type may not be legal, e.g. it might require
2500 // promotion or expansion. Relegalize the return.
2501 Result = LegalizeOp(Result);
2503 // FIXME: Returns of gcc generic vectors larger than a legal vector
2504 // type should be returned by reference!
2506 SplitVectorOp(Tmp2, Lo, Hi);
2507 Result = DAG.getNode(ISD::RET, dl, MVT::Other,
2508 Tmp1, Lo, Tmp3, Hi,Tmp3);
2509 Result = LegalizeOp(Result);
2514 Tmp2 = PromoteOp(Node->getOperand(1));
2515 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2516 Result = LegalizeOp(Result);
2521 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2523 default: { // ret <values>
2524 SmallVector<SDValue, 8> NewValues;
2525 NewValues.push_back(Tmp1);
2526 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
2527 switch (getTypeAction(Node->getOperand(i).getValueType())) {
2529 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
2530 NewValues.push_back(Node->getOperand(i+1));
2534 assert(!Node->getOperand(i).getValueType().isExtended() &&
2535 "FIXME: TODO: implement returning non-legal vector types!");
2536 ExpandOp(Node->getOperand(i), Lo, Hi);
2537 NewValues.push_back(Lo);
2538 NewValues.push_back(Node->getOperand(i+1));
2540 NewValues.push_back(Hi);
2541 NewValues.push_back(Node->getOperand(i+1));
2546 assert(0 && "Can't promote multiple return value yet!");
2549 if (NewValues.size() == Node->getNumOperands())
2550 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
2552 Result = DAG.getNode(ISD::RET, dl, MVT::Other,
2553 &NewValues[0], NewValues.size());
2558 if (Result.getOpcode() == ISD::RET) {
2559 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
2560 default: assert(0 && "This action is not supported yet!");
2561 case TargetLowering::Legal: break;
2562 case TargetLowering::Custom:
2563 Tmp1 = TLI.LowerOperation(Result, DAG);
2564 if (Tmp1.getNode()) Result = Tmp1;
2570 StoreSDNode *ST = cast<StoreSDNode>(Node);
2571 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
2572 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
2573 int SVOffset = ST->getSrcValueOffset();
2574 unsigned Alignment = ST->getAlignment();
2575 bool isVolatile = ST->isVolatile();
2577 if (!ST->isTruncatingStore()) {
2578 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
2579 // FIXME: We shouldn't do this for TargetConstantFP's.
2580 // FIXME: move this to the DAG Combiner! Note that we can't regress due
2581 // to phase ordering between legalized code and the dag combiner. This
2582 // probably means that we need to integrate dag combiner and legalizer
2584 // We generally can't do this one for long doubles.
2585 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
2586 if (CFP->getValueType(0) == MVT::f32 &&
2587 getTypeAction(MVT::i32) == Legal) {
2588 Tmp3 = DAG.getConstant(CFP->getValueAPF().
2589 bitcastToAPInt().zextOrTrunc(32),
2591 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2592 SVOffset, isVolatile, Alignment);
2594 } else if (CFP->getValueType(0) == MVT::f64) {
2595 // If this target supports 64-bit registers, do a single 64-bit store.
2596 if (getTypeAction(MVT::i64) == Legal) {
2597 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
2598 zextOrTrunc(64), MVT::i64);
2599 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2600 SVOffset, isVolatile, Alignment);
2602 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
2603 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
2604 // stores. If the target supports neither 32- nor 64-bits, this
2605 // xform is certainly not worth it.
2606 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
2607 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
2608 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
2609 if (TLI.isBigEndian()) std::swap(Lo, Hi);
2611 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(),
2612 SVOffset, isVolatile, Alignment);
2613 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
2614 DAG.getIntPtrConstant(4));
2615 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
2616 isVolatile, MinAlign(Alignment, 4U));
2618 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2624 switch (getTypeAction(ST->getMemoryVT())) {
2626 Tmp3 = LegalizeOp(ST->getValue());
2627 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2630 MVT VT = Tmp3.getValueType();
2631 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2632 default: assert(0 && "This action is not supported yet!");
2633 case TargetLowering::Legal:
2634 // If this is an unaligned store and the target doesn't support it,
2636 if (!TLI.allowsUnalignedMemoryAccesses()) {
2637 unsigned ABIAlignment = TLI.getTargetData()->
2638 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2639 if (ST->getAlignment() < ABIAlignment)
2640 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
2644 case TargetLowering::Custom:
2645 Tmp1 = TLI.LowerOperation(Result, DAG);
2646 if (Tmp1.getNode()) Result = Tmp1;
2648 case TargetLowering::Promote:
2649 assert(VT.isVector() && "Unknown legal promote case!");
2650 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, dl,
2651 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2652 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2,
2653 ST->getSrcValue(), SVOffset, isVolatile,
2660 if (!ST->getMemoryVT().isVector()) {
2661 // Truncate the value and store the result.
2662 Tmp3 = PromoteOp(ST->getValue());
2663 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2664 SVOffset, ST->getMemoryVT(),
2665 isVolatile, Alignment);
2668 // Fall thru to expand for vector
2670 unsigned IncrementSize = 0;
2673 // If this is a vector type, then we have to calculate the increment as
2674 // the product of the element size in bytes, and the number of elements
2675 // in the high half of the vector.
2676 if (ST->getValue().getValueType().isVector()) {
2677 SDNode *InVal = ST->getValue().getNode();
2678 int InIx = ST->getValue().getResNo();
2679 MVT InVT = InVal->getValueType(InIx);
2680 unsigned NumElems = InVT.getVectorNumElements();
2681 MVT EVT = InVT.getVectorElementType();
2683 // Figure out if there is a simple type corresponding to this Vector
2684 // type. If so, convert to the vector type.
2685 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2686 if (TLI.isTypeLegal(TVT)) {
2687 // Turn this into a normal store of the vector type.
2688 Tmp3 = LegalizeOp(ST->getValue());
2689 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2690 SVOffset, isVolatile, Alignment);
2691 Result = LegalizeOp(Result);
2693 } else if (NumElems == 1) {
2694 // Turn this into a normal store of the scalar type.
2695 Tmp3 = ScalarizeVectorOp(ST->getValue());
2696 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2697 SVOffset, isVolatile, Alignment);
2698 // The scalarized value type may not be legal, e.g. it might require
2699 // promotion or expansion. Relegalize the scalar store.
2700 Result = LegalizeOp(Result);
2703 // Check if we have widen this node with another value
2704 std::map<SDValue, SDValue>::iterator I =
2705 WidenNodes.find(ST->getValue());
2706 if (I != WidenNodes.end()) {
2707 Result = StoreWidenVectorOp(ST, Tmp1, Tmp2);
2711 SplitVectorOp(ST->getValue(), Lo, Hi);
2712 IncrementSize = Lo.getNode()->getValueType(0).getVectorNumElements() *
2713 EVT.getSizeInBits()/8;
2717 ExpandOp(ST->getValue(), Lo, Hi);
2718 IncrementSize = Hi.getNode() ? Hi.getValueType().getSizeInBits()/8 : 0;
2720 if (Hi.getNode() && TLI.isBigEndian())
2724 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(),
2725 SVOffset, isVolatile, Alignment);
2727 if (Hi.getNode() == NULL) {
2728 // Must be int <-> float one-to-one expansion.
2733 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
2734 DAG.getIntPtrConstant(IncrementSize));
2735 assert(isTypeLegal(Tmp2.getValueType()) &&
2736 "Pointers must be legal!");
2737 SVOffset += IncrementSize;
2738 Alignment = MinAlign(Alignment, IncrementSize);
2739 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
2740 SVOffset, isVolatile, Alignment);
2741 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2746 switch (getTypeAction(ST->getValue().getValueType())) {
2748 Tmp3 = LegalizeOp(ST->getValue());
2751 if (!ST->getValue().getValueType().isVector()) {
2752 // We can promote the value, the truncstore will still take care of it.
2753 Tmp3 = PromoteOp(ST->getValue());
2756 // Vector case falls through to expand
2758 // Just store the low part. This may become a non-trunc store, so make
2759 // sure to use getTruncStore, not UpdateNodeOperands below.
2760 ExpandOp(ST->getValue(), Tmp3, Tmp4);
2761 return DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2762 SVOffset, MVT::i8, isVolatile, Alignment);
2765 MVT StVT = ST->getMemoryVT();
2766 unsigned StWidth = StVT.getSizeInBits();
2768 if (StWidth != StVT.getStoreSizeInBits()) {
2769 // Promote to a byte-sized store with upper bits zero if not
2770 // storing an integral number of bytes. For example, promote
2771 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
2772 MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits());
2773 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT);
2774 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2775 SVOffset, NVT, isVolatile, Alignment);
2776 } else if (StWidth & (StWidth - 1)) {
2777 // If not storing a power-of-2 number of bits, expand as two stores.
2778 assert(StVT.isExtended() && !StVT.isVector() &&
2779 "Unsupported truncstore!");
2780 unsigned RoundWidth = 1 << Log2_32(StWidth);
2781 assert(RoundWidth < StWidth);
2782 unsigned ExtraWidth = StWidth - RoundWidth;
2783 assert(ExtraWidth < RoundWidth);
2784 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2785 "Store size not an integral number of bytes!");
2786 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2787 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2789 unsigned IncrementSize;
2791 if (TLI.isLittleEndian()) {
2792 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
2793 // Store the bottom RoundWidth bits.
2794 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2796 isVolatile, Alignment);
2798 // Store the remaining ExtraWidth bits.
2799 IncrementSize = RoundWidth / 8;
2800 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
2801 DAG.getIntPtrConstant(IncrementSize));
2802 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
2803 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2804 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
2805 SVOffset + IncrementSize, ExtraVT, isVolatile,
2806 MinAlign(Alignment, IncrementSize));
2808 // Big endian - avoid unaligned stores.
2809 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
2810 // Store the top RoundWidth bits.
2811 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
2812 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2813 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
2814 SVOffset, RoundVT, isVolatile, Alignment);
2816 // Store the remaining ExtraWidth bits.
2817 IncrementSize = RoundWidth / 8;
2818 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
2819 DAG.getIntPtrConstant(IncrementSize));
2820 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2821 SVOffset + IncrementSize, ExtraVT, isVolatile,
2822 MinAlign(Alignment, IncrementSize));
2825 // The order of the stores doesn't matter.
2826 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2828 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2829 Tmp2 != ST->getBasePtr())
2830 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2833 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
2834 default: assert(0 && "This action is not supported yet!");
2835 case TargetLowering::Legal:
2836 // If this is an unaligned store and the target doesn't support it,
2838 if (!TLI.allowsUnalignedMemoryAccesses()) {
2839 unsigned ABIAlignment = TLI.getTargetData()->
2840 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2841 if (ST->getAlignment() < ABIAlignment)
2842 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
2846 case TargetLowering::Custom:
2847 Result = TLI.LowerOperation(Result, DAG);
2850 // TRUNCSTORE:i16 i32 -> STORE i16
2851 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
2852 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3);
2853 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2854 SVOffset, isVolatile, Alignment);
2862 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2863 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2865 case ISD::STACKSAVE:
2866 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2867 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2868 Tmp1 = Result.getValue(0);
2869 Tmp2 = Result.getValue(1);
2871 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2872 default: assert(0 && "This action is not supported yet!");
2873 case TargetLowering::Legal: break;
2874 case TargetLowering::Custom:
2875 Tmp3 = TLI.LowerOperation(Result, DAG);
2876 if (Tmp3.getNode()) {
2877 Tmp1 = LegalizeOp(Tmp3);
2878 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2881 case TargetLowering::Expand:
2882 // Expand to CopyFromReg if the target set
2883 // StackPointerRegisterToSaveRestore.
2884 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2885 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
2886 Node->getValueType(0));
2887 Tmp2 = Tmp1.getValue(1);
2889 Tmp1 = DAG.getNode(ISD::UNDEF, dl, Node->getValueType(0));
2890 Tmp2 = Node->getOperand(0);
2895 // Since stacksave produce two values, make sure to remember that we
2896 // legalized both of them.
2897 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2898 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2899 return Op.getResNo() ? Tmp2 : Tmp1;
2901 case ISD::STACKRESTORE:
2902 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2903 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2904 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2906 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2907 default: assert(0 && "This action is not supported yet!");
2908 case TargetLowering::Legal: break;
2909 case TargetLowering::Custom:
2910 Tmp1 = TLI.LowerOperation(Result, DAG);
2911 if (Tmp1.getNode()) Result = Tmp1;
2913 case TargetLowering::Expand:
2914 // Expand to CopyToReg if the target set
2915 // StackPointerRegisterToSaveRestore.
2916 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2917 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
2925 case ISD::READCYCLECOUNTER:
2926 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2927 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2928 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2929 Node->getValueType(0))) {
2930 default: assert(0 && "This action is not supported yet!");
2931 case TargetLowering::Legal:
2932 Tmp1 = Result.getValue(0);
2933 Tmp2 = Result.getValue(1);
2935 case TargetLowering::Custom:
2936 Result = TLI.LowerOperation(Result, DAG);
2937 Tmp1 = LegalizeOp(Result.getValue(0));
2938 Tmp2 = LegalizeOp(Result.getValue(1));
2942 // Since rdcc produce two values, make sure to remember that we legalized
2944 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2945 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2949 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2950 case Expand: assert(0 && "It's impossible to expand bools");
2952 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2955 assert(!Node->getOperand(0).getValueType().isVector() && "not possible");
2956 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2957 // Make sure the condition is either zero or one.
2958 unsigned BitWidth = Tmp1.getValueSizeInBits();
2959 if (!DAG.MaskedValueIsZero(Tmp1,
2960 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2961 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, MVT::i1);
2965 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2966 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2968 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2970 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2971 default: assert(0 && "This action is not supported yet!");
2972 case TargetLowering::Legal: break;
2973 case TargetLowering::Custom: {
2974 Tmp1 = TLI.LowerOperation(Result, DAG);
2975 if (Tmp1.getNode()) Result = Tmp1;
2978 case TargetLowering::Expand:
2979 if (Tmp1.getOpcode() == ISD::SETCC) {
2980 Result = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
2982 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2984 Result = DAG.getSelectCC(dl, Tmp1,
2985 DAG.getConstant(0, Tmp1.getValueType()),
2986 Tmp2, Tmp3, ISD::SETNE);
2989 case TargetLowering::Promote: {
2991 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2992 unsigned ExtOp, TruncOp;
2993 if (Tmp2.getValueType().isVector()) {
2994 ExtOp = ISD::BIT_CONVERT;
2995 TruncOp = ISD::BIT_CONVERT;
2996 } else if (Tmp2.getValueType().isInteger()) {
2997 ExtOp = ISD::ANY_EXTEND;
2998 TruncOp = ISD::TRUNCATE;
3000 ExtOp = ISD::FP_EXTEND;
3001 TruncOp = ISD::FP_ROUND;
3003 // Promote each of the values to the new type.
3004 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Tmp2);
3005 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Tmp3);
3006 // Perform the larger operation, then round down.
3007 Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2,Tmp3);
3008 if (TruncOp != ISD::FP_ROUND)
3009 Result = DAG.getNode(TruncOp, dl, Node->getValueType(0), Result);
3011 Result = DAG.getNode(TruncOp, dl, Node->getValueType(0), Result,
3012 DAG.getIntPtrConstant(0));
3017 case ISD::SELECT_CC: {
3018 Tmp1 = Node->getOperand(0); // LHS
3019 Tmp2 = Node->getOperand(1); // RHS
3020 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
3021 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
3022 SDValue CC = Node->getOperand(4);
3024 LegalizeSetCC(TLI.getSetCCResultType(Tmp1.getValueType()),
3025 Tmp1, Tmp2, CC, dl);
3027 // If we didn't get both a LHS and RHS back from LegalizeSetCC,
3028 // the LHS is a legal SETCC itself. In this case, we need to compare
3029 // the result against zero to select between true and false values.
3030 if (Tmp2.getNode() == 0) {
3031 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3032 CC = DAG.getCondCode(ISD::SETNE);
3034 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
3036 // Everything is legal, see if we should expand this op or something.
3037 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
3038 default: assert(0 && "This action is not supported yet!");
3039 case TargetLowering::Legal: break;
3040 case TargetLowering::Custom:
3041 Tmp1 = TLI.LowerOperation(Result, DAG);
3042 if (Tmp1.getNode()) Result = Tmp1;
3048 Tmp1 = Node->getOperand(0);
3049 Tmp2 = Node->getOperand(1);
3050 Tmp3 = Node->getOperand(2);
3051 LegalizeSetCC(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl);
3053 // If we had to Expand the SetCC operands into a SELECT node, then it may
3054 // not always be possible to return a true LHS & RHS. In this case, just
3055 // return the value we legalized, returned in the LHS
3056 if (Tmp2.getNode() == 0) {
3061 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
3062 default: assert(0 && "Cannot handle this action for SETCC yet!");
3063 case TargetLowering::Custom:
3066 case TargetLowering::Legal:
3067 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3069 Tmp4 = TLI.LowerOperation(Result, DAG);
3070 if (Tmp4.getNode()) Result = Tmp4;
3073 case TargetLowering::Promote: {
3074 // First step, figure out the appropriate operation to use.
3075 // Allow SETCC to not be supported for all legal data types
3076 // Mostly this targets FP
3077 MVT NewInTy = Node->getOperand(0).getValueType();
3078 MVT OldVT = NewInTy; OldVT = OldVT;
3080 // Scan for the appropriate larger type to use.
3082 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
3084 assert(NewInTy.isInteger() == OldVT.isInteger() &&
3085 "Fell off of the edge of the integer world");
3086 assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() &&
3087 "Fell off of the edge of the floating point world");
3089 // If the target supports SETCC of this type, use it.
3090 if (TLI.isOperationLegalOrCustom(ISD::SETCC, NewInTy))
3093 if (NewInTy.isInteger())
3094 assert(0 && "Cannot promote Legal Integer SETCC yet");
3096 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NewInTy, Tmp1);
3097 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NewInTy, Tmp2);
3099 Tmp1 = LegalizeOp(Tmp1);
3100 Tmp2 = LegalizeOp(Tmp2);
3101 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3102 Result = LegalizeOp(Result);
3105 case TargetLowering::Expand:
3106 // Expand a setcc node into a select_cc of the same condition, lhs, and
3107 // rhs that selects between const 1 (true) and const 0 (false).
3108 MVT VT = Node->getValueType(0);
3109 Result = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3110 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3116 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3117 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3118 SDValue CC = Node->getOperand(2);
3120 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, CC);
3122 // Everything is legal, see if we should expand this op or something.
3123 switch (TLI.getOperationAction(ISD::VSETCC, Tmp1.getValueType())) {
3124 default: assert(0 && "This action is not supported yet!");
3125 case TargetLowering::Legal: break;
3126 case TargetLowering::Custom:
3127 Tmp1 = TLI.LowerOperation(Result, DAG);
3128 if (Tmp1.getNode()) Result = Tmp1;
3130 case TargetLowering::Expand: {
3131 // Unroll into a nasty set of scalar code for now.
3132 MVT VT = Node->getValueType(0);
3133 unsigned NumElems = VT.getVectorNumElements();
3134 MVT EltVT = VT.getVectorElementType();
3135 MVT TmpEltVT = Tmp1.getValueType().getVectorElementType();
3136 SmallVector<SDValue, 8> Ops(NumElems);
3137 for (unsigned i = 0; i < NumElems; ++i) {
3138 SDValue In1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT,
3139 Tmp1, DAG.getIntPtrConstant(i));
3140 Ops[i] = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(TmpEltVT),
3141 In1, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3143 DAG.getIntPtrConstant(i)),
3145 Ops[i] = DAG.getNode(ISD::SELECT, dl, EltVT, Ops[i], DAG.getConstant(
3146 APInt::getAllOnesValue(EltVT.getSizeInBits()),
3147 EltVT), DAG.getConstant(0, EltVT));
3149 Result = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElems);
3156 case ISD::SHL_PARTS:
3157 case ISD::SRA_PARTS:
3158 case ISD::SRL_PARTS: {
3159 SmallVector<SDValue, 8> Ops;
3160 bool Changed = false;
3161 unsigned N = Node->getNumOperands();
3162 for (unsigned i = 0; i + 1 < N; ++i) {
3163 Ops.push_back(LegalizeOp(Node->getOperand(i)));
3164 Changed |= Ops.back() != Node->getOperand(i);
3166 Ops.push_back(LegalizeOp(DAG.getShiftAmountOperand(Node->getOperand(N-1))));
3167 Changed |= Ops.back() != Node->getOperand(N-1);
3169 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
3171 switch (TLI.getOperationAction(Node->getOpcode(),
3172 Node->getValueType(0))) {
3173 default: assert(0 && "This action is not supported yet!");
3174 case TargetLowering::Legal: break;
3175 case TargetLowering::Custom:
3176 Tmp1 = TLI.LowerOperation(Result, DAG);
3177 if (Tmp1.getNode()) {
3178 SDValue Tmp2, RetVal(0, 0);
3179 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
3180 Tmp2 = LegalizeOp(Tmp1.getValue(i));
3181 AddLegalizedOperand(SDValue(Node, i), Tmp2);
3182 if (i == Op.getResNo())
3185 assert(RetVal.getNode() && "Illegal result number");
3191 // Since these produce multiple values, make sure to remember that we
3192 // legalized all of them.
3193 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
3194 AddLegalizedOperand(SDValue(Node, i), Result.getValue(i));
3195 return Result.getValue(Op.getResNo());
3217 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3218 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3220 if ((Node->getOpcode() == ISD::SHL ||
3221 Node->getOpcode() == ISD::SRL ||
3222 Node->getOpcode() == ISD::SRA) &&
3223 !Node->getValueType(0).isVector())
3224 Tmp2 = DAG.getShiftAmountOperand(Tmp2);
3226 switch (getTypeAction(Tmp2.getValueType())) {
3227 case Expand: assert(0 && "Not possible");
3229 Tmp2 = LegalizeOp(Tmp2); // Legalize the RHS.
3232 Tmp2 = PromoteOp(Tmp2); // Promote the RHS.
3236 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3238 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3239 default: assert(0 && "BinOp legalize operation not supported");
3240 case TargetLowering::Legal: break;
3241 case TargetLowering::Custom:
3242 Tmp1 = TLI.LowerOperation(Result, DAG);
3243 if (Tmp1.getNode()) {
3247 // Fall through if the custom lower can't deal with the operation
3248 case TargetLowering::Expand: {
3249 MVT VT = Op.getValueType();
3251 // See if multiply or divide can be lowered using two-result operations.
3252 SDVTList VTs = DAG.getVTList(VT, VT);
3253 if (Node->getOpcode() == ISD::MUL) {
3254 // We just need the low half of the multiply; try both the signed
3255 // and unsigned forms. If the target supports both SMUL_LOHI and
3256 // UMUL_LOHI, form a preference by checking which forms of plain
3257 // MULH it supports.
3258 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3259 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3260 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3261 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3262 unsigned OpToUse = 0;
3263 if (HasSMUL_LOHI && !HasMULHS) {
3264 OpToUse = ISD::SMUL_LOHI;
3265 } else if (HasUMUL_LOHI && !HasMULHU) {
3266 OpToUse = ISD::UMUL_LOHI;
3267 } else if (HasSMUL_LOHI) {
3268 OpToUse = ISD::SMUL_LOHI;
3269 } else if (HasUMUL_LOHI) {
3270 OpToUse = ISD::UMUL_LOHI;
3273 Result = SDValue(DAG.getNode(OpToUse, dl, VTs, Tmp1, Tmp2).getNode(),
3278 if (Node->getOpcode() == ISD::MULHS &&
3279 TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) {
3280 Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl,
3281 VTs, Tmp1, Tmp2).getNode(),
3285 if (Node->getOpcode() == ISD::MULHU &&
3286 TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) {
3287 Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl,
3288 VTs, Tmp1, Tmp2).getNode(),
3292 if (Node->getOpcode() == ISD::SDIV &&
3293 TLI.isOperationLegalOrCustom(ISD::SDIVREM, VT)) {
3294 Result = SDValue(DAG.getNode(ISD::SDIVREM, dl,
3295 VTs, Tmp1, Tmp2).getNode(),
3299 if (Node->getOpcode() == ISD::UDIV &&
3300 TLI.isOperationLegalOrCustom(ISD::UDIVREM, VT)) {
3301 Result = SDValue(DAG.getNode(ISD::UDIVREM, dl,
3302 VTs, Tmp1, Tmp2).getNode(),
3307 // Check to see if we have a libcall for this operator.
3308 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3309 bool isSigned = false;
3310 switch (Node->getOpcode()) {
3313 if (VT == MVT::i32) {
3314 LC = Node->getOpcode() == ISD::UDIV
3315 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
3316 isSigned = Node->getOpcode() == ISD::SDIV;
3321 LC = RTLIB::MUL_I32;
3322 else if (VT == MVT::i64)
3323 LC = RTLIB::MUL_I64;
3326 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
3327 RTLIB::POW_PPCF128);
3330 LC = GetFPLibCall(VT, RTLIB::DIV_F32, RTLIB::DIV_F64, RTLIB::DIV_F80,
3331 RTLIB::DIV_PPCF128);
3335 if (LC != RTLIB::UNKNOWN_LIBCALL) {
3337 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3341 assert(Node->getValueType(0).isVector() &&
3342 "Cannot expand this binary operator!");
3343 // Expand the operation into a bunch of nasty scalar code.
3344 Result = LegalizeOp(UnrollVectorOp(Op));
3347 case TargetLowering::Promote: {
3348 switch (Node->getOpcode()) {
3349 default: assert(0 && "Do not know how to promote this BinOp!");
3353 MVT OVT = Node->getValueType(0);
3354 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3355 assert(OVT.isVector() && "Cannot promote this BinOp!");
3356 // Bit convert each of the values to the new type.
3357 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp1);
3358 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp2);
3359 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3360 // Bit convert the result back the original type.
3361 Result = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Result);
3369 case ISD::SMUL_LOHI:
3370 case ISD::UMUL_LOHI:
3373 // These nodes will only be produced by target-specific lowering, so
3374 // they shouldn't be here if they aren't legal.
3375 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
3376 "This must be legal!");
3378 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3379 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3380 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3383 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
3384 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3385 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3386 case Expand: assert(0 && "Not possible");
3388 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3391 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3395 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3397 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3398 default: assert(0 && "Operation not supported");
3399 case TargetLowering::Custom:
3400 Tmp1 = TLI.LowerOperation(Result, DAG);
3401 if (Tmp1.getNode()) Result = Tmp1;
3403 case TargetLowering::Legal: break;
3404 case TargetLowering::Expand: {
3405 // If this target supports fabs/fneg natively and select is cheap,
3406 // do this efficiently.
3407 if (!TLI.isSelectExpensive() &&
3408 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
3409 TargetLowering::Legal &&
3410 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
3411 TargetLowering::Legal) {
3412 // Get the sign bit of the RHS.
3414 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
3415 SDValue SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, IVT, Tmp2);
3416 SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(IVT),
3417 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
3418 // Get the absolute value of the result.
3419 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
3420 // Select between the nabs and abs value based on the sign bit of
3422 Result = DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit,
3423 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
3426 Result = LegalizeOp(Result);
3430 // Otherwise, do bitwise ops!
3432 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
3433 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
3434 Result = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0), Result);
3435 Result = LegalizeOp(Result);
3443 Tmp1 = LegalizeOp(Node->getOperand(0));
3444 Tmp2 = LegalizeOp(Node->getOperand(1));
3445 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3446 Tmp3 = Result.getValue(0);
3447 Tmp4 = Result.getValue(1);
3449 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3450 default: assert(0 && "This action is not supported yet!");
3451 case TargetLowering::Legal:
3453 case TargetLowering::Custom:
3454 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
3455 if (Tmp1.getNode() != NULL) {
3456 Tmp3 = LegalizeOp(Tmp1);
3457 Tmp4 = LegalizeOp(Tmp1.getValue(1));
3461 // Since this produces two values, make sure to remember that we legalized
3463 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
3464 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
3465 return Op.getResNo() ? Tmp4 : Tmp3;
3469 Tmp1 = LegalizeOp(Node->getOperand(0));
3470 Tmp2 = LegalizeOp(Node->getOperand(1));
3471 Tmp3 = LegalizeOp(Node->getOperand(2));
3472 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3473 Tmp3 = Result.getValue(0);
3474 Tmp4 = Result.getValue(1);
3476 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3477 default: assert(0 && "This action is not supported yet!");
3478 case TargetLowering::Legal:
3480 case TargetLowering::Custom:
3481 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
3482 if (Tmp1.getNode() != NULL) {
3483 Tmp3 = LegalizeOp(Tmp1);
3484 Tmp4 = LegalizeOp(Tmp1.getValue(1));
3488 // Since this produces two values, make sure to remember that we legalized
3490 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
3491 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
3492 return Op.getResNo() ? Tmp4 : Tmp3;
3494 case ISD::BUILD_PAIR: {
3495 MVT PairTy = Node->getValueType(0);
3496 // TODO: handle the case where the Lo and Hi operands are not of legal type
3497 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
3498 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
3499 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
3500 case TargetLowering::Promote:
3501 case TargetLowering::Custom:
3502 assert(0 && "Cannot promote/custom this yet!");
3503 case TargetLowering::Legal:
3504 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
3505 Result = DAG.getNode(ISD::BUILD_PAIR, dl, PairTy, Tmp1, Tmp2);
3507 case TargetLowering::Expand:
3508 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Tmp1);
3509 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Tmp2);
3510 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
3511 DAG.getConstant(PairTy.getSizeInBits()/2,
3512 TLI.getShiftAmountTy()));
3513 Result = DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2);
3522 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3523 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3525 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3526 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
3527 case TargetLowering::Custom:
3530 case TargetLowering::Legal:
3531 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3533 Tmp1 = TLI.LowerOperation(Result, DAG);
3534 if (Tmp1.getNode()) Result = Tmp1;
3537 case TargetLowering::Expand: {
3538 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
3539 bool isSigned = DivOpc == ISD::SDIV;
3540 MVT VT = Node->getValueType(0);
3542 // See if remainder can be lowered using two-result operations.
3543 SDVTList VTs = DAG.getVTList(VT, VT);
3544 if (Node->getOpcode() == ISD::SREM &&
3545 TLI.isOperationLegalOrCustom(ISD::SDIVREM, VT)) {
3546 Result = SDValue(DAG.getNode(ISD::SDIVREM, dl,
3547 VTs, Tmp1, Tmp2).getNode(), 1);
3550 if (Node->getOpcode() == ISD::UREM &&
3551 TLI.isOperationLegalOrCustom(ISD::UDIVREM, VT)) {
3552 Result = SDValue(DAG.getNode(ISD::UDIVREM, dl,
3553 VTs, Tmp1, Tmp2).getNode(), 1);
3557 if (VT.isInteger()) {
3558 if (TLI.getOperationAction(DivOpc, VT) ==
3559 TargetLowering::Legal) {
3561 Result = DAG.getNode(DivOpc, dl, VT, Tmp1, Tmp2);
3562 Result = DAG.getNode(ISD::MUL, dl, VT, Result, Tmp2);
3563 Result = DAG.getNode(ISD::SUB, dl, VT, Tmp1, Result);
3564 } else if (VT.isVector()) {
3565 Result = LegalizeOp(UnrollVectorOp(Op));
3567 assert(VT == MVT::i32 &&
3568 "Cannot expand this binary operator!");
3569 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
3570 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
3572 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3575 assert(VT.isFloatingPoint() &&
3576 "remainder op must have integer or floating-point type");
3577 if (VT.isVector()) {
3578 Result = LegalizeOp(UnrollVectorOp(Op));
3580 // Floating point mod -> fmod libcall.
3581 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
3582 RTLIB::REM_F80, RTLIB::REM_PPCF128);
3584 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3592 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3593 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3595 MVT VT = Node->getValueType(0);
3596 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
3597 default: assert(0 && "This action is not supported yet!");
3598 case TargetLowering::Custom:
3601 case TargetLowering::Legal:
3602 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3603 Result = Result.getValue(0);
3604 Tmp1 = Result.getValue(1);
3607 Tmp2 = TLI.LowerOperation(Result, DAG);
3608 if (Tmp2.getNode()) {
3609 Result = LegalizeOp(Tmp2);
3610 Tmp1 = LegalizeOp(Tmp2.getValue(1));
3614 case TargetLowering::Expand: {
3615 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3616 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0);
3617 // Increment the pointer, VAList, to the next vaarg
3618 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
3619 DAG.getConstant(TLI.getTargetData()->
3620 getTypePaddedSize(VT.getTypeForMVT()),
3621 TLI.getPointerTy()));
3622 // Store the incremented VAList to the legalized pointer
3623 Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0);
3624 // Load the actual argument out of the pointer VAList
3625 Result = DAG.getLoad(VT, dl, Tmp3, VAList, NULL, 0);
3626 Tmp1 = LegalizeOp(Result.getValue(1));
3627 Result = LegalizeOp(Result);
3631 // Since VAARG produces two values, make sure to remember that we
3632 // legalized both of them.
3633 AddLegalizedOperand(SDValue(Node, 0), Result);
3634 AddLegalizedOperand(SDValue(Node, 1), Tmp1);
3635 return Op.getResNo() ? Tmp1 : Result;
3639 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3640 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
3641 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
3643 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
3644 default: assert(0 && "This action is not supported yet!");
3645 case TargetLowering::Custom:
3648 case TargetLowering::Legal:
3649 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
3650 Node->getOperand(3), Node->getOperand(4));
3652 Tmp1 = TLI.LowerOperation(Result, DAG);
3653 if (Tmp1.getNode()) Result = Tmp1;
3656 case TargetLowering::Expand:
3657 // This defaults to loading a pointer from the input and storing it to the
3658 // output, returning the chain.
3659 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3660 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3661 Tmp4 = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp3, VS, 0);
3662 Result = DAG.getStore(Tmp4.getValue(1), dl, Tmp4, Tmp2, VD, 0);
3668 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3669 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3671 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
3672 default: assert(0 && "This action is not supported yet!");
3673 case TargetLowering::Custom:
3676 case TargetLowering::Legal:
3677 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3679 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
3680 if (Tmp1.getNode()) Result = Tmp1;
3683 case TargetLowering::Expand:
3684 Result = Tmp1; // Default to a no-op, return the chain
3690 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3691 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3693 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3695 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
3696 default: assert(0 && "This action is not supported yet!");
3697 case TargetLowering::Legal: break;
3698 case TargetLowering::Custom:
3699 Tmp1 = TLI.LowerOperation(Result, DAG);
3700 if (Tmp1.getNode()) Result = Tmp1;
3707 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3708 Tmp2 = LegalizeOp(DAG.getShiftAmountOperand(Node->getOperand(1))); // RHS
3709 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3710 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3712 assert(0 && "ROTL/ROTR legalize operation not supported");
3714 case TargetLowering::Legal:
3716 case TargetLowering::Custom:
3717 Tmp1 = TLI.LowerOperation(Result, DAG);
3718 if (Tmp1.getNode()) Result = Tmp1;
3720 case TargetLowering::Promote:
3721 assert(0 && "Do not know how to promote ROTL/ROTR");
3723 case TargetLowering::Expand:
3724 assert(0 && "Do not know how to expand ROTL/ROTR");
3730 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3731 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3732 case TargetLowering::Custom:
3733 assert(0 && "Cannot custom legalize this yet!");
3734 case TargetLowering::Legal:
3735 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3737 case TargetLowering::Promote: {
3738 MVT OVT = Tmp1.getValueType();
3739 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3740 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3742 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1);
3743 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
3744 Result = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
3745 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3748 case TargetLowering::Expand:
3749 Result = ExpandBSWAP(Tmp1, dl);
3757 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3758 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3759 case TargetLowering::Custom:
3760 case TargetLowering::Legal:
3761 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3762 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3763 TargetLowering::Custom) {
3764 Tmp1 = TLI.LowerOperation(Result, DAG);
3765 if (Tmp1.getNode()) {
3770 case TargetLowering::Promote: {
3771 MVT OVT = Tmp1.getValueType();
3772 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3774 // Zero extend the argument.
3775 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1);
3776 // Perform the larger operation, then subtract if needed.
3777 Tmp1 = DAG.getNode(Node->getOpcode(), dl, Node->getValueType(0), Tmp1);
3778 switch (Node->getOpcode()) {
3783 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3784 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
3785 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
3787 Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
3788 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3791 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3792 Result = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
3793 DAG.getConstant(NVT.getSizeInBits() -
3794 OVT.getSizeInBits(), NVT));
3799 case TargetLowering::Expand:
3800 Result = ExpandBitCount(Node->getOpcode(), Tmp1, dl);
3820 case ISD::FNEARBYINT:
3821 Tmp1 = LegalizeOp(Node->getOperand(0));
3822 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3823 case TargetLowering::Promote:
3824 case TargetLowering::Custom:
3827 case TargetLowering::Legal:
3828 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3830 Tmp1 = TLI.LowerOperation(Result, DAG);
3831 if (Tmp1.getNode()) Result = Tmp1;
3834 case TargetLowering::Expand:
3835 switch (Node->getOpcode()) {
3836 default: assert(0 && "Unreachable!");
3838 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3839 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3840 Result = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp2, Tmp1);
3843 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3844 MVT VT = Node->getValueType(0);
3845 Tmp2 = DAG.getConstantFP(0.0, VT);
3846 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
3847 Tmp1, Tmp2, ISD::SETUGT);
3848 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
3849 Result = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3);
3864 case ISD::FNEARBYINT: {
3865 MVT VT = Node->getValueType(0);
3867 // Expand unsupported unary vector operators by unrolling them.
3868 if (VT.isVector()) {
3869 Result = LegalizeOp(UnrollVectorOp(Op));
3873 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3874 switch(Node->getOpcode()) {
3876 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3877 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
3880 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
3881 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
3884 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
3885 RTLIB::COS_F80, RTLIB::COS_PPCF128);
3888 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
3889 RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
3892 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3893 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
3896 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3897 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
3900 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
3901 RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
3904 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3905 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
3908 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3909 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
3912 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3913 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128);
3916 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3917 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128);
3920 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64,
3921 RTLIB::RINT_F80, RTLIB::RINT_PPCF128);
3923 case ISD::FNEARBYINT:
3924 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
3925 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
3928 default: assert(0 && "Unreachable!");
3931 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3939 MVT VT = Node->getValueType(0);
3941 // Expand unsupported unary vector operators by unrolling them.
3942 if (VT.isVector()) {
3943 Result = LegalizeOp(UnrollVectorOp(Op));
3947 // We always lower FPOWI into a libcall. No target support for it yet.
3948 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
3949 RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
3951 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3954 case ISD::BIT_CONVERT:
3955 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3956 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3957 Node->getValueType(0), dl);
3958 } else if (Op.getOperand(0).getValueType().isVector()) {
3959 // The input has to be a vector type, we have to either scalarize it, pack
3960 // it, or convert it based on whether the input vector type is legal.
3961 SDNode *InVal = Node->getOperand(0).getNode();
3962 int InIx = Node->getOperand(0).getResNo();
3963 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
3964 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
3966 // Figure out if there is a simple type corresponding to this Vector
3967 // type. If so, convert to the vector type.
3968 MVT TVT = MVT::getVectorVT(EVT, NumElems);
3969 if (TLI.isTypeLegal(TVT)) {
3970 // Turn this into a bit convert of the vector input.
3971 Result = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0),
3972 LegalizeOp(Node->getOperand(0)));
3974 } else if (NumElems == 1) {
3975 // Turn this into a bit convert of the scalar input.
3976 Result = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0),
3977 ScalarizeVectorOp(Node->getOperand(0)));
3980 // FIXME: UNIMP! Store then reload
3981 assert(0 && "Cast from unsupported vector type not implemented yet!");
3984 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3985 Node->getOperand(0).getValueType())) {
3986 default: assert(0 && "Unknown operation action!");
3987 case TargetLowering::Expand:
3988 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3989 Node->getValueType(0), dl);
3991 case TargetLowering::Legal:
3992 Tmp1 = LegalizeOp(Node->getOperand(0));
3993 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3998 case ISD::CONVERT_RNDSAT: {
3999 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
4001 default: assert(0 && "Unknown cvt code!");
4012 SDValue DTyOp = Node->getOperand(1);
4013 SDValue STyOp = Node->getOperand(2);
4014 SDValue RndOp = Node->getOperand(3);
4015 SDValue SatOp = Node->getOperand(4);
4016 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4017 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4019 Tmp1 = LegalizeOp(Node->getOperand(0));
4020 Result = DAG.UpdateNodeOperands(Result, Tmp1, DTyOp, STyOp,
4022 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
4023 TargetLowering::Custom) {
4024 Tmp1 = TLI.LowerOperation(Result, DAG);
4025 if (Tmp1.getNode()) Result = Tmp1;
4029 Result = PromoteOp(Node->getOperand(0));
4030 // For FP, make Op1 a i32
4032 Result = DAG.getConvertRndSat(Op.getValueType(), Result,
4033 DTyOp, STyOp, RndOp, SatOp, CvtCode);
4038 } // end switch CvtCode
4041 // Conversion operators. The source and destination have different types.
4042 case ISD::SINT_TO_FP:
4043 case ISD::UINT_TO_FP: {
4044 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
4045 Result = LegalizeINT_TO_FP(Result, isSigned,
4046 Node->getValueType(0), Node->getOperand(0), dl);
4050 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4052 Tmp1 = LegalizeOp(Node->getOperand(0));
4053 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
4054 default: assert(0 && "Unknown TRUNCATE legalization operation action!");
4055 case TargetLowering::Custom:
4058 case TargetLowering::Legal:
4059 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4061 Tmp1 = TLI.LowerOperation(Result, DAG);
4062 if (Tmp1.getNode()) Result = Tmp1;
4065 case TargetLowering::Expand:
4066 assert(Result.getValueType().isVector() && "must be vector type");
4067 // Unroll the truncate. We should do better.
4068 Result = LegalizeOp(UnrollVectorOp(Result));
4072 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4074 // Since the result is legal, we should just be able to truncate the low
4075 // part of the source.
4076 Result = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
4079 Result = PromoteOp(Node->getOperand(0));
4080 Result = DAG.getNode(ISD::TRUNCATE, dl, Op.getValueType(), Result);
4085 case ISD::FP_TO_SINT:
4086 case ISD::FP_TO_UINT:
4087 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4089 Tmp1 = LegalizeOp(Node->getOperand(0));
4091 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
4092 default: assert(0 && "Unknown operation action!");
4093 case TargetLowering::Custom:
4096 case TargetLowering::Legal:
4097 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4099 Tmp1 = TLI.LowerOperation(Result, DAG);
4100 if (Tmp1.getNode()) Result = Tmp1;
4103 case TargetLowering::Promote:
4104 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
4105 Node->getOpcode() == ISD::FP_TO_SINT,
4108 case TargetLowering::Expand:
4109 if (Node->getOpcode() == ISD::FP_TO_UINT) {
4110 SDValue True, False;
4111 MVT VT = Node->getOperand(0).getValueType();
4112 MVT NVT = Node->getValueType(0);
4113 const uint64_t zero[] = {0, 0};
4114 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero));
4115 APInt x = APInt::getSignBit(NVT.getSizeInBits());
4116 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
4117 Tmp2 = DAG.getConstantFP(apf, VT);
4118 Tmp3 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
4119 Node->getOperand(0),
4121 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
4122 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
4123 DAG.getNode(ISD::FSUB, dl, VT,
4124 Node->getOperand(0), Tmp2));
4125 False = DAG.getNode(ISD::XOR, dl, NVT, False,
4126 DAG.getConstant(x, NVT));
4127 Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp3, True, False);
4130 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
4136 MVT VT = Op.getValueType();
4137 MVT OVT = Node->getOperand(0).getValueType();
4138 // Convert ppcf128 to i32
4139 if (OVT == MVT::ppcf128 && VT == MVT::i32) {
4140 if (Node->getOpcode() == ISD::FP_TO_SINT) {
4141 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, MVT::ppcf128,
4142 Node->getOperand(0), DAG.getValueType(MVT::f64));
4143 Result = DAG.getNode(ISD::FP_ROUND, dl, MVT::f64, Result,
4144 DAG.getIntPtrConstant(1));
4145 Result = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Result);
4147 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
4148 APFloat apf = APFloat(APInt(128, 2, TwoE31));
4149 Tmp2 = DAG.getConstantFP(apf, OVT);
4150 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
4151 // FIXME: generated code sucks.
4152 Result = DAG.getNode(ISD::SELECT_CC, dl, VT, Node->getOperand(0),
4154 DAG.getNode(ISD::ADD, dl, MVT::i32,
4155 DAG.getNode(ISD::FP_TO_SINT, dl, VT,
4156 DAG.getNode(ISD::FSUB, dl, OVT,
4157 Node->getOperand(0), Tmp2)),
4158 DAG.getConstant(0x80000000, MVT::i32)),
4159 DAG.getNode(ISD::FP_TO_SINT, dl, VT,
4160 Node->getOperand(0)),
4161 DAG.getCondCode(ISD::SETGE));
4165 // Convert f32 / f64 to i32 / i64 / i128.
4166 RTLIB::Libcall LC = (Node->getOpcode() == ISD::FP_TO_SINT) ?
4167 RTLIB::getFPTOSINT(OVT, VT) : RTLIB::getFPTOUINT(OVT, VT);
4168 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpectd fp-to-int conversion!");
4170 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
4174 Tmp1 = PromoteOp(Node->getOperand(0));
4175 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
4176 Result = LegalizeOp(Result);
4181 case ISD::FP_EXTEND: {
4182 MVT DstVT = Op.getValueType();
4183 MVT SrcVT = Op.getOperand(0).getValueType();
4184 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
4185 // The only other way we can lower this is to turn it into a STORE,
4186 // LOAD pair, targetting a temporary location (a stack slot).
4187 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT, dl);
4190 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4191 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4193 Tmp1 = LegalizeOp(Node->getOperand(0));
4194 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4197 Tmp1 = PromoteOp(Node->getOperand(0));
4198 Result = DAG.getNode(ISD::FP_EXTEND, dl, Op.getValueType(), Tmp1);
4203 case ISD::FP_ROUND: {
4204 MVT DstVT = Op.getValueType();
4205 MVT SrcVT = Op.getOperand(0).getValueType();
4206 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
4207 if (SrcVT == MVT::ppcf128) {
4209 ExpandOp(Node->getOperand(0), Lo, Result);
4210 // Round it the rest of the way (e.g. to f32) if needed.
4211 if (DstVT!=MVT::f64)
4212 Result = DAG.getNode(ISD::FP_ROUND, dl,
4213 DstVT, Result, Op.getOperand(1));
4216 // The only other way we can lower this is to turn it into a STORE,
4217 // LOAD pair, targetting a temporary location (a stack slot).
4218 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT, dl);
4221 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4222 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4224 Tmp1 = LegalizeOp(Node->getOperand(0));
4225 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
4228 Tmp1 = PromoteOp(Node->getOperand(0));
4229 Result = DAG.getNode(ISD::FP_ROUND, dl, Op.getValueType(), Tmp1,
4230 Node->getOperand(1));
4235 case ISD::ANY_EXTEND:
4236 case ISD::ZERO_EXTEND:
4237 case ISD::SIGN_EXTEND:
4238 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4239 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4241 Tmp1 = LegalizeOp(Node->getOperand(0));
4242 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4243 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
4244 TargetLowering::Custom) {
4245 Tmp1 = TLI.LowerOperation(Result, DAG);
4246 if (Tmp1.getNode()) Result = Tmp1;
4250 switch (Node->getOpcode()) {
4251 case ISD::ANY_EXTEND:
4252 Tmp1 = PromoteOp(Node->getOperand(0));
4253 Result = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), Tmp1);
4255 case ISD::ZERO_EXTEND:
4256 Result = PromoteOp(Node->getOperand(0));
4257 Result = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), Result);
4258 Result = DAG.getZeroExtendInReg(Result, dl,
4259 Node->getOperand(0).getValueType());
4261 case ISD::SIGN_EXTEND:
4262 Result = PromoteOp(Node->getOperand(0));
4263 Result = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), Result);
4264 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Result.getValueType(),
4266 DAG.getValueType(Node->getOperand(0).getValueType()));
4271 case ISD::FP_ROUND_INREG:
4272 case ISD::SIGN_EXTEND_INREG: {
4273 Tmp1 = LegalizeOp(Node->getOperand(0));
4274 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
4276 // If this operation is not supported, convert it to a shl/shr or load/store
4278 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
4279 default: assert(0 && "This action not supported for this op yet!");
4280 case TargetLowering::Legal:
4281 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
4283 case TargetLowering::Expand:
4284 // If this is an integer extend and shifts are supported, do that.
4285 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
4286 // NOTE: we could fall back on load/store here too for targets without
4287 // SAR. However, it is doubtful that any exist.
4288 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() -
4289 ExtraVT.getSizeInBits();
4290 SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
4291 Result = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
4292 Node->getOperand(0), ShiftCst);
4293 Result = DAG.getNode(ISD::SRA, dl, Node->getValueType(0),
4295 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
4296 // The only way we can lower this is to turn it into a TRUNCSTORE,
4297 // EXTLOAD pair, targetting a temporary location (a stack slot).
4299 // NOTE: there is a choice here between constantly creating new stack
4300 // slots and always reusing the same one. We currently always create
4301 // new ones, as reuse may inhibit scheduling.
4302 Result = EmitStackConvert(Node->getOperand(0), ExtraVT,
4303 Node->getValueType(0), dl);
4305 assert(0 && "Unknown op");
4311 case ISD::TRAMPOLINE: {
4313 for (unsigned i = 0; i != 6; ++i)
4314 Ops[i] = LegalizeOp(Node->getOperand(i));
4315 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
4316 // The only option for this node is to custom lower it.
4317 Result = TLI.LowerOperation(Result, DAG);
4318 assert(Result.getNode() && "Should always custom lower!");
4320 // Since trampoline produces two values, make sure to remember that we
4321 // legalized both of them.
4322 Tmp1 = LegalizeOp(Result.getValue(1));
4323 Result = LegalizeOp(Result);
4324 AddLegalizedOperand(SDValue(Node, 0), Result);
4325 AddLegalizedOperand(SDValue(Node, 1), Tmp1);
4326 return Op.getResNo() ? Tmp1 : Result;
4328 case ISD::FLT_ROUNDS_: {
4329 MVT VT = Node->getValueType(0);
4330 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4331 default: assert(0 && "This action not supported for this op yet!");
4332 case TargetLowering::Custom:
4333 Result = TLI.LowerOperation(Op, DAG);
4334 if (Result.getNode()) break;
4336 case TargetLowering::Legal:
4337 // If this operation is not supported, lower it to constant 1
4338 Result = DAG.getConstant(1, VT);
4344 MVT VT = Node->getValueType(0);
4345 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4346 default: assert(0 && "This action not supported for this op yet!");
4347 case TargetLowering::Legal:
4348 Tmp1 = LegalizeOp(Node->getOperand(0));
4349 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4351 case TargetLowering::Custom:
4352 Result = TLI.LowerOperation(Op, DAG);
4353 if (Result.getNode()) break;
4355 case TargetLowering::Expand:
4356 // If this operation is not supported, lower it to 'abort()' call
4357 Tmp1 = LegalizeOp(Node->getOperand(0));
4358 TargetLowering::ArgListTy Args;
4359 std::pair<SDValue,SDValue> CallResult =
4360 TLI.LowerCallTo(Tmp1, Type::VoidTy,
4361 false, false, false, false, CallingConv::C, false,
4362 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
4364 Result = CallResult.second;
4372 MVT VT = Node->getValueType(0);
4373 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4374 default: assert(0 && "This action not supported for this op yet!");
4375 case TargetLowering::Custom:
4376 Result = TLI.LowerOperation(Op, DAG);
4377 if (Result.getNode()) break;
4379 case TargetLowering::Legal: {
4380 SDValue LHS = LegalizeOp(Node->getOperand(0));
4381 SDValue RHS = LegalizeOp(Node->getOperand(1));
4383 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
4384 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
4386 MVT OType = Node->getValueType(1);
4388 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
4390 // LHSSign -> LHS >= 0
4391 // RHSSign -> RHS >= 0
4392 // SumSign -> Sum >= 0
4395 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
4397 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
4399 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
4400 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
4401 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
4402 Node->getOpcode() == ISD::SADDO ?
4403 ISD::SETEQ : ISD::SETNE);
4405 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
4406 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
4408 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
4410 MVT ValueVTs[] = { LHS.getValueType(), OType };
4411 SDValue Ops[] = { Sum, Cmp };
4413 Result = DAG.getNode(ISD::MERGE_VALUES, dl,
4414 DAG.getVTList(&ValueVTs[0], 2),
4416 SDNode *RNode = Result.getNode();
4417 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), SDValue(RNode, 0));
4418 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), SDValue(RNode, 1));
4427 MVT VT = Node->getValueType(0);
4428 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4429 default: assert(0 && "This action not supported for this op yet!");
4430 case TargetLowering::Custom:
4431 Result = TLI.LowerOperation(Op, DAG);
4432 if (Result.getNode()) break;
4434 case TargetLowering::Legal: {
4435 SDValue LHS = LegalizeOp(Node->getOperand(0));
4436 SDValue RHS = LegalizeOp(Node->getOperand(1));
4438 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
4439 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
4441 MVT OType = Node->getValueType(1);
4442 SDValue Cmp = DAG.getSetCC(dl, OType, Sum, LHS,
4443 Node->getOpcode () == ISD::UADDO ?
4444 ISD::SETULT : ISD::SETUGT);
4446 MVT ValueVTs[] = { LHS.getValueType(), OType };
4447 SDValue Ops[] = { Sum, Cmp };
4449 Result = DAG.getNode(ISD::MERGE_VALUES, dl,
4450 DAG.getVTList(&ValueVTs[0], 2),
4452 SDNode *RNode = Result.getNode();
4453 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), SDValue(RNode, 0));
4454 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), SDValue(RNode, 1));
4463 MVT VT = Node->getValueType(0);
4464 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4465 default: assert(0 && "This action is not supported at all!");
4466 case TargetLowering::Custom:
4467 Result = TLI.LowerOperation(Op, DAG);
4468 if (Result.getNode()) break;
4470 case TargetLowering::Legal:
4471 // FIXME: According to Hacker's Delight, this can be implemented in
4472 // target independent lowering, but it would be inefficient, since it
4473 // requires a division + a branch.
4474 assert(0 && "Target independent lowering is not supported for SMULO/UMULO!");
4482 assert(Result.getValueType() == Op.getValueType() &&
4483 "Bad legalization!");
4485 // Make sure that the generated code is itself legal.
4487 Result = LegalizeOp(Result);
4489 // Note that LegalizeOp may be reentered even from single-use nodes, which
4490 // means that we always must cache transformed nodes.
4491 AddLegalizedOperand(Op, Result);
4495 /// PromoteOp - Given an operation that produces a value in an invalid type,
4496 /// promote it to compute the value into a larger type. The produced value will
4497 /// have the correct bits for the low portion of the register, but no guarantee
4498 /// is made about the top bits: it may be zero, sign-extended, or garbage.
4499 SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) {
4500 MVT VT = Op.getValueType();
4501 MVT NVT = TLI.getTypeToTransformTo(VT);
4502 assert(getTypeAction(VT) == Promote &&
4503 "Caller should expand or legalize operands that are not promotable!");
4504 assert(NVT.bitsGT(VT) && NVT.isInteger() == VT.isInteger() &&
4505 "Cannot promote to smaller type!");
4507 SDValue Tmp1, Tmp2, Tmp3;
4509 SDNode *Node = Op.getNode();
4510 DebugLoc dl = Node->getDebugLoc();
4512 DenseMap<SDValue, SDValue>::iterator I = PromotedNodes.find(Op);
4513 if (I != PromotedNodes.end()) return I->second;
4515 switch (Node->getOpcode()) {
4516 case ISD::CopyFromReg:
4517 assert(0 && "CopyFromReg must be legal!");
4520 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
4522 assert(0 && "Do not know how to promote this operator!");
4525 Result = DAG.getNode(ISD::UNDEF, dl, NVT);
4529 Result = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, Op);
4531 Result = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Op);
4532 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
4534 case ISD::ConstantFP:
4535 Result = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Op);
4536 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
4540 MVT VT0 = Node->getOperand(0).getValueType();
4541 assert(isTypeLegal(TLI.getSetCCResultType(VT0))
4542 && "SetCC type is not legal??");
4543 Result = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(VT0),
4544 Node->getOperand(0), Node->getOperand(1),
4545 Node->getOperand(2));
4549 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4551 Result = LegalizeOp(Node->getOperand(0));
4552 assert(Result.getValueType().bitsGE(NVT) &&
4553 "This truncation doesn't make sense!");
4554 if (Result.getValueType().bitsGT(NVT)) // Truncate to NVT instead of VT
4555 Result = DAG.getNode(ISD::TRUNCATE, dl, NVT, Result);
4558 // The truncation is not required, because we don't guarantee anything
4559 // about high bits anyway.
4560 Result = PromoteOp(Node->getOperand(0));
4563 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4564 // Truncate the low part of the expanded value to the result type
4565 Result = DAG.getNode(ISD::TRUNCATE, dl, NVT, Tmp1);
4568 case ISD::SIGN_EXTEND:
4569 case ISD::ZERO_EXTEND:
4570 case ISD::ANY_EXTEND:
4571 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4572 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
4574 // Input is legal? Just do extend all the way to the larger type.
4575 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Node->getOperand(0));
4578 // Promote the reg if it's smaller.
4579 Result = PromoteOp(Node->getOperand(0));
4580 // The high bits are not guaranteed to be anything. Insert an extend.
4581 if (Node->getOpcode() == ISD::SIGN_EXTEND)
4582 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Result,
4583 DAG.getValueType(Node->getOperand(0).getValueType()));
4584 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
4585 Result = DAG.getZeroExtendInReg(Result, dl,
4586 Node->getOperand(0).getValueType());
4590 case ISD::CONVERT_RNDSAT: {
4591 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
4592 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
4593 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
4594 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
4595 "can only promote integers");
4596 Result = DAG.getConvertRndSat(NVT, Node->getOperand(0),
4597 Node->getOperand(1), Node->getOperand(2),
4598 Node->getOperand(3), Node->getOperand(4),
4603 case ISD::BIT_CONVERT:
4604 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
4605 Node->getValueType(0), dl);
4606 Result = PromoteOp(Result);
4609 case ISD::FP_EXTEND:
4610 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
4612 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4613 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
4614 case Promote: assert(0 && "Unreachable with 2 FP types!");
4616 if (Node->getConstantOperandVal(1) == 0) {
4617 // Input is legal? Do an FP_ROUND_INREG.
4618 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Node->getOperand(0),
4619 DAG.getValueType(VT));
4621 // Just remove the truncate, it isn't affecting the value.
4622 Result = DAG.getNode(ISD::FP_ROUND, dl, NVT, Node->getOperand(0),
4623 Node->getOperand(1));
4628 case ISD::SINT_TO_FP:
4629 case ISD::UINT_TO_FP:
4630 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4632 // No extra round required here.
4633 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Node->getOperand(0));
4637 Result = PromoteOp(Node->getOperand(0));
4638 if (Node->getOpcode() == ISD::SINT_TO_FP)
4639 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Result.getValueType(),
4641 DAG.getValueType(Node->getOperand(0).getValueType()));
4643 Result = DAG.getZeroExtendInReg(Result, dl,
4644 Node->getOperand(0).getValueType());
4645 // No extra round required here.
4646 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Result);
4649 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
4650 Node->getOperand(0), dl);
4651 // Round if we cannot tolerate excess precision.
4652 if (NoExcessFPPrecision)
4653 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4654 DAG.getValueType(VT));
4659 case ISD::SIGN_EXTEND_INREG:
4660 Result = PromoteOp(Node->getOperand(0));
4661 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Result,
4662 Node->getOperand(1));
4664 case ISD::FP_TO_SINT:
4665 case ISD::FP_TO_UINT:
4666 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4669 Tmp1 = Node->getOperand(0);
4672 // The input result is prerounded, so we don't have to do anything
4674 Tmp1 = PromoteOp(Node->getOperand(0));
4677 // If we're promoting a UINT to a larger size, check to see if the new node
4678 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
4679 // we can use that instead. This allows us to generate better code for
4680 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
4681 // legal, such as PowerPC.
4682 if (Node->getOpcode() == ISD::FP_TO_UINT &&
4683 !TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NVT) &&
4684 (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT) ||
4685 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
4686 Result = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Tmp1);
4688 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4694 Tmp1 = PromoteOp(Node->getOperand(0));
4695 assert(Tmp1.getValueType() == NVT);
4696 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4697 // NOTE: we do not have to do any extra rounding here for
4698 // NoExcessFPPrecision, because we know the input will have the appropriate
4699 // precision, and these operations don't modify precision at all.
4714 case ISD::FNEARBYINT:
4715 Tmp1 = PromoteOp(Node->getOperand(0));
4716 assert(Tmp1.getValueType() == NVT);
4717 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4718 if (NoExcessFPPrecision)
4719 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4720 DAG.getValueType(VT));
4725 // Promote f32 pow(i) to f64 pow(i). Note that this could insert a libcall
4726 // directly as well, which may be better.
4727 Tmp1 = PromoteOp(Node->getOperand(0));
4728 Tmp2 = Node->getOperand(1);
4729 if (Node->getOpcode() == ISD::FPOW)
4730 Tmp2 = PromoteOp(Tmp2);
4731 assert(Tmp1.getValueType() == NVT);
4732 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4733 if (NoExcessFPPrecision)
4734 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4735 DAG.getValueType(VT));
4739 case ISD::ATOMIC_CMP_SWAP: {
4740 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4741 Tmp2 = PromoteOp(Node->getOperand(2));
4742 Tmp3 = PromoteOp(Node->getOperand(3));
4743 Result = DAG.getAtomic(Node->getOpcode(), dl, AtomNode->getMemoryVT(),
4744 AtomNode->getChain(),
4745 AtomNode->getBasePtr(), Tmp2, Tmp3,
4746 AtomNode->getSrcValue(),
4747 AtomNode->getAlignment());
4748 // Remember that we legalized the chain.
4749 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4752 case ISD::ATOMIC_LOAD_ADD:
4753 case ISD::ATOMIC_LOAD_SUB:
4754 case ISD::ATOMIC_LOAD_AND:
4755 case ISD::ATOMIC_LOAD_OR:
4756 case ISD::ATOMIC_LOAD_XOR:
4757 case ISD::ATOMIC_LOAD_NAND:
4758 case ISD::ATOMIC_LOAD_MIN:
4759 case ISD::ATOMIC_LOAD_MAX:
4760 case ISD::ATOMIC_LOAD_UMIN:
4761 case ISD::ATOMIC_LOAD_UMAX:
4762 case ISD::ATOMIC_SWAP: {
4763 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4764 Tmp2 = PromoteOp(Node->getOperand(2));
4765 Result = DAG.getAtomic(Node->getOpcode(), dl, AtomNode->getMemoryVT(),
4766 AtomNode->getChain(),
4767 AtomNode->getBasePtr(), Tmp2,
4768 AtomNode->getSrcValue(),
4769 AtomNode->getAlignment());
4770 // Remember that we legalized the chain.
4771 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4781 // The input may have strange things in the top bits of the registers, but
4782 // these operations don't care. They may have weird bits going out, but
4783 // that too is okay if they are integer operations.
4784 Tmp1 = PromoteOp(Node->getOperand(0));
4785 Tmp2 = PromoteOp(Node->getOperand(1));
4786 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4787 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4792 Tmp1 = PromoteOp(Node->getOperand(0));
4793 Tmp2 = PromoteOp(Node->getOperand(1));
4794 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4795 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4797 // Floating point operations will give excess precision that we may not be
4798 // able to tolerate. If we DO allow excess precision, just leave it,
4799 // otherwise excise it.
4800 // FIXME: Why would we need to round FP ops more than integer ones?
4801 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
4802 if (NoExcessFPPrecision)
4803 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4804 DAG.getValueType(VT));
4809 // These operators require that their input be sign extended.
4810 Tmp1 = PromoteOp(Node->getOperand(0));
4811 Tmp2 = PromoteOp(Node->getOperand(1));
4812 if (NVT.isInteger()) {
4813 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp1,
4814 DAG.getValueType(VT));
4815 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp2,
4816 DAG.getValueType(VT));
4818 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4820 // Perform FP_ROUND: this is probably overly pessimistic.
4821 if (NVT.isFloatingPoint() && NoExcessFPPrecision)
4822 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4823 DAG.getValueType(VT));
4827 case ISD::FCOPYSIGN:
4828 // These operators require that their input be fp extended.
4829 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4830 case Expand: assert(0 && "not implemented");
4831 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break;
4832 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break;
4834 switch (getTypeAction(Node->getOperand(1).getValueType())) {
4835 case Expand: assert(0 && "not implemented");
4836 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
4837 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
4839 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4841 // Perform FP_ROUND: this is probably overly pessimistic.
4842 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
4843 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4844 DAG.getValueType(VT));
4849 // These operators require that their input be zero extended.
4850 Tmp1 = PromoteOp(Node->getOperand(0));
4851 Tmp2 = PromoteOp(Node->getOperand(1));
4852 assert(NVT.isInteger() && "Operators don't apply to FP!");
4853 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, VT);
4854 Tmp2 = DAG.getZeroExtendInReg(Tmp2, dl, VT);
4855 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4859 Tmp1 = PromoteOp(Node->getOperand(0));
4860 Result = DAG.getNode(ISD::SHL, dl, NVT, Tmp1, Node->getOperand(1));
4863 // The input value must be properly sign extended.
4864 Tmp1 = PromoteOp(Node->getOperand(0));
4865 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp1,
4866 DAG.getValueType(VT));
4867 Result = DAG.getNode(ISD::SRA, dl, NVT, Tmp1, Node->getOperand(1));
4870 // The input value must be properly zero extended.
4871 Tmp1 = PromoteOp(Node->getOperand(0));
4872 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, VT);
4873 Result = DAG.getNode(ISD::SRL, dl, NVT, Tmp1, Node->getOperand(1));
4877 Tmp1 = Node->getOperand(0); // Get the chain.
4878 Tmp2 = Node->getOperand(1); // Get the pointer.
4879 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
4880 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
4881 Result = TLI.LowerOperation(Tmp3, DAG);
4883 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
4884 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
4885 // Increment the pointer, VAList, to the next vaarg
4886 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
4887 DAG.getConstant(VT.getSizeInBits()/8,
4888 TLI.getPointerTy()));
4889 // Store the incremented VAList to the legalized pointer
4890 Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0);
4891 // Load the actual argument out of the pointer VAList
4892 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, NVT, Tmp3, VAList, NULL, 0, VT);
4894 // Remember that we legalized the chain.
4895 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4899 LoadSDNode *LD = cast<LoadSDNode>(Node);
4900 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
4901 ? ISD::EXTLOAD : LD->getExtensionType();
4902 Result = DAG.getExtLoad(ExtType, dl, NVT,
4903 LD->getChain(), LD->getBasePtr(),
4904 LD->getSrcValue(), LD->getSrcValueOffset(),
4907 LD->getAlignment());
4908 // Remember that we legalized the chain.
4909 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4913 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
4914 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
4916 MVT VT2 = Tmp2.getValueType();
4917 assert(VT2 == Tmp3.getValueType()
4918 && "PromoteOp SELECT: Operands 2 and 3 ValueTypes don't match");
4919 // Ensure that the resulting node is at least the same size as the operands'
4920 // value types, because we cannot assume that TLI.getSetCCValueType() is
4922 Result = DAG.getNode(ISD::SELECT, dl, VT2, Node->getOperand(0), Tmp2, Tmp3);
4925 case ISD::SELECT_CC:
4926 Tmp2 = PromoteOp(Node->getOperand(2)); // True
4927 Tmp3 = PromoteOp(Node->getOperand(3)); // False
4928 Result = DAG.getNode(ISD::SELECT_CC, dl, NVT, Node->getOperand(0),
4929 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
4932 Tmp1 = Node->getOperand(0);
4933 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1);
4934 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
4935 Result = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
4936 DAG.getConstant(NVT.getSizeInBits() -
4938 TLI.getShiftAmountTy()));
4943 // Zero extend the argument
4944 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4945 // Perform the larger operation, then subtract if needed.
4946 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4947 switch(Node->getOpcode()) {
4952 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
4953 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()), Tmp1,
4954 DAG.getConstant(NVT.getSizeInBits(), NVT),
4956 Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
4957 DAG.getConstant(VT.getSizeInBits(), NVT), Tmp1);
4960 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4961 Result = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
4962 DAG.getConstant(NVT.getSizeInBits() -
4963 VT.getSizeInBits(), NVT));
4967 case ISD::EXTRACT_SUBVECTOR:
4968 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
4970 case ISD::EXTRACT_VECTOR_ELT:
4971 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
4975 assert(Result.getNode() && "Didn't set a result!");
4977 // Make sure the result is itself legal.
4978 Result = LegalizeOp(Result);
4980 // Remember that we promoted this!
4981 AddPromotedOperand(Op, Result);
4985 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
4986 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
4987 /// based on the vector type. The return type of this matches the element type
4988 /// of the vector, which may not be legal for the target.
4989 SDValue SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDValue Op) {
4990 // We know that operand #0 is the Vec vector. If the index is a constant
4991 // or if the invec is a supported hardware type, we can use it. Otherwise,
4992 // lower to a store then an indexed load.
4993 SDValue Vec = Op.getOperand(0);
4994 SDValue Idx = Op.getOperand(1);
4995 DebugLoc dl = Op.getNode()->getDebugLoc();
4997 MVT TVT = Vec.getValueType();
4998 unsigned NumElems = TVT.getVectorNumElements();
5000 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
5001 default: assert(0 && "This action is not supported yet!");
5002 case TargetLowering::Custom: {
5003 Vec = LegalizeOp(Vec);
5004 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
5005 SDValue Tmp3 = TLI.LowerOperation(Op, DAG);
5010 case TargetLowering::Legal:
5011 if (isTypeLegal(TVT)) {
5012 Vec = LegalizeOp(Vec);
5013 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
5017 case TargetLowering::Promote:
5018 assert(TVT.isVector() && "not vector type");
5019 // fall thru to expand since vectors are by default are promote
5020 case TargetLowering::Expand:
5024 if (NumElems == 1) {
5025 // This must be an access of the only element. Return it.
5026 Op = ScalarizeVectorOp(Vec);
5027 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
5028 unsigned NumLoElts = 1 << Log2_32(NumElems-1);
5029 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
5031 SplitVectorOp(Vec, Lo, Hi);
5032 if (CIdx->getZExtValue() < NumLoElts) {
5036 Idx = DAG.getConstant(CIdx->getZExtValue() - NumLoElts,
5037 Idx.getValueType());
5040 // It's now an extract from the appropriate high or low part. Recurse.
5041 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
5042 Op = ExpandEXTRACT_VECTOR_ELT(Op);
5044 // Store the value to a temporary stack slot, then LOAD the scalar
5045 // element back out.
5046 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
5047 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0);
5049 // Add the offset to the index.
5050 unsigned EltSize = Op.getValueType().getSizeInBits()/8;
5051 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
5052 DAG.getConstant(EltSize, Idx.getValueType()));
5054 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
5055 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
5057 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
5059 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
5061 Op = DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, NULL, 0);
5066 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
5067 /// we assume the operation can be split if it is not already legal.
5068 SDValue SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDValue Op) {
5069 // We know that operand #0 is the Vec vector. For now we assume the index
5070 // is a constant and that the extracted result is a supported hardware type.
5071 SDValue Vec = Op.getOperand(0);
5072 SDValue Idx = LegalizeOp(Op.getOperand(1));
5074 unsigned NumElems = Vec.getValueType().getVectorNumElements();
5076 if (NumElems == Op.getValueType().getVectorNumElements()) {
5077 // This must be an access of the desired vector length. Return it.
5081 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
5083 SplitVectorOp(Vec, Lo, Hi);
5084 if (CIdx->getZExtValue() < NumElems/2) {
5088 Idx = DAG.getConstant(CIdx->getZExtValue() - NumElems/2,
5089 Idx.getValueType());
5092 // It's now an extract from the appropriate high or low part. Recurse.
5093 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
5094 return ExpandEXTRACT_SUBVECTOR(Op);
5097 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
5098 /// with condition CC on the current target. This usually involves legalizing
5099 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
5100 /// there may be no choice but to create a new SetCC node to represent the
5101 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
5102 /// LHS, and the SDValue returned in RHS has a nil SDNode value.
5103 void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS,
5107 SDValue Tmp1, Tmp2, Tmp3, Result;
5109 switch (getTypeAction(LHS.getValueType())) {
5111 Tmp1 = LegalizeOp(LHS); // LHS
5112 Tmp2 = LegalizeOp(RHS); // RHS
5115 Tmp1 = PromoteOp(LHS); // LHS
5116 Tmp2 = PromoteOp(RHS); // RHS
5118 // If this is an FP compare, the operands have already been extended.
5119 if (LHS.getValueType().isInteger()) {
5120 MVT VT = LHS.getValueType();
5121 MVT NVT = TLI.getTypeToTransformTo(VT);
5123 // Otherwise, we have to insert explicit sign or zero extends. Note
5124 // that we could insert sign extends for ALL conditions, but zero extend
5125 // is cheaper on many machines (an AND instead of two shifts), so prefer
5127 switch (cast<CondCodeSDNode>(CC)->get()) {
5128 default: assert(0 && "Unknown integer comparison!");
5135 // ALL of these operations will work if we either sign or zero extend
5136 // the operands (including the unsigned comparisons!). Zero extend is
5137 // usually a simpler/cheaper operation, so prefer it.
5138 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, VT);
5139 Tmp2 = DAG.getZeroExtendInReg(Tmp2, dl, VT);
5145 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp1,
5146 DAG.getValueType(VT));
5147 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp2,
5148 DAG.getValueType(VT));
5149 Tmp1 = LegalizeOp(Tmp1); // Relegalize new nodes.
5150 Tmp2 = LegalizeOp(Tmp2); // Relegalize new nodes.
5156 MVT VT = LHS.getValueType();
5157 if (VT == MVT::f32 || VT == MVT::f64) {
5158 // Expand into one or more soft-fp libcall(s).
5159 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
5160 switch (cast<CondCodeSDNode>(CC)->get()) {
5163 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
5167 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
5171 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
5175 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
5179 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
5183 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
5186 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
5189 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
5192 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
5193 switch (cast<CondCodeSDNode>(CC)->get()) {
5195 // SETONE = SETOLT | SETOGT
5196 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
5199 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
5202 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
5205 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
5208 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
5211 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
5213 default: assert(0 && "Unsupported FP setcc!");
5218 SDValue Ops[2] = { LHS, RHS };
5219 Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2, dl).getNode(),
5220 false /*sign irrelevant*/, Dummy);
5221 Tmp2 = DAG.getConstant(0, MVT::i32);
5222 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
5223 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
5224 Tmp1 = DAG.getNode(ISD::SETCC, dl,
5225 TLI.getSetCCResultType(Tmp1.getValueType()),
5227 LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2, dl).getNode(),
5228 false /*sign irrelevant*/, Dummy);
5229 Tmp2 = DAG.getNode(ISD::SETCC, dl,
5230 TLI.getSetCCResultType(LHS.getValueType()), LHS,
5231 Tmp2, DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
5232 Tmp1 = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp2);
5235 LHS = LegalizeOp(Tmp1);
5240 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
5241 ExpandOp(LHS, LHSLo, LHSHi);
5242 ExpandOp(RHS, RHSLo, RHSHi);
5243 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
5245 if (VT==MVT::ppcf128) {
5246 // FIXME: This generated code sucks. We want to generate
5247 // FCMPU crN, hi1, hi2
5249 // FCMPU crN, lo1, lo2
5250 // The following can be improved, but not that much.
5251 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
5252 LHSHi, RHSHi, ISD::SETOEQ);
5253 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()),
5254 LHSLo, RHSLo, CCCode);
5255 Tmp3 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2);
5256 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
5257 LHSHi, RHSHi, ISD::SETUNE);
5258 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
5259 LHSHi, RHSHi, CCCode);
5260 Tmp1 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2);
5261 Tmp1 = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp3);
5270 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
5271 if (RHSCST->isAllOnesValue()) {
5272 // Comparison to -1.
5273 Tmp1 = DAG.getNode(ISD::AND, dl,LHSLo.getValueType(), LHSLo, LHSHi);
5278 Tmp1 = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
5279 Tmp2 = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
5280 Tmp1 = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp2);
5281 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
5284 // If this is a comparison of the sign bit, just look at the top part.
5286 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
5287 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
5288 CST->isNullValue()) || // X < 0
5289 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
5290 CST->isAllOnesValue())) { // X > -1
5296 // FIXME: This generated code sucks.
5297 ISD::CondCode LowCC;
5299 default: assert(0 && "Unknown integer setcc!");
5301 case ISD::SETULT: LowCC = ISD::SETULT; break;
5303 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
5305 case ISD::SETULE: LowCC = ISD::SETULE; break;
5307 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
5310 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
5311 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
5312 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
5314 // NOTE: on targets without efficient SELECT of bools, we can always use
5315 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
5316 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
5317 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
5318 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
5319 if (!Tmp1.getNode())
5320 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()),
5321 LHSLo, RHSLo, LowCC);
5322 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
5323 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
5324 if (!Tmp2.getNode())
5325 Tmp2 = DAG.getNode(ISD::SETCC, dl,
5326 TLI.getSetCCResultType(LHSHi.getValueType()),
5329 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
5330 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
5331 if ((Tmp1C && Tmp1C->isNullValue()) ||
5332 (Tmp2C && Tmp2C->isNullValue() &&
5333 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
5334 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
5335 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
5336 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
5337 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
5338 // low part is known false, returns high part.
5339 // For LE / GE, if high part is known false, ignore the low part.
5340 // For LT / GT, if high part is known true, ignore the low part.
5344 Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
5345 LHSHi, RHSHi, ISD::SETEQ, false,
5346 DagCombineInfo, dl);
5347 if (!Result.getNode())
5348 Result=DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
5349 LHSHi, RHSHi, ISD::SETEQ);
5350 Result = LegalizeOp(DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(),
5351 Result, Tmp1, Tmp2));
5362 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
5363 /// condition code CC on the current target. This routine assumes LHS and rHS
5364 /// have already been legalized by LegalizeSetCCOperands. It expands SETCC with
5365 /// illegal condition code into AND / OR of multiple SETCC values.
5366 void SelectionDAGLegalize::LegalizeSetCCCondCode(MVT VT,
5367 SDValue &LHS, SDValue &RHS,
5370 MVT OpVT = LHS.getValueType();
5371 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
5372 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
5373 default: assert(0 && "Unknown condition code action!");
5374 case TargetLowering::Legal:
5377 case TargetLowering::Expand: {
5378 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
5381 default: assert(0 && "Don't know how to expand this condition!"); abort();
5382 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break;
5383 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break;
5384 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5385 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break;
5386 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5387 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5388 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5389 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5390 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5391 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5392 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5393 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5394 // FIXME: Implement more expansions.
5397 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
5398 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
5399 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
5407 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
5408 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
5409 /// a load from the stack slot to DestVT, extending it if needed.
5410 /// The resultant code need not be legal.
5411 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
5415 // Create the stack frame object.
5416 unsigned SrcAlign = TLI.getTargetData()->getPrefTypeAlignment(
5417 SrcOp.getValueType().getTypeForMVT());
5418 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
5420 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
5421 int SPFI = StackPtrFI->getIndex();
5422 const Value *SV = PseudoSourceValue::getFixedStack(SPFI);
5424 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
5425 unsigned SlotSize = SlotVT.getSizeInBits();
5426 unsigned DestSize = DestVT.getSizeInBits();
5427 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(
5428 DestVT.getTypeForMVT());
5430 // Emit a store to the stack slot. Use a truncstore if the input value is
5431 // later than DestVT.
5434 if (SrcSize > SlotSize)
5435 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
5436 SV, 0, SlotVT, false, SrcAlign);
5438 assert(SrcSize == SlotSize && "Invalid store");
5439 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
5440 SV, 0, false, SrcAlign);
5443 // Result is a load from the stack slot.
5444 if (SlotSize == DestSize)
5445 return DAG.getLoad(DestVT, dl, Store, FIPtr, SV, 0, false, DestAlign);
5447 assert(SlotSize < DestSize && "Unknown extension!");
5448 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, SV, 0, SlotVT,
5452 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
5453 DebugLoc dl = Node->getDebugLoc();
5454 // Create a vector sized/aligned stack slot, store the value to element #0,
5455 // then load the whole vector back out.
5456 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
5458 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
5459 int SPFI = StackPtrFI->getIndex();
5461 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(0),
5463 PseudoSourceValue::getFixedStack(SPFI), 0);
5464 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
5465 PseudoSourceValue::getFixedStack(SPFI), 0);
5469 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
5470 /// support the operation, but do support the resultant vector type.
5471 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
5473 // If the only non-undef value is the low element, turn this into a
5474 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
5475 unsigned NumElems = Node->getNumOperands();
5476 bool isOnlyLowElement = true;
5477 SDValue SplatValue = Node->getOperand(0);
5478 DebugLoc dl = Node->getDebugLoc();
5480 // FIXME: it would be far nicer to change this into map<SDValue,uint64_t>
5481 // and use a bitmask instead of a list of elements.
5482 std::map<SDValue, std::vector<unsigned> > Values;
5483 Values[SplatValue].push_back(0);
5484 bool isConstant = true;
5485 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
5486 SplatValue.getOpcode() != ISD::UNDEF)
5489 for (unsigned i = 1; i < NumElems; ++i) {
5490 SDValue V = Node->getOperand(i);
5491 Values[V].push_back(i);
5492 if (V.getOpcode() != ISD::UNDEF)
5493 isOnlyLowElement = false;
5494 if (SplatValue != V)
5495 SplatValue = SDValue(0,0);
5497 // If this isn't a constant element or an undef, we can't use a constant
5499 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
5500 V.getOpcode() != ISD::UNDEF)
5504 if (isOnlyLowElement) {
5505 // If the low element is an undef too, then this whole things is an undef.
5506 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
5507 return DAG.getNode(ISD::UNDEF, dl, Node->getValueType(0));
5508 // Otherwise, turn this into a scalar_to_vector node.
5509 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, Node->getValueType(0),
5510 Node->getOperand(0));
5513 // If all elements are constants, create a load from the constant pool.
5515 MVT VT = Node->getValueType(0);
5516 std::vector<Constant*> CV;
5517 for (unsigned i = 0, e = NumElems; i != e; ++i) {
5518 if (ConstantFPSDNode *V =
5519 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
5520 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
5521 } else if (ConstantSDNode *V =
5522 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
5523 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
5525 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
5527 Node->getOperand(0).getValueType().getTypeForMVT();
5528 CV.push_back(UndefValue::get(OpNTy));
5531 Constant *CP = ConstantVector::get(CV);
5532 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
5533 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5534 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5535 PseudoSourceValue::getConstantPool(), 0,
5539 if (SplatValue.getNode()) { // Splat of one value?
5540 // Build the shuffle constant vector: <0, 0, 0, 0>
5541 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
5542 SDValue Zero = DAG.getConstant(0, MaskVT.getVectorElementType());
5543 std::vector<SDValue> ZeroVec(NumElems, Zero);
5544 SDValue SplatMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
5545 &ZeroVec[0], ZeroVec.size());
5547 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
5548 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
5549 // Get the splatted value into the low element of a vector register.
5551 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5552 Node->getValueType(0), SplatValue);
5554 // Return shuffle(LowValVec, undef, <0,0,0,0>)
5555 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl,
5556 Node->getValueType(0), LowValVec,
5557 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
5562 // If there are only two unique elements, we may be able to turn this into a
5564 if (Values.size() == 2) {
5565 // Get the two values in deterministic order.
5566 SDValue Val1 = Node->getOperand(1);
5568 std::map<SDValue, std::vector<unsigned> >::iterator MI = Values.begin();
5569 if (MI->first != Val1)
5572 Val2 = (++MI)->first;
5574 // If Val1 is an undef, make sure end ends up as Val2, to ensure that our
5575 // vector shuffle has the undef vector on the RHS.
5576 if (Val1.getOpcode() == ISD::UNDEF)
5577 std::swap(Val1, Val2);
5579 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
5580 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
5581 MVT MaskEltVT = MaskVT.getVectorElementType();
5582 std::vector<SDValue> MaskVec(NumElems);
5584 // Set elements of the shuffle mask for Val1.
5585 std::vector<unsigned> &Val1Elts = Values[Val1];
5586 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i)
5587 MaskVec[Val1Elts[i]] = DAG.getConstant(0, MaskEltVT);
5589 // Set elements of the shuffle mask for Val2.
5590 std::vector<unsigned> &Val2Elts = Values[Val2];
5591 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i)
5592 if (Val2.getOpcode() != ISD::UNDEF)
5593 MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT);
5595 MaskVec[Val2Elts[i]] = DAG.getNode(ISD::UNDEF, dl, MaskEltVT);
5597 SDValue ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
5598 &MaskVec[0], MaskVec.size());
5600 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it.
5601 if (TLI.isOperationLegalOrCustom(ISD::SCALAR_TO_VECTOR,
5602 Node->getValueType(0)) &&
5603 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
5604 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,Node->getValueType(0), Val1);
5605 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,Node->getValueType(0), Val2);
5606 SDValue Ops[] = { Val1, Val2, ShuffleMask };
5608 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
5609 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl,Node->getValueType(0), Ops, 3);
5613 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
5614 // aligned object on the stack, store each element into it, then load
5615 // the result as a vector.
5616 MVT VT = Node->getValueType(0);
5617 // Create the stack frame object.
5618 SDValue FIPtr = DAG.CreateStackTemporary(VT);
5619 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
5620 const Value *SV = PseudoSourceValue::getFixedStack(FI);
5622 // Emit a store of each element to the stack slot.
5623 SmallVector<SDValue, 8> Stores;
5624 unsigned TypeByteSize = Node->getOperand(0).getValueType().getSizeInBits()/8;
5625 // Store (in the right endianness) the elements to memory.
5626 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5627 // Ignore undef elements.
5628 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
5630 unsigned Offset = TypeByteSize*i;
5632 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
5633 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
5635 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(i),
5640 if (!Stores.empty()) // Not all undef elements?
5641 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
5642 &Stores[0], Stores.size());
5644 StoreChain = DAG.getEntryNode();
5646 // Result is a load from the stack slot.
5647 return DAG.getLoad(VT, dl, StoreChain, FIPtr, SV, 0);
5650 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
5651 SDValue Op, SDValue Amt,
5652 SDValue &Lo, SDValue &Hi,
5654 // Expand the subcomponents.
5656 ExpandOp(Op, LHSL, LHSH);
5658 SDValue Ops[] = { LHSL, LHSH, Amt };
5659 MVT VT = LHSL.getValueType();
5660 Lo = DAG.getNode(NodeOp, dl, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
5661 Hi = Lo.getValue(1);
5665 /// ExpandShift - Try to find a clever way to expand this shift operation out to
5666 /// smaller elements. If we can't find a way that is more efficient than a
5667 /// libcall on this target, return false. Otherwise, return true with the
5668 /// low-parts expanded into Lo and Hi.
5669 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op,SDValue Amt,
5670 SDValue &Lo, SDValue &Hi,
5672 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
5673 "This is not a shift!");
5675 MVT NVT = TLI.getTypeToTransformTo(Op.getValueType());
5676 SDValue ShAmt = LegalizeOp(Amt);
5677 MVT ShTy = ShAmt.getValueType();
5678 unsigned ShBits = ShTy.getSizeInBits();
5679 unsigned VTBits = Op.getValueType().getSizeInBits();
5680 unsigned NVTBits = NVT.getSizeInBits();
5682 // Handle the case when Amt is an immediate.
5683 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.getNode())) {
5684 unsigned Cst = CN->getZExtValue();
5685 // Expand the incoming operand to be shifted, so that we have its parts
5687 ExpandOp(Op, InL, InH);
5691 Lo = DAG.getConstant(0, NVT);
5692 Hi = DAG.getConstant(0, NVT);
5693 } else if (Cst > NVTBits) {
5694 Lo = DAG.getConstant(0, NVT);
5695 Hi = DAG.getNode(ISD::SHL, dl,
5696 NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
5697 } else if (Cst == NVTBits) {
5698 Lo = DAG.getConstant(0, NVT);
5701 Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, DAG.getConstant(Cst, ShTy));
5702 Hi = DAG.getNode(ISD::OR, dl, NVT,
5703 DAG.getNode(ISD::SHL, dl, NVT, InH, DAG.getConstant(Cst, ShTy)),
5704 DAG.getNode(ISD::SRL, dl, NVT, InL,
5705 DAG.getConstant(NVTBits-Cst, ShTy)));
5710 Lo = DAG.getConstant(0, NVT);
5711 Hi = DAG.getConstant(0, NVT);
5712 } else if (Cst > NVTBits) {
5713 Lo = DAG.getNode(ISD::SRL, dl, NVT,
5714 InH, DAG.getConstant(Cst-NVTBits,ShTy));
5715 Hi = DAG.getConstant(0, NVT);
5716 } else if (Cst == NVTBits) {
5718 Hi = DAG.getConstant(0, NVT);
5720 Lo = DAG.getNode(ISD::OR, dl, NVT,
5721 DAG.getNode(ISD::SRL, dl, NVT, InL, DAG.getConstant(Cst, ShTy)),
5722 DAG.getNode(ISD::SHL, dl, NVT, InH,
5723 DAG.getConstant(NVTBits-Cst, ShTy)));
5724 Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, DAG.getConstant(Cst, ShTy));
5729 Hi = Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
5730 DAG.getConstant(NVTBits-1, ShTy));
5731 } else if (Cst > NVTBits) {
5732 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
5733 DAG.getConstant(Cst-NVTBits, ShTy));
5734 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
5735 DAG.getConstant(NVTBits-1, ShTy));
5736 } else if (Cst == NVTBits) {
5738 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
5739 DAG.getConstant(NVTBits-1, ShTy));
5741 Lo = DAG.getNode(ISD::OR, dl, NVT,
5742 DAG.getNode(ISD::SRL, dl, NVT, InL, DAG.getConstant(Cst, ShTy)),
5743 DAG.getNode(ISD::SHL, dl,
5744 NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5745 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(Cst, ShTy));
5751 // Okay, the shift amount isn't constant. However, if we can tell that it is
5752 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
5753 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
5754 APInt KnownZero, KnownOne;
5755 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
5757 // If we know that if any of the high bits of the shift amount are one, then
5758 // we can do this as a couple of simple shifts.
5759 if (KnownOne.intersects(Mask)) {
5760 // Mask out the high bit, which we know is set.
5761 Amt = DAG.getNode(ISD::AND, dl, Amt.getValueType(), Amt,
5762 DAG.getConstant(~Mask, Amt.getValueType()));
5764 // Expand the incoming operand to be shifted, so that we have its parts
5766 ExpandOp(Op, InL, InH);
5769 Lo = DAG.getConstant(0, NVT); // Low part is zero.
5770 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
5773 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
5774 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
5777 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
5778 DAG.getConstant(NVTBits-1, Amt.getValueType()));
5779 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
5784 // If we know that the high bits of the shift amount are all zero, then we can
5785 // do this as a couple of simple shifts.
5786 if ((KnownZero & Mask) == Mask) {
5788 SDValue Amt2 = DAG.getNode(ISD::SUB, dl, Amt.getValueType(),
5789 DAG.getConstant(NVTBits, Amt.getValueType()),
5792 // Expand the incoming operand to be shifted, so that we have its parts
5794 ExpandOp(Op, InL, InH);
5797 Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
5798 Hi = DAG.getNode(ISD::OR, dl, NVT,
5799 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
5800 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt2));
5803 Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
5804 Lo = DAG.getNode(ISD::OR, dl, NVT,
5805 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
5806 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt2));
5809 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
5810 Lo = DAG.getNode(ISD::OR, dl, NVT,
5811 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
5812 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt2));
5821 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
5822 // does not fit into a register, return the lo part and set the hi part to the
5823 // by-reg argument. If it does fit into a single register, return the result
5824 // and leave the Hi part unset.
5825 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
5826 bool isSigned, SDValue &Hi) {
5827 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
5828 // The input chain to this libcall is the entry node of the function.
5829 // Legalizing the call will automatically add the previous call to the
5831 SDValue InChain = DAG.getEntryNode();
5833 TargetLowering::ArgListTy Args;
5834 TargetLowering::ArgListEntry Entry;
5835 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5836 MVT ArgVT = Node->getOperand(i).getValueType();
5837 const Type *ArgTy = ArgVT.getTypeForMVT();
5838 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
5839 Entry.isSExt = isSigned;
5840 Entry.isZExt = !isSigned;
5841 Args.push_back(Entry);
5843 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
5844 TLI.getPointerTy());
5846 // Splice the libcall in wherever FindInputOutputChains tells us to.
5847 const Type *RetTy = Node->getValueType(0).getTypeForMVT();
5848 std::pair<SDValue,SDValue> CallInfo =
5849 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
5850 CallingConv::C, false, Callee, Args, DAG,
5851 Node->getDebugLoc());
5853 // Legalize the call sequence, starting with the chain. This will advance
5854 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
5855 // was added by LowerCallTo (guaranteeing proper serialization of calls).
5856 LegalizeOp(CallInfo.second);
5858 switch (getTypeAction(CallInfo.first.getValueType())) {
5859 default: assert(0 && "Unknown thing");
5861 Result = CallInfo.first;
5864 ExpandOp(CallInfo.first, Result, Hi);
5870 /// LegalizeINT_TO_FP - Legalize a [US]INT_TO_FP operation.
5872 SDValue SelectionDAGLegalize::
5873 LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op,
5875 bool isCustom = false;
5877 switch (getTypeAction(Op.getValueType())) {
5879 switch (TLI.getOperationAction(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5880 Op.getValueType())) {
5881 default: assert(0 && "Unknown operation action!");
5882 case TargetLowering::Custom:
5885 case TargetLowering::Legal:
5886 Tmp1 = LegalizeOp(Op);
5887 if (Result.getNode())
5888 Result = DAG.UpdateNodeOperands(Result, Tmp1);
5890 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, dl,
5893 Tmp1 = TLI.LowerOperation(Result, DAG);
5894 if (Tmp1.getNode()) Result = Tmp1;
5897 case TargetLowering::Expand:
5898 Result = ExpandLegalINT_TO_FP(isSigned, LegalizeOp(Op), DestTy, dl);
5900 case TargetLowering::Promote:
5901 Result = PromoteLegalINT_TO_FP(LegalizeOp(Op), DestTy, isSigned, dl);
5906 Result = ExpandIntToFP(isSigned, DestTy, Op, dl) ;
5909 Tmp1 = PromoteOp(Op);
5911 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Tmp1.getValueType(),
5912 Tmp1, DAG.getValueType(Op.getValueType()));
5914 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl,
5917 if (Result.getNode())
5918 Result = DAG.UpdateNodeOperands(Result, Tmp1);
5920 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, dl,
5922 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
5928 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
5930 SDValue SelectionDAGLegalize::
5931 ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source, DebugLoc dl) {
5932 MVT SourceVT = Source.getValueType();
5933 bool ExpandSource = getTypeAction(SourceVT) == Expand;
5935 // Expand unsupported int-to-fp vector casts by unrolling them.
5936 if (DestTy.isVector()) {
5938 return LegalizeOp(UnrollVectorOp(Source));
5939 MVT DestEltTy = DestTy.getVectorElementType();
5940 if (DestTy.getVectorNumElements() == 1) {
5941 SDValue Scalar = ScalarizeVectorOp(Source);
5942 SDValue Result = LegalizeINT_TO_FP(SDValue(), isSigned,
5943 DestEltTy, Scalar, dl);
5944 return DAG.getNode(ISD::BUILD_VECTOR, dl, DestTy, Result);
5947 SplitVectorOp(Source, Lo, Hi);
5948 MVT SplitDestTy = MVT::getVectorVT(DestEltTy,
5949 DestTy.getVectorNumElements() / 2);
5950 SDValue LoResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy,
5952 SDValue HiResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy,
5954 return LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, dl, DestTy, LoResult,
5958 // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc.
5959 if (!isSigned && SourceVT != MVT::i32) {
5960 // The integer value loaded will be incorrectly if the 'sign bit' of the
5961 // incoming integer is set. To handle this, we dynamically test to see if
5962 // it is set, and, if so, add a fudge factor.
5966 ExpandOp(Source, Lo, Hi);
5967 Source = DAG.getNode(ISD::BUILD_PAIR, dl, SourceVT, Lo, Hi);
5969 // The comparison for the sign bit will use the entire operand.
5973 // Check to see if the target has a custom way to lower this. If so, use
5974 // it. (Note we've already expanded the operand in this case.)
5975 switch (TLI.getOperationAction(ISD::UINT_TO_FP, SourceVT)) {
5976 default: assert(0 && "This action not implemented for this operation!");
5977 case TargetLowering::Legal:
5978 case TargetLowering::Expand:
5979 break; // This case is handled below.
5980 case TargetLowering::Custom: {
5981 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::UINT_TO_FP, DestTy,
5984 return LegalizeOp(NV);
5985 break; // The target decided this was legal after all
5989 // If this is unsigned, and not supported, first perform the conversion to
5990 // signed, then adjust the result if the sign bit is set.
5991 SDValue SignedConv = ExpandIntToFP(true, DestTy, Source, dl);
5993 SDValue SignSet = DAG.getSetCC(dl,
5994 TLI.getSetCCResultType(Hi.getValueType()),
5995 Hi, DAG.getConstant(0, Hi.getValueType()),
5997 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5998 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
5999 SignSet, Four, Zero);
6000 uint64_t FF = 0x5f800000ULL;
6001 if (TLI.isLittleEndian()) FF <<= 32;
6002 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
6004 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
6005 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
6006 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
6007 Alignment = std::min(Alignment, 4u);
6009 if (DestTy == MVT::f32)
6010 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
6011 PseudoSourceValue::getConstantPool(), 0,
6013 else if (DestTy.bitsGT(MVT::f32))
6014 // FIXME: Avoid the extend by construction the right constantpool?
6015 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, dl, DestTy, DAG.getEntryNode(),
6017 PseudoSourceValue::getConstantPool(), 0,
6018 MVT::f32, false, Alignment);
6020 assert(0 && "Unexpected conversion");
6022 MVT SCVT = SignedConv.getValueType();
6023 if (SCVT != DestTy) {
6024 // Destination type needs to be expanded as well. The FADD now we are
6025 // constructing will be expanded into a libcall.
6026 if (SCVT.getSizeInBits() != DestTy.getSizeInBits()) {
6027 assert(SCVT.getSizeInBits() * 2 == DestTy.getSizeInBits());
6028 SignedConv = DAG.getNode(ISD::BUILD_PAIR, dl, DestTy,
6029 SignedConv, SignedConv.getValue(1));
6031 SignedConv = DAG.getNode(ISD::BIT_CONVERT, dl, DestTy, SignedConv);
6033 return DAG.getNode(ISD::FADD, dl, DestTy, SignedConv, FudgeInReg);
6036 // Check to see if the target has a custom way to lower this. If so, use it.
6037 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) {
6038 default: assert(0 && "This action not implemented for this operation!");
6039 case TargetLowering::Legal:
6040 case TargetLowering::Expand:
6041 break; // This case is handled below.
6042 case TargetLowering::Custom: {
6043 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, dl, DestTy,
6046 return LegalizeOp(NV);
6047 break; // The target decided this was legal after all
6051 // Expand the source, then glue it back together for the call. We must expand
6052 // the source in case it is shared (this pass of legalize must traverse it).
6054 SDValue SrcLo, SrcHi;
6055 ExpandOp(Source, SrcLo, SrcHi);
6056 Source = DAG.getNode(ISD::BUILD_PAIR, dl, SourceVT, SrcLo, SrcHi);
6059 RTLIB::Libcall LC = isSigned ?
6060 RTLIB::getSINTTOFP(SourceVT, DestTy) :
6061 RTLIB::getUINTTOFP(SourceVT, DestTy);
6062 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unknown int value type");
6064 Source = DAG.getNode(ISD::SINT_TO_FP, dl, DestTy, Source);
6066 SDValue Result = ExpandLibCall(LC, Source.getNode(), isSigned, HiPart);
6067 if (Result.getValueType() != DestTy && HiPart.getNode())
6068 Result = DAG.getNode(ISD::BUILD_PAIR, dl, DestTy, Result, HiPart);
6072 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
6073 /// INT_TO_FP operation of the specified operand when the target requests that
6074 /// we expand it. At this point, we know that the result and operand types are
6075 /// legal for the target.
6076 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
6080 if (Op0.getValueType() == MVT::i32) {
6081 // simple 32-bit [signed|unsigned] integer to float/double expansion
6083 // Get the stack frame index of a 8 byte buffer.
6084 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
6086 // word offset constant for Hi/Lo address computation
6087 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
6088 // set up Hi and Lo (into buffer) address based on endian
6089 SDValue Hi = StackSlot;
6090 SDValue Lo = DAG.getNode(ISD::ADD, dl,
6091 TLI.getPointerTy(), StackSlot,WordOff);
6092 if (TLI.isLittleEndian())
6095 // if signed map to unsigned space
6098 // constant used to invert sign bit (signed to unsigned mapping)
6099 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
6100 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
6104 // store the lo of the constructed double - based on integer input
6105 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
6106 Op0Mapped, Lo, NULL, 0);
6107 // initial hi portion of constructed double
6108 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
6109 // store the hi of the constructed double - biased exponent
6110 SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0);
6111 // load the constructed double
6112 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0);
6113 // FP constant to bias correct the final result
6114 SDValue Bias = DAG.getConstantFP(isSigned ?
6115 BitsToDouble(0x4330000080000000ULL)
6116 : BitsToDouble(0x4330000000000000ULL),
6118 // subtract the bias
6119 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
6122 // handle final rounding
6123 if (DestVT == MVT::f64) {
6126 } else if (DestVT.bitsLT(MVT::f64)) {
6127 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
6128 DAG.getIntPtrConstant(0));
6129 } else if (DestVT.bitsGT(MVT::f64)) {
6130 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
6134 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
6135 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
6137 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()),
6138 Op0, DAG.getConstant(0, Op0.getValueType()),
6140 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
6141 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
6142 SignSet, Four, Zero);
6144 // If the sign bit of the integer is set, the large number will be treated
6145 // as a negative number. To counteract this, the dynamic code adds an
6146 // offset depending on the data type.
6148 switch (Op0.getValueType().getSimpleVT()) {
6149 default: assert(0 && "Unsupported integer type!");
6150 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
6151 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
6152 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
6153 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
6155 if (TLI.isLittleEndian()) FF <<= 32;
6156 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
6158 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
6159 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
6160 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
6161 Alignment = std::min(Alignment, 4u);
6163 if (DestVT == MVT::f32)
6164 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
6165 PseudoSourceValue::getConstantPool(), 0,
6169 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
6170 DAG.getEntryNode(), CPIdx,
6171 PseudoSourceValue::getConstantPool(), 0,
6172 MVT::f32, false, Alignment));
6175 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
6178 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
6179 /// *INT_TO_FP operation of the specified operand when the target requests that
6180 /// we promote it. At this point, we know that the result and operand types are
6181 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
6182 /// operation that takes a larger input.
6183 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
6187 // First step, figure out the appropriate *INT_TO_FP operation to use.
6188 MVT NewInTy = LegalOp.getValueType();
6190 unsigned OpToUse = 0;
6192 // Scan for the appropriate larger type to use.
6194 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
6195 assert(NewInTy.isInteger() && "Ran out of possibilities!");
6197 // If the target supports SINT_TO_FP of this type, use it.
6198 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
6200 case TargetLowering::Legal:
6201 if (!TLI.isTypeLegal(NewInTy))
6202 break; // Can't use this datatype.
6204 case TargetLowering::Custom:
6205 OpToUse = ISD::SINT_TO_FP;
6209 if (isSigned) continue;
6211 // If the target supports UINT_TO_FP of this type, use it.
6212 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
6214 case TargetLowering::Legal:
6215 if (!TLI.isTypeLegal(NewInTy))
6216 break; // Can't use this datatype.
6218 case TargetLowering::Custom:
6219 OpToUse = ISD::UINT_TO_FP;
6224 // Otherwise, try a larger type.
6227 // Okay, we found the operation and type to use. Zero extend our input to the
6228 // desired type then run the operation on it.
6229 return DAG.getNode(OpToUse, dl, DestVT,
6230 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
6231 dl, NewInTy, LegalOp));
6234 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
6235 /// FP_TO_*INT operation of the specified operand when the target requests that
6236 /// we promote it. At this point, we know that the result and operand types are
6237 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
6238 /// operation that returns a larger result.
6239 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
6243 // First step, figure out the appropriate FP_TO*INT operation to use.
6244 MVT NewOutTy = DestVT;
6246 unsigned OpToUse = 0;
6248 // Scan for the appropriate larger type to use.
6250 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1);
6251 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
6253 // If the target supports FP_TO_SINT returning this type, use it.
6254 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
6256 case TargetLowering::Legal:
6257 if (!TLI.isTypeLegal(NewOutTy))
6258 break; // Can't use this datatype.
6260 case TargetLowering::Custom:
6261 OpToUse = ISD::FP_TO_SINT;
6266 // If the target supports FP_TO_UINT of this type, use it.
6267 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
6269 case TargetLowering::Legal:
6270 if (!TLI.isTypeLegal(NewOutTy))
6271 break; // Can't use this datatype.
6273 case TargetLowering::Custom:
6274 OpToUse = ISD::FP_TO_UINT;
6279 // Otherwise, try a larger type.
6283 // Okay, we found the operation and type to use.
6284 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
6286 // If the operation produces an invalid type, it must be custom lowered. Use
6287 // the target lowering hooks to expand it. Just keep the low part of the
6288 // expanded operation, we know that we're truncating anyway.
6289 if (getTypeAction(NewOutTy) == Expand) {
6290 SmallVector<SDValue, 2> Results;
6291 TLI.ReplaceNodeResults(Operation.getNode(), Results, DAG);
6292 assert(Results.size() == 1 && "Incorrect FP_TO_XINT lowering!");
6293 Operation = Results[0];
6296 // Truncate the result of the extended FP_TO_*INT operation to the desired
6298 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
6301 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
6303 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) {
6304 MVT VT = Op.getValueType();
6305 MVT SHVT = TLI.getShiftAmountTy();
6306 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
6307 switch (VT.getSimpleVT()) {
6308 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
6310 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
6311 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
6312 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
6314 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
6315 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
6316 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
6317 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
6318 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
6319 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
6320 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
6321 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
6322 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
6324 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
6325 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
6326 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
6327 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
6328 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
6329 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
6330 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
6331 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
6332 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
6333 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
6334 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
6335 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
6336 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
6337 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
6338 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
6339 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
6340 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
6341 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
6342 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
6343 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
6344 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
6348 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
6350 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
6353 default: assert(0 && "Cannot expand this yet!");
6355 static const uint64_t mask[6] = {
6356 0x5555555555555555ULL, 0x3333333333333333ULL,
6357 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
6358 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
6360 MVT VT = Op.getValueType();
6361 MVT ShVT = TLI.getShiftAmountTy();
6362 unsigned len = VT.getSizeInBits();
6363 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
6364 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
6365 unsigned EltSize = VT.isVector() ?
6366 VT.getVectorElementType().getSizeInBits() : len;
6367 SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT);
6368 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
6369 Op = DAG.getNode(ISD::ADD, dl, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
6370 DAG.getNode(ISD::AND, dl, VT,
6371 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3),
6377 // for now, we do this:
6378 // x = x | (x >> 1);
6379 // x = x | (x >> 2);
6381 // x = x | (x >>16);
6382 // x = x | (x >>32); // for 64-bit input
6383 // return popcount(~x);
6385 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
6386 MVT VT = Op.getValueType();
6387 MVT ShVT = TLI.getShiftAmountTy();
6388 unsigned len = VT.getSizeInBits();
6389 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
6390 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
6391 Op = DAG.getNode(ISD::OR, dl, VT, Op,
6392 DAG.getNode(ISD::SRL, VT, Op, Tmp3));
6394 Op = DAG.getNOT(dl, Op, VT);
6395 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
6398 // for now, we use: { return popcount(~x & (x - 1)); }
6399 // unless the target has ctlz but not ctpop, in which case we use:
6400 // { return 32 - nlz(~x & (x-1)); }
6401 // see also http://www.hackersdelight.org/HDcode/ntz.cc
6402 MVT VT = Op.getValueType();
6403 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
6404 DAG.getNOT(dl, Op, VT),
6405 DAG.getNode(ISD::SUB, dl, VT, Op,
6406 DAG.getConstant(1, VT)));
6407 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
6408 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
6409 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
6410 return DAG.getNode(ISD::SUB, dl, VT,
6411 DAG.getConstant(VT.getSizeInBits(), VT),
6412 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
6413 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
6418 /// ExpandOp - Expand the specified SDValue into its two component pieces
6419 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
6420 /// LegalizedNodes map is filled in for any results that are not expanded, the
6421 /// ExpandedNodes map is filled in for any results that are expanded, and the
6422 /// Lo/Hi values are returned.
6423 void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
6424 MVT VT = Op.getValueType();
6425 MVT NVT = TLI.getTypeToTransformTo(VT);
6426 SDNode *Node = Op.getNode();
6427 DebugLoc dl = Node->getDebugLoc();
6428 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
6429 assert(((NVT.isInteger() && NVT.bitsLT(VT)) || VT.isFloatingPoint() ||
6430 VT.isVector()) && "Cannot expand to FP value or to larger int value!");
6432 // See if we already expanded it.
6433 DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator I
6434 = ExpandedNodes.find(Op);
6435 if (I != ExpandedNodes.end()) {
6436 Lo = I->second.first;
6437 Hi = I->second.second;
6441 switch (Node->getOpcode()) {
6442 case ISD::CopyFromReg:
6443 assert(0 && "CopyFromReg must be legal!");
6444 case ISD::FP_ROUND_INREG:
6445 if (VT == MVT::ppcf128 &&
6446 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
6447 TargetLowering::Custom) {
6448 SDValue SrcLo, SrcHi, Src;
6449 ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
6450 Src = DAG.getNode(ISD::BUILD_PAIR, dl, VT, SrcLo, SrcHi);
6451 SDValue Result = TLI.LowerOperation(
6452 DAG.getNode(ISD::FP_ROUND_INREG, dl, VT, Src, Op.getOperand(1)), DAG);
6453 assert(Result.getNode()->getOpcode() == ISD::BUILD_PAIR);
6454 Lo = Result.getNode()->getOperand(0);
6455 Hi = Result.getNode()->getOperand(1);
6461 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
6463 assert(0 && "Do not know how to expand this operator!");
6465 case ISD::EXTRACT_ELEMENT:
6466 ExpandOp(Node->getOperand(0), Lo, Hi);
6467 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
6468 return ExpandOp(Hi, Lo, Hi);
6469 return ExpandOp(Lo, Lo, Hi);
6470 case ISD::EXTRACT_VECTOR_ELT:
6471 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types.
6472 Lo = ExpandEXTRACT_VECTOR_ELT(Op);
6473 return ExpandOp(Lo, Lo, Hi);
6475 Lo = DAG.getNode(ISD::UNDEF, dl, NVT);
6476 Hi = DAG.getNode(ISD::UNDEF, dl, NVT);
6478 case ISD::Constant: {
6479 unsigned NVTBits = NVT.getSizeInBits();
6480 const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue();
6481 Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT);
6482 Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT);
6485 case ISD::ConstantFP: {
6486 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
6487 if (CFP->getValueType(0) == MVT::ppcf128) {
6488 APInt api = CFP->getValueAPF().bitcastToAPInt();
6489 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
6491 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
6495 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
6496 if (getTypeAction(Lo.getValueType()) == Expand)
6497 ExpandOp(Lo, Lo, Hi);
6500 case ISD::BUILD_PAIR:
6501 // Return the operands.
6502 Lo = Node->getOperand(0);
6503 Hi = Node->getOperand(1);
6506 case ISD::MERGE_VALUES:
6507 if (Node->getNumValues() == 1) {
6508 ExpandOp(Op.getOperand(0), Lo, Hi);
6511 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y)
6512 assert(Op.getResNo() == 0 && Node->getNumValues() == 2 &&
6513 Op.getValue(1).getValueType() == MVT::Other &&
6514 "unhandled MERGE_VALUES");
6515 ExpandOp(Op.getOperand(0), Lo, Hi);
6516 // Remember that we legalized the chain.
6517 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1)));
6520 case ISD::SIGN_EXTEND_INREG:
6521 ExpandOp(Node->getOperand(0), Lo, Hi);
6522 // sext_inreg the low part if needed.
6523 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Lo, Node->getOperand(1));
6525 // The high part gets the sign extension from the lo-part. This handles
6526 // things like sextinreg V:i64 from i8.
6527 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
6528 DAG.getConstant(NVT.getSizeInBits()-1,
6529 TLI.getShiftAmountTy()));
6533 ExpandOp(Node->getOperand(0), Lo, Hi);
6534 SDValue TempLo = DAG.getNode(ISD::BSWAP, dl, NVT, Hi);
6535 Hi = DAG.getNode(ISD::BSWAP, dl, NVT, Lo);
6541 ExpandOp(Node->getOperand(0), Lo, Hi);
6542 Lo = DAG.getNode(ISD::ADD, dl, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
6543 DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
6544 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
6545 Hi = DAG.getConstant(0, NVT);
6549 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
6550 ExpandOp(Node->getOperand(0), Lo, Hi);
6551 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
6552 SDValue HLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Hi);
6553 SDValue TopNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), HLZ,
6555 SDValue LowPart = DAG.getNode(ISD::CTLZ, dl, NVT, Lo);
6556 LowPart = DAG.getNode(ISD::ADD, dl, NVT, LowPart, BitsC);
6558 Lo = DAG.getNode(ISD::SELECT, dl, NVT, TopNotZero, HLZ, LowPart);
6559 Hi = DAG.getConstant(0, NVT);
6564 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
6565 ExpandOp(Node->getOperand(0), Lo, Hi);
6566 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
6567 SDValue LTZ = DAG.getNode(ISD::CTTZ, dl, NVT, Lo);
6568 SDValue BotNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), LTZ,
6570 SDValue HiPart = DAG.getNode(ISD::CTTZ, dl, NVT, Hi);
6571 HiPart = DAG.getNode(ISD::ADD, dl, NVT, HiPart, BitsC);
6573 Lo = DAG.getNode(ISD::SELECT, dl, NVT, BotNotZero, LTZ, HiPart);
6574 Hi = DAG.getConstant(0, NVT);
6579 SDValue Ch = Node->getOperand(0); // Legalize the chain.
6580 SDValue Ptr = Node->getOperand(1); // Legalize the pointer.
6581 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
6582 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
6584 // Remember that we legalized the chain.
6585 Hi = LegalizeOp(Hi);
6586 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
6587 if (TLI.isBigEndian())
6593 LoadSDNode *LD = cast<LoadSDNode>(Node);
6594 SDValue Ch = LD->getChain(); // Legalize the chain.
6595 SDValue Ptr = LD->getBasePtr(); // Legalize the pointer.
6596 ISD::LoadExtType ExtType = LD->getExtensionType();
6597 const Value *SV = LD->getSrcValue();
6598 int SVOffset = LD->getSrcValueOffset();
6599 unsigned Alignment = LD->getAlignment();
6600 bool isVolatile = LD->isVolatile();
6602 if (ExtType == ISD::NON_EXTLOAD) {
6603 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, SV, SVOffset,
6604 isVolatile, Alignment);
6605 if (VT == MVT::f32 || VT == MVT::f64) {
6606 // f32->i32 or f64->i64 one to one expansion.
6607 // Remember that we legalized the chain.
6608 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
6609 // Recursively expand the new load.
6610 if (getTypeAction(NVT) == Expand)
6611 ExpandOp(Lo, Lo, Hi);
6615 // Increment the pointer to the other half.
6616 unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8;
6617 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
6618 DAG.getIntPtrConstant(IncrementSize));
6619 SVOffset += IncrementSize;
6620 Alignment = MinAlign(Alignment, IncrementSize);
6621 Hi = DAG.getLoad(NVT, dl, Ch, Ptr, SV, SVOffset,
6622 isVolatile, Alignment);
6624 // Build a factor node to remember that this load is independent of the
6626 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
6629 // Remember that we legalized the chain.
6630 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
6631 if (TLI.isBigEndian())
6634 MVT EVT = LD->getMemoryVT();
6636 if ((VT == MVT::f64 && EVT == MVT::f32) ||
6637 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
6638 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
6639 SDValue Load = DAG.getLoad(EVT, dl, Ch, Ptr, SV,
6640 SVOffset, isVolatile, Alignment);
6641 // Remember that we legalized the chain.
6642 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Load.getValue(1)));
6643 ExpandOp(DAG.getNode(ISD::FP_EXTEND, dl, VT, Load), Lo, Hi);
6648 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, SV,
6649 SVOffset, isVolatile, Alignment);
6651 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, SV,
6652 SVOffset, EVT, isVolatile,
6655 // Remember that we legalized the chain.
6656 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
6658 if (ExtType == ISD::SEXTLOAD) {
6659 // The high part is obtained by SRA'ing all but one of the bits of the
6661 unsigned LoSize = Lo.getValueType().getSizeInBits();
6662 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
6663 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6664 } else if (ExtType == ISD::ZEXTLOAD) {
6665 // The high part is just a zero.
6666 Hi = DAG.getConstant(0, NVT);
6667 } else /* if (ExtType == ISD::EXTLOAD) */ {
6668 // The high part is undefined.
6669 Hi = DAG.getNode(ISD::UNDEF, dl, NVT);
6676 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
6677 SDValue LL, LH, RL, RH;
6678 ExpandOp(Node->getOperand(0), LL, LH);
6679 ExpandOp(Node->getOperand(1), RL, RH);
6680 Lo = DAG.getNode(Node->getOpcode(), dl, NVT, LL, RL);
6681 Hi = DAG.getNode(Node->getOpcode(), dl, NVT, LH, RH);
6685 SDValue LL, LH, RL, RH;
6686 ExpandOp(Node->getOperand(1), LL, LH);
6687 ExpandOp(Node->getOperand(2), RL, RH);
6688 if (getTypeAction(NVT) == Expand)
6689 NVT = TLI.getTypeToExpandTo(NVT);
6690 Lo = DAG.getNode(ISD::SELECT, dl, NVT, Node->getOperand(0), LL, RL);
6692 Hi = DAG.getNode(ISD::SELECT, dl, NVT, Node->getOperand(0), LH, RH);
6695 case ISD::SELECT_CC: {
6696 SDValue TL, TH, FL, FH;
6697 ExpandOp(Node->getOperand(2), TL, TH);
6698 ExpandOp(Node->getOperand(3), FL, FH);
6699 if (getTypeAction(NVT) == Expand)
6700 NVT = TLI.getTypeToExpandTo(NVT);
6701 Lo = DAG.getNode(ISD::SELECT_CC, dl, NVT, Node->getOperand(0),
6702 Node->getOperand(1), TL, FL, Node->getOperand(4));
6704 Hi = DAG.getNode(ISD::SELECT_CC, dl, NVT, Node->getOperand(0),
6705 Node->getOperand(1), TH, FH, Node->getOperand(4));
6708 case ISD::ANY_EXTEND:
6709 // The low part is any extension of the input (which degenerates to a copy).
6710 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Node->getOperand(0));
6711 // The high part is undefined.
6712 Hi = DAG.getNode(ISD::UNDEF, dl, NVT);
6714 case ISD::SIGN_EXTEND: {
6715 // The low part is just a sign extension of the input (which degenerates to
6717 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, Node->getOperand(0));
6719 // The high part is obtained by SRA'ing all but one of the bits of the lo
6721 unsigned LoSize = Lo.getValueType().getSizeInBits();
6722 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
6723 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6726 case ISD::ZERO_EXTEND:
6727 // The low part is just a zero extension of the input (which degenerates to
6729 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
6731 // The high part is just a zero.
6732 Hi = DAG.getConstant(0, NVT);
6735 case ISD::TRUNCATE: {
6736 // The input value must be larger than this value. Expand *it*.
6738 ExpandOp(Node->getOperand(0), NewLo, Hi);
6740 // The low part is now either the right size, or it is closer. If not the
6741 // right size, make an illegal truncate so we recursively expand it.
6742 if (NewLo.getValueType() != Node->getValueType(0))
6743 NewLo = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), NewLo);
6744 ExpandOp(NewLo, Lo, Hi);
6748 case ISD::BIT_CONVERT: {
6750 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
6751 // If the target wants to, allow it to lower this itself.
6752 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6753 case Expand: assert(0 && "cannot expand FP!");
6754 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
6755 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
6757 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp), DAG);
6760 // f32 / f64 must be expanded to i32 / i64.
6761 if (VT == MVT::f32 || VT == MVT::f64) {
6762 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
6763 if (getTypeAction(NVT) == Expand)
6764 ExpandOp(Lo, Lo, Hi);
6768 // If source operand will be expanded to the same type as VT, i.e.
6769 // i64 <- f64, i32 <- f32, expand the source operand instead.
6770 MVT VT0 = Node->getOperand(0).getValueType();
6771 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
6772 ExpandOp(Node->getOperand(0), Lo, Hi);
6776 // Turn this into a load/store pair by default.
6777 if (Tmp.getNode() == 0)
6778 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT, dl);
6780 ExpandOp(Tmp, Lo, Hi);
6784 case ISD::READCYCLECOUNTER: {
6785 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
6786 TargetLowering::Custom &&
6787 "Must custom expand ReadCycleCounter");
6788 SDValue Tmp = TLI.LowerOperation(Op, DAG);
6789 assert(Tmp.getNode() && "Node must be custom expanded!");
6790 ExpandOp(Tmp.getValue(0), Lo, Hi);
6791 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6792 LegalizeOp(Tmp.getValue(1)));
6796 case ISD::ATOMIC_CMP_SWAP: {
6797 // This operation does not need a loop.
6798 SDValue Tmp = TLI.LowerOperation(Op, DAG);
6799 assert(Tmp.getNode() && "Node must be custom expanded!");
6800 ExpandOp(Tmp.getValue(0), Lo, Hi);
6801 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6802 LegalizeOp(Tmp.getValue(1)));
6806 case ISD::ATOMIC_LOAD_ADD:
6807 case ISD::ATOMIC_LOAD_SUB:
6808 case ISD::ATOMIC_LOAD_AND:
6809 case ISD::ATOMIC_LOAD_OR:
6810 case ISD::ATOMIC_LOAD_XOR:
6811 case ISD::ATOMIC_LOAD_NAND:
6812 case ISD::ATOMIC_SWAP: {
6813 // These operations require a loop to be generated. We can't do that yet,
6814 // so substitute a target-dependent pseudo and expand that later.
6815 SDValue In2Lo, In2Hi, In2;
6816 ExpandOp(Op.getOperand(2), In2Lo, In2Hi);
6817 In2 = DAG.getNode(ISD::BUILD_PAIR, dl, VT, In2Lo, In2Hi);
6818 AtomicSDNode* Anode = cast<AtomicSDNode>(Node);
6820 DAG.getAtomic(Op.getOpcode(), dl, Anode->getMemoryVT(),
6821 Op.getOperand(0), Op.getOperand(1), In2,
6822 Anode->getSrcValue(), Anode->getAlignment());
6823 SDValue Result = TLI.LowerOperation(Replace, DAG);
6824 ExpandOp(Result.getValue(0), Lo, Hi);
6825 // Remember that we legalized the chain.
6826 AddLegalizedOperand(SDValue(Node,1), LegalizeOp(Result.getValue(1)));
6830 // These operators cannot be expanded directly, emit them as calls to
6831 // library functions.
6832 case ISD::FP_TO_SINT: {
6833 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
6835 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6836 case Expand: assert(0 && "cannot expand FP!");
6837 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6838 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6841 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op), DAG);
6843 // Now that the custom expander is done, expand the result, which is still
6846 ExpandOp(Op, Lo, Hi);
6851 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Node->getOperand(0).getValueType(),
6853 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected uint-to-fp conversion!");
6854 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6858 case ISD::FP_TO_UINT: {
6859 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
6861 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6862 case Expand: assert(0 && "cannot expand FP!");
6863 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6864 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6867 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, dl, VT, Op), DAG);
6869 // Now that the custom expander is done, expand the result.
6871 ExpandOp(Op, Lo, Hi);
6876 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Node->getOperand(0).getValueType(),
6878 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
6879 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6884 // If the target wants custom lowering, do so.
6885 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6886 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
6887 SDValue Op = DAG.getNode(ISD::SHL, dl, VT, Node->getOperand(0), ShiftAmt);
6888 Op = TLI.LowerOperation(Op, DAG);
6890 // Now that the custom expander is done, expand the result, which is
6892 ExpandOp(Op, Lo, Hi);
6897 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
6898 // this X << 1 as X+X.
6899 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
6900 if (ShAmt->getAPIntValue() == 1 &&
6901 TLI.isOperationLegalOrCustom(ISD::ADDC, NVT) &&
6902 TLI.isOperationLegalOrCustom(ISD::ADDE, NVT)) {
6903 SDValue LoOps[2], HiOps[3];
6904 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
6905 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
6906 LoOps[1] = LoOps[0];
6907 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
6909 HiOps[1] = HiOps[0];
6910 HiOps[2] = Lo.getValue(1);
6911 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
6916 // If we can emit an efficient shift operation, do so now.
6917 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi, dl))
6920 // If this target supports SHL_PARTS, use it.
6921 TargetLowering::LegalizeAction Action =
6922 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
6923 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6924 Action == TargetLowering::Custom) {
6925 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0),
6926 ShiftAmt, Lo, Hi, dl);
6930 // Otherwise, emit a libcall.
6931 Lo = ExpandLibCall(RTLIB::SHL_I64, Node, false/*left shift=unsigned*/, Hi);
6936 // If the target wants custom lowering, do so.
6937 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6938 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
6939 SDValue Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
6940 Op = TLI.LowerOperation(Op, DAG);
6942 // Now that the custom expander is done, expand the result, which is
6944 ExpandOp(Op, Lo, Hi);
6949 // If we can emit an efficient shift operation, do so now.
6950 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi, dl))
6953 // If this target supports SRA_PARTS, use it.
6954 TargetLowering::LegalizeAction Action =
6955 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
6956 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6957 Action == TargetLowering::Custom) {
6958 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0),
6959 ShiftAmt, Lo, Hi, dl);
6963 // Otherwise, emit a libcall.
6964 Lo = ExpandLibCall(RTLIB::SRA_I64, Node, true/*ashr is signed*/, Hi);
6969 // If the target wants custom lowering, do so.
6970 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6971 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
6972 SDValue Op = DAG.getNode(ISD::SRL, dl, VT, Node->getOperand(0), ShiftAmt);
6973 Op = TLI.LowerOperation(Op, DAG);
6975 // Now that the custom expander is done, expand the result, which is
6977 ExpandOp(Op, Lo, Hi);
6982 // If we can emit an efficient shift operation, do so now.
6983 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi, dl))
6986 // If this target supports SRL_PARTS, use it.
6987 TargetLowering::LegalizeAction Action =
6988 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
6989 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6990 Action == TargetLowering::Custom) {
6991 ExpandShiftParts(ISD::SRL_PARTS,
6992 Node->getOperand(0), ShiftAmt, Lo, Hi, dl);
6996 // Otherwise, emit a libcall.
6997 Lo = ExpandLibCall(RTLIB::SRL_I64, Node, false/*lshr is unsigned*/, Hi);
7003 // If the target wants to custom expand this, let them.
7004 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
7005 TargetLowering::Custom) {
7006 SDValue Result = TLI.LowerOperation(Op, DAG);
7007 if (Result.getNode()) {
7008 ExpandOp(Result, Lo, Hi);
7012 // Expand the subcomponents.
7013 SDValue LHSL, LHSH, RHSL, RHSH;
7014 ExpandOp(Node->getOperand(0), LHSL, LHSH);
7015 ExpandOp(Node->getOperand(1), RHSL, RHSH);
7016 SDValue LoOps[2], HiOps[3];
7022 //cascaded check to see if any smaller size has a a carry flag.
7023 unsigned OpV = Node->getOpcode() == ISD::ADD ? ISD::ADDC : ISD::SUBC;
7024 bool hasCarry = false;
7025 for (unsigned BitSize = NVT.getSizeInBits(); BitSize != 0; BitSize /= 2) {
7026 MVT AVT = MVT::getIntegerVT(BitSize);
7027 if (TLI.isOperationLegalOrCustom(OpV, AVT)) {
7034 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
7035 if (Node->getOpcode() == ISD::ADD) {
7036 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
7037 HiOps[2] = Lo.getValue(1);
7038 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
7040 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
7041 HiOps[2] = Lo.getValue(1);
7042 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
7046 if (Node->getOpcode() == ISD::ADD) {
7047 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2);
7048 Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2);
7049 SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
7050 Lo, LoOps[0], ISD::SETULT);
7051 SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1,
7052 DAG.getConstant(1, NVT),
7053 DAG.getConstant(0, NVT));
7054 SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
7055 Lo, LoOps[1], ISD::SETULT);
7056 SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2,
7057 DAG.getConstant(1, NVT),
7059 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
7061 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2);
7062 Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2);
7063 SDValue Cmp = DAG.getSetCC(dl, NVT, LoOps[0], LoOps[1], ISD::SETULT);
7064 SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp,
7065 DAG.getConstant(1, NVT),
7066 DAG.getConstant(0, NVT));
7067 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
7075 // Expand the subcomponents.
7076 SDValue LHSL, LHSH, RHSL, RHSH;
7077 ExpandOp(Node->getOperand(0), LHSL, LHSH);
7078 ExpandOp(Node->getOperand(1), RHSL, RHSH);
7079 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
7080 SDValue LoOps[2] = { LHSL, RHSL };
7081 SDValue HiOps[3] = { LHSH, RHSH };
7083 if (Node->getOpcode() == ISD::ADDC) {
7084 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
7085 HiOps[2] = Lo.getValue(1);
7086 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
7088 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
7089 HiOps[2] = Lo.getValue(1);
7090 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
7092 // Remember that we legalized the flag.
7093 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
7098 // Expand the subcomponents.
7099 SDValue LHSL, LHSH, RHSL, RHSH;
7100 ExpandOp(Node->getOperand(0), LHSL, LHSH);
7101 ExpandOp(Node->getOperand(1), RHSL, RHSH);
7102 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
7103 SDValue LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
7104 SDValue HiOps[3] = { LHSH, RHSH };
7106 Lo = DAG.getNode(Node->getOpcode(), dl, VTList, LoOps, 3);
7107 HiOps[2] = Lo.getValue(1);
7108 Hi = DAG.getNode(Node->getOpcode(), dl, VTList, HiOps, 3);
7110 // Remember that we legalized the flag.
7111 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
7115 // If the target wants to custom expand this, let them.
7116 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
7117 SDValue New = TLI.LowerOperation(Op, DAG);
7118 if (New.getNode()) {
7119 ExpandOp(New, Lo, Hi);
7124 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT);
7125 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT);
7126 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT);
7127 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT);
7128 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
7129 SDValue LL, LH, RL, RH;
7130 ExpandOp(Node->getOperand(0), LL, LH);
7131 ExpandOp(Node->getOperand(1), RL, RH);
7132 unsigned OuterBitSize = Op.getValueSizeInBits();
7133 unsigned InnerBitSize = RH.getValueSizeInBits();
7134 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
7135 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
7136 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
7137 if (DAG.MaskedValueIsZero(Node->getOperand(0), HighMask) &&
7138 DAG.MaskedValueIsZero(Node->getOperand(1), HighMask)) {
7139 // The inputs are both zero-extended.
7141 // We can emit a umul_lohi.
7142 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
7143 Hi = SDValue(Lo.getNode(), 1);
7147 // We can emit a mulhu+mul.
7148 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
7149 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
7153 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
7154 // The input values are both sign-extended.
7156 // We can emit a smul_lohi.
7157 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
7158 Hi = SDValue(Lo.getNode(), 1);
7162 // We can emit a mulhs+mul.
7163 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
7164 Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL);
7169 // Lo,Hi = umul LHS, RHS.
7170 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
7171 DAG.getVTList(NVT, NVT), LL, RL);
7173 Hi = UMulLOHI.getValue(1);
7174 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
7175 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
7176 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
7177 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
7181 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
7182 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
7183 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
7184 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
7185 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
7186 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
7191 // If nothing else, we can make a libcall.
7192 Lo = ExpandLibCall(RTLIB::MUL_I64, Node, false/*sign irrelevant*/, Hi);
7196 Lo = ExpandLibCall(RTLIB::SDIV_I64, Node, true, Hi);
7199 Lo = ExpandLibCall(RTLIB::UDIV_I64, Node, true, Hi);
7202 Lo = ExpandLibCall(RTLIB::SREM_I64, Node, true, Hi);
7205 Lo = ExpandLibCall(RTLIB::UREM_I64, Node, true, Hi);
7209 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::ADD_F32,
7212 RTLIB::ADD_PPCF128),
7216 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::SUB_F32,
7219 RTLIB::SUB_PPCF128),
7223 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::MUL_F32,
7226 RTLIB::MUL_PPCF128),
7230 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::DIV_F32,
7233 RTLIB::DIV_PPCF128),
7236 case ISD::FP_EXTEND: {
7237 if (VT == MVT::ppcf128) {
7238 assert(Node->getOperand(0).getValueType()==MVT::f32 ||
7239 Node->getOperand(0).getValueType()==MVT::f64);
7240 const uint64_t zero = 0;
7241 if (Node->getOperand(0).getValueType()==MVT::f32)
7242 Hi = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Node->getOperand(0));
7244 Hi = Node->getOperand(0);
7245 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7248 RTLIB::Libcall LC = RTLIB::getFPEXT(Node->getOperand(0).getValueType(), VT);
7249 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!");
7250 Lo = ExpandLibCall(LC, Node, true, Hi);
7253 case ISD::FP_ROUND: {
7254 RTLIB::Libcall LC = RTLIB::getFPROUND(Node->getOperand(0).getValueType(),
7256 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!");
7257 Lo = ExpandLibCall(LC, Node, true, Hi);
7272 case ISD::FNEARBYINT:
7275 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
7276 switch(Node->getOpcode()) {
7278 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
7279 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
7282 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
7283 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
7286 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
7287 RTLIB::COS_F80, RTLIB::COS_PPCF128);
7290 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
7291 RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
7294 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
7295 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
7298 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
7299 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
7302 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
7303 RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
7306 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
7307 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
7310 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
7311 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
7314 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
7315 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128);
7318 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
7319 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128);
7322 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64,
7323 RTLIB::RINT_F80, RTLIB::RINT_PPCF128);
7325 case ISD::FNEARBYINT:
7326 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
7327 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
7330 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
7331 RTLIB::POW_PPCF128);
7334 LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64, RTLIB::POWI_F80,
7335 RTLIB::POWI_PPCF128);
7337 default: assert(0 && "Unreachable!");
7339 Lo = ExpandLibCall(LC, Node, false, Hi);
7343 if (VT == MVT::ppcf128) {
7345 ExpandOp(Node->getOperand(0), Lo, Tmp);
7346 Hi = DAG.getNode(ISD::FABS, dl, NVT, Tmp);
7347 // lo = hi==fabs(hi) ? lo : -lo;
7348 Lo = DAG.getNode(ISD::SELECT_CC, dl, NVT, Hi, Tmp,
7349 Lo, DAG.getNode(ISD::FNEG, dl, NVT, Lo),
7350 DAG.getCondCode(ISD::SETEQ));
7353 SDValue Mask = (VT == MVT::f64)
7354 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
7355 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
7356 Mask = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Mask);
7357 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
7358 Lo = DAG.getNode(ISD::AND, dl, NVT, Lo, Mask);
7359 if (getTypeAction(NVT) == Expand)
7360 ExpandOp(Lo, Lo, Hi);
7364 if (VT == MVT::ppcf128) {
7365 ExpandOp(Node->getOperand(0), Lo, Hi);
7366 Lo = DAG.getNode(ISD::FNEG, dl, MVT::f64, Lo);
7367 Hi = DAG.getNode(ISD::FNEG, dl, MVT::f64, Hi);
7370 SDValue Mask = (VT == MVT::f64)
7371 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
7372 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
7373 Mask = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Mask);
7374 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
7375 Lo = DAG.getNode(ISD::XOR, dl, NVT, Lo, Mask);
7376 if (getTypeAction(NVT) == Expand)
7377 ExpandOp(Lo, Lo, Hi);
7380 case ISD::FCOPYSIGN: {
7381 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
7382 if (getTypeAction(NVT) == Expand)
7383 ExpandOp(Lo, Lo, Hi);
7386 case ISD::SINT_TO_FP:
7387 case ISD::UINT_TO_FP: {
7388 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
7389 MVT SrcVT = Node->getOperand(0).getValueType();
7391 // Promote the operand if needed. Do this before checking for
7392 // ppcf128 so conversions of i16 and i8 work.
7393 if (getTypeAction(SrcVT) == Promote) {
7394 SDValue Tmp = PromoteOp(Node->getOperand(0));
7396 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Tmp.getValueType(), Tmp,
7397 DAG.getValueType(SrcVT))
7398 : DAG.getZeroExtendInReg(Tmp, dl, SrcVT);
7399 Node = DAG.UpdateNodeOperands(Op, Tmp).getNode();
7400 SrcVT = Node->getOperand(0).getValueType();
7403 if (VT == MVT::ppcf128 && SrcVT == MVT::i32) {
7404 static const uint64_t zero = 0;
7406 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f64,
7407 Node->getOperand(0)));
7408 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7410 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
7411 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f64,
7412 Node->getOperand(0)));
7413 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7414 Hi = DAG.getNode(ISD::BUILD_PAIR, dl, VT, Lo, Hi);
7415 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
7416 ExpandOp(DAG.getNode(ISD::SELECT_CC, dl,
7417 MVT::ppcf128, Node->getOperand(0),
7418 DAG.getConstant(0, MVT::i32),
7419 DAG.getNode(ISD::FADD, dl, MVT::ppcf128, Hi,
7421 APFloat(APInt(128, 2, TwoE32)),
7424 DAG.getCondCode(ISD::SETLT)),
7429 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) {
7430 // si64->ppcf128 done by libcall, below
7431 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
7432 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, dl, MVT::ppcf128,
7433 Node->getOperand(0)), Lo, Hi);
7434 Hi = DAG.getNode(ISD::BUILD_PAIR, dl, VT, Lo, Hi);
7435 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
7436 ExpandOp(DAG.getNode(ISD::SELECT_CC, dl, MVT::ppcf128,
7437 Node->getOperand(0),
7438 DAG.getConstant(0, MVT::i64),
7439 DAG.getNode(ISD::FADD, dl, MVT::ppcf128, Hi,
7441 APFloat(APInt(128, 2, TwoE64)),
7444 DAG.getCondCode(ISD::SETLT)),
7449 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
7450 Node->getOperand(0), dl);
7451 if (getTypeAction(Lo.getValueType()) == Expand)
7452 // float to i32 etc. can be 'expanded' to a single node.
7453 ExpandOp(Lo, Lo, Hi);
7458 // Make sure the resultant values have been legalized themselves, unless this
7459 // is a type that requires multi-step expansion.
7460 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
7461 Lo = LegalizeOp(Lo);
7463 // Don't legalize the high part if it is expanded to a single node.
7464 Hi = LegalizeOp(Hi);
7467 // Remember in a map if the values will be reused later.
7469 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
7470 assert(isNew && "Value already expanded?!?");
7474 /// SplitVectorOp - Given an operand of vector type, break it down into
7475 /// two smaller values, still of vector type.
7476 void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
7478 assert(Op.getValueType().isVector() && "Cannot split non-vector type!");
7479 SDNode *Node = Op.getNode();
7480 DebugLoc dl = Node->getDebugLoc();
7481 unsigned NumElements = Op.getValueType().getVectorNumElements();
7482 assert(NumElements > 1 && "Cannot split a single element vector!");
7484 MVT NewEltVT = Op.getValueType().getVectorElementType();
7486 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
7487 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
7489 MVT NewVT_Lo = MVT::getVectorVT(NewEltVT, NewNumElts_Lo);
7490 MVT NewVT_Hi = MVT::getVectorVT(NewEltVT, NewNumElts_Hi);
7492 // See if we already split it.
7493 std::map<SDValue, std::pair<SDValue, SDValue> >::iterator I
7494 = SplitNodes.find(Op);
7495 if (I != SplitNodes.end()) {
7496 Lo = I->second.first;
7497 Hi = I->second.second;
7501 switch (Node->getOpcode()) {
7506 assert(0 && "Unhandled operation in SplitVectorOp!");
7508 Lo = DAG.getNode(ISD::UNDEF, dl, NewVT_Lo);
7509 Hi = DAG.getNode(ISD::UNDEF, dl, NewVT_Hi);
7511 case ISD::BUILD_PAIR:
7512 Lo = Node->getOperand(0);
7513 Hi = Node->getOperand(1);
7515 case ISD::INSERT_VECTOR_ELT: {
7516 if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) {
7517 SplitVectorOp(Node->getOperand(0), Lo, Hi);
7518 unsigned Index = Idx->getZExtValue();
7519 SDValue ScalarOp = Node->getOperand(1);
7520 if (Index < NewNumElts_Lo)
7521 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVT_Lo, Lo, ScalarOp,
7522 DAG.getIntPtrConstant(Index));
7524 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVT_Hi, Hi, ScalarOp,
7525 DAG.getIntPtrConstant(Index - NewNumElts_Lo));
7528 SDValue Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0),
7529 Node->getOperand(1),
7530 Node->getOperand(2), dl);
7531 SplitVectorOp(Tmp, Lo, Hi);
7534 case ISD::VECTOR_SHUFFLE: {
7535 // Build the low part.
7536 SDValue Mask = Node->getOperand(2);
7537 SmallVector<SDValue, 8> Ops;
7538 MVT PtrVT = TLI.getPointerTy();
7540 // Insert all of the elements from the input that are needed. We use
7541 // buildvector of extractelement here because the input vectors will have
7542 // to be legalized, so this makes the code simpler.
7543 for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
7544 SDValue IdxNode = Mask.getOperand(i);
7545 if (IdxNode.getOpcode() == ISD::UNDEF) {
7546 Ops.push_back(DAG.getNode(ISD::UNDEF, dl, NewEltVT));
7549 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
7550 SDValue InVec = Node->getOperand(0);
7551 if (Idx >= NumElements) {
7552 InVec = Node->getOperand(1);
7555 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewEltVT, InVec,
7556 DAG.getConstant(Idx, PtrVT)));
7558 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Lo, &Ops[0], Ops.size());
7561 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
7562 SDValue IdxNode = Mask.getOperand(i);
7563 if (IdxNode.getOpcode() == ISD::UNDEF) {
7564 Ops.push_back(DAG.getNode(ISD::UNDEF, dl, NewEltVT));
7567 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
7568 SDValue InVec = Node->getOperand(0);
7569 if (Idx >= NumElements) {
7570 InVec = Node->getOperand(1);
7573 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewEltVT, InVec,
7574 DAG.getConstant(Idx, PtrVT)));
7576 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Hi, &Ops[0], Ops.size());
7579 case ISD::BUILD_VECTOR: {
7580 SmallVector<SDValue, 8> LoOps(Node->op_begin(),
7581 Node->op_begin()+NewNumElts_Lo);
7582 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Lo, &LoOps[0], LoOps.size());
7584 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
7586 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Hi, &HiOps[0], HiOps.size());
7589 case ISD::CONCAT_VECTORS: {
7590 // FIXME: Handle non-power-of-two vectors?
7591 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
7592 if (NewNumSubvectors == 1) {
7593 Lo = Node->getOperand(0);
7594 Hi = Node->getOperand(1);
7596 SmallVector<SDValue, 8> LoOps(Node->op_begin(),
7597 Node->op_begin()+NewNumSubvectors);
7598 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewVT_Lo,
7599 &LoOps[0], LoOps.size());
7601 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumSubvectors,
7603 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewVT_Hi,
7604 &HiOps[0], HiOps.size());
7608 case ISD::EXTRACT_SUBVECTOR: {
7609 SDValue Vec = Op.getOperand(0);
7610 SDValue Idx = Op.getOperand(1);
7611 MVT IdxVT = Idx.getValueType();
7613 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT_Lo, Vec, Idx);
7614 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx);
7616 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT_Hi, Vec,
7617 DAG.getConstant(CIdx->getZExtValue() + NewNumElts_Lo,
7620 Idx = DAG.getNode(ISD::ADD, dl, IdxVT, Idx,
7621 DAG.getConstant(NewNumElts_Lo, IdxVT));
7622 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT_Hi, Vec, Idx);
7627 SDValue Cond = Node->getOperand(0);
7629 SDValue LL, LH, RL, RH;
7630 SplitVectorOp(Node->getOperand(1), LL, LH);
7631 SplitVectorOp(Node->getOperand(2), RL, RH);
7633 if (Cond.getValueType().isVector()) {
7634 // Handle a vector merge.
7636 SplitVectorOp(Cond, CL, CH);
7637 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, CL, LL, RL);
7638 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, CH, LH, RH);
7640 // Handle a simple select with vector operands.
7641 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, Cond, LL, RL);
7642 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, Cond, LH, RH);
7646 case ISD::SELECT_CC: {
7647 SDValue CondLHS = Node->getOperand(0);
7648 SDValue CondRHS = Node->getOperand(1);
7649 SDValue CondCode = Node->getOperand(4);
7651 SDValue LL, LH, RL, RH;
7652 SplitVectorOp(Node->getOperand(2), LL, LH);
7653 SplitVectorOp(Node->getOperand(3), RL, RH);
7655 // Handle a simple select with vector operands.
7656 Lo = DAG.getNode(ISD::SELECT_CC, dl, NewVT_Lo, CondLHS, CondRHS,
7658 Hi = DAG.getNode(ISD::SELECT_CC, dl, NewVT_Hi, CondLHS, CondRHS,
7663 SDValue LL, LH, RL, RH;
7664 SplitVectorOp(Node->getOperand(0), LL, LH);
7665 SplitVectorOp(Node->getOperand(1), RL, RH);
7666 Lo = DAG.getNode(ISD::VSETCC, dl, NewVT_Lo, LL, RL, Node->getOperand(2));
7667 Hi = DAG.getNode(ISD::VSETCC, dl, NewVT_Hi, LH, RH, Node->getOperand(2));
7689 SDValue LL, LH, RL, RH;
7690 SplitVectorOp(Node->getOperand(0), LL, LH);
7691 SplitVectorOp(Node->getOperand(1), RL, RH);
7693 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, LL, RL);
7694 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, LH, RH);
7700 SplitVectorOp(Node->getOperand(0), L, H);
7702 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, L, Node->getOperand(1));
7703 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, H, Node->getOperand(1));
7719 case ISD::FP_TO_SINT:
7720 case ISD::FP_TO_UINT:
7721 case ISD::SINT_TO_FP:
7722 case ISD::UINT_TO_FP:
7724 case ISD::ANY_EXTEND:
7725 case ISD::SIGN_EXTEND:
7726 case ISD::ZERO_EXTEND:
7727 case ISD::FP_EXTEND: {
7729 SplitVectorOp(Node->getOperand(0), L, H);
7731 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, L);
7732 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, H);
7735 case ISD::CONVERT_RNDSAT: {
7736 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
7738 SplitVectorOp(Node->getOperand(0), L, H);
7739 SDValue DTyOpL = DAG.getValueType(NewVT_Lo);
7740 SDValue DTyOpH = DAG.getValueType(NewVT_Hi);
7741 SDValue STyOpL = DAG.getValueType(L.getValueType());
7742 SDValue STyOpH = DAG.getValueType(H.getValueType());
7744 SDValue RndOp = Node->getOperand(3);
7745 SDValue SatOp = Node->getOperand(4);
7747 Lo = DAG.getConvertRndSat(NewVT_Lo, L, DTyOpL, STyOpL,
7748 RndOp, SatOp, CvtCode);
7749 Hi = DAG.getConvertRndSat(NewVT_Hi, H, DTyOpH, STyOpH,
7750 RndOp, SatOp, CvtCode);
7754 LoadSDNode *LD = cast<LoadSDNode>(Node);
7755 SDValue Ch = LD->getChain();
7756 SDValue Ptr = LD->getBasePtr();
7757 ISD::LoadExtType ExtType = LD->getExtensionType();
7758 const Value *SV = LD->getSrcValue();
7759 int SVOffset = LD->getSrcValueOffset();
7760 MVT MemoryVT = LD->getMemoryVT();
7761 unsigned Alignment = LD->getAlignment();
7762 bool isVolatile = LD->isVolatile();
7764 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
7765 SDValue Offset = DAG.getNode(ISD::UNDEF, dl, Ptr.getValueType());
7767 MVT MemNewEltVT = MemoryVT.getVectorElementType();
7768 MVT MemNewVT_Lo = MVT::getVectorVT(MemNewEltVT, NewNumElts_Lo);
7769 MVT MemNewVT_Hi = MVT::getVectorVT(MemNewEltVT, NewNumElts_Hi);
7771 Lo = DAG.getLoad(ISD::UNINDEXED, dl, ExtType,
7772 NewVT_Lo, Ch, Ptr, Offset,
7773 SV, SVOffset, MemNewVT_Lo, isVolatile, Alignment);
7774 unsigned IncrementSize = NewNumElts_Lo * MemNewEltVT.getSizeInBits()/8;
7775 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
7776 DAG.getIntPtrConstant(IncrementSize));
7777 SVOffset += IncrementSize;
7778 Alignment = MinAlign(Alignment, IncrementSize);
7779 Hi = DAG.getLoad(ISD::UNINDEXED, dl, ExtType,
7780 NewVT_Hi, Ch, Ptr, Offset,
7781 SV, SVOffset, MemNewVT_Hi, isVolatile, Alignment);
7783 // Build a factor node to remember that this load is independent of the
7785 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
7788 // Remember that we legalized the chain.
7789 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
7792 case ISD::BIT_CONVERT: {
7793 // We know the result is a vector. The input may be either a vector or a
7795 SDValue InOp = Node->getOperand(0);
7796 if (!InOp.getValueType().isVector() ||
7797 InOp.getValueType().getVectorNumElements() == 1) {
7798 // The input is a scalar or single-element vector.
7799 // Lower to a store/load so that it can be split.
7800 // FIXME: this could be improved probably.
7801 unsigned LdAlign = TLI.getTargetData()->getPrefTypeAlignment(
7802 Op.getValueType().getTypeForMVT());
7803 SDValue Ptr = DAG.CreateStackTemporary(InOp.getValueType(), LdAlign);
7804 int FI = cast<FrameIndexSDNode>(Ptr.getNode())->getIndex();
7806 SDValue St = DAG.getStore(DAG.getEntryNode(), dl,
7808 PseudoSourceValue::getFixedStack(FI), 0);
7809 InOp = DAG.getLoad(Op.getValueType(), dl, St, Ptr,
7810 PseudoSourceValue::getFixedStack(FI), 0);
7812 // Split the vector and convert each of the pieces now.
7813 SplitVectorOp(InOp, Lo, Hi);
7814 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT_Lo, Lo);
7815 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT_Hi, Hi);
7820 // Remember in a map if the values will be reused later.
7822 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
7823 assert(isNew && "Value already split?!?");
7828 /// ScalarizeVectorOp - Given an operand of single-element vector type
7829 /// (e.g. v1f32), convert it into the equivalent operation that returns a
7830 /// scalar (e.g. f32) value.
7831 SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) {
7832 assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!");
7833 SDNode *Node = Op.getNode();
7834 DebugLoc dl = Node->getDebugLoc();
7835 MVT NewVT = Op.getValueType().getVectorElementType();
7836 assert(Op.getValueType().getVectorNumElements() == 1);
7838 // See if we already scalarized it.
7839 std::map<SDValue, SDValue>::iterator I = ScalarizedNodes.find(Op);
7840 if (I != ScalarizedNodes.end()) return I->second;
7843 switch (Node->getOpcode()) {
7846 Node->dump(&DAG); cerr << "\n";
7848 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
7865 Result = DAG.getNode(Node->getOpcode(), dl,
7867 ScalarizeVectorOp(Node->getOperand(0)),
7868 ScalarizeVectorOp(Node->getOperand(1)));
7880 case ISD::FP_TO_SINT:
7881 case ISD::FP_TO_UINT:
7882 case ISD::SINT_TO_FP:
7883 case ISD::UINT_TO_FP:
7884 case ISD::SIGN_EXTEND:
7885 case ISD::ZERO_EXTEND:
7886 case ISD::ANY_EXTEND:
7888 case ISD::FP_EXTEND:
7889 Result = DAG.getNode(Node->getOpcode(), dl,
7891 ScalarizeVectorOp(Node->getOperand(0)));
7893 case ISD::CONVERT_RNDSAT: {
7894 SDValue Op0 = ScalarizeVectorOp(Node->getOperand(0));
7895 Result = DAG.getConvertRndSat(NewVT, Op0,
7896 DAG.getValueType(NewVT),
7897 DAG.getValueType(Op0.getValueType()),
7898 Node->getOperand(3),
7899 Node->getOperand(4),
7900 cast<CvtRndSatSDNode>(Node)->getCvtCode());
7905 Result = DAG.getNode(Node->getOpcode(), dl,
7907 ScalarizeVectorOp(Node->getOperand(0)),
7908 Node->getOperand(1));
7911 LoadSDNode *LD = cast<LoadSDNode>(Node);
7912 SDValue Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
7913 SDValue Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
7914 ISD::LoadExtType ExtType = LD->getExtensionType();
7915 const Value *SV = LD->getSrcValue();
7916 int SVOffset = LD->getSrcValueOffset();
7917 MVT MemoryVT = LD->getMemoryVT();
7918 unsigned Alignment = LD->getAlignment();
7919 bool isVolatile = LD->isVolatile();
7921 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
7922 SDValue Offset = DAG.getNode(ISD::UNDEF, dl, Ptr.getValueType());
7924 Result = DAG.getLoad(ISD::UNINDEXED, dl, ExtType,
7925 NewVT, Ch, Ptr, Offset, SV, SVOffset,
7926 MemoryVT.getVectorElementType(),
7927 isVolatile, Alignment);
7929 // Remember that we legalized the chain.
7930 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
7933 case ISD::BUILD_VECTOR:
7934 Result = Node->getOperand(0);
7936 case ISD::INSERT_VECTOR_ELT:
7937 // Returning the inserted scalar element.
7938 Result = Node->getOperand(1);
7940 case ISD::CONCAT_VECTORS:
7941 assert(Node->getOperand(0).getValueType() == NewVT &&
7942 "Concat of non-legal vectors not yet supported!");
7943 Result = Node->getOperand(0);
7945 case ISD::VECTOR_SHUFFLE: {
7946 // Figure out if the scalar is the LHS or RHS and return it.
7947 SDValue EltNum = Node->getOperand(2).getOperand(0);
7948 if (cast<ConstantSDNode>(EltNum)->getZExtValue())
7949 Result = ScalarizeVectorOp(Node->getOperand(1));
7951 Result = ScalarizeVectorOp(Node->getOperand(0));
7954 case ISD::EXTRACT_SUBVECTOR:
7955 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT,
7956 Node->getOperand(0), Node->getOperand(1));
7958 case ISD::BIT_CONVERT: {
7959 SDValue Op0 = Op.getOperand(0);
7960 if (Op0.getValueType().getVectorNumElements() == 1)
7961 Op0 = ScalarizeVectorOp(Op0);
7962 Result = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, Op0);
7966 Result = DAG.getNode(ISD::SELECT, dl, NewVT, Op.getOperand(0),
7967 ScalarizeVectorOp(Op.getOperand(1)),
7968 ScalarizeVectorOp(Op.getOperand(2)));
7970 case ISD::SELECT_CC:
7971 Result = DAG.getNode(ISD::SELECT_CC, dl, NewVT, Node->getOperand(0),
7972 Node->getOperand(1),
7973 ScalarizeVectorOp(Op.getOperand(2)),
7974 ScalarizeVectorOp(Op.getOperand(3)),
7975 Node->getOperand(4));
7978 SDValue Op0 = ScalarizeVectorOp(Op.getOperand(0));
7979 SDValue Op1 = ScalarizeVectorOp(Op.getOperand(1));
7980 Result = DAG.getNode(ISD::SETCC, dl,
7981 TLI.getSetCCResultType(Op0.getValueType()),
7982 Op0, Op1, Op.getOperand(2));
7983 Result = DAG.getNode(ISD::SELECT, dl, NewVT, Result,
7984 DAG.getConstant(-1ULL, NewVT),
7985 DAG.getConstant(0ULL, NewVT));
7990 if (TLI.isTypeLegal(NewVT))
7991 Result = LegalizeOp(Result);
7992 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
7993 assert(isNew && "Value already scalarized?");
7999 SDValue SelectionDAGLegalize::WidenVectorOp(SDValue Op, MVT WidenVT) {
8000 std::map<SDValue, SDValue>::iterator I = WidenNodes.find(Op);
8001 if (I != WidenNodes.end()) return I->second;
8003 MVT VT = Op.getValueType();
8004 assert(VT.isVector() && "Cannot widen non-vector type!");
8007 SDNode *Node = Op.getNode();
8008 DebugLoc dl = Node->getDebugLoc();
8009 MVT EVT = VT.getVectorElementType();
8011 unsigned NumElts = VT.getVectorNumElements();
8012 unsigned NewNumElts = WidenVT.getVectorNumElements();
8013 assert(NewNumElts > NumElts && "Cannot widen to smaller type!");
8014 assert(NewNumElts < 17);
8016 // When widen is called, it is assumed that it is more efficient to use a
8017 // wide type. The default action is to widen to operation to a wider legal
8018 // vector type and then do the operation if it is legal by calling LegalizeOp
8019 // again. If there is no vector equivalent, we will unroll the operation, do
8020 // it, and rebuild the vector. If most of the operations are vectorizible to
8021 // the legal type, the resulting code will be more efficient. If this is not
8022 // the case, the resulting code will preform badly as we end up generating
8023 // code to pack/unpack the results. It is the function that calls widen
8024 // that is responsible for seeing this doesn't happen.
8025 switch (Node->getOpcode()) {
8030 assert(0 && "Unexpected operation in WidenVectorOp!");
8032 case ISD::CopyFromReg:
8033 assert(0 && "CopyFromReg doesn't need widening!");
8035 case ISD::ConstantFP:
8036 // To build a vector of these elements, clients should call BuildVector
8037 // and with each element instead of creating a node with a vector type
8038 assert(0 && "Unexpected operation in WidenVectorOp!");
8040 // Variable Arguments with vector types doesn't make any sense to me
8041 assert(0 && "Unexpected operation in WidenVectorOp!");
8044 Result = DAG.getNode(ISD::UNDEF, dl, WidenVT);
8046 case ISD::BUILD_VECTOR: {
8047 // Build a vector with undefined for the new nodes
8048 SDValueVector NewOps(Node->op_begin(), Node->op_end());
8049 for (unsigned i = NumElts; i < NewNumElts; ++i) {
8050 NewOps.push_back(DAG.getNode(ISD::UNDEF, dl, EVT));
8052 Result = DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT,
8053 &NewOps[0], NewOps.size());
8056 case ISD::INSERT_VECTOR_ELT: {
8057 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8058 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, WidenVT, Tmp1,
8059 Node->getOperand(1), Node->getOperand(2));
8062 case ISD::VECTOR_SHUFFLE: {
8063 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8064 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT);
8065 // VECTOR_SHUFFLE 3rd operand must be a constant build vector that is
8066 // used as permutation array. We build the vector here instead of widening
8067 // because we don't want to legalize and have it turned to something else.
8068 SDValue PermOp = Node->getOperand(2);
8069 SDValueVector NewOps;
8070 MVT PVT = PermOp.getValueType().getVectorElementType();
8071 for (unsigned i = 0; i < NumElts; ++i) {
8072 if (PermOp.getOperand(i).getOpcode() == ISD::UNDEF) {
8073 NewOps.push_back(PermOp.getOperand(i));
8076 cast<ConstantSDNode>(PermOp.getOperand(i))->getZExtValue();
8077 if (Idx < NumElts) {
8078 NewOps.push_back(PermOp.getOperand(i));
8081 NewOps.push_back(DAG.getConstant(Idx + NewNumElts - NumElts,
8082 PermOp.getOperand(i).getValueType()));
8086 for (unsigned i = NumElts; i < NewNumElts; ++i) {
8087 NewOps.push_back(DAG.getNode(ISD::UNDEF, dl, PVT));
8090 SDValue Tmp3 = DAG.getNode(ISD::BUILD_VECTOR, dl,
8091 MVT::getVectorVT(PVT, NewOps.size()),
8092 &NewOps[0], NewOps.size());
8094 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, WidenVT, Tmp1, Tmp2, Tmp3);
8098 // If the load widen returns true, we can use a single load for the
8099 // vector. Otherwise, it is returning a token factor for multiple
8102 if (LoadWidenVectorOp(Result, TFOp, Op, WidenVT))
8103 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TFOp.getValue(1)));
8105 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TFOp.getValue(0)));
8109 case ISD::BIT_CONVERT: {
8110 SDValue Tmp1 = Node->getOperand(0);
8111 // Converts between two different types so we need to determine
8112 // the correct widen type for the input operand.
8113 MVT InVT = Tmp1.getValueType();
8114 unsigned WidenSize = WidenVT.getSizeInBits();
8115 if (InVT.isVector()) {
8116 MVT InEltVT = InVT.getVectorElementType();
8117 unsigned InEltSize = InEltVT.getSizeInBits();
8118 assert(WidenSize % InEltSize == 0 &&
8119 "can not widen bit convert that are not multiple of element type");
8120 MVT NewInWidenVT = MVT::getVectorVT(InEltVT, WidenSize / InEltSize);
8121 Tmp1 = WidenVectorOp(Tmp1, NewInWidenVT);
8122 assert(Tmp1.getValueType().getSizeInBits() == WidenVT.getSizeInBits());
8123 Result = DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, Tmp1);
8125 // If the result size is a multiple of the input size, widen the input
8126 // and then convert.
8127 unsigned InSize = InVT.getSizeInBits();
8128 assert(WidenSize % InSize == 0 &&
8129 "can not widen bit convert that are not multiple of element type");
8130 unsigned NewNumElts = WidenSize / InSize;
8131 SmallVector<SDValue, 16> Ops(NewNumElts);
8132 SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, InVT);
8134 for (unsigned i = 1; i < NewNumElts; ++i)
8137 MVT NewInVT = MVT::getVectorVT(InVT, NewNumElts);
8138 Result = DAG.getNode(ISD::BUILD_VECTOR, dl, NewInVT, &Ops[0], NewNumElts);
8139 Result = DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, Result);
8144 case ISD::SINT_TO_FP:
8145 case ISD::UINT_TO_FP:
8146 case ISD::FP_TO_SINT:
8147 case ISD::FP_TO_UINT:
8148 case ISD::FP_ROUND: {
8149 SDValue Tmp1 = Node->getOperand(0);
8150 // Converts between two different types so we need to determine
8151 // the correct widen type for the input operand.
8152 MVT TVT = Tmp1.getValueType();
8153 assert(TVT.isVector() && "can not widen non vector type");
8154 MVT TEVT = TVT.getVectorElementType();
8155 MVT TWidenVT = MVT::getVectorVT(TEVT, NewNumElts);
8156 Tmp1 = WidenVectorOp(Tmp1, TWidenVT);
8157 assert(Tmp1.getValueType().getVectorNumElements() == NewNumElts);
8158 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1);
8162 case ISD::FP_EXTEND:
8163 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
8165 case ISD::SIGN_EXTEND:
8166 case ISD::ZERO_EXTEND:
8167 case ISD::ANY_EXTEND:
8168 case ISD::SIGN_EXTEND_INREG:
8177 // Unary op widening
8179 Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8180 assert(Tmp1.getValueType() == WidenVT);
8181 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1);
8184 case ISD::CONVERT_RNDSAT: {
8185 SDValue RndOp = Node->getOperand(3);
8186 SDValue SatOp = Node->getOperand(4);
8187 SDValue SrcOp = Node->getOperand(0);
8189 // Converts between two different types so we need to determine
8190 // the correct widen type for the input operand.
8191 MVT SVT = SrcOp.getValueType();
8192 assert(SVT.isVector() && "can not widen non vector type");
8193 MVT SEVT = SVT.getVectorElementType();
8194 MVT SWidenVT = MVT::getVectorVT(SEVT, NewNumElts);
8196 SrcOp = WidenVectorOp(SrcOp, SWidenVT);
8197 assert(SrcOp.getValueType() == WidenVT);
8198 SDValue DTyOp = DAG.getValueType(WidenVT);
8199 SDValue STyOp = DAG.getValueType(SrcOp.getValueType());
8200 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
8202 Result = DAG.getConvertRndSat(WidenVT, SrcOp, DTyOp, STyOp,
8203 RndOp, SatOp, CvtCode);
8223 case ISD::FCOPYSIGN:
8227 // Binary op widening
8228 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8229 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT);
8230 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT);
8231 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1, Tmp2);
8238 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8239 assert(Tmp1.getValueType() == WidenVT);
8240 SDValue ShOp = Node->getOperand(1);
8241 MVT ShVT = ShOp.getValueType();
8242 MVT NewShVT = MVT::getVectorVT(ShVT.getVectorElementType(),
8243 WidenVT.getVectorNumElements());
8244 ShOp = WidenVectorOp(ShOp, NewShVT);
8245 assert(ShOp.getValueType() == NewShVT);
8246 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1, ShOp);
8250 case ISD::EXTRACT_VECTOR_ELT: {
8251 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8252 assert(Tmp1.getValueType() == WidenVT);
8253 Result = DAG.getNode(Node->getOpcode(), dl, EVT, Tmp1, Node->getOperand(1));
8256 case ISD::CONCAT_VECTORS: {
8257 // We concurrently support only widen on a multiple of the incoming vector.
8258 // We could widen on a multiple of the incoming operand if necessary.
8259 unsigned NumConcat = NewNumElts / NumElts;
8260 assert(NewNumElts % NumElts == 0 && "Can widen only a multiple of vector");
8261 SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, VT);
8262 SmallVector<SDValue, 8> MOps;
8264 for (unsigned i = 1; i != NumConcat; ++i) {
8265 MOps.push_back(UndefVal);
8267 Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
8268 &MOps[0], MOps.size()));
8271 case ISD::EXTRACT_SUBVECTOR: {
8272 SDValue Tmp1 = Node->getOperand(0);
8273 SDValue Idx = Node->getOperand(1);
8274 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx);
8275 if (CIdx && CIdx->getZExtValue() == 0) {
8276 // Since we are access the start of the vector, the incoming
8277 // vector type might be the proper.
8278 MVT Tmp1VT = Tmp1.getValueType();
8279 if (Tmp1VT == WidenVT)
8282 unsigned Tmp1VTNumElts = Tmp1VT.getVectorNumElements();
8283 if (Tmp1VTNumElts < NewNumElts)
8284 Result = WidenVectorOp(Tmp1, WidenVT);
8286 Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, Tmp1, Idx);
8288 } else if (NewNumElts % NumElts == 0) {
8289 // Widen the extracted subvector.
8290 unsigned NumConcat = NewNumElts / NumElts;
8291 SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, VT);
8292 SmallVector<SDValue, 8> MOps;
8294 for (unsigned i = 1; i != NumConcat; ++i) {
8295 MOps.push_back(UndefVal);
8297 Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
8298 &MOps[0], MOps.size()));
8300 assert(0 && "can not widen extract subvector");
8301 // This could be implemented using insert and build vector but I would
8302 // like to see when this happens.
8308 // Determine new condition widen type and widen
8309 SDValue Cond1 = Node->getOperand(0);
8310 MVT CondVT = Cond1.getValueType();
8311 assert(CondVT.isVector() && "can not widen non vector type");
8312 MVT CondEVT = CondVT.getVectorElementType();
8313 MVT CondWidenVT = MVT::getVectorVT(CondEVT, NewNumElts);
8314 Cond1 = WidenVectorOp(Cond1, CondWidenVT);
8315 assert(Cond1.getValueType() == CondWidenVT && "Condition not widen");
8317 SDValue Tmp1 = WidenVectorOp(Node->getOperand(1), WidenVT);
8318 SDValue Tmp2 = WidenVectorOp(Node->getOperand(2), WidenVT);
8319 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT);
8320 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Cond1, Tmp1, Tmp2);
8324 case ISD::SELECT_CC: {
8325 // Determine new condition widen type and widen
8326 SDValue Cond1 = Node->getOperand(0);
8327 SDValue Cond2 = Node->getOperand(1);
8328 MVT CondVT = Cond1.getValueType();
8329 assert(CondVT.isVector() && "can not widen non vector type");
8330 assert(CondVT == Cond2.getValueType() && "mismatch lhs/rhs");
8331 MVT CondEVT = CondVT.getVectorElementType();
8332 MVT CondWidenVT = MVT::getVectorVT(CondEVT, NewNumElts);
8333 Cond1 = WidenVectorOp(Cond1, CondWidenVT);
8334 Cond2 = WidenVectorOp(Cond2, CondWidenVT);
8335 assert(Cond1.getValueType() == CondWidenVT &&
8336 Cond2.getValueType() == CondWidenVT && "condition not widen");
8338 SDValue Tmp1 = WidenVectorOp(Node->getOperand(2), WidenVT);
8339 SDValue Tmp2 = WidenVectorOp(Node->getOperand(3), WidenVT);
8340 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT &&
8341 "operands not widen");
8342 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Cond1, Cond2, Tmp1,
8343 Tmp2, Node->getOperand(4));
8347 // Determine widen for the operand
8348 SDValue Tmp1 = Node->getOperand(0);
8349 MVT TmpVT = Tmp1.getValueType();
8350 assert(TmpVT.isVector() && "can not widen non vector type");
8351 MVT TmpEVT = TmpVT.getVectorElementType();
8352 MVT TmpWidenVT = MVT::getVectorVT(TmpEVT, NewNumElts);
8353 Tmp1 = WidenVectorOp(Tmp1, TmpWidenVT);
8354 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), TmpWidenVT);
8355 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1, Tmp2,
8356 Node->getOperand(2));
8359 case ISD::ATOMIC_CMP_SWAP:
8360 case ISD::ATOMIC_LOAD_ADD:
8361 case ISD::ATOMIC_LOAD_SUB:
8362 case ISD::ATOMIC_LOAD_AND:
8363 case ISD::ATOMIC_LOAD_OR:
8364 case ISD::ATOMIC_LOAD_XOR:
8365 case ISD::ATOMIC_LOAD_NAND:
8366 case ISD::ATOMIC_LOAD_MIN:
8367 case ISD::ATOMIC_LOAD_MAX:
8368 case ISD::ATOMIC_LOAD_UMIN:
8369 case ISD::ATOMIC_LOAD_UMAX:
8370 case ISD::ATOMIC_SWAP: {
8371 // For now, we assume that using vectors for these operations don't make
8372 // much sense so we just split it. We return an empty result
8374 SplitVectorOp(Op, X, Y);
8379 } // end switch (Node->getOpcode())
8381 assert(Result.getNode() && "Didn't set a result!");
8383 Result = LegalizeOp(Result);
8385 AddWidenedOperand(Op, Result);
8389 // Utility function to find a legal vector type and its associated element
8390 // type from a preferred width and whose vector type must be the same size
8392 // TLI: Target lowering used to determine legal types
8393 // Width: Preferred width of element type
8394 // VVT: Vector value type whose size we must match.
8395 // Returns VecEVT and EVT - the vector type and its associated element type
8396 static void FindWidenVecType(const TargetLowering &TLI, unsigned Width, MVT VVT,
8397 MVT& EVT, MVT& VecEVT) {
8398 // We start with the preferred width, make it a power of 2 and see if
8399 // we can find a vector type of that width. If not, we reduce it by
8400 // another power of 2. If we have widen the type, a vector of bytes should
8402 assert(TLI.isTypeLegal(VVT));
8403 unsigned EWidth = Width + 1;
8406 EWidth = (1 << Log2_32(EWidth-1));
8407 EVT = MVT::getIntegerVT(EWidth);
8408 unsigned NumEVT = VVT.getSizeInBits()/EWidth;
8409 VecEVT = MVT::getVectorVT(EVT, NumEVT);
8410 } while (!TLI.isTypeLegal(VecEVT) ||
8411 VVT.getSizeInBits() != VecEVT.getSizeInBits());
8414 SDValue SelectionDAGLegalize::genWidenVectorLoads(SDValueVector& LdChain,
8424 // We assume that we have good rules to handle loading power of two loads so
8425 // we break down the operations to power of 2 loads. The strategy is to
8426 // load the largest power of 2 that we can easily transform to a legal vector
8427 // and then insert into that vector, and the cast the result into the legal
8428 // vector that we want. This avoids unnecessary stack converts.
8429 // TODO: If the Ldwidth is legal, alignment is the same as the LdWidth, and
8430 // the load is nonvolatile, we an use a wider load for the value.
8431 // Find a vector length we can load a large chunk
8434 FindWidenVecType(TLI, LdWidth, ResType, EVT, VecEVT);
8435 EVTWidth = EVT.getSizeInBits();
8437 SDValue LdOp = DAG.getLoad(EVT, dl, Chain, BasePtr, SV, SVOffset,
8438 isVolatile, Alignment);
8439 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecEVT, LdOp);
8440 LdChain.push_back(LdOp.getValue(1));
8442 // Check if we can load the element with one instruction
8443 if (LdWidth == EVTWidth) {
8444 return DAG.getNode(ISD::BIT_CONVERT, dl, ResType, VecOp);
8447 // The vector element order is endianness dependent.
8449 LdWidth -= EVTWidth;
8450 unsigned Offset = 0;
8452 while (LdWidth > 0) {
8453 unsigned Increment = EVTWidth / 8;
8454 Offset += Increment;
8455 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
8456 DAG.getIntPtrConstant(Increment));
8458 if (LdWidth < EVTWidth) {
8459 // Our current type we are using is too large, use a smaller size by
8460 // using a smaller power of 2
8461 unsigned oEVTWidth = EVTWidth;
8462 FindWidenVecType(TLI, LdWidth, ResType, EVT, VecEVT);
8463 EVTWidth = EVT.getSizeInBits();
8464 // Readjust position and vector position based on new load type
8465 Idx = Idx * (oEVTWidth/EVTWidth);
8466 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, VecEVT, VecOp);
8469 SDValue LdOp = DAG.getLoad(EVT, dl, Chain, BasePtr, SV,
8470 SVOffset+Offset, isVolatile,
8471 MinAlign(Alignment, Offset));
8472 LdChain.push_back(LdOp.getValue(1));
8473 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VecEVT, VecOp, LdOp,
8474 DAG.getIntPtrConstant(Idx++));
8476 LdWidth -= EVTWidth;
8479 return DAG.getNode(ISD::BIT_CONVERT, dl, ResType, VecOp);
8482 bool SelectionDAGLegalize::LoadWidenVectorOp(SDValue& Result,
8486 // TODO: Add support for ConcatVec and the ability to load many vector
8487 // types (e.g., v4i8). This will not work when a vector register
8488 // to memory mapping is strange (e.g., vector elements are not
8489 // stored in some sequential order).
8491 // It must be true that the widen vector type is bigger than where
8492 // we need to load from.
8493 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
8494 MVT LdVT = LD->getMemoryVT();
8495 DebugLoc dl = LD->getDebugLoc();
8496 assert(LdVT.isVector() && NVT.isVector());
8497 assert(LdVT.getVectorElementType() == NVT.getVectorElementType());
8500 SDValue Chain = LD->getChain();
8501 SDValue BasePtr = LD->getBasePtr();
8502 int SVOffset = LD->getSrcValueOffset();
8503 unsigned Alignment = LD->getAlignment();
8504 bool isVolatile = LD->isVolatile();
8505 const Value *SV = LD->getSrcValue();
8506 unsigned int LdWidth = LdVT.getSizeInBits();
8508 // Load value as a large register
8509 SDValueVector LdChain;
8510 Result = genWidenVectorLoads(LdChain, Chain, BasePtr, SV, SVOffset,
8511 Alignment, isVolatile, LdWidth, NVT, dl);
8513 if (LdChain.size() == 1) {
8518 TFOp=DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
8519 &LdChain[0], LdChain.size());
8525 void SelectionDAGLegalize::genWidenVectorStores(SDValueVector& StChain,
8535 // Breaks the stores into a series of power of 2 width stores. For any
8536 // width, we convert the vector to the vector of element size that we
8537 // want to store. This avoids requiring a stack convert.
8539 // Find a width of the element type we can store with
8540 MVT VVT = ValOp.getValueType();
8543 FindWidenVecType(TLI, StWidth, VVT, EVT, VecEVT);
8544 EVTWidth = EVT.getSizeInBits();
8546 SDValue VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, VecEVT, ValOp);
8547 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT, VecOp,
8548 DAG.getIntPtrConstant(0));
8549 SDValue StOp = DAG.getStore(Chain, dl, EOp, BasePtr, SV, SVOffset,
8550 isVolatile, Alignment);
8551 StChain.push_back(StOp);
8553 // Check if we are done
8554 if (StWidth == EVTWidth) {
8559 StWidth -= EVTWidth;
8560 unsigned Offset = 0;
8562 while (StWidth > 0) {
8563 unsigned Increment = EVTWidth / 8;
8564 Offset += Increment;
8565 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
8566 DAG.getIntPtrConstant(Increment));
8568 if (StWidth < EVTWidth) {
8569 // Our current type we are using is too large, use a smaller size by
8570 // using a smaller power of 2
8571 unsigned oEVTWidth = EVTWidth;
8572 FindWidenVecType(TLI, StWidth, VVT, EVT, VecEVT);
8573 EVTWidth = EVT.getSizeInBits();
8574 // Readjust position and vector position based on new load type
8575 Idx = Idx * (oEVTWidth/EVTWidth);
8576 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, VecEVT, VecOp);
8579 EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT, VecOp,
8580 DAG.getIntPtrConstant(Idx++));
8581 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr, SV,
8582 SVOffset + Offset, isVolatile,
8583 MinAlign(Alignment, Offset)));
8584 StWidth -= EVTWidth;
8589 SDValue SelectionDAGLegalize::StoreWidenVectorOp(StoreSDNode *ST,
8592 // TODO: It might be cleaner if we can use SplitVector and have more legal
8593 // vector types that can be stored into memory (e.g., v4xi8 can
8594 // be stored as a word). This will not work when a vector register
8595 // to memory mapping is strange (e.g., vector elements are not
8596 // stored in some sequential order).
8598 MVT StVT = ST->getMemoryVT();
8599 SDValue ValOp = ST->getValue();
8600 DebugLoc dl = ST->getDebugLoc();
8602 // Check if we have widen this node with another value
8603 std::map<SDValue, SDValue>::iterator I = WidenNodes.find(ValOp);
8604 if (I != WidenNodes.end())
8607 MVT VVT = ValOp.getValueType();
8609 // It must be true that we the widen vector type is bigger than where
8610 // we need to store.
8611 assert(StVT.isVector() && VVT.isVector());
8612 assert(StVT.bitsLT(VVT));
8613 assert(StVT.getVectorElementType() == VVT.getVectorElementType());
8616 SDValueVector StChain;
8617 genWidenVectorStores(StChain, Chain, BasePtr, ST->getSrcValue(),
8618 ST->getSrcValueOffset(), ST->getAlignment(),
8619 ST->isVolatile(), ValOp, StVT.getSizeInBits(), dl);
8620 if (StChain.size() == 1)
8623 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
8624 &StChain[0], StChain.size());
8628 // SelectionDAG::Legalize - This is the entry point for the file.
8630 void SelectionDAG::Legalize(bool TypesNeedLegalizing) {
8631 /// run - This is the main entry point to this class.
8633 SelectionDAGLegalize(*this, TypesNeedLegalizing).LegalizeDAG();