1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/ADT/DenseMap.h"
16 #include "llvm/ADT/SmallPtrSet.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/CallingConv.h"
19 #include "llvm/CodeGen/Analysis.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineJumpTableInfo.h"
22 #include "llvm/Constants.h"
23 #include "llvm/DataLayout.h"
24 #include "llvm/DebugInfo.h"
25 #include "llvm/DerivedTypes.h"
26 #include "llvm/LLVMContext.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/MathExtras.h"
30 #include "llvm/Support/raw_ostream.h"
31 #include "llvm/Target/TargetFrameLowering.h"
32 #include "llvm/Target/TargetLowering.h"
33 #include "llvm/Target/TargetMachine.h"
36 //===----------------------------------------------------------------------===//
37 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
38 /// hacks on it until the target machine can handle it. This involves
39 /// eliminating value sizes the machine cannot handle (promoting small sizes to
40 /// large sizes or splitting up large values into small values) as well as
41 /// eliminating operations the machine cannot handle.
43 /// This code also does a small amount of optimization and recognition of idioms
44 /// as part of its processing. For example, if a target does not support a
45 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
46 /// will attempt merge setcc and brc instructions into brcc's.
49 class SelectionDAGLegalize : public SelectionDAG::DAGUpdateListener {
50 const TargetMachine &TM;
51 const TargetLowering &TLI;
54 /// LegalizePosition - The iterator for walking through the node list.
55 SelectionDAG::allnodes_iterator LegalizePosition;
57 /// LegalizedNodes - The set of nodes which have already been legalized.
58 SmallPtrSet<SDNode *, 16> LegalizedNodes;
60 // Libcall insertion helpers.
63 explicit SelectionDAGLegalize(SelectionDAG &DAG);
68 /// LegalizeOp - Legalizes the given operation.
69 void LegalizeOp(SDNode *Node);
71 SDValue OptimizeFloatStore(StoreSDNode *ST);
73 void LegalizeLoadOps(SDNode *Node);
74 void LegalizeStoreOps(SDNode *Node);
76 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
77 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
78 /// is necessary to spill the vector being inserted into to memory, perform
79 /// the insert there, and then read the result back.
80 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
81 SDValue Idx, DebugLoc dl);
82 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
83 SDValue Idx, DebugLoc dl);
85 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
86 /// performs the same shuffe in terms of order or result bytes, but on a type
87 /// whose vector element type is narrower than the original shuffle type.
88 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
89 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
90 SDValue N1, SDValue N2,
91 ArrayRef<int> Mask) const;
93 void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
96 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
97 SDValue ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops,
98 unsigned NumOps, bool isSigned, DebugLoc dl);
100 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
101 SDNode *Node, bool isSigned);
102 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
103 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
104 RTLIB::Libcall Call_PPCF128);
105 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
106 RTLIB::Libcall Call_I8,
107 RTLIB::Libcall Call_I16,
108 RTLIB::Libcall Call_I32,
109 RTLIB::Libcall Call_I64,
110 RTLIB::Libcall Call_I128);
111 void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
113 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl);
114 SDValue ExpandBUILD_VECTOR(SDNode *Node);
115 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
116 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
117 SmallVectorImpl<SDValue> &Results);
118 SDValue ExpandFCOPYSIGN(SDNode *Node);
119 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
121 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
123 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
126 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl);
127 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl);
129 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
130 SDValue ExpandInsertToVectorThroughStack(SDValue Op);
131 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
133 SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP);
135 std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node);
137 void ExpandNode(SDNode *Node);
138 void PromoteNode(SDNode *Node);
140 void ForgetNode(SDNode *N) {
141 LegalizedNodes.erase(N);
142 if (LegalizePosition == SelectionDAG::allnodes_iterator(N))
147 // DAGUpdateListener implementation.
148 virtual void NodeDeleted(SDNode *N, SDNode *E) {
151 virtual void NodeUpdated(SDNode *N) {}
153 // Node replacement helpers
154 void ReplacedNode(SDNode *N) {
155 if (N->use_empty()) {
156 DAG.RemoveDeadNode(N);
161 void ReplaceNode(SDNode *Old, SDNode *New) {
162 DAG.ReplaceAllUsesWith(Old, New);
165 void ReplaceNode(SDValue Old, SDValue New) {
166 DAG.ReplaceAllUsesWith(Old, New);
167 ReplacedNode(Old.getNode());
169 void ReplaceNode(SDNode *Old, const SDValue *New) {
170 DAG.ReplaceAllUsesWith(Old, New);
176 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
177 /// performs the same shuffe in terms of order or result bytes, but on a type
178 /// whose vector element type is narrower than the original shuffle type.
179 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
181 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
182 SDValue N1, SDValue N2,
183 ArrayRef<int> Mask) const {
184 unsigned NumMaskElts = VT.getVectorNumElements();
185 unsigned NumDestElts = NVT.getVectorNumElements();
186 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
188 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
190 if (NumEltsGrowth == 1)
191 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
193 SmallVector<int, 8> NewMask;
194 for (unsigned i = 0; i != NumMaskElts; ++i) {
196 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
198 NewMask.push_back(-1);
200 NewMask.push_back(Idx * NumEltsGrowth + j);
203 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
204 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
205 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
208 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
209 : SelectionDAG::DAGUpdateListener(dag),
210 TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()),
214 void SelectionDAGLegalize::LegalizeDAG() {
215 DAG.AssignTopologicalOrder();
217 // Visit all the nodes. We start in topological order, so that we see
218 // nodes with their original operands intact. Legalization can produce
219 // new nodes which may themselves need to be legalized. Iterate until all
220 // nodes have been legalized.
222 bool AnyLegalized = false;
223 for (LegalizePosition = DAG.allnodes_end();
224 LegalizePosition != DAG.allnodes_begin(); ) {
227 SDNode *N = LegalizePosition;
228 if (LegalizedNodes.insert(N)) {
238 // Remove dead nodes now.
239 DAG.RemoveDeadNodes();
242 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
243 /// a load from the constant pool.
245 SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) {
247 DebugLoc dl = CFP->getDebugLoc();
249 // If a FP immediate is precise when represented as a float and if the
250 // target can do an extending load from float to double, we put it into
251 // the constant pool as a float, even if it's is statically typed as a
252 // double. This shrinks FP constants and canonicalizes them for targets where
253 // an FP extending load is the same cost as a normal load (such as on the x87
254 // fp stack or PPC FP unit).
255 EVT VT = CFP->getValueType(0);
256 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
258 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
259 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
260 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
265 while (SVT != MVT::f32) {
266 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
267 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) &&
268 // Only do this if the target has a native EXTLOAD instruction from
270 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
271 TLI.ShouldShrinkFPConstant(OrigVT)) {
272 Type *SType = SVT.getTypeForEVT(*DAG.getContext());
273 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
279 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
280 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
283 DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT,
285 CPIdx, MachinePointerInfo::getConstantPool(),
286 VT, false, false, Alignment);
290 DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
291 MachinePointerInfo::getConstantPool(), false, false, false,
296 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
297 static void ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
298 const TargetLowering &TLI,
299 SelectionDAGLegalize *DAGLegalize) {
300 assert(ST->getAddressingMode() == ISD::UNINDEXED &&
301 "unaligned indexed stores not implemented!");
302 SDValue Chain = ST->getChain();
303 SDValue Ptr = ST->getBasePtr();
304 SDValue Val = ST->getValue();
305 EVT VT = Val.getValueType();
306 int Alignment = ST->getAlignment();
307 DebugLoc dl = ST->getDebugLoc();
308 if (ST->getMemoryVT().isFloatingPoint() ||
309 ST->getMemoryVT().isVector()) {
310 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
311 if (TLI.isTypeLegal(intVT)) {
312 // Expand to a bitconvert of the value to the integer type of the
313 // same size, then a (misaligned) int store.
314 // FIXME: Does not handle truncating floating point stores!
315 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
316 Result = DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
317 ST->isVolatile(), ST->isNonTemporal(), Alignment);
318 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
321 // Do a (aligned) store to a stack slot, then copy from the stack slot
322 // to the final destination using (unaligned) integer loads and stores.
323 EVT StoredVT = ST->getMemoryVT();
325 TLI.getRegisterType(*DAG.getContext(),
326 EVT::getIntegerVT(*DAG.getContext(),
327 StoredVT.getSizeInBits()));
328 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
329 unsigned RegBytes = RegVT.getSizeInBits() / 8;
330 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
332 // Make sure the stack slot is also aligned for the register type.
333 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
335 // Perform the original store, only redirected to the stack slot.
336 SDValue Store = DAG.getTruncStore(Chain, dl,
337 Val, StackPtr, MachinePointerInfo(),
338 StoredVT, false, false, 0);
339 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
340 SmallVector<SDValue, 8> Stores;
343 // Do all but one copies using the full register width.
344 for (unsigned i = 1; i < NumRegs; i++) {
345 // Load one integer register's worth from the stack slot.
346 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr,
347 MachinePointerInfo(),
348 false, false, false, 0);
349 // Store it to the final location. Remember the store.
350 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
351 ST->getPointerInfo().getWithOffset(Offset),
352 ST->isVolatile(), ST->isNonTemporal(),
353 MinAlign(ST->getAlignment(), Offset)));
354 // Increment the pointers.
356 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
358 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
361 // The last store may be partial. Do a truncating store. On big-endian
362 // machines this requires an extending load from the stack slot to ensure
363 // that the bits are in the right place.
364 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
365 8 * (StoredBytes - Offset));
367 // Load from the stack slot.
368 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
369 MachinePointerInfo(),
370 MemVT, false, false, 0);
372 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
374 .getWithOffset(Offset),
375 MemVT, ST->isVolatile(),
377 MinAlign(ST->getAlignment(), Offset)));
378 // The order of the stores doesn't matter - say it with a TokenFactor.
380 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
382 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
385 assert(ST->getMemoryVT().isInteger() &&
386 !ST->getMemoryVT().isVector() &&
387 "Unaligned store of unknown type.");
388 // Get the half-size VT
389 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext());
390 int NumBits = NewStoredVT.getSizeInBits();
391 int IncrementSize = NumBits / 8;
393 // Divide the stored value in two parts.
394 SDValue ShiftAmount = DAG.getConstant(NumBits,
395 TLI.getShiftAmountTy(Val.getValueType()));
397 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
399 // Store the two parts
400 SDValue Store1, Store2;
401 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
402 ST->getPointerInfo(), NewStoredVT,
403 ST->isVolatile(), ST->isNonTemporal(), Alignment);
404 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
405 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
406 Alignment = MinAlign(Alignment, IncrementSize);
407 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
408 ST->getPointerInfo().getWithOffset(IncrementSize),
409 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(),
413 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
414 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
417 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
419 ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
420 const TargetLowering &TLI,
421 SDValue &ValResult, SDValue &ChainResult) {
422 assert(LD->getAddressingMode() == ISD::UNINDEXED &&
423 "unaligned indexed loads not implemented!");
424 SDValue Chain = LD->getChain();
425 SDValue Ptr = LD->getBasePtr();
426 EVT VT = LD->getValueType(0);
427 EVT LoadedVT = LD->getMemoryVT();
428 DebugLoc dl = LD->getDebugLoc();
429 if (VT.isFloatingPoint() || VT.isVector()) {
430 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
431 if (TLI.isTypeLegal(intVT) && TLI.isTypeLegal(LoadedVT)) {
432 // Expand to a (misaligned) integer load of the same size,
433 // then bitconvert to floating point or vector.
434 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getPointerInfo(),
437 LD->isInvariant(), LD->getAlignment());
438 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad);
440 Result = DAG.getNode(VT.isFloatingPoint() ? ISD::FP_EXTEND :
441 ISD::ANY_EXTEND, dl, VT, Result);
448 // Copy the value to a (aligned) stack slot using (unaligned) integer
449 // loads and stores, then do a (aligned) load from the stack slot.
450 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
451 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
452 unsigned RegBytes = RegVT.getSizeInBits() / 8;
453 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
455 // Make sure the stack slot is also aligned for the register type.
456 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
458 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
459 SmallVector<SDValue, 8> Stores;
460 SDValue StackPtr = StackBase;
463 // Do all but one copies using the full register width.
464 for (unsigned i = 1; i < NumRegs; i++) {
465 // Load one integer register's worth from the original location.
466 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr,
467 LD->getPointerInfo().getWithOffset(Offset),
468 LD->isVolatile(), LD->isNonTemporal(),
470 MinAlign(LD->getAlignment(), Offset));
471 // Follow the load with a store to the stack slot. Remember the store.
472 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
473 MachinePointerInfo(), false, false, 0));
474 // Increment the pointers.
476 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
477 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
481 // The last copy may be partial. Do an extending load.
482 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
483 8 * (LoadedBytes - Offset));
484 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
485 LD->getPointerInfo().getWithOffset(Offset),
486 MemVT, LD->isVolatile(),
488 MinAlign(LD->getAlignment(), Offset));
489 // Follow the load with a store to the stack slot. Remember the store.
490 // On big-endian machines this requires a truncating store to ensure
491 // that the bits end up in the right place.
492 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
493 MachinePointerInfo(), MemVT,
496 // The order of the stores doesn't matter - say it with a TokenFactor.
497 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
500 // Finally, perform the original load only redirected to the stack slot.
501 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
502 MachinePointerInfo(), LoadedVT, false, false, 0);
504 // Callers expect a MERGE_VALUES node.
509 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
510 "Unaligned load of unsupported type.");
512 // Compute the new VT that is half the size of the old one. This is an
514 unsigned NumBits = LoadedVT.getSizeInBits();
516 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
519 unsigned Alignment = LD->getAlignment();
520 unsigned IncrementSize = NumBits / 8;
521 ISD::LoadExtType HiExtType = LD->getExtensionType();
523 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
524 if (HiExtType == ISD::NON_EXTLOAD)
525 HiExtType = ISD::ZEXTLOAD;
527 // Load the value in two parts
529 if (TLI.isLittleEndian()) {
530 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
531 NewLoadedVT, LD->isVolatile(),
532 LD->isNonTemporal(), Alignment);
533 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
534 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
535 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr,
536 LD->getPointerInfo().getWithOffset(IncrementSize),
537 NewLoadedVT, LD->isVolatile(),
538 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
540 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(),
541 NewLoadedVT, LD->isVolatile(),
542 LD->isNonTemporal(), Alignment);
543 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
544 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
545 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
546 LD->getPointerInfo().getWithOffset(IncrementSize),
547 NewLoadedVT, LD->isVolatile(),
548 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
551 // aggregate the two parts
552 SDValue ShiftAmount = DAG.getConstant(NumBits,
553 TLI.getShiftAmountTy(Hi.getValueType()));
554 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
555 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
557 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
564 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
565 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
566 /// is necessary to spill the vector being inserted into to memory, perform
567 /// the insert there, and then read the result back.
568 SDValue SelectionDAGLegalize::
569 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
575 // If the target doesn't support this, we have to spill the input vector
576 // to a temporary stack slot, update the element, then reload it. This is
577 // badness. We could also load the value into a vector register (either
578 // with a "move to register" or "extload into register" instruction, then
579 // permute it into place, if the idx is a constant and if the idx is
580 // supported by the target.
581 EVT VT = Tmp1.getValueType();
582 EVT EltVT = VT.getVectorElementType();
583 EVT IdxVT = Tmp3.getValueType();
584 EVT PtrVT = TLI.getPointerTy();
585 SDValue StackPtr = DAG.CreateStackTemporary(VT);
587 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
590 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
591 MachinePointerInfo::getFixedStack(SPFI),
594 // Truncate or zero extend offset to target pointer type.
595 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
596 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
597 // Add the offset to the index.
598 unsigned EltSize = EltVT.getSizeInBits()/8;
599 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
600 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
601 // Store the scalar value.
602 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT,
604 // Load the updated vector.
605 return DAG.getLoad(VT, dl, Ch, StackPtr,
606 MachinePointerInfo::getFixedStack(SPFI), false, false,
611 SDValue SelectionDAGLegalize::
612 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) {
613 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
614 // SCALAR_TO_VECTOR requires that the type of the value being inserted
615 // match the element type of the vector being created, except for
616 // integers in which case the inserted value can be over width.
617 EVT EltVT = Vec.getValueType().getVectorElementType();
618 if (Val.getValueType() == EltVT ||
619 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
620 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
621 Vec.getValueType(), Val);
623 unsigned NumElts = Vec.getValueType().getVectorNumElements();
624 // We generate a shuffle of InVec and ScVec, so the shuffle mask
625 // should be 0,1,2,3,4,5... with the appropriate element replaced with
627 SmallVector<int, 8> ShufOps;
628 for (unsigned i = 0; i != NumElts; ++i)
629 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
631 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
635 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
638 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
639 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
640 // FIXME: We shouldn't do this for TargetConstantFP's.
641 // FIXME: move this to the DAG Combiner! Note that we can't regress due
642 // to phase ordering between legalized code and the dag combiner. This
643 // probably means that we need to integrate dag combiner and legalizer
645 // We generally can't do this one for long doubles.
646 SDValue Chain = ST->getChain();
647 SDValue Ptr = ST->getBasePtr();
648 unsigned Alignment = ST->getAlignment();
649 bool isVolatile = ST->isVolatile();
650 bool isNonTemporal = ST->isNonTemporal();
651 DebugLoc dl = ST->getDebugLoc();
652 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
653 if (CFP->getValueType(0) == MVT::f32 &&
654 TLI.isTypeLegal(MVT::i32)) {
655 SDValue Con = DAG.getConstant(CFP->getValueAPF().
656 bitcastToAPInt().zextOrTrunc(32),
658 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
659 isVolatile, isNonTemporal, Alignment);
662 if (CFP->getValueType(0) == MVT::f64) {
663 // If this target supports 64-bit registers, do a single 64-bit store.
664 if (TLI.isTypeLegal(MVT::i64)) {
665 SDValue Con = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
666 zextOrTrunc(64), MVT::i64);
667 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
668 isVolatile, isNonTemporal, Alignment);
671 if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) {
672 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
673 // stores. If the target supports neither 32- nor 64-bits, this
674 // xform is certainly not worth it.
675 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
676 SDValue Lo = DAG.getConstant(IntVal.trunc(32), MVT::i32);
677 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
678 if (TLI.isBigEndian()) std::swap(Lo, Hi);
680 Lo = DAG.getStore(Chain, dl, Lo, Ptr, ST->getPointerInfo(), isVolatile,
681 isNonTemporal, Alignment);
682 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
683 DAG.getIntPtrConstant(4));
684 Hi = DAG.getStore(Chain, dl, Hi, Ptr,
685 ST->getPointerInfo().getWithOffset(4),
686 isVolatile, isNonTemporal, MinAlign(Alignment, 4U));
688 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
692 return SDValue(0, 0);
695 void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
696 StoreSDNode *ST = cast<StoreSDNode>(Node);
697 SDValue Chain = ST->getChain();
698 SDValue Ptr = ST->getBasePtr();
699 DebugLoc dl = Node->getDebugLoc();
701 unsigned Alignment = ST->getAlignment();
702 bool isVolatile = ST->isVolatile();
703 bool isNonTemporal = ST->isNonTemporal();
705 if (!ST->isTruncatingStore()) {
706 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
707 ReplaceNode(ST, OptStore);
712 SDValue Value = ST->getValue();
713 EVT VT = Value.getValueType();
714 switch (TLI.getOperationAction(ISD::STORE, VT)) {
715 default: llvm_unreachable("This action is not supported yet!");
716 case TargetLowering::Legal:
717 // If this is an unaligned store and the target doesn't support it,
719 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
720 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
721 unsigned ABIAlignment= TLI.getDataLayout()->getABITypeAlignment(Ty);
722 if (ST->getAlignment() < ABIAlignment)
723 ExpandUnalignedStore(cast<StoreSDNode>(Node),
727 case TargetLowering::Custom: {
728 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
730 ReplaceNode(SDValue(Node, 0), Res);
733 case TargetLowering::Promote: {
734 assert(VT.isVector() && "Unknown legal promote case!");
735 Value = DAG.getNode(ISD::BITCAST, dl,
736 TLI.getTypeToPromoteTo(ISD::STORE, VT), Value);
738 DAG.getStore(Chain, dl, Value, Ptr,
739 ST->getPointerInfo(), isVolatile,
740 isNonTemporal, Alignment);
741 ReplaceNode(SDValue(Node, 0), Result);
748 SDValue Value = ST->getValue();
750 EVT StVT = ST->getMemoryVT();
751 unsigned StWidth = StVT.getSizeInBits();
753 if (StWidth != StVT.getStoreSizeInBits()) {
754 // Promote to a byte-sized store with upper bits zero if not
755 // storing an integral number of bytes. For example, promote
756 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
757 EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
758 StVT.getStoreSizeInBits());
759 Value = DAG.getZeroExtendInReg(Value, dl, StVT);
761 DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
762 NVT, isVolatile, isNonTemporal, Alignment);
763 ReplaceNode(SDValue(Node, 0), Result);
764 } else if (StWidth & (StWidth - 1)) {
765 // If not storing a power-of-2 number of bits, expand as two stores.
766 assert(!StVT.isVector() && "Unsupported truncstore!");
767 unsigned RoundWidth = 1 << Log2_32(StWidth);
768 assert(RoundWidth < StWidth);
769 unsigned ExtraWidth = StWidth - RoundWidth;
770 assert(ExtraWidth < RoundWidth);
771 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
772 "Store size not an integral number of bytes!");
773 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
774 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
776 unsigned IncrementSize;
778 if (TLI.isLittleEndian()) {
779 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
780 // Store the bottom RoundWidth bits.
781 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
783 isVolatile, isNonTemporal, Alignment);
785 // Store the remaining ExtraWidth bits.
786 IncrementSize = RoundWidth / 8;
787 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
788 DAG.getIntPtrConstant(IncrementSize));
789 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
790 DAG.getConstant(RoundWidth,
791 TLI.getShiftAmountTy(Value.getValueType())));
792 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr,
793 ST->getPointerInfo().getWithOffset(IncrementSize),
794 ExtraVT, isVolatile, isNonTemporal,
795 MinAlign(Alignment, IncrementSize));
797 // Big endian - avoid unaligned stores.
798 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
799 // Store the top RoundWidth bits.
800 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
801 DAG.getConstant(ExtraWidth,
802 TLI.getShiftAmountTy(Value.getValueType())));
803 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, ST->getPointerInfo(),
804 RoundVT, isVolatile, isNonTemporal, Alignment);
806 // Store the remaining ExtraWidth bits.
807 IncrementSize = RoundWidth / 8;
808 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
809 DAG.getIntPtrConstant(IncrementSize));
810 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr,
811 ST->getPointerInfo().getWithOffset(IncrementSize),
812 ExtraVT, isVolatile, isNonTemporal,
813 MinAlign(Alignment, IncrementSize));
816 // The order of the stores doesn't matter.
817 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
818 ReplaceNode(SDValue(Node, 0), Result);
820 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
821 default: llvm_unreachable("This action is not supported yet!");
822 case TargetLowering::Legal:
823 // If this is an unaligned store and the target doesn't support it,
825 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
826 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
827 unsigned ABIAlignment= TLI.getDataLayout()->getABITypeAlignment(Ty);
828 if (ST->getAlignment() < ABIAlignment)
829 ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this);
832 case TargetLowering::Custom: {
833 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
835 ReplaceNode(SDValue(Node, 0), Res);
838 case TargetLowering::Expand:
839 assert(!StVT.isVector() &&
840 "Vector Stores are handled in LegalizeVectorOps");
842 // TRUNCSTORE:i16 i32 -> STORE i16
843 assert(TLI.isTypeLegal(StVT) &&
844 "Do not know how to expand this store!");
845 Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value);
847 DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
848 isVolatile, isNonTemporal, Alignment);
849 ReplaceNode(SDValue(Node, 0), Result);
856 void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
857 LoadSDNode *LD = cast<LoadSDNode>(Node);
858 SDValue Chain = LD->getChain(); // The chain.
859 SDValue Ptr = LD->getBasePtr(); // The base pointer.
860 SDValue Value; // The value returned by the load op.
861 DebugLoc dl = Node->getDebugLoc();
863 ISD::LoadExtType ExtType = LD->getExtensionType();
864 if (ExtType == ISD::NON_EXTLOAD) {
865 EVT VT = Node->getValueType(0);
866 SDValue RVal = SDValue(Node, 0);
867 SDValue RChain = SDValue(Node, 1);
869 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
870 default: llvm_unreachable("This action is not supported yet!");
871 case TargetLowering::Legal:
872 // If this is an unaligned load and the target doesn't support it,
874 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
875 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
876 unsigned ABIAlignment =
877 TLI.getDataLayout()->getABITypeAlignment(Ty);
878 if (LD->getAlignment() < ABIAlignment){
879 ExpandUnalignedLoad(cast<LoadSDNode>(Node), DAG, TLI, RVal, RChain);
883 case TargetLowering::Custom: {
884 SDValue Res = TLI.LowerOperation(RVal, DAG);
887 RChain = Res.getValue(1);
891 case TargetLowering::Promote: {
892 // Only promote a load of vector type to another.
893 assert(VT.isVector() && "Cannot promote this load!");
894 // Change base type to a different vector type.
895 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
897 SDValue Res = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getPointerInfo(),
898 LD->isVolatile(), LD->isNonTemporal(),
899 LD->isInvariant(), LD->getAlignment());
900 RVal = DAG.getNode(ISD::BITCAST, dl, VT, Res);
901 RChain = Res.getValue(1);
905 if (RChain.getNode() != Node) {
906 assert(RVal.getNode() != Node && "Load must be completely replaced");
907 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), RVal);
908 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), RChain);
914 EVT SrcVT = LD->getMemoryVT();
915 unsigned SrcWidth = SrcVT.getSizeInBits();
916 unsigned Alignment = LD->getAlignment();
917 bool isVolatile = LD->isVolatile();
918 bool isNonTemporal = LD->isNonTemporal();
920 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
921 // Some targets pretend to have an i1 loading operation, and actually
922 // load an i8. This trick is correct for ZEXTLOAD because the top 7
923 // bits are guaranteed to be zero; it helps the optimizers understand
924 // that these bits are zero. It is also useful for EXTLOAD, since it
925 // tells the optimizers that those bits are undefined. It would be
926 // nice to have an effective generic way of getting these benefits...
927 // Until such a way is found, don't insist on promoting i1 here.
929 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
930 // Promote to a byte-sized load if not loading an integral number of
931 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
932 unsigned NewWidth = SrcVT.getStoreSizeInBits();
933 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
936 // The extra bits are guaranteed to be zero, since we stored them that
937 // way. A zext load from NVT thus automatically gives zext from SrcVT.
939 ISD::LoadExtType NewExtType =
940 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
943 DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
944 Chain, Ptr, LD->getPointerInfo(),
945 NVT, isVolatile, isNonTemporal, Alignment);
947 Ch = Result.getValue(1); // The chain.
949 if (ExtType == ISD::SEXTLOAD)
950 // Having the top bits zero doesn't help when sign extending.
951 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
952 Result.getValueType(),
953 Result, DAG.getValueType(SrcVT));
954 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
955 // All the top bits are guaranteed to be zero - inform the optimizers.
956 Result = DAG.getNode(ISD::AssertZext, dl,
957 Result.getValueType(), Result,
958 DAG.getValueType(SrcVT));
962 } else if (SrcWidth & (SrcWidth - 1)) {
963 // If not loading a power-of-2 number of bits, expand as two loads.
964 assert(!SrcVT.isVector() && "Unsupported extload!");
965 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
966 assert(RoundWidth < SrcWidth);
967 unsigned ExtraWidth = SrcWidth - RoundWidth;
968 assert(ExtraWidth < RoundWidth);
969 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
970 "Load size not an integral number of bytes!");
971 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
972 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
974 unsigned IncrementSize;
976 if (TLI.isLittleEndian()) {
977 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
978 // Load the bottom RoundWidth bits.
979 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0),
981 LD->getPointerInfo(), RoundVT, isVolatile,
982 isNonTemporal, Alignment);
984 // Load the remaining ExtraWidth bits.
985 IncrementSize = RoundWidth / 8;
986 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
987 DAG.getIntPtrConstant(IncrementSize));
988 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
989 LD->getPointerInfo().getWithOffset(IncrementSize),
990 ExtraVT, isVolatile, isNonTemporal,
991 MinAlign(Alignment, IncrementSize));
993 // Build a factor node to remember that this load is independent of
995 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
998 // Move the top bits to the right place.
999 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1000 DAG.getConstant(RoundWidth,
1001 TLI.getShiftAmountTy(Hi.getValueType())));
1003 // Join the hi and lo parts.
1004 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1006 // Big endian - avoid unaligned loads.
1007 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1008 // Load the top RoundWidth bits.
1009 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
1010 LD->getPointerInfo(), RoundVT, isVolatile,
1011 isNonTemporal, Alignment);
1013 // Load the remaining ExtraWidth bits.
1014 IncrementSize = RoundWidth / 8;
1015 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1016 DAG.getIntPtrConstant(IncrementSize));
1017 Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
1018 dl, Node->getValueType(0), Chain, Ptr,
1019 LD->getPointerInfo().getWithOffset(IncrementSize),
1020 ExtraVT, isVolatile, isNonTemporal,
1021 MinAlign(Alignment, IncrementSize));
1023 // Build a factor node to remember that this load is independent of
1025 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1028 // Move the top bits to the right place.
1029 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1030 DAG.getConstant(ExtraWidth,
1031 TLI.getShiftAmountTy(Hi.getValueType())));
1033 // Join the hi and lo parts.
1034 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1039 bool isCustom = false;
1040 switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
1041 default: llvm_unreachable("This action is not supported yet!");
1042 case TargetLowering::Custom:
1045 case TargetLowering::Legal: {
1046 Value = SDValue(Node, 0);
1047 Chain = SDValue(Node, 1);
1050 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1051 if (Res.getNode()) {
1053 Chain = Res.getValue(1);
1056 // If this is an unaligned load and the target doesn't support it,
1058 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
1060 LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1061 unsigned ABIAlignment =
1062 TLI.getDataLayout()->getABITypeAlignment(Ty);
1063 if (LD->getAlignment() < ABIAlignment){
1064 ExpandUnalignedLoad(cast<LoadSDNode>(Node),
1065 DAG, TLI, Value, Chain);
1071 case TargetLowering::Expand:
1072 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) && TLI.isTypeLegal(SrcVT)) {
1073 SDValue Load = DAG.getLoad(SrcVT, dl, Chain, Ptr,
1074 LD->getPointerInfo(),
1075 LD->isVolatile(), LD->isNonTemporal(),
1076 LD->isInvariant(), LD->getAlignment());
1080 ExtendOp = (SrcVT.isFloatingPoint() ?
1081 ISD::FP_EXTEND : ISD::ANY_EXTEND);
1083 case ISD::SEXTLOAD: ExtendOp = ISD::SIGN_EXTEND; break;
1084 case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break;
1085 default: llvm_unreachable("Unexpected extend load type!");
1087 Value = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
1088 Chain = Load.getValue(1);
1092 assert(!SrcVT.isVector() &&
1093 "Vector Loads are handled in LegalizeVectorOps");
1095 // FIXME: This does not work for vectors on most targets. Sign- and
1096 // zero-extend operations are currently folded into extending loads,
1097 // whether they are legal or not, and then we end up here without any
1098 // support for legalizing them.
1099 assert(ExtType != ISD::EXTLOAD &&
1100 "EXTLOAD should always be supported!");
1101 // Turn the unsupported load into an EXTLOAD followed by an explicit
1102 // zero/sign extend inreg.
1103 SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
1104 Chain, Ptr, LD->getPointerInfo(), SrcVT,
1105 LD->isVolatile(), LD->isNonTemporal(),
1106 LD->getAlignment());
1108 if (ExtType == ISD::SEXTLOAD)
1109 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1110 Result.getValueType(),
1111 Result, DAG.getValueType(SrcVT));
1113 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType());
1115 Chain = Result.getValue(1);
1120 // Since loads produce two values, make sure to remember that we legalized
1122 if (Chain.getNode() != Node) {
1123 assert(Value.getNode() != Node && "Load must be completely replaced");
1124 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Value);
1125 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
1130 /// LegalizeOp - Return a legal replacement for the given operation, with
1131 /// all legal operands.
1132 void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
1133 if (Node->getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
1136 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1137 assert(TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) ==
1138 TargetLowering::TypeLegal &&
1139 "Unexpected illegal type!");
1141 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1142 assert((TLI.getTypeAction(*DAG.getContext(),
1143 Node->getOperand(i).getValueType()) ==
1144 TargetLowering::TypeLegal ||
1145 Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
1146 "Unexpected illegal type!");
1148 // Figure out the correct action; the way to query this varies by opcode
1149 TargetLowering::LegalizeAction Action = TargetLowering::Legal;
1150 bool SimpleFinishLegalizing = true;
1151 switch (Node->getOpcode()) {
1152 case ISD::INTRINSIC_W_CHAIN:
1153 case ISD::INTRINSIC_WO_CHAIN:
1154 case ISD::INTRINSIC_VOID:
1155 case ISD::STACKSAVE:
1156 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1159 Action = TLI.getOperationAction(Node->getOpcode(),
1160 Node->getValueType(0));
1161 if (Action != TargetLowering::Promote)
1162 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1164 case ISD::SINT_TO_FP:
1165 case ISD::UINT_TO_FP:
1166 case ISD::EXTRACT_VECTOR_ELT:
1167 Action = TLI.getOperationAction(Node->getOpcode(),
1168 Node->getOperand(0).getValueType());
1170 case ISD::FP_ROUND_INREG:
1171 case ISD::SIGN_EXTEND_INREG: {
1172 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
1173 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
1176 case ISD::ATOMIC_STORE: {
1177 Action = TLI.getOperationAction(Node->getOpcode(),
1178 Node->getOperand(2).getValueType());
1181 case ISD::SELECT_CC:
1184 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
1185 Node->getOpcode() == ISD::SETCC ? 2 : 1;
1186 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
1187 EVT OpVT = Node->getOperand(CompareOperand).getValueType();
1188 ISD::CondCode CCCode =
1189 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
1190 Action = TLI.getCondCodeAction(CCCode, OpVT);
1191 if (Action == TargetLowering::Legal) {
1192 if (Node->getOpcode() == ISD::SELECT_CC)
1193 Action = TLI.getOperationAction(Node->getOpcode(),
1194 Node->getValueType(0));
1196 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
1202 // FIXME: Model these properly. LOAD and STORE are complicated, and
1203 // STORE expects the unlegalized operand in some cases.
1204 SimpleFinishLegalizing = false;
1206 case ISD::CALLSEQ_START:
1207 case ISD::CALLSEQ_END:
1208 // FIXME: This shouldn't be necessary. These nodes have special properties
1209 // dealing with the recursive nature of legalization. Removing this
1210 // special case should be done as part of making LegalizeDAG non-recursive.
1211 SimpleFinishLegalizing = false;
1213 case ISD::EXTRACT_ELEMENT:
1214 case ISD::FLT_ROUNDS_:
1222 case ISD::MERGE_VALUES:
1223 case ISD::EH_RETURN:
1224 case ISD::FRAME_TO_ARGS_OFFSET:
1225 case ISD::EH_SJLJ_SETJMP:
1226 case ISD::EH_SJLJ_LONGJMP:
1227 // These operations lie about being legal: when they claim to be legal,
1228 // they should actually be expanded.
1229 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1230 if (Action == TargetLowering::Legal)
1231 Action = TargetLowering::Expand;
1233 case ISD::INIT_TRAMPOLINE:
1234 case ISD::ADJUST_TRAMPOLINE:
1235 case ISD::FRAMEADDR:
1236 case ISD::RETURNADDR:
1237 // These operations lie about being legal: when they claim to be legal,
1238 // they should actually be custom-lowered.
1239 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1240 if (Action == TargetLowering::Legal)
1241 Action = TargetLowering::Custom;
1243 case ISD::DEBUGTRAP:
1244 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1245 if (Action == TargetLowering::Expand) {
1246 // replace ISD::DEBUGTRAP with ISD::TRAP
1248 NewVal = DAG.getNode(ISD::TRAP, Node->getDebugLoc(), Node->getVTList(),
1249 Node->getOperand(0));
1250 ReplaceNode(Node, NewVal.getNode());
1251 LegalizeOp(NewVal.getNode());
1257 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1258 Action = TargetLowering::Legal;
1260 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1265 if (SimpleFinishLegalizing) {
1266 SDNode *NewNode = Node;
1267 switch (Node->getOpcode()) {
1274 // Legalizing shifts/rotates requires adjusting the shift amount
1275 // to the appropriate width.
1276 if (!Node->getOperand(1).getValueType().isVector()) {
1278 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1279 Node->getOperand(1));
1280 HandleSDNode Handle(SAO);
1281 LegalizeOp(SAO.getNode());
1282 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1286 case ISD::SRL_PARTS:
1287 case ISD::SRA_PARTS:
1288 case ISD::SHL_PARTS:
1289 // Legalizing shifts/rotates requires adjusting the shift amount
1290 // to the appropriate width.
1291 if (!Node->getOperand(2).getValueType().isVector()) {
1293 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1294 Node->getOperand(2));
1295 HandleSDNode Handle(SAO);
1296 LegalizeOp(SAO.getNode());
1297 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1298 Node->getOperand(1),
1304 if (NewNode != Node) {
1305 DAG.ReplaceAllUsesWith(Node, NewNode);
1306 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1307 DAG.TransferDbgValues(SDValue(Node, i), SDValue(NewNode, i));
1312 case TargetLowering::Legal:
1314 case TargetLowering::Custom: {
1315 // FIXME: The handling for custom lowering with multiple results is
1317 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1318 if (Res.getNode()) {
1319 SmallVector<SDValue, 8> ResultVals;
1320 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
1322 ResultVals.push_back(Res);
1324 ResultVals.push_back(Res.getValue(i));
1326 if (Res.getNode() != Node || Res.getResNo() != 0) {
1327 DAG.ReplaceAllUsesWith(Node, ResultVals.data());
1328 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1329 DAG.TransferDbgValues(SDValue(Node, i), ResultVals[i]);
1336 case TargetLowering::Expand:
1339 case TargetLowering::Promote:
1345 switch (Node->getOpcode()) {
1352 llvm_unreachable("Do not know how to legalize this operator!");
1354 case ISD::CALLSEQ_START:
1355 case ISD::CALLSEQ_END:
1358 return LegalizeLoadOps(Node);
1361 return LegalizeStoreOps(Node);
1366 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1367 SDValue Vec = Op.getOperand(0);
1368 SDValue Idx = Op.getOperand(1);
1369 DebugLoc dl = Op.getDebugLoc();
1370 // Store the value to a temporary stack slot, then LOAD the returned part.
1371 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1372 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1373 MachinePointerInfo(), false, false, 0);
1375 // Add the offset to the index.
1377 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1378 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1379 DAG.getConstant(EltSize, Idx.getValueType()));
1381 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1382 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1384 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1386 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1388 if (Op.getValueType().isVector())
1389 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,MachinePointerInfo(),
1390 false, false, false, 0);
1391 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
1392 MachinePointerInfo(),
1393 Vec.getValueType().getVectorElementType(),
1397 SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
1398 assert(Op.getValueType().isVector() && "Non-vector insert subvector!");
1400 SDValue Vec = Op.getOperand(0);
1401 SDValue Part = Op.getOperand(1);
1402 SDValue Idx = Op.getOperand(2);
1403 DebugLoc dl = Op.getDebugLoc();
1405 // Store the value to a temporary stack slot, then LOAD the returned part.
1407 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1408 int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1409 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1411 // First store the whole vector.
1412 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo,
1415 // Then store the inserted part.
1417 // Add the offset to the index.
1419 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1421 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1422 DAG.getConstant(EltSize, Idx.getValueType()));
1424 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1425 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1427 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1429 SDValue SubStackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
1432 // Store the subvector.
1433 Ch = DAG.getStore(DAG.getEntryNode(), dl, Part, SubStackPtr,
1434 MachinePointerInfo(), false, false, 0);
1436 // Finally, load the updated vector.
1437 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo,
1438 false, false, false, 0);
1441 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1442 // We can't handle this case efficiently. Allocate a sufficiently
1443 // aligned object on the stack, store each element into it, then load
1444 // the result as a vector.
1445 // Create the stack frame object.
1446 EVT VT = Node->getValueType(0);
1447 EVT EltVT = VT.getVectorElementType();
1448 DebugLoc dl = Node->getDebugLoc();
1449 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1450 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1451 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1453 // Emit a store of each element to the stack slot.
1454 SmallVector<SDValue, 8> Stores;
1455 unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1456 // Store (in the right endianness) the elements to memory.
1457 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1458 // Ignore undef elements.
1459 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1461 unsigned Offset = TypeByteSize*i;
1463 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
1464 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1466 // If the destination vector element type is narrower than the source
1467 // element type, only store the bits necessary.
1468 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1469 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1470 Node->getOperand(i), Idx,
1471 PtrInfo.getWithOffset(Offset),
1472 EltVT, false, false, 0));
1474 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
1475 Node->getOperand(i), Idx,
1476 PtrInfo.getWithOffset(Offset),
1481 if (!Stores.empty()) // Not all undef elements?
1482 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1483 &Stores[0], Stores.size());
1485 StoreChain = DAG.getEntryNode();
1487 // Result is a load from the stack slot.
1488 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo,
1489 false, false, false, 0);
1492 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
1493 DebugLoc dl = Node->getDebugLoc();
1494 SDValue Tmp1 = Node->getOperand(0);
1495 SDValue Tmp2 = Node->getOperand(1);
1497 // Get the sign bit of the RHS. First obtain a value that has the same
1498 // sign as the sign bit, i.e. negative if and only if the sign bit is 1.
1500 EVT FloatVT = Tmp2.getValueType();
1501 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits());
1502 if (TLI.isTypeLegal(IVT)) {
1503 // Convert to an integer with the same sign bit.
1504 SignBit = DAG.getNode(ISD::BITCAST, dl, IVT, Tmp2);
1506 // Store the float to memory, then load the sign part out as an integer.
1507 MVT LoadTy = TLI.getPointerTy();
1508 // First create a temporary that is aligned for both the load and store.
1509 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1510 // Then store the float to it.
1512 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, MachinePointerInfo(),
1514 if (TLI.isBigEndian()) {
1515 assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1516 // Load out a legal integer with the same sign bit as the float.
1517 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, MachinePointerInfo(),
1518 false, false, false, 0);
1519 } else { // Little endian
1520 SDValue LoadPtr = StackPtr;
1521 // The float may be wider than the integer we are going to load. Advance
1522 // the pointer so that the loaded integer will contain the sign bit.
1523 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits();
1524 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8;
1525 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(),
1526 LoadPtr, DAG.getIntPtrConstant(ByteOffset));
1527 // Load a legal integer containing the sign bit.
1528 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(),
1529 false, false, false, 0);
1530 // Move the sign bit to the top bit of the loaded integer.
1531 unsigned BitShift = LoadTy.getSizeInBits() -
1532 (FloatVT.getSizeInBits() - 8 * ByteOffset);
1533 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?");
1535 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit,
1536 DAG.getConstant(BitShift,
1537 TLI.getShiftAmountTy(SignBit.getValueType())));
1540 // Now get the sign bit proper, by seeing whether the value is negative.
1541 SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()),
1542 SignBit, DAG.getConstant(0, SignBit.getValueType()),
1544 // Get the absolute value of the result.
1545 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1546 // Select between the nabs and abs value based on the sign bit of
1548 return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit,
1549 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1553 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1554 SmallVectorImpl<SDValue> &Results) {
1555 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1556 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1557 " not tell us which reg is the stack pointer!");
1558 DebugLoc dl = Node->getDebugLoc();
1559 EVT VT = Node->getValueType(0);
1560 SDValue Tmp1 = SDValue(Node, 0);
1561 SDValue Tmp2 = SDValue(Node, 1);
1562 SDValue Tmp3 = Node->getOperand(2);
1563 SDValue Chain = Tmp1.getOperand(0);
1565 // Chain the dynamic stack allocation so that it doesn't modify the stack
1566 // pointer when other instructions are using the stack.
1567 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1569 SDValue Size = Tmp2.getOperand(1);
1570 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1571 Chain = SP.getValue(1);
1572 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1573 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
1574 if (Align > StackAlign)
1575 SP = DAG.getNode(ISD::AND, dl, VT, SP,
1576 DAG.getConstant(-(uint64_t)Align, VT));
1577 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1578 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1580 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1581 DAG.getIntPtrConstant(0, true), SDValue());
1583 Results.push_back(Tmp1);
1584 Results.push_back(Tmp2);
1587 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
1588 /// condition code CC on the current target. This routine expands SETCC with
1589 /// illegal condition code into AND / OR of multiple SETCC values.
1590 void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1591 SDValue &LHS, SDValue &RHS,
1594 EVT OpVT = LHS.getValueType();
1595 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1596 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1597 default: llvm_unreachable("Unknown condition code action!");
1598 case TargetLowering::Legal:
1601 case TargetLowering::Expand: {
1602 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1603 ISD::CondCode InvCC = ISD::SETCC_INVALID;
1606 default: llvm_unreachable("Don't know how to expand this condition!");
1608 assert(TLI.getCondCodeAction(ISD::SETOEQ, OpVT)
1609 == TargetLowering::Legal
1610 && "If SETO is expanded, SETOEQ must be legal!");
1611 CC1 = ISD::SETOEQ; CC2 = ISD::SETOEQ; Opc = ISD::AND; break;
1613 assert(TLI.getCondCodeAction(ISD::SETUNE, OpVT)
1614 == TargetLowering::Legal
1615 && "If SETUO is expanded, SETUNE must be legal!");
1616 CC1 = ISD::SETUNE; CC2 = ISD::SETUNE; Opc = ISD::OR; break;
1629 // If we are floating point, assign and break, otherwise fall through.
1630 if (!OpVT.isInteger()) {
1631 // We can use the 4th bit to tell if we are the unordered
1632 // or ordered version of the opcode.
1633 CC2 = ((unsigned)CCCode & 0x8U) ? ISD::SETUO : ISD::SETO;
1634 Opc = ((unsigned)CCCode & 0x8U) ? ISD::OR : ISD::AND;
1635 CC1 = (ISD::CondCode)(((int)CCCode & 0x7) | 0x10);
1638 // Fallthrough if we are unsigned integer.
1645 InvCC = ISD::getSetCCSwappedOperands(CCCode);
1646 if (TLI.getCondCodeAction(InvCC, OpVT) == TargetLowering::Expand) {
1647 // We only support using the inverted operation and not a
1648 // different manner of supporting expanding these cases.
1649 llvm_unreachable("Don't know how to expand this condition!");
1651 LHS = DAG.getSetCC(dl, VT, RHS, LHS, InvCC);
1657 SDValue SetCC1, SetCC2;
1658 if (CCCode != ISD::SETO && CCCode != ISD::SETUO) {
1659 // If we aren't the ordered or unorder operation,
1660 // then the pattern is (LHS CC1 RHS) Opc (LHS CC2 RHS).
1661 SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1662 SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1664 // Otherwise, the pattern is (LHS CC1 LHS) Opc (RHS CC2 RHS)
1665 SetCC1 = DAG.getSetCC(dl, VT, LHS, LHS, CC1);
1666 SetCC2 = DAG.getSetCC(dl, VT, RHS, RHS, CC2);
1668 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1676 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
1677 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1678 /// a load from the stack slot to DestVT, extending it if needed.
1679 /// The resultant code need not be legal.
1680 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
1684 // Create the stack frame object.
1686 TLI.getDataLayout()->getPrefTypeAlignment(SrcOp.getValueType().
1687 getTypeForEVT(*DAG.getContext()));
1688 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1690 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1691 int SPFI = StackPtrFI->getIndex();
1692 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(SPFI);
1694 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
1695 unsigned SlotSize = SlotVT.getSizeInBits();
1696 unsigned DestSize = DestVT.getSizeInBits();
1697 Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
1698 unsigned DestAlign = TLI.getDataLayout()->getPrefTypeAlignment(DestType);
1700 // Emit a store to the stack slot. Use a truncstore if the input value is
1701 // later than DestVT.
1704 if (SrcSize > SlotSize)
1705 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1706 PtrInfo, SlotVT, false, false, SrcAlign);
1708 assert(SrcSize == SlotSize && "Invalid store");
1709 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1710 PtrInfo, false, false, SrcAlign);
1713 // Result is a load from the stack slot.
1714 if (SlotSize == DestSize)
1715 return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo,
1716 false, false, false, DestAlign);
1718 assert(SlotSize < DestSize && "Unknown extension!");
1719 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr,
1720 PtrInfo, SlotVT, false, false, DestAlign);
1723 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1724 DebugLoc dl = Node->getDebugLoc();
1725 // Create a vector sized/aligned stack slot, store the value to element #0,
1726 // then load the whole vector back out.
1727 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1729 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1730 int SPFI = StackPtrFI->getIndex();
1732 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0),
1734 MachinePointerInfo::getFixedStack(SPFI),
1735 Node->getValueType(0).getVectorElementType(),
1737 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
1738 MachinePointerInfo::getFixedStack(SPFI),
1739 false, false, false, 0);
1743 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
1744 /// support the operation, but do support the resultant vector type.
1745 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1746 unsigned NumElems = Node->getNumOperands();
1747 SDValue Value1, Value2;
1748 DebugLoc dl = Node->getDebugLoc();
1749 EVT VT = Node->getValueType(0);
1750 EVT OpVT = Node->getOperand(0).getValueType();
1751 EVT EltVT = VT.getVectorElementType();
1753 // If the only non-undef value is the low element, turn this into a
1754 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1755 bool isOnlyLowElement = true;
1756 bool MoreThanTwoValues = false;
1757 bool isConstant = true;
1758 for (unsigned i = 0; i < NumElems; ++i) {
1759 SDValue V = Node->getOperand(i);
1760 if (V.getOpcode() == ISD::UNDEF)
1763 isOnlyLowElement = false;
1764 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1767 if (!Value1.getNode()) {
1769 } else if (!Value2.getNode()) {
1772 } else if (V != Value1 && V != Value2) {
1773 MoreThanTwoValues = true;
1777 if (!Value1.getNode())
1778 return DAG.getUNDEF(VT);
1780 if (isOnlyLowElement)
1781 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1783 // If all elements are constants, create a load from the constant pool.
1785 SmallVector<Constant*, 16> CV;
1786 for (unsigned i = 0, e = NumElems; i != e; ++i) {
1787 if (ConstantFPSDNode *V =
1788 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1789 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1790 } else if (ConstantSDNode *V =
1791 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1793 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1795 // If OpVT and EltVT don't match, EltVT is not legal and the
1796 // element values have been promoted/truncated earlier. Undo this;
1797 // we don't want a v16i8 to become a v16i32 for example.
1798 const ConstantInt *CI = V->getConstantIntValue();
1799 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
1800 CI->getZExtValue()));
1803 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
1804 Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
1805 CV.push_back(UndefValue::get(OpNTy));
1808 Constant *CP = ConstantVector::get(CV);
1809 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
1810 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
1811 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
1812 MachinePointerInfo::getConstantPool(),
1813 false, false, false, Alignment);
1816 if (!MoreThanTwoValues) {
1817 SmallVector<int, 8> ShuffleVec(NumElems, -1);
1818 for (unsigned i = 0; i < NumElems; ++i) {
1819 SDValue V = Node->getOperand(i);
1820 if (V.getOpcode() == ISD::UNDEF)
1822 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
1824 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
1825 // Get the splatted value into the low element of a vector register.
1826 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
1828 if (Value2.getNode())
1829 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
1831 Vec2 = DAG.getUNDEF(VT);
1833 // Return shuffle(LowValVec, undef, <0,0,0,0>)
1834 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
1838 // Otherwise, we can't handle this case efficiently.
1839 return ExpandVectorBuildThroughStack(Node);
1842 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
1843 // does not fit into a register, return the lo part and set the hi part to the
1844 // by-reg argument. If it does fit into a single register, return the result
1845 // and leave the Hi part unset.
1846 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
1848 TargetLowering::ArgListTy Args;
1849 TargetLowering::ArgListEntry Entry;
1850 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1851 EVT ArgVT = Node->getOperand(i).getValueType();
1852 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1853 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
1854 Entry.isSExt = isSigned;
1855 Entry.isZExt = !isSigned;
1856 Args.push_back(Entry);
1858 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1859 TLI.getPointerTy());
1861 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
1863 // By default, the input chain to this libcall is the entry node of the
1864 // function. If the libcall is going to be emitted as a tail call then
1865 // TLI.isUsedByReturnOnly will change it to the right chain if the return
1866 // node which is being folded has a non-entry input chain.
1867 SDValue InChain = DAG.getEntryNode();
1869 // isTailCall may be true since the callee does not reference caller stack
1870 // frame. Check if it's in the right position.
1871 SDValue TCChain = InChain;
1872 bool isTailCall = isInTailCallPosition(DAG, Node, TCChain, TLI);
1877 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
1878 0, TLI.getLibcallCallingConv(LC), isTailCall,
1879 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
1880 Callee, Args, DAG, Node->getDebugLoc());
1881 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
1884 if (!CallInfo.second.getNode())
1885 // It's a tailcall, return the chain (which is the DAG root).
1886 return DAG.getRoot();
1888 return CallInfo.first;
1891 /// ExpandLibCall - Generate a libcall taking the given operands as arguments
1892 /// and returning a result of type RetVT.
1893 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, EVT RetVT,
1894 const SDValue *Ops, unsigned NumOps,
1895 bool isSigned, DebugLoc dl) {
1896 TargetLowering::ArgListTy Args;
1897 Args.reserve(NumOps);
1899 TargetLowering::ArgListEntry Entry;
1900 for (unsigned i = 0; i != NumOps; ++i) {
1901 Entry.Node = Ops[i];
1902 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
1903 Entry.isSExt = isSigned;
1904 Entry.isZExt = !isSigned;
1905 Args.push_back(Entry);
1907 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1908 TLI.getPointerTy());
1910 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
1912 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
1913 false, 0, TLI.getLibcallCallingConv(LC),
1914 /*isTailCall=*/false,
1915 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
1916 Callee, Args, DAG, dl);
1917 std::pair<SDValue,SDValue> CallInfo = TLI.LowerCallTo(CLI);
1919 return CallInfo.first;
1922 // ExpandChainLibCall - Expand a node into a call to a libcall. Similar to
1923 // ExpandLibCall except that the first operand is the in-chain.
1924 std::pair<SDValue, SDValue>
1925 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
1928 SDValue InChain = Node->getOperand(0);
1930 TargetLowering::ArgListTy Args;
1931 TargetLowering::ArgListEntry Entry;
1932 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) {
1933 EVT ArgVT = Node->getOperand(i).getValueType();
1934 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1935 Entry.Node = Node->getOperand(i);
1937 Entry.isSExt = isSigned;
1938 Entry.isZExt = !isSigned;
1939 Args.push_back(Entry);
1941 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1942 TLI.getPointerTy());
1944 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
1946 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
1947 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
1948 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
1949 Callee, Args, DAG, Node->getDebugLoc());
1950 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
1955 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
1956 RTLIB::Libcall Call_F32,
1957 RTLIB::Libcall Call_F64,
1958 RTLIB::Libcall Call_F80,
1959 RTLIB::Libcall Call_PPCF128) {
1961 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
1962 default: llvm_unreachable("Unexpected request for libcall!");
1963 case MVT::f32: LC = Call_F32; break;
1964 case MVT::f64: LC = Call_F64; break;
1965 case MVT::f80: LC = Call_F80; break;
1966 case MVT::ppcf128: LC = Call_PPCF128; break;
1968 return ExpandLibCall(LC, Node, false);
1971 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
1972 RTLIB::Libcall Call_I8,
1973 RTLIB::Libcall Call_I16,
1974 RTLIB::Libcall Call_I32,
1975 RTLIB::Libcall Call_I64,
1976 RTLIB::Libcall Call_I128) {
1978 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
1979 default: llvm_unreachable("Unexpected request for libcall!");
1980 case MVT::i8: LC = Call_I8; break;
1981 case MVT::i16: LC = Call_I16; break;
1982 case MVT::i32: LC = Call_I32; break;
1983 case MVT::i64: LC = Call_I64; break;
1984 case MVT::i128: LC = Call_I128; break;
1986 return ExpandLibCall(LC, Node, isSigned);
1989 /// isDivRemLibcallAvailable - Return true if divmod libcall is available.
1990 static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
1991 const TargetLowering &TLI) {
1993 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
1994 default: llvm_unreachable("Unexpected request for libcall!");
1995 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
1996 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
1997 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
1998 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
1999 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2002 return TLI.getLibcallName(LC) != 0;
2005 /// useDivRem - Only issue divrem libcall if both quotient and remainder are
2007 static bool useDivRem(SDNode *Node, bool isSigned, bool isDIV) {
2008 // The other use might have been replaced with a divrem already.
2009 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2010 unsigned OtherOpcode = 0;
2012 OtherOpcode = isDIV ? ISD::SREM : ISD::SDIV;
2014 OtherOpcode = isDIV ? ISD::UREM : ISD::UDIV;
2016 SDValue Op0 = Node->getOperand(0);
2017 SDValue Op1 = Node->getOperand(1);
2018 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2019 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2023 if ((User->getOpcode() == OtherOpcode || User->getOpcode() == DivRemOpc) &&
2024 User->getOperand(0) == Op0 &&
2025 User->getOperand(1) == Op1)
2031 /// ExpandDivRemLibCall - Issue libcalls to __{u}divmod to compute div / rem
2034 SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
2035 SmallVectorImpl<SDValue> &Results) {
2036 unsigned Opcode = Node->getOpcode();
2037 bool isSigned = Opcode == ISD::SDIVREM;
2040 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
2041 default: llvm_unreachable("Unexpected request for libcall!");
2042 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2043 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2044 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2045 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2046 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2049 // The input chain to this libcall is the entry node of the function.
2050 // Legalizing the call will automatically add the previous call to the
2052 SDValue InChain = DAG.getEntryNode();
2054 EVT RetVT = Node->getValueType(0);
2055 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2057 TargetLowering::ArgListTy Args;
2058 TargetLowering::ArgListEntry Entry;
2059 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2060 EVT ArgVT = Node->getOperand(i).getValueType();
2061 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2062 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
2063 Entry.isSExt = isSigned;
2064 Entry.isZExt = !isSigned;
2065 Args.push_back(Entry);
2068 // Also pass the return address of the remainder.
2069 SDValue FIPtr = DAG.CreateStackTemporary(RetVT);
2071 Entry.Ty = RetTy->getPointerTo();
2072 Entry.isSExt = isSigned;
2073 Entry.isZExt = !isSigned;
2074 Args.push_back(Entry);
2076 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2077 TLI.getPointerTy());
2079 DebugLoc dl = Node->getDebugLoc();
2081 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
2082 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
2083 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2084 Callee, Args, DAG, dl);
2085 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2087 // Remainder is loaded back from the stack frame.
2088 SDValue Rem = DAG.getLoad(RetVT, dl, CallInfo.second, FIPtr,
2089 MachinePointerInfo(), false, false, false, 0);
2090 Results.push_back(CallInfo.first);
2091 Results.push_back(Rem);
2094 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
2095 /// INT_TO_FP operation of the specified operand when the target requests that
2096 /// we expand it. At this point, we know that the result and operand types are
2097 /// legal for the target.
2098 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
2102 if (Op0.getValueType() == MVT::i32 && TLI.isTypeLegal(MVT::f64)) {
2103 // simple 32-bit [signed|unsigned] integer to float/double expansion
2105 // Get the stack frame index of a 8 byte buffer.
2106 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2108 // word offset constant for Hi/Lo address computation
2109 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
2110 // set up Hi and Lo (into buffer) address based on endian
2111 SDValue Hi = StackSlot;
2112 SDValue Lo = DAG.getNode(ISD::ADD, dl,
2113 TLI.getPointerTy(), StackSlot, WordOff);
2114 if (TLI.isLittleEndian())
2117 // if signed map to unsigned space
2120 // constant used to invert sign bit (signed to unsigned mapping)
2121 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
2122 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2126 // store the lo of the constructed double - based on integer input
2127 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
2128 Op0Mapped, Lo, MachinePointerInfo(),
2130 // initial hi portion of constructed double
2131 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
2132 // store the hi of the constructed double - biased exponent
2133 SDValue Store2 = DAG.getStore(Store1, dl, InitialHi, Hi,
2134 MachinePointerInfo(),
2136 // load the constructed double
2137 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot,
2138 MachinePointerInfo(), false, false, false, 0);
2139 // FP constant to bias correct the final result
2140 SDValue Bias = DAG.getConstantFP(isSigned ?
2141 BitsToDouble(0x4330000080000000ULL) :
2142 BitsToDouble(0x4330000000000000ULL),
2144 // subtract the bias
2145 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2148 // handle final rounding
2149 if (DestVT == MVT::f64) {
2152 } else if (DestVT.bitsLT(MVT::f64)) {
2153 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2154 DAG.getIntPtrConstant(0));
2155 } else if (DestVT.bitsGT(MVT::f64)) {
2156 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2160 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2161 // Code below here assumes !isSigned without checking again.
2163 // Implementation of unsigned i64 to f64 following the algorithm in
2164 // __floatundidf in compiler_rt. This implementation has the advantage
2165 // of performing rounding correctly, both in the default rounding mode
2166 // and in all alternate rounding modes.
2167 // TODO: Generalize this for use with other types.
2168 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
2170 DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64);
2171 SDValue TwoP84PlusTwoP52 =
2172 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64);
2174 DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64);
2176 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32);
2177 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2178 DAG.getConstant(32, MVT::i64));
2179 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2180 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2181 SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr);
2182 SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr);
2183 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
2185 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
2188 // Implementation of unsigned i64 to f32.
2189 // TODO: Generalize this for use with other types.
2190 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) {
2191 // For unsigned conversions, convert them to signed conversions using the
2192 // algorithm from the x86_64 __floatundidf in compiler_rt.
2194 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0);
2196 SDValue ShiftConst =
2197 DAG.getConstant(1, TLI.getShiftAmountTy(Op0.getValueType()));
2198 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
2199 SDValue AndConst = DAG.getConstant(1, MVT::i64);
2200 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst);
2201 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr);
2203 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or);
2204 SDValue Slow = DAG.getNode(ISD::FADD, dl, MVT::f32, SignCvt, SignCvt);
2206 // TODO: This really should be implemented using a branch rather than a
2207 // select. We happen to get lucky and machinesink does the right
2208 // thing most of the time. This would be a good candidate for a
2209 //pseudo-op, or, even better, for whole-function isel.
2210 SDValue SignBitTest = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2211 Op0, DAG.getConstant(0, MVT::i64), ISD::SETLT);
2212 return DAG.getNode(ISD::SELECT, dl, MVT::f32, SignBitTest, Slow, Fast);
2215 // Otherwise, implement the fully general conversion.
2217 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2218 DAG.getConstant(UINT64_C(0xfffffffffffff800), MVT::i64));
2219 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
2220 DAG.getConstant(UINT64_C(0x800), MVT::i64));
2221 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2222 DAG.getConstant(UINT64_C(0x7ff), MVT::i64));
2223 SDValue Ne = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2224 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE);
2225 SDValue Sel = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ne, Or, Op0);
2226 SDValue Ge = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2227 Op0, DAG.getConstant(UINT64_C(0x0020000000000000), MVT::i64),
2229 SDValue Sel2 = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ge, Sel, Op0);
2230 EVT SHVT = TLI.getShiftAmountTy(Sel2.getValueType());
2232 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2233 DAG.getConstant(32, SHVT));
2234 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh);
2235 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc);
2237 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), MVT::f64);
2238 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt);
2239 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2);
2240 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo);
2241 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2);
2242 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd,
2243 DAG.getIntPtrConstant(0));
2246 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2248 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()),
2249 Op0, DAG.getConstant(0, Op0.getValueType()),
2251 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
2252 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
2253 SignSet, Four, Zero);
2255 // If the sign bit of the integer is set, the large number will be treated
2256 // as a negative number. To counteract this, the dynamic code adds an
2257 // offset depending on the data type.
2259 switch (Op0.getValueType().getSimpleVT().SimpleTy) {
2260 default: llvm_unreachable("Unsupported integer type!");
2261 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2262 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2263 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2264 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2266 if (TLI.isLittleEndian()) FF <<= 32;
2267 Constant *FudgeFactor = ConstantInt::get(
2268 Type::getInt64Ty(*DAG.getContext()), FF);
2270 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
2271 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2272 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
2273 Alignment = std::min(Alignment, 4u);
2275 if (DestVT == MVT::f32)
2276 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2277 MachinePointerInfo::getConstantPool(),
2278 false, false, false, Alignment);
2280 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
2281 DAG.getEntryNode(), CPIdx,
2282 MachinePointerInfo::getConstantPool(),
2283 MVT::f32, false, false, Alignment);
2284 HandleSDNode Handle(Load);
2285 LegalizeOp(Load.getNode());
2286 FudgeInReg = Handle.getValue();
2289 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2292 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
2293 /// *INT_TO_FP operation of the specified operand when the target requests that
2294 /// we promote it. At this point, we know that the result and operand types are
2295 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2296 /// operation that takes a larger input.
2297 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2301 // First step, figure out the appropriate *INT_TO_FP operation to use.
2302 EVT NewInTy = LegalOp.getValueType();
2304 unsigned OpToUse = 0;
2306 // Scan for the appropriate larger type to use.
2308 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2309 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2311 // If the target supports SINT_TO_FP of this type, use it.
2312 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2313 OpToUse = ISD::SINT_TO_FP;
2316 if (isSigned) continue;
2318 // If the target supports UINT_TO_FP of this type, use it.
2319 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2320 OpToUse = ISD::UINT_TO_FP;
2324 // Otherwise, try a larger type.
2327 // Okay, we found the operation and type to use. Zero extend our input to the
2328 // desired type then run the operation on it.
2329 return DAG.getNode(OpToUse, dl, DestVT,
2330 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2331 dl, NewInTy, LegalOp));
2334 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
2335 /// FP_TO_*INT operation of the specified operand when the target requests that
2336 /// we promote it. At this point, we know that the result and operand types are
2337 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2338 /// operation that returns a larger result.
2339 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2343 // First step, figure out the appropriate FP_TO*INT operation to use.
2344 EVT NewOutTy = DestVT;
2346 unsigned OpToUse = 0;
2348 // Scan for the appropriate larger type to use.
2350 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2351 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2353 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2354 OpToUse = ISD::FP_TO_SINT;
2358 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2359 OpToUse = ISD::FP_TO_UINT;
2363 // Otherwise, try a larger type.
2367 // Okay, we found the operation and type to use.
2368 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2370 // Truncate the result of the extended FP_TO_*INT operation to the desired
2372 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2375 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
2377 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) {
2378 EVT VT = Op.getValueType();
2379 EVT SHVT = TLI.getShiftAmountTy(VT);
2380 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2381 switch (VT.getSimpleVT().SimpleTy) {
2382 default: llvm_unreachable("Unhandled Expand type in BSWAP!");
2384 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2385 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2386 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2388 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2389 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2390 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2391 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2392 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
2393 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
2394 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2395 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2396 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2398 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
2399 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
2400 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2401 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2402 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2403 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2404 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
2405 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
2406 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
2407 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
2408 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
2409 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
2410 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
2411 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
2412 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2413 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2414 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2415 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2416 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2417 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2418 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2422 /// SplatByte - Distribute ByteVal over NumBits bits.
2423 // FIXME: Move this helper to a common place.
2424 static APInt SplatByte(unsigned NumBits, uint8_t ByteVal) {
2425 APInt Val = APInt(NumBits, ByteVal);
2427 for (unsigned i = NumBits; i > 8; i >>= 1) {
2428 Val = (Val << Shift) | Val;
2434 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
2436 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2439 default: llvm_unreachable("Cannot expand this yet!");
2441 EVT VT = Op.getValueType();
2442 EVT ShVT = TLI.getShiftAmountTy(VT);
2443 unsigned Len = VT.getSizeInBits();
2445 assert(VT.isInteger() && Len <= 128 && Len % 8 == 0 &&
2446 "CTPOP not implemented for this type.");
2448 // This is the "best" algorithm from
2449 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
2451 SDValue Mask55 = DAG.getConstant(SplatByte(Len, 0x55), VT);
2452 SDValue Mask33 = DAG.getConstant(SplatByte(Len, 0x33), VT);
2453 SDValue Mask0F = DAG.getConstant(SplatByte(Len, 0x0F), VT);
2454 SDValue Mask01 = DAG.getConstant(SplatByte(Len, 0x01), VT);
2456 // v = v - ((v >> 1) & 0x55555555...)
2457 Op = DAG.getNode(ISD::SUB, dl, VT, Op,
2458 DAG.getNode(ISD::AND, dl, VT,
2459 DAG.getNode(ISD::SRL, dl, VT, Op,
2460 DAG.getConstant(1, ShVT)),
2462 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
2463 Op = DAG.getNode(ISD::ADD, dl, VT,
2464 DAG.getNode(ISD::AND, dl, VT, Op, Mask33),
2465 DAG.getNode(ISD::AND, dl, VT,
2466 DAG.getNode(ISD::SRL, dl, VT, Op,
2467 DAG.getConstant(2, ShVT)),
2469 // v = (v + (v >> 4)) & 0x0F0F0F0F...
2470 Op = DAG.getNode(ISD::AND, dl, VT,
2471 DAG.getNode(ISD::ADD, dl, VT, Op,
2472 DAG.getNode(ISD::SRL, dl, VT, Op,
2473 DAG.getConstant(4, ShVT))),
2475 // v = (v * 0x01010101...) >> (Len - 8)
2476 Op = DAG.getNode(ISD::SRL, dl, VT,
2477 DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
2478 DAG.getConstant(Len - 8, ShVT));
2482 case ISD::CTLZ_ZERO_UNDEF:
2483 // This trivially expands to CTLZ.
2484 return DAG.getNode(ISD::CTLZ, dl, Op.getValueType(), Op);
2486 // for now, we do this:
2487 // x = x | (x >> 1);
2488 // x = x | (x >> 2);
2490 // x = x | (x >>16);
2491 // x = x | (x >>32); // for 64-bit input
2492 // return popcount(~x);
2494 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
2495 EVT VT = Op.getValueType();
2496 EVT ShVT = TLI.getShiftAmountTy(VT);
2497 unsigned len = VT.getSizeInBits();
2498 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2499 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2500 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2501 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2503 Op = DAG.getNOT(dl, Op, VT);
2504 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2506 case ISD::CTTZ_ZERO_UNDEF:
2507 // This trivially expands to CTTZ.
2508 return DAG.getNode(ISD::CTTZ, dl, Op.getValueType(), Op);
2510 // for now, we use: { return popcount(~x & (x - 1)); }
2511 // unless the target has ctlz but not ctpop, in which case we use:
2512 // { return 32 - nlz(~x & (x-1)); }
2513 // see also http://www.hackersdelight.org/HDcode/ntz.cc
2514 EVT VT = Op.getValueType();
2515 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2516 DAG.getNOT(dl, Op, VT),
2517 DAG.getNode(ISD::SUB, dl, VT, Op,
2518 DAG.getConstant(1, VT)));
2519 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2520 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2521 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2522 return DAG.getNode(ISD::SUB, dl, VT,
2523 DAG.getConstant(VT.getSizeInBits(), VT),
2524 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2525 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2530 std::pair <SDValue, SDValue> SelectionDAGLegalize::ExpandAtomic(SDNode *Node) {
2531 unsigned Opc = Node->getOpcode();
2532 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
2537 llvm_unreachable("Unhandled atomic intrinsic Expand!");
2538 case ISD::ATOMIC_SWAP:
2539 switch (VT.SimpleTy) {
2540 default: llvm_unreachable("Unexpected value type for atomic!");
2541 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break;
2542 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
2543 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
2544 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
2547 case ISD::ATOMIC_CMP_SWAP:
2548 switch (VT.SimpleTy) {
2549 default: llvm_unreachable("Unexpected value type for atomic!");
2550 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break;
2551 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;
2552 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;
2553 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
2556 case ISD::ATOMIC_LOAD_ADD:
2557 switch (VT.SimpleTy) {
2558 default: llvm_unreachable("Unexpected value type for atomic!");
2559 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break;
2560 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;
2561 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;
2562 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
2565 case ISD::ATOMIC_LOAD_SUB:
2566 switch (VT.SimpleTy) {
2567 default: llvm_unreachable("Unexpected value type for atomic!");
2568 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break;
2569 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;
2570 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;
2571 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
2574 case ISD::ATOMIC_LOAD_AND:
2575 switch (VT.SimpleTy) {
2576 default: llvm_unreachable("Unexpected value type for atomic!");
2577 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break;
2578 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;
2579 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;
2580 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
2583 case ISD::ATOMIC_LOAD_OR:
2584 switch (VT.SimpleTy) {
2585 default: llvm_unreachable("Unexpected value type for atomic!");
2586 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break;
2587 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;
2588 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;
2589 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
2592 case ISD::ATOMIC_LOAD_XOR:
2593 switch (VT.SimpleTy) {
2594 default: llvm_unreachable("Unexpected value type for atomic!");
2595 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break;
2596 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;
2597 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;
2598 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
2601 case ISD::ATOMIC_LOAD_NAND:
2602 switch (VT.SimpleTy) {
2603 default: llvm_unreachable("Unexpected value type for atomic!");
2604 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break;
2605 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;
2606 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;
2607 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
2612 return ExpandChainLibCall(LC, Node, false);
2615 void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
2616 SmallVector<SDValue, 8> Results;
2617 DebugLoc dl = Node->getDebugLoc();
2618 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2619 switch (Node->getOpcode()) {
2622 case ISD::CTLZ_ZERO_UNDEF:
2624 case ISD::CTTZ_ZERO_UNDEF:
2625 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
2626 Results.push_back(Tmp1);
2629 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2631 case ISD::FRAMEADDR:
2632 case ISD::RETURNADDR:
2633 case ISD::FRAME_TO_ARGS_OFFSET:
2634 Results.push_back(DAG.getConstant(0, Node->getValueType(0)));
2636 case ISD::FLT_ROUNDS_:
2637 Results.push_back(DAG.getConstant(1, Node->getValueType(0)));
2639 case ISD::EH_RETURN:
2643 case ISD::EH_SJLJ_LONGJMP:
2644 // If the target didn't expand these, there's nothing to do, so just
2645 // preserve the chain and be done.
2646 Results.push_back(Node->getOperand(0));
2648 case ISD::EH_SJLJ_SETJMP:
2649 // If the target didn't expand this, just return 'zero' and preserve the
2651 Results.push_back(DAG.getConstant(0, MVT::i32));
2652 Results.push_back(Node->getOperand(0));
2654 case ISD::ATOMIC_FENCE:
2655 case ISD::MEMBARRIER: {
2656 // If the target didn't lower this, lower it to '__sync_synchronize()' call
2657 // FIXME: handle "fence singlethread" more efficiently.
2658 TargetLowering::ArgListTy Args;
2660 CallLoweringInfo CLI(Node->getOperand(0),
2661 Type::getVoidTy(*DAG.getContext()),
2662 false, false, false, false, 0, CallingConv::C,
2663 /*isTailCall=*/false,
2664 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2665 DAG.getExternalSymbol("__sync_synchronize",
2666 TLI.getPointerTy()),
2668 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
2670 Results.push_back(CallResult.second);
2673 case ISD::ATOMIC_LOAD: {
2674 // There is no libcall for atomic load; fake it with ATOMIC_CMP_SWAP.
2675 SDValue Zero = DAG.getConstant(0, Node->getValueType(0));
2676 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl,
2677 cast<AtomicSDNode>(Node)->getMemoryVT(),
2678 Node->getOperand(0),
2679 Node->getOperand(1), Zero, Zero,
2680 cast<AtomicSDNode>(Node)->getMemOperand(),
2681 cast<AtomicSDNode>(Node)->getOrdering(),
2682 cast<AtomicSDNode>(Node)->getSynchScope());
2683 Results.push_back(Swap.getValue(0));
2684 Results.push_back(Swap.getValue(1));
2687 case ISD::ATOMIC_STORE: {
2688 // There is no libcall for atomic store; fake it with ATOMIC_SWAP.
2689 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
2690 cast<AtomicSDNode>(Node)->getMemoryVT(),
2691 Node->getOperand(0),
2692 Node->getOperand(1), Node->getOperand(2),
2693 cast<AtomicSDNode>(Node)->getMemOperand(),
2694 cast<AtomicSDNode>(Node)->getOrdering(),
2695 cast<AtomicSDNode>(Node)->getSynchScope());
2696 Results.push_back(Swap.getValue(1));
2699 // By default, atomic intrinsics are marked Legal and lowered. Targets
2700 // which don't support them directly, however, may want libcalls, in which
2701 // case they mark them Expand, and we get here.
2702 case ISD::ATOMIC_SWAP:
2703 case ISD::ATOMIC_LOAD_ADD:
2704 case ISD::ATOMIC_LOAD_SUB:
2705 case ISD::ATOMIC_LOAD_AND:
2706 case ISD::ATOMIC_LOAD_OR:
2707 case ISD::ATOMIC_LOAD_XOR:
2708 case ISD::ATOMIC_LOAD_NAND:
2709 case ISD::ATOMIC_LOAD_MIN:
2710 case ISD::ATOMIC_LOAD_MAX:
2711 case ISD::ATOMIC_LOAD_UMIN:
2712 case ISD::ATOMIC_LOAD_UMAX:
2713 case ISD::ATOMIC_CMP_SWAP: {
2714 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node);
2715 Results.push_back(Tmp.first);
2716 Results.push_back(Tmp.second);
2719 case ISD::DYNAMIC_STACKALLOC:
2720 ExpandDYNAMIC_STACKALLOC(Node, Results);
2722 case ISD::MERGE_VALUES:
2723 for (unsigned i = 0; i < Node->getNumValues(); i++)
2724 Results.push_back(Node->getOperand(i));
2727 EVT VT = Node->getValueType(0);
2729 Results.push_back(DAG.getConstant(0, VT));
2731 assert(VT.isFloatingPoint() && "Unknown value type!");
2732 Results.push_back(DAG.getConstantFP(0, VT));
2737 // If this operation is not supported, lower it to 'abort()' call
2738 TargetLowering::ArgListTy Args;
2740 CallLoweringInfo CLI(Node->getOperand(0),
2741 Type::getVoidTy(*DAG.getContext()),
2742 false, false, false, false, 0, CallingConv::C,
2743 /*isTailCall=*/false,
2744 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2745 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
2747 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
2749 Results.push_back(CallResult.second);
2754 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
2755 Node->getValueType(0), dl);
2756 Results.push_back(Tmp1);
2758 case ISD::FP_EXTEND:
2759 Tmp1 = EmitStackConvert(Node->getOperand(0),
2760 Node->getOperand(0).getValueType(),
2761 Node->getValueType(0), dl);
2762 Results.push_back(Tmp1);
2764 case ISD::SIGN_EXTEND_INREG: {
2765 // NOTE: we could fall back on load/store here too for targets without
2766 // SAR. However, it is doubtful that any exist.
2767 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2768 EVT VT = Node->getValueType(0);
2769 EVT ShiftAmountTy = TLI.getShiftAmountTy(VT);
2772 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
2773 ExtraVT.getScalarType().getSizeInBits();
2774 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy);
2775 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
2776 Node->getOperand(0), ShiftCst);
2777 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
2778 Results.push_back(Tmp1);
2781 case ISD::FP_ROUND_INREG: {
2782 // The only way we can lower this is to turn it into a TRUNCSTORE,
2783 // EXTLOAD pair, targeting a temporary location (a stack slot).
2785 // NOTE: there is a choice here between constantly creating new stack
2786 // slots and always reusing the same one. We currently always create
2787 // new ones, as reuse may inhibit scheduling.
2788 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2789 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
2790 Node->getValueType(0), dl);
2791 Results.push_back(Tmp1);
2794 case ISD::SINT_TO_FP:
2795 case ISD::UINT_TO_FP:
2796 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
2797 Node->getOperand(0), Node->getValueType(0), dl);
2798 Results.push_back(Tmp1);
2800 case ISD::FP_TO_UINT: {
2801 SDValue True, False;
2802 EVT VT = Node->getOperand(0).getValueType();
2803 EVT NVT = Node->getValueType(0);
2804 APFloat apf(APInt::getNullValue(VT.getSizeInBits()));
2805 APInt x = APInt::getSignBit(NVT.getSizeInBits());
2806 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
2807 Tmp1 = DAG.getConstantFP(apf, VT);
2808 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
2809 Node->getOperand(0),
2811 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
2812 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
2813 DAG.getNode(ISD::FSUB, dl, VT,
2814 Node->getOperand(0), Tmp1));
2815 False = DAG.getNode(ISD::XOR, dl, NVT, False,
2816 DAG.getConstant(x, NVT));
2817 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False);
2818 Results.push_back(Tmp1);
2822 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2823 EVT VT = Node->getValueType(0);
2824 Tmp1 = Node->getOperand(0);
2825 Tmp2 = Node->getOperand(1);
2826 unsigned Align = Node->getConstantOperandVal(3);
2828 SDValue VAListLoad = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2,
2829 MachinePointerInfo(V),
2830 false, false, false, 0);
2831 SDValue VAList = VAListLoad;
2833 if (Align > TLI.getMinStackArgumentAlignment()) {
2834 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
2836 VAList = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
2837 DAG.getConstant(Align - 1,
2838 TLI.getPointerTy()));
2840 VAList = DAG.getNode(ISD::AND, dl, TLI.getPointerTy(), VAList,
2841 DAG.getConstant(-(int64_t)Align,
2842 TLI.getPointerTy()));
2845 // Increment the pointer, VAList, to the next vaarg
2846 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
2847 DAG.getConstant(TLI.getDataLayout()->
2848 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())),
2849 TLI.getPointerTy()));
2850 // Store the incremented VAList to the legalized pointer
2851 Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2,
2852 MachinePointerInfo(V), false, false, 0);
2853 // Load the actual argument out of the pointer VAList
2854 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(),
2855 false, false, false, 0));
2856 Results.push_back(Results[0].getValue(1));
2860 // This defaults to loading a pointer from the input and storing it to the
2861 // output, returning the chain.
2862 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
2863 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
2864 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0),
2865 Node->getOperand(2), MachinePointerInfo(VS),
2866 false, false, false, 0);
2867 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1),
2868 MachinePointerInfo(VD), false, false, 0);
2869 Results.push_back(Tmp1);
2872 case ISD::EXTRACT_VECTOR_ELT:
2873 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
2874 // This must be an access of the only element. Return it.
2875 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
2876 Node->getOperand(0));
2878 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
2879 Results.push_back(Tmp1);
2881 case ISD::EXTRACT_SUBVECTOR:
2882 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
2884 case ISD::INSERT_SUBVECTOR:
2885 Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0)));
2887 case ISD::CONCAT_VECTORS: {
2888 Results.push_back(ExpandVectorBuildThroughStack(Node));
2891 case ISD::SCALAR_TO_VECTOR:
2892 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
2894 case ISD::INSERT_VECTOR_ELT:
2895 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
2896 Node->getOperand(1),
2897 Node->getOperand(2), dl));
2899 case ISD::VECTOR_SHUFFLE: {
2900 SmallVector<int, 32> NewMask;
2901 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
2903 EVT VT = Node->getValueType(0);
2904 EVT EltVT = VT.getVectorElementType();
2905 SDValue Op0 = Node->getOperand(0);
2906 SDValue Op1 = Node->getOperand(1);
2907 if (!TLI.isTypeLegal(EltVT)) {
2909 EVT NewEltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
2911 // BUILD_VECTOR operands are allowed to be wider than the element type.
2912 // But if NewEltVT is smaller that EltVT the BUILD_VECTOR does not accept it
2913 if (NewEltVT.bitsLT(EltVT)) {
2915 // Convert shuffle node.
2916 // If original node was v4i64 and the new EltVT is i32,
2917 // cast operands to v8i32 and re-build the mask.
2919 // Calculate new VT, the size of the new VT should be equal to original.
2920 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), NewEltVT,
2921 VT.getSizeInBits()/NewEltVT.getSizeInBits());
2922 assert(NewVT.bitsEq(VT));
2924 // cast operands to new VT
2925 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0);
2926 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1);
2928 // Convert the shuffle mask
2929 unsigned int factor = NewVT.getVectorNumElements()/VT.getVectorNumElements();
2931 // EltVT gets smaller
2934 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
2936 for (unsigned fi = 0; fi < factor; ++fi)
2937 NewMask.push_back(Mask[i]);
2940 for (unsigned fi = 0; fi < factor; ++fi)
2941 NewMask.push_back(Mask[i]*factor+fi);
2949 unsigned NumElems = VT.getVectorNumElements();
2950 SmallVector<SDValue, 16> Ops;
2951 for (unsigned i = 0; i != NumElems; ++i) {
2953 Ops.push_back(DAG.getUNDEF(EltVT));
2956 unsigned Idx = Mask[i];
2958 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
2960 DAG.getIntPtrConstant(Idx)));
2962 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
2964 DAG.getIntPtrConstant(Idx - NumElems)));
2967 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
2968 // We may have changed the BUILD_VECTOR type. Cast it back to the Node type.
2969 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), Tmp1);
2970 Results.push_back(Tmp1);
2973 case ISD::EXTRACT_ELEMENT: {
2974 EVT OpTy = Node->getOperand(0).getValueType();
2975 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
2977 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
2978 DAG.getConstant(OpTy.getSizeInBits()/2,
2979 TLI.getShiftAmountTy(Node->getOperand(0).getValueType())));
2980 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
2983 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
2984 Node->getOperand(0));
2986 Results.push_back(Tmp1);
2989 case ISD::STACKSAVE:
2990 // Expand to CopyFromReg if the target set
2991 // StackPointerRegisterToSaveRestore.
2992 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2993 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
2994 Node->getValueType(0)));
2995 Results.push_back(Results[0].getValue(1));
2997 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
2998 Results.push_back(Node->getOperand(0));
3001 case ISD::STACKRESTORE:
3002 // Expand to CopyToReg if the target set
3003 // StackPointerRegisterToSaveRestore.
3004 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3005 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
3006 Node->getOperand(1)));
3008 Results.push_back(Node->getOperand(0));
3011 case ISD::FCOPYSIGN:
3012 Results.push_back(ExpandFCOPYSIGN(Node));
3015 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3016 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3017 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
3018 Node->getOperand(0));
3019 Results.push_back(Tmp1);
3022 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3023 EVT VT = Node->getValueType(0);
3024 Tmp1 = Node->getOperand(0);
3025 Tmp2 = DAG.getConstantFP(0.0, VT);
3026 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
3027 Tmp1, Tmp2, ISD::SETUGT);
3028 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
3029 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3);
3030 Results.push_back(Tmp1);
3034 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3035 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128));
3038 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
3039 RTLIB::SIN_F80, RTLIB::SIN_PPCF128));
3042 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
3043 RTLIB::COS_F80, RTLIB::COS_PPCF128));
3046 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
3047 RTLIB::LOG_F80, RTLIB::LOG_PPCF128));
3050 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3051 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128));
3054 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3055 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128));
3058 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
3059 RTLIB::EXP_F80, RTLIB::EXP_PPCF128));
3062 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3063 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128));
3066 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3067 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128));
3070 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3071 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128));
3074 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3075 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128));
3078 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
3079 RTLIB::RINT_F80, RTLIB::RINT_PPCF128));
3081 case ISD::FNEARBYINT:
3082 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
3083 RTLIB::NEARBYINT_F64,
3084 RTLIB::NEARBYINT_F80,
3085 RTLIB::NEARBYINT_PPCF128));
3088 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
3089 RTLIB::POWI_F80, RTLIB::POWI_PPCF128));
3092 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
3093 RTLIB::POW_F80, RTLIB::POW_PPCF128));
3096 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
3097 RTLIB::DIV_F80, RTLIB::DIV_PPCF128));
3100 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
3101 RTLIB::REM_F80, RTLIB::REM_PPCF128));
3104 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMA_F32, RTLIB::FMA_F64,
3105 RTLIB::FMA_F80, RTLIB::FMA_PPCF128));
3107 case ISD::FP16_TO_FP32:
3108 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
3110 case ISD::FP32_TO_FP16:
3111 Results.push_back(ExpandLibCall(RTLIB::FPROUND_F32_F16, Node, false));
3113 case ISD::ConstantFP: {
3114 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
3115 // Check to see if this FP immediate is already legal.
3116 // If this is a legal constant, turn it into a TargetConstantFP node.
3117 if (!TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
3118 Results.push_back(ExpandConstantFP(CFP, true));
3121 case ISD::EHSELECTION: {
3122 unsigned Reg = TLI.getExceptionSelectorRegister();
3123 assert(Reg && "Can't expand to unknown register!");
3124 Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg,
3125 Node->getValueType(0)));
3126 Results.push_back(Results[0].getValue(1));
3129 case ISD::EXCEPTIONADDR: {
3130 unsigned Reg = TLI.getExceptionPointerRegister();
3131 assert(Reg && "Can't expand to unknown register!");
3132 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg,
3133 Node->getValueType(0)));
3134 Results.push_back(Results[0].getValue(1));
3138 EVT VT = Node->getValueType(0);
3139 assert(TLI.isOperationLegalOrCustom(ISD::FADD, VT) &&
3140 TLI.isOperationLegalOrCustom(ISD::FNEG, VT) &&
3141 "Don't know how to expand this FP subtraction!");
3142 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1));
3143 Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1);
3144 Results.push_back(Tmp1);
3148 EVT VT = Node->getValueType(0);
3149 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3150 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3151 "Don't know how to expand this subtraction!");
3152 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3153 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
3154 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, VT));
3155 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3160 EVT VT = Node->getValueType(0);
3161 SDVTList VTs = DAG.getVTList(VT, VT);
3162 bool isSigned = Node->getOpcode() == ISD::SREM;
3163 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3164 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3165 Tmp2 = Node->getOperand(0);
3166 Tmp3 = Node->getOperand(1);
3167 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3168 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3169 // If div is legal, it's better to do the normal expansion
3170 !TLI.isOperationLegalOrCustom(DivOpc, Node->getValueType(0)) &&
3171 useDivRem(Node, isSigned, false))) {
3172 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
3173 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
3175 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
3176 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3177 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3178 } else if (isSigned)
3179 Tmp1 = ExpandIntLibCall(Node, true,
3181 RTLIB::SREM_I16, RTLIB::SREM_I32,
3182 RTLIB::SREM_I64, RTLIB::SREM_I128);
3184 Tmp1 = ExpandIntLibCall(Node, false,
3186 RTLIB::UREM_I16, RTLIB::UREM_I32,
3187 RTLIB::UREM_I64, RTLIB::UREM_I128);
3188 Results.push_back(Tmp1);
3193 bool isSigned = Node->getOpcode() == ISD::SDIV;
3194 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3195 EVT VT = Node->getValueType(0);
3196 SDVTList VTs = DAG.getVTList(VT, VT);
3197 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3198 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3199 useDivRem(Node, isSigned, true)))
3200 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
3201 Node->getOperand(1));
3203 Tmp1 = ExpandIntLibCall(Node, true,
3205 RTLIB::SDIV_I16, RTLIB::SDIV_I32,
3206 RTLIB::SDIV_I64, RTLIB::SDIV_I128);
3208 Tmp1 = ExpandIntLibCall(Node, false,
3210 RTLIB::UDIV_I16, RTLIB::UDIV_I32,
3211 RTLIB::UDIV_I64, RTLIB::UDIV_I128);
3212 Results.push_back(Tmp1);
3217 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
3219 EVT VT = Node->getValueType(0);
3220 SDVTList VTs = DAG.getVTList(VT, VT);
3221 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
3222 "If this wasn't legal, it shouldn't have been created!");
3223 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
3224 Node->getOperand(1));
3225 Results.push_back(Tmp1.getValue(1));
3230 // Expand into divrem libcall
3231 ExpandDivRemLibCall(Node, Results);
3234 EVT VT = Node->getValueType(0);
3235 SDVTList VTs = DAG.getVTList(VT, VT);
3236 // See if multiply or divide can be lowered using two-result operations.
3237 // We just need the low half of the multiply; try both the signed
3238 // and unsigned forms. If the target supports both SMUL_LOHI and
3239 // UMUL_LOHI, form a preference by checking which forms of plain
3240 // MULH it supports.
3241 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3242 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3243 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3244 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3245 unsigned OpToUse = 0;
3246 if (HasSMUL_LOHI && !HasMULHS) {
3247 OpToUse = ISD::SMUL_LOHI;
3248 } else if (HasUMUL_LOHI && !HasMULHU) {
3249 OpToUse = ISD::UMUL_LOHI;
3250 } else if (HasSMUL_LOHI) {
3251 OpToUse = ISD::SMUL_LOHI;
3252 } else if (HasUMUL_LOHI) {
3253 OpToUse = ISD::UMUL_LOHI;
3256 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
3257 Node->getOperand(1)));
3260 Tmp1 = ExpandIntLibCall(Node, false,
3262 RTLIB::MUL_I16, RTLIB::MUL_I32,
3263 RTLIB::MUL_I64, RTLIB::MUL_I128);
3264 Results.push_back(Tmp1);
3269 SDValue LHS = Node->getOperand(0);
3270 SDValue RHS = Node->getOperand(1);
3271 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3272 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3274 Results.push_back(Sum);
3275 EVT OType = Node->getValueType(1);
3277 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
3279 // LHSSign -> LHS >= 0
3280 // RHSSign -> RHS >= 0
3281 // SumSign -> Sum >= 0
3284 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3286 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3288 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3289 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3290 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
3291 Node->getOpcode() == ISD::SADDO ?
3292 ISD::SETEQ : ISD::SETNE);
3294 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3295 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3297 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3298 Results.push_back(Cmp);
3303 SDValue LHS = Node->getOperand(0);
3304 SDValue RHS = Node->getOperand(1);
3305 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
3306 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3308 Results.push_back(Sum);
3309 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS,
3310 Node->getOpcode () == ISD::UADDO ?
3311 ISD::SETULT : ISD::SETUGT));
3316 EVT VT = Node->getValueType(0);
3317 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
3318 SDValue LHS = Node->getOperand(0);
3319 SDValue RHS = Node->getOperand(1);
3322 static const unsigned Ops[2][3] =
3323 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
3324 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
3325 bool isSigned = Node->getOpcode() == ISD::SMULO;
3326 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3327 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3328 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3329 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3330 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3332 TopHalf = BottomHalf.getValue(1);
3333 } else if (TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(),
3334 VT.getSizeInBits() * 2))) {
3335 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
3336 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
3337 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
3338 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3339 DAG.getIntPtrConstant(0));
3340 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3341 DAG.getIntPtrConstant(1));
3343 // We can fall back to a libcall with an illegal type for the MUL if we
3344 // have a libcall big enough.
3345 // Also, we can fall back to a division in some cases, but that's a big
3346 // performance hit in the general case.
3347 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3348 if (WideVT == MVT::i16)
3349 LC = RTLIB::MUL_I16;
3350 else if (WideVT == MVT::i32)
3351 LC = RTLIB::MUL_I32;
3352 else if (WideVT == MVT::i64)
3353 LC = RTLIB::MUL_I64;
3354 else if (WideVT == MVT::i128)
3355 LC = RTLIB::MUL_I128;
3356 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!");
3358 // The high part is obtained by SRA'ing all but one of the bits of low
3360 unsigned LoSize = VT.getSizeInBits();
3361 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, RHS,
3362 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
3363 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, VT, LHS,
3364 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
3366 // Here we're passing the 2 arguments explicitly as 4 arguments that are
3367 // pre-lowered to the correct types. This all depends upon WideVT not
3368 // being a legal type for the architecture and thus has to be split to
3370 SDValue Args[] = { LHS, HiLHS, RHS, HiRHS };
3371 SDValue Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl);
3372 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3373 DAG.getIntPtrConstant(0));
3374 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3375 DAG.getIntPtrConstant(1));
3376 // Ret is a node with an illegal type. Because such things are not
3377 // generally permitted during this phase of legalization, delete the
3378 // node. The above EXTRACT_ELEMENT nodes should have been folded.
3379 DAG.DeleteNode(Ret.getNode());
3383 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1,
3384 TLI.getShiftAmountTy(BottomHalf.getValueType()));
3385 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3386 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1,
3389 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf,
3390 DAG.getConstant(0, VT), ISD::SETNE);
3392 Results.push_back(BottomHalf);
3393 Results.push_back(TopHalf);
3396 case ISD::BUILD_PAIR: {
3397 EVT PairTy = Node->getValueType(0);
3398 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3399 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3400 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
3401 DAG.getConstant(PairTy.getSizeInBits()/2,
3402 TLI.getShiftAmountTy(PairTy)));
3403 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3407 Tmp1 = Node->getOperand(0);
3408 Tmp2 = Node->getOperand(1);
3409 Tmp3 = Node->getOperand(2);
3410 if (Tmp1.getOpcode() == ISD::SETCC) {
3411 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3413 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3415 Tmp1 = DAG.getSelectCC(dl, Tmp1,
3416 DAG.getConstant(0, Tmp1.getValueType()),
3417 Tmp2, Tmp3, ISD::SETNE);
3419 Results.push_back(Tmp1);
3422 SDValue Chain = Node->getOperand(0);
3423 SDValue Table = Node->getOperand(1);
3424 SDValue Index = Node->getOperand(2);
3426 EVT PTy = TLI.getPointerTy();
3428 const DataLayout &TD = *TLI.getDataLayout();
3429 unsigned EntrySize =
3430 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
3432 Index = DAG.getNode(ISD::MUL, dl, PTy,
3433 Index, DAG.getConstant(EntrySize, PTy));
3434 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
3436 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
3437 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
3438 MachinePointerInfo::getJumpTable(), MemVT,
3441 if (TM.getRelocationModel() == Reloc::PIC_) {
3442 // For PIC, the sequence is:
3443 // BRIND(load(Jumptable + index) + RelocBase)
3444 // RelocBase can be JumpTable, GOT or some sort of global base.
3445 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3446 TLI.getPICJumpTableRelocBase(Table, DAG));
3448 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
3449 Results.push_back(Tmp1);
3453 // Expand brcond's setcc into its constituent parts and create a BR_CC
3455 Tmp1 = Node->getOperand(0);
3456 Tmp2 = Node->getOperand(1);
3457 if (Tmp2.getOpcode() == ISD::SETCC) {
3458 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3459 Tmp1, Tmp2.getOperand(2),
3460 Tmp2.getOperand(0), Tmp2.getOperand(1),
3461 Node->getOperand(2));
3463 // We test only the i1 bit. Skip the AND if UNDEF.
3464 Tmp3 = (Tmp2.getOpcode() == ISD::UNDEF) ? Tmp2 :
3465 DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2,
3466 DAG.getConstant(1, Tmp2.getValueType()));
3467 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3468 DAG.getCondCode(ISD::SETNE), Tmp3,
3469 DAG.getConstant(0, Tmp3.getValueType()),
3470 Node->getOperand(2));
3472 Results.push_back(Tmp1);
3475 Tmp1 = Node->getOperand(0);
3476 Tmp2 = Node->getOperand(1);
3477 Tmp3 = Node->getOperand(2);
3478 LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl);
3480 // If we expanded the SETCC into an AND/OR, return the new node
3481 if (Tmp2.getNode() == 0) {
3482 Results.push_back(Tmp1);
3486 // Otherwise, SETCC for the given comparison type must be completely
3487 // illegal; expand it into a SELECT_CC.
3488 EVT VT = Node->getValueType(0);
3489 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3490 DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3);
3491 Results.push_back(Tmp1);
3494 case ISD::SELECT_CC: {
3495 Tmp1 = Node->getOperand(0); // LHS
3496 Tmp2 = Node->getOperand(1); // RHS
3497 Tmp3 = Node->getOperand(2); // True
3498 Tmp4 = Node->getOperand(3); // False
3499 SDValue CC = Node->getOperand(4);
3501 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()),
3502 Tmp1, Tmp2, CC, dl);
3504 assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!");
3505 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3506 CC = DAG.getCondCode(ISD::SETNE);
3507 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2,
3509 Results.push_back(Tmp1);
3513 Tmp1 = Node->getOperand(0); // Chain
3514 Tmp2 = Node->getOperand(2); // LHS
3515 Tmp3 = Node->getOperand(3); // RHS
3516 Tmp4 = Node->getOperand(1); // CC
3518 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()),
3519 Tmp2, Tmp3, Tmp4, dl);
3521 assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!");
3522 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
3523 Tmp4 = DAG.getCondCode(ISD::SETNE);
3524 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2,
3525 Tmp3, Node->getOperand(4));
3526 Results.push_back(Tmp1);
3529 case ISD::BUILD_VECTOR:
3530 Results.push_back(ExpandBUILD_VECTOR(Node));
3535 // Scalarize vector SRA/SRL/SHL.
3536 EVT VT = Node->getValueType(0);
3537 assert(VT.isVector() && "Unable to legalize non-vector shift");
3538 assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
3539 unsigned NumElem = VT.getVectorNumElements();
3541 SmallVector<SDValue, 8> Scalars;
3542 for (unsigned Idx = 0; Idx < NumElem; Idx++) {
3543 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3545 Node->getOperand(0), DAG.getIntPtrConstant(Idx));
3546 SDValue Sh = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3548 Node->getOperand(1), DAG.getIntPtrConstant(Idx));
3549 Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
3550 VT.getScalarType(), Ex, Sh));
3553 DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0),
3554 &Scalars[0], Scalars.size());
3555 ReplaceNode(SDValue(Node, 0), Result);
3558 case ISD::GLOBAL_OFFSET_TABLE:
3559 case ISD::GlobalAddress:
3560 case ISD::GlobalTLSAddress:
3561 case ISD::ExternalSymbol:
3562 case ISD::ConstantPool:
3563 case ISD::JumpTable:
3564 case ISD::INTRINSIC_W_CHAIN:
3565 case ISD::INTRINSIC_WO_CHAIN:
3566 case ISD::INTRINSIC_VOID:
3567 // FIXME: Custom lowering for these operations shouldn't return null!
3571 // Replace the original node with the legalized result.
3572 if (!Results.empty())
3573 ReplaceNode(Node, Results.data());
3576 void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
3577 SmallVector<SDValue, 8> Results;
3578 EVT OVT = Node->getValueType(0);
3579 if (Node->getOpcode() == ISD::UINT_TO_FP ||
3580 Node->getOpcode() == ISD::SINT_TO_FP ||
3581 Node->getOpcode() == ISD::SETCC) {
3582 OVT = Node->getOperand(0).getValueType();
3584 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3585 DebugLoc dl = Node->getDebugLoc();
3586 SDValue Tmp1, Tmp2, Tmp3;
3587 switch (Node->getOpcode()) {
3589 case ISD::CTTZ_ZERO_UNDEF:
3591 case ISD::CTLZ_ZERO_UNDEF:
3593 // Zero extend the argument.
3594 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3595 // Perform the larger operation. For CTPOP and CTTZ_ZERO_UNDEF, this is
3596 // already the correct result.
3597 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
3598 if (Node->getOpcode() == ISD::CTTZ) {
3599 // FIXME: This should set a bit in the zero extended value instead.
3600 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
3601 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
3603 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
3604 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3605 } else if (Node->getOpcode() == ISD::CTLZ ||
3606 Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) {
3607 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3608 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
3609 DAG.getConstant(NVT.getSizeInBits() -
3610 OVT.getSizeInBits(), NVT));
3612 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
3615 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3616 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3617 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
3618 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
3619 DAG.getConstant(DiffBits, TLI.getShiftAmountTy(NVT)));
3620 Results.push_back(Tmp1);
3623 case ISD::FP_TO_UINT:
3624 case ISD::FP_TO_SINT:
3625 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
3626 Node->getOpcode() == ISD::FP_TO_SINT, dl);
3627 Results.push_back(Tmp1);
3629 case ISD::UINT_TO_FP:
3630 case ISD::SINT_TO_FP:
3631 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
3632 Node->getOpcode() == ISD::SINT_TO_FP, dl);
3633 Results.push_back(Tmp1);
3636 SDValue Chain = Node->getOperand(0); // Get the chain.
3637 SDValue Ptr = Node->getOperand(1); // Get the pointer.
3640 if (OVT.isVector()) {
3641 TruncOp = ISD::BITCAST;
3643 assert(OVT.isInteger()
3644 && "VAARG promotion is supported only for vectors or integer types");
3645 TruncOp = ISD::TRUNCATE;
3648 // Perform the larger operation, then convert back
3649 Tmp1 = DAG.getVAArg(NVT, dl, Chain, Ptr, Node->getOperand(2),
3650 Node->getConstantOperandVal(3));
3651 Chain = Tmp1.getValue(1);
3653 Tmp2 = DAG.getNode(TruncOp, dl, OVT, Tmp1);
3655 // Modified the chain result - switch anything that used the old chain to
3657 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp2);
3658 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
3665 unsigned ExtOp, TruncOp;
3666 if (OVT.isVector()) {
3667 ExtOp = ISD::BITCAST;
3668 TruncOp = ISD::BITCAST;
3670 assert(OVT.isInteger() && "Cannot promote logic operation");
3671 ExtOp = ISD::ANY_EXTEND;
3672 TruncOp = ISD::TRUNCATE;
3674 // Promote each of the values to the new type.
3675 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3676 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3677 // Perform the larger operation, then convert back
3678 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3679 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
3683 unsigned ExtOp, TruncOp;
3684 if (Node->getValueType(0).isVector()) {
3685 ExtOp = ISD::BITCAST;
3686 TruncOp = ISD::BITCAST;
3687 } else if (Node->getValueType(0).isInteger()) {
3688 ExtOp = ISD::ANY_EXTEND;
3689 TruncOp = ISD::TRUNCATE;
3691 ExtOp = ISD::FP_EXTEND;
3692 TruncOp = ISD::FP_ROUND;
3694 Tmp1 = Node->getOperand(0);
3695 // Promote each of the values to the new type.
3696 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3697 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
3698 // Perform the larger operation, then round down.
3699 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3);
3700 if (TruncOp != ISD::FP_ROUND)
3701 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
3703 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
3704 DAG.getIntPtrConstant(0));
3705 Results.push_back(Tmp1);
3708 case ISD::VECTOR_SHUFFLE: {
3709 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
3711 // Cast the two input vectors.
3712 Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
3713 Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
3715 // Convert the shuffle mask to the right # elements.
3716 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
3717 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
3718 Results.push_back(Tmp1);
3722 unsigned ExtOp = ISD::FP_EXTEND;
3723 if (NVT.isInteger()) {
3724 ISD::CondCode CCCode =
3725 cast<CondCodeSDNode>(Node->getOperand(2))->get();
3726 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3728 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3729 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3730 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3731 Tmp1, Tmp2, Node->getOperand(2)));
3737 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
3738 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
3739 Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3740 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
3741 Tmp3, DAG.getIntPtrConstant(0)));
3748 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
3749 Tmp2 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
3750 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
3751 Tmp2, DAG.getIntPtrConstant(0)));
3756 // Replace the original node with the legalized result.
3757 if (!Results.empty())
3758 ReplaceNode(Node, Results.data());
3761 // SelectionDAG::Legalize - This is the entry point for the file.
3763 void SelectionDAG::Legalize() {
3764 /// run - This is the main entry point to this class.
3766 SelectionDAGLegalize(*this).LegalizeDAG();