1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CallingConv.h"
15 #include "llvm/Constants.h"
16 #include "llvm/DebugInfo.h"
17 #include "llvm/DerivedTypes.h"
18 #include "llvm/LLVMContext.h"
19 #include "llvm/CodeGen/Analysis.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineJumpTableInfo.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/Target/TargetFrameLowering.h"
24 #include "llvm/Target/TargetLowering.h"
25 #include "llvm/DataLayout.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/MathExtras.h"
30 #include "llvm/Support/raw_ostream.h"
31 #include "llvm/ADT/DenseMap.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/SmallPtrSet.h"
36 //===----------------------------------------------------------------------===//
37 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
38 /// hacks on it until the target machine can handle it. This involves
39 /// eliminating value sizes the machine cannot handle (promoting small sizes to
40 /// large sizes or splitting up large values into small values) as well as
41 /// eliminating operations the machine cannot handle.
43 /// This code also does a small amount of optimization and recognition of idioms
44 /// as part of its processing. For example, if a target does not support a
45 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
46 /// will attempt merge setcc and brc instructions into brcc's.
49 class SelectionDAGLegalize : public SelectionDAG::DAGUpdateListener {
50 const TargetMachine &TM;
51 const TargetLowering &TLI;
54 /// LegalizePosition - The iterator for walking through the node list.
55 SelectionDAG::allnodes_iterator LegalizePosition;
57 /// LegalizedNodes - The set of nodes which have already been legalized.
58 SmallPtrSet<SDNode *, 16> LegalizedNodes;
60 // Libcall insertion helpers.
63 explicit SelectionDAGLegalize(SelectionDAG &DAG);
68 /// LegalizeOp - Legalizes the given operation.
69 void LegalizeOp(SDNode *Node);
71 SDValue OptimizeFloatStore(StoreSDNode *ST);
73 void LegalizeLoadOps(SDNode *Node);
74 void LegalizeStoreOps(SDNode *Node);
76 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
77 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
78 /// is necessary to spill the vector being inserted into to memory, perform
79 /// the insert there, and then read the result back.
80 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
81 SDValue Idx, DebugLoc dl);
82 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
83 SDValue Idx, DebugLoc dl);
85 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
86 /// performs the same shuffe in terms of order or result bytes, but on a type
87 /// whose vector element type is narrower than the original shuffle type.
88 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
89 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
90 SDValue N1, SDValue N2,
91 ArrayRef<int> Mask) const;
93 void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
96 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
97 SDValue ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops,
98 unsigned NumOps, bool isSigned, DebugLoc dl);
100 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
101 SDNode *Node, bool isSigned);
102 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
103 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
104 RTLIB::Libcall Call_PPCF128);
105 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
106 RTLIB::Libcall Call_I8,
107 RTLIB::Libcall Call_I16,
108 RTLIB::Libcall Call_I32,
109 RTLIB::Libcall Call_I64,
110 RTLIB::Libcall Call_I128);
111 void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
113 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl);
114 SDValue ExpandBUILD_VECTOR(SDNode *Node);
115 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
116 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
117 SmallVectorImpl<SDValue> &Results);
118 SDValue ExpandFCOPYSIGN(SDNode *Node);
119 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
121 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
123 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
126 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl);
127 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl);
129 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
130 SDValue ExpandInsertToVectorThroughStack(SDValue Op);
131 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
133 SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP);
135 std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node);
137 void ExpandNode(SDNode *Node);
138 void PromoteNode(SDNode *Node);
140 void ForgetNode(SDNode *N) {
141 LegalizedNodes.erase(N);
142 if (LegalizePosition == SelectionDAG::allnodes_iterator(N))
147 // DAGUpdateListener implementation.
148 virtual void NodeDeleted(SDNode *N, SDNode *E) {
151 virtual void NodeUpdated(SDNode *N) {}
153 // Node replacement helpers
154 void ReplacedNode(SDNode *N) {
155 if (N->use_empty()) {
156 DAG.RemoveDeadNode(N);
161 void ReplaceNode(SDNode *Old, SDNode *New) {
162 DAG.ReplaceAllUsesWith(Old, New);
165 void ReplaceNode(SDValue Old, SDValue New) {
166 DAG.ReplaceAllUsesWith(Old, New);
167 ReplacedNode(Old.getNode());
169 void ReplaceNode(SDNode *Old, const SDValue *New) {
170 DAG.ReplaceAllUsesWith(Old, New);
176 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
177 /// performs the same shuffe in terms of order or result bytes, but on a type
178 /// whose vector element type is narrower than the original shuffle type.
179 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
181 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
182 SDValue N1, SDValue N2,
183 ArrayRef<int> Mask) const {
184 unsigned NumMaskElts = VT.getVectorNumElements();
185 unsigned NumDestElts = NVT.getVectorNumElements();
186 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
188 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
190 if (NumEltsGrowth == 1)
191 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
193 SmallVector<int, 8> NewMask;
194 for (unsigned i = 0; i != NumMaskElts; ++i) {
196 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
198 NewMask.push_back(-1);
200 NewMask.push_back(Idx * NumEltsGrowth + j);
203 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
204 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
205 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
208 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
209 : SelectionDAG::DAGUpdateListener(dag),
210 TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()),
214 void SelectionDAGLegalize::LegalizeDAG() {
215 DAG.AssignTopologicalOrder();
217 // Visit all the nodes. We start in topological order, so that we see
218 // nodes with their original operands intact. Legalization can produce
219 // new nodes which may themselves need to be legalized. Iterate until all
220 // nodes have been legalized.
222 bool AnyLegalized = false;
223 for (LegalizePosition = DAG.allnodes_end();
224 LegalizePosition != DAG.allnodes_begin(); ) {
227 SDNode *N = LegalizePosition;
228 if (LegalizedNodes.insert(N)) {
238 // Remove dead nodes now.
239 DAG.RemoveDeadNodes();
242 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
243 /// a load from the constant pool.
245 SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) {
247 DebugLoc dl = CFP->getDebugLoc();
249 // If a FP immediate is precise when represented as a float and if the
250 // target can do an extending load from float to double, we put it into
251 // the constant pool as a float, even if it's is statically typed as a
252 // double. This shrinks FP constants and canonicalizes them for targets where
253 // an FP extending load is the same cost as a normal load (such as on the x87
254 // fp stack or PPC FP unit).
255 EVT VT = CFP->getValueType(0);
256 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
258 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
259 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
260 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
265 while (SVT != MVT::f32) {
266 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
267 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) &&
268 // Only do this if the target has a native EXTLOAD instruction from
270 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
271 TLI.ShouldShrinkFPConstant(OrigVT)) {
272 Type *SType = SVT.getTypeForEVT(*DAG.getContext());
273 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
279 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
280 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
283 DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT,
285 CPIdx, MachinePointerInfo::getConstantPool(),
286 VT, false, false, Alignment);
290 DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
291 MachinePointerInfo::getConstantPool(), false, false, false,
296 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
297 static void ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
298 const TargetLowering &TLI,
299 SelectionDAGLegalize *DAGLegalize) {
300 assert(ST->getAddressingMode() == ISD::UNINDEXED &&
301 "unaligned indexed stores not implemented!");
302 SDValue Chain = ST->getChain();
303 SDValue Ptr = ST->getBasePtr();
304 SDValue Val = ST->getValue();
305 EVT VT = Val.getValueType();
306 int Alignment = ST->getAlignment();
307 DebugLoc dl = ST->getDebugLoc();
308 if (ST->getMemoryVT().isFloatingPoint() ||
309 ST->getMemoryVT().isVector()) {
310 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
311 if (TLI.isTypeLegal(intVT)) {
312 // Expand to a bitconvert of the value to the integer type of the
313 // same size, then a (misaligned) int store.
314 // FIXME: Does not handle truncating floating point stores!
315 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
316 Result = DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
317 ST->isVolatile(), ST->isNonTemporal(), Alignment);
318 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
321 // Do a (aligned) store to a stack slot, then copy from the stack slot
322 // to the final destination using (unaligned) integer loads and stores.
323 EVT StoredVT = ST->getMemoryVT();
325 TLI.getRegisterType(*DAG.getContext(),
326 EVT::getIntegerVT(*DAG.getContext(),
327 StoredVT.getSizeInBits()));
328 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
329 unsigned RegBytes = RegVT.getSizeInBits() / 8;
330 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
332 // Make sure the stack slot is also aligned for the register type.
333 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
335 // Perform the original store, only redirected to the stack slot.
336 SDValue Store = DAG.getTruncStore(Chain, dl,
337 Val, StackPtr, MachinePointerInfo(),
338 StoredVT, false, false, 0);
339 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
340 SmallVector<SDValue, 8> Stores;
343 // Do all but one copies using the full register width.
344 for (unsigned i = 1; i < NumRegs; i++) {
345 // Load one integer register's worth from the stack slot.
346 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr,
347 MachinePointerInfo(),
348 false, false, false, 0);
349 // Store it to the final location. Remember the store.
350 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
351 ST->getPointerInfo().getWithOffset(Offset),
352 ST->isVolatile(), ST->isNonTemporal(),
353 MinAlign(ST->getAlignment(), Offset)));
354 // Increment the pointers.
356 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
358 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
361 // The last store may be partial. Do a truncating store. On big-endian
362 // machines this requires an extending load from the stack slot to ensure
363 // that the bits are in the right place.
364 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
365 8 * (StoredBytes - Offset));
367 // Load from the stack slot.
368 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
369 MachinePointerInfo(),
370 MemVT, false, false, 0);
372 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
374 .getWithOffset(Offset),
375 MemVT, ST->isVolatile(),
377 MinAlign(ST->getAlignment(), Offset)));
378 // The order of the stores doesn't matter - say it with a TokenFactor.
380 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
382 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
385 assert(ST->getMemoryVT().isInteger() &&
386 !ST->getMemoryVT().isVector() &&
387 "Unaligned store of unknown type.");
388 // Get the half-size VT
389 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext());
390 int NumBits = NewStoredVT.getSizeInBits();
391 int IncrementSize = NumBits / 8;
393 // Divide the stored value in two parts.
394 SDValue ShiftAmount = DAG.getConstant(NumBits,
395 TLI.getShiftAmountTy(Val.getValueType()));
397 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
399 // Store the two parts
400 SDValue Store1, Store2;
401 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
402 ST->getPointerInfo(), NewStoredVT,
403 ST->isVolatile(), ST->isNonTemporal(), Alignment);
404 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
405 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
406 Alignment = MinAlign(Alignment, IncrementSize);
407 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
408 ST->getPointerInfo().getWithOffset(IncrementSize),
409 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(),
413 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
414 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
417 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
419 ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
420 const TargetLowering &TLI,
421 SDValue &ValResult, SDValue &ChainResult) {
422 assert(LD->getAddressingMode() == ISD::UNINDEXED &&
423 "unaligned indexed loads not implemented!");
424 SDValue Chain = LD->getChain();
425 SDValue Ptr = LD->getBasePtr();
426 EVT VT = LD->getValueType(0);
427 EVT LoadedVT = LD->getMemoryVT();
428 DebugLoc dl = LD->getDebugLoc();
429 if (VT.isFloatingPoint() || VT.isVector()) {
430 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
431 if (TLI.isTypeLegal(intVT) && TLI.isTypeLegal(LoadedVT)) {
432 // Expand to a (misaligned) integer load of the same size,
433 // then bitconvert to floating point or vector.
434 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getPointerInfo(),
437 LD->isInvariant(), LD->getAlignment());
438 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad);
440 Result = DAG.getNode(VT.isFloatingPoint() ? ISD::FP_EXTEND :
441 ISD::ANY_EXTEND, dl, VT, Result);
448 // Copy the value to a (aligned) stack slot using (unaligned) integer
449 // loads and stores, then do a (aligned) load from the stack slot.
450 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
451 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
452 unsigned RegBytes = RegVT.getSizeInBits() / 8;
453 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
455 // Make sure the stack slot is also aligned for the register type.
456 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
458 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
459 SmallVector<SDValue, 8> Stores;
460 SDValue StackPtr = StackBase;
463 // Do all but one copies using the full register width.
464 for (unsigned i = 1; i < NumRegs; i++) {
465 // Load one integer register's worth from the original location.
466 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr,
467 LD->getPointerInfo().getWithOffset(Offset),
468 LD->isVolatile(), LD->isNonTemporal(),
470 MinAlign(LD->getAlignment(), Offset));
471 // Follow the load with a store to the stack slot. Remember the store.
472 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
473 MachinePointerInfo(), false, false, 0));
474 // Increment the pointers.
476 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
477 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
481 // The last copy may be partial. Do an extending load.
482 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
483 8 * (LoadedBytes - Offset));
484 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
485 LD->getPointerInfo().getWithOffset(Offset),
486 MemVT, LD->isVolatile(),
488 MinAlign(LD->getAlignment(), Offset));
489 // Follow the load with a store to the stack slot. Remember the store.
490 // On big-endian machines this requires a truncating store to ensure
491 // that the bits end up in the right place.
492 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
493 MachinePointerInfo(), MemVT,
496 // The order of the stores doesn't matter - say it with a TokenFactor.
497 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
500 // Finally, perform the original load only redirected to the stack slot.
501 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
502 MachinePointerInfo(), LoadedVT, false, false, 0);
504 // Callers expect a MERGE_VALUES node.
509 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
510 "Unaligned load of unsupported type.");
512 // Compute the new VT that is half the size of the old one. This is an
514 unsigned NumBits = LoadedVT.getSizeInBits();
516 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
519 unsigned Alignment = LD->getAlignment();
520 unsigned IncrementSize = NumBits / 8;
521 ISD::LoadExtType HiExtType = LD->getExtensionType();
523 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
524 if (HiExtType == ISD::NON_EXTLOAD)
525 HiExtType = ISD::ZEXTLOAD;
527 // Load the value in two parts
529 if (TLI.isLittleEndian()) {
530 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
531 NewLoadedVT, LD->isVolatile(),
532 LD->isNonTemporal(), Alignment);
533 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
534 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
535 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr,
536 LD->getPointerInfo().getWithOffset(IncrementSize),
537 NewLoadedVT, LD->isVolatile(),
538 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
540 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(),
541 NewLoadedVT, LD->isVolatile(),
542 LD->isNonTemporal(), Alignment);
543 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
544 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
545 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
546 LD->getPointerInfo().getWithOffset(IncrementSize),
547 NewLoadedVT, LD->isVolatile(),
548 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
551 // aggregate the two parts
552 SDValue ShiftAmount = DAG.getConstant(NumBits,
553 TLI.getShiftAmountTy(Hi.getValueType()));
554 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
555 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
557 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
564 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
565 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
566 /// is necessary to spill the vector being inserted into to memory, perform
567 /// the insert there, and then read the result back.
568 SDValue SelectionDAGLegalize::
569 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
575 // If the target doesn't support this, we have to spill the input vector
576 // to a temporary stack slot, update the element, then reload it. This is
577 // badness. We could also load the value into a vector register (either
578 // with a "move to register" or "extload into register" instruction, then
579 // permute it into place, if the idx is a constant and if the idx is
580 // supported by the target.
581 EVT VT = Tmp1.getValueType();
582 EVT EltVT = VT.getVectorElementType();
583 EVT IdxVT = Tmp3.getValueType();
584 EVT PtrVT = TLI.getPointerTy();
585 SDValue StackPtr = DAG.CreateStackTemporary(VT);
587 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
590 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
591 MachinePointerInfo::getFixedStack(SPFI),
594 // Truncate or zero extend offset to target pointer type.
595 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
596 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
597 // Add the offset to the index.
598 unsigned EltSize = EltVT.getSizeInBits()/8;
599 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
600 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
601 // Store the scalar value.
602 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT,
604 // Load the updated vector.
605 return DAG.getLoad(VT, dl, Ch, StackPtr,
606 MachinePointerInfo::getFixedStack(SPFI), false, false,
611 SDValue SelectionDAGLegalize::
612 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) {
613 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
614 // SCALAR_TO_VECTOR requires that the type of the value being inserted
615 // match the element type of the vector being created, except for
616 // integers in which case the inserted value can be over width.
617 EVT EltVT = Vec.getValueType().getVectorElementType();
618 if (Val.getValueType() == EltVT ||
619 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
620 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
621 Vec.getValueType(), Val);
623 unsigned NumElts = Vec.getValueType().getVectorNumElements();
624 // We generate a shuffle of InVec and ScVec, so the shuffle mask
625 // should be 0,1,2,3,4,5... with the appropriate element replaced with
627 SmallVector<int, 8> ShufOps;
628 for (unsigned i = 0; i != NumElts; ++i)
629 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
631 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
635 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
638 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
639 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
640 // FIXME: We shouldn't do this for TargetConstantFP's.
641 // FIXME: move this to the DAG Combiner! Note that we can't regress due
642 // to phase ordering between legalized code and the dag combiner. This
643 // probably means that we need to integrate dag combiner and legalizer
645 // We generally can't do this one for long doubles.
646 SDValue Chain = ST->getChain();
647 SDValue Ptr = ST->getBasePtr();
648 unsigned Alignment = ST->getAlignment();
649 bool isVolatile = ST->isVolatile();
650 bool isNonTemporal = ST->isNonTemporal();
651 DebugLoc dl = ST->getDebugLoc();
652 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
653 if (CFP->getValueType(0) == MVT::f32 &&
654 TLI.isTypeLegal(MVT::i32)) {
655 SDValue Con = DAG.getConstant(CFP->getValueAPF().
656 bitcastToAPInt().zextOrTrunc(32),
658 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
659 isVolatile, isNonTemporal, Alignment);
662 if (CFP->getValueType(0) == MVT::f64) {
663 // If this target supports 64-bit registers, do a single 64-bit store.
664 if (TLI.isTypeLegal(MVT::i64)) {
665 SDValue Con = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
666 zextOrTrunc(64), MVT::i64);
667 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
668 isVolatile, isNonTemporal, Alignment);
671 if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) {
672 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
673 // stores. If the target supports neither 32- nor 64-bits, this
674 // xform is certainly not worth it.
675 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
676 SDValue Lo = DAG.getConstant(IntVal.trunc(32), MVT::i32);
677 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
678 if (TLI.isBigEndian()) std::swap(Lo, Hi);
680 Lo = DAG.getStore(Chain, dl, Lo, Ptr, ST->getPointerInfo(), isVolatile,
681 isNonTemporal, Alignment);
682 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
683 DAG.getIntPtrConstant(4));
684 Hi = DAG.getStore(Chain, dl, Hi, Ptr,
685 ST->getPointerInfo().getWithOffset(4),
686 isVolatile, isNonTemporal, MinAlign(Alignment, 4U));
688 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
692 return SDValue(0, 0);
695 void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
696 StoreSDNode *ST = cast<StoreSDNode>(Node);
697 SDValue Chain = ST->getChain();
698 SDValue Ptr = ST->getBasePtr();
699 DebugLoc dl = Node->getDebugLoc();
701 unsigned Alignment = ST->getAlignment();
702 bool isVolatile = ST->isVolatile();
703 bool isNonTemporal = ST->isNonTemporal();
705 if (!ST->isTruncatingStore()) {
706 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
707 ReplaceNode(ST, OptStore);
712 SDValue Value = ST->getValue();
713 EVT VT = Value.getValueType();
714 switch (TLI.getOperationAction(ISD::STORE, VT)) {
715 default: llvm_unreachable("This action is not supported yet!");
716 case TargetLowering::Legal:
717 // If this is an unaligned store and the target doesn't support it,
719 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
720 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
721 unsigned ABIAlignment= TLI.getDataLayout()->getABITypeAlignment(Ty);
722 if (ST->getAlignment() < ABIAlignment)
723 ExpandUnalignedStore(cast<StoreSDNode>(Node),
727 case TargetLowering::Custom: {
728 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
730 ReplaceNode(SDValue(Node, 0), Res);
733 case TargetLowering::Promote: {
734 assert(VT.isVector() && "Unknown legal promote case!");
735 Value = DAG.getNode(ISD::BITCAST, dl,
736 TLI.getTypeToPromoteTo(ISD::STORE, VT), Value);
738 DAG.getStore(Chain, dl, Value, Ptr,
739 ST->getPointerInfo(), isVolatile,
740 isNonTemporal, Alignment);
741 ReplaceNode(SDValue(Node, 0), Result);
748 SDValue Value = ST->getValue();
750 EVT StVT = ST->getMemoryVT();
751 unsigned StWidth = StVT.getSizeInBits();
753 if (StWidth != StVT.getStoreSizeInBits()) {
754 // Promote to a byte-sized store with upper bits zero if not
755 // storing an integral number of bytes. For example, promote
756 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
757 EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
758 StVT.getStoreSizeInBits());
759 Value = DAG.getZeroExtendInReg(Value, dl, StVT);
761 DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
762 NVT, isVolatile, isNonTemporal, Alignment);
763 ReplaceNode(SDValue(Node, 0), Result);
764 } else if (StWidth & (StWidth - 1)) {
765 // If not storing a power-of-2 number of bits, expand as two stores.
766 assert(!StVT.isVector() && "Unsupported truncstore!");
767 unsigned RoundWidth = 1 << Log2_32(StWidth);
768 assert(RoundWidth < StWidth);
769 unsigned ExtraWidth = StWidth - RoundWidth;
770 assert(ExtraWidth < RoundWidth);
771 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
772 "Store size not an integral number of bytes!");
773 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
774 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
776 unsigned IncrementSize;
778 if (TLI.isLittleEndian()) {
779 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
780 // Store the bottom RoundWidth bits.
781 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
783 isVolatile, isNonTemporal, Alignment);
785 // Store the remaining ExtraWidth bits.
786 IncrementSize = RoundWidth / 8;
787 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
788 DAG.getIntPtrConstant(IncrementSize));
789 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
790 DAG.getConstant(RoundWidth,
791 TLI.getShiftAmountTy(Value.getValueType())));
792 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr,
793 ST->getPointerInfo().getWithOffset(IncrementSize),
794 ExtraVT, isVolatile, isNonTemporal,
795 MinAlign(Alignment, IncrementSize));
797 // Big endian - avoid unaligned stores.
798 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
799 // Store the top RoundWidth bits.
800 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
801 DAG.getConstant(ExtraWidth,
802 TLI.getShiftAmountTy(Value.getValueType())));
803 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, ST->getPointerInfo(),
804 RoundVT, isVolatile, isNonTemporal, Alignment);
806 // Store the remaining ExtraWidth bits.
807 IncrementSize = RoundWidth / 8;
808 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
809 DAG.getIntPtrConstant(IncrementSize));
810 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr,
811 ST->getPointerInfo().getWithOffset(IncrementSize),
812 ExtraVT, isVolatile, isNonTemporal,
813 MinAlign(Alignment, IncrementSize));
816 // The order of the stores doesn't matter.
817 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
818 ReplaceNode(SDValue(Node, 0), Result);
820 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
821 default: llvm_unreachable("This action is not supported yet!");
822 case TargetLowering::Legal:
823 // If this is an unaligned store and the target doesn't support it,
825 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
826 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
827 unsigned ABIAlignment= TLI.getDataLayout()->getABITypeAlignment(Ty);
828 if (ST->getAlignment() < ABIAlignment)
829 ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this);
832 case TargetLowering::Custom: {
833 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
835 ReplaceNode(SDValue(Node, 0), Res);
838 case TargetLowering::Expand:
839 assert(!StVT.isVector() &&
840 "Vector Stores are handled in LegalizeVectorOps");
842 // TRUNCSTORE:i16 i32 -> STORE i16
843 assert(TLI.isTypeLegal(StVT) &&
844 "Do not know how to expand this store!");
845 Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value);
847 DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
848 isVolatile, isNonTemporal, Alignment);
849 ReplaceNode(SDValue(Node, 0), Result);
856 void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
857 LoadSDNode *LD = cast<LoadSDNode>(Node);
858 SDValue Chain = LD->getChain(); // The chain.
859 SDValue Ptr = LD->getBasePtr(); // The base pointer.
860 SDValue Value; // The value returned by the load op.
861 DebugLoc dl = Node->getDebugLoc();
863 ISD::LoadExtType ExtType = LD->getExtensionType();
864 if (ExtType == ISD::NON_EXTLOAD) {
865 EVT VT = Node->getValueType(0);
866 SDValue RVal = SDValue(Node, 0);
867 SDValue RChain = SDValue(Node, 1);
869 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
870 default: llvm_unreachable("This action is not supported yet!");
871 case TargetLowering::Legal:
872 // If this is an unaligned load and the target doesn't support it,
874 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
875 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
876 unsigned ABIAlignment =
877 TLI.getDataLayout()->getABITypeAlignment(Ty);
878 if (LD->getAlignment() < ABIAlignment){
879 ExpandUnalignedLoad(cast<LoadSDNode>(Node), DAG, TLI, RVal, RChain);
883 case TargetLowering::Custom: {
884 SDValue Res = TLI.LowerOperation(RVal, DAG);
887 RChain = Res.getValue(1);
891 case TargetLowering::Promote: {
892 // Only promote a load of vector type to another.
893 assert(VT.isVector() && "Cannot promote this load!");
894 // Change base type to a different vector type.
895 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
897 SDValue Res = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getPointerInfo(),
898 LD->isVolatile(), LD->isNonTemporal(),
899 LD->isInvariant(), LD->getAlignment());
900 RVal = DAG.getNode(ISD::BITCAST, dl, VT, Res);
901 RChain = Res.getValue(1);
905 if (RChain.getNode() != Node) {
906 assert(RVal.getNode() != Node && "Load must be completely replaced");
907 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), RVal);
908 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), RChain);
914 EVT SrcVT = LD->getMemoryVT();
915 unsigned SrcWidth = SrcVT.getSizeInBits();
916 unsigned Alignment = LD->getAlignment();
917 bool isVolatile = LD->isVolatile();
918 bool isNonTemporal = LD->isNonTemporal();
920 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
921 // Some targets pretend to have an i1 loading operation, and actually
922 // load an i8. This trick is correct for ZEXTLOAD because the top 7
923 // bits are guaranteed to be zero; it helps the optimizers understand
924 // that these bits are zero. It is also useful for EXTLOAD, since it
925 // tells the optimizers that those bits are undefined. It would be
926 // nice to have an effective generic way of getting these benefits...
927 // Until such a way is found, don't insist on promoting i1 here.
929 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
930 // Promote to a byte-sized load if not loading an integral number of
931 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
932 unsigned NewWidth = SrcVT.getStoreSizeInBits();
933 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
936 // The extra bits are guaranteed to be zero, since we stored them that
937 // way. A zext load from NVT thus automatically gives zext from SrcVT.
939 ISD::LoadExtType NewExtType =
940 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
943 DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
944 Chain, Ptr, LD->getPointerInfo(),
945 NVT, isVolatile, isNonTemporal, Alignment);
947 Ch = Result.getValue(1); // The chain.
949 if (ExtType == ISD::SEXTLOAD)
950 // Having the top bits zero doesn't help when sign extending.
951 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
952 Result.getValueType(),
953 Result, DAG.getValueType(SrcVT));
954 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
955 // All the top bits are guaranteed to be zero - inform the optimizers.
956 Result = DAG.getNode(ISD::AssertZext, dl,
957 Result.getValueType(), Result,
958 DAG.getValueType(SrcVT));
962 } else if (SrcWidth & (SrcWidth - 1)) {
963 // If not loading a power-of-2 number of bits, expand as two loads.
964 assert(!SrcVT.isVector() && "Unsupported extload!");
965 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
966 assert(RoundWidth < SrcWidth);
967 unsigned ExtraWidth = SrcWidth - RoundWidth;
968 assert(ExtraWidth < RoundWidth);
969 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
970 "Load size not an integral number of bytes!");
971 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
972 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
974 unsigned IncrementSize;
976 if (TLI.isLittleEndian()) {
977 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
978 // Load the bottom RoundWidth bits.
979 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0),
981 LD->getPointerInfo(), RoundVT, isVolatile,
982 isNonTemporal, Alignment);
984 // Load the remaining ExtraWidth bits.
985 IncrementSize = RoundWidth / 8;
986 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
987 DAG.getIntPtrConstant(IncrementSize));
988 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
989 LD->getPointerInfo().getWithOffset(IncrementSize),
990 ExtraVT, isVolatile, isNonTemporal,
991 MinAlign(Alignment, IncrementSize));
993 // Build a factor node to remember that this load is independent of
995 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
998 // Move the top bits to the right place.
999 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1000 DAG.getConstant(RoundWidth,
1001 TLI.getShiftAmountTy(Hi.getValueType())));
1003 // Join the hi and lo parts.
1004 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1006 // Big endian - avoid unaligned loads.
1007 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1008 // Load the top RoundWidth bits.
1009 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
1010 LD->getPointerInfo(), RoundVT, isVolatile,
1011 isNonTemporal, Alignment);
1013 // Load the remaining ExtraWidth bits.
1014 IncrementSize = RoundWidth / 8;
1015 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1016 DAG.getIntPtrConstant(IncrementSize));
1017 Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
1018 dl, Node->getValueType(0), Chain, Ptr,
1019 LD->getPointerInfo().getWithOffset(IncrementSize),
1020 ExtraVT, isVolatile, isNonTemporal,
1021 MinAlign(Alignment, IncrementSize));
1023 // Build a factor node to remember that this load is independent of
1025 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1028 // Move the top bits to the right place.
1029 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1030 DAG.getConstant(ExtraWidth,
1031 TLI.getShiftAmountTy(Hi.getValueType())));
1033 // Join the hi and lo parts.
1034 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1039 bool isCustom = false;
1040 switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
1041 default: llvm_unreachable("This action is not supported yet!");
1042 case TargetLowering::Custom:
1045 case TargetLowering::Legal: {
1046 Value = SDValue(Node, 0);
1047 Chain = SDValue(Node, 1);
1050 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1051 if (Res.getNode()) {
1053 Chain = Res.getValue(1);
1056 // If this is an unaligned load and the target doesn't support it,
1058 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
1060 LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1061 unsigned ABIAlignment =
1062 TLI.getDataLayout()->getABITypeAlignment(Ty);
1063 if (LD->getAlignment() < ABIAlignment){
1064 ExpandUnalignedLoad(cast<LoadSDNode>(Node),
1065 DAG, TLI, Value, Chain);
1071 case TargetLowering::Expand:
1072 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) && TLI.isTypeLegal(SrcVT)) {
1073 SDValue Load = DAG.getLoad(SrcVT, dl, Chain, Ptr,
1074 LD->getPointerInfo(),
1075 LD->isVolatile(), LD->isNonTemporal(),
1076 LD->isInvariant(), LD->getAlignment());
1080 ExtendOp = (SrcVT.isFloatingPoint() ?
1081 ISD::FP_EXTEND : ISD::ANY_EXTEND);
1083 case ISD::SEXTLOAD: ExtendOp = ISD::SIGN_EXTEND; break;
1084 case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break;
1085 default: llvm_unreachable("Unexpected extend load type!");
1087 Value = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
1088 Chain = Load.getValue(1);
1092 assert(!SrcVT.isVector() &&
1093 "Vector Loads are handled in LegalizeVectorOps");
1095 // FIXME: This does not work for vectors on most targets. Sign- and
1096 // zero-extend operations are currently folded into extending loads,
1097 // whether they are legal or not, and then we end up here without any
1098 // support for legalizing them.
1099 assert(ExtType != ISD::EXTLOAD &&
1100 "EXTLOAD should always be supported!");
1101 // Turn the unsupported load into an EXTLOAD followed by an explicit
1102 // zero/sign extend inreg.
1103 SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
1104 Chain, Ptr, LD->getPointerInfo(), SrcVT,
1105 LD->isVolatile(), LD->isNonTemporal(),
1106 LD->getAlignment());
1108 if (ExtType == ISD::SEXTLOAD)
1109 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1110 Result.getValueType(),
1111 Result, DAG.getValueType(SrcVT));
1113 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType());
1115 Chain = Result.getValue(1);
1120 // Since loads produce two values, make sure to remember that we legalized
1122 if (Chain.getNode() != Node) {
1123 assert(Value.getNode() != Node && "Load must be completely replaced");
1124 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Value);
1125 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
1130 /// LegalizeOp - Return a legal replacement for the given operation, with
1131 /// all legal operands.
1132 void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
1133 if (Node->getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
1136 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1137 assert(TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) ==
1138 TargetLowering::TypeLegal &&
1139 "Unexpected illegal type!");
1141 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1142 assert((TLI.getTypeAction(*DAG.getContext(),
1143 Node->getOperand(i).getValueType()) ==
1144 TargetLowering::TypeLegal ||
1145 Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
1146 "Unexpected illegal type!");
1148 // Figure out the correct action; the way to query this varies by opcode
1149 TargetLowering::LegalizeAction Action = TargetLowering::Legal;
1150 bool SimpleFinishLegalizing = true;
1151 switch (Node->getOpcode()) {
1152 case ISD::INTRINSIC_W_CHAIN:
1153 case ISD::INTRINSIC_WO_CHAIN:
1154 case ISD::INTRINSIC_VOID:
1155 case ISD::STACKSAVE:
1156 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1159 Action = TLI.getOperationAction(Node->getOpcode(),
1160 Node->getValueType(0));
1161 if (Action != TargetLowering::Promote)
1162 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1164 case ISD::SINT_TO_FP:
1165 case ISD::UINT_TO_FP:
1166 case ISD::EXTRACT_VECTOR_ELT:
1167 Action = TLI.getOperationAction(Node->getOpcode(),
1168 Node->getOperand(0).getValueType());
1170 case ISD::FP_ROUND_INREG:
1171 case ISD::SIGN_EXTEND_INREG: {
1172 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
1173 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
1176 case ISD::ATOMIC_STORE: {
1177 Action = TLI.getOperationAction(Node->getOpcode(),
1178 Node->getOperand(2).getValueType());
1181 case ISD::SELECT_CC:
1184 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
1185 Node->getOpcode() == ISD::SETCC ? 2 : 1;
1186 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
1187 EVT OpVT = Node->getOperand(CompareOperand).getValueType();
1188 ISD::CondCode CCCode =
1189 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
1190 Action = TLI.getCondCodeAction(CCCode, OpVT);
1191 if (Action == TargetLowering::Legal) {
1192 if (Node->getOpcode() == ISD::SELECT_CC)
1193 Action = TLI.getOperationAction(Node->getOpcode(),
1194 Node->getValueType(0));
1196 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
1202 // FIXME: Model these properly. LOAD and STORE are complicated, and
1203 // STORE expects the unlegalized operand in some cases.
1204 SimpleFinishLegalizing = false;
1206 case ISD::CALLSEQ_START:
1207 case ISD::CALLSEQ_END:
1208 // FIXME: This shouldn't be necessary. These nodes have special properties
1209 // dealing with the recursive nature of legalization. Removing this
1210 // special case should be done as part of making LegalizeDAG non-recursive.
1211 SimpleFinishLegalizing = false;
1213 case ISD::EXTRACT_ELEMENT:
1214 case ISD::FLT_ROUNDS_:
1222 case ISD::MERGE_VALUES:
1223 case ISD::EH_RETURN:
1224 case ISD::FRAME_TO_ARGS_OFFSET:
1225 case ISD::EH_SJLJ_SETJMP:
1226 case ISD::EH_SJLJ_LONGJMP:
1227 // These operations lie about being legal: when they claim to be legal,
1228 // they should actually be expanded.
1229 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1230 if (Action == TargetLowering::Legal)
1231 Action = TargetLowering::Expand;
1233 case ISD::INIT_TRAMPOLINE:
1234 case ISD::ADJUST_TRAMPOLINE:
1235 case ISD::FRAMEADDR:
1236 case ISD::RETURNADDR:
1237 // These operations lie about being legal: when they claim to be legal,
1238 // they should actually be custom-lowered.
1239 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1240 if (Action == TargetLowering::Legal)
1241 Action = TargetLowering::Custom;
1244 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1245 Action = TargetLowering::Legal;
1247 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1252 if (SimpleFinishLegalizing) {
1253 SDNode *NewNode = Node;
1254 switch (Node->getOpcode()) {
1261 // Legalizing shifts/rotates requires adjusting the shift amount
1262 // to the appropriate width.
1263 if (!Node->getOperand(1).getValueType().isVector()) {
1265 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1266 Node->getOperand(1));
1267 HandleSDNode Handle(SAO);
1268 LegalizeOp(SAO.getNode());
1269 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1273 case ISD::SRL_PARTS:
1274 case ISD::SRA_PARTS:
1275 case ISD::SHL_PARTS:
1276 // Legalizing shifts/rotates requires adjusting the shift amount
1277 // to the appropriate width.
1278 if (!Node->getOperand(2).getValueType().isVector()) {
1280 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1281 Node->getOperand(2));
1282 HandleSDNode Handle(SAO);
1283 LegalizeOp(SAO.getNode());
1284 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1285 Node->getOperand(1),
1291 if (NewNode != Node) {
1292 DAG.ReplaceAllUsesWith(Node, NewNode);
1293 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1294 DAG.TransferDbgValues(SDValue(Node, i), SDValue(NewNode, i));
1299 case TargetLowering::Legal:
1301 case TargetLowering::Custom: {
1302 // FIXME: The handling for custom lowering with multiple results is
1304 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1305 if (Res.getNode()) {
1306 SmallVector<SDValue, 8> ResultVals;
1307 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
1309 ResultVals.push_back(Res);
1311 ResultVals.push_back(Res.getValue(i));
1313 if (Res.getNode() != Node || Res.getResNo() != 0) {
1314 DAG.ReplaceAllUsesWith(Node, ResultVals.data());
1315 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1316 DAG.TransferDbgValues(SDValue(Node, i), ResultVals[i]);
1323 case TargetLowering::Expand:
1326 case TargetLowering::Promote:
1332 switch (Node->getOpcode()) {
1339 llvm_unreachable("Do not know how to legalize this operator!");
1341 case ISD::CALLSEQ_START:
1342 case ISD::CALLSEQ_END:
1345 return LegalizeLoadOps(Node);
1348 return LegalizeStoreOps(Node);
1353 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1354 SDValue Vec = Op.getOperand(0);
1355 SDValue Idx = Op.getOperand(1);
1356 DebugLoc dl = Op.getDebugLoc();
1357 // Store the value to a temporary stack slot, then LOAD the returned part.
1358 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1359 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1360 MachinePointerInfo(), false, false, 0);
1362 // Add the offset to the index.
1364 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1365 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1366 DAG.getConstant(EltSize, Idx.getValueType()));
1368 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1369 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1371 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1373 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1375 if (Op.getValueType().isVector())
1376 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,MachinePointerInfo(),
1377 false, false, false, 0);
1378 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
1379 MachinePointerInfo(),
1380 Vec.getValueType().getVectorElementType(),
1384 SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
1385 assert(Op.getValueType().isVector() && "Non-vector insert subvector!");
1387 SDValue Vec = Op.getOperand(0);
1388 SDValue Part = Op.getOperand(1);
1389 SDValue Idx = Op.getOperand(2);
1390 DebugLoc dl = Op.getDebugLoc();
1392 // Store the value to a temporary stack slot, then LOAD the returned part.
1394 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1395 int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1396 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1398 // First store the whole vector.
1399 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo,
1402 // Then store the inserted part.
1404 // Add the offset to the index.
1406 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1408 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1409 DAG.getConstant(EltSize, Idx.getValueType()));
1411 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1412 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1414 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1416 SDValue SubStackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
1419 // Store the subvector.
1420 Ch = DAG.getStore(DAG.getEntryNode(), dl, Part, SubStackPtr,
1421 MachinePointerInfo(), false, false, 0);
1423 // Finally, load the updated vector.
1424 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo,
1425 false, false, false, 0);
1428 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1429 // We can't handle this case efficiently. Allocate a sufficiently
1430 // aligned object on the stack, store each element into it, then load
1431 // the result as a vector.
1432 // Create the stack frame object.
1433 EVT VT = Node->getValueType(0);
1434 EVT EltVT = VT.getVectorElementType();
1435 DebugLoc dl = Node->getDebugLoc();
1436 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1437 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1438 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1440 // Emit a store of each element to the stack slot.
1441 SmallVector<SDValue, 8> Stores;
1442 unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1443 // Store (in the right endianness) the elements to memory.
1444 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1445 // Ignore undef elements.
1446 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1448 unsigned Offset = TypeByteSize*i;
1450 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
1451 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1453 // If the destination vector element type is narrower than the source
1454 // element type, only store the bits necessary.
1455 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1456 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1457 Node->getOperand(i), Idx,
1458 PtrInfo.getWithOffset(Offset),
1459 EltVT, false, false, 0));
1461 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
1462 Node->getOperand(i), Idx,
1463 PtrInfo.getWithOffset(Offset),
1468 if (!Stores.empty()) // Not all undef elements?
1469 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1470 &Stores[0], Stores.size());
1472 StoreChain = DAG.getEntryNode();
1474 // Result is a load from the stack slot.
1475 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo,
1476 false, false, false, 0);
1479 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
1480 DebugLoc dl = Node->getDebugLoc();
1481 SDValue Tmp1 = Node->getOperand(0);
1482 SDValue Tmp2 = Node->getOperand(1);
1484 // Get the sign bit of the RHS. First obtain a value that has the same
1485 // sign as the sign bit, i.e. negative if and only if the sign bit is 1.
1487 EVT FloatVT = Tmp2.getValueType();
1488 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits());
1489 if (TLI.isTypeLegal(IVT)) {
1490 // Convert to an integer with the same sign bit.
1491 SignBit = DAG.getNode(ISD::BITCAST, dl, IVT, Tmp2);
1493 // Store the float to memory, then load the sign part out as an integer.
1494 MVT LoadTy = TLI.getPointerTy();
1495 // First create a temporary that is aligned for both the load and store.
1496 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1497 // Then store the float to it.
1499 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, MachinePointerInfo(),
1501 if (TLI.isBigEndian()) {
1502 assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1503 // Load out a legal integer with the same sign bit as the float.
1504 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, MachinePointerInfo(),
1505 false, false, false, 0);
1506 } else { // Little endian
1507 SDValue LoadPtr = StackPtr;
1508 // The float may be wider than the integer we are going to load. Advance
1509 // the pointer so that the loaded integer will contain the sign bit.
1510 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits();
1511 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8;
1512 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(),
1513 LoadPtr, DAG.getIntPtrConstant(ByteOffset));
1514 // Load a legal integer containing the sign bit.
1515 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(),
1516 false, false, false, 0);
1517 // Move the sign bit to the top bit of the loaded integer.
1518 unsigned BitShift = LoadTy.getSizeInBits() -
1519 (FloatVT.getSizeInBits() - 8 * ByteOffset);
1520 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?");
1522 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit,
1523 DAG.getConstant(BitShift,
1524 TLI.getShiftAmountTy(SignBit.getValueType())));
1527 // Now get the sign bit proper, by seeing whether the value is negative.
1528 SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()),
1529 SignBit, DAG.getConstant(0, SignBit.getValueType()),
1531 // Get the absolute value of the result.
1532 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1533 // Select between the nabs and abs value based on the sign bit of
1535 return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit,
1536 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1540 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1541 SmallVectorImpl<SDValue> &Results) {
1542 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1543 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1544 " not tell us which reg is the stack pointer!");
1545 DebugLoc dl = Node->getDebugLoc();
1546 EVT VT = Node->getValueType(0);
1547 SDValue Tmp1 = SDValue(Node, 0);
1548 SDValue Tmp2 = SDValue(Node, 1);
1549 SDValue Tmp3 = Node->getOperand(2);
1550 SDValue Chain = Tmp1.getOperand(0);
1552 // Chain the dynamic stack allocation so that it doesn't modify the stack
1553 // pointer when other instructions are using the stack.
1554 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1556 SDValue Size = Tmp2.getOperand(1);
1557 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1558 Chain = SP.getValue(1);
1559 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1560 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
1561 if (Align > StackAlign)
1562 SP = DAG.getNode(ISD::AND, dl, VT, SP,
1563 DAG.getConstant(-(uint64_t)Align, VT));
1564 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1565 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1567 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1568 DAG.getIntPtrConstant(0, true), SDValue());
1570 Results.push_back(Tmp1);
1571 Results.push_back(Tmp2);
1574 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
1575 /// condition code CC on the current target. This routine expands SETCC with
1576 /// illegal condition code into AND / OR of multiple SETCC values.
1577 void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1578 SDValue &LHS, SDValue &RHS,
1581 EVT OpVT = LHS.getValueType();
1582 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1583 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1584 default: llvm_unreachable("Unknown condition code action!");
1585 case TargetLowering::Legal:
1588 case TargetLowering::Expand: {
1589 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1590 ISD::CondCode InvCC = ISD::SETCC_INVALID;
1593 default: llvm_unreachable("Don't know how to expand this condition!");
1595 assert(TLI.getCondCodeAction(ISD::SETOEQ, OpVT)
1596 == TargetLowering::Legal
1597 && "If SETO is expanded, SETOEQ must be legal!");
1598 CC1 = ISD::SETOEQ; CC2 = ISD::SETOEQ; Opc = ISD::AND; break;
1600 assert(TLI.getCondCodeAction(ISD::SETUNE, OpVT)
1601 == TargetLowering::Legal
1602 && "If SETUO is expanded, SETUNE must be legal!");
1603 CC1 = ISD::SETUNE; CC2 = ISD::SETUNE; Opc = ISD::OR; break;
1616 // If we are floating point, assign and break, otherwise fall through.
1617 if (!OpVT.isInteger()) {
1618 // We can use the 4th bit to tell if we are the unordered
1619 // or ordered version of the opcode.
1620 CC2 = ((unsigned)CCCode & 0x8U) ? ISD::SETUO : ISD::SETO;
1621 Opc = ((unsigned)CCCode & 0x8U) ? ISD::OR : ISD::AND;
1622 CC1 = (ISD::CondCode)(((int)CCCode & 0x7) | 0x10);
1625 // Fallthrough if we are unsigned integer.
1632 InvCC = ISD::getSetCCSwappedOperands(CCCode);
1633 if (TLI.getCondCodeAction(InvCC, OpVT) == TargetLowering::Expand) {
1634 // We only support using the inverted operation and not a
1635 // different manner of supporting expanding these cases.
1636 llvm_unreachable("Don't know how to expand this condition!");
1638 LHS = DAG.getSetCC(dl, VT, RHS, LHS, InvCC);
1644 SDValue SetCC1, SetCC2;
1645 if (CCCode != ISD::SETO && CCCode != ISD::SETUO) {
1646 // If we aren't the ordered or unorder operation,
1647 // then the pattern is (LHS CC1 RHS) Opc (LHS CC2 RHS).
1648 SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1649 SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1651 // Otherwise, the pattern is (LHS CC1 LHS) Opc (RHS CC2 RHS)
1652 SetCC1 = DAG.getSetCC(dl, VT, LHS, LHS, CC1);
1653 SetCC2 = DAG.getSetCC(dl, VT, RHS, RHS, CC2);
1655 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1663 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
1664 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1665 /// a load from the stack slot to DestVT, extending it if needed.
1666 /// The resultant code need not be legal.
1667 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
1671 // Create the stack frame object.
1673 TLI.getDataLayout()->getPrefTypeAlignment(SrcOp.getValueType().
1674 getTypeForEVT(*DAG.getContext()));
1675 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1677 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1678 int SPFI = StackPtrFI->getIndex();
1679 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(SPFI);
1681 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
1682 unsigned SlotSize = SlotVT.getSizeInBits();
1683 unsigned DestSize = DestVT.getSizeInBits();
1684 Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
1685 unsigned DestAlign = TLI.getDataLayout()->getPrefTypeAlignment(DestType);
1687 // Emit a store to the stack slot. Use a truncstore if the input value is
1688 // later than DestVT.
1691 if (SrcSize > SlotSize)
1692 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1693 PtrInfo, SlotVT, false, false, SrcAlign);
1695 assert(SrcSize == SlotSize && "Invalid store");
1696 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1697 PtrInfo, false, false, SrcAlign);
1700 // Result is a load from the stack slot.
1701 if (SlotSize == DestSize)
1702 return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo,
1703 false, false, false, DestAlign);
1705 assert(SlotSize < DestSize && "Unknown extension!");
1706 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr,
1707 PtrInfo, SlotVT, false, false, DestAlign);
1710 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1711 DebugLoc dl = Node->getDebugLoc();
1712 // Create a vector sized/aligned stack slot, store the value to element #0,
1713 // then load the whole vector back out.
1714 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1716 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1717 int SPFI = StackPtrFI->getIndex();
1719 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0),
1721 MachinePointerInfo::getFixedStack(SPFI),
1722 Node->getValueType(0).getVectorElementType(),
1724 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
1725 MachinePointerInfo::getFixedStack(SPFI),
1726 false, false, false, 0);
1730 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
1731 /// support the operation, but do support the resultant vector type.
1732 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1733 unsigned NumElems = Node->getNumOperands();
1734 SDValue Value1, Value2;
1735 DebugLoc dl = Node->getDebugLoc();
1736 EVT VT = Node->getValueType(0);
1737 EVT OpVT = Node->getOperand(0).getValueType();
1738 EVT EltVT = VT.getVectorElementType();
1740 // If the only non-undef value is the low element, turn this into a
1741 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1742 bool isOnlyLowElement = true;
1743 bool MoreThanTwoValues = false;
1744 bool isConstant = true;
1745 for (unsigned i = 0; i < NumElems; ++i) {
1746 SDValue V = Node->getOperand(i);
1747 if (V.getOpcode() == ISD::UNDEF)
1750 isOnlyLowElement = false;
1751 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1754 if (!Value1.getNode()) {
1756 } else if (!Value2.getNode()) {
1759 } else if (V != Value1 && V != Value2) {
1760 MoreThanTwoValues = true;
1764 if (!Value1.getNode())
1765 return DAG.getUNDEF(VT);
1767 if (isOnlyLowElement)
1768 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1770 // If all elements are constants, create a load from the constant pool.
1772 SmallVector<Constant*, 16> CV;
1773 for (unsigned i = 0, e = NumElems; i != e; ++i) {
1774 if (ConstantFPSDNode *V =
1775 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1776 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1777 } else if (ConstantSDNode *V =
1778 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1780 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1782 // If OpVT and EltVT don't match, EltVT is not legal and the
1783 // element values have been promoted/truncated earlier. Undo this;
1784 // we don't want a v16i8 to become a v16i32 for example.
1785 const ConstantInt *CI = V->getConstantIntValue();
1786 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
1787 CI->getZExtValue()));
1790 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
1791 Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
1792 CV.push_back(UndefValue::get(OpNTy));
1795 Constant *CP = ConstantVector::get(CV);
1796 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
1797 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
1798 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
1799 MachinePointerInfo::getConstantPool(),
1800 false, false, false, Alignment);
1803 if (!MoreThanTwoValues) {
1804 SmallVector<int, 8> ShuffleVec(NumElems, -1);
1805 for (unsigned i = 0; i < NumElems; ++i) {
1806 SDValue V = Node->getOperand(i);
1807 if (V.getOpcode() == ISD::UNDEF)
1809 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
1811 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
1812 // Get the splatted value into the low element of a vector register.
1813 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
1815 if (Value2.getNode())
1816 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
1818 Vec2 = DAG.getUNDEF(VT);
1820 // Return shuffle(LowValVec, undef, <0,0,0,0>)
1821 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
1825 // Otherwise, we can't handle this case efficiently.
1826 return ExpandVectorBuildThroughStack(Node);
1829 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
1830 // does not fit into a register, return the lo part and set the hi part to the
1831 // by-reg argument. If it does fit into a single register, return the result
1832 // and leave the Hi part unset.
1833 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
1835 TargetLowering::ArgListTy Args;
1836 TargetLowering::ArgListEntry Entry;
1837 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1838 EVT ArgVT = Node->getOperand(i).getValueType();
1839 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1840 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
1841 Entry.isSExt = isSigned;
1842 Entry.isZExt = !isSigned;
1843 Args.push_back(Entry);
1845 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1846 TLI.getPointerTy());
1848 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
1850 // By default, the input chain to this libcall is the entry node of the
1851 // function. If the libcall is going to be emitted as a tail call then
1852 // TLI.isUsedByReturnOnly will change it to the right chain if the return
1853 // node which is being folded has a non-entry input chain.
1854 SDValue InChain = DAG.getEntryNode();
1856 // isTailCall may be true since the callee does not reference caller stack
1857 // frame. Check if it's in the right position.
1858 SDValue TCChain = InChain;
1859 bool isTailCall = isInTailCallPosition(DAG, Node, TCChain, TLI);
1864 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
1865 0, TLI.getLibcallCallingConv(LC), isTailCall,
1866 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
1867 Callee, Args, DAG, Node->getDebugLoc());
1868 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
1871 if (!CallInfo.second.getNode())
1872 // It's a tailcall, return the chain (which is the DAG root).
1873 return DAG.getRoot();
1875 return CallInfo.first;
1878 /// ExpandLibCall - Generate a libcall taking the given operands as arguments
1879 /// and returning a result of type RetVT.
1880 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, EVT RetVT,
1881 const SDValue *Ops, unsigned NumOps,
1882 bool isSigned, DebugLoc dl) {
1883 TargetLowering::ArgListTy Args;
1884 Args.reserve(NumOps);
1886 TargetLowering::ArgListEntry Entry;
1887 for (unsigned i = 0; i != NumOps; ++i) {
1888 Entry.Node = Ops[i];
1889 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
1890 Entry.isSExt = isSigned;
1891 Entry.isZExt = !isSigned;
1892 Args.push_back(Entry);
1894 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1895 TLI.getPointerTy());
1897 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
1899 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
1900 false, 0, TLI.getLibcallCallingConv(LC),
1901 /*isTailCall=*/false,
1902 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
1903 Callee, Args, DAG, dl);
1904 std::pair<SDValue,SDValue> CallInfo = TLI.LowerCallTo(CLI);
1906 return CallInfo.first;
1909 // ExpandChainLibCall - Expand a node into a call to a libcall. Similar to
1910 // ExpandLibCall except that the first operand is the in-chain.
1911 std::pair<SDValue, SDValue>
1912 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
1915 SDValue InChain = Node->getOperand(0);
1917 TargetLowering::ArgListTy Args;
1918 TargetLowering::ArgListEntry Entry;
1919 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) {
1920 EVT ArgVT = Node->getOperand(i).getValueType();
1921 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1922 Entry.Node = Node->getOperand(i);
1924 Entry.isSExt = isSigned;
1925 Entry.isZExt = !isSigned;
1926 Args.push_back(Entry);
1928 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1929 TLI.getPointerTy());
1931 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
1933 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
1934 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
1935 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
1936 Callee, Args, DAG, Node->getDebugLoc());
1937 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
1942 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
1943 RTLIB::Libcall Call_F32,
1944 RTLIB::Libcall Call_F64,
1945 RTLIB::Libcall Call_F80,
1946 RTLIB::Libcall Call_PPCF128) {
1948 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
1949 default: llvm_unreachable("Unexpected request for libcall!");
1950 case MVT::f32: LC = Call_F32; break;
1951 case MVT::f64: LC = Call_F64; break;
1952 case MVT::f80: LC = Call_F80; break;
1953 case MVT::ppcf128: LC = Call_PPCF128; break;
1955 return ExpandLibCall(LC, Node, false);
1958 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
1959 RTLIB::Libcall Call_I8,
1960 RTLIB::Libcall Call_I16,
1961 RTLIB::Libcall Call_I32,
1962 RTLIB::Libcall Call_I64,
1963 RTLIB::Libcall Call_I128) {
1965 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
1966 default: llvm_unreachable("Unexpected request for libcall!");
1967 case MVT::i8: LC = Call_I8; break;
1968 case MVT::i16: LC = Call_I16; break;
1969 case MVT::i32: LC = Call_I32; break;
1970 case MVT::i64: LC = Call_I64; break;
1971 case MVT::i128: LC = Call_I128; break;
1973 return ExpandLibCall(LC, Node, isSigned);
1976 /// isDivRemLibcallAvailable - Return true if divmod libcall is available.
1977 static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
1978 const TargetLowering &TLI) {
1980 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
1981 default: llvm_unreachable("Unexpected request for libcall!");
1982 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
1983 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
1984 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
1985 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
1986 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
1989 return TLI.getLibcallName(LC) != 0;
1992 /// useDivRem - Only issue divrem libcall if both quotient and remainder are
1994 static bool useDivRem(SDNode *Node, bool isSigned, bool isDIV) {
1995 // The other use might have been replaced with a divrem already.
1996 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
1997 unsigned OtherOpcode = 0;
1999 OtherOpcode = isDIV ? ISD::SREM : ISD::SDIV;
2001 OtherOpcode = isDIV ? ISD::UREM : ISD::UDIV;
2003 SDValue Op0 = Node->getOperand(0);
2004 SDValue Op1 = Node->getOperand(1);
2005 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2006 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2010 if ((User->getOpcode() == OtherOpcode || User->getOpcode() == DivRemOpc) &&
2011 User->getOperand(0) == Op0 &&
2012 User->getOperand(1) == Op1)
2018 /// ExpandDivRemLibCall - Issue libcalls to __{u}divmod to compute div / rem
2021 SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
2022 SmallVectorImpl<SDValue> &Results) {
2023 unsigned Opcode = Node->getOpcode();
2024 bool isSigned = Opcode == ISD::SDIVREM;
2027 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
2028 default: llvm_unreachable("Unexpected request for libcall!");
2029 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2030 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2031 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2032 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2033 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2036 // The input chain to this libcall is the entry node of the function.
2037 // Legalizing the call will automatically add the previous call to the
2039 SDValue InChain = DAG.getEntryNode();
2041 EVT RetVT = Node->getValueType(0);
2042 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2044 TargetLowering::ArgListTy Args;
2045 TargetLowering::ArgListEntry Entry;
2046 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2047 EVT ArgVT = Node->getOperand(i).getValueType();
2048 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2049 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
2050 Entry.isSExt = isSigned;
2051 Entry.isZExt = !isSigned;
2052 Args.push_back(Entry);
2055 // Also pass the return address of the remainder.
2056 SDValue FIPtr = DAG.CreateStackTemporary(RetVT);
2058 Entry.Ty = RetTy->getPointerTo();
2059 Entry.isSExt = isSigned;
2060 Entry.isZExt = !isSigned;
2061 Args.push_back(Entry);
2063 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2064 TLI.getPointerTy());
2066 DebugLoc dl = Node->getDebugLoc();
2068 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
2069 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
2070 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2071 Callee, Args, DAG, dl);
2072 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2074 // Remainder is loaded back from the stack frame.
2075 SDValue Rem = DAG.getLoad(RetVT, dl, CallInfo.second, FIPtr,
2076 MachinePointerInfo(), false, false, false, 0);
2077 Results.push_back(CallInfo.first);
2078 Results.push_back(Rem);
2081 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
2082 /// INT_TO_FP operation of the specified operand when the target requests that
2083 /// we expand it. At this point, we know that the result and operand types are
2084 /// legal for the target.
2085 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
2089 if (Op0.getValueType() == MVT::i32 && TLI.isTypeLegal(MVT::f64)) {
2090 // simple 32-bit [signed|unsigned] integer to float/double expansion
2092 // Get the stack frame index of a 8 byte buffer.
2093 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2095 // word offset constant for Hi/Lo address computation
2096 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
2097 // set up Hi and Lo (into buffer) address based on endian
2098 SDValue Hi = StackSlot;
2099 SDValue Lo = DAG.getNode(ISD::ADD, dl,
2100 TLI.getPointerTy(), StackSlot, WordOff);
2101 if (TLI.isLittleEndian())
2104 // if signed map to unsigned space
2107 // constant used to invert sign bit (signed to unsigned mapping)
2108 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
2109 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2113 // store the lo of the constructed double - based on integer input
2114 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
2115 Op0Mapped, Lo, MachinePointerInfo(),
2117 // initial hi portion of constructed double
2118 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
2119 // store the hi of the constructed double - biased exponent
2120 SDValue Store2 = DAG.getStore(Store1, dl, InitialHi, Hi,
2121 MachinePointerInfo(),
2123 // load the constructed double
2124 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot,
2125 MachinePointerInfo(), false, false, false, 0);
2126 // FP constant to bias correct the final result
2127 SDValue Bias = DAG.getConstantFP(isSigned ?
2128 BitsToDouble(0x4330000080000000ULL) :
2129 BitsToDouble(0x4330000000000000ULL),
2131 // subtract the bias
2132 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2135 // handle final rounding
2136 if (DestVT == MVT::f64) {
2139 } else if (DestVT.bitsLT(MVT::f64)) {
2140 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2141 DAG.getIntPtrConstant(0));
2142 } else if (DestVT.bitsGT(MVT::f64)) {
2143 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2147 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2148 // Code below here assumes !isSigned without checking again.
2150 // Implementation of unsigned i64 to f64 following the algorithm in
2151 // __floatundidf in compiler_rt. This implementation has the advantage
2152 // of performing rounding correctly, both in the default rounding mode
2153 // and in all alternate rounding modes.
2154 // TODO: Generalize this for use with other types.
2155 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
2157 DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64);
2158 SDValue TwoP84PlusTwoP52 =
2159 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64);
2161 DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64);
2163 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32);
2164 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2165 DAG.getConstant(32, MVT::i64));
2166 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2167 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2168 SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr);
2169 SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr);
2170 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
2172 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
2175 // Implementation of unsigned i64 to f32.
2176 // TODO: Generalize this for use with other types.
2177 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) {
2178 // For unsigned conversions, convert them to signed conversions using the
2179 // algorithm from the x86_64 __floatundidf in compiler_rt.
2181 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0);
2183 SDValue ShiftConst =
2184 DAG.getConstant(1, TLI.getShiftAmountTy(Op0.getValueType()));
2185 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
2186 SDValue AndConst = DAG.getConstant(1, MVT::i64);
2187 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst);
2188 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr);
2190 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or);
2191 SDValue Slow = DAG.getNode(ISD::FADD, dl, MVT::f32, SignCvt, SignCvt);
2193 // TODO: This really should be implemented using a branch rather than a
2194 // select. We happen to get lucky and machinesink does the right
2195 // thing most of the time. This would be a good candidate for a
2196 //pseudo-op, or, even better, for whole-function isel.
2197 SDValue SignBitTest = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2198 Op0, DAG.getConstant(0, MVT::i64), ISD::SETLT);
2199 return DAG.getNode(ISD::SELECT, dl, MVT::f32, SignBitTest, Slow, Fast);
2202 // Otherwise, implement the fully general conversion.
2204 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2205 DAG.getConstant(UINT64_C(0xfffffffffffff800), MVT::i64));
2206 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
2207 DAG.getConstant(UINT64_C(0x800), MVT::i64));
2208 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2209 DAG.getConstant(UINT64_C(0x7ff), MVT::i64));
2210 SDValue Ne = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2211 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE);
2212 SDValue Sel = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ne, Or, Op0);
2213 SDValue Ge = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2214 Op0, DAG.getConstant(UINT64_C(0x0020000000000000), MVT::i64),
2216 SDValue Sel2 = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ge, Sel, Op0);
2217 EVT SHVT = TLI.getShiftAmountTy(Sel2.getValueType());
2219 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2220 DAG.getConstant(32, SHVT));
2221 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh);
2222 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc);
2224 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), MVT::f64);
2225 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt);
2226 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2);
2227 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo);
2228 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2);
2229 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd,
2230 DAG.getIntPtrConstant(0));
2233 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2235 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()),
2236 Op0, DAG.getConstant(0, Op0.getValueType()),
2238 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
2239 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
2240 SignSet, Four, Zero);
2242 // If the sign bit of the integer is set, the large number will be treated
2243 // as a negative number. To counteract this, the dynamic code adds an
2244 // offset depending on the data type.
2246 switch (Op0.getValueType().getSimpleVT().SimpleTy) {
2247 default: llvm_unreachable("Unsupported integer type!");
2248 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2249 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2250 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2251 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2253 if (TLI.isLittleEndian()) FF <<= 32;
2254 Constant *FudgeFactor = ConstantInt::get(
2255 Type::getInt64Ty(*DAG.getContext()), FF);
2257 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
2258 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2259 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
2260 Alignment = std::min(Alignment, 4u);
2262 if (DestVT == MVT::f32)
2263 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2264 MachinePointerInfo::getConstantPool(),
2265 false, false, false, Alignment);
2267 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
2268 DAG.getEntryNode(), CPIdx,
2269 MachinePointerInfo::getConstantPool(),
2270 MVT::f32, false, false, Alignment);
2271 HandleSDNode Handle(Load);
2272 LegalizeOp(Load.getNode());
2273 FudgeInReg = Handle.getValue();
2276 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2279 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
2280 /// *INT_TO_FP operation of the specified operand when the target requests that
2281 /// we promote it. At this point, we know that the result and operand types are
2282 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2283 /// operation that takes a larger input.
2284 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2288 // First step, figure out the appropriate *INT_TO_FP operation to use.
2289 EVT NewInTy = LegalOp.getValueType();
2291 unsigned OpToUse = 0;
2293 // Scan for the appropriate larger type to use.
2295 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2296 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2298 // If the target supports SINT_TO_FP of this type, use it.
2299 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2300 OpToUse = ISD::SINT_TO_FP;
2303 if (isSigned) continue;
2305 // If the target supports UINT_TO_FP of this type, use it.
2306 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2307 OpToUse = ISD::UINT_TO_FP;
2311 // Otherwise, try a larger type.
2314 // Okay, we found the operation and type to use. Zero extend our input to the
2315 // desired type then run the operation on it.
2316 return DAG.getNode(OpToUse, dl, DestVT,
2317 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2318 dl, NewInTy, LegalOp));
2321 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
2322 /// FP_TO_*INT operation of the specified operand when the target requests that
2323 /// we promote it. At this point, we know that the result and operand types are
2324 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2325 /// operation that returns a larger result.
2326 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2330 // First step, figure out the appropriate FP_TO*INT operation to use.
2331 EVT NewOutTy = DestVT;
2333 unsigned OpToUse = 0;
2335 // Scan for the appropriate larger type to use.
2337 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2338 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2340 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2341 OpToUse = ISD::FP_TO_SINT;
2345 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2346 OpToUse = ISD::FP_TO_UINT;
2350 // Otherwise, try a larger type.
2354 // Okay, we found the operation and type to use.
2355 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2357 // Truncate the result of the extended FP_TO_*INT operation to the desired
2359 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2362 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
2364 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) {
2365 EVT VT = Op.getValueType();
2366 EVT SHVT = TLI.getShiftAmountTy(VT);
2367 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2368 switch (VT.getSimpleVT().SimpleTy) {
2369 default: llvm_unreachable("Unhandled Expand type in BSWAP!");
2371 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2372 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2373 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2375 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2376 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2377 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2378 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2379 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
2380 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
2381 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2382 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2383 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2385 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
2386 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
2387 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2388 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2389 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2390 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2391 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
2392 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
2393 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
2394 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
2395 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
2396 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
2397 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
2398 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
2399 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2400 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2401 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2402 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2403 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2404 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2405 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2409 /// SplatByte - Distribute ByteVal over NumBits bits.
2410 // FIXME: Move this helper to a common place.
2411 static APInt SplatByte(unsigned NumBits, uint8_t ByteVal) {
2412 APInt Val = APInt(NumBits, ByteVal);
2414 for (unsigned i = NumBits; i > 8; i >>= 1) {
2415 Val = (Val << Shift) | Val;
2421 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
2423 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2426 default: llvm_unreachable("Cannot expand this yet!");
2428 EVT VT = Op.getValueType();
2429 EVT ShVT = TLI.getShiftAmountTy(VT);
2430 unsigned Len = VT.getSizeInBits();
2432 assert(VT.isInteger() && Len <= 128 && Len % 8 == 0 &&
2433 "CTPOP not implemented for this type.");
2435 // This is the "best" algorithm from
2436 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
2438 SDValue Mask55 = DAG.getConstant(SplatByte(Len, 0x55), VT);
2439 SDValue Mask33 = DAG.getConstant(SplatByte(Len, 0x33), VT);
2440 SDValue Mask0F = DAG.getConstant(SplatByte(Len, 0x0F), VT);
2441 SDValue Mask01 = DAG.getConstant(SplatByte(Len, 0x01), VT);
2443 // v = v - ((v >> 1) & 0x55555555...)
2444 Op = DAG.getNode(ISD::SUB, dl, VT, Op,
2445 DAG.getNode(ISD::AND, dl, VT,
2446 DAG.getNode(ISD::SRL, dl, VT, Op,
2447 DAG.getConstant(1, ShVT)),
2449 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
2450 Op = DAG.getNode(ISD::ADD, dl, VT,
2451 DAG.getNode(ISD::AND, dl, VT, Op, Mask33),
2452 DAG.getNode(ISD::AND, dl, VT,
2453 DAG.getNode(ISD::SRL, dl, VT, Op,
2454 DAG.getConstant(2, ShVT)),
2456 // v = (v + (v >> 4)) & 0x0F0F0F0F...
2457 Op = DAG.getNode(ISD::AND, dl, VT,
2458 DAG.getNode(ISD::ADD, dl, VT, Op,
2459 DAG.getNode(ISD::SRL, dl, VT, Op,
2460 DAG.getConstant(4, ShVT))),
2462 // v = (v * 0x01010101...) >> (Len - 8)
2463 Op = DAG.getNode(ISD::SRL, dl, VT,
2464 DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
2465 DAG.getConstant(Len - 8, ShVT));
2469 case ISD::CTLZ_ZERO_UNDEF:
2470 // This trivially expands to CTLZ.
2471 return DAG.getNode(ISD::CTLZ, dl, Op.getValueType(), Op);
2473 // for now, we do this:
2474 // x = x | (x >> 1);
2475 // x = x | (x >> 2);
2477 // x = x | (x >>16);
2478 // x = x | (x >>32); // for 64-bit input
2479 // return popcount(~x);
2481 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
2482 EVT VT = Op.getValueType();
2483 EVT ShVT = TLI.getShiftAmountTy(VT);
2484 unsigned len = VT.getSizeInBits();
2485 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2486 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2487 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2488 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2490 Op = DAG.getNOT(dl, Op, VT);
2491 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2493 case ISD::CTTZ_ZERO_UNDEF:
2494 // This trivially expands to CTTZ.
2495 return DAG.getNode(ISD::CTTZ, dl, Op.getValueType(), Op);
2497 // for now, we use: { return popcount(~x & (x - 1)); }
2498 // unless the target has ctlz but not ctpop, in which case we use:
2499 // { return 32 - nlz(~x & (x-1)); }
2500 // see also http://www.hackersdelight.org/HDcode/ntz.cc
2501 EVT VT = Op.getValueType();
2502 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2503 DAG.getNOT(dl, Op, VT),
2504 DAG.getNode(ISD::SUB, dl, VT, Op,
2505 DAG.getConstant(1, VT)));
2506 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2507 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2508 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2509 return DAG.getNode(ISD::SUB, dl, VT,
2510 DAG.getConstant(VT.getSizeInBits(), VT),
2511 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2512 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2517 std::pair <SDValue, SDValue> SelectionDAGLegalize::ExpandAtomic(SDNode *Node) {
2518 unsigned Opc = Node->getOpcode();
2519 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
2524 llvm_unreachable("Unhandled atomic intrinsic Expand!");
2525 case ISD::ATOMIC_SWAP:
2526 switch (VT.SimpleTy) {
2527 default: llvm_unreachable("Unexpected value type for atomic!");
2528 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break;
2529 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
2530 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
2531 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
2534 case ISD::ATOMIC_CMP_SWAP:
2535 switch (VT.SimpleTy) {
2536 default: llvm_unreachable("Unexpected value type for atomic!");
2537 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break;
2538 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;
2539 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;
2540 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
2543 case ISD::ATOMIC_LOAD_ADD:
2544 switch (VT.SimpleTy) {
2545 default: llvm_unreachable("Unexpected value type for atomic!");
2546 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break;
2547 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;
2548 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;
2549 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
2552 case ISD::ATOMIC_LOAD_SUB:
2553 switch (VT.SimpleTy) {
2554 default: llvm_unreachable("Unexpected value type for atomic!");
2555 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break;
2556 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;
2557 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;
2558 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
2561 case ISD::ATOMIC_LOAD_AND:
2562 switch (VT.SimpleTy) {
2563 default: llvm_unreachable("Unexpected value type for atomic!");
2564 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break;
2565 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;
2566 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;
2567 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
2570 case ISD::ATOMIC_LOAD_OR:
2571 switch (VT.SimpleTy) {
2572 default: llvm_unreachable("Unexpected value type for atomic!");
2573 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break;
2574 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;
2575 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;
2576 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
2579 case ISD::ATOMIC_LOAD_XOR:
2580 switch (VT.SimpleTy) {
2581 default: llvm_unreachable("Unexpected value type for atomic!");
2582 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break;
2583 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;
2584 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;
2585 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
2588 case ISD::ATOMIC_LOAD_NAND:
2589 switch (VT.SimpleTy) {
2590 default: llvm_unreachable("Unexpected value type for atomic!");
2591 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break;
2592 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;
2593 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;
2594 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
2599 return ExpandChainLibCall(LC, Node, false);
2602 void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
2603 SmallVector<SDValue, 8> Results;
2604 DebugLoc dl = Node->getDebugLoc();
2605 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2606 switch (Node->getOpcode()) {
2609 case ISD::CTLZ_ZERO_UNDEF:
2611 case ISD::CTTZ_ZERO_UNDEF:
2612 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
2613 Results.push_back(Tmp1);
2616 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2618 case ISD::FRAMEADDR:
2619 case ISD::RETURNADDR:
2620 case ISD::FRAME_TO_ARGS_OFFSET:
2621 Results.push_back(DAG.getConstant(0, Node->getValueType(0)));
2623 case ISD::FLT_ROUNDS_:
2624 Results.push_back(DAG.getConstant(1, Node->getValueType(0)));
2626 case ISD::EH_RETURN:
2630 case ISD::EH_SJLJ_LONGJMP:
2631 // If the target didn't expand these, there's nothing to do, so just
2632 // preserve the chain and be done.
2633 Results.push_back(Node->getOperand(0));
2635 case ISD::EH_SJLJ_SETJMP:
2636 // If the target didn't expand this, just return 'zero' and preserve the
2638 Results.push_back(DAG.getConstant(0, MVT::i32));
2639 Results.push_back(Node->getOperand(0));
2641 case ISD::ATOMIC_FENCE:
2642 case ISD::MEMBARRIER: {
2643 // If the target didn't lower this, lower it to '__sync_synchronize()' call
2644 // FIXME: handle "fence singlethread" more efficiently.
2645 TargetLowering::ArgListTy Args;
2647 CallLoweringInfo CLI(Node->getOperand(0),
2648 Type::getVoidTy(*DAG.getContext()),
2649 false, false, false, false, 0, CallingConv::C,
2650 /*isTailCall=*/false,
2651 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2652 DAG.getExternalSymbol("__sync_synchronize",
2653 TLI.getPointerTy()),
2655 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
2657 Results.push_back(CallResult.second);
2660 case ISD::ATOMIC_LOAD: {
2661 // There is no libcall for atomic load; fake it with ATOMIC_CMP_SWAP.
2662 SDValue Zero = DAG.getConstant(0, Node->getValueType(0));
2663 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl,
2664 cast<AtomicSDNode>(Node)->getMemoryVT(),
2665 Node->getOperand(0),
2666 Node->getOperand(1), Zero, Zero,
2667 cast<AtomicSDNode>(Node)->getMemOperand(),
2668 cast<AtomicSDNode>(Node)->getOrdering(),
2669 cast<AtomicSDNode>(Node)->getSynchScope());
2670 Results.push_back(Swap.getValue(0));
2671 Results.push_back(Swap.getValue(1));
2674 case ISD::ATOMIC_STORE: {
2675 // There is no libcall for atomic store; fake it with ATOMIC_SWAP.
2676 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
2677 cast<AtomicSDNode>(Node)->getMemoryVT(),
2678 Node->getOperand(0),
2679 Node->getOperand(1), Node->getOperand(2),
2680 cast<AtomicSDNode>(Node)->getMemOperand(),
2681 cast<AtomicSDNode>(Node)->getOrdering(),
2682 cast<AtomicSDNode>(Node)->getSynchScope());
2683 Results.push_back(Swap.getValue(1));
2686 // By default, atomic intrinsics are marked Legal and lowered. Targets
2687 // which don't support them directly, however, may want libcalls, in which
2688 // case they mark them Expand, and we get here.
2689 case ISD::ATOMIC_SWAP:
2690 case ISD::ATOMIC_LOAD_ADD:
2691 case ISD::ATOMIC_LOAD_SUB:
2692 case ISD::ATOMIC_LOAD_AND:
2693 case ISD::ATOMIC_LOAD_OR:
2694 case ISD::ATOMIC_LOAD_XOR:
2695 case ISD::ATOMIC_LOAD_NAND:
2696 case ISD::ATOMIC_LOAD_MIN:
2697 case ISD::ATOMIC_LOAD_MAX:
2698 case ISD::ATOMIC_LOAD_UMIN:
2699 case ISD::ATOMIC_LOAD_UMAX:
2700 case ISD::ATOMIC_CMP_SWAP: {
2701 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node);
2702 Results.push_back(Tmp.first);
2703 Results.push_back(Tmp.second);
2706 case ISD::DYNAMIC_STACKALLOC:
2707 ExpandDYNAMIC_STACKALLOC(Node, Results);
2709 case ISD::MERGE_VALUES:
2710 for (unsigned i = 0; i < Node->getNumValues(); i++)
2711 Results.push_back(Node->getOperand(i));
2714 EVT VT = Node->getValueType(0);
2716 Results.push_back(DAG.getConstant(0, VT));
2718 assert(VT.isFloatingPoint() && "Unknown value type!");
2719 Results.push_back(DAG.getConstantFP(0, VT));
2724 // If this operation is not supported, lower it to 'abort()' call
2725 TargetLowering::ArgListTy Args;
2727 CallLoweringInfo CLI(Node->getOperand(0),
2728 Type::getVoidTy(*DAG.getContext()),
2729 false, false, false, false, 0, CallingConv::C,
2730 /*isTailCall=*/false,
2731 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2732 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
2734 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
2736 Results.push_back(CallResult.second);
2741 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
2742 Node->getValueType(0), dl);
2743 Results.push_back(Tmp1);
2745 case ISD::FP_EXTEND:
2746 Tmp1 = EmitStackConvert(Node->getOperand(0),
2747 Node->getOperand(0).getValueType(),
2748 Node->getValueType(0), dl);
2749 Results.push_back(Tmp1);
2751 case ISD::SIGN_EXTEND_INREG: {
2752 // NOTE: we could fall back on load/store here too for targets without
2753 // SAR. However, it is doubtful that any exist.
2754 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2755 EVT VT = Node->getValueType(0);
2756 EVT ShiftAmountTy = TLI.getShiftAmountTy(VT);
2759 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
2760 ExtraVT.getScalarType().getSizeInBits();
2761 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy);
2762 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
2763 Node->getOperand(0), ShiftCst);
2764 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
2765 Results.push_back(Tmp1);
2768 case ISD::FP_ROUND_INREG: {
2769 // The only way we can lower this is to turn it into a TRUNCSTORE,
2770 // EXTLOAD pair, targeting a temporary location (a stack slot).
2772 // NOTE: there is a choice here between constantly creating new stack
2773 // slots and always reusing the same one. We currently always create
2774 // new ones, as reuse may inhibit scheduling.
2775 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2776 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
2777 Node->getValueType(0), dl);
2778 Results.push_back(Tmp1);
2781 case ISD::SINT_TO_FP:
2782 case ISD::UINT_TO_FP:
2783 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
2784 Node->getOperand(0), Node->getValueType(0), dl);
2785 Results.push_back(Tmp1);
2787 case ISD::FP_TO_UINT: {
2788 SDValue True, False;
2789 EVT VT = Node->getOperand(0).getValueType();
2790 EVT NVT = Node->getValueType(0);
2791 APFloat apf(APInt::getNullValue(VT.getSizeInBits()));
2792 APInt x = APInt::getSignBit(NVT.getSizeInBits());
2793 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
2794 Tmp1 = DAG.getConstantFP(apf, VT);
2795 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
2796 Node->getOperand(0),
2798 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
2799 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
2800 DAG.getNode(ISD::FSUB, dl, VT,
2801 Node->getOperand(0), Tmp1));
2802 False = DAG.getNode(ISD::XOR, dl, NVT, False,
2803 DAG.getConstant(x, NVT));
2804 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False);
2805 Results.push_back(Tmp1);
2809 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2810 EVT VT = Node->getValueType(0);
2811 Tmp1 = Node->getOperand(0);
2812 Tmp2 = Node->getOperand(1);
2813 unsigned Align = Node->getConstantOperandVal(3);
2815 SDValue VAListLoad = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2,
2816 MachinePointerInfo(V),
2817 false, false, false, 0);
2818 SDValue VAList = VAListLoad;
2820 if (Align > TLI.getMinStackArgumentAlignment()) {
2821 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
2823 VAList = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
2824 DAG.getConstant(Align - 1,
2825 TLI.getPointerTy()));
2827 VAList = DAG.getNode(ISD::AND, dl, TLI.getPointerTy(), VAList,
2828 DAG.getConstant(-(int64_t)Align,
2829 TLI.getPointerTy()));
2832 // Increment the pointer, VAList, to the next vaarg
2833 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
2834 DAG.getConstant(TLI.getDataLayout()->
2835 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())),
2836 TLI.getPointerTy()));
2837 // Store the incremented VAList to the legalized pointer
2838 Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2,
2839 MachinePointerInfo(V), false, false, 0);
2840 // Load the actual argument out of the pointer VAList
2841 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(),
2842 false, false, false, 0));
2843 Results.push_back(Results[0].getValue(1));
2847 // This defaults to loading a pointer from the input and storing it to the
2848 // output, returning the chain.
2849 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
2850 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
2851 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0),
2852 Node->getOperand(2), MachinePointerInfo(VS),
2853 false, false, false, 0);
2854 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1),
2855 MachinePointerInfo(VD), false, false, 0);
2856 Results.push_back(Tmp1);
2859 case ISD::EXTRACT_VECTOR_ELT:
2860 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
2861 // This must be an access of the only element. Return it.
2862 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
2863 Node->getOperand(0));
2865 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
2866 Results.push_back(Tmp1);
2868 case ISD::EXTRACT_SUBVECTOR:
2869 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
2871 case ISD::INSERT_SUBVECTOR:
2872 Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0)));
2874 case ISD::CONCAT_VECTORS: {
2875 Results.push_back(ExpandVectorBuildThroughStack(Node));
2878 case ISD::SCALAR_TO_VECTOR:
2879 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
2881 case ISD::INSERT_VECTOR_ELT:
2882 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
2883 Node->getOperand(1),
2884 Node->getOperand(2), dl));
2886 case ISD::VECTOR_SHUFFLE: {
2887 SmallVector<int, 32> NewMask;
2888 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
2890 EVT VT = Node->getValueType(0);
2891 EVT EltVT = VT.getVectorElementType();
2892 SDValue Op0 = Node->getOperand(0);
2893 SDValue Op1 = Node->getOperand(1);
2894 if (!TLI.isTypeLegal(EltVT)) {
2896 EVT NewEltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
2898 // BUILD_VECTOR operands are allowed to be wider than the element type.
2899 // But if NewEltVT is smaller that EltVT the BUILD_VECTOR does not accept it
2900 if (NewEltVT.bitsLT(EltVT)) {
2902 // Convert shuffle node.
2903 // If original node was v4i64 and the new EltVT is i32,
2904 // cast operands to v8i32 and re-build the mask.
2906 // Calculate new VT, the size of the new VT should be equal to original.
2907 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), NewEltVT,
2908 VT.getSizeInBits()/NewEltVT.getSizeInBits());
2909 assert(NewVT.bitsEq(VT));
2911 // cast operands to new VT
2912 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0);
2913 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1);
2915 // Convert the shuffle mask
2916 unsigned int factor = NewVT.getVectorNumElements()/VT.getVectorNumElements();
2918 // EltVT gets smaller
2921 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
2923 for (unsigned fi = 0; fi < factor; ++fi)
2924 NewMask.push_back(Mask[i]);
2927 for (unsigned fi = 0; fi < factor; ++fi)
2928 NewMask.push_back(Mask[i]*factor+fi);
2936 unsigned NumElems = VT.getVectorNumElements();
2937 SmallVector<SDValue, 16> Ops;
2938 for (unsigned i = 0; i != NumElems; ++i) {
2940 Ops.push_back(DAG.getUNDEF(EltVT));
2943 unsigned Idx = Mask[i];
2945 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
2947 DAG.getIntPtrConstant(Idx)));
2949 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
2951 DAG.getIntPtrConstant(Idx - NumElems)));
2954 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
2955 // We may have changed the BUILD_VECTOR type. Cast it back to the Node type.
2956 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), Tmp1);
2957 Results.push_back(Tmp1);
2960 case ISD::EXTRACT_ELEMENT: {
2961 EVT OpTy = Node->getOperand(0).getValueType();
2962 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
2964 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
2965 DAG.getConstant(OpTy.getSizeInBits()/2,
2966 TLI.getShiftAmountTy(Node->getOperand(0).getValueType())));
2967 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
2970 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
2971 Node->getOperand(0));
2973 Results.push_back(Tmp1);
2976 case ISD::STACKSAVE:
2977 // Expand to CopyFromReg if the target set
2978 // StackPointerRegisterToSaveRestore.
2979 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2980 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
2981 Node->getValueType(0)));
2982 Results.push_back(Results[0].getValue(1));
2984 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
2985 Results.push_back(Node->getOperand(0));
2988 case ISD::STACKRESTORE:
2989 // Expand to CopyToReg if the target set
2990 // StackPointerRegisterToSaveRestore.
2991 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2992 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
2993 Node->getOperand(1)));
2995 Results.push_back(Node->getOperand(0));
2998 case ISD::FCOPYSIGN:
2999 Results.push_back(ExpandFCOPYSIGN(Node));
3002 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3003 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3004 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
3005 Node->getOperand(0));
3006 Results.push_back(Tmp1);
3009 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3010 EVT VT = Node->getValueType(0);
3011 Tmp1 = Node->getOperand(0);
3012 Tmp2 = DAG.getConstantFP(0.0, VT);
3013 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
3014 Tmp1, Tmp2, ISD::SETUGT);
3015 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
3016 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3);
3017 Results.push_back(Tmp1);
3021 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3022 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128));
3025 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
3026 RTLIB::SIN_F80, RTLIB::SIN_PPCF128));
3029 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
3030 RTLIB::COS_F80, RTLIB::COS_PPCF128));
3033 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
3034 RTLIB::LOG_F80, RTLIB::LOG_PPCF128));
3037 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3038 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128));
3041 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3042 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128));
3045 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
3046 RTLIB::EXP_F80, RTLIB::EXP_PPCF128));
3049 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3050 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128));
3053 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3054 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128));
3057 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3058 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128));
3061 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3062 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128));
3065 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
3066 RTLIB::RINT_F80, RTLIB::RINT_PPCF128));
3068 case ISD::FNEARBYINT:
3069 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
3070 RTLIB::NEARBYINT_F64,
3071 RTLIB::NEARBYINT_F80,
3072 RTLIB::NEARBYINT_PPCF128));
3075 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
3076 RTLIB::POWI_F80, RTLIB::POWI_PPCF128));
3079 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
3080 RTLIB::POW_F80, RTLIB::POW_PPCF128));
3083 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
3084 RTLIB::DIV_F80, RTLIB::DIV_PPCF128));
3087 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
3088 RTLIB::REM_F80, RTLIB::REM_PPCF128));
3091 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMA_F32, RTLIB::FMA_F64,
3092 RTLIB::FMA_F80, RTLIB::FMA_PPCF128));
3094 case ISD::FP16_TO_FP32:
3095 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
3097 case ISD::FP32_TO_FP16:
3098 Results.push_back(ExpandLibCall(RTLIB::FPROUND_F32_F16, Node, false));
3100 case ISD::ConstantFP: {
3101 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
3102 // Check to see if this FP immediate is already legal.
3103 // If this is a legal constant, turn it into a TargetConstantFP node.
3104 if (!TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
3105 Results.push_back(ExpandConstantFP(CFP, true));
3108 case ISD::EHSELECTION: {
3109 unsigned Reg = TLI.getExceptionSelectorRegister();
3110 assert(Reg && "Can't expand to unknown register!");
3111 Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg,
3112 Node->getValueType(0)));
3113 Results.push_back(Results[0].getValue(1));
3116 case ISD::EXCEPTIONADDR: {
3117 unsigned Reg = TLI.getExceptionPointerRegister();
3118 assert(Reg && "Can't expand to unknown register!");
3119 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg,
3120 Node->getValueType(0)));
3121 Results.push_back(Results[0].getValue(1));
3125 EVT VT = Node->getValueType(0);
3126 assert(TLI.isOperationLegalOrCustom(ISD::FADD, VT) &&
3127 TLI.isOperationLegalOrCustom(ISD::FNEG, VT) &&
3128 "Don't know how to expand this FP subtraction!");
3129 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1));
3130 Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1);
3131 Results.push_back(Tmp1);
3135 EVT VT = Node->getValueType(0);
3136 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3137 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3138 "Don't know how to expand this subtraction!");
3139 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3140 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
3141 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, VT));
3142 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3147 EVT VT = Node->getValueType(0);
3148 SDVTList VTs = DAG.getVTList(VT, VT);
3149 bool isSigned = Node->getOpcode() == ISD::SREM;
3150 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3151 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3152 Tmp2 = Node->getOperand(0);
3153 Tmp3 = Node->getOperand(1);
3154 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3155 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3156 useDivRem(Node, isSigned, false))) {
3157 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
3158 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
3160 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
3161 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3162 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3163 } else if (isSigned)
3164 Tmp1 = ExpandIntLibCall(Node, true,
3166 RTLIB::SREM_I16, RTLIB::SREM_I32,
3167 RTLIB::SREM_I64, RTLIB::SREM_I128);
3169 Tmp1 = ExpandIntLibCall(Node, false,
3171 RTLIB::UREM_I16, RTLIB::UREM_I32,
3172 RTLIB::UREM_I64, RTLIB::UREM_I128);
3173 Results.push_back(Tmp1);
3178 bool isSigned = Node->getOpcode() == ISD::SDIV;
3179 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3180 EVT VT = Node->getValueType(0);
3181 SDVTList VTs = DAG.getVTList(VT, VT);
3182 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3183 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3184 useDivRem(Node, isSigned, true)))
3185 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
3186 Node->getOperand(1));
3188 Tmp1 = ExpandIntLibCall(Node, true,
3190 RTLIB::SDIV_I16, RTLIB::SDIV_I32,
3191 RTLIB::SDIV_I64, RTLIB::SDIV_I128);
3193 Tmp1 = ExpandIntLibCall(Node, false,
3195 RTLIB::UDIV_I16, RTLIB::UDIV_I32,
3196 RTLIB::UDIV_I64, RTLIB::UDIV_I128);
3197 Results.push_back(Tmp1);
3202 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
3204 EVT VT = Node->getValueType(0);
3205 SDVTList VTs = DAG.getVTList(VT, VT);
3206 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
3207 "If this wasn't legal, it shouldn't have been created!");
3208 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
3209 Node->getOperand(1));
3210 Results.push_back(Tmp1.getValue(1));
3215 // Expand into divrem libcall
3216 ExpandDivRemLibCall(Node, Results);
3219 EVT VT = Node->getValueType(0);
3220 SDVTList VTs = DAG.getVTList(VT, VT);
3221 // See if multiply or divide can be lowered using two-result operations.
3222 // We just need the low half of the multiply; try both the signed
3223 // and unsigned forms. If the target supports both SMUL_LOHI and
3224 // UMUL_LOHI, form a preference by checking which forms of plain
3225 // MULH it supports.
3226 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3227 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3228 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3229 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3230 unsigned OpToUse = 0;
3231 if (HasSMUL_LOHI && !HasMULHS) {
3232 OpToUse = ISD::SMUL_LOHI;
3233 } else if (HasUMUL_LOHI && !HasMULHU) {
3234 OpToUse = ISD::UMUL_LOHI;
3235 } else if (HasSMUL_LOHI) {
3236 OpToUse = ISD::SMUL_LOHI;
3237 } else if (HasUMUL_LOHI) {
3238 OpToUse = ISD::UMUL_LOHI;
3241 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
3242 Node->getOperand(1)));
3245 Tmp1 = ExpandIntLibCall(Node, false,
3247 RTLIB::MUL_I16, RTLIB::MUL_I32,
3248 RTLIB::MUL_I64, RTLIB::MUL_I128);
3249 Results.push_back(Tmp1);
3254 SDValue LHS = Node->getOperand(0);
3255 SDValue RHS = Node->getOperand(1);
3256 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3257 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3259 Results.push_back(Sum);
3260 EVT OType = Node->getValueType(1);
3262 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
3264 // LHSSign -> LHS >= 0
3265 // RHSSign -> RHS >= 0
3266 // SumSign -> Sum >= 0
3269 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3271 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3273 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3274 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3275 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
3276 Node->getOpcode() == ISD::SADDO ?
3277 ISD::SETEQ : ISD::SETNE);
3279 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3280 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3282 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3283 Results.push_back(Cmp);
3288 SDValue LHS = Node->getOperand(0);
3289 SDValue RHS = Node->getOperand(1);
3290 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
3291 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3293 Results.push_back(Sum);
3294 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS,
3295 Node->getOpcode () == ISD::UADDO ?
3296 ISD::SETULT : ISD::SETUGT));
3301 EVT VT = Node->getValueType(0);
3302 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
3303 SDValue LHS = Node->getOperand(0);
3304 SDValue RHS = Node->getOperand(1);
3307 static const unsigned Ops[2][3] =
3308 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
3309 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
3310 bool isSigned = Node->getOpcode() == ISD::SMULO;
3311 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3312 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3313 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3314 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3315 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3317 TopHalf = BottomHalf.getValue(1);
3318 } else if (TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(),
3319 VT.getSizeInBits() * 2))) {
3320 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
3321 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
3322 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
3323 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3324 DAG.getIntPtrConstant(0));
3325 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3326 DAG.getIntPtrConstant(1));
3328 // We can fall back to a libcall with an illegal type for the MUL if we
3329 // have a libcall big enough.
3330 // Also, we can fall back to a division in some cases, but that's a big
3331 // performance hit in the general case.
3332 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3333 if (WideVT == MVT::i16)
3334 LC = RTLIB::MUL_I16;
3335 else if (WideVT == MVT::i32)
3336 LC = RTLIB::MUL_I32;
3337 else if (WideVT == MVT::i64)
3338 LC = RTLIB::MUL_I64;
3339 else if (WideVT == MVT::i128)
3340 LC = RTLIB::MUL_I128;
3341 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!");
3343 // The high part is obtained by SRA'ing all but one of the bits of low
3345 unsigned LoSize = VT.getSizeInBits();
3346 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, RHS,
3347 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
3348 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, VT, LHS,
3349 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
3351 // Here we're passing the 2 arguments explicitly as 4 arguments that are
3352 // pre-lowered to the correct types. This all depends upon WideVT not
3353 // being a legal type for the architecture and thus has to be split to
3355 SDValue Args[] = { LHS, HiLHS, RHS, HiRHS };
3356 SDValue Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl);
3357 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3358 DAG.getIntPtrConstant(0));
3359 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3360 DAG.getIntPtrConstant(1));
3361 // Ret is a node with an illegal type. Because such things are not
3362 // generally permitted during this phase of legalization, delete the
3363 // node. The above EXTRACT_ELEMENT nodes should have been folded.
3364 DAG.DeleteNode(Ret.getNode());
3368 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1,
3369 TLI.getShiftAmountTy(BottomHalf.getValueType()));
3370 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3371 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1,
3374 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf,
3375 DAG.getConstant(0, VT), ISD::SETNE);
3377 Results.push_back(BottomHalf);
3378 Results.push_back(TopHalf);
3381 case ISD::BUILD_PAIR: {
3382 EVT PairTy = Node->getValueType(0);
3383 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3384 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3385 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
3386 DAG.getConstant(PairTy.getSizeInBits()/2,
3387 TLI.getShiftAmountTy(PairTy)));
3388 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3392 Tmp1 = Node->getOperand(0);
3393 Tmp2 = Node->getOperand(1);
3394 Tmp3 = Node->getOperand(2);
3395 if (Tmp1.getOpcode() == ISD::SETCC) {
3396 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3398 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3400 Tmp1 = DAG.getSelectCC(dl, Tmp1,
3401 DAG.getConstant(0, Tmp1.getValueType()),
3402 Tmp2, Tmp3, ISD::SETNE);
3404 Results.push_back(Tmp1);
3407 SDValue Chain = Node->getOperand(0);
3408 SDValue Table = Node->getOperand(1);
3409 SDValue Index = Node->getOperand(2);
3411 EVT PTy = TLI.getPointerTy();
3413 const DataLayout &TD = *TLI.getDataLayout();
3414 unsigned EntrySize =
3415 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
3417 Index = DAG.getNode(ISD::MUL, dl, PTy,
3418 Index, DAG.getConstant(EntrySize, PTy));
3419 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
3421 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
3422 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
3423 MachinePointerInfo::getJumpTable(), MemVT,
3426 if (TM.getRelocationModel() == Reloc::PIC_) {
3427 // For PIC, the sequence is:
3428 // BRIND(load(Jumptable + index) + RelocBase)
3429 // RelocBase can be JumpTable, GOT or some sort of global base.
3430 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3431 TLI.getPICJumpTableRelocBase(Table, DAG));
3433 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
3434 Results.push_back(Tmp1);
3438 // Expand brcond's setcc into its constituent parts and create a BR_CC
3440 Tmp1 = Node->getOperand(0);
3441 Tmp2 = Node->getOperand(1);
3442 if (Tmp2.getOpcode() == ISD::SETCC) {
3443 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3444 Tmp1, Tmp2.getOperand(2),
3445 Tmp2.getOperand(0), Tmp2.getOperand(1),
3446 Node->getOperand(2));
3448 // We test only the i1 bit. Skip the AND if UNDEF.
3449 Tmp3 = (Tmp2.getOpcode() == ISD::UNDEF) ? Tmp2 :
3450 DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2,
3451 DAG.getConstant(1, Tmp2.getValueType()));
3452 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3453 DAG.getCondCode(ISD::SETNE), Tmp3,
3454 DAG.getConstant(0, Tmp3.getValueType()),
3455 Node->getOperand(2));
3457 Results.push_back(Tmp1);
3460 Tmp1 = Node->getOperand(0);
3461 Tmp2 = Node->getOperand(1);
3462 Tmp3 = Node->getOperand(2);
3463 LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl);
3465 // If we expanded the SETCC into an AND/OR, return the new node
3466 if (Tmp2.getNode() == 0) {
3467 Results.push_back(Tmp1);
3471 // Otherwise, SETCC for the given comparison type must be completely
3472 // illegal; expand it into a SELECT_CC.
3473 EVT VT = Node->getValueType(0);
3474 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3475 DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3);
3476 Results.push_back(Tmp1);
3479 case ISD::SELECT_CC: {
3480 Tmp1 = Node->getOperand(0); // LHS
3481 Tmp2 = Node->getOperand(1); // RHS
3482 Tmp3 = Node->getOperand(2); // True
3483 Tmp4 = Node->getOperand(3); // False
3484 SDValue CC = Node->getOperand(4);
3486 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()),
3487 Tmp1, Tmp2, CC, dl);
3489 assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!");
3490 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3491 CC = DAG.getCondCode(ISD::SETNE);
3492 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2,
3494 Results.push_back(Tmp1);
3498 Tmp1 = Node->getOperand(0); // Chain
3499 Tmp2 = Node->getOperand(2); // LHS
3500 Tmp3 = Node->getOperand(3); // RHS
3501 Tmp4 = Node->getOperand(1); // CC
3503 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()),
3504 Tmp2, Tmp3, Tmp4, dl);
3506 assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!");
3507 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
3508 Tmp4 = DAG.getCondCode(ISD::SETNE);
3509 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2,
3510 Tmp3, Node->getOperand(4));
3511 Results.push_back(Tmp1);
3514 case ISD::BUILD_VECTOR:
3515 Results.push_back(ExpandBUILD_VECTOR(Node));
3520 // Scalarize vector SRA/SRL/SHL.
3521 EVT VT = Node->getValueType(0);
3522 assert(VT.isVector() && "Unable to legalize non-vector shift");
3523 assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
3524 unsigned NumElem = VT.getVectorNumElements();
3526 SmallVector<SDValue, 8> Scalars;
3527 for (unsigned Idx = 0; Idx < NumElem; Idx++) {
3528 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3530 Node->getOperand(0), DAG.getIntPtrConstant(Idx));
3531 SDValue Sh = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3533 Node->getOperand(1), DAG.getIntPtrConstant(Idx));
3534 Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
3535 VT.getScalarType(), Ex, Sh));
3538 DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0),
3539 &Scalars[0], Scalars.size());
3540 ReplaceNode(SDValue(Node, 0), Result);
3543 case ISD::GLOBAL_OFFSET_TABLE:
3544 case ISD::GlobalAddress:
3545 case ISD::GlobalTLSAddress:
3546 case ISD::ExternalSymbol:
3547 case ISD::ConstantPool:
3548 case ISD::JumpTable:
3549 case ISD::INTRINSIC_W_CHAIN:
3550 case ISD::INTRINSIC_WO_CHAIN:
3551 case ISD::INTRINSIC_VOID:
3552 // FIXME: Custom lowering for these operations shouldn't return null!
3556 // Replace the original node with the legalized result.
3557 if (!Results.empty())
3558 ReplaceNode(Node, Results.data());
3561 void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
3562 SmallVector<SDValue, 8> Results;
3563 EVT OVT = Node->getValueType(0);
3564 if (Node->getOpcode() == ISD::UINT_TO_FP ||
3565 Node->getOpcode() == ISD::SINT_TO_FP ||
3566 Node->getOpcode() == ISD::SETCC) {
3567 OVT = Node->getOperand(0).getValueType();
3569 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3570 DebugLoc dl = Node->getDebugLoc();
3571 SDValue Tmp1, Tmp2, Tmp3;
3572 switch (Node->getOpcode()) {
3574 case ISD::CTTZ_ZERO_UNDEF:
3576 case ISD::CTLZ_ZERO_UNDEF:
3578 // Zero extend the argument.
3579 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3580 // Perform the larger operation. For CTPOP and CTTZ_ZERO_UNDEF, this is
3581 // already the correct result.
3582 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
3583 if (Node->getOpcode() == ISD::CTTZ) {
3584 // FIXME: This should set a bit in the zero extended value instead.
3585 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
3586 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
3588 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
3589 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3590 } else if (Node->getOpcode() == ISD::CTLZ ||
3591 Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) {
3592 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3593 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
3594 DAG.getConstant(NVT.getSizeInBits() -
3595 OVT.getSizeInBits(), NVT));
3597 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
3600 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3601 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3602 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
3603 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
3604 DAG.getConstant(DiffBits, TLI.getShiftAmountTy(NVT)));
3605 Results.push_back(Tmp1);
3608 case ISD::FP_TO_UINT:
3609 case ISD::FP_TO_SINT:
3610 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
3611 Node->getOpcode() == ISD::FP_TO_SINT, dl);
3612 Results.push_back(Tmp1);
3614 case ISD::UINT_TO_FP:
3615 case ISD::SINT_TO_FP:
3616 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
3617 Node->getOpcode() == ISD::SINT_TO_FP, dl);
3618 Results.push_back(Tmp1);
3621 SDValue Chain = Node->getOperand(0); // Get the chain.
3622 SDValue Ptr = Node->getOperand(1); // Get the pointer.
3625 if (OVT.isVector()) {
3626 TruncOp = ISD::BITCAST;
3628 assert(OVT.isInteger()
3629 && "VAARG promotion is supported only for vectors or integer types");
3630 TruncOp = ISD::TRUNCATE;
3633 // Perform the larger operation, then convert back
3634 Tmp1 = DAG.getVAArg(NVT, dl, Chain, Ptr, Node->getOperand(2),
3635 Node->getConstantOperandVal(3));
3636 Chain = Tmp1.getValue(1);
3638 Tmp2 = DAG.getNode(TruncOp, dl, OVT, Tmp1);
3640 // Modified the chain result - switch anything that used the old chain to
3642 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp2);
3643 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
3650 unsigned ExtOp, TruncOp;
3651 if (OVT.isVector()) {
3652 ExtOp = ISD::BITCAST;
3653 TruncOp = ISD::BITCAST;
3655 assert(OVT.isInteger() && "Cannot promote logic operation");
3656 ExtOp = ISD::ANY_EXTEND;
3657 TruncOp = ISD::TRUNCATE;
3659 // Promote each of the values to the new type.
3660 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3661 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3662 // Perform the larger operation, then convert back
3663 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3664 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
3668 unsigned ExtOp, TruncOp;
3669 if (Node->getValueType(0).isVector()) {
3670 ExtOp = ISD::BITCAST;
3671 TruncOp = ISD::BITCAST;
3672 } else if (Node->getValueType(0).isInteger()) {
3673 ExtOp = ISD::ANY_EXTEND;
3674 TruncOp = ISD::TRUNCATE;
3676 ExtOp = ISD::FP_EXTEND;
3677 TruncOp = ISD::FP_ROUND;
3679 Tmp1 = Node->getOperand(0);
3680 // Promote each of the values to the new type.
3681 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3682 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
3683 // Perform the larger operation, then round down.
3684 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3);
3685 if (TruncOp != ISD::FP_ROUND)
3686 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
3688 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
3689 DAG.getIntPtrConstant(0));
3690 Results.push_back(Tmp1);
3693 case ISD::VECTOR_SHUFFLE: {
3694 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
3696 // Cast the two input vectors.
3697 Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
3698 Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
3700 // Convert the shuffle mask to the right # elements.
3701 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
3702 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
3703 Results.push_back(Tmp1);
3707 unsigned ExtOp = ISD::FP_EXTEND;
3708 if (NVT.isInteger()) {
3709 ISD::CondCode CCCode =
3710 cast<CondCodeSDNode>(Node->getOperand(2))->get();
3711 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3713 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3714 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3715 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3716 Tmp1, Tmp2, Node->getOperand(2)));
3722 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
3723 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
3724 Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3725 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
3726 Tmp3, DAG.getIntPtrConstant(0)));
3733 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
3734 Tmp2 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
3735 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
3736 Tmp2, DAG.getIntPtrConstant(0)));
3741 // Replace the original node with the legalized result.
3742 if (!Results.empty())
3743 ReplaceNode(Node, Results.data());
3746 // SelectionDAG::Legalize - This is the entry point for the file.
3748 void SelectionDAG::Legalize() {
3749 /// run - This is the main entry point to this class.
3751 SelectionDAGLegalize(*this).LegalizeDAG();