1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/ADT/SmallPtrSet.h"
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/ADT/Triple.h"
18 #include "llvm/CodeGen/Analysis.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineJumpTableInfo.h"
21 #include "llvm/DebugInfo.h"
22 #include "llvm/IR/CallingConv.h"
23 #include "llvm/IR/Constants.h"
24 #include "llvm/IR/DataLayout.h"
25 #include "llvm/IR/DerivedTypes.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/IR/LLVMContext.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/MathExtras.h"
31 #include "llvm/Support/raw_ostream.h"
32 #include "llvm/Target/TargetFrameLowering.h"
33 #include "llvm/Target/TargetLowering.h"
34 #include "llvm/Target/TargetMachine.h"
37 //===----------------------------------------------------------------------===//
38 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
39 /// hacks on it until the target machine can handle it. This involves
40 /// eliminating value sizes the machine cannot handle (promoting small sizes to
41 /// large sizes or splitting up large values into small values) as well as
42 /// eliminating operations the machine cannot handle.
44 /// This code also does a small amount of optimization and recognition of idioms
45 /// as part of its processing. For example, if a target does not support a
46 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
47 /// will attempt merge setcc and brc instructions into brcc's.
50 class SelectionDAGLegalize : public SelectionDAG::DAGUpdateListener {
51 const TargetMachine &TM;
52 const TargetLowering &TLI;
55 /// LegalizePosition - The iterator for walking through the node list.
56 SelectionDAG::allnodes_iterator LegalizePosition;
58 /// LegalizedNodes - The set of nodes which have already been legalized.
59 SmallPtrSet<SDNode *, 16> LegalizedNodes;
61 EVT getSetCCResultType(EVT VT) const {
62 return TLI.getSetCCResultType(*DAG.getContext(), VT);
65 // Libcall insertion helpers.
68 explicit SelectionDAGLegalize(SelectionDAG &DAG);
73 /// LegalizeOp - Legalizes the given operation.
74 void LegalizeOp(SDNode *Node);
76 SDValue OptimizeFloatStore(StoreSDNode *ST);
78 void LegalizeLoadOps(SDNode *Node);
79 void LegalizeStoreOps(SDNode *Node);
81 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
82 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
83 /// is necessary to spill the vector being inserted into to memory, perform
84 /// the insert there, and then read the result back.
85 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
86 SDValue Idx, SDLoc dl);
87 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
88 SDValue Idx, SDLoc dl);
90 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
91 /// performs the same shuffe in terms of order or result bytes, but on a type
92 /// whose vector element type is narrower than the original shuffle type.
93 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
94 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl,
95 SDValue N1, SDValue N2,
96 ArrayRef<int> Mask) const;
98 bool LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
101 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
102 SDValue ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops,
103 unsigned NumOps, bool isSigned, SDLoc dl);
105 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
106 SDNode *Node, bool isSigned);
107 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
108 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
109 RTLIB::Libcall Call_F128,
110 RTLIB::Libcall Call_PPCF128);
111 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
112 RTLIB::Libcall Call_I8,
113 RTLIB::Libcall Call_I16,
114 RTLIB::Libcall Call_I32,
115 RTLIB::Libcall Call_I64,
116 RTLIB::Libcall Call_I128);
117 void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
118 void ExpandSinCosLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
120 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, SDLoc dl);
121 SDValue ExpandBUILD_VECTOR(SDNode *Node);
122 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
123 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
124 SmallVectorImpl<SDValue> &Results);
125 SDValue ExpandFCOPYSIGN(SDNode *Node);
126 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
128 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
130 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
133 SDValue ExpandBSWAP(SDValue Op, SDLoc dl);
134 SDValue ExpandBitCount(unsigned Opc, SDValue Op, SDLoc dl);
136 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
137 SDValue ExpandInsertToVectorThroughStack(SDValue Op);
138 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
140 SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP);
142 std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node);
144 void ExpandNode(SDNode *Node);
145 void PromoteNode(SDNode *Node);
147 void ForgetNode(SDNode *N) {
148 LegalizedNodes.erase(N);
149 if (LegalizePosition == SelectionDAG::allnodes_iterator(N))
154 // DAGUpdateListener implementation.
155 virtual void NodeDeleted(SDNode *N, SDNode *E) {
158 virtual void NodeUpdated(SDNode *N) {}
160 // Node replacement helpers
161 void ReplacedNode(SDNode *N) {
162 if (N->use_empty()) {
163 DAG.RemoveDeadNode(N);
168 void ReplaceNode(SDNode *Old, SDNode *New) {
169 DAG.ReplaceAllUsesWith(Old, New);
172 void ReplaceNode(SDValue Old, SDValue New) {
173 DAG.ReplaceAllUsesWith(Old, New);
174 ReplacedNode(Old.getNode());
176 void ReplaceNode(SDNode *Old, const SDValue *New) {
177 DAG.ReplaceAllUsesWith(Old, New);
183 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
184 /// performs the same shuffe in terms of order or result bytes, but on a type
185 /// whose vector element type is narrower than the original shuffle type.
186 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
188 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl,
189 SDValue N1, SDValue N2,
190 ArrayRef<int> Mask) const {
191 unsigned NumMaskElts = VT.getVectorNumElements();
192 unsigned NumDestElts = NVT.getVectorNumElements();
193 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
195 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
197 if (NumEltsGrowth == 1)
198 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
200 SmallVector<int, 8> NewMask;
201 for (unsigned i = 0; i != NumMaskElts; ++i) {
203 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
205 NewMask.push_back(-1);
207 NewMask.push_back(Idx * NumEltsGrowth + j);
210 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
211 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
212 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
215 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
216 : SelectionDAG::DAGUpdateListener(dag),
217 TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()),
221 void SelectionDAGLegalize::LegalizeDAG() {
222 DAG.AssignTopologicalOrder();
224 // Visit all the nodes. We start in topological order, so that we see
225 // nodes with their original operands intact. Legalization can produce
226 // new nodes which may themselves need to be legalized. Iterate until all
227 // nodes have been legalized.
229 bool AnyLegalized = false;
230 for (LegalizePosition = DAG.allnodes_end();
231 LegalizePosition != DAG.allnodes_begin(); ) {
234 SDNode *N = LegalizePosition;
235 if (LegalizedNodes.insert(N)) {
245 // Remove dead nodes now.
246 DAG.RemoveDeadNodes();
249 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
250 /// a load from the constant pool.
252 SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) {
256 // If a FP immediate is precise when represented as a float and if the
257 // target can do an extending load from float to double, we put it into
258 // the constant pool as a float, even if it's is statically typed as a
259 // double. This shrinks FP constants and canonicalizes them for targets where
260 // an FP extending load is the same cost as a normal load (such as on the x87
261 // fp stack or PPC FP unit).
262 EVT VT = CFP->getValueType(0);
263 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
265 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
266 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
267 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
272 while (SVT != MVT::f32) {
273 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
274 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) &&
275 // Only do this if the target has a native EXTLOAD instruction from
277 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
278 TLI.ShouldShrinkFPConstant(OrigVT)) {
279 Type *SType = SVT.getTypeForEVT(*DAG.getContext());
280 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
286 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
287 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
290 DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT,
292 CPIdx, MachinePointerInfo::getConstantPool(),
293 VT, false, false, Alignment);
297 DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
298 MachinePointerInfo::getConstantPool(), false, false, false,
303 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
304 static void ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
305 const TargetLowering &TLI,
306 SelectionDAGLegalize *DAGLegalize) {
307 assert(ST->getAddressingMode() == ISD::UNINDEXED &&
308 "unaligned indexed stores not implemented!");
309 SDValue Chain = ST->getChain();
310 SDValue Ptr = ST->getBasePtr();
311 SDValue Val = ST->getValue();
312 EVT VT = Val.getValueType();
313 int Alignment = ST->getAlignment();
315 if (ST->getMemoryVT().isFloatingPoint() ||
316 ST->getMemoryVT().isVector()) {
317 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
318 if (TLI.isTypeLegal(intVT)) {
319 // Expand to a bitconvert of the value to the integer type of the
320 // same size, then a (misaligned) int store.
321 // FIXME: Does not handle truncating floating point stores!
322 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
323 Result = DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
324 ST->isVolatile(), ST->isNonTemporal(), Alignment);
325 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
328 // Do a (aligned) store to a stack slot, then copy from the stack slot
329 // to the final destination using (unaligned) integer loads and stores.
330 EVT StoredVT = ST->getMemoryVT();
332 TLI.getRegisterType(*DAG.getContext(),
333 EVT::getIntegerVT(*DAG.getContext(),
334 StoredVT.getSizeInBits()));
335 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
336 unsigned RegBytes = RegVT.getSizeInBits() / 8;
337 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
339 // Make sure the stack slot is also aligned for the register type.
340 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
342 // Perform the original store, only redirected to the stack slot.
343 SDValue Store = DAG.getTruncStore(Chain, dl,
344 Val, StackPtr, MachinePointerInfo(),
345 StoredVT, false, false, 0);
346 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
347 SmallVector<SDValue, 8> Stores;
350 // Do all but one copies using the full register width.
351 for (unsigned i = 1; i < NumRegs; i++) {
352 // Load one integer register's worth from the stack slot.
353 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr,
354 MachinePointerInfo(),
355 false, false, false, 0);
356 // Store it to the final location. Remember the store.
357 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
358 ST->getPointerInfo().getWithOffset(Offset),
359 ST->isVolatile(), ST->isNonTemporal(),
360 MinAlign(ST->getAlignment(), Offset)));
361 // Increment the pointers.
363 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
365 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
368 // The last store may be partial. Do a truncating store. On big-endian
369 // machines this requires an extending load from the stack slot to ensure
370 // that the bits are in the right place.
371 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
372 8 * (StoredBytes - Offset));
374 // Load from the stack slot.
375 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
376 MachinePointerInfo(),
377 MemVT, false, false, 0);
379 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
381 .getWithOffset(Offset),
382 MemVT, ST->isVolatile(),
384 MinAlign(ST->getAlignment(), Offset),
386 // The order of the stores doesn't matter - say it with a TokenFactor.
388 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
390 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
393 assert(ST->getMemoryVT().isInteger() &&
394 !ST->getMemoryVT().isVector() &&
395 "Unaligned store of unknown type.");
396 // Get the half-size VT
397 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext());
398 int NumBits = NewStoredVT.getSizeInBits();
399 int IncrementSize = NumBits / 8;
401 // Divide the stored value in two parts.
402 SDValue ShiftAmount = DAG.getConstant(NumBits,
403 TLI.getShiftAmountTy(Val.getValueType()));
405 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
407 // Store the two parts
408 SDValue Store1, Store2;
409 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
410 ST->getPointerInfo(), NewStoredVT,
411 ST->isVolatile(), ST->isNonTemporal(), Alignment);
412 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
413 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
414 Alignment = MinAlign(Alignment, IncrementSize);
415 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
416 ST->getPointerInfo().getWithOffset(IncrementSize),
417 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(),
418 Alignment, ST->getTBAAInfo());
421 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
422 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
425 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
427 ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
428 const TargetLowering &TLI,
429 SDValue &ValResult, SDValue &ChainResult) {
430 assert(LD->getAddressingMode() == ISD::UNINDEXED &&
431 "unaligned indexed loads not implemented!");
432 SDValue Chain = LD->getChain();
433 SDValue Ptr = LD->getBasePtr();
434 EVT VT = LD->getValueType(0);
435 EVT LoadedVT = LD->getMemoryVT();
437 if (VT.isFloatingPoint() || VT.isVector()) {
438 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
439 if (TLI.isTypeLegal(intVT) && TLI.isTypeLegal(LoadedVT)) {
440 // Expand to a (misaligned) integer load of the same size,
441 // then bitconvert to floating point or vector.
442 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr,
443 LD->getMemOperand());
444 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad);
446 Result = DAG.getNode(VT.isFloatingPoint() ? ISD::FP_EXTEND :
447 ISD::ANY_EXTEND, dl, VT, Result);
454 // Copy the value to a (aligned) stack slot using (unaligned) integer
455 // loads and stores, then do a (aligned) load from the stack slot.
456 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
457 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
458 unsigned RegBytes = RegVT.getSizeInBits() / 8;
459 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
461 // Make sure the stack slot is also aligned for the register type.
462 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
464 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
465 SmallVector<SDValue, 8> Stores;
466 SDValue StackPtr = StackBase;
469 // Do all but one copies using the full register width.
470 for (unsigned i = 1; i < NumRegs; i++) {
471 // Load one integer register's worth from the original location.
472 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr,
473 LD->getPointerInfo().getWithOffset(Offset),
474 LD->isVolatile(), LD->isNonTemporal(),
476 MinAlign(LD->getAlignment(), Offset),
478 // Follow the load with a store to the stack slot. Remember the store.
479 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
480 MachinePointerInfo(), false, false, 0));
481 // Increment the pointers.
483 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
484 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
488 // The last copy may be partial. Do an extending load.
489 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
490 8 * (LoadedBytes - Offset));
491 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
492 LD->getPointerInfo().getWithOffset(Offset),
493 MemVT, LD->isVolatile(),
495 MinAlign(LD->getAlignment(), Offset),
497 // Follow the load with a store to the stack slot. Remember the store.
498 // On big-endian machines this requires a truncating store to ensure
499 // that the bits end up in the right place.
500 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
501 MachinePointerInfo(), MemVT,
504 // The order of the stores doesn't matter - say it with a TokenFactor.
505 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
508 // Finally, perform the original load only redirected to the stack slot.
509 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
510 MachinePointerInfo(), LoadedVT, false, false, 0);
512 // Callers expect a MERGE_VALUES node.
517 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
518 "Unaligned load of unsupported type.");
520 // Compute the new VT that is half the size of the old one. This is an
522 unsigned NumBits = LoadedVT.getSizeInBits();
524 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
527 unsigned Alignment = LD->getAlignment();
528 unsigned IncrementSize = NumBits / 8;
529 ISD::LoadExtType HiExtType = LD->getExtensionType();
531 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
532 if (HiExtType == ISD::NON_EXTLOAD)
533 HiExtType = ISD::ZEXTLOAD;
535 // Load the value in two parts
537 if (TLI.isLittleEndian()) {
538 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
539 NewLoadedVT, LD->isVolatile(),
540 LD->isNonTemporal(), Alignment, LD->getTBAAInfo());
541 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
542 DAG.getConstant(IncrementSize, Ptr.getValueType()));
543 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr,
544 LD->getPointerInfo().getWithOffset(IncrementSize),
545 NewLoadedVT, LD->isVolatile(),
546 LD->isNonTemporal(), MinAlign(Alignment, IncrementSize),
549 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(),
550 NewLoadedVT, LD->isVolatile(),
551 LD->isNonTemporal(), Alignment, LD->getTBAAInfo());
552 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
553 DAG.getConstant(IncrementSize, Ptr.getValueType()));
554 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
555 LD->getPointerInfo().getWithOffset(IncrementSize),
556 NewLoadedVT, LD->isVolatile(),
557 LD->isNonTemporal(), MinAlign(Alignment, IncrementSize),
561 // aggregate the two parts
562 SDValue ShiftAmount = DAG.getConstant(NumBits,
563 TLI.getShiftAmountTy(Hi.getValueType()));
564 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
565 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
567 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
574 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
575 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
576 /// is necessary to spill the vector being inserted into to memory, perform
577 /// the insert there, and then read the result back.
578 SDValue SelectionDAGLegalize::
579 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
585 // If the target doesn't support this, we have to spill the input vector
586 // to a temporary stack slot, update the element, then reload it. This is
587 // badness. We could also load the value into a vector register (either
588 // with a "move to register" or "extload into register" instruction, then
589 // permute it into place, if the idx is a constant and if the idx is
590 // supported by the target.
591 EVT VT = Tmp1.getValueType();
592 EVT EltVT = VT.getVectorElementType();
593 EVT IdxVT = Tmp3.getValueType();
594 EVT PtrVT = TLI.getPointerTy();
595 SDValue StackPtr = DAG.CreateStackTemporary(VT);
597 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
600 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
601 MachinePointerInfo::getFixedStack(SPFI),
604 // Truncate or zero extend offset to target pointer type.
605 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
606 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
607 // Add the offset to the index.
608 unsigned EltSize = EltVT.getSizeInBits()/8;
609 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
610 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
611 // Store the scalar value.
612 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT,
614 // Load the updated vector.
615 return DAG.getLoad(VT, dl, Ch, StackPtr,
616 MachinePointerInfo::getFixedStack(SPFI), false, false,
621 SDValue SelectionDAGLegalize::
622 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, SDLoc dl) {
623 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
624 // SCALAR_TO_VECTOR requires that the type of the value being inserted
625 // match the element type of the vector being created, except for
626 // integers in which case the inserted value can be over width.
627 EVT EltVT = Vec.getValueType().getVectorElementType();
628 if (Val.getValueType() == EltVT ||
629 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
630 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
631 Vec.getValueType(), Val);
633 unsigned NumElts = Vec.getValueType().getVectorNumElements();
634 // We generate a shuffle of InVec and ScVec, so the shuffle mask
635 // should be 0,1,2,3,4,5... with the appropriate element replaced with
637 SmallVector<int, 8> ShufOps;
638 for (unsigned i = 0; i != NumElts; ++i)
639 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
641 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
645 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
648 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
649 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
650 // FIXME: We shouldn't do this for TargetConstantFP's.
651 // FIXME: move this to the DAG Combiner! Note that we can't regress due
652 // to phase ordering between legalized code and the dag combiner. This
653 // probably means that we need to integrate dag combiner and legalizer
655 // We generally can't do this one for long doubles.
656 SDValue Chain = ST->getChain();
657 SDValue Ptr = ST->getBasePtr();
658 unsigned Alignment = ST->getAlignment();
659 bool isVolatile = ST->isVolatile();
660 bool isNonTemporal = ST->isNonTemporal();
661 const MDNode *TBAAInfo = ST->getTBAAInfo();
663 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
664 if (CFP->getValueType(0) == MVT::f32 &&
665 TLI.isTypeLegal(MVT::i32)) {
666 SDValue Con = DAG.getConstant(CFP->getValueAPF().
667 bitcastToAPInt().zextOrTrunc(32),
669 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
670 isVolatile, isNonTemporal, Alignment, TBAAInfo);
673 if (CFP->getValueType(0) == MVT::f64) {
674 // If this target supports 64-bit registers, do a single 64-bit store.
675 if (TLI.isTypeLegal(MVT::i64)) {
676 SDValue Con = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
677 zextOrTrunc(64), MVT::i64);
678 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
679 isVolatile, isNonTemporal, Alignment, TBAAInfo);
682 if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) {
683 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
684 // stores. If the target supports neither 32- nor 64-bits, this
685 // xform is certainly not worth it.
686 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
687 SDValue Lo = DAG.getConstant(IntVal.trunc(32), MVT::i32);
688 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
689 if (TLI.isBigEndian()) std::swap(Lo, Hi);
691 Lo = DAG.getStore(Chain, dl, Lo, Ptr, ST->getPointerInfo(), isVolatile,
692 isNonTemporal, Alignment, TBAAInfo);
693 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
694 DAG.getConstant(4, Ptr.getValueType()));
695 Hi = DAG.getStore(Chain, dl, Hi, Ptr,
696 ST->getPointerInfo().getWithOffset(4),
697 isVolatile, isNonTemporal, MinAlign(Alignment, 4U),
700 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
704 return SDValue(0, 0);
707 void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
708 StoreSDNode *ST = cast<StoreSDNode>(Node);
709 SDValue Chain = ST->getChain();
710 SDValue Ptr = ST->getBasePtr();
713 unsigned Alignment = ST->getAlignment();
714 bool isVolatile = ST->isVolatile();
715 bool isNonTemporal = ST->isNonTemporal();
716 const MDNode *TBAAInfo = ST->getTBAAInfo();
718 if (!ST->isTruncatingStore()) {
719 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
720 ReplaceNode(ST, OptStore);
725 SDValue Value = ST->getValue();
726 MVT VT = Value.getSimpleValueType();
727 switch (TLI.getOperationAction(ISD::STORE, VT)) {
728 default: llvm_unreachable("This action is not supported yet!");
729 case TargetLowering::Legal:
730 // If this is an unaligned store and the target doesn't support it,
732 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
733 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
734 unsigned ABIAlignment= TLI.getDataLayout()->getABITypeAlignment(Ty);
735 if (ST->getAlignment() < ABIAlignment)
736 ExpandUnalignedStore(cast<StoreSDNode>(Node),
740 case TargetLowering::Custom: {
741 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
743 ReplaceNode(SDValue(Node, 0), Res);
746 case TargetLowering::Promote: {
747 MVT NVT = TLI.getTypeToPromoteTo(ISD::STORE, VT);
748 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
749 "Can only promote stores to same size type");
750 Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value);
752 DAG.getStore(Chain, dl, Value, Ptr,
753 ST->getPointerInfo(), isVolatile,
754 isNonTemporal, Alignment, TBAAInfo);
755 ReplaceNode(SDValue(Node, 0), Result);
762 SDValue Value = ST->getValue();
764 EVT StVT = ST->getMemoryVT();
765 unsigned StWidth = StVT.getSizeInBits();
767 if (StWidth != StVT.getStoreSizeInBits()) {
768 // Promote to a byte-sized store with upper bits zero if not
769 // storing an integral number of bytes. For example, promote
770 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
771 EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
772 StVT.getStoreSizeInBits());
773 Value = DAG.getZeroExtendInReg(Value, dl, StVT);
775 DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
776 NVT, isVolatile, isNonTemporal, Alignment,
778 ReplaceNode(SDValue(Node, 0), Result);
779 } else if (StWidth & (StWidth - 1)) {
780 // If not storing a power-of-2 number of bits, expand as two stores.
781 assert(!StVT.isVector() && "Unsupported truncstore!");
782 unsigned RoundWidth = 1 << Log2_32(StWidth);
783 assert(RoundWidth < StWidth);
784 unsigned ExtraWidth = StWidth - RoundWidth;
785 assert(ExtraWidth < RoundWidth);
786 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
787 "Store size not an integral number of bytes!");
788 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
789 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
791 unsigned IncrementSize;
793 if (TLI.isLittleEndian()) {
794 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
795 // Store the bottom RoundWidth bits.
796 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
798 isVolatile, isNonTemporal, Alignment,
801 // Store the remaining ExtraWidth bits.
802 IncrementSize = RoundWidth / 8;
803 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
804 DAG.getConstant(IncrementSize, Ptr.getValueType()));
805 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
806 DAG.getConstant(RoundWidth,
807 TLI.getShiftAmountTy(Value.getValueType())));
808 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr,
809 ST->getPointerInfo().getWithOffset(IncrementSize),
810 ExtraVT, isVolatile, isNonTemporal,
811 MinAlign(Alignment, IncrementSize), TBAAInfo);
813 // Big endian - avoid unaligned stores.
814 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
815 // Store the top RoundWidth bits.
816 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
817 DAG.getConstant(ExtraWidth,
818 TLI.getShiftAmountTy(Value.getValueType())));
819 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, ST->getPointerInfo(),
820 RoundVT, isVolatile, isNonTemporal, Alignment,
823 // Store the remaining ExtraWidth bits.
824 IncrementSize = RoundWidth / 8;
825 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
826 DAG.getConstant(IncrementSize, Ptr.getValueType()));
827 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr,
828 ST->getPointerInfo().getWithOffset(IncrementSize),
829 ExtraVT, isVolatile, isNonTemporal,
830 MinAlign(Alignment, IncrementSize), TBAAInfo);
833 // The order of the stores doesn't matter.
834 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
835 ReplaceNode(SDValue(Node, 0), Result);
837 switch (TLI.getTruncStoreAction(ST->getValue().getSimpleValueType(),
838 StVT.getSimpleVT())) {
839 default: llvm_unreachable("This action is not supported yet!");
840 case TargetLowering::Legal:
841 // If this is an unaligned store and the target doesn't support it,
843 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
844 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
845 unsigned ABIAlignment= TLI.getDataLayout()->getABITypeAlignment(Ty);
846 if (ST->getAlignment() < ABIAlignment)
847 ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this);
850 case TargetLowering::Custom: {
851 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
853 ReplaceNode(SDValue(Node, 0), Res);
856 case TargetLowering::Expand:
857 assert(!StVT.isVector() &&
858 "Vector Stores are handled in LegalizeVectorOps");
860 // TRUNCSTORE:i16 i32 -> STORE i16
861 assert(TLI.isTypeLegal(StVT) &&
862 "Do not know how to expand this store!");
863 Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value);
865 DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
866 isVolatile, isNonTemporal, Alignment, TBAAInfo);
867 ReplaceNode(SDValue(Node, 0), Result);
874 void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
875 LoadSDNode *LD = cast<LoadSDNode>(Node);
876 SDValue Chain = LD->getChain(); // The chain.
877 SDValue Ptr = LD->getBasePtr(); // The base pointer.
878 SDValue Value; // The value returned by the load op.
881 ISD::LoadExtType ExtType = LD->getExtensionType();
882 if (ExtType == ISD::NON_EXTLOAD) {
883 MVT VT = Node->getSimpleValueType(0);
884 SDValue RVal = SDValue(Node, 0);
885 SDValue RChain = SDValue(Node, 1);
887 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
888 default: llvm_unreachable("This action is not supported yet!");
889 case TargetLowering::Legal:
890 // If this is an unaligned load and the target doesn't support it,
892 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
893 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
894 unsigned ABIAlignment =
895 TLI.getDataLayout()->getABITypeAlignment(Ty);
896 if (LD->getAlignment() < ABIAlignment){
897 ExpandUnalignedLoad(cast<LoadSDNode>(Node), DAG, TLI, RVal, RChain);
901 case TargetLowering::Custom: {
902 SDValue Res = TLI.LowerOperation(RVal, DAG);
905 RChain = Res.getValue(1);
909 case TargetLowering::Promote: {
910 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
911 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
912 "Can only promote loads to same size type");
914 SDValue Res = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getMemOperand());
915 RVal = DAG.getNode(ISD::BITCAST, dl, VT, Res);
916 RChain = Res.getValue(1);
920 if (RChain.getNode() != Node) {
921 assert(RVal.getNode() != Node && "Load must be completely replaced");
922 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), RVal);
923 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), RChain);
929 EVT SrcVT = LD->getMemoryVT();
930 unsigned SrcWidth = SrcVT.getSizeInBits();
931 unsigned Alignment = LD->getAlignment();
932 bool isVolatile = LD->isVolatile();
933 bool isNonTemporal = LD->isNonTemporal();
934 const MDNode *TBAAInfo = LD->getTBAAInfo();
936 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
937 // Some targets pretend to have an i1 loading operation, and actually
938 // load an i8. This trick is correct for ZEXTLOAD because the top 7
939 // bits are guaranteed to be zero; it helps the optimizers understand
940 // that these bits are zero. It is also useful for EXTLOAD, since it
941 // tells the optimizers that those bits are undefined. It would be
942 // nice to have an effective generic way of getting these benefits...
943 // Until such a way is found, don't insist on promoting i1 here.
945 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
946 // Promote to a byte-sized load if not loading an integral number of
947 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
948 unsigned NewWidth = SrcVT.getStoreSizeInBits();
949 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
952 // The extra bits are guaranteed to be zero, since we stored them that
953 // way. A zext load from NVT thus automatically gives zext from SrcVT.
955 ISD::LoadExtType NewExtType =
956 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
959 DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
960 Chain, Ptr, LD->getPointerInfo(),
961 NVT, isVolatile, isNonTemporal, Alignment, TBAAInfo);
963 Ch = Result.getValue(1); // The chain.
965 if (ExtType == ISD::SEXTLOAD)
966 // Having the top bits zero doesn't help when sign extending.
967 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
968 Result.getValueType(),
969 Result, DAG.getValueType(SrcVT));
970 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
971 // All the top bits are guaranteed to be zero - inform the optimizers.
972 Result = DAG.getNode(ISD::AssertZext, dl,
973 Result.getValueType(), Result,
974 DAG.getValueType(SrcVT));
978 } else if (SrcWidth & (SrcWidth - 1)) {
979 // If not loading a power-of-2 number of bits, expand as two loads.
980 assert(!SrcVT.isVector() && "Unsupported extload!");
981 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
982 assert(RoundWidth < SrcWidth);
983 unsigned ExtraWidth = SrcWidth - RoundWidth;
984 assert(ExtraWidth < RoundWidth);
985 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
986 "Load size not an integral number of bytes!");
987 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
988 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
990 unsigned IncrementSize;
992 if (TLI.isLittleEndian()) {
993 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
994 // Load the bottom RoundWidth bits.
995 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0),
997 LD->getPointerInfo(), RoundVT, isVolatile,
998 isNonTemporal, Alignment, TBAAInfo);
1000 // Load the remaining ExtraWidth bits.
1001 IncrementSize = RoundWidth / 8;
1002 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1003 DAG.getConstant(IncrementSize, Ptr.getValueType()));
1004 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
1005 LD->getPointerInfo().getWithOffset(IncrementSize),
1006 ExtraVT, isVolatile, isNonTemporal,
1007 MinAlign(Alignment, IncrementSize), TBAAInfo);
1009 // Build a factor node to remember that this load is independent of
1011 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1014 // Move the top bits to the right place.
1015 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1016 DAG.getConstant(RoundWidth,
1017 TLI.getShiftAmountTy(Hi.getValueType())));
1019 // Join the hi and lo parts.
1020 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1022 // Big endian - avoid unaligned loads.
1023 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1024 // Load the top RoundWidth bits.
1025 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
1026 LD->getPointerInfo(), RoundVT, isVolatile,
1027 isNonTemporal, Alignment, TBAAInfo);
1029 // Load the remaining ExtraWidth bits.
1030 IncrementSize = RoundWidth / 8;
1031 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1032 DAG.getConstant(IncrementSize, Ptr.getValueType()));
1033 Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
1034 dl, Node->getValueType(0), Chain, Ptr,
1035 LD->getPointerInfo().getWithOffset(IncrementSize),
1036 ExtraVT, isVolatile, isNonTemporal,
1037 MinAlign(Alignment, IncrementSize), TBAAInfo);
1039 // Build a factor node to remember that this load is independent of
1041 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1044 // Move the top bits to the right place.
1045 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1046 DAG.getConstant(ExtraWidth,
1047 TLI.getShiftAmountTy(Hi.getValueType())));
1049 // Join the hi and lo parts.
1050 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1055 bool isCustom = false;
1056 switch (TLI.getLoadExtAction(ExtType, SrcVT.getSimpleVT())) {
1057 default: llvm_unreachable("This action is not supported yet!");
1058 case TargetLowering::Custom:
1061 case TargetLowering::Legal: {
1062 Value = SDValue(Node, 0);
1063 Chain = SDValue(Node, 1);
1066 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1067 if (Res.getNode()) {
1069 Chain = Res.getValue(1);
1072 // If this is an unaligned load and the target doesn't support it,
1074 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
1076 LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1077 unsigned ABIAlignment =
1078 TLI.getDataLayout()->getABITypeAlignment(Ty);
1079 if (LD->getAlignment() < ABIAlignment){
1080 ExpandUnalignedLoad(cast<LoadSDNode>(Node),
1081 DAG, TLI, Value, Chain);
1087 case TargetLowering::Expand:
1088 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) && TLI.isTypeLegal(SrcVT)) {
1089 SDValue Load = DAG.getLoad(SrcVT, dl, Chain, Ptr,
1090 LD->getMemOperand());
1094 ExtendOp = (SrcVT.isFloatingPoint() ?
1095 ISD::FP_EXTEND : ISD::ANY_EXTEND);
1097 case ISD::SEXTLOAD: ExtendOp = ISD::SIGN_EXTEND; break;
1098 case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break;
1099 default: llvm_unreachable("Unexpected extend load type!");
1101 Value = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
1102 Chain = Load.getValue(1);
1106 assert(!SrcVT.isVector() &&
1107 "Vector Loads are handled in LegalizeVectorOps");
1109 // FIXME: This does not work for vectors on most targets. Sign- and
1110 // zero-extend operations are currently folded into extending loads,
1111 // whether they are legal or not, and then we end up here without any
1112 // support for legalizing them.
1113 assert(ExtType != ISD::EXTLOAD &&
1114 "EXTLOAD should always be supported!");
1115 // Turn the unsupported load into an EXTLOAD followed by an explicit
1116 // zero/sign extend inreg.
1117 SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
1119 LD->getMemOperand());
1121 if (ExtType == ISD::SEXTLOAD)
1122 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1123 Result.getValueType(),
1124 Result, DAG.getValueType(SrcVT));
1126 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType());
1128 Chain = Result.getValue(1);
1133 // Since loads produce two values, make sure to remember that we legalized
1135 if (Chain.getNode() != Node) {
1136 assert(Value.getNode() != Node && "Load must be completely replaced");
1137 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Value);
1138 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
1143 /// LegalizeOp - Return a legal replacement for the given operation, with
1144 /// all legal operands.
1145 void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
1146 if (Node->getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
1149 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1150 assert(TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) ==
1151 TargetLowering::TypeLegal &&
1152 "Unexpected illegal type!");
1154 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1155 assert((TLI.getTypeAction(*DAG.getContext(),
1156 Node->getOperand(i).getValueType()) ==
1157 TargetLowering::TypeLegal ||
1158 Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
1159 "Unexpected illegal type!");
1161 // Figure out the correct action; the way to query this varies by opcode
1162 TargetLowering::LegalizeAction Action = TargetLowering::Legal;
1163 bool SimpleFinishLegalizing = true;
1164 switch (Node->getOpcode()) {
1165 case ISD::INTRINSIC_W_CHAIN:
1166 case ISD::INTRINSIC_WO_CHAIN:
1167 case ISD::INTRINSIC_VOID:
1168 case ISD::STACKSAVE:
1169 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1172 Action = TLI.getOperationAction(Node->getOpcode(),
1173 Node->getValueType(0));
1174 if (Action != TargetLowering::Promote)
1175 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1177 case ISD::SINT_TO_FP:
1178 case ISD::UINT_TO_FP:
1179 case ISD::EXTRACT_VECTOR_ELT:
1180 Action = TLI.getOperationAction(Node->getOpcode(),
1181 Node->getOperand(0).getValueType());
1183 case ISD::FP_ROUND_INREG:
1184 case ISD::SIGN_EXTEND_INREG: {
1185 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
1186 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
1189 case ISD::ATOMIC_STORE: {
1190 Action = TLI.getOperationAction(Node->getOpcode(),
1191 Node->getOperand(2).getValueType());
1194 case ISD::SELECT_CC:
1197 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
1198 Node->getOpcode() == ISD::SETCC ? 2 : 1;
1199 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
1200 MVT OpVT = Node->getOperand(CompareOperand).getSimpleValueType();
1201 ISD::CondCode CCCode =
1202 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
1203 Action = TLI.getCondCodeAction(CCCode, OpVT);
1204 if (Action == TargetLowering::Legal) {
1205 if (Node->getOpcode() == ISD::SELECT_CC)
1206 Action = TLI.getOperationAction(Node->getOpcode(),
1207 Node->getValueType(0));
1209 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
1215 // FIXME: Model these properly. LOAD and STORE are complicated, and
1216 // STORE expects the unlegalized operand in some cases.
1217 SimpleFinishLegalizing = false;
1219 case ISD::CALLSEQ_START:
1220 case ISD::CALLSEQ_END:
1221 // FIXME: This shouldn't be necessary. These nodes have special properties
1222 // dealing with the recursive nature of legalization. Removing this
1223 // special case should be done as part of making LegalizeDAG non-recursive.
1224 SimpleFinishLegalizing = false;
1226 case ISD::EXTRACT_ELEMENT:
1227 case ISD::FLT_ROUNDS_:
1235 case ISD::MERGE_VALUES:
1236 case ISD::EH_RETURN:
1237 case ISD::FRAME_TO_ARGS_OFFSET:
1238 case ISD::EH_SJLJ_SETJMP:
1239 case ISD::EH_SJLJ_LONGJMP:
1240 // These operations lie about being legal: when they claim to be legal,
1241 // they should actually be expanded.
1242 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1243 if (Action == TargetLowering::Legal)
1244 Action = TargetLowering::Expand;
1246 case ISD::INIT_TRAMPOLINE:
1247 case ISD::ADJUST_TRAMPOLINE:
1248 case ISD::FRAMEADDR:
1249 case ISD::RETURNADDR:
1250 // These operations lie about being legal: when they claim to be legal,
1251 // they should actually be custom-lowered.
1252 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1253 if (Action == TargetLowering::Legal)
1254 Action = TargetLowering::Custom;
1256 case ISD::DEBUGTRAP:
1257 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1258 if (Action == TargetLowering::Expand) {
1259 // replace ISD::DEBUGTRAP with ISD::TRAP
1261 NewVal = DAG.getNode(ISD::TRAP, SDLoc(Node), Node->getVTList(),
1262 Node->getOperand(0));
1263 ReplaceNode(Node, NewVal.getNode());
1264 LegalizeOp(NewVal.getNode());
1270 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1271 Action = TargetLowering::Legal;
1273 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1278 if (SimpleFinishLegalizing) {
1279 SDNode *NewNode = Node;
1280 switch (Node->getOpcode()) {
1287 // Legalizing shifts/rotates requires adjusting the shift amount
1288 // to the appropriate width.
1289 if (!Node->getOperand(1).getValueType().isVector()) {
1291 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1292 Node->getOperand(1));
1293 HandleSDNode Handle(SAO);
1294 LegalizeOp(SAO.getNode());
1295 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1299 case ISD::SRL_PARTS:
1300 case ISD::SRA_PARTS:
1301 case ISD::SHL_PARTS:
1302 // Legalizing shifts/rotates requires adjusting the shift amount
1303 // to the appropriate width.
1304 if (!Node->getOperand(2).getValueType().isVector()) {
1306 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1307 Node->getOperand(2));
1308 HandleSDNode Handle(SAO);
1309 LegalizeOp(SAO.getNode());
1310 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1311 Node->getOperand(1),
1317 if (NewNode != Node) {
1318 DAG.ReplaceAllUsesWith(Node, NewNode);
1319 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1320 DAG.TransferDbgValues(SDValue(Node, i), SDValue(NewNode, i));
1325 case TargetLowering::Legal:
1327 case TargetLowering::Custom: {
1328 // FIXME: The handling for custom lowering with multiple results is
1330 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1331 if (Res.getNode()) {
1332 SmallVector<SDValue, 8> ResultVals;
1333 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
1335 ResultVals.push_back(Res);
1337 ResultVals.push_back(Res.getValue(i));
1339 if (Res.getNode() != Node || Res.getResNo() != 0) {
1340 DAG.ReplaceAllUsesWith(Node, ResultVals.data());
1341 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1342 DAG.TransferDbgValues(SDValue(Node, i), ResultVals[i]);
1349 case TargetLowering::Expand:
1352 case TargetLowering::Promote:
1358 switch (Node->getOpcode()) {
1365 llvm_unreachable("Do not know how to legalize this operator!");
1367 case ISD::CALLSEQ_START:
1368 case ISD::CALLSEQ_END:
1371 return LegalizeLoadOps(Node);
1374 return LegalizeStoreOps(Node);
1379 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1380 SDValue Vec = Op.getOperand(0);
1381 SDValue Idx = Op.getOperand(1);
1383 // Store the value to a temporary stack slot, then LOAD the returned part.
1384 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1385 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1386 MachinePointerInfo(), false, false, 0);
1388 // Add the offset to the index.
1390 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1391 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1392 DAG.getConstant(EltSize, Idx.getValueType()));
1394 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1395 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1397 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1399 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1401 if (Op.getValueType().isVector())
1402 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,MachinePointerInfo(),
1403 false, false, false, 0);
1404 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
1405 MachinePointerInfo(),
1406 Vec.getValueType().getVectorElementType(),
1410 SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
1411 assert(Op.getValueType().isVector() && "Non-vector insert subvector!");
1413 SDValue Vec = Op.getOperand(0);
1414 SDValue Part = Op.getOperand(1);
1415 SDValue Idx = Op.getOperand(2);
1418 // Store the value to a temporary stack slot, then LOAD the returned part.
1420 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1421 int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1422 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1424 // First store the whole vector.
1425 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo,
1428 // Then store the inserted part.
1430 // Add the offset to the index.
1432 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1434 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1435 DAG.getConstant(EltSize, Idx.getValueType()));
1437 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1438 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1440 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1442 SDValue SubStackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
1445 // Store the subvector.
1446 Ch = DAG.getStore(DAG.getEntryNode(), dl, Part, SubStackPtr,
1447 MachinePointerInfo(), false, false, 0);
1449 // Finally, load the updated vector.
1450 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo,
1451 false, false, false, 0);
1454 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1455 // We can't handle this case efficiently. Allocate a sufficiently
1456 // aligned object on the stack, store each element into it, then load
1457 // the result as a vector.
1458 // Create the stack frame object.
1459 EVT VT = Node->getValueType(0);
1460 EVT EltVT = VT.getVectorElementType();
1462 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1463 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1464 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1466 // Emit a store of each element to the stack slot.
1467 SmallVector<SDValue, 8> Stores;
1468 unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1469 // Store (in the right endianness) the elements to memory.
1470 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1471 // Ignore undef elements.
1472 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1474 unsigned Offset = TypeByteSize*i;
1476 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
1477 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1479 // If the destination vector element type is narrower than the source
1480 // element type, only store the bits necessary.
1481 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1482 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1483 Node->getOperand(i), Idx,
1484 PtrInfo.getWithOffset(Offset),
1485 EltVT, false, false, 0));
1487 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
1488 Node->getOperand(i), Idx,
1489 PtrInfo.getWithOffset(Offset),
1494 if (!Stores.empty()) // Not all undef elements?
1495 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1496 &Stores[0], Stores.size());
1498 StoreChain = DAG.getEntryNode();
1500 // Result is a load from the stack slot.
1501 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo,
1502 false, false, false, 0);
1505 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
1507 SDValue Tmp1 = Node->getOperand(0);
1508 SDValue Tmp2 = Node->getOperand(1);
1510 // Get the sign bit of the RHS. First obtain a value that has the same
1511 // sign as the sign bit, i.e. negative if and only if the sign bit is 1.
1513 EVT FloatVT = Tmp2.getValueType();
1514 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits());
1515 if (TLI.isTypeLegal(IVT)) {
1516 // Convert to an integer with the same sign bit.
1517 SignBit = DAG.getNode(ISD::BITCAST, dl, IVT, Tmp2);
1519 // Store the float to memory, then load the sign part out as an integer.
1520 MVT LoadTy = TLI.getPointerTy();
1521 // First create a temporary that is aligned for both the load and store.
1522 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1523 // Then store the float to it.
1525 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, MachinePointerInfo(),
1527 if (TLI.isBigEndian()) {
1528 assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1529 // Load out a legal integer with the same sign bit as the float.
1530 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, MachinePointerInfo(),
1531 false, false, false, 0);
1532 } else { // Little endian
1533 SDValue LoadPtr = StackPtr;
1534 // The float may be wider than the integer we are going to load. Advance
1535 // the pointer so that the loaded integer will contain the sign bit.
1536 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits();
1537 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8;
1538 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(),
1540 DAG.getConstant(ByteOffset, LoadPtr.getValueType()));
1541 // Load a legal integer containing the sign bit.
1542 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(),
1543 false, false, false, 0);
1544 // Move the sign bit to the top bit of the loaded integer.
1545 unsigned BitShift = LoadTy.getSizeInBits() -
1546 (FloatVT.getSizeInBits() - 8 * ByteOffset);
1547 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?");
1549 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit,
1550 DAG.getConstant(BitShift,
1551 TLI.getShiftAmountTy(SignBit.getValueType())));
1554 // Now get the sign bit proper, by seeing whether the value is negative.
1555 SignBit = DAG.getSetCC(dl, getSetCCResultType(SignBit.getValueType()),
1556 SignBit, DAG.getConstant(0, SignBit.getValueType()),
1558 // Get the absolute value of the result.
1559 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1560 // Select between the nabs and abs value based on the sign bit of
1562 return DAG.getSelect(dl, AbsVal.getValueType(), SignBit,
1563 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1567 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1568 SmallVectorImpl<SDValue> &Results) {
1569 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1570 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1571 " not tell us which reg is the stack pointer!");
1573 EVT VT = Node->getValueType(0);
1574 SDValue Tmp1 = SDValue(Node, 0);
1575 SDValue Tmp2 = SDValue(Node, 1);
1576 SDValue Tmp3 = Node->getOperand(2);
1577 SDValue Chain = Tmp1.getOperand(0);
1579 // Chain the dynamic stack allocation so that it doesn't modify the stack
1580 // pointer when other instructions are using the stack.
1581 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
1584 SDValue Size = Tmp2.getOperand(1);
1585 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1586 Chain = SP.getValue(1);
1587 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1588 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
1589 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1590 if (Align > StackAlign)
1591 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
1592 DAG.getConstant(-(uint64_t)Align, VT));
1593 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1595 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1596 DAG.getIntPtrConstant(0, true), SDValue(),
1599 Results.push_back(Tmp1);
1600 Results.push_back(Tmp2);
1603 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
1604 /// condition code CC on the current target.
1605 /// If the SETCC has been legalized using AND / OR, then the legalized node
1606 /// will be stored in LHS. RHS and CC will be set to SDValue().
1607 /// If the SETCC has been legalized by using getSetCCSwappedOperands(),
1608 /// then the values of LHS and RHS will be swapped and CC will be set to the
1610 /// \returns true if the SetCC has been legalized, false if it hasn't.
1611 bool SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1612 SDValue &LHS, SDValue &RHS,
1615 MVT OpVT = LHS.getSimpleValueType();
1616 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1617 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1618 default: llvm_unreachable("Unknown condition code action!");
1619 case TargetLowering::Legal:
1622 case TargetLowering::Expand: {
1623 ISD::CondCode InvCC = ISD::getSetCCSwappedOperands(CCCode);
1624 if (TLI.isCondCodeLegal(InvCC, OpVT)) {
1625 std::swap(LHS, RHS);
1626 CC = DAG.getCondCode(InvCC);
1629 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1632 default: llvm_unreachable("Don't know how to expand this condition!");
1634 assert(TLI.getCondCodeAction(ISD::SETOEQ, OpVT)
1635 == TargetLowering::Legal
1636 && "If SETO is expanded, SETOEQ must be legal!");
1637 CC1 = ISD::SETOEQ; CC2 = ISD::SETOEQ; Opc = ISD::AND; break;
1639 assert(TLI.getCondCodeAction(ISD::SETUNE, OpVT)
1640 == TargetLowering::Legal
1641 && "If SETUO is expanded, SETUNE must be legal!");
1642 CC1 = ISD::SETUNE; CC2 = ISD::SETUNE; Opc = ISD::OR; break;
1655 // If we are floating point, assign and break, otherwise fall through.
1656 if (!OpVT.isInteger()) {
1657 // We can use the 4th bit to tell if we are the unordered
1658 // or ordered version of the opcode.
1659 CC2 = ((unsigned)CCCode & 0x8U) ? ISD::SETUO : ISD::SETO;
1660 Opc = ((unsigned)CCCode & 0x8U) ? ISD::OR : ISD::AND;
1661 CC1 = (ISD::CondCode)(((int)CCCode & 0x7) | 0x10);
1664 // Fallthrough if we are unsigned integer.
1671 // We only support using the inverted operation, which is computed above
1672 // and not a different manner of supporting expanding these cases.
1673 llvm_unreachable("Don't know how to expand this condition!");
1676 SDValue SetCC1, SetCC2;
1677 if (CCCode != ISD::SETO && CCCode != ISD::SETUO) {
1678 // If we aren't the ordered or unorder operation,
1679 // then the pattern is (LHS CC1 RHS) Opc (LHS CC2 RHS).
1680 SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1681 SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1683 // Otherwise, the pattern is (LHS CC1 LHS) Opc (RHS CC2 RHS)
1684 SetCC1 = DAG.getSetCC(dl, VT, LHS, LHS, CC1);
1685 SetCC2 = DAG.getSetCC(dl, VT, RHS, RHS, CC2);
1687 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1696 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
1697 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1698 /// a load from the stack slot to DestVT, extending it if needed.
1699 /// The resultant code need not be legal.
1700 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
1704 // Create the stack frame object.
1706 TLI.getDataLayout()->getPrefTypeAlignment(SrcOp.getValueType().
1707 getTypeForEVT(*DAG.getContext()));
1708 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1710 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1711 int SPFI = StackPtrFI->getIndex();
1712 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(SPFI);
1714 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
1715 unsigned SlotSize = SlotVT.getSizeInBits();
1716 unsigned DestSize = DestVT.getSizeInBits();
1717 Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
1718 unsigned DestAlign = TLI.getDataLayout()->getPrefTypeAlignment(DestType);
1720 // Emit a store to the stack slot. Use a truncstore if the input value is
1721 // later than DestVT.
1724 if (SrcSize > SlotSize)
1725 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1726 PtrInfo, SlotVT, false, false, SrcAlign);
1728 assert(SrcSize == SlotSize && "Invalid store");
1729 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1730 PtrInfo, false, false, SrcAlign);
1733 // Result is a load from the stack slot.
1734 if (SlotSize == DestSize)
1735 return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo,
1736 false, false, false, DestAlign);
1738 assert(SlotSize < DestSize && "Unknown extension!");
1739 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr,
1740 PtrInfo, SlotVT, false, false, DestAlign);
1743 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1745 // Create a vector sized/aligned stack slot, store the value to element #0,
1746 // then load the whole vector back out.
1747 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1749 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1750 int SPFI = StackPtrFI->getIndex();
1752 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0),
1754 MachinePointerInfo::getFixedStack(SPFI),
1755 Node->getValueType(0).getVectorElementType(),
1757 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
1758 MachinePointerInfo::getFixedStack(SPFI),
1759 false, false, false, 0);
1763 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
1764 /// support the operation, but do support the resultant vector type.
1765 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1766 unsigned NumElems = Node->getNumOperands();
1767 SDValue Value1, Value2;
1769 EVT VT = Node->getValueType(0);
1770 EVT OpVT = Node->getOperand(0).getValueType();
1771 EVT EltVT = VT.getVectorElementType();
1773 // If the only non-undef value is the low element, turn this into a
1774 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1775 bool isOnlyLowElement = true;
1776 bool MoreThanTwoValues = false;
1777 bool isConstant = true;
1778 for (unsigned i = 0; i < NumElems; ++i) {
1779 SDValue V = Node->getOperand(i);
1780 if (V.getOpcode() == ISD::UNDEF)
1783 isOnlyLowElement = false;
1784 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1787 if (!Value1.getNode()) {
1789 } else if (!Value2.getNode()) {
1792 } else if (V != Value1 && V != Value2) {
1793 MoreThanTwoValues = true;
1797 if (!Value1.getNode())
1798 return DAG.getUNDEF(VT);
1800 if (isOnlyLowElement)
1801 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1803 // If all elements are constants, create a load from the constant pool.
1805 SmallVector<Constant*, 16> CV;
1806 for (unsigned i = 0, e = NumElems; i != e; ++i) {
1807 if (ConstantFPSDNode *V =
1808 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1809 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1810 } else if (ConstantSDNode *V =
1811 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1813 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1815 // If OpVT and EltVT don't match, EltVT is not legal and the
1816 // element values have been promoted/truncated earlier. Undo this;
1817 // we don't want a v16i8 to become a v16i32 for example.
1818 const ConstantInt *CI = V->getConstantIntValue();
1819 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
1820 CI->getZExtValue()));
1823 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
1824 Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
1825 CV.push_back(UndefValue::get(OpNTy));
1828 Constant *CP = ConstantVector::get(CV);
1829 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
1830 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
1831 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
1832 MachinePointerInfo::getConstantPool(),
1833 false, false, false, Alignment);
1836 if (!MoreThanTwoValues) {
1837 SmallVector<int, 8> ShuffleVec(NumElems, -1);
1838 for (unsigned i = 0; i < NumElems; ++i) {
1839 SDValue V = Node->getOperand(i);
1840 if (V.getOpcode() == ISD::UNDEF)
1842 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
1844 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
1845 // Get the splatted value into the low element of a vector register.
1846 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
1848 if (Value2.getNode())
1849 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
1851 Vec2 = DAG.getUNDEF(VT);
1853 // Return shuffle(LowValVec, undef, <0,0,0,0>)
1854 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
1858 // Otherwise, we can't handle this case efficiently.
1859 return ExpandVectorBuildThroughStack(Node);
1862 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
1863 // does not fit into a register, return the lo part and set the hi part to the
1864 // by-reg argument. If it does fit into a single register, return the result
1865 // and leave the Hi part unset.
1866 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
1868 TargetLowering::ArgListTy Args;
1869 TargetLowering::ArgListEntry Entry;
1870 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1871 EVT ArgVT = Node->getOperand(i).getValueType();
1872 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1873 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
1874 Entry.isSExt = isSigned;
1875 Entry.isZExt = !isSigned;
1876 Args.push_back(Entry);
1878 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1879 TLI.getPointerTy());
1881 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
1883 // By default, the input chain to this libcall is the entry node of the
1884 // function. If the libcall is going to be emitted as a tail call then
1885 // TLI.isUsedByReturnOnly will change it to the right chain if the return
1886 // node which is being folded has a non-entry input chain.
1887 SDValue InChain = DAG.getEntryNode();
1889 // isTailCall may be true since the callee does not reference caller stack
1890 // frame. Check if it's in the right position.
1891 SDValue TCChain = InChain;
1892 bool isTailCall = TLI.isInTailCallPosition(DAG, Node, TCChain);
1897 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
1898 0, TLI.getLibcallCallingConv(LC), isTailCall,
1899 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
1900 Callee, Args, DAG, SDLoc(Node));
1901 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
1904 if (!CallInfo.second.getNode())
1905 // It's a tailcall, return the chain (which is the DAG root).
1906 return DAG.getRoot();
1908 return CallInfo.first;
1911 /// ExpandLibCall - Generate a libcall taking the given operands as arguments
1912 /// and returning a result of type RetVT.
1913 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, EVT RetVT,
1914 const SDValue *Ops, unsigned NumOps,
1915 bool isSigned, SDLoc dl) {
1916 TargetLowering::ArgListTy Args;
1917 Args.reserve(NumOps);
1919 TargetLowering::ArgListEntry Entry;
1920 for (unsigned i = 0; i != NumOps; ++i) {
1921 Entry.Node = Ops[i];
1922 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
1923 Entry.isSExt = isSigned;
1924 Entry.isZExt = !isSigned;
1925 Args.push_back(Entry);
1927 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1928 TLI.getPointerTy());
1930 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
1932 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
1933 false, 0, TLI.getLibcallCallingConv(LC),
1934 /*isTailCall=*/false,
1935 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
1936 Callee, Args, DAG, dl);
1937 std::pair<SDValue,SDValue> CallInfo = TLI.LowerCallTo(CLI);
1939 return CallInfo.first;
1942 // ExpandChainLibCall - Expand a node into a call to a libcall. Similar to
1943 // ExpandLibCall except that the first operand is the in-chain.
1944 std::pair<SDValue, SDValue>
1945 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
1948 SDValue InChain = Node->getOperand(0);
1950 TargetLowering::ArgListTy Args;
1951 TargetLowering::ArgListEntry Entry;
1952 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) {
1953 EVT ArgVT = Node->getOperand(i).getValueType();
1954 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1955 Entry.Node = Node->getOperand(i);
1957 Entry.isSExt = isSigned;
1958 Entry.isZExt = !isSigned;
1959 Args.push_back(Entry);
1961 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1962 TLI.getPointerTy());
1964 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
1966 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
1967 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
1968 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
1969 Callee, Args, DAG, SDLoc(Node));
1970 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
1975 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
1976 RTLIB::Libcall Call_F32,
1977 RTLIB::Libcall Call_F64,
1978 RTLIB::Libcall Call_F80,
1979 RTLIB::Libcall Call_F128,
1980 RTLIB::Libcall Call_PPCF128) {
1982 switch (Node->getSimpleValueType(0).SimpleTy) {
1983 default: llvm_unreachable("Unexpected request for libcall!");
1984 case MVT::f32: LC = Call_F32; break;
1985 case MVT::f64: LC = Call_F64; break;
1986 case MVT::f80: LC = Call_F80; break;
1987 case MVT::f128: LC = Call_F128; break;
1988 case MVT::ppcf128: LC = Call_PPCF128; break;
1990 return ExpandLibCall(LC, Node, false);
1993 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
1994 RTLIB::Libcall Call_I8,
1995 RTLIB::Libcall Call_I16,
1996 RTLIB::Libcall Call_I32,
1997 RTLIB::Libcall Call_I64,
1998 RTLIB::Libcall Call_I128) {
2000 switch (Node->getSimpleValueType(0).SimpleTy) {
2001 default: llvm_unreachable("Unexpected request for libcall!");
2002 case MVT::i8: LC = Call_I8; break;
2003 case MVT::i16: LC = Call_I16; break;
2004 case MVT::i32: LC = Call_I32; break;
2005 case MVT::i64: LC = Call_I64; break;
2006 case MVT::i128: LC = Call_I128; break;
2008 return ExpandLibCall(LC, Node, isSigned);
2011 /// isDivRemLibcallAvailable - Return true if divmod libcall is available.
2012 static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
2013 const TargetLowering &TLI) {
2015 switch (Node->getSimpleValueType(0).SimpleTy) {
2016 default: llvm_unreachable("Unexpected request for libcall!");
2017 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2018 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2019 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2020 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2021 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2024 return TLI.getLibcallName(LC) != 0;
2027 /// useDivRem - Only issue divrem libcall if both quotient and remainder are
2029 static bool useDivRem(SDNode *Node, bool isSigned, bool isDIV) {
2030 // The other use might have been replaced with a divrem already.
2031 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2032 unsigned OtherOpcode = 0;
2034 OtherOpcode = isDIV ? ISD::SREM : ISD::SDIV;
2036 OtherOpcode = isDIV ? ISD::UREM : ISD::UDIV;
2038 SDValue Op0 = Node->getOperand(0);
2039 SDValue Op1 = Node->getOperand(1);
2040 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2041 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2045 if ((User->getOpcode() == OtherOpcode || User->getOpcode() == DivRemOpc) &&
2046 User->getOperand(0) == Op0 &&
2047 User->getOperand(1) == Op1)
2053 /// ExpandDivRemLibCall - Issue libcalls to __{u}divmod to compute div / rem
2056 SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
2057 SmallVectorImpl<SDValue> &Results) {
2058 unsigned Opcode = Node->getOpcode();
2059 bool isSigned = Opcode == ISD::SDIVREM;
2062 switch (Node->getSimpleValueType(0).SimpleTy) {
2063 default: llvm_unreachable("Unexpected request for libcall!");
2064 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2065 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2066 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2067 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2068 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2071 // The input chain to this libcall is the entry node of the function.
2072 // Legalizing the call will automatically add the previous call to the
2074 SDValue InChain = DAG.getEntryNode();
2076 EVT RetVT = Node->getValueType(0);
2077 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2079 TargetLowering::ArgListTy Args;
2080 TargetLowering::ArgListEntry Entry;
2081 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2082 EVT ArgVT = Node->getOperand(i).getValueType();
2083 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2084 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
2085 Entry.isSExt = isSigned;
2086 Entry.isZExt = !isSigned;
2087 Args.push_back(Entry);
2090 // Also pass the return address of the remainder.
2091 SDValue FIPtr = DAG.CreateStackTemporary(RetVT);
2093 Entry.Ty = RetTy->getPointerTo();
2094 Entry.isSExt = isSigned;
2095 Entry.isZExt = !isSigned;
2096 Args.push_back(Entry);
2098 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2099 TLI.getPointerTy());
2103 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
2104 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
2105 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2106 Callee, Args, DAG, dl);
2107 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2109 // Remainder is loaded back from the stack frame.
2110 SDValue Rem = DAG.getLoad(RetVT, dl, CallInfo.second, FIPtr,
2111 MachinePointerInfo(), false, false, false, 0);
2112 Results.push_back(CallInfo.first);
2113 Results.push_back(Rem);
2116 /// isSinCosLibcallAvailable - Return true if sincos libcall is available.
2117 static bool isSinCosLibcallAvailable(SDNode *Node, const TargetLowering &TLI) {
2119 switch (Node->getSimpleValueType(0).SimpleTy) {
2120 default: llvm_unreachable("Unexpected request for libcall!");
2121 case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2122 case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2123 case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2124 case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2125 case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2127 return TLI.getLibcallName(LC) != 0;
2130 /// canCombineSinCosLibcall - Return true if sincos libcall is available and
2131 /// can be used to combine sin and cos.
2132 static bool canCombineSinCosLibcall(SDNode *Node, const TargetLowering &TLI,
2133 const TargetMachine &TM) {
2134 if (!isSinCosLibcallAvailable(Node, TLI))
2136 // GNU sin/cos functions set errno while sincos does not. Therefore
2137 // combining sin and cos is only safe if unsafe-fpmath is enabled.
2138 bool isGNU = Triple(TM.getTargetTriple()).getEnvironment() == Triple::GNU;
2139 if (isGNU && !TM.Options.UnsafeFPMath)
2144 /// useSinCos - Only issue sincos libcall if both sin and cos are
2146 static bool useSinCos(SDNode *Node) {
2147 unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN
2148 ? ISD::FCOS : ISD::FSIN;
2150 SDValue Op0 = Node->getOperand(0);
2151 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2152 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2156 // The other user might have been turned into sincos already.
2157 if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS)
2163 /// ExpandSinCosLibCall - Issue libcalls to sincos to compute sin / cos
2166 SelectionDAGLegalize::ExpandSinCosLibCall(SDNode *Node,
2167 SmallVectorImpl<SDValue> &Results) {
2169 switch (Node->getSimpleValueType(0).SimpleTy) {
2170 default: llvm_unreachable("Unexpected request for libcall!");
2171 case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2172 case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2173 case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2174 case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2175 case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2178 // The input chain to this libcall is the entry node of the function.
2179 // Legalizing the call will automatically add the previous call to the
2181 SDValue InChain = DAG.getEntryNode();
2183 EVT RetVT = Node->getValueType(0);
2184 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2186 TargetLowering::ArgListTy Args;
2187 TargetLowering::ArgListEntry Entry;
2189 // Pass the argument.
2190 Entry.Node = Node->getOperand(0);
2192 Entry.isSExt = false;
2193 Entry.isZExt = false;
2194 Args.push_back(Entry);
2196 // Pass the return address of sin.
2197 SDValue SinPtr = DAG.CreateStackTemporary(RetVT);
2198 Entry.Node = SinPtr;
2199 Entry.Ty = RetTy->getPointerTo();
2200 Entry.isSExt = false;
2201 Entry.isZExt = false;
2202 Args.push_back(Entry);
2204 // Also pass the return address of the cos.
2205 SDValue CosPtr = DAG.CreateStackTemporary(RetVT);
2206 Entry.Node = CosPtr;
2207 Entry.Ty = RetTy->getPointerTo();
2208 Entry.isSExt = false;
2209 Entry.isZExt = false;
2210 Args.push_back(Entry);
2212 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2213 TLI.getPointerTy());
2217 CallLoweringInfo CLI(InChain, Type::getVoidTy(*DAG.getContext()),
2218 false, false, false, false,
2219 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
2220 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2221 Callee, Args, DAG, dl);
2222 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2224 Results.push_back(DAG.getLoad(RetVT, dl, CallInfo.second, SinPtr,
2225 MachinePointerInfo(), false, false, false, 0));
2226 Results.push_back(DAG.getLoad(RetVT, dl, CallInfo.second, CosPtr,
2227 MachinePointerInfo(), false, false, false, 0));
2230 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
2231 /// INT_TO_FP operation of the specified operand when the target requests that
2232 /// we expand it. At this point, we know that the result and operand types are
2233 /// legal for the target.
2234 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
2238 if (Op0.getValueType() == MVT::i32 && TLI.isTypeLegal(MVT::f64)) {
2239 // simple 32-bit [signed|unsigned] integer to float/double expansion
2241 // Get the stack frame index of a 8 byte buffer.
2242 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2244 // word offset constant for Hi/Lo address computation
2245 SDValue WordOff = DAG.getConstant(sizeof(int), StackSlot.getValueType());
2246 // set up Hi and Lo (into buffer) address based on endian
2247 SDValue Hi = StackSlot;
2248 SDValue Lo = DAG.getNode(ISD::ADD, dl, StackSlot.getValueType(),
2249 StackSlot, WordOff);
2250 if (TLI.isLittleEndian())
2253 // if signed map to unsigned space
2256 // constant used to invert sign bit (signed to unsigned mapping)
2257 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
2258 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2262 // store the lo of the constructed double - based on integer input
2263 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
2264 Op0Mapped, Lo, MachinePointerInfo(),
2266 // initial hi portion of constructed double
2267 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
2268 // store the hi of the constructed double - biased exponent
2269 SDValue Store2 = DAG.getStore(Store1, dl, InitialHi, Hi,
2270 MachinePointerInfo(),
2272 // load the constructed double
2273 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot,
2274 MachinePointerInfo(), false, false, false, 0);
2275 // FP constant to bias correct the final result
2276 SDValue Bias = DAG.getConstantFP(isSigned ?
2277 BitsToDouble(0x4330000080000000ULL) :
2278 BitsToDouble(0x4330000000000000ULL),
2280 // subtract the bias
2281 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2284 // handle final rounding
2285 if (DestVT == MVT::f64) {
2288 } else if (DestVT.bitsLT(MVT::f64)) {
2289 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2290 DAG.getIntPtrConstant(0));
2291 } else if (DestVT.bitsGT(MVT::f64)) {
2292 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2296 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2297 // Code below here assumes !isSigned without checking again.
2299 // Implementation of unsigned i64 to f64 following the algorithm in
2300 // __floatundidf in compiler_rt. This implementation has the advantage
2301 // of performing rounding correctly, both in the default rounding mode
2302 // and in all alternate rounding modes.
2303 // TODO: Generalize this for use with other types.
2304 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
2306 DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64);
2307 SDValue TwoP84PlusTwoP52 =
2308 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64);
2310 DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64);
2312 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32);
2313 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2314 DAG.getConstant(32, MVT::i64));
2315 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2316 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2317 SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr);
2318 SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr);
2319 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
2321 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
2324 // Implementation of unsigned i64 to f32.
2325 // TODO: Generalize this for use with other types.
2326 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) {
2327 // For unsigned conversions, convert them to signed conversions using the
2328 // algorithm from the x86_64 __floatundidf in compiler_rt.
2330 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0);
2332 SDValue ShiftConst =
2333 DAG.getConstant(1, TLI.getShiftAmountTy(Op0.getValueType()));
2334 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
2335 SDValue AndConst = DAG.getConstant(1, MVT::i64);
2336 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst);
2337 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr);
2339 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or);
2340 SDValue Slow = DAG.getNode(ISD::FADD, dl, MVT::f32, SignCvt, SignCvt);
2342 // TODO: This really should be implemented using a branch rather than a
2343 // select. We happen to get lucky and machinesink does the right
2344 // thing most of the time. This would be a good candidate for a
2345 //pseudo-op, or, even better, for whole-function isel.
2346 SDValue SignBitTest = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
2347 Op0, DAG.getConstant(0, MVT::i64), ISD::SETLT);
2348 return DAG.getSelect(dl, MVT::f32, SignBitTest, Slow, Fast);
2351 // Otherwise, implement the fully general conversion.
2353 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2354 DAG.getConstant(UINT64_C(0xfffffffffffff800), MVT::i64));
2355 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
2356 DAG.getConstant(UINT64_C(0x800), MVT::i64));
2357 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2358 DAG.getConstant(UINT64_C(0x7ff), MVT::i64));
2359 SDValue Ne = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
2360 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE);
2361 SDValue Sel = DAG.getSelect(dl, MVT::i64, Ne, Or, Op0);
2362 SDValue Ge = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
2363 Op0, DAG.getConstant(UINT64_C(0x0020000000000000), MVT::i64),
2365 SDValue Sel2 = DAG.getSelect(dl, MVT::i64, Ge, Sel, Op0);
2366 EVT SHVT = TLI.getShiftAmountTy(Sel2.getValueType());
2368 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2369 DAG.getConstant(32, SHVT));
2370 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh);
2371 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc);
2373 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), MVT::f64);
2374 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt);
2375 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2);
2376 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo);
2377 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2);
2378 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd,
2379 DAG.getIntPtrConstant(0));
2382 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2384 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(Op0.getValueType()),
2385 Op0, DAG.getConstant(0, Op0.getValueType()),
2387 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
2388 SDValue CstOffset = DAG.getSelect(dl, Zero.getValueType(),
2389 SignSet, Four, Zero);
2391 // If the sign bit of the integer is set, the large number will be treated
2392 // as a negative number. To counteract this, the dynamic code adds an
2393 // offset depending on the data type.
2395 switch (Op0.getSimpleValueType().SimpleTy) {
2396 default: llvm_unreachable("Unsupported integer type!");
2397 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2398 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2399 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2400 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2402 if (TLI.isLittleEndian()) FF <<= 32;
2403 Constant *FudgeFactor = ConstantInt::get(
2404 Type::getInt64Ty(*DAG.getContext()), FF);
2406 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
2407 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2408 CPIdx = DAG.getNode(ISD::ADD, dl, CPIdx.getValueType(), CPIdx, CstOffset);
2409 Alignment = std::min(Alignment, 4u);
2411 if (DestVT == MVT::f32)
2412 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2413 MachinePointerInfo::getConstantPool(),
2414 false, false, false, Alignment);
2416 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
2417 DAG.getEntryNode(), CPIdx,
2418 MachinePointerInfo::getConstantPool(),
2419 MVT::f32, false, false, Alignment);
2420 HandleSDNode Handle(Load);
2421 LegalizeOp(Load.getNode());
2422 FudgeInReg = Handle.getValue();
2425 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2428 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
2429 /// *INT_TO_FP operation of the specified operand when the target requests that
2430 /// we promote it. At this point, we know that the result and operand types are
2431 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2432 /// operation that takes a larger input.
2433 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2437 // First step, figure out the appropriate *INT_TO_FP operation to use.
2438 EVT NewInTy = LegalOp.getValueType();
2440 unsigned OpToUse = 0;
2442 // Scan for the appropriate larger type to use.
2444 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2445 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2447 // If the target supports SINT_TO_FP of this type, use it.
2448 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2449 OpToUse = ISD::SINT_TO_FP;
2452 if (isSigned) continue;
2454 // If the target supports UINT_TO_FP of this type, use it.
2455 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2456 OpToUse = ISD::UINT_TO_FP;
2460 // Otherwise, try a larger type.
2463 // Okay, we found the operation and type to use. Zero extend our input to the
2464 // desired type then run the operation on it.
2465 return DAG.getNode(OpToUse, dl, DestVT,
2466 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2467 dl, NewInTy, LegalOp));
2470 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
2471 /// FP_TO_*INT operation of the specified operand when the target requests that
2472 /// we promote it. At this point, we know that the result and operand types are
2473 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2474 /// operation that returns a larger result.
2475 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2479 // First step, figure out the appropriate FP_TO*INT operation to use.
2480 EVT NewOutTy = DestVT;
2482 unsigned OpToUse = 0;
2484 // Scan for the appropriate larger type to use.
2486 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2487 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2489 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2490 OpToUse = ISD::FP_TO_SINT;
2494 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2495 OpToUse = ISD::FP_TO_UINT;
2499 // Otherwise, try a larger type.
2503 // Okay, we found the operation and type to use.
2504 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2506 // Truncate the result of the extended FP_TO_*INT operation to the desired
2508 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2511 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
2513 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, SDLoc dl) {
2514 EVT VT = Op.getValueType();
2515 EVT SHVT = TLI.getShiftAmountTy(VT);
2516 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2517 switch (VT.getSimpleVT().SimpleTy) {
2518 default: llvm_unreachable("Unhandled Expand type in BSWAP!");
2520 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2521 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2522 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2524 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2525 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2526 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2527 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2528 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
2529 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
2530 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2531 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2532 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2534 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
2535 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
2536 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2537 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2538 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2539 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2540 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
2541 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
2542 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
2543 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
2544 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
2545 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
2546 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
2547 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
2548 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2549 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2550 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2551 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2552 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2553 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2554 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2558 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
2560 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2563 default: llvm_unreachable("Cannot expand this yet!");
2565 EVT VT = Op.getValueType();
2566 EVT ShVT = TLI.getShiftAmountTy(VT);
2567 unsigned Len = VT.getSizeInBits();
2569 assert(VT.isInteger() && Len <= 128 && Len % 8 == 0 &&
2570 "CTPOP not implemented for this type.");
2572 // This is the "best" algorithm from
2573 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
2575 SDValue Mask55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)), VT);
2576 SDValue Mask33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)), VT);
2577 SDValue Mask0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)), VT);
2578 SDValue Mask01 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x01)), VT);
2580 // v = v - ((v >> 1) & 0x55555555...)
2581 Op = DAG.getNode(ISD::SUB, dl, VT, Op,
2582 DAG.getNode(ISD::AND, dl, VT,
2583 DAG.getNode(ISD::SRL, dl, VT, Op,
2584 DAG.getConstant(1, ShVT)),
2586 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
2587 Op = DAG.getNode(ISD::ADD, dl, VT,
2588 DAG.getNode(ISD::AND, dl, VT, Op, Mask33),
2589 DAG.getNode(ISD::AND, dl, VT,
2590 DAG.getNode(ISD::SRL, dl, VT, Op,
2591 DAG.getConstant(2, ShVT)),
2593 // v = (v + (v >> 4)) & 0x0F0F0F0F...
2594 Op = DAG.getNode(ISD::AND, dl, VT,
2595 DAG.getNode(ISD::ADD, dl, VT, Op,
2596 DAG.getNode(ISD::SRL, dl, VT, Op,
2597 DAG.getConstant(4, ShVT))),
2599 // v = (v * 0x01010101...) >> (Len - 8)
2600 Op = DAG.getNode(ISD::SRL, dl, VT,
2601 DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
2602 DAG.getConstant(Len - 8, ShVT));
2606 case ISD::CTLZ_ZERO_UNDEF:
2607 // This trivially expands to CTLZ.
2608 return DAG.getNode(ISD::CTLZ, dl, Op.getValueType(), Op);
2610 // for now, we do this:
2611 // x = x | (x >> 1);
2612 // x = x | (x >> 2);
2614 // x = x | (x >>16);
2615 // x = x | (x >>32); // for 64-bit input
2616 // return popcount(~x);
2618 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
2619 EVT VT = Op.getValueType();
2620 EVT ShVT = TLI.getShiftAmountTy(VT);
2621 unsigned len = VT.getSizeInBits();
2622 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2623 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2624 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2625 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2627 Op = DAG.getNOT(dl, Op, VT);
2628 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2630 case ISD::CTTZ_ZERO_UNDEF:
2631 // This trivially expands to CTTZ.
2632 return DAG.getNode(ISD::CTTZ, dl, Op.getValueType(), Op);
2634 // for now, we use: { return popcount(~x & (x - 1)); }
2635 // unless the target has ctlz but not ctpop, in which case we use:
2636 // { return 32 - nlz(~x & (x-1)); }
2637 // see also http://www.hackersdelight.org/HDcode/ntz.cc
2638 EVT VT = Op.getValueType();
2639 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2640 DAG.getNOT(dl, Op, VT),
2641 DAG.getNode(ISD::SUB, dl, VT, Op,
2642 DAG.getConstant(1, VT)));
2643 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2644 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2645 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2646 return DAG.getNode(ISD::SUB, dl, VT,
2647 DAG.getConstant(VT.getSizeInBits(), VT),
2648 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2649 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2654 std::pair <SDValue, SDValue> SelectionDAGLegalize::ExpandAtomic(SDNode *Node) {
2655 unsigned Opc = Node->getOpcode();
2656 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
2661 llvm_unreachable("Unhandled atomic intrinsic Expand!");
2662 case ISD::ATOMIC_SWAP:
2663 switch (VT.SimpleTy) {
2664 default: llvm_unreachable("Unexpected value type for atomic!");
2665 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break;
2666 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
2667 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
2668 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
2669 case MVT::i128:LC = RTLIB::SYNC_LOCK_TEST_AND_SET_16;break;
2672 case ISD::ATOMIC_CMP_SWAP:
2673 switch (VT.SimpleTy) {
2674 default: llvm_unreachable("Unexpected value type for atomic!");
2675 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break;
2676 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;
2677 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;
2678 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
2679 case MVT::i128:LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16;break;
2682 case ISD::ATOMIC_LOAD_ADD:
2683 switch (VT.SimpleTy) {
2684 default: llvm_unreachable("Unexpected value type for atomic!");
2685 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break;
2686 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;
2687 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;
2688 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
2689 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_ADD_16;break;
2692 case ISD::ATOMIC_LOAD_SUB:
2693 switch (VT.SimpleTy) {
2694 default: llvm_unreachable("Unexpected value type for atomic!");
2695 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break;
2696 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;
2697 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;
2698 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
2699 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_SUB_16;break;
2702 case ISD::ATOMIC_LOAD_AND:
2703 switch (VT.SimpleTy) {
2704 default: llvm_unreachable("Unexpected value type for atomic!");
2705 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break;
2706 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;
2707 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;
2708 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
2709 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_AND_16;break;
2712 case ISD::ATOMIC_LOAD_OR:
2713 switch (VT.SimpleTy) {
2714 default: llvm_unreachable("Unexpected value type for atomic!");
2715 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break;
2716 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;
2717 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;
2718 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
2719 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_OR_16;break;
2722 case ISD::ATOMIC_LOAD_XOR:
2723 switch (VT.SimpleTy) {
2724 default: llvm_unreachable("Unexpected value type for atomic!");
2725 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break;
2726 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;
2727 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;
2728 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
2729 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_XOR_16;break;
2732 case ISD::ATOMIC_LOAD_NAND:
2733 switch (VT.SimpleTy) {
2734 default: llvm_unreachable("Unexpected value type for atomic!");
2735 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break;
2736 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;
2737 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;
2738 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
2739 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_NAND_16;break;
2742 case ISD::ATOMIC_LOAD_MAX:
2743 switch (VT.SimpleTy) {
2744 default: llvm_unreachable("Unexpected value type for atomic!");
2745 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_MAX_1; break;
2746 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_MAX_2; break;
2747 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_MAX_4; break;
2748 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_MAX_8; break;
2749 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_MAX_16;break;
2752 case ISD::ATOMIC_LOAD_UMAX:
2753 switch (VT.SimpleTy) {
2754 default: llvm_unreachable("Unexpected value type for atomic!");
2755 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_UMAX_1; break;
2756 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_UMAX_2; break;
2757 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_UMAX_4; break;
2758 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_UMAX_8; break;
2759 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_UMAX_16;break;
2762 case ISD::ATOMIC_LOAD_MIN:
2763 switch (VT.SimpleTy) {
2764 default: llvm_unreachable("Unexpected value type for atomic!");
2765 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_MIN_1; break;
2766 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_MIN_2; break;
2767 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_MIN_4; break;
2768 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_MIN_8; break;
2769 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_MIN_16;break;
2772 case ISD::ATOMIC_LOAD_UMIN:
2773 switch (VT.SimpleTy) {
2774 default: llvm_unreachable("Unexpected value type for atomic!");
2775 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_UMIN_1; break;
2776 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_UMIN_2; break;
2777 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_UMIN_4; break;
2778 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_UMIN_8; break;
2779 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_UMIN_16;break;
2784 return ExpandChainLibCall(LC, Node, false);
2787 void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
2788 SmallVector<SDValue, 8> Results;
2790 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2791 switch (Node->getOpcode()) {
2794 case ISD::CTLZ_ZERO_UNDEF:
2796 case ISD::CTTZ_ZERO_UNDEF:
2797 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
2798 Results.push_back(Tmp1);
2801 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2803 case ISD::FRAMEADDR:
2804 case ISD::RETURNADDR:
2805 case ISD::FRAME_TO_ARGS_OFFSET:
2806 Results.push_back(DAG.getConstant(0, Node->getValueType(0)));
2808 case ISD::FLT_ROUNDS_:
2809 Results.push_back(DAG.getConstant(1, Node->getValueType(0)));
2811 case ISD::EH_RETURN:
2815 case ISD::EH_SJLJ_LONGJMP:
2816 // If the target didn't expand these, there's nothing to do, so just
2817 // preserve the chain and be done.
2818 Results.push_back(Node->getOperand(0));
2820 case ISD::EH_SJLJ_SETJMP:
2821 // If the target didn't expand this, just return 'zero' and preserve the
2823 Results.push_back(DAG.getConstant(0, MVT::i32));
2824 Results.push_back(Node->getOperand(0));
2826 case ISD::ATOMIC_FENCE: {
2827 // If the target didn't lower this, lower it to '__sync_synchronize()' call
2828 // FIXME: handle "fence singlethread" more efficiently.
2829 TargetLowering::ArgListTy Args;
2831 CallLoweringInfo CLI(Node->getOperand(0),
2832 Type::getVoidTy(*DAG.getContext()),
2833 false, false, false, false, 0, CallingConv::C,
2834 /*isTailCall=*/false,
2835 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2836 DAG.getExternalSymbol("__sync_synchronize",
2837 TLI.getPointerTy()),
2839 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
2841 Results.push_back(CallResult.second);
2844 case ISD::ATOMIC_LOAD: {
2845 // There is no libcall for atomic load; fake it with ATOMIC_CMP_SWAP.
2846 SDValue Zero = DAG.getConstant(0, Node->getValueType(0));
2847 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl,
2848 cast<AtomicSDNode>(Node)->getMemoryVT(),
2849 Node->getOperand(0),
2850 Node->getOperand(1), Zero, Zero,
2851 cast<AtomicSDNode>(Node)->getMemOperand(),
2852 cast<AtomicSDNode>(Node)->getOrdering(),
2853 cast<AtomicSDNode>(Node)->getSynchScope());
2854 Results.push_back(Swap.getValue(0));
2855 Results.push_back(Swap.getValue(1));
2858 case ISD::ATOMIC_STORE: {
2859 // There is no libcall for atomic store; fake it with ATOMIC_SWAP.
2860 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
2861 cast<AtomicSDNode>(Node)->getMemoryVT(),
2862 Node->getOperand(0),
2863 Node->getOperand(1), Node->getOperand(2),
2864 cast<AtomicSDNode>(Node)->getMemOperand(),
2865 cast<AtomicSDNode>(Node)->getOrdering(),
2866 cast<AtomicSDNode>(Node)->getSynchScope());
2867 Results.push_back(Swap.getValue(1));
2870 // By default, atomic intrinsics are marked Legal and lowered. Targets
2871 // which don't support them directly, however, may want libcalls, in which
2872 // case they mark them Expand, and we get here.
2873 case ISD::ATOMIC_SWAP:
2874 case ISD::ATOMIC_LOAD_ADD:
2875 case ISD::ATOMIC_LOAD_SUB:
2876 case ISD::ATOMIC_LOAD_AND:
2877 case ISD::ATOMIC_LOAD_OR:
2878 case ISD::ATOMIC_LOAD_XOR:
2879 case ISD::ATOMIC_LOAD_NAND:
2880 case ISD::ATOMIC_LOAD_MIN:
2881 case ISD::ATOMIC_LOAD_MAX:
2882 case ISD::ATOMIC_LOAD_UMIN:
2883 case ISD::ATOMIC_LOAD_UMAX:
2884 case ISD::ATOMIC_CMP_SWAP: {
2885 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node);
2886 Results.push_back(Tmp.first);
2887 Results.push_back(Tmp.second);
2890 case ISD::DYNAMIC_STACKALLOC:
2891 ExpandDYNAMIC_STACKALLOC(Node, Results);
2893 case ISD::MERGE_VALUES:
2894 for (unsigned i = 0; i < Node->getNumValues(); i++)
2895 Results.push_back(Node->getOperand(i));
2898 EVT VT = Node->getValueType(0);
2900 Results.push_back(DAG.getConstant(0, VT));
2902 assert(VT.isFloatingPoint() && "Unknown value type!");
2903 Results.push_back(DAG.getConstantFP(0, VT));
2908 // If this operation is not supported, lower it to 'abort()' call
2909 TargetLowering::ArgListTy Args;
2911 CallLoweringInfo CLI(Node->getOperand(0),
2912 Type::getVoidTy(*DAG.getContext()),
2913 false, false, false, false, 0, CallingConv::C,
2914 /*isTailCall=*/false,
2915 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2916 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
2918 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
2920 Results.push_back(CallResult.second);
2925 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
2926 Node->getValueType(0), dl);
2927 Results.push_back(Tmp1);
2929 case ISD::FP_EXTEND:
2930 Tmp1 = EmitStackConvert(Node->getOperand(0),
2931 Node->getOperand(0).getValueType(),
2932 Node->getValueType(0), dl);
2933 Results.push_back(Tmp1);
2935 case ISD::SIGN_EXTEND_INREG: {
2936 // NOTE: we could fall back on load/store here too for targets without
2937 // SAR. However, it is doubtful that any exist.
2938 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2939 EVT VT = Node->getValueType(0);
2940 EVT ShiftAmountTy = TLI.getShiftAmountTy(VT);
2943 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
2944 ExtraVT.getScalarType().getSizeInBits();
2945 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy);
2946 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
2947 Node->getOperand(0), ShiftCst);
2948 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
2949 Results.push_back(Tmp1);
2952 case ISD::FP_ROUND_INREG: {
2953 // The only way we can lower this is to turn it into a TRUNCSTORE,
2954 // EXTLOAD pair, targeting a temporary location (a stack slot).
2956 // NOTE: there is a choice here between constantly creating new stack
2957 // slots and always reusing the same one. We currently always create
2958 // new ones, as reuse may inhibit scheduling.
2959 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2960 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
2961 Node->getValueType(0), dl);
2962 Results.push_back(Tmp1);
2965 case ISD::SINT_TO_FP:
2966 case ISD::UINT_TO_FP:
2967 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
2968 Node->getOperand(0), Node->getValueType(0), dl);
2969 Results.push_back(Tmp1);
2971 case ISD::FP_TO_UINT: {
2972 SDValue True, False;
2973 EVT VT = Node->getOperand(0).getValueType();
2974 EVT NVT = Node->getValueType(0);
2975 APFloat apf(DAG.EVTToAPFloatSemantics(VT),
2976 APInt::getNullValue(VT.getSizeInBits()));
2977 APInt x = APInt::getSignBit(NVT.getSizeInBits());
2978 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
2979 Tmp1 = DAG.getConstantFP(apf, VT);
2980 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(VT),
2981 Node->getOperand(0),
2983 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
2984 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
2985 DAG.getNode(ISD::FSUB, dl, VT,
2986 Node->getOperand(0), Tmp1));
2987 False = DAG.getNode(ISD::XOR, dl, NVT, False,
2988 DAG.getConstant(x, NVT));
2989 Tmp1 = DAG.getSelect(dl, NVT, Tmp2, True, False);
2990 Results.push_back(Tmp1);
2994 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2995 EVT VT = Node->getValueType(0);
2996 Tmp1 = Node->getOperand(0);
2997 Tmp2 = Node->getOperand(1);
2998 unsigned Align = Node->getConstantOperandVal(3);
3000 SDValue VAListLoad = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2,
3001 MachinePointerInfo(V),
3002 false, false, false, 0);
3003 SDValue VAList = VAListLoad;
3005 if (Align > TLI.getMinStackArgumentAlignment()) {
3006 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
3008 VAList = DAG.getNode(ISD::ADD, dl, VAList.getValueType(), VAList,
3009 DAG.getConstant(Align - 1,
3010 VAList.getValueType()));
3012 VAList = DAG.getNode(ISD::AND, dl, VAList.getValueType(), VAList,
3013 DAG.getConstant(-(int64_t)Align,
3014 VAList.getValueType()));
3017 // Increment the pointer, VAList, to the next vaarg
3018 Tmp3 = DAG.getNode(ISD::ADD, dl, VAList.getValueType(), VAList,
3019 DAG.getConstant(TLI.getDataLayout()->
3020 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())),
3021 VAList.getValueType()));
3022 // Store the incremented VAList to the legalized pointer
3023 Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2,
3024 MachinePointerInfo(V), false, false, 0);
3025 // Load the actual argument out of the pointer VAList
3026 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(),
3027 false, false, false, 0));
3028 Results.push_back(Results[0].getValue(1));
3032 // This defaults to loading a pointer from the input and storing it to the
3033 // output, returning the chain.
3034 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3035 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3036 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0),
3037 Node->getOperand(2), MachinePointerInfo(VS),
3038 false, false, false, 0);
3039 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1),
3040 MachinePointerInfo(VD), false, false, 0);
3041 Results.push_back(Tmp1);
3044 case ISD::EXTRACT_VECTOR_ELT:
3045 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
3046 // This must be an access of the only element. Return it.
3047 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
3048 Node->getOperand(0));
3050 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
3051 Results.push_back(Tmp1);
3053 case ISD::EXTRACT_SUBVECTOR:
3054 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
3056 case ISD::INSERT_SUBVECTOR:
3057 Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0)));
3059 case ISD::CONCAT_VECTORS: {
3060 Results.push_back(ExpandVectorBuildThroughStack(Node));
3063 case ISD::SCALAR_TO_VECTOR:
3064 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
3066 case ISD::INSERT_VECTOR_ELT:
3067 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
3068 Node->getOperand(1),
3069 Node->getOperand(2), dl));
3071 case ISD::VECTOR_SHUFFLE: {
3072 SmallVector<int, 32> NewMask;
3073 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
3075 EVT VT = Node->getValueType(0);
3076 EVT EltVT = VT.getVectorElementType();
3077 SDValue Op0 = Node->getOperand(0);
3078 SDValue Op1 = Node->getOperand(1);
3079 if (!TLI.isTypeLegal(EltVT)) {
3081 EVT NewEltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
3083 // BUILD_VECTOR operands are allowed to be wider than the element type.
3084 // But if NewEltVT is smaller that EltVT the BUILD_VECTOR does not accept it
3085 if (NewEltVT.bitsLT(EltVT)) {
3087 // Convert shuffle node.
3088 // If original node was v4i64 and the new EltVT is i32,
3089 // cast operands to v8i32 and re-build the mask.
3091 // Calculate new VT, the size of the new VT should be equal to original.
3092 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), NewEltVT,
3093 VT.getSizeInBits()/NewEltVT.getSizeInBits());
3094 assert(NewVT.bitsEq(VT));
3096 // cast operands to new VT
3097 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0);
3098 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1);
3100 // Convert the shuffle mask
3101 unsigned int factor = NewVT.getVectorNumElements()/VT.getVectorNumElements();
3103 // EltVT gets smaller
3106 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
3108 for (unsigned fi = 0; fi < factor; ++fi)
3109 NewMask.push_back(Mask[i]);
3112 for (unsigned fi = 0; fi < factor; ++fi)
3113 NewMask.push_back(Mask[i]*factor+fi);
3121 unsigned NumElems = VT.getVectorNumElements();
3122 SmallVector<SDValue, 16> Ops;
3123 for (unsigned i = 0; i != NumElems; ++i) {
3125 Ops.push_back(DAG.getUNDEF(EltVT));
3128 unsigned Idx = Mask[i];
3130 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3132 DAG.getConstant(Idx, TLI.getVectorIdxTy())));
3134 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3136 DAG.getConstant(Idx - NumElems,
3137 TLI.getVectorIdxTy())));
3140 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
3141 // We may have changed the BUILD_VECTOR type. Cast it back to the Node type.
3142 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), Tmp1);
3143 Results.push_back(Tmp1);
3146 case ISD::EXTRACT_ELEMENT: {
3147 EVT OpTy = Node->getOperand(0).getValueType();
3148 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
3150 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
3151 DAG.getConstant(OpTy.getSizeInBits()/2,
3152 TLI.getShiftAmountTy(Node->getOperand(0).getValueType())));
3153 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
3156 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
3157 Node->getOperand(0));
3159 Results.push_back(Tmp1);
3162 case ISD::STACKSAVE:
3163 // Expand to CopyFromReg if the target set
3164 // StackPointerRegisterToSaveRestore.
3165 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3166 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
3167 Node->getValueType(0)));
3168 Results.push_back(Results[0].getValue(1));
3170 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
3171 Results.push_back(Node->getOperand(0));
3174 case ISD::STACKRESTORE:
3175 // Expand to CopyToReg if the target set
3176 // StackPointerRegisterToSaveRestore.
3177 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3178 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
3179 Node->getOperand(1)));
3181 Results.push_back(Node->getOperand(0));
3184 case ISD::FCOPYSIGN:
3185 Results.push_back(ExpandFCOPYSIGN(Node));
3188 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3189 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3190 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
3191 Node->getOperand(0));
3192 Results.push_back(Tmp1);
3195 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3196 EVT VT = Node->getValueType(0);
3197 Tmp1 = Node->getOperand(0);
3198 Tmp2 = DAG.getConstantFP(0.0, VT);
3199 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(Tmp1.getValueType()),
3200 Tmp1, Tmp2, ISD::SETUGT);
3201 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
3202 Tmp1 = DAG.getSelect(dl, VT, Tmp2, Tmp1, Tmp3);
3203 Results.push_back(Tmp1);
3207 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3208 RTLIB::SQRT_F80, RTLIB::SQRT_F128,
3209 RTLIB::SQRT_PPCF128));
3213 EVT VT = Node->getValueType(0);
3214 bool isSIN = Node->getOpcode() == ISD::FSIN;
3215 // Turn fsin / fcos into ISD::FSINCOS node if there are a pair of fsin /
3216 // fcos which share the same operand and both are used.
3217 if ((TLI.isOperationLegalOrCustom(ISD::FSINCOS, VT) ||
3218 canCombineSinCosLibcall(Node, TLI, TM))
3219 && useSinCos(Node)) {
3220 SDVTList VTs = DAG.getVTList(VT, VT);
3221 Tmp1 = DAG.getNode(ISD::FSINCOS, dl, VTs, Node->getOperand(0));
3223 Tmp1 = Tmp1.getValue(1);
3224 Results.push_back(Tmp1);
3226 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
3227 RTLIB::SIN_F80, RTLIB::SIN_F128,
3228 RTLIB::SIN_PPCF128));
3230 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
3231 RTLIB::COS_F80, RTLIB::COS_F128,
3232 RTLIB::COS_PPCF128));
3237 // Expand into sincos libcall.
3238 ExpandSinCosLibCall(Node, Results);
3241 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
3242 RTLIB::LOG_F80, RTLIB::LOG_F128,
3243 RTLIB::LOG_PPCF128));
3246 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3247 RTLIB::LOG2_F80, RTLIB::LOG2_F128,
3248 RTLIB::LOG2_PPCF128));
3251 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3252 RTLIB::LOG10_F80, RTLIB::LOG10_F128,
3253 RTLIB::LOG10_PPCF128));
3256 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
3257 RTLIB::EXP_F80, RTLIB::EXP_F128,
3258 RTLIB::EXP_PPCF128));
3261 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3262 RTLIB::EXP2_F80, RTLIB::EXP2_F128,
3263 RTLIB::EXP2_PPCF128));
3266 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3267 RTLIB::TRUNC_F80, RTLIB::TRUNC_F128,
3268 RTLIB::TRUNC_PPCF128));
3271 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3272 RTLIB::FLOOR_F80, RTLIB::FLOOR_F128,
3273 RTLIB::FLOOR_PPCF128));
3276 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3277 RTLIB::CEIL_F80, RTLIB::CEIL_F128,
3278 RTLIB::CEIL_PPCF128));
3281 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
3282 RTLIB::RINT_F80, RTLIB::RINT_F128,
3283 RTLIB::RINT_PPCF128));
3285 case ISD::FNEARBYINT:
3286 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
3287 RTLIB::NEARBYINT_F64,
3288 RTLIB::NEARBYINT_F80,
3289 RTLIB::NEARBYINT_F128,
3290 RTLIB::NEARBYINT_PPCF128));
3293 Results.push_back(ExpandFPLibCall(Node, RTLIB::ROUND_F32,
3297 RTLIB::ROUND_PPCF128));
3300 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
3301 RTLIB::POWI_F80, RTLIB::POWI_F128,
3302 RTLIB::POWI_PPCF128));
3305 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
3306 RTLIB::POW_F80, RTLIB::POW_F128,
3307 RTLIB::POW_PPCF128));
3310 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
3311 RTLIB::DIV_F80, RTLIB::DIV_F128,
3312 RTLIB::DIV_PPCF128));
3315 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
3316 RTLIB::REM_F80, RTLIB::REM_F128,
3317 RTLIB::REM_PPCF128));
3320 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMA_F32, RTLIB::FMA_F64,
3321 RTLIB::FMA_F80, RTLIB::FMA_F128,
3322 RTLIB::FMA_PPCF128));
3324 case ISD::FP16_TO_FP32:
3325 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
3327 case ISD::FP32_TO_FP16:
3328 Results.push_back(ExpandLibCall(RTLIB::FPROUND_F32_F16, Node, false));
3330 case ISD::ConstantFP: {
3331 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
3332 // Check to see if this FP immediate is already legal.
3333 // If this is a legal constant, turn it into a TargetConstantFP node.
3334 if (!TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
3335 Results.push_back(ExpandConstantFP(CFP, true));
3339 EVT VT = Node->getValueType(0);
3340 assert(TLI.isOperationLegalOrCustom(ISD::FADD, VT) &&
3341 TLI.isOperationLegalOrCustom(ISD::FNEG, VT) &&
3342 "Don't know how to expand this FP subtraction!");
3343 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1));
3344 Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1);
3345 Results.push_back(Tmp1);
3349 EVT VT = Node->getValueType(0);
3350 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3351 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3352 "Don't know how to expand this subtraction!");
3353 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3354 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
3355 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, VT));
3356 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3361 EVT VT = Node->getValueType(0);
3362 bool isSigned = Node->getOpcode() == ISD::SREM;
3363 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3364 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3365 Tmp2 = Node->getOperand(0);
3366 Tmp3 = Node->getOperand(1);
3367 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3368 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3369 // If div is legal, it's better to do the normal expansion
3370 !TLI.isOperationLegalOrCustom(DivOpc, Node->getValueType(0)) &&
3371 useDivRem(Node, isSigned, false))) {
3372 SDVTList VTs = DAG.getVTList(VT, VT);
3373 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
3374 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
3376 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
3377 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3378 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3379 } else if (isSigned)
3380 Tmp1 = ExpandIntLibCall(Node, true,
3382 RTLIB::SREM_I16, RTLIB::SREM_I32,
3383 RTLIB::SREM_I64, RTLIB::SREM_I128);
3385 Tmp1 = ExpandIntLibCall(Node, false,
3387 RTLIB::UREM_I16, RTLIB::UREM_I32,
3388 RTLIB::UREM_I64, RTLIB::UREM_I128);
3389 Results.push_back(Tmp1);
3394 bool isSigned = Node->getOpcode() == ISD::SDIV;
3395 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3396 EVT VT = Node->getValueType(0);
3397 SDVTList VTs = DAG.getVTList(VT, VT);
3398 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3399 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3400 useDivRem(Node, isSigned, true)))
3401 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
3402 Node->getOperand(1));
3404 Tmp1 = ExpandIntLibCall(Node, true,
3406 RTLIB::SDIV_I16, RTLIB::SDIV_I32,
3407 RTLIB::SDIV_I64, RTLIB::SDIV_I128);
3409 Tmp1 = ExpandIntLibCall(Node, false,
3411 RTLIB::UDIV_I16, RTLIB::UDIV_I32,
3412 RTLIB::UDIV_I64, RTLIB::UDIV_I128);
3413 Results.push_back(Tmp1);
3418 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
3420 EVT VT = Node->getValueType(0);
3421 SDVTList VTs = DAG.getVTList(VT, VT);
3422 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
3423 "If this wasn't legal, it shouldn't have been created!");
3424 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
3425 Node->getOperand(1));
3426 Results.push_back(Tmp1.getValue(1));
3431 // Expand into divrem libcall
3432 ExpandDivRemLibCall(Node, Results);
3435 EVT VT = Node->getValueType(0);
3436 SDVTList VTs = DAG.getVTList(VT, VT);
3437 // See if multiply or divide can be lowered using two-result operations.
3438 // We just need the low half of the multiply; try both the signed
3439 // and unsigned forms. If the target supports both SMUL_LOHI and
3440 // UMUL_LOHI, form a preference by checking which forms of plain
3441 // MULH it supports.
3442 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3443 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3444 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3445 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3446 unsigned OpToUse = 0;
3447 if (HasSMUL_LOHI && !HasMULHS) {
3448 OpToUse = ISD::SMUL_LOHI;
3449 } else if (HasUMUL_LOHI && !HasMULHU) {
3450 OpToUse = ISD::UMUL_LOHI;
3451 } else if (HasSMUL_LOHI) {
3452 OpToUse = ISD::SMUL_LOHI;
3453 } else if (HasUMUL_LOHI) {
3454 OpToUse = ISD::UMUL_LOHI;
3457 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
3458 Node->getOperand(1)));
3461 Tmp1 = ExpandIntLibCall(Node, false,
3463 RTLIB::MUL_I16, RTLIB::MUL_I32,
3464 RTLIB::MUL_I64, RTLIB::MUL_I128);
3465 Results.push_back(Tmp1);
3470 SDValue LHS = Node->getOperand(0);
3471 SDValue RHS = Node->getOperand(1);
3472 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3473 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3475 Results.push_back(Sum);
3476 EVT OType = Node->getValueType(1);
3478 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
3480 // LHSSign -> LHS >= 0
3481 // RHSSign -> RHS >= 0
3482 // SumSign -> Sum >= 0
3485 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3487 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3489 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3490 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3491 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
3492 Node->getOpcode() == ISD::SADDO ?
3493 ISD::SETEQ : ISD::SETNE);
3495 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3496 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3498 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3499 Results.push_back(Cmp);
3504 SDValue LHS = Node->getOperand(0);
3505 SDValue RHS = Node->getOperand(1);
3506 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
3507 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3509 Results.push_back(Sum);
3510 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS,
3511 Node->getOpcode () == ISD::UADDO ?
3512 ISD::SETULT : ISD::SETUGT));
3517 EVT VT = Node->getValueType(0);
3518 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
3519 SDValue LHS = Node->getOperand(0);
3520 SDValue RHS = Node->getOperand(1);
3523 static const unsigned Ops[2][3] =
3524 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
3525 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
3526 bool isSigned = Node->getOpcode() == ISD::SMULO;
3527 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3528 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3529 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3530 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3531 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3533 TopHalf = BottomHalf.getValue(1);
3534 } else if (TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(),
3535 VT.getSizeInBits() * 2))) {
3536 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
3537 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
3538 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
3539 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3540 DAG.getIntPtrConstant(0));
3541 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3542 DAG.getIntPtrConstant(1));
3544 // We can fall back to a libcall with an illegal type for the MUL if we
3545 // have a libcall big enough.
3546 // Also, we can fall back to a division in some cases, but that's a big
3547 // performance hit in the general case.
3548 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3549 if (WideVT == MVT::i16)
3550 LC = RTLIB::MUL_I16;
3551 else if (WideVT == MVT::i32)
3552 LC = RTLIB::MUL_I32;
3553 else if (WideVT == MVT::i64)
3554 LC = RTLIB::MUL_I64;
3555 else if (WideVT == MVT::i128)
3556 LC = RTLIB::MUL_I128;
3557 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!");
3559 // The high part is obtained by SRA'ing all but one of the bits of low
3561 unsigned LoSize = VT.getSizeInBits();
3562 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, RHS,
3563 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
3564 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, VT, LHS,
3565 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
3567 // Here we're passing the 2 arguments explicitly as 4 arguments that are
3568 // pre-lowered to the correct types. This all depends upon WideVT not
3569 // being a legal type for the architecture and thus has to be split to
3571 SDValue Args[] = { LHS, HiLHS, RHS, HiRHS };
3572 SDValue Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl);
3573 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3574 DAG.getIntPtrConstant(0));
3575 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3576 DAG.getIntPtrConstant(1));
3577 // Ret is a node with an illegal type. Because such things are not
3578 // generally permitted during this phase of legalization, delete the
3579 // node. The above EXTRACT_ELEMENT nodes should have been folded.
3580 DAG.DeleteNode(Ret.getNode());
3584 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1,
3585 TLI.getShiftAmountTy(BottomHalf.getValueType()));
3586 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3587 TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf, Tmp1,
3590 TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf,
3591 DAG.getConstant(0, VT), ISD::SETNE);
3593 Results.push_back(BottomHalf);
3594 Results.push_back(TopHalf);
3597 case ISD::BUILD_PAIR: {
3598 EVT PairTy = Node->getValueType(0);
3599 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3600 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3601 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
3602 DAG.getConstant(PairTy.getSizeInBits()/2,
3603 TLI.getShiftAmountTy(PairTy)));
3604 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3608 Tmp1 = Node->getOperand(0);
3609 Tmp2 = Node->getOperand(1);
3610 Tmp3 = Node->getOperand(2);
3611 if (Tmp1.getOpcode() == ISD::SETCC) {
3612 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3614 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3616 Tmp1 = DAG.getSelectCC(dl, Tmp1,
3617 DAG.getConstant(0, Tmp1.getValueType()),
3618 Tmp2, Tmp3, ISD::SETNE);
3620 Results.push_back(Tmp1);
3623 SDValue Chain = Node->getOperand(0);
3624 SDValue Table = Node->getOperand(1);
3625 SDValue Index = Node->getOperand(2);
3627 EVT PTy = TLI.getPointerTy();
3629 const DataLayout &TD = *TLI.getDataLayout();
3630 unsigned EntrySize =
3631 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
3633 Index = DAG.getNode(ISD::MUL, dl, Index.getValueType(),
3634 Index, DAG.getConstant(EntrySize, Index.getValueType()));
3635 SDValue Addr = DAG.getNode(ISD::ADD, dl, Index.getValueType(),
3638 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
3639 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
3640 MachinePointerInfo::getJumpTable(), MemVT,
3643 if (TM.getRelocationModel() == Reloc::PIC_) {
3644 // For PIC, the sequence is:
3645 // BRIND(load(Jumptable + index) + RelocBase)
3646 // RelocBase can be JumpTable, GOT or some sort of global base.
3647 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3648 TLI.getPICJumpTableRelocBase(Table, DAG));
3650 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
3651 Results.push_back(Tmp1);
3655 // Expand brcond's setcc into its constituent parts and create a BR_CC
3657 Tmp1 = Node->getOperand(0);
3658 Tmp2 = Node->getOperand(1);
3659 if (Tmp2.getOpcode() == ISD::SETCC) {
3660 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3661 Tmp1, Tmp2.getOperand(2),
3662 Tmp2.getOperand(0), Tmp2.getOperand(1),
3663 Node->getOperand(2));
3665 // We test only the i1 bit. Skip the AND if UNDEF.
3666 Tmp3 = (Tmp2.getOpcode() == ISD::UNDEF) ? Tmp2 :
3667 DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2,
3668 DAG.getConstant(1, Tmp2.getValueType()));
3669 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3670 DAG.getCondCode(ISD::SETNE), Tmp3,
3671 DAG.getConstant(0, Tmp3.getValueType()),
3672 Node->getOperand(2));
3674 Results.push_back(Tmp1);
3677 Tmp1 = Node->getOperand(0);
3678 Tmp2 = Node->getOperand(1);
3679 Tmp3 = Node->getOperand(2);
3680 bool Legalized = LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2,
3684 // If we exapanded the SETCC by swapping LHS and RHS, create a new SETCC
3687 Tmp1 = DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3690 Results.push_back(Tmp1);
3694 // Otherwise, SETCC for the given comparison type must be completely
3695 // illegal; expand it into a SELECT_CC.
3696 EVT VT = Node->getValueType(0);
3698 switch (TLI.getBooleanContents(VT.isVector())) {
3699 case TargetLowering::ZeroOrOneBooleanContent:
3700 case TargetLowering::UndefinedBooleanContent:
3703 case TargetLowering::ZeroOrNegativeOneBooleanContent:
3707 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3708 DAG.getConstant(TrueValue, VT), DAG.getConstant(0, VT),
3710 Results.push_back(Tmp1);
3713 case ISD::SELECT_CC: {
3714 Tmp1 = Node->getOperand(0); // LHS
3715 Tmp2 = Node->getOperand(1); // RHS
3716 Tmp3 = Node->getOperand(2); // True
3717 Tmp4 = Node->getOperand(3); // False
3718 SDValue CC = Node->getOperand(4);
3720 bool Legalized = false;
3721 // Try to legalize by inverting the condition. This is for targets that
3722 // might support an ordered version of a condition, but not the unordered
3723 // version (or vice versa).
3724 ISD::CondCode InvCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
3725 Tmp1.getValueType().isInteger());
3726 if (TLI.isCondCodeLegal(InvCC, Tmp1.getSimpleValueType())) {
3727 // Use the new condition code and swap true and false
3729 Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp4, Tmp3, InvCC);
3731 // If The inverse is not legal, then try to swap the arguments using
3732 // the inverse condition code.
3733 ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(InvCC);
3734 if (TLI.isCondCodeLegal(SwapInvCC, Tmp1.getSimpleValueType())) {
3735 // The swapped inverse condition is legal, so swap true and false,
3738 Tmp1 = DAG.getSelectCC(dl, Tmp2, Tmp1, Tmp4, Tmp3, SwapInvCC);
3743 Legalized = LegalizeSetCCCondCode(
3744 getSetCCResultType(Tmp1.getValueType()), Tmp1, Tmp2, CC, dl);
3746 assert(Legalized && "Can't legalize SELECT_CC with legal condition!");
3747 // If we exapanded the SETCC by swapping LHS and RHS, create a new
3750 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0),
3751 Tmp1, Tmp2, Tmp3, Tmp4, CC);
3753 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3754 CC = DAG.getCondCode(ISD::SETNE);
3755 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2,
3759 Results.push_back(Tmp1);
3763 Tmp1 = Node->getOperand(0); // Chain
3764 Tmp2 = Node->getOperand(2); // LHS
3765 Tmp3 = Node->getOperand(3); // RHS
3766 Tmp4 = Node->getOperand(1); // CC
3768 bool Legalized = LegalizeSetCCCondCode(getSetCCResultType(
3769 Tmp2.getValueType()), Tmp2, Tmp3, Tmp4, dl);
3771 assert(Legalized && "Can't legalize BR_CC with legal condition!");
3773 // If we exapanded the SETCC by swapping LHS and RHS, create a new BR_CC
3775 if (Tmp4.getNode()) {
3776 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1,
3777 Tmp4, Tmp2, Tmp3, Node->getOperand(4));
3779 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
3780 Tmp4 = DAG.getCondCode(ISD::SETNE);
3781 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2,
3782 Tmp3, Node->getOperand(4));
3784 Results.push_back(Tmp1);
3787 case ISD::BUILD_VECTOR:
3788 Results.push_back(ExpandBUILD_VECTOR(Node));
3793 // Scalarize vector SRA/SRL/SHL.
3794 EVT VT = Node->getValueType(0);
3795 assert(VT.isVector() && "Unable to legalize non-vector shift");
3796 assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
3797 unsigned NumElem = VT.getVectorNumElements();
3799 SmallVector<SDValue, 8> Scalars;
3800 for (unsigned Idx = 0; Idx < NumElem; Idx++) {
3801 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3803 Node->getOperand(0), DAG.getConstant(Idx,
3804 TLI.getVectorIdxTy()));
3805 SDValue Sh = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3807 Node->getOperand(1), DAG.getConstant(Idx,
3808 TLI.getVectorIdxTy()));
3809 Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
3810 VT.getScalarType(), Ex, Sh));
3813 DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0),
3814 &Scalars[0], Scalars.size());
3815 ReplaceNode(SDValue(Node, 0), Result);
3818 case ISD::GLOBAL_OFFSET_TABLE:
3819 case ISD::GlobalAddress:
3820 case ISD::GlobalTLSAddress:
3821 case ISD::ExternalSymbol:
3822 case ISD::ConstantPool:
3823 case ISD::JumpTable:
3824 case ISD::INTRINSIC_W_CHAIN:
3825 case ISD::INTRINSIC_WO_CHAIN:
3826 case ISD::INTRINSIC_VOID:
3827 // FIXME: Custom lowering for these operations shouldn't return null!
3831 // Replace the original node with the legalized result.
3832 if (!Results.empty())
3833 ReplaceNode(Node, Results.data());
3836 void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
3837 SmallVector<SDValue, 8> Results;
3838 MVT OVT = Node->getSimpleValueType(0);
3839 if (Node->getOpcode() == ISD::UINT_TO_FP ||
3840 Node->getOpcode() == ISD::SINT_TO_FP ||
3841 Node->getOpcode() == ISD::SETCC) {
3842 OVT = Node->getOperand(0).getSimpleValueType();
3844 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3846 SDValue Tmp1, Tmp2, Tmp3;
3847 switch (Node->getOpcode()) {
3849 case ISD::CTTZ_ZERO_UNDEF:
3851 case ISD::CTLZ_ZERO_UNDEF:
3853 // Zero extend the argument.
3854 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3855 // Perform the larger operation. For CTPOP and CTTZ_ZERO_UNDEF, this is
3856 // already the correct result.
3857 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
3858 if (Node->getOpcode() == ISD::CTTZ) {
3859 // FIXME: This should set a bit in the zero extended value instead.
3860 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT),
3861 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
3863 Tmp1 = DAG.getSelect(dl, NVT, Tmp2,
3864 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3865 } else if (Node->getOpcode() == ISD::CTLZ ||
3866 Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) {
3867 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3868 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
3869 DAG.getConstant(NVT.getSizeInBits() -
3870 OVT.getSizeInBits(), NVT));
3872 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
3875 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3876 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3877 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
3878 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
3879 DAG.getConstant(DiffBits, TLI.getShiftAmountTy(NVT)));
3880 Results.push_back(Tmp1);
3883 case ISD::FP_TO_UINT:
3884 case ISD::FP_TO_SINT:
3885 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
3886 Node->getOpcode() == ISD::FP_TO_SINT, dl);
3887 Results.push_back(Tmp1);
3889 case ISD::UINT_TO_FP:
3890 case ISD::SINT_TO_FP:
3891 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
3892 Node->getOpcode() == ISD::SINT_TO_FP, dl);
3893 Results.push_back(Tmp1);
3896 SDValue Chain = Node->getOperand(0); // Get the chain.
3897 SDValue Ptr = Node->getOperand(1); // Get the pointer.
3900 if (OVT.isVector()) {
3901 TruncOp = ISD::BITCAST;
3903 assert(OVT.isInteger()
3904 && "VAARG promotion is supported only for vectors or integer types");
3905 TruncOp = ISD::TRUNCATE;
3908 // Perform the larger operation, then convert back
3909 Tmp1 = DAG.getVAArg(NVT, dl, Chain, Ptr, Node->getOperand(2),
3910 Node->getConstantOperandVal(3));
3911 Chain = Tmp1.getValue(1);
3913 Tmp2 = DAG.getNode(TruncOp, dl, OVT, Tmp1);
3915 // Modified the chain result - switch anything that used the old chain to
3917 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp2);
3918 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
3925 unsigned ExtOp, TruncOp;
3926 if (OVT.isVector()) {
3927 ExtOp = ISD::BITCAST;
3928 TruncOp = ISD::BITCAST;
3930 assert(OVT.isInteger() && "Cannot promote logic operation");
3931 ExtOp = ISD::ANY_EXTEND;
3932 TruncOp = ISD::TRUNCATE;
3934 // Promote each of the values to the new type.
3935 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3936 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3937 // Perform the larger operation, then convert back
3938 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3939 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
3943 unsigned ExtOp, TruncOp;
3944 if (Node->getValueType(0).isVector()) {
3945 ExtOp = ISD::BITCAST;
3946 TruncOp = ISD::BITCAST;
3947 } else if (Node->getValueType(0).isInteger()) {
3948 ExtOp = ISD::ANY_EXTEND;
3949 TruncOp = ISD::TRUNCATE;
3951 ExtOp = ISD::FP_EXTEND;
3952 TruncOp = ISD::FP_ROUND;
3954 Tmp1 = Node->getOperand(0);
3955 // Promote each of the values to the new type.
3956 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3957 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
3958 // Perform the larger operation, then round down.
3959 Tmp1 = DAG.getSelect(dl, NVT, Tmp1, Tmp2, Tmp3);
3960 if (TruncOp != ISD::FP_ROUND)
3961 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
3963 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
3964 DAG.getIntPtrConstant(0));
3965 Results.push_back(Tmp1);
3968 case ISD::VECTOR_SHUFFLE: {
3969 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
3971 // Cast the two input vectors.
3972 Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
3973 Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
3975 // Convert the shuffle mask to the right # elements.
3976 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
3977 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
3978 Results.push_back(Tmp1);
3982 unsigned ExtOp = ISD::FP_EXTEND;
3983 if (NVT.isInteger()) {
3984 ISD::CondCode CCCode =
3985 cast<CondCodeSDNode>(Node->getOperand(2))->get();
3986 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3988 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3989 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3990 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3991 Tmp1, Tmp2, Node->getOperand(2)));
3997 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
3998 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
3999 Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4000 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4001 Tmp3, DAG.getIntPtrConstant(0)));
4008 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4009 Tmp2 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4010 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4011 Tmp2, DAG.getIntPtrConstant(0)));
4016 // Replace the original node with the legalized result.
4017 if (!Results.empty())
4018 ReplaceNode(Node, Results.data());
4021 // SelectionDAG::Legalize - This is the entry point for the file.
4023 void SelectionDAG::Legalize() {
4024 /// run - This is the main entry point to this class.
4026 SelectionDAGLegalize(*this).LegalizeDAG();