1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/CodeGen/DwarfWriter.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/CodeGen/PseudoSourceValue.h"
22 #include "llvm/Target/TargetFrameInfo.h"
23 #include "llvm/Target/TargetLowering.h"
24 #include "llvm/Target/TargetData.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Target/TargetSubtarget.h"
28 #include "llvm/CallingConv.h"
29 #include "llvm/Constants.h"
30 #include "llvm/DerivedTypes.h"
31 #include "llvm/Function.h"
32 #include "llvm/GlobalVariable.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Compiler.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/ADT/DenseMap.h"
37 #include "llvm/ADT/SmallVector.h"
38 #include "llvm/ADT/SmallPtrSet.h"
42 //===----------------------------------------------------------------------===//
43 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
44 /// hacks on it until the target machine can handle it. This involves
45 /// eliminating value sizes the machine cannot handle (promoting small sizes to
46 /// large sizes or splitting up large values into small values) as well as
47 /// eliminating operations the machine cannot handle.
49 /// This code also does a small amount of optimization and recognition of idioms
50 /// as part of its processing. For example, if a target does not support a
51 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
52 /// will attempt merge setcc and brc instructions into brcc's.
55 class VISIBILITY_HIDDEN SelectionDAGLegalize {
58 CodeGenOpt::Level OptLevel;
59 bool TypesNeedLegalizing;
61 // Libcall insertion helpers.
63 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
64 /// legalized. We use this to ensure that calls are properly serialized
65 /// against each other, including inserted libcalls.
66 SDValue LastCALLSEQ_END;
68 /// IsLegalizingCall - This member is used *only* for purposes of providing
69 /// helpful assertions that a libcall isn't created while another call is
70 /// being legalized (which could lead to non-serialized call sequences).
71 bool IsLegalizingCall;
73 /// IsLegalizingCallArguments - This member is used only for the purpose
74 /// of providing assert to check for LegalizeTypes because legalizing an
75 /// operation might introduce call nodes that might need type legalization.
76 bool IsLegalizingCallArgs;
79 Legal, // The target natively supports this operation.
80 Promote, // This operation should be executed in a larger type.
81 Expand // Try to expand this to other ops, otherwise use a libcall.
84 /// ValueTypeActions - This is a bitvector that contains two bits for each
85 /// value type, where the two bits correspond to the LegalizeAction enum.
86 /// This can be queried with "getTypeAction(VT)".
87 TargetLowering::ValueTypeActionImpl ValueTypeActions;
89 /// LegalizedNodes - For nodes that are of legal width, and that have more
90 /// than one use, this map indicates what regularized operand to use. This
91 /// allows us to avoid legalizing the same thing more than once.
92 DenseMap<SDValue, SDValue> LegalizedNodes;
94 /// PromotedNodes - For nodes that are below legal width, and that have more
95 /// than one use, this map indicates what promoted value to use. This allows
96 /// us to avoid promoting the same thing more than once.
97 DenseMap<SDValue, SDValue> PromotedNodes;
99 /// ExpandedNodes - For nodes that need to be expanded this map indicates
100 /// which operands are the expanded version of the input. This allows
101 /// us to avoid expanding the same node more than once.
102 DenseMap<SDValue, std::pair<SDValue, SDValue> > ExpandedNodes;
104 /// SplitNodes - For vector nodes that need to be split, this map indicates
105 /// which operands are the split version of the input. This allows us
106 /// to avoid splitting the same node more than once.
107 std::map<SDValue, std::pair<SDValue, SDValue> > SplitNodes;
109 /// ScalarizedNodes - For nodes that need to be converted from vector types to
110 /// scalar types, this contains the mapping of ones we have already
111 /// processed to the result.
112 std::map<SDValue, SDValue> ScalarizedNodes;
114 /// WidenNodes - For nodes that need to be widened from one vector type to
115 /// another, this contains the mapping of those that we have already widen.
116 /// This allows us to avoid widening more than once.
117 std::map<SDValue, SDValue> WidenNodes;
119 void AddLegalizedOperand(SDValue From, SDValue To) {
120 LegalizedNodes.insert(std::make_pair(From, To));
121 // If someone requests legalization of the new node, return itself.
123 LegalizedNodes.insert(std::make_pair(To, To));
125 void AddPromotedOperand(SDValue From, SDValue To) {
126 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
127 assert(isNew && "Got into the map somehow?");
129 // If someone requests legalization of the new node, return itself.
130 LegalizedNodes.insert(std::make_pair(To, To));
132 void AddWidenedOperand(SDValue From, SDValue To) {
133 bool isNew = WidenNodes.insert(std::make_pair(From, To)).second;
134 assert(isNew && "Got into the map somehow?");
136 // If someone requests legalization of the new node, return itself.
137 LegalizedNodes.insert(std::make_pair(To, To));
141 explicit SelectionDAGLegalize(SelectionDAG &DAG, bool TypesNeedLegalizing,
142 CodeGenOpt::Level ol);
144 /// getTypeAction - Return how we should legalize values of this type, either
145 /// it is already legal or we need to expand it into multiple registers of
146 /// smaller integer type, or we need to promote it to a larger type.
147 LegalizeAction getTypeAction(MVT VT) const {
148 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
151 /// isTypeLegal - Return true if this type is legal on this target.
153 bool isTypeLegal(MVT VT) const {
154 return getTypeAction(VT) == Legal;
160 /// HandleOp - Legalize, Promote, or Expand the specified operand as
161 /// appropriate for its type.
162 void HandleOp(SDValue Op);
164 /// LegalizeOp - We know that the specified value has a legal type.
165 /// Recursively ensure that the operands have legal types, then return the
167 SDValue LegalizeOp(SDValue O);
169 /// UnrollVectorOp - We know that the given vector has a legal type, however
170 /// the operation it performs is not legal and is an operation that we have
171 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
172 /// operating on each element individually.
173 SDValue UnrollVectorOp(SDValue O);
175 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
176 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
177 /// is necessary to spill the vector being inserted into to memory, perform
178 /// the insert there, and then read the result back.
179 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
180 SDValue Idx, DebugLoc dl);
182 /// PromoteOp - Given an operation that produces a value in an invalid type,
183 /// promote it to compute the value into a larger type. The produced value
184 /// will have the correct bits for the low portion of the register, but no
185 /// guarantee is made about the top bits: it may be zero, sign-extended, or
187 SDValue PromoteOp(SDValue O);
189 /// ExpandOp - Expand the specified SDValue into its two component pieces
190 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
191 /// the LegalizedNodes map is filled in for any results that are not expanded,
192 /// the ExpandedNodes map is filled in for any results that are expanded, and
193 /// the Lo/Hi values are returned. This applies to integer types and Vector
195 void ExpandOp(SDValue O, SDValue &Lo, SDValue &Hi);
197 /// WidenVectorOp - Widen a vector operation to a wider type given by WidenVT
198 /// (e.g., v3i32 to v4i32). The produced value will have the correct value
199 /// for the existing elements but no guarantee is made about the new elements
200 /// at the end of the vector: it may be zero, ones, or garbage. This is useful
201 /// when we have an instruction operating on an illegal vector type and we
202 /// want to widen it to do the computation on a legal wider vector type.
203 SDValue WidenVectorOp(SDValue Op, MVT WidenVT);
205 /// SplitVectorOp - Given an operand of vector type, break it down into
206 /// two smaller values.
207 void SplitVectorOp(SDValue O, SDValue &Lo, SDValue &Hi);
209 /// ScalarizeVectorOp - Given an operand of single-element vector type
210 /// (e.g. v1f32), convert it into the equivalent operation that returns a
211 /// scalar (e.g. f32) value.
212 SDValue ScalarizeVectorOp(SDValue O);
214 /// Useful 16 element vector type that is used to pass operands for widening.
215 typedef SmallVector<SDValue, 16> SDValueVector;
217 /// LoadWidenVectorOp - Load a vector for a wider type. Returns true if
218 /// the LdChain contains a single load and false if it contains a token
219 /// factor for multiple loads. It takes
220 /// Result: location to return the result
221 /// LdChain: location to return the load chain
222 /// Op: load operation to widen
223 /// NVT: widen vector result type we want for the load
224 bool LoadWidenVectorOp(SDValue& Result, SDValue& LdChain,
225 SDValue Op, MVT NVT);
227 /// Helper genWidenVectorLoads - Helper function to generate a set of
228 /// loads to load a vector with a resulting wider type. It takes
229 /// LdChain: list of chains for the load we have generated
230 /// Chain: incoming chain for the ld vector
231 /// BasePtr: base pointer to load from
232 /// SV: memory disambiguation source value
233 /// SVOffset: memory disambiugation offset
234 /// Alignment: alignment of the memory
235 /// isVolatile: volatile load
236 /// LdWidth: width of memory that we want to load
237 /// ResType: the wider result result type for the resulting loaded vector
238 SDValue genWidenVectorLoads(SDValueVector& LdChain, SDValue Chain,
239 SDValue BasePtr, const Value *SV,
240 int SVOffset, unsigned Alignment,
241 bool isVolatile, unsigned LdWidth,
242 MVT ResType, DebugLoc dl);
244 /// StoreWidenVectorOp - Stores a widen vector into non widen memory
245 /// location. It takes
246 /// ST: store node that we want to replace
247 /// Chain: incoming store chain
248 /// BasePtr: base address of where we want to store into
249 SDValue StoreWidenVectorOp(StoreSDNode *ST, SDValue Chain,
252 /// Helper genWidenVectorStores - Helper function to generate a set of
253 /// stores to store a widen vector into non widen memory
255 // StChain: list of chains for the stores we have generated
256 // Chain: incoming chain for the ld vector
257 // BasePtr: base pointer to load from
258 // SV: memory disambiguation source value
259 // SVOffset: memory disambiugation offset
260 // Alignment: alignment of the memory
261 // isVolatile: volatile lod
262 // ValOp: value to store
263 // StWidth: width of memory that we want to store
264 void genWidenVectorStores(SDValueVector& StChain, SDValue Chain,
265 SDValue BasePtr, const Value *SV,
266 int SVOffset, unsigned Alignment,
267 bool isVolatile, SDValue ValOp,
268 unsigned StWidth, DebugLoc dl);
270 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
271 /// performs the same shuffe in terms of order or result bytes, but on a type
272 /// whose vector element type is narrower than the original shuffle type.
273 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
274 SDValue ShuffleWithNarrowerEltType(MVT NVT, MVT VT, DebugLoc dl,
275 SDValue N1, SDValue N2,
276 SmallVectorImpl<int> &Mask) const;
278 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
279 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
281 void LegalizeSetCCOperands(SDValue &LHS, SDValue &RHS, SDValue &CC,
283 void LegalizeSetCCCondCode(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
285 void LegalizeSetCC(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
287 LegalizeSetCCOperands(LHS, RHS, CC, dl);
288 LegalizeSetCCCondCode(VT, LHS, RHS, CC, dl);
291 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned,
293 SDValue ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source, DebugLoc dl);
295 SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT, DebugLoc dl);
296 SDValue ExpandBUILD_VECTOR(SDNode *Node);
297 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
298 SDValue LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy,
299 SDValue Op, DebugLoc dl);
300 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT,
302 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, bool isSigned,
304 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned,
307 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl);
308 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl);
309 bool ExpandShift(unsigned Opc, SDValue Op, SDValue Amt,
310 SDValue &Lo, SDValue &Hi, DebugLoc dl);
311 void ExpandShiftParts(unsigned NodeOp, SDValue Op, SDValue Amt,
312 SDValue &Lo, SDValue &Hi, DebugLoc dl);
314 SDValue ExpandEXTRACT_SUBVECTOR(SDValue Op);
315 SDValue ExpandEXTRACT_VECTOR_ELT(SDValue Op);
319 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
320 /// performs the same shuffe in terms of order or result bytes, but on a type
321 /// whose vector element type is narrower than the original shuffle type.
322 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
324 SelectionDAGLegalize::ShuffleWithNarrowerEltType(MVT NVT, MVT VT, DebugLoc dl,
325 SDValue N1, SDValue N2,
326 SmallVectorImpl<int> &Mask) const {
327 MVT EltVT = NVT.getVectorElementType();
328 unsigned NumMaskElts = VT.getVectorNumElements();
329 unsigned NumDestElts = NVT.getVectorNumElements();
330 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
332 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
334 if (NumEltsGrowth == 1)
335 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
337 SmallVector<int, 8> NewMask;
338 for (unsigned i = 0; i != NumMaskElts; ++i) {
340 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
342 NewMask.push_back(-1);
344 NewMask.push_back(Idx * NumEltsGrowth + j);
347 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
348 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
349 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
352 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag,
353 bool types, CodeGenOpt::Level ol)
354 : TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol),
355 TypesNeedLegalizing(types), ValueTypeActions(TLI.getValueTypeActions()) {
356 assert(MVT::LAST_VALUETYPE <= 32 &&
357 "Too many value types for ValueTypeActions to hold!");
360 void SelectionDAGLegalize::LegalizeDAG() {
361 LastCALLSEQ_END = DAG.getEntryNode();
362 IsLegalizingCall = false;
363 IsLegalizingCallArgs = false;
365 // The legalize process is inherently a bottom-up recursive process (users
366 // legalize their uses before themselves). Given infinite stack space, we
367 // could just start legalizing on the root and traverse the whole graph. In
368 // practice however, this causes us to run out of stack space on large basic
369 // blocks. To avoid this problem, compute an ordering of the nodes where each
370 // node is only legalized after all of its operands are legalized.
371 DAG.AssignTopologicalOrder();
372 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
373 E = prior(DAG.allnodes_end()); I != next(E); ++I)
374 HandleOp(SDValue(I, 0));
376 // Finally, it's possible the root changed. Get the new root.
377 SDValue OldRoot = DAG.getRoot();
378 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
379 DAG.setRoot(LegalizedNodes[OldRoot]);
381 ExpandedNodes.clear();
382 LegalizedNodes.clear();
383 PromotedNodes.clear();
385 ScalarizedNodes.clear();
388 // Remove dead nodes now.
389 DAG.RemoveDeadNodes();
393 /// FindCallEndFromCallStart - Given a chained node that is part of a call
394 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
395 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
396 if (Node->getOpcode() == ISD::CALLSEQ_END)
398 if (Node->use_empty())
399 return 0; // No CallSeqEnd
401 // The chain is usually at the end.
402 SDValue TheChain(Node, Node->getNumValues()-1);
403 if (TheChain.getValueType() != MVT::Other) {
404 // Sometimes it's at the beginning.
405 TheChain = SDValue(Node, 0);
406 if (TheChain.getValueType() != MVT::Other) {
407 // Otherwise, hunt for it.
408 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
409 if (Node->getValueType(i) == MVT::Other) {
410 TheChain = SDValue(Node, i);
414 // Otherwise, we walked into a node without a chain.
415 if (TheChain.getValueType() != MVT::Other)
420 for (SDNode::use_iterator UI = Node->use_begin(),
421 E = Node->use_end(); UI != E; ++UI) {
423 // Make sure to only follow users of our token chain.
425 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
426 if (User->getOperand(i) == TheChain)
427 if (SDNode *Result = FindCallEndFromCallStart(User))
433 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
434 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
435 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
436 assert(Node && "Didn't find callseq_start for a call??");
437 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
439 assert(Node->getOperand(0).getValueType() == MVT::Other &&
440 "Node doesn't have a token chain argument!");
441 return FindCallStartFromCallEnd(Node->getOperand(0).getNode());
444 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
445 /// see if any uses can reach Dest. If no dest operands can get to dest,
446 /// legalize them, legalize ourself, and return false, otherwise, return true.
448 /// Keep track of the nodes we fine that actually do lead to Dest in
449 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
451 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
452 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
453 if (N == Dest) return true; // N certainly leads to Dest :)
455 // If we've already processed this node and it does lead to Dest, there is no
456 // need to reprocess it.
457 if (NodesLeadingTo.count(N)) return true;
459 // If the first result of this node has been already legalized, then it cannot
461 switch (getTypeAction(N->getValueType(0))) {
463 if (LegalizedNodes.count(SDValue(N, 0))) return false;
466 if (PromotedNodes.count(SDValue(N, 0))) return false;
469 if (ExpandedNodes.count(SDValue(N, 0))) return false;
473 // Okay, this node has not already been legalized. Check and legalize all
474 // operands. If none lead to Dest, then we can legalize this node.
475 bool OperandsLeadToDest = false;
476 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
477 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
478 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo);
480 if (OperandsLeadToDest) {
481 NodesLeadingTo.insert(N);
485 // Okay, this node looks safe, legalize it and return false.
486 HandleOp(SDValue(N, 0));
490 /// HandleOp - Legalize, Promote, Widen, or Expand the specified operand as
491 /// appropriate for its type.
492 void SelectionDAGLegalize::HandleOp(SDValue Op) {
493 MVT VT = Op.getValueType();
494 // If the type legalizer was run then we should never see any illegal result
495 // types here except for target constants (the type legalizer does not touch
496 // those) or for build vector used as a mask for a vector shuffle.
497 assert((TypesNeedLegalizing || getTypeAction(VT) == Legal ||
498 IsLegalizingCallArgs || Op.getOpcode() == ISD::TargetConstant) &&
499 "Illegal type introduced after type legalization?");
500 switch (getTypeAction(VT)) {
501 default: assert(0 && "Bad type action!");
502 case Legal: (void)LegalizeOp(Op); break;
504 if (!VT.isVector()) {
509 // See if we can widen otherwise use Expand to either scalarize or split
510 MVT WidenVT = TLI.getWidenVectorType(VT);
511 if (WidenVT != MVT::Other) {
512 (void) WidenVectorOp(Op, WidenVT);
515 // else fall thru to expand since we can't widen the vector
518 if (!VT.isVector()) {
519 // If this is an illegal scalar, expand it into its two component
522 if (Op.getOpcode() == ISD::TargetConstant)
523 break; // Allow illegal target nodes.
525 } else if (VT.getVectorNumElements() == 1) {
526 // If this is an illegal single element vector, convert it to a
528 (void)ScalarizeVectorOp(Op);
530 // This is an illegal multiple element vector.
531 // Split it in half and legalize both parts.
533 SplitVectorOp(Op, X, Y);
539 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
540 /// a load from the constant pool.
541 static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
542 SelectionDAG &DAG, const TargetLowering &TLI) {
544 DebugLoc dl = CFP->getDebugLoc();
546 // If a FP immediate is precise when represented as a float and if the
547 // target can do an extending load from float to double, we put it into
548 // the constant pool as a float, even if it's is statically typed as a
549 // double. This shrinks FP constants and canonicalizes them for targets where
550 // an FP extending load is the same cost as a normal load (such as on the x87
551 // fp stack or PPC FP unit).
552 MVT VT = CFP->getValueType(0);
553 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
555 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
556 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
557 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
562 while (SVT != MVT::f32) {
563 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1);
564 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
565 // Only do this if the target has a native EXTLOAD instruction from
567 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
568 TLI.ShouldShrinkFPConstant(OrigVT)) {
569 const Type *SType = SVT.getTypeForMVT();
570 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
576 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
577 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
579 return DAG.getExtLoad(ISD::EXTLOAD, dl,
580 OrigVT, DAG.getEntryNode(),
581 CPIdx, PseudoSourceValue::getConstantPool(),
582 0, VT, false, Alignment);
583 return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
584 PseudoSourceValue::getConstantPool(), 0, false, Alignment);
588 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
591 SDValue ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT,
593 const TargetLowering &TLI) {
594 DebugLoc dl = Node->getDebugLoc();
595 MVT VT = Node->getValueType(0);
596 MVT SrcVT = Node->getOperand(1).getValueType();
597 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
598 "fcopysign expansion only supported for f32 and f64");
599 MVT SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
601 // First get the sign bit of second operand.
602 SDValue Mask1 = (SrcVT == MVT::f64)
603 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
604 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
605 Mask1 = DAG.getNode(ISD::BIT_CONVERT, dl, SrcNVT, Mask1);
606 SDValue SignBit= DAG.getNode(ISD::BIT_CONVERT, dl, SrcNVT,
607 Node->getOperand(1));
608 SignBit = DAG.getNode(ISD::AND, dl, SrcNVT, SignBit, Mask1);
609 // Shift right or sign-extend it if the two operands have different types.
610 int SizeDiff = SrcNVT.getSizeInBits() - NVT.getSizeInBits();
612 SignBit = DAG.getNode(ISD::SRL, dl, SrcNVT, SignBit,
613 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
614 SignBit = DAG.getNode(ISD::TRUNCATE, dl, NVT, SignBit);
615 } else if (SizeDiff < 0) {
616 SignBit = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, SignBit);
617 SignBit = DAG.getNode(ISD::SHL, dl, NVT, SignBit,
618 DAG.getConstant(-SizeDiff, TLI.getShiftAmountTy()));
621 // Clear the sign bit of first operand.
622 SDValue Mask2 = (VT == MVT::f64)
623 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
624 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
625 Mask2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Mask2);
626 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
627 Result = DAG.getNode(ISD::AND, dl, NVT, Result, Mask2);
629 // Or the value with the sign bit.
630 Result = DAG.getNode(ISD::OR, dl, NVT, Result, SignBit);
634 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
636 SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
637 const TargetLowering &TLI) {
638 SDValue Chain = ST->getChain();
639 SDValue Ptr = ST->getBasePtr();
640 SDValue Val = ST->getValue();
641 MVT VT = Val.getValueType();
642 int Alignment = ST->getAlignment();
643 int SVOffset = ST->getSrcValueOffset();
644 DebugLoc dl = ST->getDebugLoc();
645 if (ST->getMemoryVT().isFloatingPoint() ||
646 ST->getMemoryVT().isVector()) {
647 MVT intVT = MVT::getIntegerVT(VT.getSizeInBits());
648 if (TLI.isTypeLegal(intVT)) {
649 // Expand to a bitconvert of the value to the integer type of the
650 // same size, then a (misaligned) int store.
651 // FIXME: Does not handle truncating floating point stores!
652 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, intVT, Val);
653 return DAG.getStore(Chain, dl, Result, Ptr, ST->getSrcValue(),
654 SVOffset, ST->isVolatile(), Alignment);
656 // Do a (aligned) store to a stack slot, then copy from the stack slot
657 // to the final destination using (unaligned) integer loads and stores.
658 MVT StoredVT = ST->getMemoryVT();
660 TLI.getRegisterType(MVT::getIntegerVT(StoredVT.getSizeInBits()));
661 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
662 unsigned RegBytes = RegVT.getSizeInBits() / 8;
663 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
665 // Make sure the stack slot is also aligned for the register type.
666 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
668 // Perform the original store, only redirected to the stack slot.
669 SDValue Store = DAG.getTruncStore(Chain, dl,
670 Val, StackPtr, NULL, 0, StoredVT);
671 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
672 SmallVector<SDValue, 8> Stores;
675 // Do all but one copies using the full register width.
676 for (unsigned i = 1; i < NumRegs; i++) {
677 // Load one integer register's worth from the stack slot.
678 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, NULL, 0);
679 // Store it to the final location. Remember the store.
680 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
681 ST->getSrcValue(), SVOffset + Offset,
683 MinAlign(ST->getAlignment(), Offset)));
684 // Increment the pointers.
686 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
688 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
691 // The last store may be partial. Do a truncating store. On big-endian
692 // machines this requires an extending load from the stack slot to ensure
693 // that the bits are in the right place.
694 MVT MemVT = MVT::getIntegerVT(8 * (StoredBytes - Offset));
696 // Load from the stack slot.
697 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
700 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
701 ST->getSrcValue(), SVOffset + Offset,
702 MemVT, ST->isVolatile(),
703 MinAlign(ST->getAlignment(), Offset)));
704 // The order of the stores doesn't matter - say it with a TokenFactor.
705 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
709 assert(ST->getMemoryVT().isInteger() &&
710 !ST->getMemoryVT().isVector() &&
711 "Unaligned store of unknown type.");
712 // Get the half-size VT
714 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1);
715 int NumBits = NewStoredVT.getSizeInBits();
716 int IncrementSize = NumBits / 8;
718 // Divide the stored value in two parts.
719 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
721 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
723 // Store the two parts
724 SDValue Store1, Store2;
725 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
726 ST->getSrcValue(), SVOffset, NewStoredVT,
727 ST->isVolatile(), Alignment);
728 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
729 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
730 Alignment = MinAlign(Alignment, IncrementSize);
731 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
732 ST->getSrcValue(), SVOffset + IncrementSize,
733 NewStoredVT, ST->isVolatile(), Alignment);
735 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
738 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
740 SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
741 const TargetLowering &TLI) {
742 int SVOffset = LD->getSrcValueOffset();
743 SDValue Chain = LD->getChain();
744 SDValue Ptr = LD->getBasePtr();
745 MVT VT = LD->getValueType(0);
746 MVT LoadedVT = LD->getMemoryVT();
747 DebugLoc dl = LD->getDebugLoc();
748 if (VT.isFloatingPoint() || VT.isVector()) {
749 MVT intVT = MVT::getIntegerVT(LoadedVT.getSizeInBits());
750 if (TLI.isTypeLegal(intVT)) {
751 // Expand to a (misaligned) integer load of the same size,
752 // then bitconvert to floating point or vector.
753 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getSrcValue(),
754 SVOffset, LD->isVolatile(),
756 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, LoadedVT, newLoad);
757 if (VT.isFloatingPoint() && LoadedVT != VT)
758 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result);
760 SDValue Ops[] = { Result, Chain };
761 return DAG.getMergeValues(Ops, 2, dl);
763 // Copy the value to a (aligned) stack slot using (unaligned) integer
764 // loads and stores, then do a (aligned) load from the stack slot.
765 MVT RegVT = TLI.getRegisterType(intVT);
766 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
767 unsigned RegBytes = RegVT.getSizeInBits() / 8;
768 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
770 // Make sure the stack slot is also aligned for the register type.
771 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
773 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
774 SmallVector<SDValue, 8> Stores;
775 SDValue StackPtr = StackBase;
778 // Do all but one copies using the full register width.
779 for (unsigned i = 1; i < NumRegs; i++) {
780 // Load one integer register's worth from the original location.
781 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, LD->getSrcValue(),
782 SVOffset + Offset, LD->isVolatile(),
783 MinAlign(LD->getAlignment(), Offset));
784 // Follow the load with a store to the stack slot. Remember the store.
785 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
787 // Increment the pointers.
789 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
790 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
794 // The last copy may be partial. Do an extending load.
795 MVT MemVT = MVT::getIntegerVT(8 * (LoadedBytes - Offset));
796 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
797 LD->getSrcValue(), SVOffset + Offset,
798 MemVT, LD->isVolatile(),
799 MinAlign(LD->getAlignment(), Offset));
800 // Follow the load with a store to the stack slot. Remember the store.
801 // On big-endian machines this requires a truncating store to ensure
802 // that the bits end up in the right place.
803 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
806 // The order of the stores doesn't matter - say it with a TokenFactor.
807 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
810 // Finally, perform the original load only redirected to the stack slot.
811 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
814 // Callers expect a MERGE_VALUES node.
815 SDValue Ops[] = { Load, TF };
816 return DAG.getMergeValues(Ops, 2, dl);
819 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
820 "Unaligned load of unsupported type.");
822 // Compute the new VT that is half the size of the old one. This is an
824 unsigned NumBits = LoadedVT.getSizeInBits();
826 NewLoadedVT = MVT::getIntegerVT(NumBits/2);
829 unsigned Alignment = LD->getAlignment();
830 unsigned IncrementSize = NumBits / 8;
831 ISD::LoadExtType HiExtType = LD->getExtensionType();
833 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
834 if (HiExtType == ISD::NON_EXTLOAD)
835 HiExtType = ISD::ZEXTLOAD;
837 // Load the value in two parts
839 if (TLI.isLittleEndian()) {
840 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(),
841 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
842 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
843 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
844 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(),
845 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
846 MinAlign(Alignment, IncrementSize));
848 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(),
849 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
850 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
851 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
852 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(),
853 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
854 MinAlign(Alignment, IncrementSize));
857 // aggregate the two parts
858 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
859 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
860 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
862 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
865 SDValue Ops[] = { Result, TF };
866 return DAG.getMergeValues(Ops, 2, dl);
869 /// UnrollVectorOp - We know that the given vector has a legal type, however
870 /// the operation it performs is not legal and is an operation that we have
871 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
872 /// operating on each element individually.
873 SDValue SelectionDAGLegalize::UnrollVectorOp(SDValue Op) {
874 MVT VT = Op.getValueType();
875 assert(isTypeLegal(VT) &&
876 "Caller should expand or promote operands that are not legal!");
877 assert(Op.getNode()->getNumValues() == 1 &&
878 "Can't unroll a vector with multiple results!");
879 unsigned NE = VT.getVectorNumElements();
880 MVT EltVT = VT.getVectorElementType();
881 DebugLoc dl = Op.getDebugLoc();
883 SmallVector<SDValue, 8> Scalars;
884 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
885 for (unsigned i = 0; i != NE; ++i) {
886 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
887 SDValue Operand = Op.getOperand(j);
888 MVT OperandVT = Operand.getValueType();
889 if (OperandVT.isVector()) {
890 // A vector operand; extract a single element.
891 MVT OperandEltVT = OperandVT.getVectorElementType();
892 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
895 DAG.getConstant(i, MVT::i32));
897 // A scalar operand; just use it as is.
898 Operands[j] = Operand;
902 switch (Op.getOpcode()) {
904 Scalars.push_back(DAG.getNode(Op.getOpcode(), dl, EltVT,
905 &Operands[0], Operands.size()));
912 Scalars.push_back(DAG.getNode(Op.getOpcode(), dl, EltVT, Operands[0],
913 DAG.getShiftAmountOperand(Operands[1])));
918 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Scalars[0], Scalars.size());
921 /// GetFPLibCall - Return the right libcall for the given floating point type.
922 static RTLIB::Libcall GetFPLibCall(MVT VT,
923 RTLIB::Libcall Call_F32,
924 RTLIB::Libcall Call_F64,
925 RTLIB::Libcall Call_F80,
926 RTLIB::Libcall Call_PPCF128) {
928 VT == MVT::f32 ? Call_F32 :
929 VT == MVT::f64 ? Call_F64 :
930 VT == MVT::f80 ? Call_F80 :
931 VT == MVT::ppcf128 ? Call_PPCF128 :
932 RTLIB::UNKNOWN_LIBCALL;
935 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
936 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
937 /// is necessary to spill the vector being inserted into to memory, perform
938 /// the insert there, and then read the result back.
939 SDValue SelectionDAGLegalize::
940 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
946 // If the target doesn't support this, we have to spill the input vector
947 // to a temporary stack slot, update the element, then reload it. This is
948 // badness. We could also load the value into a vector register (either
949 // with a "move to register" or "extload into register" instruction, then
950 // permute it into place, if the idx is a constant and if the idx is
951 // supported by the target.
952 MVT VT = Tmp1.getValueType();
953 MVT EltVT = VT.getVectorElementType();
954 MVT IdxVT = Tmp3.getValueType();
955 MVT PtrVT = TLI.getPointerTy();
956 SDValue StackPtr = DAG.CreateStackTemporary(VT);
958 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
961 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
962 PseudoSourceValue::getFixedStack(SPFI), 0);
964 // Truncate or zero extend offset to target pointer type.
965 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
966 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
967 // Add the offset to the index.
968 unsigned EltSize = EltVT.getSizeInBits()/8;
969 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
970 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
971 // Store the scalar value.
972 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2,
973 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT);
974 // Load the updated vector.
975 return DAG.getLoad(VT, dl, Ch, StackPtr,
976 PseudoSourceValue::getFixedStack(SPFI), 0);
980 /// LegalizeOp - We know that the specified value has a legal type, and
981 /// that its operands are legal. Now ensure that the operation itself
982 /// is legal, recursively ensuring that the operands' operations remain
984 SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
985 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
988 assert(isTypeLegal(Op.getValueType()) &&
989 "Caller should expand or promote operands that are not legal!");
990 SDNode *Node = Op.getNode();
991 DebugLoc dl = Node->getDebugLoc();
993 // If this operation defines any values that cannot be represented in a
994 // register on this target, make sure to expand or promote them.
995 if (Node->getNumValues() > 1) {
996 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
997 if (getTypeAction(Node->getValueType(i)) != Legal) {
998 HandleOp(Op.getValue(i));
999 assert(LegalizedNodes.count(Op) &&
1000 "Handling didn't add legal operands!");
1001 return LegalizedNodes[Op];
1005 // Note that LegalizeOp may be reentered even from single-use nodes, which
1006 // means that we always must cache transformed nodes.
1007 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1008 if (I != LegalizedNodes.end()) return I->second;
1010 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
1011 SDValue Result = Op;
1012 bool isCustom = false;
1014 switch (Node->getOpcode()) {
1015 case ISD::FrameIndex:
1016 case ISD::EntryToken:
1018 case ISD::BasicBlock:
1019 case ISD::TargetFrameIndex:
1020 case ISD::TargetJumpTable:
1021 case ISD::TargetConstant:
1022 case ISD::TargetConstantFP:
1023 case ISD::TargetConstantPool:
1024 case ISD::TargetGlobalAddress:
1025 case ISD::TargetGlobalTLSAddress:
1026 case ISD::TargetExternalSymbol:
1027 case ISD::VALUETYPE:
1029 case ISD::MEMOPERAND:
1031 case ISD::ARG_FLAGS:
1032 // Primitives must all be legal.
1033 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
1034 "This must be legal!");
1037 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1038 // If this is a target node, legalize it by legalizing the operands then
1039 // passing it through.
1040 SmallVector<SDValue, 8> Ops;
1041 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1042 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1044 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
1046 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1047 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
1048 return Result.getValue(Op.getResNo());
1050 // Otherwise this is an unhandled builtin node. splat.
1052 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
1054 assert(0 && "Do not know how to legalize this operator!");
1056 case ISD::GLOBAL_OFFSET_TABLE:
1057 case ISD::GlobalAddress:
1058 case ISD::GlobalTLSAddress:
1059 case ISD::ExternalSymbol:
1060 case ISD::ConstantPool:
1061 case ISD::JumpTable: // Nothing to do.
1062 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1063 default: assert(0 && "This action is not supported yet!");
1064 case TargetLowering::Custom:
1065 Tmp1 = TLI.LowerOperation(Op, DAG);
1066 if (Tmp1.getNode()) Result = Tmp1;
1067 // FALLTHROUGH if the target doesn't want to lower this op after all.
1068 case TargetLowering::Legal:
1072 case ISD::FRAMEADDR:
1073 case ISD::RETURNADDR:
1074 // The only option for these nodes is to custom lower them. If the target
1075 // does not custom lower them, then return zero.
1076 Tmp1 = TLI.LowerOperation(Op, DAG);
1080 Result = DAG.getConstant(0, TLI.getPointerTy());
1082 case ISD::FRAME_TO_ARGS_OFFSET: {
1083 MVT VT = Node->getValueType(0);
1084 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1085 default: assert(0 && "This action is not supported yet!");
1086 case TargetLowering::Custom:
1087 Result = TLI.LowerOperation(Op, DAG);
1088 if (Result.getNode()) break;
1090 case TargetLowering::Legal:
1091 Result = DAG.getConstant(0, VT);
1096 case ISD::EXCEPTIONADDR: {
1097 Tmp1 = LegalizeOp(Node->getOperand(0));
1098 MVT VT = Node->getValueType(0);
1099 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1100 default: assert(0 && "This action is not supported yet!");
1101 case TargetLowering::Expand: {
1102 unsigned Reg = TLI.getExceptionAddressRegister();
1103 Result = DAG.getCopyFromReg(Tmp1, dl, Reg, VT);
1106 case TargetLowering::Custom:
1107 Result = TLI.LowerOperation(Op, DAG);
1108 if (Result.getNode()) break;
1110 case TargetLowering::Legal: {
1111 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp1 };
1112 Result = DAG.getMergeValues(Ops, 2, dl);
1117 if (Result.getNode()->getNumValues() == 1) break;
1119 assert(Result.getNode()->getNumValues() == 2 &&
1120 "Cannot return more than two values!");
1122 // Since we produced two values, make sure to remember that we
1123 // legalized both of them.
1124 Tmp1 = LegalizeOp(Result);
1125 Tmp2 = LegalizeOp(Result.getValue(1));
1126 AddLegalizedOperand(Op.getValue(0), Tmp1);
1127 AddLegalizedOperand(Op.getValue(1), Tmp2);
1128 return Op.getResNo() ? Tmp2 : Tmp1;
1129 case ISD::EHSELECTION: {
1130 Tmp1 = LegalizeOp(Node->getOperand(0));
1131 Tmp2 = LegalizeOp(Node->getOperand(1));
1132 MVT VT = Node->getValueType(0);
1133 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1134 default: assert(0 && "This action is not supported yet!");
1135 case TargetLowering::Expand: {
1136 unsigned Reg = TLI.getExceptionSelectorRegister();
1137 Result = DAG.getCopyFromReg(Tmp2, dl, Reg, VT);
1140 case TargetLowering::Custom:
1141 Result = TLI.LowerOperation(Op, DAG);
1142 if (Result.getNode()) break;
1144 case TargetLowering::Legal: {
1145 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp2 };
1146 Result = DAG.getMergeValues(Ops, 2, dl);
1151 if (Result.getNode()->getNumValues() == 1) break;
1153 assert(Result.getNode()->getNumValues() == 2 &&
1154 "Cannot return more than two values!");
1156 // Since we produced two values, make sure to remember that we
1157 // legalized both of them.
1158 Tmp1 = LegalizeOp(Result);
1159 Tmp2 = LegalizeOp(Result.getValue(1));
1160 AddLegalizedOperand(Op.getValue(0), Tmp1);
1161 AddLegalizedOperand(Op.getValue(1), Tmp2);
1162 return Op.getResNo() ? Tmp2 : Tmp1;
1163 case ISD::EH_RETURN: {
1164 MVT VT = Node->getValueType(0);
1165 // The only "good" option for this node is to custom lower it.
1166 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1167 default: assert(0 && "This action is not supported at all!");
1168 case TargetLowering::Custom:
1169 Result = TLI.LowerOperation(Op, DAG);
1170 if (Result.getNode()) break;
1172 case TargetLowering::Legal:
1173 // Target does not know, how to lower this, lower to noop
1174 Result = LegalizeOp(Node->getOperand(0));
1179 case ISD::AssertSext:
1180 case ISD::AssertZext:
1181 Tmp1 = LegalizeOp(Node->getOperand(0));
1182 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1184 case ISD::MERGE_VALUES:
1185 // Legalize eliminates MERGE_VALUES nodes.
1186 Result = Node->getOperand(Op.getResNo());
1188 case ISD::CopyFromReg:
1189 Tmp1 = LegalizeOp(Node->getOperand(0));
1190 Result = Op.getValue(0);
1191 if (Node->getNumValues() == 2) {
1192 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1194 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
1195 if (Node->getNumOperands() == 3) {
1196 Tmp2 = LegalizeOp(Node->getOperand(2));
1197 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1199 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1201 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
1203 // Since CopyFromReg produces two values, make sure to remember that we
1204 // legalized both of them.
1205 AddLegalizedOperand(Op.getValue(0), Result);
1206 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1207 return Result.getValue(Op.getResNo());
1209 MVT VT = Op.getValueType();
1210 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
1211 default: assert(0 && "This action is not supported yet!");
1212 case TargetLowering::Expand:
1214 Result = DAG.getConstant(0, VT);
1215 else if (VT.isFloatingPoint())
1216 Result = DAG.getConstantFP(APFloat(APInt(VT.getSizeInBits(), 0)),
1219 assert(0 && "Unknown value type!");
1221 case TargetLowering::Legal:
1227 case ISD::INTRINSIC_W_CHAIN:
1228 case ISD::INTRINSIC_WO_CHAIN:
1229 case ISD::INTRINSIC_VOID: {
1230 SmallVector<SDValue, 8> Ops;
1231 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1232 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1233 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1235 // Allow the target to custom lower its intrinsics if it wants to.
1236 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
1237 TargetLowering::Custom) {
1238 Tmp3 = TLI.LowerOperation(Result, DAG);
1239 if (Tmp3.getNode()) Result = Tmp3;
1242 if (Result.getNode()->getNumValues() == 1) break;
1244 // Must have return value and chain result.
1245 assert(Result.getNode()->getNumValues() == 2 &&
1246 "Cannot return more than two values!");
1248 // Since loads produce two values, make sure to remember that we
1249 // legalized both of them.
1250 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1251 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1252 return Result.getValue(Op.getResNo());
1255 case ISD::DBG_STOPPOINT:
1256 assert(Node->getNumOperands() == 1 && "Invalid DBG_STOPPOINT node!");
1257 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
1259 switch (TLI.getOperationAction(ISD::DBG_STOPPOINT, MVT::Other)) {
1260 case TargetLowering::Promote:
1261 default: assert(0 && "This action is not supported yet!");
1262 case TargetLowering::Expand: {
1263 DwarfWriter *DW = DAG.getDwarfWriter();
1264 bool useDEBUG_LOC = TLI.isOperationLegalOrCustom(ISD::DEBUG_LOC,
1266 bool useLABEL = TLI.isOperationLegalOrCustom(ISD::DBG_LABEL, MVT::Other);
1268 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node);
1269 GlobalVariable *CU_GV = cast<GlobalVariable>(DSP->getCompileUnit());
1270 if (DW && (useDEBUG_LOC || useLABEL) && !CU_GV->isDeclaration()) {
1271 DICompileUnit CU(cast<GlobalVariable>(DSP->getCompileUnit()));
1273 unsigned Line = DSP->getLine();
1274 unsigned Col = DSP->getColumn();
1276 if (OptLevel == CodeGenOpt::None) {
1277 // A bit self-referential to have DebugLoc on Debug_Loc nodes, but it
1278 // won't hurt anything.
1280 SDValue Ops[] = { Tmp1, DAG.getConstant(Line, MVT::i32),
1281 DAG.getConstant(Col, MVT::i32),
1282 DAG.getSrcValue(CU.getGV()) };
1283 Result = DAG.getNode(ISD::DEBUG_LOC, dl, MVT::Other, Ops, 4);
1285 unsigned ID = DW->RecordSourceLine(Line, Col, CU);
1286 Result = DAG.getLabel(ISD::DBG_LABEL, dl, Tmp1, ID);
1289 Result = Tmp1; // chain
1292 Result = Tmp1; // chain
1296 case TargetLowering::Custom:
1297 Result = TLI.LowerOperation(Op, DAG);
1298 if (Result.getNode())
1300 case TargetLowering::Legal: {
1301 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1302 if (Action == Legal && Tmp1 == Node->getOperand(0))
1305 SmallVector<SDValue, 8> Ops;
1306 Ops.push_back(Tmp1);
1307 if (Action == Legal) {
1308 Ops.push_back(Node->getOperand(1)); // line # must be legal.
1309 Ops.push_back(Node->getOperand(2)); // col # must be legal.
1311 // Otherwise promote them.
1312 Ops.push_back(PromoteOp(Node->getOperand(1)));
1313 Ops.push_back(PromoteOp(Node->getOperand(2)));
1315 Ops.push_back(Node->getOperand(3)); // filename must be legal.
1316 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
1317 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1324 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!");
1325 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) {
1326 default: assert(0 && "This action is not supported yet!");
1327 case TargetLowering::Legal:
1328 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1329 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1330 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable.
1331 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1333 case TargetLowering::Expand:
1334 Result = LegalizeOp(Node->getOperand(0));
1339 case ISD::DEBUG_LOC:
1340 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
1341 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
1342 default: assert(0 && "This action is not supported yet!");
1343 case TargetLowering::Legal: {
1344 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1345 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1346 if (Action == Legal && Tmp1 == Node->getOperand(0))
1348 if (Action == Legal) {
1349 Tmp2 = Node->getOperand(1);
1350 Tmp3 = Node->getOperand(2);
1351 Tmp4 = Node->getOperand(3);
1353 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1354 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1355 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1357 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1363 case ISD::DBG_LABEL:
1365 assert(Node->getNumOperands() == 1 && "Invalid LABEL node!");
1366 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
1367 default: assert(0 && "This action is not supported yet!");
1368 case TargetLowering::Legal:
1369 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1370 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1372 case TargetLowering::Expand:
1373 Result = LegalizeOp(Node->getOperand(0));
1379 assert(Node->getNumOperands() == 4 && "Invalid Prefetch node!");
1380 switch (TLI.getOperationAction(ISD::PREFETCH, MVT::Other)) {
1381 default: assert(0 && "This action is not supported yet!");
1382 case TargetLowering::Legal:
1383 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1384 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1385 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the rw specifier.
1386 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize locality specifier.
1387 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1389 case TargetLowering::Expand:
1391 Result = LegalizeOp(Node->getOperand(0));
1396 case ISD::MEMBARRIER: {
1397 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!");
1398 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) {
1399 default: assert(0 && "This action is not supported yet!");
1400 case TargetLowering::Legal: {
1402 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1403 for (int x = 1; x < 6; ++x) {
1404 Ops[x] = Node->getOperand(x);
1405 if (!isTypeLegal(Ops[x].getValueType()))
1406 Ops[x] = PromoteOp(Ops[x]);
1408 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6);
1411 case TargetLowering::Expand:
1412 //There is no libgcc call for this op
1413 Result = Node->getOperand(0); // Noop
1419 case ISD::ATOMIC_CMP_SWAP: {
1420 unsigned int num_operands = 4;
1421 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1423 for (unsigned int x = 0; x < num_operands; ++x)
1424 Ops[x] = LegalizeOp(Node->getOperand(x));
1425 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1427 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1428 default: assert(0 && "This action is not supported yet!");
1429 case TargetLowering::Custom:
1430 Result = TLI.LowerOperation(Result, DAG);
1432 case TargetLowering::Legal:
1435 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1436 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1437 return Result.getValue(Op.getResNo());
1439 case ISD::ATOMIC_LOAD_ADD:
1440 case ISD::ATOMIC_LOAD_SUB:
1441 case ISD::ATOMIC_LOAD_AND:
1442 case ISD::ATOMIC_LOAD_OR:
1443 case ISD::ATOMIC_LOAD_XOR:
1444 case ISD::ATOMIC_LOAD_NAND:
1445 case ISD::ATOMIC_LOAD_MIN:
1446 case ISD::ATOMIC_LOAD_MAX:
1447 case ISD::ATOMIC_LOAD_UMIN:
1448 case ISD::ATOMIC_LOAD_UMAX:
1449 case ISD::ATOMIC_SWAP: {
1450 unsigned int num_operands = 3;
1451 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1453 for (unsigned int x = 0; x < num_operands; ++x)
1454 Ops[x] = LegalizeOp(Node->getOperand(x));
1455 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1457 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1458 default: assert(0 && "This action is not supported yet!");
1459 case TargetLowering::Custom:
1460 Result = TLI.LowerOperation(Result, DAG);
1462 case TargetLowering::Legal:
1465 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1466 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1467 return Result.getValue(Op.getResNo());
1469 case ISD::Constant: {
1470 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1472 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1474 // We know we don't need to expand constants here, constants only have one
1475 // value and we check that it is fine above.
1477 if (opAction == TargetLowering::Custom) {
1478 Tmp1 = TLI.LowerOperation(Result, DAG);
1484 case ISD::ConstantFP: {
1485 // Spill FP immediates to the constant pool if the target cannot directly
1486 // codegen them. Targets often have some immediate values that can be
1487 // efficiently generated into an FP register without a load. We explicitly
1488 // leave these constants as ConstantFP nodes for the target to deal with.
1489 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1491 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1492 default: assert(0 && "This action is not supported yet!");
1493 case TargetLowering::Legal:
1495 case TargetLowering::Custom:
1496 Tmp3 = TLI.LowerOperation(Result, DAG);
1497 if (Tmp3.getNode()) {
1502 case TargetLowering::Expand: {
1503 // Check to see if this FP immediate is already legal.
1504 bool isLegal = false;
1505 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1506 E = TLI.legal_fpimm_end(); I != E; ++I) {
1507 if (CFP->isExactlyValue(*I)) {
1512 // If this is a legal constant, turn it into a TargetConstantFP node.
1515 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1520 case ISD::TokenFactor:
1521 if (Node->getNumOperands() == 2) {
1522 Tmp1 = LegalizeOp(Node->getOperand(0));
1523 Tmp2 = LegalizeOp(Node->getOperand(1));
1524 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1525 } else if (Node->getNumOperands() == 3) {
1526 Tmp1 = LegalizeOp(Node->getOperand(0));
1527 Tmp2 = LegalizeOp(Node->getOperand(1));
1528 Tmp3 = LegalizeOp(Node->getOperand(2));
1529 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1531 SmallVector<SDValue, 8> Ops;
1532 // Legalize the operands.
1533 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1534 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1535 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1539 case ISD::FORMAL_ARGUMENTS:
1541 // The only option for this is to custom lower it.
1542 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1543 assert(Tmp3.getNode() && "Target didn't custom lower this node!");
1544 // A call within a calling sequence must be legalized to something
1545 // other than the normal CALLSEQ_END. Violating this gets Legalize
1546 // into an infinite loop.
1547 assert ((!IsLegalizingCall ||
1548 Node->getOpcode() != ISD::CALL ||
1549 Tmp3.getNode()->getOpcode() != ISD::CALLSEQ_END) &&
1550 "Nested CALLSEQ_START..CALLSEQ_END not supported.");
1552 // The number of incoming and outgoing values should match; unless the final
1553 // outgoing value is a flag.
1554 assert((Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() ||
1555 (Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() + 1 &&
1556 Tmp3.getNode()->getValueType(Tmp3.getNode()->getNumValues() - 1) ==
1558 "Lowering call/formal_arguments produced unexpected # results!");
1560 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1561 // remember that we legalized all of them, so it doesn't get relegalized.
1562 for (unsigned i = 0, e = Tmp3.getNode()->getNumValues(); i != e; ++i) {
1563 if (Tmp3.getNode()->getValueType(i) == MVT::Flag)
1565 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1566 if (Op.getResNo() == i)
1568 AddLegalizedOperand(SDValue(Node, i), Tmp1);
1571 case ISD::BUILD_VECTOR:
1572 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1573 default: assert(0 && "This action is not supported yet!");
1574 case TargetLowering::Custom:
1575 Tmp3 = TLI.LowerOperation(Result, DAG);
1576 if (Tmp3.getNode()) {
1581 case TargetLowering::Expand:
1582 Result = ExpandBUILD_VECTOR(Result.getNode());
1586 case ISD::INSERT_VECTOR_ELT:
1587 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1588 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1590 // The type of the value to insert may not be legal, even though the vector
1591 // type is legal. Legalize/Promote accordingly. We do not handle Expand
1593 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1594 default: assert(0 && "Cannot expand insert element operand");
1595 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
1596 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
1598 // FIXME: An alternative would be to check to see if the target is not
1599 // going to custom lower this operation, we could bitcast to half elt
1600 // width and perform two inserts at that width, if that is legal.
1601 Tmp2 = Node->getOperand(1);
1604 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1606 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1607 Node->getValueType(0))) {
1608 default: assert(0 && "This action is not supported yet!");
1609 case TargetLowering::Legal:
1611 case TargetLowering::Custom:
1612 Tmp4 = TLI.LowerOperation(Result, DAG);
1613 if (Tmp4.getNode()) {
1618 case TargetLowering::Promote:
1619 // Fall thru for vector case
1620 case TargetLowering::Expand: {
1621 // If the insert index is a constant, codegen this as a scalar_to_vector,
1622 // then a shuffle that inserts it into the right position in the vector.
1623 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1624 // SCALAR_TO_VECTOR requires that the type of the value being inserted
1625 // match the element type of the vector being created, except for
1626 // integers in which case the inserted value can be over width.
1627 MVT EltVT = Op.getValueType().getVectorElementType();
1628 if (Tmp2.getValueType() == EltVT ||
1629 (EltVT.isInteger() && Tmp2.getValueType().bitsGE(EltVT))) {
1630 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
1631 Tmp1.getValueType(), Tmp2);
1633 unsigned NumElts = Tmp1.getValueType().getVectorNumElements();
1634 // We generate a shuffle of InVec and ScVec, so the shuffle mask
1635 // should be 0,1,2,3,4,5... with the appropriate element replaced with
1636 // elt 0 of the RHS.
1637 SmallVector<int, 8> ShufOps;
1638 for (unsigned i = 0; i != NumElts; ++i)
1639 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
1641 Result = DAG.getVectorShuffle(Tmp1.getValueType(), dl, Tmp1, ScVec,
1643 Result = LegalizeOp(Result);
1647 Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3, dl);
1652 case ISD::SCALAR_TO_VECTOR:
1653 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1654 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1658 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1659 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1660 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1661 Node->getValueType(0))) {
1662 default: assert(0 && "This action is not supported yet!");
1663 case TargetLowering::Legal:
1665 case TargetLowering::Custom:
1666 Tmp3 = TLI.LowerOperation(Result, DAG);
1667 if (Tmp3.getNode()) {
1672 case TargetLowering::Expand:
1673 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1677 case ISD::VECTOR_SHUFFLE: {
1678 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1679 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1680 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1681 MVT VT = Result.getValueType();
1683 // Copy the Mask to a local SmallVector for use with isShuffleMaskLegal.
1684 SmallVector<int, 8> Mask;
1685 cast<ShuffleVectorSDNode>(Result)->getMask(Mask);
1687 // Allow targets to custom lower the SHUFFLEs they support.
1688 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
1689 default: assert(0 && "Unknown operation action!");
1690 case TargetLowering::Legal:
1691 assert(TLI.isShuffleMaskLegal(Mask, VT) &&
1692 "vector shuffle should not be created if not legal!");
1694 case TargetLowering::Custom:
1695 Tmp3 = TLI.LowerOperation(Result, DAG);
1696 if (Tmp3.getNode()) {
1701 case TargetLowering::Expand: {
1702 MVT EltVT = VT.getVectorElementType();
1703 unsigned NumElems = VT.getVectorNumElements();
1704 SmallVector<SDValue, 8> Ops;
1705 for (unsigned i = 0; i != NumElems; ++i) {
1707 Ops.push_back(DAG.getUNDEF(EltVT));
1710 unsigned Idx = Mask[i];
1712 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Tmp1,
1713 DAG.getIntPtrConstant(Idx)));
1715 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Tmp2,
1716 DAG.getIntPtrConstant(Idx - NumElems)));
1718 Result = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
1721 case TargetLowering::Promote: {
1722 // Change base type to a different vector type.
1723 MVT OVT = Node->getValueType(0);
1724 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1726 // Cast the two input vectors.
1727 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp1);
1728 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp2);
1730 // Convert the shuffle mask to the right # elements.
1731 Result = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
1732 Result = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Result);
1738 case ISD::EXTRACT_VECTOR_ELT:
1739 Tmp1 = Node->getOperand(0);
1740 Tmp2 = LegalizeOp(Node->getOperand(1));
1741 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1742 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1745 case ISD::EXTRACT_SUBVECTOR:
1746 Tmp1 = Node->getOperand(0);
1747 Tmp2 = LegalizeOp(Node->getOperand(1));
1748 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1749 Result = ExpandEXTRACT_SUBVECTOR(Result);
1752 case ISD::CONCAT_VECTORS: {
1753 // Legalize the operands.
1754 SmallVector<SDValue, 8> Ops;
1755 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1756 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1757 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1759 switch (TLI.getOperationAction(ISD::CONCAT_VECTORS,
1760 Node->getValueType(0))) {
1761 default: assert(0 && "Unknown operation action!");
1762 case TargetLowering::Legal:
1764 case TargetLowering::Custom:
1765 Tmp3 = TLI.LowerOperation(Result, DAG);
1766 if (Tmp3.getNode()) {
1771 case TargetLowering::Expand: {
1772 // Use extract/insert/build vector for now. We might try to be
1773 // more clever later.
1774 MVT PtrVT = TLI.getPointerTy();
1775 SmallVector<SDValue, 8> Ops;
1776 unsigned NumOperands = Node->getNumOperands();
1777 for (unsigned i=0; i < NumOperands; ++i) {
1778 SDValue SubOp = Node->getOperand(i);
1779 MVT VVT = SubOp.getNode()->getValueType(0);
1780 MVT EltVT = VVT.getVectorElementType();
1781 unsigned NumSubElem = VVT.getVectorNumElements();
1782 for (unsigned j=0; j < NumSubElem; ++j) {
1783 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp,
1784 DAG.getConstant(j, PtrVT)));
1787 return LegalizeOp(DAG.getNode(ISD::BUILD_VECTOR, dl,
1788 Node->getValueType(0),
1789 &Ops[0], Ops.size()));
1795 case ISD::CALLSEQ_START: {
1796 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1798 // Recursively Legalize all of the inputs of the call end that do not lead
1799 // to this call start. This ensures that any libcalls that need be inserted
1800 // are inserted *before* the CALLSEQ_START.
1801 IsLegalizingCallArgs = true;
1802 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1803 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1804 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
1807 IsLegalizingCallArgs = false;
1809 // Now that we legalized all of the inputs (which may have inserted
1810 // libcalls) create the new CALLSEQ_START node.
1811 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1813 // Merge in the last call, to ensure that this call start after the last
1815 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1816 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1817 Tmp1, LastCALLSEQ_END);
1818 Tmp1 = LegalizeOp(Tmp1);
1821 // Do not try to legalize the target-specific arguments (#1+).
1822 if (Tmp1 != Node->getOperand(0)) {
1823 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1825 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1828 // Remember that the CALLSEQ_START is legalized.
1829 AddLegalizedOperand(Op.getValue(0), Result);
1830 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1831 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1833 // Now that the callseq_start and all of the non-call nodes above this call
1834 // sequence have been legalized, legalize the call itself. During this
1835 // process, no libcalls can/will be inserted, guaranteeing that no calls
1837 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1838 // Note that we are selecting this call!
1839 LastCALLSEQ_END = SDValue(CallEnd, 0);
1840 IsLegalizingCall = true;
1842 // Legalize the call, starting from the CALLSEQ_END.
1843 LegalizeOp(LastCALLSEQ_END);
1844 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1847 case ISD::CALLSEQ_END:
1848 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1849 // will cause this node to be legalized as well as handling libcalls right.
1850 if (LastCALLSEQ_END.getNode() != Node) {
1851 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
1852 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1853 assert(I != LegalizedNodes.end() &&
1854 "Legalizing the call start should have legalized this node!");
1858 // Otherwise, the call start has been legalized and everything is going
1859 // according to plan. Just legalize ourselves normally here.
1860 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1861 // Do not try to legalize the target-specific arguments (#1+), except for
1862 // an optional flag input.
1863 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1864 if (Tmp1 != Node->getOperand(0)) {
1865 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1867 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1870 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1871 if (Tmp1 != Node->getOperand(0) ||
1872 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1873 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1876 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1879 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1880 // This finishes up call legalization.
1881 IsLegalizingCall = false;
1883 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1884 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1885 if (Node->getNumValues() == 2)
1886 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1887 return Result.getValue(Op.getResNo());
1888 case ISD::DYNAMIC_STACKALLOC: {
1889 MVT VT = Node->getValueType(0);
1890 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1891 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1892 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1893 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1895 Tmp1 = Result.getValue(0);
1896 Tmp2 = Result.getValue(1);
1897 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1898 default: assert(0 && "This action is not supported yet!");
1899 case TargetLowering::Expand: {
1900 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1901 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1902 " not tell us which reg is the stack pointer!");
1903 SDValue Chain = Tmp1.getOperand(0);
1905 // Chain the dynamic stack allocation so that it doesn't modify the stack
1906 // pointer when other instructions are using the stack.
1907 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1909 SDValue Size = Tmp2.getOperand(1);
1910 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1911 Chain = SP.getValue(1);
1912 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1913 unsigned StackAlign =
1914 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1915 if (Align > StackAlign)
1916 SP = DAG.getNode(ISD::AND, dl, VT, SP,
1917 DAG.getConstant(-(uint64_t)Align, VT));
1918 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1919 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1921 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1922 DAG.getIntPtrConstant(0, true), SDValue());
1924 Tmp1 = LegalizeOp(Tmp1);
1925 Tmp2 = LegalizeOp(Tmp2);
1928 case TargetLowering::Custom:
1929 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1930 if (Tmp3.getNode()) {
1931 Tmp1 = LegalizeOp(Tmp3);
1932 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1935 case TargetLowering::Legal:
1938 // Since this op produce two values, make sure to remember that we
1939 // legalized both of them.
1940 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
1941 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
1942 return Op.getResNo() ? Tmp2 : Tmp1;
1944 case ISD::INLINEASM: {
1945 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1946 bool Changed = false;
1947 // Legalize all of the operands of the inline asm, in case they are nodes
1948 // that need to be expanded or something. Note we skip the asm string and
1949 // all of the TargetConstant flags.
1950 SDValue Op = LegalizeOp(Ops[0]);
1951 Changed = Op != Ops[0];
1954 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1955 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1956 unsigned NumVals = InlineAsm::
1957 getNumOperandRegisters(cast<ConstantSDNode>(Ops[i])->getZExtValue());
1958 for (++i; NumVals; ++i, --NumVals) {
1959 SDValue Op = LegalizeOp(Ops[i]);
1968 Op = LegalizeOp(Ops.back());
1969 Changed |= Op != Ops.back();
1974 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1976 // INLINE asm returns a chain and flag, make sure to add both to the map.
1977 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1978 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1979 return Result.getValue(Op.getResNo());
1982 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1983 // Ensure that libcalls are emitted before a branch.
1984 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
1985 Tmp1 = LegalizeOp(Tmp1);
1986 LastCALLSEQ_END = DAG.getEntryNode();
1988 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1991 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1992 // Ensure that libcalls are emitted before a branch.
1993 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
1994 Tmp1 = LegalizeOp(Tmp1);
1995 LastCALLSEQ_END = DAG.getEntryNode();
1997 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1998 default: assert(0 && "Indirect target must be legal type (pointer)!");
2000 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
2003 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2006 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2007 // Ensure that libcalls are emitted before a branch.
2008 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
2009 Tmp1 = LegalizeOp(Tmp1);
2010 LastCALLSEQ_END = DAG.getEntryNode();
2012 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
2013 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2015 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
2016 default: assert(0 && "This action is not supported yet!");
2017 case TargetLowering::Legal: break;
2018 case TargetLowering::Custom:
2019 Tmp1 = TLI.LowerOperation(Result, DAG);
2020 if (Tmp1.getNode()) Result = Tmp1;
2022 case TargetLowering::Expand: {
2023 SDValue Chain = Result.getOperand(0);
2024 SDValue Table = Result.getOperand(1);
2025 SDValue Index = Result.getOperand(2);
2027 MVT PTy = TLI.getPointerTy();
2028 MachineFunction &MF = DAG.getMachineFunction();
2029 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
2030 Index= DAG.getNode(ISD::MUL, dl, PTy,
2031 Index, DAG.getConstant(EntrySize, PTy));
2032 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2034 MVT MemVT = MVT::getIntegerVT(EntrySize * 8);
2035 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
2036 PseudoSourceValue::getJumpTable(), 0, MemVT);
2038 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2039 // For PIC, the sequence is:
2040 // BRIND(load(Jumptable + index) + RelocBase)
2041 // RelocBase can be JumpTable, GOT or some sort of global base.
2042 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
2043 TLI.getPICJumpTableRelocBase(Table, DAG));
2045 Result = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
2050 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2051 // Ensure that libcalls are emitted before a return.
2052 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
2053 Tmp1 = LegalizeOp(Tmp1);
2054 LastCALLSEQ_END = DAG.getEntryNode();
2056 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2057 case Expand: assert(0 && "It's impossible to expand bools");
2059 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
2062 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
2064 // The top bits of the promoted condition are not necessarily zero, ensure
2065 // that the value is properly zero extended.
2066 unsigned BitWidth = Tmp2.getValueSizeInBits();
2067 if (!DAG.MaskedValueIsZero(Tmp2,
2068 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2069 Tmp2 = DAG.getZeroExtendInReg(Tmp2, dl, MVT::i1);
2074 // Basic block destination (Op#2) is always legal.
2075 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2077 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
2078 default: assert(0 && "This action is not supported yet!");
2079 case TargetLowering::Legal: break;
2080 case TargetLowering::Custom:
2081 Tmp1 = TLI.LowerOperation(Result, DAG);
2082 if (Tmp1.getNode()) Result = Tmp1;
2084 case TargetLowering::Expand:
2085 // Expand brcond's setcc into its constituent parts and create a BR_CC
2087 if (Tmp2.getOpcode() == ISD::SETCC) {
2088 Result = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
2089 Tmp1, Tmp2.getOperand(2),
2090 Tmp2.getOperand(0), Tmp2.getOperand(1),
2091 Node->getOperand(2));
2093 Result = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
2094 DAG.getCondCode(ISD::SETNE), Tmp2,
2095 DAG.getConstant(0, Tmp2.getValueType()),
2096 Node->getOperand(2));
2102 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2103 // Ensure that libcalls are emitted before a branch.
2104 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
2105 Tmp1 = LegalizeOp(Tmp1);
2106 Tmp2 = Node->getOperand(2); // LHS
2107 Tmp3 = Node->getOperand(3); // RHS
2108 Tmp4 = Node->getOperand(1); // CC
2110 LegalizeSetCC(TLI.getSetCCResultType(Tmp2.getValueType()),
2111 Tmp2, Tmp3, Tmp4, dl);
2112 LastCALLSEQ_END = DAG.getEntryNode();
2114 // If we didn't get both a LHS and RHS back from LegalizeSetCC,
2115 // the LHS is a legal SETCC itself. In this case, we need to compare
2116 // the result against zero to select between true and false values.
2117 if (Tmp3.getNode() == 0) {
2118 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
2119 Tmp4 = DAG.getCondCode(ISD::SETNE);
2122 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
2123 Node->getOperand(4));
2125 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
2126 default: assert(0 && "Unexpected action for BR_CC!");
2127 case TargetLowering::Legal: break;
2128 case TargetLowering::Custom:
2129 Tmp4 = TLI.LowerOperation(Result, DAG);
2130 if (Tmp4.getNode()) Result = Tmp4;
2135 LoadSDNode *LD = cast<LoadSDNode>(Node);
2136 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
2137 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
2139 ISD::LoadExtType ExtType = LD->getExtensionType();
2140 if (ExtType == ISD::NON_EXTLOAD) {
2141 MVT VT = Node->getValueType(0);
2142 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2143 Tmp3 = Result.getValue(0);
2144 Tmp4 = Result.getValue(1);
2146 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
2147 default: assert(0 && "This action is not supported yet!");
2148 case TargetLowering::Legal:
2149 // If this is an unaligned load and the target doesn't support it,
2151 if (!TLI.allowsUnalignedMemoryAccesses()) {
2152 unsigned ABIAlignment = TLI.getTargetData()->
2153 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
2154 if (LD->getAlignment() < ABIAlignment){
2155 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
2157 Tmp3 = Result.getOperand(0);
2158 Tmp4 = Result.getOperand(1);
2159 Tmp3 = LegalizeOp(Tmp3);
2160 Tmp4 = LegalizeOp(Tmp4);
2164 case TargetLowering::Custom:
2165 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
2166 if (Tmp1.getNode()) {
2167 Tmp3 = LegalizeOp(Tmp1);
2168 Tmp4 = LegalizeOp(Tmp1.getValue(1));
2171 case TargetLowering::Promote: {
2172 // Only promote a load of vector type to another.
2173 assert(VT.isVector() && "Cannot promote this load!");
2174 // Change base type to a different vector type.
2175 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
2177 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
2178 LD->getSrcValueOffset(),
2179 LD->isVolatile(), LD->getAlignment());
2180 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp1));
2181 Tmp4 = LegalizeOp(Tmp1.getValue(1));
2185 // Since loads produce two values, make sure to remember that we
2186 // legalized both of them.
2187 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
2188 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
2189 return Op.getResNo() ? Tmp4 : Tmp3;
2191 MVT SrcVT = LD->getMemoryVT();
2192 unsigned SrcWidth = SrcVT.getSizeInBits();
2193 int SVOffset = LD->getSrcValueOffset();
2194 unsigned Alignment = LD->getAlignment();
2195 bool isVolatile = LD->isVolatile();
2197 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
2198 // Some targets pretend to have an i1 loading operation, and actually
2199 // load an i8. This trick is correct for ZEXTLOAD because the top 7
2200 // bits are guaranteed to be zero; it helps the optimizers understand
2201 // that these bits are zero. It is also useful for EXTLOAD, since it
2202 // tells the optimizers that those bits are undefined. It would be
2203 // nice to have an effective generic way of getting these benefits...
2204 // Until such a way is found, don't insist on promoting i1 here.
2205 (SrcVT != MVT::i1 ||
2206 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
2207 // Promote to a byte-sized load if not loading an integral number of
2208 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
2209 unsigned NewWidth = SrcVT.getStoreSizeInBits();
2210 MVT NVT = MVT::getIntegerVT(NewWidth);
2213 // The extra bits are guaranteed to be zero, since we stored them that
2214 // way. A zext load from NVT thus automatically gives zext from SrcVT.
2216 ISD::LoadExtType NewExtType =
2217 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
2219 Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
2220 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
2221 NVT, isVolatile, Alignment);
2223 Ch = Result.getValue(1); // The chain.
2225 if (ExtType == ISD::SEXTLOAD)
2226 // Having the top bits zero doesn't help when sign extending.
2227 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
2228 Result.getValueType(),
2229 Result, DAG.getValueType(SrcVT));
2230 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
2231 // All the top bits are guaranteed to be zero - inform the optimizers.
2232 Result = DAG.getNode(ISD::AssertZext, dl,
2233 Result.getValueType(), Result,
2234 DAG.getValueType(SrcVT));
2236 Tmp1 = LegalizeOp(Result);
2237 Tmp2 = LegalizeOp(Ch);
2238 } else if (SrcWidth & (SrcWidth - 1)) {
2239 // If not loading a power-of-2 number of bits, expand as two loads.
2240 assert(SrcVT.isExtended() && !SrcVT.isVector() &&
2241 "Unsupported extload!");
2242 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
2243 assert(RoundWidth < SrcWidth);
2244 unsigned ExtraWidth = SrcWidth - RoundWidth;
2245 assert(ExtraWidth < RoundWidth);
2246 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2247 "Load size not an integral number of bytes!");
2248 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2249 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2251 unsigned IncrementSize;
2253 if (TLI.isLittleEndian()) {
2254 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
2255 // Load the bottom RoundWidth bits.
2256 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl,
2257 Node->getValueType(0), Tmp1, Tmp2,
2258 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2261 // Load the remaining ExtraWidth bits.
2262 IncrementSize = RoundWidth / 8;
2263 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
2264 DAG.getIntPtrConstant(IncrementSize));
2265 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
2266 LD->getSrcValue(), SVOffset + IncrementSize,
2267 ExtraVT, isVolatile,
2268 MinAlign(Alignment, IncrementSize));
2270 // Build a factor node to remember that this load is independent of the
2272 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
2275 // Move the top bits to the right place.
2276 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
2277 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2279 // Join the hi and lo parts.
2280 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
2282 // Big endian - avoid unaligned loads.
2283 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
2284 // Load the top RoundWidth bits.
2285 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
2286 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2289 // Load the remaining ExtraWidth bits.
2290 IncrementSize = RoundWidth / 8;
2291 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
2292 DAG.getIntPtrConstant(IncrementSize));
2293 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl,
2294 Node->getValueType(0), Tmp1, Tmp2,
2295 LD->getSrcValue(), SVOffset + IncrementSize,
2296 ExtraVT, isVolatile,
2297 MinAlign(Alignment, IncrementSize));
2299 // Build a factor node to remember that this load is independent of the
2301 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
2304 // Move the top bits to the right place.
2305 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
2306 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2308 // Join the hi and lo parts.
2309 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
2312 Tmp1 = LegalizeOp(Result);
2313 Tmp2 = LegalizeOp(Ch);
2315 switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
2316 default: assert(0 && "This action is not supported yet!");
2317 case TargetLowering::Custom:
2320 case TargetLowering::Legal:
2321 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2322 Tmp1 = Result.getValue(0);
2323 Tmp2 = Result.getValue(1);
2326 Tmp3 = TLI.LowerOperation(Result, DAG);
2327 if (Tmp3.getNode()) {
2328 Tmp1 = LegalizeOp(Tmp3);
2329 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2332 // If this is an unaligned load and the target doesn't support it,
2334 if (!TLI.allowsUnalignedMemoryAccesses()) {
2335 unsigned ABIAlignment = TLI.getTargetData()->
2336 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
2337 if (LD->getAlignment() < ABIAlignment){
2338 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
2340 Tmp1 = Result.getOperand(0);
2341 Tmp2 = Result.getOperand(1);
2342 Tmp1 = LegalizeOp(Tmp1);
2343 Tmp2 = LegalizeOp(Tmp2);
2348 case TargetLowering::Expand:
2349 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
2350 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
2351 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
2352 LD->getSrcValueOffset(),
2353 LD->isVolatile(), LD->getAlignment());
2354 Result = DAG.getNode(ISD::FP_EXTEND, dl,
2355 Node->getValueType(0), Load);
2356 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
2357 Tmp2 = LegalizeOp(Load.getValue(1));
2360 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
2361 // Turn the unsupported load into an EXTLOAD followed by an explicit
2362 // zero/sign extend inreg.
2363 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
2364 Tmp1, Tmp2, LD->getSrcValue(),
2365 LD->getSrcValueOffset(), SrcVT,
2366 LD->isVolatile(), LD->getAlignment());
2368 if (ExtType == ISD::SEXTLOAD)
2369 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
2370 Result.getValueType(),
2371 Result, DAG.getValueType(SrcVT));
2373 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT);
2374 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
2375 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
2380 // Since loads produce two values, make sure to remember that we legalized
2382 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2383 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2384 return Op.getResNo() ? Tmp2 : Tmp1;
2387 case ISD::EXTRACT_ELEMENT: {
2388 MVT OpTy = Node->getOperand(0).getValueType();
2389 switch (getTypeAction(OpTy)) {
2390 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
2392 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
2394 Result = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
2395 DAG.getConstant(OpTy.getSizeInBits()/2,
2396 TLI.getShiftAmountTy()));
2397 Result = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Result);
2400 Result = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
2401 Node->getOperand(0));
2405 // Get both the low and high parts.
2406 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2407 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
2408 Result = Tmp2; // 1 -> Hi
2410 Result = Tmp1; // 0 -> Lo
2416 case ISD::CopyToReg:
2417 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2419 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
2420 "Register type must be legal!");
2421 // Legalize the incoming value (must be a legal type).
2422 Tmp2 = LegalizeOp(Node->getOperand(2));
2423 if (Node->getNumValues() == 1) {
2424 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
2426 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
2427 if (Node->getNumOperands() == 4) {
2428 Tmp3 = LegalizeOp(Node->getOperand(3));
2429 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
2432 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
2435 // Since this produces two values, make sure to remember that we legalized
2437 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
2438 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
2444 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2446 // Ensure that libcalls are emitted before a return.
2447 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
2448 Tmp1 = LegalizeOp(Tmp1);
2449 LastCALLSEQ_END = DAG.getEntryNode();
2451 switch (Node->getNumOperands()) {
2453 Tmp2 = Node->getOperand(1);
2454 Tmp3 = Node->getOperand(2); // Signness
2455 switch (getTypeAction(Tmp2.getValueType())) {
2457 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
2460 if (!Tmp2.getValueType().isVector()) {
2462 ExpandOp(Tmp2, Lo, Hi);
2464 // Big endian systems want the hi reg first.
2465 if (TLI.isBigEndian())
2469 Result = DAG.getNode(ISD::RET, dl, MVT::Other,
2470 Tmp1, Lo, Tmp3, Hi, Tmp3);
2472 Result = DAG.getNode(ISD::RET, dl, MVT::Other, Tmp1, Lo, Tmp3);
2473 Result = LegalizeOp(Result);
2475 SDNode *InVal = Tmp2.getNode();
2476 int InIx = Tmp2.getResNo();
2477 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
2478 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
2480 // Figure out if there is a simple type corresponding to this Vector
2481 // type. If so, convert to the vector type.
2482 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2483 if (TLI.isTypeLegal(TVT)) {
2484 // Turn this into a return of the vector type.
2485 Tmp2 = LegalizeOp(Tmp2);
2486 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2487 } else if (NumElems == 1) {
2488 // Turn this into a return of the scalar type.
2489 Tmp2 = ScalarizeVectorOp(Tmp2);
2490 Tmp2 = LegalizeOp(Tmp2);
2491 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2493 // FIXME: Returns of gcc generic vectors smaller than a legal type
2494 // should be returned in integer registers!
2496 // The scalarized value type may not be legal, e.g. it might require
2497 // promotion or expansion. Relegalize the return.
2498 Result = LegalizeOp(Result);
2500 // FIXME: Returns of gcc generic vectors larger than a legal vector
2501 // type should be returned by reference!
2503 SplitVectorOp(Tmp2, Lo, Hi);
2504 Result = DAG.getNode(ISD::RET, dl, MVT::Other,
2505 Tmp1, Lo, Tmp3, Hi, Tmp3);
2506 Result = LegalizeOp(Result);
2511 Tmp2 = PromoteOp(Node->getOperand(1));
2512 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2513 Result = LegalizeOp(Result);
2518 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2520 default: { // ret <values>
2521 SmallVector<SDValue, 8> NewValues;
2522 NewValues.push_back(Tmp1);
2523 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
2524 switch (getTypeAction(Node->getOperand(i).getValueType())) {
2526 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
2527 NewValues.push_back(Node->getOperand(i+1));
2531 assert(!Node->getOperand(i).getValueType().isExtended() &&
2532 "FIXME: TODO: implement returning non-legal vector types!");
2533 ExpandOp(Node->getOperand(i), Lo, Hi);
2534 NewValues.push_back(Lo);
2535 NewValues.push_back(Node->getOperand(i+1));
2537 NewValues.push_back(Hi);
2538 NewValues.push_back(Node->getOperand(i+1));
2543 assert(0 && "Can't promote multiple return value yet!");
2546 if (NewValues.size() == Node->getNumOperands())
2547 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
2549 Result = DAG.getNode(ISD::RET, dl, MVT::Other,
2550 &NewValues[0], NewValues.size());
2555 if (Result.getOpcode() == ISD::RET) {
2556 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
2557 default: assert(0 && "This action is not supported yet!");
2558 case TargetLowering::Legal: break;
2559 case TargetLowering::Custom:
2560 Tmp1 = TLI.LowerOperation(Result, DAG);
2561 if (Tmp1.getNode()) Result = Tmp1;
2567 StoreSDNode *ST = cast<StoreSDNode>(Node);
2568 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
2569 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
2570 int SVOffset = ST->getSrcValueOffset();
2571 unsigned Alignment = ST->getAlignment();
2572 bool isVolatile = ST->isVolatile();
2574 if (!ST->isTruncatingStore()) {
2575 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
2576 // FIXME: We shouldn't do this for TargetConstantFP's.
2577 // FIXME: move this to the DAG Combiner! Note that we can't regress due
2578 // to phase ordering between legalized code and the dag combiner. This
2579 // probably means that we need to integrate dag combiner and legalizer
2581 // We generally can't do this one for long doubles.
2582 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
2583 if (CFP->getValueType(0) == MVT::f32 &&
2584 getTypeAction(MVT::i32) == Legal) {
2585 Tmp3 = DAG.getConstant(CFP->getValueAPF().
2586 bitcastToAPInt().zextOrTrunc(32),
2588 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2589 SVOffset, isVolatile, Alignment);
2591 } else if (CFP->getValueType(0) == MVT::f64) {
2592 // If this target supports 64-bit registers, do a single 64-bit store.
2593 if (getTypeAction(MVT::i64) == Legal) {
2594 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
2595 zextOrTrunc(64), MVT::i64);
2596 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2597 SVOffset, isVolatile, Alignment);
2599 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
2600 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
2601 // stores. If the target supports neither 32- nor 64-bits, this
2602 // xform is certainly not worth it.
2603 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
2604 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
2605 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
2606 if (TLI.isBigEndian()) std::swap(Lo, Hi);
2608 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(),
2609 SVOffset, isVolatile, Alignment);
2610 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
2611 DAG.getIntPtrConstant(4));
2612 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
2613 isVolatile, MinAlign(Alignment, 4U));
2615 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2621 switch (getTypeAction(ST->getMemoryVT())) {
2623 Tmp3 = LegalizeOp(ST->getValue());
2624 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2627 MVT VT = Tmp3.getValueType();
2628 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2629 default: assert(0 && "This action is not supported yet!");
2630 case TargetLowering::Legal:
2631 // If this is an unaligned store and the target doesn't support it,
2633 if (!TLI.allowsUnalignedMemoryAccesses()) {
2634 unsigned ABIAlignment = TLI.getTargetData()->
2635 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2636 if (ST->getAlignment() < ABIAlignment)
2637 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
2641 case TargetLowering::Custom:
2642 Tmp1 = TLI.LowerOperation(Result, DAG);
2643 if (Tmp1.getNode()) Result = Tmp1;
2645 case TargetLowering::Promote:
2646 assert(VT.isVector() && "Unknown legal promote case!");
2647 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, dl,
2648 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2649 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2,
2650 ST->getSrcValue(), SVOffset, isVolatile,
2657 if (!ST->getMemoryVT().isVector()) {
2658 // Truncate the value and store the result.
2659 Tmp3 = PromoteOp(ST->getValue());
2660 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2661 SVOffset, ST->getMemoryVT(),
2662 isVolatile, Alignment);
2665 // Fall thru to expand for vector
2667 unsigned IncrementSize = 0;
2670 // If this is a vector type, then we have to calculate the increment as
2671 // the product of the element size in bytes, and the number of elements
2672 // in the high half of the vector.
2673 if (ST->getValue().getValueType().isVector()) {
2674 SDNode *InVal = ST->getValue().getNode();
2675 int InIx = ST->getValue().getResNo();
2676 MVT InVT = InVal->getValueType(InIx);
2677 unsigned NumElems = InVT.getVectorNumElements();
2678 MVT EVT = InVT.getVectorElementType();
2680 // Figure out if there is a simple type corresponding to this Vector
2681 // type. If so, convert to the vector type.
2682 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2683 if (TLI.isTypeLegal(TVT)) {
2684 // Turn this into a normal store of the vector type.
2685 Tmp3 = LegalizeOp(ST->getValue());
2686 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2687 SVOffset, isVolatile, Alignment);
2688 Result = LegalizeOp(Result);
2690 } else if (NumElems == 1) {
2691 // Turn this into a normal store of the scalar type.
2692 Tmp3 = ScalarizeVectorOp(ST->getValue());
2693 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2694 SVOffset, isVolatile, Alignment);
2695 // The scalarized value type may not be legal, e.g. it might require
2696 // promotion or expansion. Relegalize the scalar store.
2697 Result = LegalizeOp(Result);
2700 // Check if we have widen this node with another value
2701 std::map<SDValue, SDValue>::iterator I =
2702 WidenNodes.find(ST->getValue());
2703 if (I != WidenNodes.end()) {
2704 Result = StoreWidenVectorOp(ST, Tmp1, Tmp2);
2708 SplitVectorOp(ST->getValue(), Lo, Hi);
2709 IncrementSize = Lo.getNode()->getValueType(0).getVectorNumElements() *
2710 EVT.getSizeInBits()/8;
2714 ExpandOp(ST->getValue(), Lo, Hi);
2715 IncrementSize = Hi.getNode() ? Hi.getValueType().getSizeInBits()/8 : 0;
2717 if (Hi.getNode() && TLI.isBigEndian())
2721 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(),
2722 SVOffset, isVolatile, Alignment);
2724 if (Hi.getNode() == NULL) {
2725 // Must be int <-> float one-to-one expansion.
2730 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
2731 DAG.getIntPtrConstant(IncrementSize));
2732 assert(isTypeLegal(Tmp2.getValueType()) &&
2733 "Pointers must be legal!");
2734 SVOffset += IncrementSize;
2735 Alignment = MinAlign(Alignment, IncrementSize);
2736 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
2737 SVOffset, isVolatile, Alignment);
2738 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2743 switch (getTypeAction(ST->getValue().getValueType())) {
2745 Tmp3 = LegalizeOp(ST->getValue());
2748 if (!ST->getValue().getValueType().isVector()) {
2749 // We can promote the value, the truncstore will still take care of it.
2750 Tmp3 = PromoteOp(ST->getValue());
2753 // Vector case falls through to expand
2755 // Just store the low part. This may become a non-trunc store, so make
2756 // sure to use getTruncStore, not UpdateNodeOperands below.
2757 ExpandOp(ST->getValue(), Tmp3, Tmp4);
2758 return DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2759 SVOffset, MVT::i8, isVolatile, Alignment);
2762 MVT StVT = ST->getMemoryVT();
2763 unsigned StWidth = StVT.getSizeInBits();
2765 if (StWidth != StVT.getStoreSizeInBits()) {
2766 // Promote to a byte-sized store with upper bits zero if not
2767 // storing an integral number of bytes. For example, promote
2768 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
2769 MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits());
2770 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT);
2771 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2772 SVOffset, NVT, isVolatile, Alignment);
2773 } else if (StWidth & (StWidth - 1)) {
2774 // If not storing a power-of-2 number of bits, expand as two stores.
2775 assert(StVT.isExtended() && !StVT.isVector() &&
2776 "Unsupported truncstore!");
2777 unsigned RoundWidth = 1 << Log2_32(StWidth);
2778 assert(RoundWidth < StWidth);
2779 unsigned ExtraWidth = StWidth - RoundWidth;
2780 assert(ExtraWidth < RoundWidth);
2781 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2782 "Store size not an integral number of bytes!");
2783 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2784 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2786 unsigned IncrementSize;
2788 if (TLI.isLittleEndian()) {
2789 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
2790 // Store the bottom RoundWidth bits.
2791 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2793 isVolatile, Alignment);
2795 // Store the remaining ExtraWidth bits.
2796 IncrementSize = RoundWidth / 8;
2797 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
2798 DAG.getIntPtrConstant(IncrementSize));
2799 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
2800 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2801 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
2802 SVOffset + IncrementSize, ExtraVT, isVolatile,
2803 MinAlign(Alignment, IncrementSize));
2805 // Big endian - avoid unaligned stores.
2806 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
2807 // Store the top RoundWidth bits.
2808 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
2809 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2810 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
2811 SVOffset, RoundVT, isVolatile, Alignment);
2813 // Store the remaining ExtraWidth bits.
2814 IncrementSize = RoundWidth / 8;
2815 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
2816 DAG.getIntPtrConstant(IncrementSize));
2817 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2818 SVOffset + IncrementSize, ExtraVT, isVolatile,
2819 MinAlign(Alignment, IncrementSize));
2822 // The order of the stores doesn't matter.
2823 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2825 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2826 Tmp2 != ST->getBasePtr())
2827 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2830 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
2831 default: assert(0 && "This action is not supported yet!");
2832 case TargetLowering::Legal:
2833 // If this is an unaligned store and the target doesn't support it,
2835 if (!TLI.allowsUnalignedMemoryAccesses()) {
2836 unsigned ABIAlignment = TLI.getTargetData()->
2837 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2838 if (ST->getAlignment() < ABIAlignment)
2839 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
2843 case TargetLowering::Custom:
2844 Result = TLI.LowerOperation(Result, DAG);
2847 // TRUNCSTORE:i16 i32 -> STORE i16
2848 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
2849 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3);
2850 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2851 SVOffset, isVolatile, Alignment);
2859 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2860 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2862 case ISD::STACKSAVE:
2863 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2864 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2865 Tmp1 = Result.getValue(0);
2866 Tmp2 = Result.getValue(1);
2868 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2869 default: assert(0 && "This action is not supported yet!");
2870 case TargetLowering::Legal: break;
2871 case TargetLowering::Custom:
2872 Tmp3 = TLI.LowerOperation(Result, DAG);
2873 if (Tmp3.getNode()) {
2874 Tmp1 = LegalizeOp(Tmp3);
2875 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2878 case TargetLowering::Expand:
2879 // Expand to CopyFromReg if the target set
2880 // StackPointerRegisterToSaveRestore.
2881 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2882 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), dl, SP,
2883 Node->getValueType(0));
2884 Tmp2 = Tmp1.getValue(1);
2886 Tmp1 = DAG.getUNDEF(Node->getValueType(0));
2887 Tmp2 = Node->getOperand(0);
2892 // Since stacksave produce two values, make sure to remember that we
2893 // legalized both of them.
2894 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2895 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2896 return Op.getResNo() ? Tmp2 : Tmp1;
2898 case ISD::STACKRESTORE:
2899 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2900 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2901 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2903 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2904 default: assert(0 && "This action is not supported yet!");
2905 case TargetLowering::Legal: break;
2906 case TargetLowering::Custom:
2907 Tmp1 = TLI.LowerOperation(Result, DAG);
2908 if (Tmp1.getNode()) Result = Tmp1;
2910 case TargetLowering::Expand:
2911 // Expand to CopyToReg if the target set
2912 // StackPointerRegisterToSaveRestore.
2913 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2914 Result = DAG.getCopyToReg(Tmp1, dl, SP, Tmp2);
2922 case ISD::READCYCLECOUNTER:
2923 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2924 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2925 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2926 Node->getValueType(0))) {
2927 default: assert(0 && "This action is not supported yet!");
2928 case TargetLowering::Legal:
2929 Tmp1 = Result.getValue(0);
2930 Tmp2 = Result.getValue(1);
2932 case TargetLowering::Custom:
2933 Result = TLI.LowerOperation(Result, DAG);
2934 Tmp1 = LegalizeOp(Result.getValue(0));
2935 Tmp2 = LegalizeOp(Result.getValue(1));
2939 // Since rdcc produce two values, make sure to remember that we legalized
2941 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2942 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2946 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2947 case Expand: assert(0 && "It's impossible to expand bools");
2949 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2952 assert(!Node->getOperand(0).getValueType().isVector() && "not possible");
2953 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2954 // Make sure the condition is either zero or one.
2955 unsigned BitWidth = Tmp1.getValueSizeInBits();
2956 if (!DAG.MaskedValueIsZero(Tmp1,
2957 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2958 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, MVT::i1);
2962 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2963 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2965 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2967 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2968 default: assert(0 && "This action is not supported yet!");
2969 case TargetLowering::Legal: break;
2970 case TargetLowering::Custom: {
2971 Tmp1 = TLI.LowerOperation(Result, DAG);
2972 if (Tmp1.getNode()) Result = Tmp1;
2975 case TargetLowering::Expand:
2976 if (Tmp1.getOpcode() == ISD::SETCC) {
2977 Result = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
2979 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2981 Result = DAG.getSelectCC(dl, Tmp1,
2982 DAG.getConstant(0, Tmp1.getValueType()),
2983 Tmp2, Tmp3, ISD::SETNE);
2986 case TargetLowering::Promote: {
2988 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2989 unsigned ExtOp, TruncOp;
2990 if (Tmp2.getValueType().isVector()) {
2991 ExtOp = ISD::BIT_CONVERT;
2992 TruncOp = ISD::BIT_CONVERT;
2993 } else if (Tmp2.getValueType().isInteger()) {
2994 ExtOp = ISD::ANY_EXTEND;
2995 TruncOp = ISD::TRUNCATE;
2997 ExtOp = ISD::FP_EXTEND;
2998 TruncOp = ISD::FP_ROUND;
3000 // Promote each of the values to the new type.
3001 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Tmp2);
3002 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Tmp3);
3003 // Perform the larger operation, then round down.
3004 Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3);
3005 if (TruncOp != ISD::FP_ROUND)
3006 Result = DAG.getNode(TruncOp, dl, Node->getValueType(0), Result);
3008 Result = DAG.getNode(TruncOp, dl, Node->getValueType(0), Result,
3009 DAG.getIntPtrConstant(0));
3014 case ISD::SELECT_CC: {
3015 Tmp1 = Node->getOperand(0); // LHS
3016 Tmp2 = Node->getOperand(1); // RHS
3017 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
3018 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
3019 SDValue CC = Node->getOperand(4);
3021 LegalizeSetCC(TLI.getSetCCResultType(Tmp1.getValueType()),
3022 Tmp1, Tmp2, CC, dl);
3024 // If we didn't get both a LHS and RHS back from LegalizeSetCC,
3025 // the LHS is a legal SETCC itself. In this case, we need to compare
3026 // the result against zero to select between true and false values.
3027 if (Tmp2.getNode() == 0) {
3028 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3029 CC = DAG.getCondCode(ISD::SETNE);
3031 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
3033 // Everything is legal, see if we should expand this op or something.
3034 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
3035 default: assert(0 && "This action is not supported yet!");
3036 case TargetLowering::Legal: break;
3037 case TargetLowering::Custom:
3038 Tmp1 = TLI.LowerOperation(Result, DAG);
3039 if (Tmp1.getNode()) Result = Tmp1;
3045 Tmp1 = Node->getOperand(0);
3046 Tmp2 = Node->getOperand(1);
3047 Tmp3 = Node->getOperand(2);
3048 LegalizeSetCC(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl);
3050 // If we had to Expand the SetCC operands into a SELECT node, then it may
3051 // not always be possible to return a true LHS & RHS. In this case, just
3052 // return the value we legalized, returned in the LHS
3053 if (Tmp2.getNode() == 0) {
3058 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
3059 default: assert(0 && "Cannot handle this action for SETCC yet!");
3060 case TargetLowering::Custom:
3063 case TargetLowering::Legal:
3064 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3066 Tmp4 = TLI.LowerOperation(Result, DAG);
3067 if (Tmp4.getNode()) Result = Tmp4;
3070 case TargetLowering::Promote: {
3071 // First step, figure out the appropriate operation to use.
3072 // Allow SETCC to not be supported for all legal data types
3073 // Mostly this targets FP
3074 MVT NewInTy = Node->getOperand(0).getValueType();
3075 MVT OldVT = NewInTy; OldVT = OldVT;
3077 // Scan for the appropriate larger type to use.
3079 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
3081 assert(NewInTy.isInteger() == OldVT.isInteger() &&
3082 "Fell off of the edge of the integer world");
3083 assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() &&
3084 "Fell off of the edge of the floating point world");
3086 // If the target supports SETCC of this type, use it.
3087 if (TLI.isOperationLegalOrCustom(ISD::SETCC, NewInTy))
3090 if (NewInTy.isInteger())
3091 assert(0 && "Cannot promote Legal Integer SETCC yet");
3093 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NewInTy, Tmp1);
3094 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NewInTy, Tmp2);
3096 Tmp1 = LegalizeOp(Tmp1);
3097 Tmp2 = LegalizeOp(Tmp2);
3098 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3099 Result = LegalizeOp(Result);
3102 case TargetLowering::Expand:
3103 // Expand a setcc node into a select_cc of the same condition, lhs, and
3104 // rhs that selects between const 1 (true) and const 0 (false).
3105 MVT VT = Node->getValueType(0);
3106 Result = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3107 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3113 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3114 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3115 SDValue CC = Node->getOperand(2);
3117 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, CC);
3119 // Everything is legal, see if we should expand this op or something.
3120 switch (TLI.getOperationAction(ISD::VSETCC, Tmp1.getValueType())) {
3121 default: assert(0 && "This action is not supported yet!");
3122 case TargetLowering::Legal: break;
3123 case TargetLowering::Custom:
3124 Tmp1 = TLI.LowerOperation(Result, DAG);
3125 if (Tmp1.getNode()) Result = Tmp1;
3127 case TargetLowering::Expand: {
3128 // Unroll into a nasty set of scalar code for now.
3129 MVT VT = Node->getValueType(0);
3130 unsigned NumElems = VT.getVectorNumElements();
3131 MVT EltVT = VT.getVectorElementType();
3132 MVT TmpEltVT = Tmp1.getValueType().getVectorElementType();
3133 SmallVector<SDValue, 8> Ops(NumElems);
3134 for (unsigned i = 0; i < NumElems; ++i) {
3135 SDValue In1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT,
3136 Tmp1, DAG.getIntPtrConstant(i));
3137 Ops[i] = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(TmpEltVT),
3138 In1, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3140 DAG.getIntPtrConstant(i)),
3142 Ops[i] = DAG.getNode(ISD::SELECT, dl, EltVT, Ops[i],
3143 DAG.getConstant(APInt::getAllOnesValue
3144 (EltVT.getSizeInBits()), EltVT),
3145 DAG.getConstant(0, EltVT));
3147 Result = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElems);
3154 case ISD::SHL_PARTS:
3155 case ISD::SRA_PARTS:
3156 case ISD::SRL_PARTS: {
3157 SmallVector<SDValue, 8> Ops;
3158 bool Changed = false;
3159 unsigned N = Node->getNumOperands();
3160 for (unsigned i = 0; i + 1 < N; ++i) {
3161 Ops.push_back(LegalizeOp(Node->getOperand(i)));
3162 Changed |= Ops.back() != Node->getOperand(i);
3164 Ops.push_back(LegalizeOp(DAG.getShiftAmountOperand(Node->getOperand(N-1))));
3165 Changed |= Ops.back() != Node->getOperand(N-1);
3167 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
3169 switch (TLI.getOperationAction(Node->getOpcode(),
3170 Node->getValueType(0))) {
3171 default: assert(0 && "This action is not supported yet!");
3172 case TargetLowering::Legal: break;
3173 case TargetLowering::Custom:
3174 Tmp1 = TLI.LowerOperation(Result, DAG);
3175 if (Tmp1.getNode()) {
3176 SDValue Tmp2, RetVal(0, 0);
3177 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
3178 Tmp2 = LegalizeOp(Tmp1.getValue(i));
3179 AddLegalizedOperand(SDValue(Node, i), Tmp2);
3180 if (i == Op.getResNo())
3183 assert(RetVal.getNode() && "Illegal result number");
3189 // Since these produce multiple values, make sure to remember that we
3190 // legalized all of them.
3191 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
3192 AddLegalizedOperand(SDValue(Node, i), Result.getValue(i));
3193 return Result.getValue(Op.getResNo());
3215 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3216 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3218 if ((Node->getOpcode() == ISD::SHL ||
3219 Node->getOpcode() == ISD::SRL ||
3220 Node->getOpcode() == ISD::SRA) &&
3221 !Node->getValueType(0).isVector())
3222 Tmp2 = DAG.getShiftAmountOperand(Tmp2);
3224 switch (getTypeAction(Tmp2.getValueType())) {
3225 case Expand: assert(0 && "Not possible");
3227 Tmp2 = LegalizeOp(Tmp2); // Legalize the RHS.
3230 Tmp2 = PromoteOp(Tmp2); // Promote the RHS.
3234 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3236 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3237 default: assert(0 && "BinOp legalize operation not supported");
3238 case TargetLowering::Legal: break;
3239 case TargetLowering::Custom:
3240 Tmp1 = TLI.LowerOperation(Result, DAG);
3241 if (Tmp1.getNode()) {
3245 // Fall through if the custom lower can't deal with the operation
3246 case TargetLowering::Expand: {
3247 MVT VT = Op.getValueType();
3249 // See if multiply or divide can be lowered using two-result operations.
3250 SDVTList VTs = DAG.getVTList(VT, VT);
3251 if (Node->getOpcode() == ISD::MUL) {
3252 // We just need the low half of the multiply; try both the signed
3253 // and unsigned forms. If the target supports both SMUL_LOHI and
3254 // UMUL_LOHI, form a preference by checking which forms of plain
3255 // MULH it supports.
3256 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3257 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3258 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3259 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3260 unsigned OpToUse = 0;
3261 if (HasSMUL_LOHI && !HasMULHS) {
3262 OpToUse = ISD::SMUL_LOHI;
3263 } else if (HasUMUL_LOHI && !HasMULHU) {
3264 OpToUse = ISD::UMUL_LOHI;
3265 } else if (HasSMUL_LOHI) {
3266 OpToUse = ISD::SMUL_LOHI;
3267 } else if (HasUMUL_LOHI) {
3268 OpToUse = ISD::UMUL_LOHI;
3271 Result = SDValue(DAG.getNode(OpToUse, dl, VTs, Tmp1, Tmp2).getNode(),
3276 if (Node->getOpcode() == ISD::MULHS &&
3277 TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) {
3278 Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl,
3279 VTs, Tmp1, Tmp2).getNode(),
3283 if (Node->getOpcode() == ISD::MULHU &&
3284 TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) {
3285 Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl,
3286 VTs, Tmp1, Tmp2).getNode(),
3290 if (Node->getOpcode() == ISD::SDIV &&
3291 TLI.isOperationLegalOrCustom(ISD::SDIVREM, VT)) {
3292 Result = SDValue(DAG.getNode(ISD::SDIVREM, dl,
3293 VTs, Tmp1, Tmp2).getNode(),
3297 if (Node->getOpcode() == ISD::UDIV &&
3298 TLI.isOperationLegalOrCustom(ISD::UDIVREM, VT)) {
3299 Result = SDValue(DAG.getNode(ISD::UDIVREM, dl,
3300 VTs, Tmp1, Tmp2).getNode(),
3305 // Check to see if we have a libcall for this operator.
3306 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3307 bool isSigned = false;
3308 switch (Node->getOpcode()) {
3311 isSigned = Node->getOpcode() == ISD::SDIV;
3313 LC = (isSigned ? RTLIB::SDIV_I16 : RTLIB::UDIV_I16);
3314 else if (VT == MVT::i32)
3315 LC = (isSigned ? RTLIB::SDIV_I32 : RTLIB::UDIV_I32);
3316 else if (VT == MVT::i64)
3317 LC = (isSigned ? RTLIB::SDIV_I64 : RTLIB::UDIV_I64);
3318 else if (VT == MVT::i128)
3319 LC = (isSigned ? RTLIB::SDIV_I128 : RTLIB::UDIV_I128);
3323 LC = RTLIB::MUL_I16;
3324 else if (VT == MVT::i32)
3325 LC = RTLIB::MUL_I32;
3326 else if (VT == MVT::i64)
3327 LC = RTLIB::MUL_I64;
3328 else if (VT == MVT::i128)
3329 LC = RTLIB::MUL_I128;
3332 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
3333 RTLIB::POW_PPCF128);
3336 LC = GetFPLibCall(VT, RTLIB::DIV_F32, RTLIB::DIV_F64, RTLIB::DIV_F80,
3337 RTLIB::DIV_PPCF128);
3341 if (LC != RTLIB::UNKNOWN_LIBCALL) {
3343 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3347 assert(Node->getValueType(0).isVector() &&
3348 "Cannot expand this binary operator!");
3349 // Expand the operation into a bunch of nasty scalar code.
3350 Result = LegalizeOp(UnrollVectorOp(Op));
3353 case TargetLowering::Promote: {
3354 switch (Node->getOpcode()) {
3355 default: assert(0 && "Do not know how to promote this BinOp!");
3359 MVT OVT = Node->getValueType(0);
3360 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3361 assert(OVT.isVector() && "Cannot promote this BinOp!");
3362 // Bit convert each of the values to the new type.
3363 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp1);
3364 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp2);
3365 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3366 // Bit convert the result back the original type.
3367 Result = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Result);
3375 case ISD::SMUL_LOHI:
3376 case ISD::UMUL_LOHI:
3379 // These nodes will only be produced by target-specific lowering, so
3380 // they shouldn't be here if they aren't legal.
3381 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
3382 "This must be legal!");
3384 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3385 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3386 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3389 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
3390 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3391 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3392 case Expand: assert(0 && "Not possible");
3394 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3397 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3401 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3403 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3404 default: assert(0 && "Operation not supported");
3405 case TargetLowering::Custom:
3406 Tmp1 = TLI.LowerOperation(Result, DAG);
3407 if (Tmp1.getNode()) Result = Tmp1;
3409 case TargetLowering::Legal: break;
3410 case TargetLowering::Expand: {
3411 // If this target supports fabs/fneg natively and select is cheap,
3412 // do this efficiently.
3413 if (!TLI.isSelectExpensive() &&
3414 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
3415 TargetLowering::Legal &&
3416 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
3417 TargetLowering::Legal) {
3418 // Get the sign bit of the RHS.
3420 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
3421 SDValue SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, IVT, Tmp2);
3422 SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(IVT),
3423 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
3424 // Get the absolute value of the result.
3425 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
3426 // Select between the nabs and abs value based on the sign bit of
3428 Result = DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit,
3429 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(),
3432 Result = LegalizeOp(Result);
3436 // Otherwise, do bitwise ops!
3438 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
3439 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
3440 Result = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0), Result);
3441 Result = LegalizeOp(Result);
3449 Tmp1 = LegalizeOp(Node->getOperand(0));
3450 Tmp2 = LegalizeOp(Node->getOperand(1));
3451 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3452 Tmp3 = Result.getValue(0);
3453 Tmp4 = Result.getValue(1);
3455 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3456 default: assert(0 && "This action is not supported yet!");
3457 case TargetLowering::Legal:
3459 case TargetLowering::Custom:
3460 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
3461 if (Tmp1.getNode() != NULL) {
3462 Tmp3 = LegalizeOp(Tmp1);
3463 Tmp4 = LegalizeOp(Tmp1.getValue(1));
3467 // Since this produces two values, make sure to remember that we legalized
3469 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
3470 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
3471 return Op.getResNo() ? Tmp4 : Tmp3;
3475 Tmp1 = LegalizeOp(Node->getOperand(0));
3476 Tmp2 = LegalizeOp(Node->getOperand(1));
3477 Tmp3 = LegalizeOp(Node->getOperand(2));
3478 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3479 Tmp3 = Result.getValue(0);
3480 Tmp4 = Result.getValue(1);
3482 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3483 default: assert(0 && "This action is not supported yet!");
3484 case TargetLowering::Legal:
3486 case TargetLowering::Custom:
3487 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
3488 if (Tmp1.getNode() != NULL) {
3489 Tmp3 = LegalizeOp(Tmp1);
3490 Tmp4 = LegalizeOp(Tmp1.getValue(1));
3494 // Since this produces two values, make sure to remember that we legalized
3496 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
3497 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
3498 return Op.getResNo() ? Tmp4 : Tmp3;
3500 case ISD::BUILD_PAIR: {
3501 MVT PairTy = Node->getValueType(0);
3502 // TODO: handle the case where the Lo and Hi operands are not of legal type
3503 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
3504 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
3505 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
3506 case TargetLowering::Promote:
3507 case TargetLowering::Custom:
3508 assert(0 && "Cannot promote/custom this yet!");
3509 case TargetLowering::Legal:
3510 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
3511 Result = DAG.getNode(ISD::BUILD_PAIR, dl, PairTy, Tmp1, Tmp2);
3513 case TargetLowering::Expand:
3514 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Tmp1);
3515 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Tmp2);
3516 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
3517 DAG.getConstant(PairTy.getSizeInBits()/2,
3518 TLI.getShiftAmountTy()));
3519 Result = DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2);
3528 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3529 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3531 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3532 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
3533 case TargetLowering::Custom:
3536 case TargetLowering::Legal:
3537 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3539 Tmp1 = TLI.LowerOperation(Result, DAG);
3540 if (Tmp1.getNode()) Result = Tmp1;
3543 case TargetLowering::Expand: {
3544 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
3545 bool isSigned = DivOpc == ISD::SDIV;
3546 MVT VT = Node->getValueType(0);
3548 // See if remainder can be lowered using two-result operations.
3549 SDVTList VTs = DAG.getVTList(VT, VT);
3550 if (Node->getOpcode() == ISD::SREM &&
3551 TLI.isOperationLegalOrCustom(ISD::SDIVREM, VT)) {
3552 Result = SDValue(DAG.getNode(ISD::SDIVREM, dl,
3553 VTs, Tmp1, Tmp2).getNode(), 1);
3556 if (Node->getOpcode() == ISD::UREM &&
3557 TLI.isOperationLegalOrCustom(ISD::UDIVREM, VT)) {
3558 Result = SDValue(DAG.getNode(ISD::UDIVREM, dl,
3559 VTs, Tmp1, Tmp2).getNode(), 1);
3563 if (VT.isInteger()) {
3564 if (TLI.getOperationAction(DivOpc, VT) ==
3565 TargetLowering::Legal) {
3567 Result = DAG.getNode(DivOpc, dl, VT, Tmp1, Tmp2);
3568 Result = DAG.getNode(ISD::MUL, dl, VT, Result, Tmp2);
3569 Result = DAG.getNode(ISD::SUB, dl, VT, Tmp1, Result);
3570 } else if (VT.isVector()) {
3571 Result = LegalizeOp(UnrollVectorOp(Op));
3573 assert(VT == MVT::i32 &&
3574 "Cannot expand this binary operator!");
3575 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
3576 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
3578 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3581 assert(VT.isFloatingPoint() &&
3582 "remainder op must have integer or floating-point type");
3583 if (VT.isVector()) {
3584 Result = LegalizeOp(UnrollVectorOp(Op));
3586 // Floating point mod -> fmod libcall.
3587 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
3588 RTLIB::REM_F80, RTLIB::REM_PPCF128);
3590 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3598 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3599 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3601 MVT VT = Node->getValueType(0);
3602 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
3603 default: assert(0 && "This action is not supported yet!");
3604 case TargetLowering::Custom:
3607 case TargetLowering::Legal:
3608 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3609 Result = Result.getValue(0);
3610 Tmp1 = Result.getValue(1);
3613 Tmp2 = TLI.LowerOperation(Result, DAG);
3614 if (Tmp2.getNode()) {
3615 Result = LegalizeOp(Tmp2);
3616 Tmp1 = LegalizeOp(Tmp2.getValue(1));
3620 case TargetLowering::Expand: {
3621 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3622 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0);
3623 // Increment the pointer, VAList, to the next vaarg
3624 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
3625 DAG.getConstant(TLI.getTargetData()->
3626 getTypePaddedSize(VT.getTypeForMVT()),
3627 TLI.getPointerTy()));
3628 // Store the incremented VAList to the legalized pointer
3629 Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0);
3630 // Load the actual argument out of the pointer VAList
3631 Result = DAG.getLoad(VT, dl, Tmp3, VAList, NULL, 0);
3632 Tmp1 = LegalizeOp(Result.getValue(1));
3633 Result = LegalizeOp(Result);
3637 // Since VAARG produces two values, make sure to remember that we
3638 // legalized both of them.
3639 AddLegalizedOperand(SDValue(Node, 0), Result);
3640 AddLegalizedOperand(SDValue(Node, 1), Tmp1);
3641 return Op.getResNo() ? Tmp1 : Result;
3645 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3646 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
3647 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
3649 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
3650 default: assert(0 && "This action is not supported yet!");
3651 case TargetLowering::Custom:
3654 case TargetLowering::Legal:
3655 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
3656 Node->getOperand(3), Node->getOperand(4));
3658 Tmp1 = TLI.LowerOperation(Result, DAG);
3659 if (Tmp1.getNode()) Result = Tmp1;
3662 case TargetLowering::Expand:
3663 // This defaults to loading a pointer from the input and storing it to the
3664 // output, returning the chain.
3665 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3666 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3667 Tmp4 = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp3, VS, 0);
3668 Result = DAG.getStore(Tmp4.getValue(1), dl, Tmp4, Tmp2, VD, 0);
3674 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3675 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3677 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
3678 default: assert(0 && "This action is not supported yet!");
3679 case TargetLowering::Custom:
3682 case TargetLowering::Legal:
3683 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3685 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
3686 if (Tmp1.getNode()) Result = Tmp1;
3689 case TargetLowering::Expand:
3690 Result = Tmp1; // Default to a no-op, return the chain
3696 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3697 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3699 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3701 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
3702 default: assert(0 && "This action is not supported yet!");
3703 case TargetLowering::Legal: break;
3704 case TargetLowering::Custom:
3705 Tmp1 = TLI.LowerOperation(Result, DAG);
3706 if (Tmp1.getNode()) Result = Tmp1;
3713 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3714 Tmp2 = LegalizeOp(DAG.getShiftAmountOperand(Node->getOperand(1))); // RHS
3715 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3716 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3718 assert(0 && "ROTL/ROTR legalize operation not supported");
3720 case TargetLowering::Legal:
3722 case TargetLowering::Custom:
3723 Tmp1 = TLI.LowerOperation(Result, DAG);
3724 if (Tmp1.getNode()) Result = Tmp1;
3726 case TargetLowering::Promote:
3727 assert(0 && "Do not know how to promote ROTL/ROTR");
3729 case TargetLowering::Expand:
3730 assert(0 && "Do not know how to expand ROTL/ROTR");
3736 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3737 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3738 case TargetLowering::Custom:
3739 assert(0 && "Cannot custom legalize this yet!");
3740 case TargetLowering::Legal:
3741 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3743 case TargetLowering::Promote: {
3744 MVT OVT = Tmp1.getValueType();
3745 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3746 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3748 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1);
3749 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
3750 Result = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
3751 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3754 case TargetLowering::Expand:
3755 Result = ExpandBSWAP(Tmp1, dl);
3763 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3764 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3765 case TargetLowering::Custom:
3766 case TargetLowering::Legal:
3767 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3768 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3769 TargetLowering::Custom) {
3770 Tmp1 = TLI.LowerOperation(Result, DAG);
3771 if (Tmp1.getNode()) {
3776 case TargetLowering::Promote: {
3777 MVT OVT = Tmp1.getValueType();
3778 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3780 // Zero extend the argument.
3781 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1);
3782 // Perform the larger operation, then subtract if needed.
3783 Tmp1 = DAG.getNode(Node->getOpcode(), dl, Node->getValueType(0), Tmp1);
3784 switch (Node->getOpcode()) {
3789 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3790 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
3791 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
3793 Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
3794 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3797 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3798 Result = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
3799 DAG.getConstant(NVT.getSizeInBits() -
3800 OVT.getSizeInBits(), NVT));
3805 case TargetLowering::Expand:
3806 Result = ExpandBitCount(Node->getOpcode(), Tmp1, dl);
3826 case ISD::FNEARBYINT:
3827 Tmp1 = LegalizeOp(Node->getOperand(0));
3828 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3829 case TargetLowering::Promote:
3830 case TargetLowering::Custom:
3833 case TargetLowering::Legal:
3834 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3836 Tmp1 = TLI.LowerOperation(Result, DAG);
3837 if (Tmp1.getNode()) Result = Tmp1;
3840 case TargetLowering::Expand:
3841 switch (Node->getOpcode()) {
3842 default: assert(0 && "Unreachable!");
3844 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3845 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3846 Result = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp2, Tmp1);
3849 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3850 MVT VT = Node->getValueType(0);
3851 Tmp2 = DAG.getConstantFP(0.0, VT);
3852 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
3853 Tmp1, Tmp2, ISD::SETUGT);
3854 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
3855 Result = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3);
3870 case ISD::FNEARBYINT: {
3871 MVT VT = Node->getValueType(0);
3873 // Expand unsupported unary vector operators by unrolling them.
3874 if (VT.isVector()) {
3875 Result = LegalizeOp(UnrollVectorOp(Op));
3879 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3880 switch(Node->getOpcode()) {
3882 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3883 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
3886 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
3887 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
3890 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
3891 RTLIB::COS_F80, RTLIB::COS_PPCF128);
3894 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
3895 RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
3898 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3899 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
3902 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3903 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
3906 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
3907 RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
3910 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3911 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
3914 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3915 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
3918 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3919 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128);
3922 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3923 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128);
3926 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64,
3927 RTLIB::RINT_F80, RTLIB::RINT_PPCF128);
3929 case ISD::FNEARBYINT:
3930 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
3931 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
3934 default: assert(0 && "Unreachable!");
3937 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3945 MVT VT = Node->getValueType(0);
3947 // Expand unsupported unary vector operators by unrolling them.
3948 if (VT.isVector()) {
3949 Result = LegalizeOp(UnrollVectorOp(Op));
3953 // We always lower FPOWI into a libcall. No target support for it yet.
3954 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
3955 RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
3957 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3960 case ISD::BIT_CONVERT:
3961 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3962 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3963 Node->getValueType(0), dl);
3964 } else if (Op.getOperand(0).getValueType().isVector()) {
3965 // The input has to be a vector type, we have to either scalarize it, pack
3966 // it, or convert it based on whether the input vector type is legal.
3967 SDNode *InVal = Node->getOperand(0).getNode();
3968 int InIx = Node->getOperand(0).getResNo();
3969 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
3970 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
3972 // Figure out if there is a simple type corresponding to this Vector
3973 // type. If so, convert to the vector type.
3974 MVT TVT = MVT::getVectorVT(EVT, NumElems);
3975 if (TLI.isTypeLegal(TVT)) {
3976 // Turn this into a bit convert of the vector input.
3977 Tmp1 = LegalizeOp(Node->getOperand(0));
3978 Result = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0), Tmp1);
3980 } else if (NumElems == 1) {
3981 // Turn this into a bit convert of the scalar input.
3982 Result = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0),
3983 ScalarizeVectorOp(Node->getOperand(0)));
3986 // FIXME: UNIMP! Store then reload
3987 assert(0 && "Cast from unsupported vector type not implemented yet!");
3990 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3991 Node->getOperand(0).getValueType())) {
3992 default: assert(0 && "Unknown operation action!");
3993 case TargetLowering::Expand:
3994 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3995 Node->getValueType(0), dl);
3997 case TargetLowering::Legal:
3998 Tmp1 = LegalizeOp(Node->getOperand(0));
3999 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4004 case ISD::CONVERT_RNDSAT: {
4005 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
4007 default: assert(0 && "Unknown cvt code!");
4018 SDValue DTyOp = Node->getOperand(1);
4019 SDValue STyOp = Node->getOperand(2);
4020 SDValue RndOp = Node->getOperand(3);
4021 SDValue SatOp = Node->getOperand(4);
4022 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4023 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4025 Tmp1 = LegalizeOp(Node->getOperand(0));
4026 Result = DAG.UpdateNodeOperands(Result, Tmp1, DTyOp, STyOp,
4028 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
4029 TargetLowering::Custom) {
4030 Tmp1 = TLI.LowerOperation(Result, DAG);
4031 if (Tmp1.getNode()) Result = Tmp1;
4035 Result = PromoteOp(Node->getOperand(0));
4036 // For FP, make Op1 a i32
4038 Result = DAG.getConvertRndSat(Op.getValueType(), dl, Result,
4039 DTyOp, STyOp, RndOp, SatOp, CvtCode);
4044 } // end switch CvtCode
4047 // Conversion operators. The source and destination have different types.
4048 case ISD::SINT_TO_FP:
4049 case ISD::UINT_TO_FP: {
4050 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
4051 Result = LegalizeINT_TO_FP(Result, isSigned,
4052 Node->getValueType(0), Node->getOperand(0), dl);
4056 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4058 Tmp1 = LegalizeOp(Node->getOperand(0));
4059 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
4060 default: assert(0 && "Unknown TRUNCATE legalization operation action!");
4061 case TargetLowering::Custom:
4064 case TargetLowering::Legal:
4065 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4067 Tmp1 = TLI.LowerOperation(Result, DAG);
4068 if (Tmp1.getNode()) Result = Tmp1;
4071 case TargetLowering::Expand:
4072 assert(Result.getValueType().isVector() && "must be vector type");
4073 // Unroll the truncate. We should do better.
4074 Result = LegalizeOp(UnrollVectorOp(Result));
4078 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4080 // Since the result is legal, we should just be able to truncate the low
4081 // part of the source.
4082 Result = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
4085 Result = PromoteOp(Node->getOperand(0));
4086 Result = DAG.getNode(ISD::TRUNCATE, dl, Op.getValueType(), Result);
4091 case ISD::FP_TO_SINT:
4092 case ISD::FP_TO_UINT:
4093 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4095 Tmp1 = LegalizeOp(Node->getOperand(0));
4097 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
4098 default: assert(0 && "Unknown operation action!");
4099 case TargetLowering::Custom:
4102 case TargetLowering::Legal:
4103 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4105 Tmp1 = TLI.LowerOperation(Result, DAG);
4106 if (Tmp1.getNode()) Result = Tmp1;
4109 case TargetLowering::Promote:
4110 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
4111 Node->getOpcode() == ISD::FP_TO_SINT,
4114 case TargetLowering::Expand:
4115 if (Node->getOpcode() == ISD::FP_TO_UINT) {
4116 SDValue True, False;
4117 MVT VT = Node->getOperand(0).getValueType();
4118 MVT NVT = Node->getValueType(0);
4119 const uint64_t zero[] = {0, 0};
4120 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero));
4121 APInt x = APInt::getSignBit(NVT.getSizeInBits());
4122 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
4123 Tmp2 = DAG.getConstantFP(apf, VT);
4124 Tmp3 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
4125 Node->getOperand(0),
4127 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
4128 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
4129 DAG.getNode(ISD::FSUB, dl, VT,
4130 Node->getOperand(0), Tmp2));
4131 False = DAG.getNode(ISD::XOR, dl, NVT, False,
4132 DAG.getConstant(x, NVT));
4133 Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp3, True, False);
4136 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
4142 MVT VT = Op.getValueType();
4143 MVT OVT = Node->getOperand(0).getValueType();
4144 // Convert ppcf128 to i32
4145 if (OVT == MVT::ppcf128 && VT == MVT::i32) {
4146 if (Node->getOpcode() == ISD::FP_TO_SINT) {
4147 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, MVT::ppcf128,
4148 Node->getOperand(0), DAG.getValueType(MVT::f64));
4149 Result = DAG.getNode(ISD::FP_ROUND, dl, MVT::f64, Result,
4150 DAG.getIntPtrConstant(1));
4151 Result = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Result);
4153 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
4154 APFloat apf = APFloat(APInt(128, 2, TwoE31));
4155 Tmp2 = DAG.getConstantFP(apf, OVT);
4156 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
4157 // FIXME: generated code sucks.
4158 Result = DAG.getNode(ISD::SELECT_CC, dl, VT, Node->getOperand(0),
4160 DAG.getNode(ISD::ADD, dl, MVT::i32,
4161 DAG.getNode(ISD::FP_TO_SINT, dl, VT,
4162 DAG.getNode(ISD::FSUB, dl, OVT,
4163 Node->getOperand(0), Tmp2)),
4164 DAG.getConstant(0x80000000, MVT::i32)),
4165 DAG.getNode(ISD::FP_TO_SINT, dl, VT,
4166 Node->getOperand(0)),
4167 DAG.getCondCode(ISD::SETGE));
4171 // Convert f32 / f64 to i32 / i64 / i128.
4172 RTLIB::Libcall LC = (Node->getOpcode() == ISD::FP_TO_SINT) ?
4173 RTLIB::getFPTOSINT(OVT, VT) : RTLIB::getFPTOUINT(OVT, VT);
4174 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpectd fp-to-int conversion!");
4176 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
4180 Tmp1 = PromoteOp(Node->getOperand(0));
4181 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
4182 Result = LegalizeOp(Result);
4187 case ISD::FP_EXTEND: {
4188 MVT DstVT = Op.getValueType();
4189 MVT SrcVT = Op.getOperand(0).getValueType();
4190 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
4191 // The only other way we can lower this is to turn it into a STORE,
4192 // LOAD pair, targetting a temporary location (a stack slot).
4193 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT, dl);
4196 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4197 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4199 Tmp1 = LegalizeOp(Node->getOperand(0));
4200 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4203 Tmp1 = PromoteOp(Node->getOperand(0));
4204 Result = DAG.getNode(ISD::FP_EXTEND, dl, Op.getValueType(), Tmp1);
4209 case ISD::FP_ROUND: {
4210 MVT DstVT = Op.getValueType();
4211 MVT SrcVT = Op.getOperand(0).getValueType();
4212 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
4213 if (SrcVT == MVT::ppcf128) {
4215 ExpandOp(Node->getOperand(0), Lo, Result);
4216 // Round it the rest of the way (e.g. to f32) if needed.
4217 if (DstVT!=MVT::f64)
4218 Result = DAG.getNode(ISD::FP_ROUND, dl,
4219 DstVT, Result, Op.getOperand(1));
4222 // The only other way we can lower this is to turn it into a STORE,
4223 // LOAD pair, targetting a temporary location (a stack slot).
4224 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT, dl);
4227 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4228 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4230 Tmp1 = LegalizeOp(Node->getOperand(0));
4231 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
4234 Tmp1 = PromoteOp(Node->getOperand(0));
4235 Result = DAG.getNode(ISD::FP_ROUND, dl, Op.getValueType(), Tmp1,
4236 Node->getOperand(1));
4241 case ISD::ANY_EXTEND:
4242 case ISD::ZERO_EXTEND:
4243 case ISD::SIGN_EXTEND:
4244 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4245 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4247 Tmp1 = LegalizeOp(Node->getOperand(0));
4248 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4249 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
4250 TargetLowering::Custom) {
4251 Tmp1 = TLI.LowerOperation(Result, DAG);
4252 if (Tmp1.getNode()) Result = Tmp1;
4256 switch (Node->getOpcode()) {
4257 case ISD::ANY_EXTEND:
4258 Tmp1 = PromoteOp(Node->getOperand(0));
4259 Result = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), Tmp1);
4261 case ISD::ZERO_EXTEND:
4262 Result = PromoteOp(Node->getOperand(0));
4263 Result = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), Result);
4264 Result = DAG.getZeroExtendInReg(Result, dl,
4265 Node->getOperand(0).getValueType());
4267 case ISD::SIGN_EXTEND:
4268 Result = PromoteOp(Node->getOperand(0));
4269 Result = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), Result);
4270 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Result.getValueType(),
4272 DAG.getValueType(Node->getOperand(0).getValueType()));
4277 case ISD::FP_ROUND_INREG:
4278 case ISD::SIGN_EXTEND_INREG: {
4279 Tmp1 = LegalizeOp(Node->getOperand(0));
4280 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
4282 // If this operation is not supported, convert it to a shl/shr or load/store
4284 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
4285 default: assert(0 && "This action not supported for this op yet!");
4286 case TargetLowering::Legal:
4287 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
4289 case TargetLowering::Expand:
4290 // If this is an integer extend and shifts are supported, do that.
4291 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
4292 // NOTE: we could fall back on load/store here too for targets without
4293 // SAR. However, it is doubtful that any exist.
4294 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() -
4295 ExtraVT.getSizeInBits();
4296 SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
4297 Result = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
4298 Node->getOperand(0), ShiftCst);
4299 Result = DAG.getNode(ISD::SRA, dl, Node->getValueType(0),
4301 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
4302 // The only way we can lower this is to turn it into a TRUNCSTORE,
4303 // EXTLOAD pair, targetting a temporary location (a stack slot).
4305 // NOTE: there is a choice here between constantly creating new stack
4306 // slots and always reusing the same one. We currently always create
4307 // new ones, as reuse may inhibit scheduling.
4308 Result = EmitStackConvert(Node->getOperand(0), ExtraVT,
4309 Node->getValueType(0), dl);
4311 assert(0 && "Unknown op");
4317 case ISD::TRAMPOLINE: {
4319 for (unsigned i = 0; i != 6; ++i)
4320 Ops[i] = LegalizeOp(Node->getOperand(i));
4321 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
4322 // The only option for this node is to custom lower it.
4323 Result = TLI.LowerOperation(Result, DAG);
4324 assert(Result.getNode() && "Should always custom lower!");
4326 // Since trampoline produces two values, make sure to remember that we
4327 // legalized both of them.
4328 Tmp1 = LegalizeOp(Result.getValue(1));
4329 Result = LegalizeOp(Result);
4330 AddLegalizedOperand(SDValue(Node, 0), Result);
4331 AddLegalizedOperand(SDValue(Node, 1), Tmp1);
4332 return Op.getResNo() ? Tmp1 : Result;
4334 case ISD::FLT_ROUNDS_: {
4335 MVT VT = Node->getValueType(0);
4336 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4337 default: assert(0 && "This action not supported for this op yet!");
4338 case TargetLowering::Custom:
4339 Result = TLI.LowerOperation(Op, DAG);
4340 if (Result.getNode()) break;
4342 case TargetLowering::Legal:
4343 // If this operation is not supported, lower it to constant 1
4344 Result = DAG.getConstant(1, VT);
4350 MVT VT = Node->getValueType(0);
4351 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4352 default: assert(0 && "This action not supported for this op yet!");
4353 case TargetLowering::Legal:
4354 Tmp1 = LegalizeOp(Node->getOperand(0));
4355 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4357 case TargetLowering::Custom:
4358 Result = TLI.LowerOperation(Op, DAG);
4359 if (Result.getNode()) break;
4361 case TargetLowering::Expand:
4362 // If this operation is not supported, lower it to 'abort()' call
4363 Tmp1 = LegalizeOp(Node->getOperand(0));
4364 TargetLowering::ArgListTy Args;
4365 std::pair<SDValue, SDValue> CallResult =
4366 TLI.LowerCallTo(Tmp1, Type::VoidTy,
4367 false, false, false, false, CallingConv::C, false,
4368 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
4370 Result = CallResult.second;
4378 MVT VT = Node->getValueType(0);
4379 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4380 default: assert(0 && "This action not supported for this op yet!");
4381 case TargetLowering::Custom:
4382 Result = TLI.LowerOperation(Op, DAG);
4383 if (Result.getNode()) break;
4385 case TargetLowering::Legal: {
4386 SDValue LHS = LegalizeOp(Node->getOperand(0));
4387 SDValue RHS = LegalizeOp(Node->getOperand(1));
4389 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
4390 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
4392 MVT OType = Node->getValueType(1);
4394 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
4396 // LHSSign -> LHS >= 0
4397 // RHSSign -> RHS >= 0
4398 // SumSign -> Sum >= 0
4401 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
4403 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
4405 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
4406 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
4407 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
4408 Node->getOpcode() == ISD::SADDO ?
4409 ISD::SETEQ : ISD::SETNE);
4411 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
4412 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
4414 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
4416 MVT ValueVTs[] = { LHS.getValueType(), OType };
4417 SDValue Ops[] = { Sum, Cmp };
4419 Result = DAG.getNode(ISD::MERGE_VALUES, dl,
4420 DAG.getVTList(&ValueVTs[0], 2),
4422 SDNode *RNode = Result.getNode();
4423 DAG.ReplaceAllUsesWith(Node, RNode);
4432 MVT VT = Node->getValueType(0);
4433 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4434 default: assert(0 && "This action not supported for this op yet!");
4435 case TargetLowering::Custom:
4436 Result = TLI.LowerOperation(Op, DAG);
4437 if (Result.getNode()) break;
4439 case TargetLowering::Legal: {
4440 SDValue LHS = LegalizeOp(Node->getOperand(0));
4441 SDValue RHS = LegalizeOp(Node->getOperand(1));
4443 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
4444 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
4446 MVT OType = Node->getValueType(1);
4447 SDValue Cmp = DAG.getSetCC(dl, OType, Sum, LHS,
4448 Node->getOpcode () == ISD::UADDO ?
4449 ISD::SETULT : ISD::SETUGT);
4451 MVT ValueVTs[] = { LHS.getValueType(), OType };
4452 SDValue Ops[] = { Sum, Cmp };
4454 Result = DAG.getNode(ISD::MERGE_VALUES, dl,
4455 DAG.getVTList(&ValueVTs[0], 2),
4457 SDNode *RNode = Result.getNode();
4458 DAG.ReplaceAllUsesWith(Node, RNode);
4467 MVT VT = Node->getValueType(0);
4468 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4469 default: assert(0 && "This action is not supported at all!");
4470 case TargetLowering::Custom:
4471 Result = TLI.LowerOperation(Op, DAG);
4472 if (Result.getNode()) break;
4474 case TargetLowering::Legal:
4475 // FIXME: According to Hacker's Delight, this can be implemented in
4476 // target independent lowering, but it would be inefficient, since it
4477 // requires a division + a branch.
4478 assert(0 && "Target independent lowering is not supported for SMULO/UMULO!");
4486 assert(Result.getValueType() == Op.getValueType() &&
4487 "Bad legalization!");
4489 // Make sure that the generated code is itself legal.
4491 Result = LegalizeOp(Result);
4493 // Note that LegalizeOp may be reentered even from single-use nodes, which
4494 // means that we always must cache transformed nodes.
4495 AddLegalizedOperand(Op, Result);
4499 /// PromoteOp - Given an operation that produces a value in an invalid type,
4500 /// promote it to compute the value into a larger type. The produced value will
4501 /// have the correct bits for the low portion of the register, but no guarantee
4502 /// is made about the top bits: it may be zero, sign-extended, or garbage.
4503 SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) {
4504 MVT VT = Op.getValueType();
4505 MVT NVT = TLI.getTypeToTransformTo(VT);
4506 assert(getTypeAction(VT) == Promote &&
4507 "Caller should expand or legalize operands that are not promotable!");
4508 assert(NVT.bitsGT(VT) && NVT.isInteger() == VT.isInteger() &&
4509 "Cannot promote to smaller type!");
4511 SDValue Tmp1, Tmp2, Tmp3;
4513 SDNode *Node = Op.getNode();
4514 DebugLoc dl = Node->getDebugLoc();
4516 DenseMap<SDValue, SDValue>::iterator I = PromotedNodes.find(Op);
4517 if (I != PromotedNodes.end()) return I->second;
4519 switch (Node->getOpcode()) {
4520 case ISD::CopyFromReg:
4521 assert(0 && "CopyFromReg must be legal!");
4524 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
4526 assert(0 && "Do not know how to promote this operator!");
4529 Result = DAG.getUNDEF(NVT);
4533 Result = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, Op);
4535 Result = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Op);
4536 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
4538 case ISD::ConstantFP:
4539 Result = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Op);
4540 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
4544 MVT VT0 = Node->getOperand(0).getValueType();
4545 assert(isTypeLegal(TLI.getSetCCResultType(VT0))
4546 && "SetCC type is not legal??");
4547 Result = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(VT0),
4548 Node->getOperand(0), Node->getOperand(1),
4549 Node->getOperand(2));
4553 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4555 Result = LegalizeOp(Node->getOperand(0));
4556 assert(Result.getValueType().bitsGE(NVT) &&
4557 "This truncation doesn't make sense!");
4558 if (Result.getValueType().bitsGT(NVT)) // Truncate to NVT instead of VT
4559 Result = DAG.getNode(ISD::TRUNCATE, dl, NVT, Result);
4562 // The truncation is not required, because we don't guarantee anything
4563 // about high bits anyway.
4564 Result = PromoteOp(Node->getOperand(0));
4567 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4568 // Truncate the low part of the expanded value to the result type
4569 Result = DAG.getNode(ISD::TRUNCATE, dl, NVT, Tmp1);
4572 case ISD::SIGN_EXTEND:
4573 case ISD::ZERO_EXTEND:
4574 case ISD::ANY_EXTEND:
4575 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4576 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
4578 // Input is legal? Just do extend all the way to the larger type.
4579 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Node->getOperand(0));
4582 // Promote the reg if it's smaller.
4583 Result = PromoteOp(Node->getOperand(0));
4584 // The high bits are not guaranteed to be anything. Insert an extend.
4585 if (Node->getOpcode() == ISD::SIGN_EXTEND)
4586 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Result,
4587 DAG.getValueType(Node->getOperand(0).getValueType()));
4588 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
4589 Result = DAG.getZeroExtendInReg(Result, dl,
4590 Node->getOperand(0).getValueType());
4594 case ISD::CONVERT_RNDSAT: {
4595 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
4596 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
4597 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
4598 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
4599 "can only promote integers");
4600 Result = DAG.getConvertRndSat(NVT, dl, Node->getOperand(0),
4601 Node->getOperand(1), Node->getOperand(2),
4602 Node->getOperand(3), Node->getOperand(4),
4607 case ISD::BIT_CONVERT:
4608 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
4609 Node->getValueType(0), dl);
4610 Result = PromoteOp(Result);
4613 case ISD::FP_EXTEND:
4614 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
4616 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4617 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
4618 case Promote: assert(0 && "Unreachable with 2 FP types!");
4620 if (Node->getConstantOperandVal(1) == 0) {
4621 // Input is legal? Do an FP_ROUND_INREG.
4622 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Node->getOperand(0),
4623 DAG.getValueType(VT));
4625 // Just remove the truncate, it isn't affecting the value.
4626 Result = DAG.getNode(ISD::FP_ROUND, dl, NVT, Node->getOperand(0),
4627 Node->getOperand(1));
4632 case ISD::SINT_TO_FP:
4633 case ISD::UINT_TO_FP:
4634 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4636 // No extra round required here.
4637 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Node->getOperand(0));
4641 Result = PromoteOp(Node->getOperand(0));
4642 if (Node->getOpcode() == ISD::SINT_TO_FP)
4643 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Result.getValueType(),
4645 DAG.getValueType(Node->getOperand(0).getValueType()));
4647 Result = DAG.getZeroExtendInReg(Result, dl,
4648 Node->getOperand(0).getValueType());
4649 // No extra round required here.
4650 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Result);
4653 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
4654 Node->getOperand(0), dl);
4655 // Round if we cannot tolerate excess precision.
4656 if (NoExcessFPPrecision)
4657 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4658 DAG.getValueType(VT));
4663 case ISD::SIGN_EXTEND_INREG:
4664 Result = PromoteOp(Node->getOperand(0));
4665 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Result,
4666 Node->getOperand(1));
4668 case ISD::FP_TO_SINT:
4669 case ISD::FP_TO_UINT:
4670 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4673 Tmp1 = Node->getOperand(0);
4676 // The input result is prerounded, so we don't have to do anything
4678 Tmp1 = PromoteOp(Node->getOperand(0));
4681 // If we're promoting a UINT to a larger size, check to see if the new node
4682 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
4683 // we can use that instead. This allows us to generate better code for
4684 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
4685 // legal, such as PowerPC.
4686 if (Node->getOpcode() == ISD::FP_TO_UINT &&
4687 !TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NVT) &&
4688 (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT) ||
4689 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
4690 Result = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Tmp1);
4692 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4698 Tmp1 = PromoteOp(Node->getOperand(0));
4699 assert(Tmp1.getValueType() == NVT);
4700 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4701 // NOTE: we do not have to do any extra rounding here for
4702 // NoExcessFPPrecision, because we know the input will have the appropriate
4703 // precision, and these operations don't modify precision at all.
4718 case ISD::FNEARBYINT:
4719 Tmp1 = PromoteOp(Node->getOperand(0));
4720 assert(Tmp1.getValueType() == NVT);
4721 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4722 if (NoExcessFPPrecision)
4723 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4724 DAG.getValueType(VT));
4729 // Promote f32 pow(i) to f64 pow(i). Note that this could insert a libcall
4730 // directly as well, which may be better.
4731 Tmp1 = PromoteOp(Node->getOperand(0));
4732 Tmp2 = Node->getOperand(1);
4733 if (Node->getOpcode() == ISD::FPOW)
4734 Tmp2 = PromoteOp(Tmp2);
4735 assert(Tmp1.getValueType() == NVT);
4736 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4737 if (NoExcessFPPrecision)
4738 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4739 DAG.getValueType(VT));
4743 case ISD::ATOMIC_CMP_SWAP: {
4744 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4745 Tmp2 = PromoteOp(Node->getOperand(2));
4746 Tmp3 = PromoteOp(Node->getOperand(3));
4747 Result = DAG.getAtomic(Node->getOpcode(), dl, AtomNode->getMemoryVT(),
4748 AtomNode->getChain(),
4749 AtomNode->getBasePtr(), Tmp2, Tmp3,
4750 AtomNode->getSrcValue(),
4751 AtomNode->getAlignment());
4752 // Remember that we legalized the chain.
4753 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4756 case ISD::ATOMIC_LOAD_ADD:
4757 case ISD::ATOMIC_LOAD_SUB:
4758 case ISD::ATOMIC_LOAD_AND:
4759 case ISD::ATOMIC_LOAD_OR:
4760 case ISD::ATOMIC_LOAD_XOR:
4761 case ISD::ATOMIC_LOAD_NAND:
4762 case ISD::ATOMIC_LOAD_MIN:
4763 case ISD::ATOMIC_LOAD_MAX:
4764 case ISD::ATOMIC_LOAD_UMIN:
4765 case ISD::ATOMIC_LOAD_UMAX:
4766 case ISD::ATOMIC_SWAP: {
4767 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4768 Tmp2 = PromoteOp(Node->getOperand(2));
4769 Result = DAG.getAtomic(Node->getOpcode(), dl, AtomNode->getMemoryVT(),
4770 AtomNode->getChain(),
4771 AtomNode->getBasePtr(), Tmp2,
4772 AtomNode->getSrcValue(),
4773 AtomNode->getAlignment());
4774 // Remember that we legalized the chain.
4775 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4785 // The input may have strange things in the top bits of the registers, but
4786 // these operations don't care. They may have weird bits going out, but
4787 // that too is okay if they are integer operations.
4788 Tmp1 = PromoteOp(Node->getOperand(0));
4789 Tmp2 = PromoteOp(Node->getOperand(1));
4790 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4791 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4796 Tmp1 = PromoteOp(Node->getOperand(0));
4797 Tmp2 = PromoteOp(Node->getOperand(1));
4798 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4799 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4801 // Floating point operations will give excess precision that we may not be
4802 // able to tolerate. If we DO allow excess precision, just leave it,
4803 // otherwise excise it.
4804 // FIXME: Why would we need to round FP ops more than integer ones?
4805 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
4806 if (NoExcessFPPrecision)
4807 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4808 DAG.getValueType(VT));
4813 // These operators require that their input be sign extended.
4814 Tmp1 = PromoteOp(Node->getOperand(0));
4815 Tmp2 = PromoteOp(Node->getOperand(1));
4816 if (NVT.isInteger()) {
4817 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp1,
4818 DAG.getValueType(VT));
4819 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp2,
4820 DAG.getValueType(VT));
4822 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4824 // Perform FP_ROUND: this is probably overly pessimistic.
4825 if (NVT.isFloatingPoint() && NoExcessFPPrecision)
4826 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4827 DAG.getValueType(VT));
4831 case ISD::FCOPYSIGN:
4832 // These operators require that their input be fp extended.
4833 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4834 case Expand: assert(0 && "not implemented");
4835 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break;
4836 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break;
4838 switch (getTypeAction(Node->getOperand(1).getValueType())) {
4839 case Expand: assert(0 && "not implemented");
4840 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
4841 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
4843 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4845 // Perform FP_ROUND: this is probably overly pessimistic.
4846 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
4847 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4848 DAG.getValueType(VT));
4853 // These operators require that their input be zero extended.
4854 Tmp1 = PromoteOp(Node->getOperand(0));
4855 Tmp2 = PromoteOp(Node->getOperand(1));
4856 assert(NVT.isInteger() && "Operators don't apply to FP!");
4857 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, VT);
4858 Tmp2 = DAG.getZeroExtendInReg(Tmp2, dl, VT);
4859 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4863 Tmp1 = PromoteOp(Node->getOperand(0));
4864 Result = DAG.getNode(ISD::SHL, dl, NVT, Tmp1, Node->getOperand(1));
4867 // The input value must be properly sign extended.
4868 Tmp1 = PromoteOp(Node->getOperand(0));
4869 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp1,
4870 DAG.getValueType(VT));
4871 Result = DAG.getNode(ISD::SRA, dl, NVT, Tmp1, Node->getOperand(1));
4874 // The input value must be properly zero extended.
4875 Tmp1 = PromoteOp(Node->getOperand(0));
4876 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, VT);
4877 Result = DAG.getNode(ISD::SRL, dl, NVT, Tmp1, Node->getOperand(1));
4881 Tmp1 = Node->getOperand(0); // Get the chain.
4882 Tmp2 = Node->getOperand(1); // Get the pointer.
4883 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
4884 Tmp3 = DAG.getVAArg(VT, dl, Tmp1, Tmp2, Node->getOperand(2));
4885 Result = TLI.LowerOperation(Tmp3, DAG);
4887 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
4888 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0);
4889 // Increment the pointer, VAList, to the next vaarg
4890 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
4891 DAG.getConstant(VT.getSizeInBits()/8,
4892 TLI.getPointerTy()));
4893 // Store the incremented VAList to the legalized pointer
4894 Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0);
4895 // Load the actual argument out of the pointer VAList
4896 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, NVT, Tmp3, VAList, NULL, 0, VT);
4898 // Remember that we legalized the chain.
4899 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4903 LoadSDNode *LD = cast<LoadSDNode>(Node);
4904 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
4905 ? ISD::EXTLOAD : LD->getExtensionType();
4906 Result = DAG.getExtLoad(ExtType, dl, NVT,
4907 LD->getChain(), LD->getBasePtr(),
4908 LD->getSrcValue(), LD->getSrcValueOffset(),
4911 LD->getAlignment());
4912 // Remember that we legalized the chain.
4913 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4917 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
4918 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
4920 MVT VT2 = Tmp2.getValueType();
4921 assert(VT2 == Tmp3.getValueType()
4922 && "PromoteOp SELECT: Operands 2 and 3 ValueTypes don't match");
4923 // Ensure that the resulting node is at least the same size as the operands'
4924 // value types, because we cannot assume that TLI.getSetCCValueType() is
4926 Result = DAG.getNode(ISD::SELECT, dl, VT2, Node->getOperand(0), Tmp2, Tmp3);
4929 case ISD::SELECT_CC:
4930 Tmp2 = PromoteOp(Node->getOperand(2)); // True
4931 Tmp3 = PromoteOp(Node->getOperand(3)); // False
4932 Result = DAG.getNode(ISD::SELECT_CC, dl, NVT, Node->getOperand(0),
4933 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
4936 Tmp1 = Node->getOperand(0);
4937 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1);
4938 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
4939 Result = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
4940 DAG.getConstant(NVT.getSizeInBits() -
4942 TLI.getShiftAmountTy()));
4947 // Zero extend the argument
4948 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4949 // Perform the larger operation, then subtract if needed.
4950 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4951 switch(Node->getOpcode()) {
4956 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
4957 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()), Tmp1,
4958 DAG.getConstant(NVT.getSizeInBits(), NVT),
4960 Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
4961 DAG.getConstant(VT.getSizeInBits(), NVT), Tmp1);
4964 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4965 Result = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
4966 DAG.getConstant(NVT.getSizeInBits() -
4967 VT.getSizeInBits(), NVT));
4971 case ISD::EXTRACT_SUBVECTOR:
4972 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
4974 case ISD::EXTRACT_VECTOR_ELT:
4975 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
4979 assert(Result.getNode() && "Didn't set a result!");
4981 // Make sure the result is itself legal.
4982 Result = LegalizeOp(Result);
4984 // Remember that we promoted this!
4985 AddPromotedOperand(Op, Result);
4989 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
4990 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
4991 /// based on the vector type. The return type of this matches the element type
4992 /// of the vector, which may not be legal for the target.
4993 SDValue SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDValue Op) {
4994 // We know that operand #0 is the Vec vector. If the index is a constant
4995 // or if the invec is a supported hardware type, we can use it. Otherwise,
4996 // lower to a store then an indexed load.
4997 SDValue Vec = Op.getOperand(0);
4998 SDValue Idx = Op.getOperand(1);
4999 DebugLoc dl = Op.getDebugLoc();
5001 MVT TVT = Vec.getValueType();
5002 unsigned NumElems = TVT.getVectorNumElements();
5004 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
5005 default: assert(0 && "This action is not supported yet!");
5006 case TargetLowering::Custom: {
5007 Vec = LegalizeOp(Vec);
5008 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
5009 SDValue Tmp3 = TLI.LowerOperation(Op, DAG);
5014 case TargetLowering::Legal:
5015 if (isTypeLegal(TVT)) {
5016 Vec = LegalizeOp(Vec);
5017 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
5021 case TargetLowering::Promote:
5022 assert(TVT.isVector() && "not vector type");
5023 // fall thru to expand since vectors are by default are promote
5024 case TargetLowering::Expand:
5028 if (NumElems == 1) {
5029 // This must be an access of the only element. Return it.
5030 Op = ScalarizeVectorOp(Vec);
5031 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
5032 unsigned NumLoElts = 1 << Log2_32(NumElems-1);
5033 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
5035 SplitVectorOp(Vec, Lo, Hi);
5036 if (CIdx->getZExtValue() < NumLoElts) {
5040 Idx = DAG.getConstant(CIdx->getZExtValue() - NumLoElts,
5041 Idx.getValueType());
5044 // It's now an extract from the appropriate high or low part. Recurse.
5045 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
5046 Op = ExpandEXTRACT_VECTOR_ELT(Op);
5048 // Store the value to a temporary stack slot, then LOAD the scalar
5049 // element back out.
5050 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
5051 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0);
5053 // Add the offset to the index.
5054 unsigned EltSize = Op.getValueType().getSizeInBits()/8;
5055 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
5056 DAG.getConstant(EltSize, Idx.getValueType()));
5058 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
5059 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
5061 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
5063 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
5065 Op = DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, NULL, 0);
5070 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
5071 /// we assume the operation can be split if it is not already legal.
5072 SDValue SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDValue Op) {
5073 // We know that operand #0 is the Vec vector. For now we assume the index
5074 // is a constant and that the extracted result is a supported hardware type.
5075 SDValue Vec = Op.getOperand(0);
5076 SDValue Idx = LegalizeOp(Op.getOperand(1));
5078 unsigned NumElems = Vec.getValueType().getVectorNumElements();
5080 if (NumElems == Op.getValueType().getVectorNumElements()) {
5081 // This must be an access of the desired vector length. Return it.
5085 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
5087 SplitVectorOp(Vec, Lo, Hi);
5088 if (CIdx->getZExtValue() < NumElems/2) {
5092 Idx = DAG.getConstant(CIdx->getZExtValue() - NumElems/2,
5093 Idx.getValueType());
5096 // It's now an extract from the appropriate high or low part. Recurse.
5097 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
5098 return ExpandEXTRACT_SUBVECTOR(Op);
5101 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
5102 /// with condition CC on the current target. This usually involves legalizing
5103 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
5104 /// there may be no choice but to create a new SetCC node to represent the
5105 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
5106 /// LHS, and the SDValue returned in RHS has a nil SDNode value.
5107 void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS,
5111 SDValue Tmp1, Tmp2, Tmp3, Result;
5113 switch (getTypeAction(LHS.getValueType())) {
5115 Tmp1 = LegalizeOp(LHS); // LHS
5116 Tmp2 = LegalizeOp(RHS); // RHS
5119 Tmp1 = PromoteOp(LHS); // LHS
5120 Tmp2 = PromoteOp(RHS); // RHS
5122 // If this is an FP compare, the operands have already been extended.
5123 if (LHS.getValueType().isInteger()) {
5124 MVT VT = LHS.getValueType();
5125 MVT NVT = TLI.getTypeToTransformTo(VT);
5127 // Otherwise, we have to insert explicit sign or zero extends. Note
5128 // that we could insert sign extends for ALL conditions, but zero extend
5129 // is cheaper on many machines (an AND instead of two shifts), so prefer
5131 switch (cast<CondCodeSDNode>(CC)->get()) {
5132 default: assert(0 && "Unknown integer comparison!");
5139 // ALL of these operations will work if we either sign or zero extend
5140 // the operands (including the unsigned comparisons!). Zero extend is
5141 // usually a simpler/cheaper operation, so prefer it.
5142 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, VT);
5143 Tmp2 = DAG.getZeroExtendInReg(Tmp2, dl, VT);
5149 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp1,
5150 DAG.getValueType(VT));
5151 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp2,
5152 DAG.getValueType(VT));
5153 Tmp1 = LegalizeOp(Tmp1); // Relegalize new nodes.
5154 Tmp2 = LegalizeOp(Tmp2); // Relegalize new nodes.
5160 MVT VT = LHS.getValueType();
5161 if (VT == MVT::f32 || VT == MVT::f64) {
5162 // Expand into one or more soft-fp libcall(s).
5163 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
5164 switch (cast<CondCodeSDNode>(CC)->get()) {
5167 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
5171 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
5175 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
5179 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
5183 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
5187 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
5190 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
5193 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
5196 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
5197 switch (cast<CondCodeSDNode>(CC)->get()) {
5199 // SETONE = SETOLT | SETOGT
5200 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
5203 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
5206 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
5209 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
5212 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
5215 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
5217 default: assert(0 && "Unsupported FP setcc!");
5222 SDValue Ops[2] = { LHS, RHS };
5223 Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2, dl).getNode(),
5224 false /*sign irrelevant*/, Dummy);
5225 Tmp2 = DAG.getConstant(0, MVT::i32);
5226 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
5227 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
5228 Tmp1 = DAG.getNode(ISD::SETCC, dl,
5229 TLI.getSetCCResultType(Tmp1.getValueType()),
5231 LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2, dl).getNode(),
5232 false /*sign irrelevant*/, Dummy);
5233 Tmp2 = DAG.getNode(ISD::SETCC, dl,
5234 TLI.getSetCCResultType(LHS.getValueType()), LHS,
5235 Tmp2, DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
5236 Tmp1 = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp2);
5239 LHS = LegalizeOp(Tmp1);
5244 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
5245 ExpandOp(LHS, LHSLo, LHSHi);
5246 ExpandOp(RHS, RHSLo, RHSHi);
5247 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
5249 if (VT==MVT::ppcf128) {
5250 // FIXME: This generated code sucks. We want to generate
5251 // FCMPU crN, hi1, hi2
5253 // FCMPU crN, lo1, lo2
5254 // The following can be improved, but not that much.
5255 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
5256 LHSHi, RHSHi, ISD::SETOEQ);
5257 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()),
5258 LHSLo, RHSLo, CCCode);
5259 Tmp3 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2);
5260 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
5261 LHSHi, RHSHi, ISD::SETUNE);
5262 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
5263 LHSHi, RHSHi, CCCode);
5264 Tmp1 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2);
5265 Tmp1 = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp3);
5274 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
5275 if (RHSCST->isAllOnesValue()) {
5276 // Comparison to -1.
5277 Tmp1 = DAG.getNode(ISD::AND, dl,LHSLo.getValueType(), LHSLo, LHSHi);
5282 Tmp1 = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
5283 Tmp2 = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
5284 Tmp1 = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp2);
5285 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
5288 // If this is a comparison of the sign bit, just look at the top part.
5290 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
5291 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
5292 CST->isNullValue()) || // X < 0
5293 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
5294 CST->isAllOnesValue())) { // X > -1
5300 // FIXME: This generated code sucks.
5301 ISD::CondCode LowCC;
5303 default: assert(0 && "Unknown integer setcc!");
5305 case ISD::SETULT: LowCC = ISD::SETULT; break;
5307 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
5309 case ISD::SETULE: LowCC = ISD::SETULE; break;
5311 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
5314 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
5315 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
5316 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
5318 // NOTE: on targets without efficient SELECT of bools, we can always use
5319 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
5320 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
5321 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
5322 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
5323 if (!Tmp1.getNode())
5324 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()),
5325 LHSLo, RHSLo, LowCC);
5326 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
5327 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
5328 if (!Tmp2.getNode())
5329 Tmp2 = DAG.getNode(ISD::SETCC, dl,
5330 TLI.getSetCCResultType(LHSHi.getValueType()),
5333 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
5334 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
5335 if ((Tmp1C && Tmp1C->isNullValue()) ||
5336 (Tmp2C && Tmp2C->isNullValue() &&
5337 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
5338 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
5339 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
5340 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
5341 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
5342 // low part is known false, returns high part.
5343 // For LE / GE, if high part is known false, ignore the low part.
5344 // For LT / GT, if high part is known true, ignore the low part.
5348 Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
5349 LHSHi, RHSHi, ISD::SETEQ, false,
5350 DagCombineInfo, dl);
5351 if (!Result.getNode())
5352 Result=DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
5353 LHSHi, RHSHi, ISD::SETEQ);
5354 Result = LegalizeOp(DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(),
5355 Result, Tmp1, Tmp2));
5366 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
5367 /// condition code CC on the current target. This routine assumes LHS and rHS
5368 /// have already been legalized by LegalizeSetCCOperands. It expands SETCC with
5369 /// illegal condition code into AND / OR of multiple SETCC values.
5370 void SelectionDAGLegalize::LegalizeSetCCCondCode(MVT VT,
5371 SDValue &LHS, SDValue &RHS,
5374 MVT OpVT = LHS.getValueType();
5375 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
5376 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
5377 default: assert(0 && "Unknown condition code action!");
5378 case TargetLowering::Legal:
5381 case TargetLowering::Expand: {
5382 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
5385 default: assert(0 && "Don't know how to expand this condition!"); abort();
5386 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break;
5387 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break;
5388 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5389 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break;
5390 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5391 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5392 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5393 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5394 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5395 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5396 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5397 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5398 // FIXME: Implement more expansions.
5401 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
5402 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
5403 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
5411 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
5412 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
5413 /// a load from the stack slot to DestVT, extending it if needed.
5414 /// The resultant code need not be legal.
5415 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
5419 // Create the stack frame object.
5421 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType().
5423 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
5425 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
5426 int SPFI = StackPtrFI->getIndex();
5427 const Value *SV = PseudoSourceValue::getFixedStack(SPFI);
5429 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
5430 unsigned SlotSize = SlotVT.getSizeInBits();
5431 unsigned DestSize = DestVT.getSizeInBits();
5432 unsigned DestAlign =
5433 TLI.getTargetData()->getPrefTypeAlignment(DestVT.getTypeForMVT());
5435 // Emit a store to the stack slot. Use a truncstore if the input value is
5436 // later than DestVT.
5439 if (SrcSize > SlotSize)
5440 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
5441 SV, 0, SlotVT, false, SrcAlign);
5443 assert(SrcSize == SlotSize && "Invalid store");
5444 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
5445 SV, 0, false, SrcAlign);
5448 // Result is a load from the stack slot.
5449 if (SlotSize == DestSize)
5450 return DAG.getLoad(DestVT, dl, Store, FIPtr, SV, 0, false, DestAlign);
5452 assert(SlotSize < DestSize && "Unknown extension!");
5453 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, SV, 0, SlotVT,
5457 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
5458 DebugLoc dl = Node->getDebugLoc();
5459 // Create a vector sized/aligned stack slot, store the value to element #0,
5460 // then load the whole vector back out.
5461 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
5463 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
5464 int SPFI = StackPtrFI->getIndex();
5466 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0),
5468 PseudoSourceValue::getFixedStack(SPFI), 0,
5469 Node->getValueType(0).getVectorElementType());
5470 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
5471 PseudoSourceValue::getFixedStack(SPFI), 0);
5475 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
5476 /// support the operation, but do support the resultant vector type.
5477 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
5478 unsigned NumElems = Node->getNumOperands();
5479 SDValue SplatValue = Node->getOperand(0);
5480 DebugLoc dl = Node->getDebugLoc();
5481 MVT VT = Node->getValueType(0);
5482 MVT OpVT = SplatValue.getValueType();
5483 MVT EltVT = VT.getVectorElementType();
5485 // If the only non-undef value is the low element, turn this into a
5486 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
5487 bool isOnlyLowElement = true;
5489 // FIXME: it would be far nicer to change this into map<SDValue,uint64_t>
5490 // and use a bitmask instead of a list of elements.
5491 // FIXME: this doesn't treat <0, u, 0, u> for example, as a splat.
5492 std::map<SDValue, std::vector<unsigned> > Values;
5493 Values[SplatValue].push_back(0);
5494 bool isConstant = true;
5495 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
5496 SplatValue.getOpcode() != ISD::UNDEF)
5499 for (unsigned i = 1; i < NumElems; ++i) {
5500 SDValue V = Node->getOperand(i);
5501 Values[V].push_back(i);
5502 if (V.getOpcode() != ISD::UNDEF)
5503 isOnlyLowElement = false;
5504 if (SplatValue != V)
5505 SplatValue = SDValue(0, 0);
5507 // If this isn't a constant element or an undef, we can't use a constant
5509 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
5510 V.getOpcode() != ISD::UNDEF)
5514 if (isOnlyLowElement) {
5515 // If the low element is an undef too, then this whole things is an undef.
5516 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
5517 return DAG.getUNDEF(VT);
5518 // Otherwise, turn this into a scalar_to_vector node.
5519 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
5522 // If all elements are constants, create a load from the constant pool.
5524 std::vector<Constant*> CV;
5525 for (unsigned i = 0, e = NumElems; i != e; ++i) {
5526 if (ConstantFPSDNode *V =
5527 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
5528 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
5529 } else if (ConstantSDNode *V =
5530 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
5531 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
5533 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
5534 const Type *OpNTy = OpVT.getTypeForMVT();
5535 CV.push_back(UndefValue::get(OpNTy));
5538 Constant *CP = ConstantVector::get(CV);
5539 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
5540 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5541 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5542 PseudoSourceValue::getConstantPool(), 0,
5546 if (SplatValue.getNode()) { // Splat of one value?
5547 // Build the shuffle constant vector: <0, 0, 0, 0>
5548 SmallVector<int, 8> ZeroVec(NumElems, 0);
5550 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
5551 if (TLI.isShuffleMaskLegal(ZeroVec, Node->getValueType(0))) {
5552 // Get the splatted value into the low element of a vector register.
5554 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, SplatValue);
5556 // Return shuffle(LowValVec, undef, <0,0,0,0>)
5557 return DAG.getVectorShuffle(VT, dl, LowValVec, DAG.getUNDEF(VT),
5562 // If there are only two unique elements, we may be able to turn this into a
5564 if (Values.size() == 2) {
5565 // Get the two values in deterministic order.
5566 SDValue Val1 = Node->getOperand(1);
5568 std::map<SDValue, std::vector<unsigned> >::iterator MI = Values.begin();
5569 if (MI->first != Val1)
5572 Val2 = (++MI)->first;
5574 // If Val1 is an undef, make sure it ends up as Val2, to ensure that our
5575 // vector shuffle has the undef vector on the RHS.
5576 if (Val1.getOpcode() == ISD::UNDEF)
5577 std::swap(Val1, Val2);
5579 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
5580 SmallVector<int, 8> ShuffleMask(NumElems, -1);
5582 // Set elements of the shuffle mask for Val1.
5583 std::vector<unsigned> &Val1Elts = Values[Val1];
5584 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i)
5585 ShuffleMask[Val1Elts[i]] = 0;
5587 // Set elements of the shuffle mask for Val2.
5588 std::vector<unsigned> &Val2Elts = Values[Val2];
5589 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i)
5590 if (Val2.getOpcode() != ISD::UNDEF)
5591 ShuffleMask[Val2Elts[i]] = NumElems;
5593 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it.
5594 if (TLI.isOperationLegalOrCustom(ISD::SCALAR_TO_VECTOR, VT) &&
5595 TLI.isShuffleMaskLegal(ShuffleMask, VT)) {
5596 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Val1);
5597 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Val2);
5598 return DAG.getVectorShuffle(VT, dl, Val1, Val2, &ShuffleMask[0]);
5602 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
5603 // aligned object on the stack, store each element into it, then load
5604 // the result as a vector.
5605 // Create the stack frame object.
5606 SDValue FIPtr = DAG.CreateStackTemporary(VT);
5607 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
5608 const Value *SV = PseudoSourceValue::getFixedStack(FI);
5610 // Emit a store of each element to the stack slot.
5611 SmallVector<SDValue, 8> Stores;
5612 unsigned TypeByteSize = OpVT.getSizeInBits() / 8;
5613 // Store (in the right endianness) the elements to memory.
5614 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5615 // Ignore undef elements.
5616 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
5618 unsigned Offset = TypeByteSize*i;
5620 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
5621 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
5623 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(i),
5628 if (!Stores.empty()) // Not all undef elements?
5629 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
5630 &Stores[0], Stores.size());
5632 StoreChain = DAG.getEntryNode();
5634 // Result is a load from the stack slot.
5635 return DAG.getLoad(VT, dl, StoreChain, FIPtr, SV, 0);
5638 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
5639 SDValue Op, SDValue Amt,
5640 SDValue &Lo, SDValue &Hi,
5642 // Expand the subcomponents.
5644 ExpandOp(Op, LHSL, LHSH);
5646 SDValue Ops[] = { LHSL, LHSH, Amt };
5647 MVT VT = LHSL.getValueType();
5648 Lo = DAG.getNode(NodeOp, dl, DAG.getVTList(VT, VT), Ops, 3);
5649 Hi = Lo.getValue(1);
5653 /// ExpandShift - Try to find a clever way to expand this shift operation out to
5654 /// smaller elements. If we can't find a way that is more efficient than a
5655 /// libcall on this target, return false. Otherwise, return true with the
5656 /// low-parts expanded into Lo and Hi.
5657 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op, SDValue Amt,
5658 SDValue &Lo, SDValue &Hi,
5660 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
5661 "This is not a shift!");
5663 MVT NVT = TLI.getTypeToTransformTo(Op.getValueType());
5664 SDValue ShAmt = LegalizeOp(Amt);
5665 MVT ShTy = ShAmt.getValueType();
5666 unsigned ShBits = ShTy.getSizeInBits();
5667 unsigned VTBits = Op.getValueType().getSizeInBits();
5668 unsigned NVTBits = NVT.getSizeInBits();
5670 // Handle the case when Amt is an immediate.
5671 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.getNode())) {
5672 unsigned Cst = CN->getZExtValue();
5673 // Expand the incoming operand to be shifted, so that we have its parts
5675 ExpandOp(Op, InL, InH);
5679 Lo = DAG.getConstant(0, NVT);
5680 Hi = DAG.getConstant(0, NVT);
5681 } else if (Cst > NVTBits) {
5682 Lo = DAG.getConstant(0, NVT);
5683 Hi = DAG.getNode(ISD::SHL, dl,
5684 NVT, InL, DAG.getConstant(Cst-NVTBits, ShTy));
5685 } else if (Cst == NVTBits) {
5686 Lo = DAG.getConstant(0, NVT);
5689 Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, DAG.getConstant(Cst, ShTy));
5690 Hi = DAG.getNode(ISD::OR, dl, NVT,
5691 DAG.getNode(ISD::SHL, dl, NVT, InH, DAG.getConstant(Cst, ShTy)),
5692 DAG.getNode(ISD::SRL, dl, NVT, InL,
5693 DAG.getConstant(NVTBits-Cst, ShTy)));
5698 Lo = DAG.getConstant(0, NVT);
5699 Hi = DAG.getConstant(0, NVT);
5700 } else if (Cst > NVTBits) {
5701 Lo = DAG.getNode(ISD::SRL, dl, NVT,
5702 InH, DAG.getConstant(Cst-NVTBits, ShTy));
5703 Hi = DAG.getConstant(0, NVT);
5704 } else if (Cst == NVTBits) {
5706 Hi = DAG.getConstant(0, NVT);
5708 Lo = DAG.getNode(ISD::OR, dl, NVT,
5709 DAG.getNode(ISD::SRL, dl, NVT, InL, DAG.getConstant(Cst, ShTy)),
5710 DAG.getNode(ISD::SHL, dl, NVT, InH,
5711 DAG.getConstant(NVTBits-Cst, ShTy)));
5712 Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, DAG.getConstant(Cst, ShTy));
5717 Hi = Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
5718 DAG.getConstant(NVTBits-1, ShTy));
5719 } else if (Cst > NVTBits) {
5720 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
5721 DAG.getConstant(Cst-NVTBits, ShTy));
5722 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
5723 DAG.getConstant(NVTBits-1, ShTy));
5724 } else if (Cst == NVTBits) {
5726 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
5727 DAG.getConstant(NVTBits-1, ShTy));
5729 Lo = DAG.getNode(ISD::OR, dl, NVT,
5730 DAG.getNode(ISD::SRL, dl, NVT, InL, DAG.getConstant(Cst, ShTy)),
5731 DAG.getNode(ISD::SHL, dl,
5732 NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5733 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(Cst, ShTy));
5739 // Okay, the shift amount isn't constant. However, if we can tell that it is
5740 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
5741 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
5742 APInt KnownZero, KnownOne;
5743 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
5745 // If we know that if any of the high bits of the shift amount are one, then
5746 // we can do this as a couple of simple shifts.
5747 if (KnownOne.intersects(Mask)) {
5748 // Mask out the high bit, which we know is set.
5749 Amt = DAG.getNode(ISD::AND, dl, Amt.getValueType(), Amt,
5750 DAG.getConstant(~Mask, Amt.getValueType()));
5752 // Expand the incoming operand to be shifted, so that we have its parts
5754 ExpandOp(Op, InL, InH);
5757 Lo = DAG.getConstant(0, NVT); // Low part is zero.
5758 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
5761 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
5762 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
5765 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
5766 DAG.getConstant(NVTBits-1, Amt.getValueType()));
5767 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
5772 // If we know that the high bits of the shift amount are all zero, then we can
5773 // do this as a couple of simple shifts.
5774 if ((KnownZero & Mask) == Mask) {
5776 SDValue Amt2 = DAG.getNode(ISD::SUB, dl, Amt.getValueType(),
5777 DAG.getConstant(NVTBits, Amt.getValueType()),
5780 // Expand the incoming operand to be shifted, so that we have its parts
5782 ExpandOp(Op, InL, InH);
5785 Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
5786 Hi = DAG.getNode(ISD::OR, dl, NVT,
5787 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
5788 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt2));
5791 Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
5792 Lo = DAG.getNode(ISD::OR, dl, NVT,
5793 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
5794 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt2));
5797 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
5798 Lo = DAG.getNode(ISD::OR, dl, NVT,
5799 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
5800 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt2));
5809 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
5810 // does not fit into a register, return the lo part and set the hi part to the
5811 // by-reg argument. If it does fit into a single register, return the result
5812 // and leave the Hi part unset.
5813 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
5814 bool isSigned, SDValue &Hi) {
5815 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
5816 // The input chain to this libcall is the entry node of the function.
5817 // Legalizing the call will automatically add the previous call to the
5819 SDValue InChain = DAG.getEntryNode();
5821 TargetLowering::ArgListTy Args;
5822 TargetLowering::ArgListEntry Entry;
5823 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5824 MVT ArgVT = Node->getOperand(i).getValueType();
5825 const Type *ArgTy = ArgVT.getTypeForMVT();
5826 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
5827 Entry.isSExt = isSigned;
5828 Entry.isZExt = !isSigned;
5829 Args.push_back(Entry);
5831 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
5832 TLI.getPointerTy());
5834 // Splice the libcall in wherever FindInputOutputChains tells us to.
5835 const Type *RetTy = Node->getValueType(0).getTypeForMVT();
5836 std::pair<SDValue, SDValue> CallInfo =
5837 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
5838 CallingConv::C, false, Callee, Args, DAG,
5839 Node->getDebugLoc());
5841 // Legalize the call sequence, starting with the chain. This will advance
5842 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
5843 // was added by LowerCallTo (guaranteeing proper serialization of calls).
5844 LegalizeOp(CallInfo.second);
5846 switch (getTypeAction(CallInfo.first.getValueType())) {
5847 default: assert(0 && "Unknown thing");
5849 Result = CallInfo.first;
5852 ExpandOp(CallInfo.first, Result, Hi);
5858 /// LegalizeINT_TO_FP - Legalize a [US]INT_TO_FP operation.
5860 SDValue SelectionDAGLegalize::
5861 LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op,
5863 bool isCustom = false;
5865 switch (getTypeAction(Op.getValueType())) {
5867 switch (TLI.getOperationAction(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5868 Op.getValueType())) {
5869 default: assert(0 && "Unknown operation action!");
5870 case TargetLowering::Custom:
5873 case TargetLowering::Legal:
5874 Tmp1 = LegalizeOp(Op);
5875 if (Result.getNode())
5876 Result = DAG.UpdateNodeOperands(Result, Tmp1);
5878 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, dl,
5881 Tmp1 = TLI.LowerOperation(Result, DAG);
5882 if (Tmp1.getNode()) Result = Tmp1;
5885 case TargetLowering::Expand:
5886 Result = ExpandLegalINT_TO_FP(isSigned, LegalizeOp(Op), DestTy, dl);
5888 case TargetLowering::Promote:
5889 Result = PromoteLegalINT_TO_FP(LegalizeOp(Op), DestTy, isSigned, dl);
5894 Result = ExpandIntToFP(isSigned, DestTy, Op, dl) ;
5897 Tmp1 = PromoteOp(Op);
5899 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Tmp1.getValueType(),
5900 Tmp1, DAG.getValueType(Op.getValueType()));
5902 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, Op.getValueType());
5904 if (Result.getNode())
5905 Result = DAG.UpdateNodeOperands(Result, Tmp1);
5907 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, dl,
5909 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
5915 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
5917 SDValue SelectionDAGLegalize::
5918 ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source, DebugLoc dl) {
5919 MVT SourceVT = Source.getValueType();
5920 bool ExpandSource = getTypeAction(SourceVT) == Expand;
5922 // Expand unsupported int-to-fp vector casts by unrolling them.
5923 if (DestTy.isVector()) {
5925 return LegalizeOp(UnrollVectorOp(Source));
5926 MVT DestEltTy = DestTy.getVectorElementType();
5927 if (DestTy.getVectorNumElements() == 1) {
5928 SDValue Scalar = ScalarizeVectorOp(Source);
5929 SDValue Result = LegalizeINT_TO_FP(SDValue(), isSigned,
5930 DestEltTy, Scalar, dl);
5931 return DAG.getNode(ISD::BUILD_VECTOR, dl, DestTy, Result);
5934 SplitVectorOp(Source, Lo, Hi);
5935 MVT SplitDestTy = MVT::getVectorVT(DestEltTy,
5936 DestTy.getVectorNumElements() / 2);
5937 SDValue LoResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy,
5939 SDValue HiResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy,
5941 return LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, dl, DestTy, LoResult,
5945 // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc.
5946 if (!isSigned && SourceVT != MVT::i32) {
5947 // The integer value loaded will be incorrectly if the 'sign bit' of the
5948 // incoming integer is set. To handle this, we dynamically test to see if
5949 // it is set, and, if so, add a fudge factor.
5953 ExpandOp(Source, Lo, Hi);
5954 Source = DAG.getNode(ISD::BUILD_PAIR, dl, SourceVT, Lo, Hi);
5956 // The comparison for the sign bit will use the entire operand.
5960 // Check to see if the target has a custom way to lower this. If so, use
5961 // it. (Note we've already expanded the operand in this case.)
5962 switch (TLI.getOperationAction(ISD::UINT_TO_FP, SourceVT)) {
5963 default: assert(0 && "This action not implemented for this operation!");
5964 case TargetLowering::Legal:
5965 case TargetLowering::Expand:
5966 break; // This case is handled below.
5967 case TargetLowering::Custom: {
5968 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::UINT_TO_FP, dl, DestTy,
5971 return LegalizeOp(NV);
5972 break; // The target decided this was legal after all
5976 // If this is unsigned, and not supported, first perform the conversion to
5977 // signed, then adjust the result if the sign bit is set.
5978 SDValue SignedConv = ExpandIntToFP(true, DestTy, Source, dl);
5980 SDValue SignSet = DAG.getSetCC(dl,
5981 TLI.getSetCCResultType(Hi.getValueType()),
5982 Hi, DAG.getConstant(0, Hi.getValueType()),
5984 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5985 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
5986 SignSet, Four, Zero);
5987 uint64_t FF = 0x5f800000ULL;
5988 if (TLI.isLittleEndian()) FF <<= 32;
5989 Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5991 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5992 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5993 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
5994 Alignment = std::min(Alignment, 4u);
5996 if (DestTy == MVT::f32)
5997 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
5998 PseudoSourceValue::getConstantPool(), 0,
6000 else if (DestTy.bitsGT(MVT::f32))
6001 // FIXME: Avoid the extend by construction the right constantpool?
6002 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, dl, DestTy, DAG.getEntryNode(),
6004 PseudoSourceValue::getConstantPool(), 0,
6005 MVT::f32, false, Alignment);
6007 assert(0 && "Unexpected conversion");
6009 MVT SCVT = SignedConv.getValueType();
6010 if (SCVT != DestTy) {
6011 // Destination type needs to be expanded as well. The FADD now we are
6012 // constructing will be expanded into a libcall.
6013 if (SCVT.getSizeInBits() != DestTy.getSizeInBits()) {
6014 assert(SCVT.getSizeInBits() * 2 == DestTy.getSizeInBits());
6015 SignedConv = DAG.getNode(ISD::BUILD_PAIR, dl, DestTy,
6016 SignedConv, SignedConv.getValue(1));
6018 SignedConv = DAG.getNode(ISD::BIT_CONVERT, dl, DestTy, SignedConv);
6020 return DAG.getNode(ISD::FADD, dl, DestTy, SignedConv, FudgeInReg);
6023 // Check to see if the target has a custom way to lower this. If so, use it.
6024 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) {
6025 default: assert(0 && "This action not implemented for this operation!");
6026 case TargetLowering::Legal:
6027 case TargetLowering::Expand:
6028 break; // This case is handled below.
6029 case TargetLowering::Custom: {
6030 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, dl, DestTy,
6033 return LegalizeOp(NV);
6034 break; // The target decided this was legal after all
6038 // Expand the source, then glue it back together for the call. We must expand
6039 // the source in case it is shared (this pass of legalize must traverse it).
6041 SDValue SrcLo, SrcHi;
6042 ExpandOp(Source, SrcLo, SrcHi);
6043 Source = DAG.getNode(ISD::BUILD_PAIR, dl, SourceVT, SrcLo, SrcHi);
6046 RTLIB::Libcall LC = isSigned ?
6047 RTLIB::getSINTTOFP(SourceVT, DestTy) :
6048 RTLIB::getUINTTOFP(SourceVT, DestTy);
6049 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unknown int value type");
6051 Source = DAG.getNode(ISD::SINT_TO_FP, dl, DestTy, Source);
6053 SDValue Result = ExpandLibCall(LC, Source.getNode(), isSigned, HiPart);
6054 if (Result.getValueType() != DestTy && HiPart.getNode())
6055 Result = DAG.getNode(ISD::BUILD_PAIR, dl, DestTy, Result, HiPart);
6059 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
6060 /// INT_TO_FP operation of the specified operand when the target requests that
6061 /// we expand it. At this point, we know that the result and operand types are
6062 /// legal for the target.
6063 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
6067 if (Op0.getValueType() == MVT::i32) {
6068 // simple 32-bit [signed|unsigned] integer to float/double expansion
6070 // Get the stack frame index of a 8 byte buffer.
6071 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
6073 // word offset constant for Hi/Lo address computation
6074 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
6075 // set up Hi and Lo (into buffer) address based on endian
6076 SDValue Hi = StackSlot;
6077 SDValue Lo = DAG.getNode(ISD::ADD, dl,
6078 TLI.getPointerTy(), StackSlot, WordOff);
6079 if (TLI.isLittleEndian())
6082 // if signed map to unsigned space
6085 // constant used to invert sign bit (signed to unsigned mapping)
6086 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
6087 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
6091 // store the lo of the constructed double - based on integer input
6092 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
6093 Op0Mapped, Lo, NULL, 0);
6094 // initial hi portion of constructed double
6095 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
6096 // store the hi of the constructed double - biased exponent
6097 SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0);
6098 // load the constructed double
6099 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0);
6100 // FP constant to bias correct the final result
6101 SDValue Bias = DAG.getConstantFP(isSigned ?
6102 BitsToDouble(0x4330000080000000ULL) :
6103 BitsToDouble(0x4330000000000000ULL),
6105 // subtract the bias
6106 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
6109 // handle final rounding
6110 if (DestVT == MVT::f64) {
6113 } else if (DestVT.bitsLT(MVT::f64)) {
6114 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
6115 DAG.getIntPtrConstant(0));
6116 } else if (DestVT.bitsGT(MVT::f64)) {
6117 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
6121 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
6122 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
6124 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()),
6125 Op0, DAG.getConstant(0, Op0.getValueType()),
6127 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
6128 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
6129 SignSet, Four, Zero);
6131 // If the sign bit of the integer is set, the large number will be treated
6132 // as a negative number. To counteract this, the dynamic code adds an
6133 // offset depending on the data type.
6135 switch (Op0.getValueType().getSimpleVT()) {
6136 default: assert(0 && "Unsupported integer type!");
6137 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
6138 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
6139 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
6140 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
6142 if (TLI.isLittleEndian()) FF <<= 32;
6143 Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
6145 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
6146 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
6147 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
6148 Alignment = std::min(Alignment, 4u);
6150 if (DestVT == MVT::f32)
6151 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
6152 PseudoSourceValue::getConstantPool(), 0,
6156 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
6157 DAG.getEntryNode(), CPIdx,
6158 PseudoSourceValue::getConstantPool(), 0,
6159 MVT::f32, false, Alignment));
6162 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
6165 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
6166 /// *INT_TO_FP operation of the specified operand when the target requests that
6167 /// we promote it. At this point, we know that the result and operand types are
6168 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
6169 /// operation that takes a larger input.
6170 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
6174 // First step, figure out the appropriate *INT_TO_FP operation to use.
6175 MVT NewInTy = LegalOp.getValueType();
6177 unsigned OpToUse = 0;
6179 // Scan for the appropriate larger type to use.
6181 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
6182 assert(NewInTy.isInteger() && "Ran out of possibilities!");
6184 // If the target supports SINT_TO_FP of this type, use it.
6185 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
6187 case TargetLowering::Legal:
6188 if (!TLI.isTypeLegal(NewInTy))
6189 break; // Can't use this datatype.
6191 case TargetLowering::Custom:
6192 OpToUse = ISD::SINT_TO_FP;
6196 if (isSigned) continue;
6198 // If the target supports UINT_TO_FP of this type, use it.
6199 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
6201 case TargetLowering::Legal:
6202 if (!TLI.isTypeLegal(NewInTy))
6203 break; // Can't use this datatype.
6205 case TargetLowering::Custom:
6206 OpToUse = ISD::UINT_TO_FP;
6211 // Otherwise, try a larger type.
6214 // Okay, we found the operation and type to use. Zero extend our input to the
6215 // desired type then run the operation on it.
6216 return DAG.getNode(OpToUse, dl, DestVT,
6217 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
6218 dl, NewInTy, LegalOp));
6221 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
6222 /// FP_TO_*INT operation of the specified operand when the target requests that
6223 /// we promote it. At this point, we know that the result and operand types are
6224 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
6225 /// operation that returns a larger result.
6226 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
6230 // First step, figure out the appropriate FP_TO*INT operation to use.
6231 MVT NewOutTy = DestVT;
6233 unsigned OpToUse = 0;
6235 // Scan for the appropriate larger type to use.
6237 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1);
6238 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
6240 // If the target supports FP_TO_SINT returning this type, use it.
6241 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
6243 case TargetLowering::Legal:
6244 if (!TLI.isTypeLegal(NewOutTy))
6245 break; // Can't use this datatype.
6247 case TargetLowering::Custom:
6248 OpToUse = ISD::FP_TO_SINT;
6253 // If the target supports FP_TO_UINT of this type, use it.
6254 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
6256 case TargetLowering::Legal:
6257 if (!TLI.isTypeLegal(NewOutTy))
6258 break; // Can't use this datatype.
6260 case TargetLowering::Custom:
6261 OpToUse = ISD::FP_TO_UINT;
6266 // Otherwise, try a larger type.
6270 // Okay, we found the operation and type to use.
6271 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
6273 // If the operation produces an invalid type, it must be custom lowered. Use
6274 // the target lowering hooks to expand it. Just keep the low part of the
6275 // expanded operation, we know that we're truncating anyway.
6276 if (getTypeAction(NewOutTy) == Expand) {
6277 SmallVector<SDValue, 2> Results;
6278 TLI.ReplaceNodeResults(Operation.getNode(), Results, DAG);
6279 assert(Results.size() == 1 && "Incorrect FP_TO_XINT lowering!");
6280 Operation = Results[0];
6283 // Truncate the result of the extended FP_TO_*INT operation to the desired
6285 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
6288 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
6290 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) {
6291 MVT VT = Op.getValueType();
6292 MVT SHVT = TLI.getShiftAmountTy();
6293 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
6294 switch (VT.getSimpleVT()) {
6295 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
6297 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
6298 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
6299 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
6301 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
6302 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
6303 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
6304 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
6305 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
6306 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
6307 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
6308 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
6309 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
6311 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
6312 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
6313 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
6314 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
6315 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
6316 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
6317 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
6318 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
6319 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
6320 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
6321 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
6322 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
6323 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
6324 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
6325 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
6326 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
6327 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
6328 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
6329 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
6330 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
6331 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
6335 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
6337 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
6340 default: assert(0 && "Cannot expand this yet!");
6342 static const uint64_t mask[6] = {
6343 0x5555555555555555ULL, 0x3333333333333333ULL,
6344 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
6345 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
6347 MVT VT = Op.getValueType();
6348 MVT ShVT = TLI.getShiftAmountTy();
6349 unsigned len = VT.getSizeInBits();
6350 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
6351 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
6352 unsigned EltSize = VT.isVector() ?
6353 VT.getVectorElementType().getSizeInBits() : len;
6354 SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT);
6355 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
6356 Op = DAG.getNode(ISD::ADD, dl, VT,
6357 DAG.getNode(ISD::AND, dl, VT, Op, Tmp2),
6358 DAG.getNode(ISD::AND, dl, VT,
6359 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3),
6365 // for now, we do this:
6366 // x = x | (x >> 1);
6367 // x = x | (x >> 2);
6369 // x = x | (x >>16);
6370 // x = x | (x >>32); // for 64-bit input
6371 // return popcount(~x);
6373 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
6374 MVT VT = Op.getValueType();
6375 MVT ShVT = TLI.getShiftAmountTy();
6376 unsigned len = VT.getSizeInBits();
6377 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
6378 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
6379 Op = DAG.getNode(ISD::OR, dl, VT, Op,
6380 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
6382 Op = DAG.getNOT(dl, Op, VT);
6383 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
6386 // for now, we use: { return popcount(~x & (x - 1)); }
6387 // unless the target has ctlz but not ctpop, in which case we use:
6388 // { return 32 - nlz(~x & (x-1)); }
6389 // see also http://www.hackersdelight.org/HDcode/ntz.cc
6390 MVT VT = Op.getValueType();
6391 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
6392 DAG.getNOT(dl, Op, VT),
6393 DAG.getNode(ISD::SUB, dl, VT, Op,
6394 DAG.getConstant(1, VT)));
6395 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
6396 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
6397 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
6398 return DAG.getNode(ISD::SUB, dl, VT,
6399 DAG.getConstant(VT.getSizeInBits(), VT),
6400 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
6401 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
6406 /// ExpandOp - Expand the specified SDValue into its two component pieces
6407 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
6408 /// LegalizedNodes map is filled in for any results that are not expanded, the
6409 /// ExpandedNodes map is filled in for any results that are expanded, and the
6410 /// Lo/Hi values are returned.
6411 void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
6412 MVT VT = Op.getValueType();
6413 MVT NVT = TLI.getTypeToTransformTo(VT);
6414 SDNode *Node = Op.getNode();
6415 DebugLoc dl = Node->getDebugLoc();
6416 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
6417 assert(((NVT.isInteger() && NVT.bitsLT(VT)) || VT.isFloatingPoint() ||
6418 VT.isVector()) && "Cannot expand to FP value or to larger int value!");
6420 // See if we already expanded it.
6421 DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator I
6422 = ExpandedNodes.find(Op);
6423 if (I != ExpandedNodes.end()) {
6424 Lo = I->second.first;
6425 Hi = I->second.second;
6429 switch (Node->getOpcode()) {
6430 case ISD::CopyFromReg:
6431 assert(0 && "CopyFromReg must be legal!");
6432 case ISD::FP_ROUND_INREG:
6433 if (VT == MVT::ppcf128 &&
6434 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
6435 TargetLowering::Custom) {
6436 SDValue SrcLo, SrcHi, Src;
6437 ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
6438 Src = DAG.getNode(ISD::BUILD_PAIR, dl, VT, SrcLo, SrcHi);
6440 TLI.LowerOperation(DAG.getNode(ISD::FP_ROUND_INREG, dl, VT, Src,
6441 Op.getOperand(1)), DAG);
6442 assert(Result.getNode()->getOpcode() == ISD::BUILD_PAIR);
6443 Lo = Result.getNode()->getOperand(0);
6444 Hi = Result.getNode()->getOperand(1);
6450 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
6452 assert(0 && "Do not know how to expand this operator!");
6454 case ISD::EXTRACT_ELEMENT:
6455 ExpandOp(Node->getOperand(0), Lo, Hi);
6456 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
6457 return ExpandOp(Hi, Lo, Hi);
6458 return ExpandOp(Lo, Lo, Hi);
6459 case ISD::EXTRACT_VECTOR_ELT:
6460 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types.
6461 Lo = ExpandEXTRACT_VECTOR_ELT(Op);
6462 return ExpandOp(Lo, Lo, Hi);
6464 Lo = DAG.getUNDEF(NVT);
6465 Hi = DAG.getUNDEF(NVT);
6467 case ISD::Constant: {
6468 unsigned NVTBits = NVT.getSizeInBits();
6469 const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue();
6470 Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT);
6471 Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT);
6474 case ISD::ConstantFP: {
6475 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
6476 if (CFP->getValueType(0) == MVT::ppcf128) {
6477 APInt api = CFP->getValueAPF().bitcastToAPInt();
6478 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
6480 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
6484 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
6485 if (getTypeAction(Lo.getValueType()) == Expand)
6486 ExpandOp(Lo, Lo, Hi);
6489 case ISD::BUILD_PAIR:
6490 // Return the operands.
6491 Lo = Node->getOperand(0);
6492 Hi = Node->getOperand(1);
6495 case ISD::MERGE_VALUES:
6496 if (Node->getNumValues() == 1) {
6497 ExpandOp(Op.getOperand(0), Lo, Hi);
6500 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y)
6501 assert(Op.getResNo() == 0 && Node->getNumValues() == 2 &&
6502 Op.getValue(1).getValueType() == MVT::Other &&
6503 "unhandled MERGE_VALUES");
6504 ExpandOp(Op.getOperand(0), Lo, Hi);
6505 // Remember that we legalized the chain.
6506 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1)));
6509 case ISD::SIGN_EXTEND_INREG:
6510 ExpandOp(Node->getOperand(0), Lo, Hi);
6511 // sext_inreg the low part if needed.
6512 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Lo, Node->getOperand(1));
6514 // The high part gets the sign extension from the lo-part. This handles
6515 // things like sextinreg V:i64 from i8.
6516 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
6517 DAG.getConstant(NVT.getSizeInBits()-1,
6518 TLI.getShiftAmountTy()));
6522 ExpandOp(Node->getOperand(0), Lo, Hi);
6523 SDValue TempLo = DAG.getNode(ISD::BSWAP, dl, NVT, Hi);
6524 Hi = DAG.getNode(ISD::BSWAP, dl, NVT, Lo);
6530 ExpandOp(Node->getOperand(0), Lo, Hi);
6531 Lo = DAG.getNode(ISD::ADD, dl, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
6532 DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
6533 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
6534 Hi = DAG.getConstant(0, NVT);
6538 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
6539 ExpandOp(Node->getOperand(0), Lo, Hi);
6540 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
6541 SDValue HLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Hi);
6542 SDValue TopNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), HLZ,
6544 SDValue LowPart = DAG.getNode(ISD::CTLZ, dl, NVT, Lo);
6545 LowPart = DAG.getNode(ISD::ADD, dl, NVT, LowPart, BitsC);
6547 Lo = DAG.getNode(ISD::SELECT, dl, NVT, TopNotZero, HLZ, LowPart);
6548 Hi = DAG.getConstant(0, NVT);
6553 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
6554 ExpandOp(Node->getOperand(0), Lo, Hi);
6555 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
6556 SDValue LTZ = DAG.getNode(ISD::CTTZ, dl, NVT, Lo);
6557 SDValue BotNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), LTZ,
6559 SDValue HiPart = DAG.getNode(ISD::CTTZ, dl, NVT, Hi);
6560 HiPart = DAG.getNode(ISD::ADD, dl, NVT, HiPart, BitsC);
6562 Lo = DAG.getNode(ISD::SELECT, dl, NVT, BotNotZero, LTZ, HiPart);
6563 Hi = DAG.getConstant(0, NVT);
6568 SDValue Ch = Node->getOperand(0); // Legalize the chain.
6569 SDValue Ptr = Node->getOperand(1); // Legalize the pointer.
6570 Lo = DAG.getVAArg(NVT, dl, Ch, Ptr, Node->getOperand(2));
6571 Hi = DAG.getVAArg(NVT, dl, Lo.getValue(1), Ptr, Node->getOperand(2));
6573 // Remember that we legalized the chain.
6574 Hi = LegalizeOp(Hi);
6575 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
6576 if (TLI.isBigEndian())
6582 LoadSDNode *LD = cast<LoadSDNode>(Node);
6583 SDValue Ch = LD->getChain(); // Legalize the chain.
6584 SDValue Ptr = LD->getBasePtr(); // Legalize the pointer.
6585 ISD::LoadExtType ExtType = LD->getExtensionType();
6586 const Value *SV = LD->getSrcValue();
6587 int SVOffset = LD->getSrcValueOffset();
6588 unsigned Alignment = LD->getAlignment();
6589 bool isVolatile = LD->isVolatile();
6591 if (ExtType == ISD::NON_EXTLOAD) {
6592 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, SV, SVOffset,
6593 isVolatile, Alignment);
6594 if (VT == MVT::f32 || VT == MVT::f64) {
6595 // f32->i32 or f64->i64 one to one expansion.
6596 // Remember that we legalized the chain.
6597 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
6598 // Recursively expand the new load.
6599 if (getTypeAction(NVT) == Expand)
6600 ExpandOp(Lo, Lo, Hi);
6604 // Increment the pointer to the other half.
6605 unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8;
6606 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
6607 DAG.getIntPtrConstant(IncrementSize));
6608 SVOffset += IncrementSize;
6609 Alignment = MinAlign(Alignment, IncrementSize);
6610 Hi = DAG.getLoad(NVT, dl, Ch, Ptr, SV, SVOffset,
6611 isVolatile, Alignment);
6613 // Build a factor node to remember that this load is independent of the
6615 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
6618 // Remember that we legalized the chain.
6619 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
6620 if (TLI.isBigEndian())
6623 MVT EVT = LD->getMemoryVT();
6625 if ((VT == MVT::f64 && EVT == MVT::f32) ||
6626 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
6627 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
6628 SDValue Load = DAG.getLoad(EVT, dl, Ch, Ptr, SV,
6629 SVOffset, isVolatile, Alignment);
6630 // Remember that we legalized the chain.
6631 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Load.getValue(1)));
6632 ExpandOp(DAG.getNode(ISD::FP_EXTEND, dl, VT, Load), Lo, Hi);
6637 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, SV,
6638 SVOffset, isVolatile, Alignment);
6640 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, SV,
6641 SVOffset, EVT, isVolatile,
6644 // Remember that we legalized the chain.
6645 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
6647 if (ExtType == ISD::SEXTLOAD) {
6648 // The high part is obtained by SRA'ing all but one of the bits of the
6650 unsigned LoSize = Lo.getValueType().getSizeInBits();
6651 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
6652 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6653 } else if (ExtType == ISD::ZEXTLOAD) {
6654 // The high part is just a zero.
6655 Hi = DAG.getConstant(0, NVT);
6656 } else /* if (ExtType == ISD::EXTLOAD) */ {
6657 // The high part is undefined.
6658 Hi = DAG.getUNDEF(NVT);
6665 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
6666 SDValue LL, LH, RL, RH;
6667 ExpandOp(Node->getOperand(0), LL, LH);
6668 ExpandOp(Node->getOperand(1), RL, RH);
6669 Lo = DAG.getNode(Node->getOpcode(), dl, NVT, LL, RL);
6670 Hi = DAG.getNode(Node->getOpcode(), dl, NVT, LH, RH);
6674 SDValue LL, LH, RL, RH;
6675 ExpandOp(Node->getOperand(1), LL, LH);
6676 ExpandOp(Node->getOperand(2), RL, RH);
6677 if (getTypeAction(NVT) == Expand)
6678 NVT = TLI.getTypeToExpandTo(NVT);
6679 Lo = DAG.getNode(ISD::SELECT, dl, NVT, Node->getOperand(0), LL, RL);
6681 Hi = DAG.getNode(ISD::SELECT, dl, NVT, Node->getOperand(0), LH, RH);
6684 case ISD::SELECT_CC: {
6685 SDValue TL, TH, FL, FH;
6686 ExpandOp(Node->getOperand(2), TL, TH);
6687 ExpandOp(Node->getOperand(3), FL, FH);
6688 if (getTypeAction(NVT) == Expand)
6689 NVT = TLI.getTypeToExpandTo(NVT);
6690 Lo = DAG.getNode(ISD::SELECT_CC, dl, NVT, Node->getOperand(0),
6691 Node->getOperand(1), TL, FL, Node->getOperand(4));
6693 Hi = DAG.getNode(ISD::SELECT_CC, dl, NVT, Node->getOperand(0),
6694 Node->getOperand(1), TH, FH, Node->getOperand(4));
6697 case ISD::ANY_EXTEND:
6698 // The low part is any extension of the input (which degenerates to a copy).
6699 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Node->getOperand(0));
6700 // The high part is undefined.
6701 Hi = DAG.getUNDEF(NVT);
6703 case ISD::SIGN_EXTEND: {
6704 // The low part is just a sign extension of the input (which degenerates to
6706 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, Node->getOperand(0));
6708 // The high part is obtained by SRA'ing all but one of the bits of the lo
6710 unsigned LoSize = Lo.getValueType().getSizeInBits();
6711 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
6712 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6715 case ISD::ZERO_EXTEND:
6716 // The low part is just a zero extension of the input (which degenerates to
6718 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
6720 // The high part is just a zero.
6721 Hi = DAG.getConstant(0, NVT);
6724 case ISD::TRUNCATE: {
6725 // The input value must be larger than this value. Expand *it*.
6727 ExpandOp(Node->getOperand(0), NewLo, Hi);
6729 // The low part is now either the right size, or it is closer. If not the
6730 // right size, make an illegal truncate so we recursively expand it.
6731 if (NewLo.getValueType() != Node->getValueType(0))
6732 NewLo = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), NewLo);
6733 ExpandOp(NewLo, Lo, Hi);
6737 case ISD::BIT_CONVERT: {
6739 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
6740 // If the target wants to, allow it to lower this itself.
6741 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6742 case Expand: assert(0 && "cannot expand FP!");
6743 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
6744 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
6746 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp), DAG);
6749 // f32 / f64 must be expanded to i32 / i64.
6750 if (VT == MVT::f32 || VT == MVT::f64) {
6751 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
6752 if (getTypeAction(NVT) == Expand)
6753 ExpandOp(Lo, Lo, Hi);
6757 // If source operand will be expanded to the same type as VT, i.e.
6758 // i64 <- f64, i32 <- f32, expand the source operand instead.
6759 MVT VT0 = Node->getOperand(0).getValueType();
6760 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
6761 ExpandOp(Node->getOperand(0), Lo, Hi);
6765 // Turn this into a load/store pair by default.
6766 if (Tmp.getNode() == 0)
6767 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT, dl);
6769 ExpandOp(Tmp, Lo, Hi);
6773 case ISD::READCYCLECOUNTER: {
6774 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
6775 TargetLowering::Custom &&
6776 "Must custom expand ReadCycleCounter");
6777 SDValue Tmp = TLI.LowerOperation(Op, DAG);
6778 assert(Tmp.getNode() && "Node must be custom expanded!");
6779 ExpandOp(Tmp.getValue(0), Lo, Hi);
6780 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6781 LegalizeOp(Tmp.getValue(1)));
6785 case ISD::ATOMIC_CMP_SWAP: {
6786 // This operation does not need a loop.
6787 SDValue Tmp = TLI.LowerOperation(Op, DAG);
6788 assert(Tmp.getNode() && "Node must be custom expanded!");
6789 ExpandOp(Tmp.getValue(0), Lo, Hi);
6790 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6791 LegalizeOp(Tmp.getValue(1)));
6795 case ISD::ATOMIC_LOAD_ADD:
6796 case ISD::ATOMIC_LOAD_SUB:
6797 case ISD::ATOMIC_LOAD_AND:
6798 case ISD::ATOMIC_LOAD_OR:
6799 case ISD::ATOMIC_LOAD_XOR:
6800 case ISD::ATOMIC_LOAD_NAND:
6801 case ISD::ATOMIC_SWAP: {
6802 // These operations require a loop to be generated. We can't do that yet,
6803 // so substitute a target-dependent pseudo and expand that later.
6804 SDValue In2Lo, In2Hi, In2;
6805 ExpandOp(Op.getOperand(2), In2Lo, In2Hi);
6806 In2 = DAG.getNode(ISD::BUILD_PAIR, dl, VT, In2Lo, In2Hi);
6807 AtomicSDNode* Anode = cast<AtomicSDNode>(Node);
6809 DAG.getAtomic(Op.getOpcode(), dl, Anode->getMemoryVT(),
6810 Op.getOperand(0), Op.getOperand(1), In2,
6811 Anode->getSrcValue(), Anode->getAlignment());
6812 SDValue Result = TLI.LowerOperation(Replace, DAG);
6813 ExpandOp(Result.getValue(0), Lo, Hi);
6814 // Remember that we legalized the chain.
6815 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Result.getValue(1)));
6819 // These operators cannot be expanded directly, emit them as calls to
6820 // library functions.
6821 case ISD::FP_TO_SINT: {
6822 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
6824 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6825 case Expand: assert(0 && "cannot expand FP!");
6826 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6827 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6830 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op), DAG);
6832 // Now that the custom expander is done, expand the result, which is still
6835 ExpandOp(Op, Lo, Hi);
6840 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Node->getOperand(0).getValueType(),
6842 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected uint-to-fp conversion!");
6843 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6847 case ISD::FP_TO_UINT: {
6848 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
6850 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6851 case Expand: assert(0 && "cannot expand FP!");
6852 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6853 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6856 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, dl, VT, Op), DAG);
6858 // Now that the custom expander is done, expand the result.
6860 ExpandOp(Op, Lo, Hi);
6865 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Node->getOperand(0).getValueType(),
6867 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
6868 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6873 // If the target wants custom lowering, do so.
6874 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6875 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
6876 SDValue Op = DAG.getNode(ISD::SHL, dl, VT, Node->getOperand(0), ShiftAmt);
6877 Op = TLI.LowerOperation(Op, DAG);
6879 // Now that the custom expander is done, expand the result, which is
6881 ExpandOp(Op, Lo, Hi);
6886 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
6887 // this X << 1 as X+X.
6888 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
6889 if (ShAmt->getAPIntValue() == 1 &&
6890 TLI.isOperationLegalOrCustom(ISD::ADDC, NVT) &&
6891 TLI.isOperationLegalOrCustom(ISD::ADDE, NVT)) {
6892 SDValue LoOps[2], HiOps[3];
6893 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
6894 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
6895 LoOps[1] = LoOps[0];
6896 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
6898 HiOps[1] = HiOps[0];
6899 HiOps[2] = Lo.getValue(1);
6900 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
6905 // If we can emit an efficient shift operation, do so now.
6906 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi, dl))
6909 // If this target supports SHL_PARTS, use it.
6910 TargetLowering::LegalizeAction Action =
6911 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
6912 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6913 Action == TargetLowering::Custom) {
6914 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0),
6915 ShiftAmt, Lo, Hi, dl);
6919 // Otherwise, emit a libcall.
6920 Lo = ExpandLibCall(RTLIB::SHL_I64, Node, false/*left shift=unsigned*/, Hi);
6925 // If the target wants custom lowering, do so.
6926 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6927 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
6928 SDValue Op = DAG.getNode(ISD::SRA, dl, VT, Node->getOperand(0), ShiftAmt);
6929 Op = TLI.LowerOperation(Op, DAG);
6931 // Now that the custom expander is done, expand the result, which is
6933 ExpandOp(Op, Lo, Hi);
6938 // If we can emit an efficient shift operation, do so now.
6939 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi, dl))
6942 // If this target supports SRA_PARTS, use it.
6943 TargetLowering::LegalizeAction Action =
6944 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
6945 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6946 Action == TargetLowering::Custom) {
6947 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0),
6948 ShiftAmt, Lo, Hi, dl);
6952 // Otherwise, emit a libcall.
6953 Lo = ExpandLibCall(RTLIB::SRA_I64, Node, true/*ashr is signed*/, Hi);
6958 // If the target wants custom lowering, do so.
6959 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6960 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
6961 SDValue Op = DAG.getNode(ISD::SRL, dl, VT, Node->getOperand(0), ShiftAmt);
6962 Op = TLI.LowerOperation(Op, DAG);
6964 // Now that the custom expander is done, expand the result, which is
6966 ExpandOp(Op, Lo, Hi);
6971 // If we can emit an efficient shift operation, do so now.
6972 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi, dl))
6975 // If this target supports SRL_PARTS, use it.
6976 TargetLowering::LegalizeAction Action =
6977 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
6978 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6979 Action == TargetLowering::Custom) {
6980 ExpandShiftParts(ISD::SRL_PARTS,
6981 Node->getOperand(0), ShiftAmt, Lo, Hi, dl);
6985 // Otherwise, emit a libcall.
6986 Lo = ExpandLibCall(RTLIB::SRL_I64, Node, false/*lshr is unsigned*/, Hi);
6992 // If the target wants to custom expand this, let them.
6993 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
6994 TargetLowering::Custom) {
6995 SDValue Result = TLI.LowerOperation(Op, DAG);
6996 if (Result.getNode()) {
6997 ExpandOp(Result, Lo, Hi);
7001 // Expand the subcomponents.
7002 SDValue LHSL, LHSH, RHSL, RHSH;
7003 ExpandOp(Node->getOperand(0), LHSL, LHSH);
7004 ExpandOp(Node->getOperand(1), RHSL, RHSH);
7005 SDValue LoOps[2], HiOps[3];
7011 //cascaded check to see if any smaller size has a a carry flag.
7012 unsigned OpV = Node->getOpcode() == ISD::ADD ? ISD::ADDC : ISD::SUBC;
7013 bool hasCarry = false;
7014 for (unsigned BitSize = NVT.getSizeInBits(); BitSize != 0; BitSize /= 2) {
7015 MVT AVT = MVT::getIntegerVT(BitSize);
7016 if (TLI.isOperationLegalOrCustom(OpV, AVT)) {
7023 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
7024 if (Node->getOpcode() == ISD::ADD) {
7025 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
7026 HiOps[2] = Lo.getValue(1);
7027 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
7029 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
7030 HiOps[2] = Lo.getValue(1);
7031 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
7035 if (Node->getOpcode() == ISD::ADD) {
7036 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2);
7037 Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2);
7038 SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
7039 Lo, LoOps[0], ISD::SETULT);
7040 SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1,
7041 DAG.getConstant(1, NVT),
7042 DAG.getConstant(0, NVT));
7043 SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
7044 Lo, LoOps[1], ISD::SETULT);
7045 SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2,
7046 DAG.getConstant(1, NVT),
7048 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
7050 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2);
7051 Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2);
7052 SDValue Cmp = DAG.getSetCC(dl, NVT, LoOps[0], LoOps[1], ISD::SETULT);
7053 SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp,
7054 DAG.getConstant(1, NVT),
7055 DAG.getConstant(0, NVT));
7056 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
7064 // Expand the subcomponents.
7065 SDValue LHSL, LHSH, RHSL, RHSH;
7066 ExpandOp(Node->getOperand(0), LHSL, LHSH);
7067 ExpandOp(Node->getOperand(1), RHSL, RHSH);
7068 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
7069 SDValue LoOps[2] = { LHSL, RHSL };
7070 SDValue HiOps[3] = { LHSH, RHSH };
7072 if (Node->getOpcode() == ISD::ADDC) {
7073 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
7074 HiOps[2] = Lo.getValue(1);
7075 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
7077 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
7078 HiOps[2] = Lo.getValue(1);
7079 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
7081 // Remember that we legalized the flag.
7082 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
7087 // Expand the subcomponents.
7088 SDValue LHSL, LHSH, RHSL, RHSH;
7089 ExpandOp(Node->getOperand(0), LHSL, LHSH);
7090 ExpandOp(Node->getOperand(1), RHSL, RHSH);
7091 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
7092 SDValue LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
7093 SDValue HiOps[3] = { LHSH, RHSH };
7095 Lo = DAG.getNode(Node->getOpcode(), dl, VTList, LoOps, 3);
7096 HiOps[2] = Lo.getValue(1);
7097 Hi = DAG.getNode(Node->getOpcode(), dl, VTList, HiOps, 3);
7099 // Remember that we legalized the flag.
7100 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
7104 // If the target wants to custom expand this, let them.
7105 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
7106 SDValue New = TLI.LowerOperation(Op, DAG);
7107 if (New.getNode()) {
7108 ExpandOp(New, Lo, Hi);
7113 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT);
7114 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT);
7115 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT);
7116 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT);
7117 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
7118 SDValue LL, LH, RL, RH;
7119 ExpandOp(Node->getOperand(0), LL, LH);
7120 ExpandOp(Node->getOperand(1), RL, RH);
7121 unsigned OuterBitSize = Op.getValueSizeInBits();
7122 unsigned InnerBitSize = RH.getValueSizeInBits();
7123 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
7124 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
7125 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
7126 if (DAG.MaskedValueIsZero(Node->getOperand(0), HighMask) &&
7127 DAG.MaskedValueIsZero(Node->getOperand(1), HighMask)) {
7128 // The inputs are both zero-extended.
7130 // We can emit a umul_lohi.
7131 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
7132 Hi = SDValue(Lo.getNode(), 1);
7136 // We can emit a mulhu+mul.
7137 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
7138 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
7142 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
7143 // The input values are both sign-extended.
7145 // We can emit a smul_lohi.
7146 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
7147 Hi = SDValue(Lo.getNode(), 1);
7151 // We can emit a mulhs+mul.
7152 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
7153 Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL);
7158 // Lo,Hi = umul LHS, RHS.
7159 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
7160 DAG.getVTList(NVT, NVT), LL, RL);
7162 Hi = UMulLOHI.getValue(1);
7163 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
7164 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
7165 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
7166 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
7170 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
7171 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
7172 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
7173 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
7174 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
7175 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
7180 // If nothing else, we can make a libcall.
7181 Lo = ExpandLibCall(RTLIB::MUL_I64, Node, false/*sign irrelevant*/, Hi);
7185 Lo = ExpandLibCall(RTLIB::SDIV_I64, Node, true, Hi);
7188 Lo = ExpandLibCall(RTLIB::UDIV_I64, Node, true, Hi);
7191 Lo = ExpandLibCall(RTLIB::SREM_I64, Node, true, Hi);
7194 Lo = ExpandLibCall(RTLIB::UREM_I64, Node, true, Hi);
7198 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::ADD_F32,
7201 RTLIB::ADD_PPCF128),
7205 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::SUB_F32,
7208 RTLIB::SUB_PPCF128),
7212 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::MUL_F32,
7215 RTLIB::MUL_PPCF128),
7219 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::DIV_F32,
7222 RTLIB::DIV_PPCF128),
7225 case ISD::FP_EXTEND: {
7226 if (VT == MVT::ppcf128) {
7227 assert(Node->getOperand(0).getValueType()==MVT::f32 ||
7228 Node->getOperand(0).getValueType()==MVT::f64);
7229 const uint64_t zero = 0;
7230 if (Node->getOperand(0).getValueType()==MVT::f32)
7231 Hi = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Node->getOperand(0));
7233 Hi = Node->getOperand(0);
7234 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7237 RTLIB::Libcall LC = RTLIB::getFPEXT(Node->getOperand(0).getValueType(), VT);
7238 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!");
7239 Lo = ExpandLibCall(LC, Node, true, Hi);
7242 case ISD::FP_ROUND: {
7243 RTLIB::Libcall LC = RTLIB::getFPROUND(Node->getOperand(0).getValueType(),
7245 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!");
7246 Lo = ExpandLibCall(LC, Node, true, Hi);
7261 case ISD::FNEARBYINT:
7264 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
7265 switch(Node->getOpcode()) {
7267 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
7268 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
7271 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
7272 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
7275 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
7276 RTLIB::COS_F80, RTLIB::COS_PPCF128);
7279 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
7280 RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
7283 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
7284 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
7287 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
7288 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
7291 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
7292 RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
7295 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
7296 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
7299 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
7300 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
7303 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
7304 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128);
7307 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
7308 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128);
7311 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64,
7312 RTLIB::RINT_F80, RTLIB::RINT_PPCF128);
7314 case ISD::FNEARBYINT:
7315 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
7316 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
7319 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
7320 RTLIB::POW_PPCF128);
7323 LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64, RTLIB::POWI_F80,
7324 RTLIB::POWI_PPCF128);
7326 default: assert(0 && "Unreachable!");
7328 Lo = ExpandLibCall(LC, Node, false, Hi);
7332 if (VT == MVT::ppcf128) {
7334 ExpandOp(Node->getOperand(0), Lo, Tmp);
7335 Hi = DAG.getNode(ISD::FABS, dl, NVT, Tmp);
7336 // lo = hi==fabs(hi) ? lo : -lo;
7337 Lo = DAG.getNode(ISD::SELECT_CC, dl, NVT, Hi, Tmp,
7338 Lo, DAG.getNode(ISD::FNEG, dl, NVT, Lo),
7339 DAG.getCondCode(ISD::SETEQ));
7342 SDValue Mask = (VT == MVT::f64)
7343 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
7344 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
7345 Mask = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Mask);
7346 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
7347 Lo = DAG.getNode(ISD::AND, dl, NVT, Lo, Mask);
7348 if (getTypeAction(NVT) == Expand)
7349 ExpandOp(Lo, Lo, Hi);
7353 if (VT == MVT::ppcf128) {
7354 ExpandOp(Node->getOperand(0), Lo, Hi);
7355 Lo = DAG.getNode(ISD::FNEG, dl, MVT::f64, Lo);
7356 Hi = DAG.getNode(ISD::FNEG, dl, MVT::f64, Hi);
7359 SDValue Mask = (VT == MVT::f64)
7360 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
7361 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
7362 Mask = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Mask);
7363 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
7364 Lo = DAG.getNode(ISD::XOR, dl, NVT, Lo, Mask);
7365 if (getTypeAction(NVT) == Expand)
7366 ExpandOp(Lo, Lo, Hi);
7369 case ISD::FCOPYSIGN: {
7370 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
7371 if (getTypeAction(NVT) == Expand)
7372 ExpandOp(Lo, Lo, Hi);
7375 case ISD::SINT_TO_FP:
7376 case ISD::UINT_TO_FP: {
7377 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
7378 MVT SrcVT = Node->getOperand(0).getValueType();
7380 // Promote the operand if needed. Do this before checking for
7381 // ppcf128 so conversions of i16 and i8 work.
7382 if (getTypeAction(SrcVT) == Promote) {
7383 SDValue Tmp = PromoteOp(Node->getOperand(0));
7385 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Tmp.getValueType(), Tmp,
7386 DAG.getValueType(SrcVT))
7387 : DAG.getZeroExtendInReg(Tmp, dl, SrcVT);
7388 Node = DAG.UpdateNodeOperands(Op, Tmp).getNode();
7389 SrcVT = Node->getOperand(0).getValueType();
7392 if (VT == MVT::ppcf128 && SrcVT == MVT::i32) {
7393 static const uint64_t zero = 0;
7395 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f64,
7396 Node->getOperand(0)));
7397 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7399 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
7400 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f64,
7401 Node->getOperand(0)));
7402 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7403 Hi = DAG.getNode(ISD::BUILD_PAIR, dl, VT, Lo, Hi);
7404 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
7405 ExpandOp(DAG.getNode(ISD::SELECT_CC, dl,
7406 MVT::ppcf128, Node->getOperand(0),
7407 DAG.getConstant(0, MVT::i32),
7408 DAG.getNode(ISD::FADD, dl, MVT::ppcf128, Hi,
7410 (APFloat(APInt(128, 2, TwoE32)),
7413 DAG.getCondCode(ISD::SETLT)),
7418 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) {
7419 // si64->ppcf128 done by libcall, below
7420 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
7421 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, dl, MVT::ppcf128,
7422 Node->getOperand(0)), Lo, Hi);
7423 Hi = DAG.getNode(ISD::BUILD_PAIR, dl, VT, Lo, Hi);
7424 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
7425 ExpandOp(DAG.getNode(ISD::SELECT_CC, dl, MVT::ppcf128,
7426 Node->getOperand(0),
7427 DAG.getConstant(0, MVT::i64),
7428 DAG.getNode(ISD::FADD, dl, MVT::ppcf128, Hi,
7430 (APFloat(APInt(128, 2, TwoE64)),
7433 DAG.getCondCode(ISD::SETLT)),
7438 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
7439 Node->getOperand(0), dl);
7440 if (getTypeAction(Lo.getValueType()) == Expand)
7441 // float to i32 etc. can be 'expanded' to a single node.
7442 ExpandOp(Lo, Lo, Hi);
7447 // Make sure the resultant values have been legalized themselves, unless this
7448 // is a type that requires multi-step expansion.
7449 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
7450 Lo = LegalizeOp(Lo);
7452 // Don't legalize the high part if it is expanded to a single node.
7453 Hi = LegalizeOp(Hi);
7456 // Remember in a map if the values will be reused later.
7458 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
7459 assert(isNew && "Value already expanded?!?");
7463 /// SplitVectorOp - Given an operand of vector type, break it down into
7464 /// two smaller values, still of vector type.
7465 void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
7467 assert(Op.getValueType().isVector() && "Cannot split non-vector type!");
7468 SDNode *Node = Op.getNode();
7469 DebugLoc dl = Node->getDebugLoc();
7470 unsigned NumElements = Op.getValueType().getVectorNumElements();
7471 assert(NumElements > 1 && "Cannot split a single element vector!");
7473 MVT NewEltVT = Op.getValueType().getVectorElementType();
7475 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
7476 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
7478 MVT NewVT_Lo = MVT::getVectorVT(NewEltVT, NewNumElts_Lo);
7479 MVT NewVT_Hi = MVT::getVectorVT(NewEltVT, NewNumElts_Hi);
7481 // See if we already split it.
7482 std::map<SDValue, std::pair<SDValue, SDValue> >::iterator I
7483 = SplitNodes.find(Op);
7484 if (I != SplitNodes.end()) {
7485 Lo = I->second.first;
7486 Hi = I->second.second;
7490 switch (Node->getOpcode()) {
7495 assert(0 && "Unhandled operation in SplitVectorOp!");
7497 Lo = DAG.getUNDEF(NewVT_Lo);
7498 Hi = DAG.getUNDEF(NewVT_Hi);
7500 case ISD::BUILD_PAIR:
7501 Lo = Node->getOperand(0);
7502 Hi = Node->getOperand(1);
7504 case ISD::INSERT_VECTOR_ELT: {
7505 if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) {
7506 SplitVectorOp(Node->getOperand(0), Lo, Hi);
7507 unsigned Index = Idx->getZExtValue();
7508 SDValue ScalarOp = Node->getOperand(1);
7509 if (Index < NewNumElts_Lo)
7510 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVT_Lo, Lo, ScalarOp,
7511 DAG.getIntPtrConstant(Index));
7513 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVT_Hi, Hi, ScalarOp,
7514 DAG.getIntPtrConstant(Index - NewNumElts_Lo));
7517 SDValue Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0),
7518 Node->getOperand(1),
7519 Node->getOperand(2), dl);
7520 SplitVectorOp(Tmp, Lo, Hi);
7523 case ISD::VECTOR_SHUFFLE: {
7524 // Build the low part.
7525 SDValue Mask = Node->getOperand(2);
7526 SmallVector<SDValue, 8> Ops;
7527 MVT PtrVT = TLI.getPointerTy();
7529 // Insert all of the elements from the input that are needed. We use
7530 // buildvector of extractelement here because the input vectors will have
7531 // to be legalized, so this makes the code simpler.
7532 for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
7533 SDValue IdxNode = Mask.getOperand(i);
7534 if (IdxNode.getOpcode() == ISD::UNDEF) {
7535 Ops.push_back(DAG.getUNDEF(NewEltVT));
7538 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
7539 SDValue InVec = Node->getOperand(0);
7540 if (Idx >= NumElements) {
7541 InVec = Node->getOperand(1);
7544 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewEltVT, InVec,
7545 DAG.getConstant(Idx, PtrVT)));
7547 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Lo, &Ops[0], Ops.size());
7550 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
7551 SDValue IdxNode = Mask.getOperand(i);
7552 if (IdxNode.getOpcode() == ISD::UNDEF) {
7553 Ops.push_back(DAG.getUNDEF(NewEltVT));
7556 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
7557 SDValue InVec = Node->getOperand(0);
7558 if (Idx >= NumElements) {
7559 InVec = Node->getOperand(1);
7562 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewEltVT, InVec,
7563 DAG.getConstant(Idx, PtrVT)));
7565 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Hi, &Ops[0], Ops.size());
7568 case ISD::BUILD_VECTOR: {
7569 SmallVector<SDValue, 8> LoOps(Node->op_begin(),
7570 Node->op_begin()+NewNumElts_Lo);
7571 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Lo, &LoOps[0], LoOps.size());
7573 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
7575 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Hi, &HiOps[0], HiOps.size());
7578 case ISD::CONCAT_VECTORS: {
7579 // FIXME: Handle non-power-of-two vectors?
7580 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
7581 if (NewNumSubvectors == 1) {
7582 Lo = Node->getOperand(0);
7583 Hi = Node->getOperand(1);
7585 SmallVector<SDValue, 8> LoOps(Node->op_begin(),
7586 Node->op_begin()+NewNumSubvectors);
7587 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewVT_Lo,
7588 &LoOps[0], LoOps.size());
7590 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumSubvectors,
7592 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewVT_Hi,
7593 &HiOps[0], HiOps.size());
7597 case ISD::EXTRACT_SUBVECTOR: {
7598 SDValue Vec = Op.getOperand(0);
7599 SDValue Idx = Op.getOperand(1);
7600 MVT IdxVT = Idx.getValueType();
7602 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT_Lo, Vec, Idx);
7603 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx);
7605 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT_Hi, Vec,
7606 DAG.getConstant(CIdx->getZExtValue() + NewNumElts_Lo,
7609 Idx = DAG.getNode(ISD::ADD, dl, IdxVT, Idx,
7610 DAG.getConstant(NewNumElts_Lo, IdxVT));
7611 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT_Hi, Vec, Idx);
7616 SDValue Cond = Node->getOperand(0);
7618 SDValue LL, LH, RL, RH;
7619 SplitVectorOp(Node->getOperand(1), LL, LH);
7620 SplitVectorOp(Node->getOperand(2), RL, RH);
7622 if (Cond.getValueType().isVector()) {
7623 // Handle a vector merge.
7625 SplitVectorOp(Cond, CL, CH);
7626 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, CL, LL, RL);
7627 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, CH, LH, RH);
7629 // Handle a simple select with vector operands.
7630 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, Cond, LL, RL);
7631 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, Cond, LH, RH);
7635 case ISD::SELECT_CC: {
7636 SDValue CondLHS = Node->getOperand(0);
7637 SDValue CondRHS = Node->getOperand(1);
7638 SDValue CondCode = Node->getOperand(4);
7640 SDValue LL, LH, RL, RH;
7641 SplitVectorOp(Node->getOperand(2), LL, LH);
7642 SplitVectorOp(Node->getOperand(3), RL, RH);
7644 // Handle a simple select with vector operands.
7645 Lo = DAG.getNode(ISD::SELECT_CC, dl, NewVT_Lo, CondLHS, CondRHS,
7647 Hi = DAG.getNode(ISD::SELECT_CC, dl, NewVT_Hi, CondLHS, CondRHS,
7652 SDValue LL, LH, RL, RH;
7653 SplitVectorOp(Node->getOperand(0), LL, LH);
7654 SplitVectorOp(Node->getOperand(1), RL, RH);
7655 Lo = DAG.getNode(ISD::VSETCC, dl, NewVT_Lo, LL, RL, Node->getOperand(2));
7656 Hi = DAG.getNode(ISD::VSETCC, dl, NewVT_Hi, LH, RH, Node->getOperand(2));
7678 SDValue LL, LH, RL, RH;
7679 SplitVectorOp(Node->getOperand(0), LL, LH);
7680 SplitVectorOp(Node->getOperand(1), RL, RH);
7682 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, LL, RL);
7683 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, LH, RH);
7689 SplitVectorOp(Node->getOperand(0), L, H);
7691 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, L, Node->getOperand(1));
7692 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, H, Node->getOperand(1));
7708 case ISD::FP_TO_SINT:
7709 case ISD::FP_TO_UINT:
7710 case ISD::SINT_TO_FP:
7711 case ISD::UINT_TO_FP:
7713 case ISD::ANY_EXTEND:
7714 case ISD::SIGN_EXTEND:
7715 case ISD::ZERO_EXTEND:
7716 case ISD::FP_EXTEND: {
7718 SplitVectorOp(Node->getOperand(0), L, H);
7720 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, L);
7721 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, H);
7724 case ISD::CONVERT_RNDSAT: {
7725 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
7727 SplitVectorOp(Node->getOperand(0), L, H);
7728 SDValue DTyOpL = DAG.getValueType(NewVT_Lo);
7729 SDValue DTyOpH = DAG.getValueType(NewVT_Hi);
7730 SDValue STyOpL = DAG.getValueType(L.getValueType());
7731 SDValue STyOpH = DAG.getValueType(H.getValueType());
7733 SDValue RndOp = Node->getOperand(3);
7734 SDValue SatOp = Node->getOperand(4);
7736 Lo = DAG.getConvertRndSat(NewVT_Lo, dl, L, DTyOpL, STyOpL,
7737 RndOp, SatOp, CvtCode);
7738 Hi = DAG.getConvertRndSat(NewVT_Hi, dl, H, DTyOpH, STyOpH,
7739 RndOp, SatOp, CvtCode);
7743 LoadSDNode *LD = cast<LoadSDNode>(Node);
7744 SDValue Ch = LD->getChain();
7745 SDValue Ptr = LD->getBasePtr();
7746 ISD::LoadExtType ExtType = LD->getExtensionType();
7747 const Value *SV = LD->getSrcValue();
7748 int SVOffset = LD->getSrcValueOffset();
7749 MVT MemoryVT = LD->getMemoryVT();
7750 unsigned Alignment = LD->getAlignment();
7751 bool isVolatile = LD->isVolatile();
7753 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
7754 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
7756 MVT MemNewEltVT = MemoryVT.getVectorElementType();
7757 MVT MemNewVT_Lo = MVT::getVectorVT(MemNewEltVT, NewNumElts_Lo);
7758 MVT MemNewVT_Hi = MVT::getVectorVT(MemNewEltVT, NewNumElts_Hi);
7760 Lo = DAG.getLoad(ISD::UNINDEXED, dl, ExtType,
7761 NewVT_Lo, Ch, Ptr, Offset,
7762 SV, SVOffset, MemNewVT_Lo, isVolatile, Alignment);
7763 unsigned IncrementSize = NewNumElts_Lo * MemNewEltVT.getSizeInBits()/8;
7764 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
7765 DAG.getIntPtrConstant(IncrementSize));
7766 SVOffset += IncrementSize;
7767 Alignment = MinAlign(Alignment, IncrementSize);
7768 Hi = DAG.getLoad(ISD::UNINDEXED, dl, ExtType,
7769 NewVT_Hi, Ch, Ptr, Offset,
7770 SV, SVOffset, MemNewVT_Hi, isVolatile, Alignment);
7772 // Build a factor node to remember that this load is independent of the
7774 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
7777 // Remember that we legalized the chain.
7778 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
7781 case ISD::BIT_CONVERT: {
7782 // We know the result is a vector. The input may be either a vector or a
7784 SDValue InOp = Node->getOperand(0);
7785 if (!InOp.getValueType().isVector() ||
7786 InOp.getValueType().getVectorNumElements() == 1) {
7787 // The input is a scalar or single-element vector.
7788 // Lower to a store/load so that it can be split.
7789 // FIXME: this could be improved probably.
7790 unsigned LdAlign = TLI.getTargetData()->
7791 getPrefTypeAlignment(Op.getValueType().getTypeForMVT());
7792 SDValue Ptr = DAG.CreateStackTemporary(InOp.getValueType(), LdAlign);
7793 int FI = cast<FrameIndexSDNode>(Ptr.getNode())->getIndex();
7795 SDValue St = DAG.getStore(DAG.getEntryNode(), dl,
7797 PseudoSourceValue::getFixedStack(FI), 0);
7798 InOp = DAG.getLoad(Op.getValueType(), dl, St, Ptr,
7799 PseudoSourceValue::getFixedStack(FI), 0);
7801 // Split the vector and convert each of the pieces now.
7802 SplitVectorOp(InOp, Lo, Hi);
7803 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT_Lo, Lo);
7804 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT_Hi, Hi);
7809 // Remember in a map if the values will be reused later.
7811 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
7812 assert(isNew && "Value already split?!?");
7817 /// ScalarizeVectorOp - Given an operand of single-element vector type
7818 /// (e.g. v1f32), convert it into the equivalent operation that returns a
7819 /// scalar (e.g. f32) value.
7820 SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) {
7821 assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!");
7822 SDNode *Node = Op.getNode();
7823 DebugLoc dl = Node->getDebugLoc();
7824 MVT NewVT = Op.getValueType().getVectorElementType();
7825 assert(Op.getValueType().getVectorNumElements() == 1);
7827 // See if we already scalarized it.
7828 std::map<SDValue, SDValue>::iterator I = ScalarizedNodes.find(Op);
7829 if (I != ScalarizedNodes.end()) return I->second;
7832 switch (Node->getOpcode()) {
7835 Node->dump(&DAG); cerr << "\n";
7837 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
7854 Result = DAG.getNode(Node->getOpcode(), dl,
7856 ScalarizeVectorOp(Node->getOperand(0)),
7857 ScalarizeVectorOp(Node->getOperand(1)));
7869 case ISD::FP_TO_SINT:
7870 case ISD::FP_TO_UINT:
7871 case ISD::SINT_TO_FP:
7872 case ISD::UINT_TO_FP:
7873 case ISD::SIGN_EXTEND:
7874 case ISD::ZERO_EXTEND:
7875 case ISD::ANY_EXTEND:
7877 case ISD::FP_EXTEND:
7878 Result = DAG.getNode(Node->getOpcode(), dl,
7880 ScalarizeVectorOp(Node->getOperand(0)));
7882 case ISD::CONVERT_RNDSAT: {
7883 SDValue Op0 = ScalarizeVectorOp(Node->getOperand(0));
7884 Result = DAG.getConvertRndSat(NewVT, dl, Op0,
7885 DAG.getValueType(NewVT),
7886 DAG.getValueType(Op0.getValueType()),
7887 Node->getOperand(3),
7888 Node->getOperand(4),
7889 cast<CvtRndSatSDNode>(Node)->getCvtCode());
7894 Result = DAG.getNode(Node->getOpcode(), dl,
7896 ScalarizeVectorOp(Node->getOperand(0)),
7897 Node->getOperand(1));
7900 LoadSDNode *LD = cast<LoadSDNode>(Node);
7901 SDValue Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
7902 SDValue Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
7903 ISD::LoadExtType ExtType = LD->getExtensionType();
7904 const Value *SV = LD->getSrcValue();
7905 int SVOffset = LD->getSrcValueOffset();
7906 MVT MemoryVT = LD->getMemoryVT();
7907 unsigned Alignment = LD->getAlignment();
7908 bool isVolatile = LD->isVolatile();
7910 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
7911 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
7913 Result = DAG.getLoad(ISD::UNINDEXED, dl, ExtType,
7914 NewVT, Ch, Ptr, Offset, SV, SVOffset,
7915 MemoryVT.getVectorElementType(),
7916 isVolatile, Alignment);
7918 // Remember that we legalized the chain.
7919 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
7922 case ISD::BUILD_VECTOR:
7923 Result = Node->getOperand(0);
7925 case ISD::INSERT_VECTOR_ELT:
7926 // Returning the inserted scalar element.
7927 Result = Node->getOperand(1);
7929 case ISD::CONCAT_VECTORS:
7930 assert(Node->getOperand(0).getValueType() == NewVT &&
7931 "Concat of non-legal vectors not yet supported!");
7932 Result = Node->getOperand(0);
7934 case ISD::VECTOR_SHUFFLE: {
7935 // Figure out if the scalar is the LHS or RHS and return it.
7936 SDValue EltNum = Node->getOperand(2).getOperand(0);
7937 if (cast<ConstantSDNode>(EltNum)->getZExtValue())
7938 Result = ScalarizeVectorOp(Node->getOperand(1));
7940 Result = ScalarizeVectorOp(Node->getOperand(0));
7943 case ISD::EXTRACT_SUBVECTOR:
7944 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT,
7945 Node->getOperand(0), Node->getOperand(1));
7947 case ISD::BIT_CONVERT: {
7948 SDValue Op0 = Op.getOperand(0);
7949 if (Op0.getValueType().getVectorNumElements() == 1)
7950 Op0 = ScalarizeVectorOp(Op0);
7951 Result = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, Op0);
7955 Result = DAG.getNode(ISD::SELECT, dl, NewVT, Op.getOperand(0),
7956 ScalarizeVectorOp(Op.getOperand(1)),
7957 ScalarizeVectorOp(Op.getOperand(2)));
7959 case ISD::SELECT_CC:
7960 Result = DAG.getNode(ISD::SELECT_CC, dl, NewVT, Node->getOperand(0),
7961 Node->getOperand(1),
7962 ScalarizeVectorOp(Op.getOperand(2)),
7963 ScalarizeVectorOp(Op.getOperand(3)),
7964 Node->getOperand(4));
7967 SDValue Op0 = ScalarizeVectorOp(Op.getOperand(0));
7968 SDValue Op1 = ScalarizeVectorOp(Op.getOperand(1));
7969 Result = DAG.getNode(ISD::SETCC, dl,
7970 TLI.getSetCCResultType(Op0.getValueType()),
7971 Op0, Op1, Op.getOperand(2));
7972 Result = DAG.getNode(ISD::SELECT, dl, NewVT, Result,
7973 DAG.getConstant(-1ULL, NewVT),
7974 DAG.getConstant(0ULL, NewVT));
7979 if (TLI.isTypeLegal(NewVT))
7980 Result = LegalizeOp(Result);
7981 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
7982 assert(isNew && "Value already scalarized?");
7988 SDValue SelectionDAGLegalize::WidenVectorOp(SDValue Op, MVT WidenVT) {
7989 std::map<SDValue, SDValue>::iterator I = WidenNodes.find(Op);
7990 if (I != WidenNodes.end()) return I->second;
7992 MVT VT = Op.getValueType();
7993 assert(VT.isVector() && "Cannot widen non-vector type!");
7996 SDNode *Node = Op.getNode();
7997 DebugLoc dl = Node->getDebugLoc();
7998 MVT EVT = VT.getVectorElementType();
8000 unsigned NumElts = VT.getVectorNumElements();
8001 unsigned NewNumElts = WidenVT.getVectorNumElements();
8002 assert(NewNumElts > NumElts && "Cannot widen to smaller type!");
8003 assert(NewNumElts < 17);
8005 // When widen is called, it is assumed that it is more efficient to use a
8006 // wide type. The default action is to widen to operation to a wider legal
8007 // vector type and then do the operation if it is legal by calling LegalizeOp
8008 // again. If there is no vector equivalent, we will unroll the operation, do
8009 // it, and rebuild the vector. If most of the operations are vectorizible to
8010 // the legal type, the resulting code will be more efficient. If this is not
8011 // the case, the resulting code will preform badly as we end up generating
8012 // code to pack/unpack the results. It is the function that calls widen
8013 // that is responsible for seeing this doesn't happen.
8014 switch (Node->getOpcode()) {
8019 assert(0 && "Unexpected operation in WidenVectorOp!");
8021 case ISD::CopyFromReg:
8022 assert(0 && "CopyFromReg doesn't need widening!");
8024 case ISD::ConstantFP:
8025 // To build a vector of these elements, clients should call BuildVector
8026 // and with each element instead of creating a node with a vector type
8027 assert(0 && "Unexpected operation in WidenVectorOp!");
8029 // Variable Arguments with vector types doesn't make any sense to me
8030 assert(0 && "Unexpected operation in WidenVectorOp!");
8033 Result = DAG.getUNDEF(WidenVT);
8035 case ISD::BUILD_VECTOR: {
8036 // Build a vector with undefined for the new nodes
8037 SDValueVector NewOps(Node->op_begin(), Node->op_end());
8038 for (unsigned i = NumElts; i < NewNumElts; ++i) {
8039 NewOps.push_back(DAG.getUNDEF(EVT));
8041 Result = DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT,
8042 &NewOps[0], NewOps.size());
8045 case ISD::INSERT_VECTOR_ELT: {
8046 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8047 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, WidenVT, Tmp1,
8048 Node->getOperand(1), Node->getOperand(2));
8051 case ISD::VECTOR_SHUFFLE: {
8052 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8053 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT);
8054 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Node);
8055 SmallVector<int, 8> NewMask;
8056 for (unsigned i = 0; i < NumElts; ++i) {
8057 int Idx = SVOp->getMaskElt(i);
8058 if (Idx < (int)NumElts)
8059 NewMask.push_back(Idx);
8061 NewMask.push_back(Idx + NewNumElts - NumElts);
8063 for (unsigned i = NumElts; i < NewNumElts; ++i)
8064 NewMask.push_back(-1);
8066 Result = DAG.getVectorShuffle(WidenVT, dl, Tmp1, Tmp2, &NewMask[0]);
8070 // If the load widen returns true, we can use a single load for the
8071 // vector. Otherwise, it is returning a token factor for multiple
8074 if (LoadWidenVectorOp(Result, TFOp, Op, WidenVT))
8075 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TFOp.getValue(1)));
8077 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TFOp.getValue(0)));
8081 case ISD::BIT_CONVERT: {
8082 SDValue Tmp1 = Node->getOperand(0);
8083 // Converts between two different types so we need to determine
8084 // the correct widen type for the input operand.
8085 MVT InVT = Tmp1.getValueType();
8086 unsigned WidenSize = WidenVT.getSizeInBits();
8087 if (InVT.isVector()) {
8088 MVT InEltVT = InVT.getVectorElementType();
8089 unsigned InEltSize = InEltVT.getSizeInBits();
8090 assert(WidenSize % InEltSize == 0 &&
8091 "can not widen bit convert that are not multiple of element type");
8092 MVT NewInWidenVT = MVT::getVectorVT(InEltVT, WidenSize / InEltSize);
8093 Tmp1 = WidenVectorOp(Tmp1, NewInWidenVT);
8094 assert(Tmp1.getValueType().getSizeInBits() == WidenVT.getSizeInBits());
8095 Result = DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, Tmp1);
8097 // If the result size is a multiple of the input size, widen the input
8098 // and then convert.
8099 unsigned InSize = InVT.getSizeInBits();
8100 assert(WidenSize % InSize == 0 &&
8101 "can not widen bit convert that are not multiple of element type");
8102 unsigned NewNumElts = WidenSize / InSize;
8103 SmallVector<SDValue, 16> Ops(NewNumElts);
8104 SDValue UndefVal = DAG.getUNDEF(InVT);
8106 for (unsigned i = 1; i < NewNumElts; ++i)
8109 MVT NewInVT = MVT::getVectorVT(InVT, NewNumElts);
8110 Result = DAG.getNode(ISD::BUILD_VECTOR, dl, NewInVT, &Ops[0], NewNumElts);
8111 Result = DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, Result);
8116 case ISD::SINT_TO_FP:
8117 case ISD::UINT_TO_FP:
8118 case ISD::FP_TO_SINT:
8119 case ISD::FP_TO_UINT:
8120 case ISD::FP_ROUND: {
8121 SDValue Tmp1 = Node->getOperand(0);
8122 // Converts between two different types so we need to determine
8123 // the correct widen type for the input operand.
8124 MVT TVT = Tmp1.getValueType();
8125 assert(TVT.isVector() && "can not widen non vector type");
8126 MVT TEVT = TVT.getVectorElementType();
8127 MVT TWidenVT = MVT::getVectorVT(TEVT, NewNumElts);
8128 Tmp1 = WidenVectorOp(Tmp1, TWidenVT);
8129 assert(Tmp1.getValueType().getVectorNumElements() == NewNumElts);
8130 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1);
8134 case ISD::FP_EXTEND:
8135 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
8137 case ISD::SIGN_EXTEND:
8138 case ISD::ZERO_EXTEND:
8139 case ISD::ANY_EXTEND:
8140 case ISD::SIGN_EXTEND_INREG:
8149 // Unary op widening
8151 Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8152 assert(Tmp1.getValueType() == WidenVT);
8153 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1);
8156 case ISD::CONVERT_RNDSAT: {
8157 SDValue RndOp = Node->getOperand(3);
8158 SDValue SatOp = Node->getOperand(4);
8159 SDValue SrcOp = Node->getOperand(0);
8161 // Converts between two different types so we need to determine
8162 // the correct widen type for the input operand.
8163 MVT SVT = SrcOp.getValueType();
8164 assert(SVT.isVector() && "can not widen non vector type");
8165 MVT SEVT = SVT.getVectorElementType();
8166 MVT SWidenVT = MVT::getVectorVT(SEVT, NewNumElts);
8168 SrcOp = WidenVectorOp(SrcOp, SWidenVT);
8169 assert(SrcOp.getValueType() == WidenVT);
8170 SDValue DTyOp = DAG.getValueType(WidenVT);
8171 SDValue STyOp = DAG.getValueType(SrcOp.getValueType());
8172 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
8174 Result = DAG.getConvertRndSat(WidenVT, dl, SrcOp, DTyOp, STyOp,
8175 RndOp, SatOp, CvtCode);
8195 case ISD::FCOPYSIGN:
8199 // Binary op widening
8200 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8201 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT);
8202 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT);
8203 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1, Tmp2);
8210 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8211 assert(Tmp1.getValueType() == WidenVT);
8212 SDValue ShOp = Node->getOperand(1);
8213 MVT ShVT = ShOp.getValueType();
8214 MVT NewShVT = MVT::getVectorVT(ShVT.getVectorElementType(),
8215 WidenVT.getVectorNumElements());
8216 ShOp = WidenVectorOp(ShOp, NewShVT);
8217 assert(ShOp.getValueType() == NewShVT);
8218 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1, ShOp);
8222 case ISD::EXTRACT_VECTOR_ELT: {
8223 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8224 assert(Tmp1.getValueType() == WidenVT);
8225 Result = DAG.getNode(Node->getOpcode(), dl, EVT, Tmp1, Node->getOperand(1));
8228 case ISD::CONCAT_VECTORS: {
8229 // We concurrently support only widen on a multiple of the incoming vector.
8230 // We could widen on a multiple of the incoming operand if necessary.
8231 unsigned NumConcat = NewNumElts / NumElts;
8232 assert(NewNumElts % NumElts == 0 && "Can widen only a multiple of vector");
8233 SDValue UndefVal = DAG.getUNDEF(VT);
8234 SmallVector<SDValue, 8> MOps;
8236 for (unsigned i = 1; i != NumConcat; ++i) {
8237 MOps.push_back(UndefVal);
8239 Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
8240 &MOps[0], MOps.size()));
8243 case ISD::EXTRACT_SUBVECTOR: {
8244 SDValue Tmp1 = Node->getOperand(0);
8245 SDValue Idx = Node->getOperand(1);
8246 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx);
8247 if (CIdx && CIdx->getZExtValue() == 0) {
8248 // Since we are access the start of the vector, the incoming
8249 // vector type might be the proper.
8250 MVT Tmp1VT = Tmp1.getValueType();
8251 if (Tmp1VT == WidenVT)
8254 unsigned Tmp1VTNumElts = Tmp1VT.getVectorNumElements();
8255 if (Tmp1VTNumElts < NewNumElts)
8256 Result = WidenVectorOp(Tmp1, WidenVT);
8258 Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, Tmp1, Idx);
8260 } else if (NewNumElts % NumElts == 0) {
8261 // Widen the extracted subvector.
8262 unsigned NumConcat = NewNumElts / NumElts;
8263 SDValue UndefVal = DAG.getUNDEF(VT);
8264 SmallVector<SDValue, 8> MOps;
8266 for (unsigned i = 1; i != NumConcat; ++i) {
8267 MOps.push_back(UndefVal);
8269 Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
8270 &MOps[0], MOps.size()));
8272 assert(0 && "can not widen extract subvector");
8273 // This could be implemented using insert and build vector but I would
8274 // like to see when this happens.
8280 // Determine new condition widen type and widen
8281 SDValue Cond1 = Node->getOperand(0);
8282 MVT CondVT = Cond1.getValueType();
8283 assert(CondVT.isVector() && "can not widen non vector type");
8284 MVT CondEVT = CondVT.getVectorElementType();
8285 MVT CondWidenVT = MVT::getVectorVT(CondEVT, NewNumElts);
8286 Cond1 = WidenVectorOp(Cond1, CondWidenVT);
8287 assert(Cond1.getValueType() == CondWidenVT && "Condition not widen");
8289 SDValue Tmp1 = WidenVectorOp(Node->getOperand(1), WidenVT);
8290 SDValue Tmp2 = WidenVectorOp(Node->getOperand(2), WidenVT);
8291 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT);
8292 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Cond1, Tmp1, Tmp2);
8296 case ISD::SELECT_CC: {
8297 // Determine new condition widen type and widen
8298 SDValue Cond1 = Node->getOperand(0);
8299 SDValue Cond2 = Node->getOperand(1);
8300 MVT CondVT = Cond1.getValueType();
8301 assert(CondVT.isVector() && "can not widen non vector type");
8302 assert(CondVT == Cond2.getValueType() && "mismatch lhs/rhs");
8303 MVT CondEVT = CondVT.getVectorElementType();
8304 MVT CondWidenVT = MVT::getVectorVT(CondEVT, NewNumElts);
8305 Cond1 = WidenVectorOp(Cond1, CondWidenVT);
8306 Cond2 = WidenVectorOp(Cond2, CondWidenVT);
8307 assert(Cond1.getValueType() == CondWidenVT &&
8308 Cond2.getValueType() == CondWidenVT && "condition not widen");
8310 SDValue Tmp1 = WidenVectorOp(Node->getOperand(2), WidenVT);
8311 SDValue Tmp2 = WidenVectorOp(Node->getOperand(3), WidenVT);
8312 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT &&
8313 "operands not widen");
8314 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Cond1, Cond2, Tmp1,
8315 Tmp2, Node->getOperand(4));
8319 // Determine widen for the operand
8320 SDValue Tmp1 = Node->getOperand(0);
8321 MVT TmpVT = Tmp1.getValueType();
8322 assert(TmpVT.isVector() && "can not widen non vector type");
8323 MVT TmpEVT = TmpVT.getVectorElementType();
8324 MVT TmpWidenVT = MVT::getVectorVT(TmpEVT, NewNumElts);
8325 Tmp1 = WidenVectorOp(Tmp1, TmpWidenVT);
8326 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), TmpWidenVT);
8327 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1, Tmp2,
8328 Node->getOperand(2));
8331 case ISD::ATOMIC_CMP_SWAP:
8332 case ISD::ATOMIC_LOAD_ADD:
8333 case ISD::ATOMIC_LOAD_SUB:
8334 case ISD::ATOMIC_LOAD_AND:
8335 case ISD::ATOMIC_LOAD_OR:
8336 case ISD::ATOMIC_LOAD_XOR:
8337 case ISD::ATOMIC_LOAD_NAND:
8338 case ISD::ATOMIC_LOAD_MIN:
8339 case ISD::ATOMIC_LOAD_MAX:
8340 case ISD::ATOMIC_LOAD_UMIN:
8341 case ISD::ATOMIC_LOAD_UMAX:
8342 case ISD::ATOMIC_SWAP: {
8343 // For now, we assume that using vectors for these operations don't make
8344 // much sense so we just split it. We return an empty result
8346 SplitVectorOp(Op, X, Y);
8351 } // end switch (Node->getOpcode())
8353 assert(Result.getNode() && "Didn't set a result!");
8355 Result = LegalizeOp(Result);
8357 AddWidenedOperand(Op, Result);
8361 // Utility function to find a legal vector type and its associated element
8362 // type from a preferred width and whose vector type must be the same size
8364 // TLI: Target lowering used to determine legal types
8365 // Width: Preferred width of element type
8366 // VVT: Vector value type whose size we must match.
8367 // Returns VecEVT and EVT - the vector type and its associated element type
8368 static void FindWidenVecType(const TargetLowering &TLI, unsigned Width, MVT VVT,
8369 MVT& EVT, MVT& VecEVT) {
8370 // We start with the preferred width, make it a power of 2 and see if
8371 // we can find a vector type of that width. If not, we reduce it by
8372 // another power of 2. If we have widen the type, a vector of bytes should
8374 assert(TLI.isTypeLegal(VVT));
8375 unsigned EWidth = Width + 1;
8378 EWidth = (1 << Log2_32(EWidth-1));
8379 EVT = MVT::getIntegerVT(EWidth);
8380 unsigned NumEVT = VVT.getSizeInBits()/EWidth;
8381 VecEVT = MVT::getVectorVT(EVT, NumEVT);
8382 } while (!TLI.isTypeLegal(VecEVT) ||
8383 VVT.getSizeInBits() != VecEVT.getSizeInBits());
8386 SDValue SelectionDAGLegalize::genWidenVectorLoads(SDValueVector& LdChain,
8396 // We assume that we have good rules to handle loading power of two loads so
8397 // we break down the operations to power of 2 loads. The strategy is to
8398 // load the largest power of 2 that we can easily transform to a legal vector
8399 // and then insert into that vector, and the cast the result into the legal
8400 // vector that we want. This avoids unnecessary stack converts.
8401 // TODO: If the Ldwidth is legal, alignment is the same as the LdWidth, and
8402 // the load is nonvolatile, we an use a wider load for the value.
8403 // Find a vector length we can load a large chunk
8406 FindWidenVecType(TLI, LdWidth, ResType, EVT, VecEVT);
8407 EVTWidth = EVT.getSizeInBits();
8409 SDValue LdOp = DAG.getLoad(EVT, dl, Chain, BasePtr, SV, SVOffset,
8410 isVolatile, Alignment);
8411 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecEVT, LdOp);
8412 LdChain.push_back(LdOp.getValue(1));
8414 // Check if we can load the element with one instruction
8415 if (LdWidth == EVTWidth) {
8416 return DAG.getNode(ISD::BIT_CONVERT, dl, ResType, VecOp);
8419 // The vector element order is endianness dependent.
8421 LdWidth -= EVTWidth;
8422 unsigned Offset = 0;
8424 while (LdWidth > 0) {
8425 unsigned Increment = EVTWidth / 8;
8426 Offset += Increment;
8427 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
8428 DAG.getIntPtrConstant(Increment));
8430 if (LdWidth < EVTWidth) {
8431 // Our current type we are using is too large, use a smaller size by
8432 // using a smaller power of 2
8433 unsigned oEVTWidth = EVTWidth;
8434 FindWidenVecType(TLI, LdWidth, ResType, EVT, VecEVT);
8435 EVTWidth = EVT.getSizeInBits();
8436 // Readjust position and vector position based on new load type
8437 Idx = Idx * (oEVTWidth/EVTWidth);
8438 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, VecEVT, VecOp);
8441 SDValue LdOp = DAG.getLoad(EVT, dl, Chain, BasePtr, SV,
8442 SVOffset+Offset, isVolatile,
8443 MinAlign(Alignment, Offset));
8444 LdChain.push_back(LdOp.getValue(1));
8445 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VecEVT, VecOp, LdOp,
8446 DAG.getIntPtrConstant(Idx++));
8448 LdWidth -= EVTWidth;
8451 return DAG.getNode(ISD::BIT_CONVERT, dl, ResType, VecOp);
8454 bool SelectionDAGLegalize::LoadWidenVectorOp(SDValue& Result,
8458 // TODO: Add support for ConcatVec and the ability to load many vector
8459 // types (e.g., v4i8). This will not work when a vector register
8460 // to memory mapping is strange (e.g., vector elements are not
8461 // stored in some sequential order).
8463 // It must be true that the widen vector type is bigger than where
8464 // we need to load from.
8465 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
8466 MVT LdVT = LD->getMemoryVT();
8467 DebugLoc dl = LD->getDebugLoc();
8468 assert(LdVT.isVector() && NVT.isVector());
8469 assert(LdVT.getVectorElementType() == NVT.getVectorElementType());
8472 SDValue Chain = LD->getChain();
8473 SDValue BasePtr = LD->getBasePtr();
8474 int SVOffset = LD->getSrcValueOffset();
8475 unsigned Alignment = LD->getAlignment();
8476 bool isVolatile = LD->isVolatile();
8477 const Value *SV = LD->getSrcValue();
8478 unsigned int LdWidth = LdVT.getSizeInBits();
8480 // Load value as a large register
8481 SDValueVector LdChain;
8482 Result = genWidenVectorLoads(LdChain, Chain, BasePtr, SV, SVOffset,
8483 Alignment, isVolatile, LdWidth, NVT, dl);
8485 if (LdChain.size() == 1) {
8490 TFOp=DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
8491 &LdChain[0], LdChain.size());
8497 void SelectionDAGLegalize::genWidenVectorStores(SDValueVector& StChain,
8507 // Breaks the stores into a series of power of 2 width stores. For any
8508 // width, we convert the vector to the vector of element size that we
8509 // want to store. This avoids requiring a stack convert.
8511 // Find a width of the element type we can store with
8512 MVT VVT = ValOp.getValueType();
8515 FindWidenVecType(TLI, StWidth, VVT, EVT, VecEVT);
8516 EVTWidth = EVT.getSizeInBits();
8518 SDValue VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, VecEVT, ValOp);
8519 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT, VecOp,
8520 DAG.getIntPtrConstant(0));
8521 SDValue StOp = DAG.getStore(Chain, dl, EOp, BasePtr, SV, SVOffset,
8522 isVolatile, Alignment);
8523 StChain.push_back(StOp);
8525 // Check if we are done
8526 if (StWidth == EVTWidth) {
8531 StWidth -= EVTWidth;
8532 unsigned Offset = 0;
8534 while (StWidth > 0) {
8535 unsigned Increment = EVTWidth / 8;
8536 Offset += Increment;
8537 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
8538 DAG.getIntPtrConstant(Increment));
8540 if (StWidth < EVTWidth) {
8541 // Our current type we are using is too large, use a smaller size by
8542 // using a smaller power of 2
8543 unsigned oEVTWidth = EVTWidth;
8544 FindWidenVecType(TLI, StWidth, VVT, EVT, VecEVT);
8545 EVTWidth = EVT.getSizeInBits();
8546 // Readjust position and vector position based on new load type
8547 Idx = Idx * (oEVTWidth/EVTWidth);
8548 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, VecEVT, VecOp);
8551 EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT, VecOp,
8552 DAG.getIntPtrConstant(Idx++));
8553 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr, SV,
8554 SVOffset + Offset, isVolatile,
8555 MinAlign(Alignment, Offset)));
8556 StWidth -= EVTWidth;
8561 SDValue SelectionDAGLegalize::StoreWidenVectorOp(StoreSDNode *ST,
8564 // TODO: It might be cleaner if we can use SplitVector and have more legal
8565 // vector types that can be stored into memory (e.g., v4xi8 can
8566 // be stored as a word). This will not work when a vector register
8567 // to memory mapping is strange (e.g., vector elements are not
8568 // stored in some sequential order).
8570 MVT StVT = ST->getMemoryVT();
8571 SDValue ValOp = ST->getValue();
8572 DebugLoc dl = ST->getDebugLoc();
8574 // Check if we have widen this node with another value
8575 std::map<SDValue, SDValue>::iterator I = WidenNodes.find(ValOp);
8576 if (I != WidenNodes.end())
8579 MVT VVT = ValOp.getValueType();
8581 // It must be true that we the widen vector type is bigger than where
8582 // we need to store.
8583 assert(StVT.isVector() && VVT.isVector());
8584 assert(StVT.bitsLT(VVT));
8585 assert(StVT.getVectorElementType() == VVT.getVectorElementType());
8588 SDValueVector StChain;
8589 genWidenVectorStores(StChain, Chain, BasePtr, ST->getSrcValue(),
8590 ST->getSrcValueOffset(), ST->getAlignment(),
8591 ST->isVolatile(), ValOp, StVT.getSizeInBits(), dl);
8592 if (StChain.size() == 1)
8595 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
8596 &StChain[0], StChain.size());
8600 // SelectionDAG::Legalize - This is the entry point for the file.
8602 void SelectionDAG::Legalize(bool TypesNeedLegalizing,
8603 CodeGenOpt::Level OptLevel) {
8604 /// run - This is the main entry point to this class.
8606 SelectionDAGLegalize(*this, TypesNeedLegalizing, OptLevel).LegalizeDAG();