1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/ADT/SmallPtrSet.h"
16 #include "llvm/ADT/SmallSet.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/CodeGen/Analysis.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineJumpTableInfo.h"
22 #include "llvm/IR/CallingConv.h"
23 #include "llvm/IR/Constants.h"
24 #include "llvm/IR/DataLayout.h"
25 #include "llvm/IR/DebugInfo.h"
26 #include "llvm/IR/DerivedTypes.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/LLVMContext.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/Target/TargetFrameLowering.h"
34 #include "llvm/Target/TargetLowering.h"
35 #include "llvm/Target/TargetMachine.h"
38 //===----------------------------------------------------------------------===//
39 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
40 /// hacks on it until the target machine can handle it. This involves
41 /// eliminating value sizes the machine cannot handle (promoting small sizes to
42 /// large sizes or splitting up large values into small values) as well as
43 /// eliminating operations the machine cannot handle.
45 /// This code also does a small amount of optimization and recognition of idioms
46 /// as part of its processing. For example, if a target does not support a
47 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
48 /// will attempt merge setcc and brc instructions into brcc's.
51 class SelectionDAGLegalize : public SelectionDAG::DAGUpdateListener {
52 const TargetMachine &TM;
53 const TargetLowering &TLI;
56 /// LegalizePosition - The iterator for walking through the node list.
57 SelectionDAG::allnodes_iterator LegalizePosition;
59 /// LegalizedNodes - The set of nodes which have already been legalized.
60 SmallPtrSet<SDNode *, 16> LegalizedNodes;
62 EVT getSetCCResultType(EVT VT) const {
63 return TLI.getSetCCResultType(*DAG.getContext(), VT);
66 // Libcall insertion helpers.
69 explicit SelectionDAGLegalize(SelectionDAG &DAG);
74 /// LegalizeOp - Legalizes the given operation.
75 void LegalizeOp(SDNode *Node);
77 SDValue OptimizeFloatStore(StoreSDNode *ST);
79 void LegalizeLoadOps(SDNode *Node);
80 void LegalizeStoreOps(SDNode *Node);
82 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
83 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
84 /// is necessary to spill the vector being inserted into to memory, perform
85 /// the insert there, and then read the result back.
86 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
87 SDValue Idx, SDLoc dl);
88 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
89 SDValue Idx, SDLoc dl);
91 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
92 /// performs the same shuffe in terms of order or result bytes, but on a type
93 /// whose vector element type is narrower than the original shuffle type.
94 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
95 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl,
96 SDValue N1, SDValue N2,
97 ArrayRef<int> Mask) const;
99 bool LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
100 bool &NeedInvert, SDLoc dl);
102 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
103 SDValue ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops,
104 unsigned NumOps, bool isSigned, SDLoc dl);
106 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
107 SDNode *Node, bool isSigned);
108 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
109 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
110 RTLIB::Libcall Call_F128,
111 RTLIB::Libcall Call_PPCF128);
112 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
113 RTLIB::Libcall Call_I8,
114 RTLIB::Libcall Call_I16,
115 RTLIB::Libcall Call_I32,
116 RTLIB::Libcall Call_I64,
117 RTLIB::Libcall Call_I128);
118 void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
119 void ExpandSinCosLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
121 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, SDLoc dl);
122 SDValue ExpandBUILD_VECTOR(SDNode *Node);
123 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
124 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
125 SmallVectorImpl<SDValue> &Results);
126 SDValue ExpandFCOPYSIGN(SDNode *Node);
127 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
129 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
131 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
134 SDValue ExpandBSWAP(SDValue Op, SDLoc dl);
135 SDValue ExpandBitCount(unsigned Opc, SDValue Op, SDLoc dl);
137 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
138 SDValue ExpandInsertToVectorThroughStack(SDValue Op);
139 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
141 SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP);
143 std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node);
145 void ExpandNode(SDNode *Node);
146 void PromoteNode(SDNode *Node);
148 void ForgetNode(SDNode *N) {
149 LegalizedNodes.erase(N);
150 if (LegalizePosition == SelectionDAG::allnodes_iterator(N))
155 // DAGUpdateListener implementation.
156 void NodeDeleted(SDNode *N, SDNode *E) override {
159 void NodeUpdated(SDNode *N) override {}
161 // Node replacement helpers
162 void ReplacedNode(SDNode *N) {
163 if (N->use_empty()) {
164 DAG.RemoveDeadNode(N);
169 void ReplaceNode(SDNode *Old, SDNode *New) {
170 DAG.ReplaceAllUsesWith(Old, New);
173 void ReplaceNode(SDValue Old, SDValue New) {
174 DAG.ReplaceAllUsesWith(Old, New);
175 ReplacedNode(Old.getNode());
177 void ReplaceNode(SDNode *Old, const SDValue *New) {
178 DAG.ReplaceAllUsesWith(Old, New);
184 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
185 /// performs the same shuffe in terms of order or result bytes, but on a type
186 /// whose vector element type is narrower than the original shuffle type.
187 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
189 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl,
190 SDValue N1, SDValue N2,
191 ArrayRef<int> Mask) const {
192 unsigned NumMaskElts = VT.getVectorNumElements();
193 unsigned NumDestElts = NVT.getVectorNumElements();
194 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
196 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
198 if (NumEltsGrowth == 1)
199 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
201 SmallVector<int, 8> NewMask;
202 for (unsigned i = 0; i != NumMaskElts; ++i) {
204 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
206 NewMask.push_back(-1);
208 NewMask.push_back(Idx * NumEltsGrowth + j);
211 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
212 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
213 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
216 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
217 : SelectionDAG::DAGUpdateListener(dag),
218 TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()),
222 void SelectionDAGLegalize::LegalizeDAG() {
223 DAG.AssignTopologicalOrder();
225 // Visit all the nodes. We start in topological order, so that we see
226 // nodes with their original operands intact. Legalization can produce
227 // new nodes which may themselves need to be legalized. Iterate until all
228 // nodes have been legalized.
230 bool AnyLegalized = false;
231 for (LegalizePosition = DAG.allnodes_end();
232 LegalizePosition != DAG.allnodes_begin(); ) {
235 SDNode *N = LegalizePosition;
236 if (LegalizedNodes.insert(N)) {
246 // Remove dead nodes now.
247 DAG.RemoveDeadNodes();
250 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
251 /// a load from the constant pool.
253 SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) {
257 // If a FP immediate is precise when represented as a float and if the
258 // target can do an extending load from float to double, we put it into
259 // the constant pool as a float, even if it's is statically typed as a
260 // double. This shrinks FP constants and canonicalizes them for targets where
261 // an FP extending load is the same cost as a normal load (such as on the x87
262 // fp stack or PPC FP unit).
263 EVT VT = CFP->getValueType(0);
264 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
266 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
267 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
268 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
273 while (SVT != MVT::f32 && SVT != MVT::f16) {
274 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
275 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) &&
276 // Only do this if the target has a native EXTLOAD instruction from
278 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
279 TLI.ShouldShrinkFPConstant(OrigVT)) {
280 Type *SType = SVT.getTypeForEVT(*DAG.getContext());
281 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
287 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
288 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
291 DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT,
293 CPIdx, MachinePointerInfo::getConstantPool(),
294 VT, false, false, Alignment);
298 DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
299 MachinePointerInfo::getConstantPool(), false, false, false,
304 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
305 static void ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
306 const TargetLowering &TLI,
307 SelectionDAGLegalize *DAGLegalize) {
308 assert(ST->getAddressingMode() == ISD::UNINDEXED &&
309 "unaligned indexed stores not implemented!");
310 SDValue Chain = ST->getChain();
311 SDValue Ptr = ST->getBasePtr();
312 SDValue Val = ST->getValue();
313 EVT VT = Val.getValueType();
314 int Alignment = ST->getAlignment();
315 unsigned AS = ST->getAddressSpace();
318 if (ST->getMemoryVT().isFloatingPoint() ||
319 ST->getMemoryVT().isVector()) {
320 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
321 if (TLI.isTypeLegal(intVT)) {
322 // Expand to a bitconvert of the value to the integer type of the
323 // same size, then a (misaligned) int store.
324 // FIXME: Does not handle truncating floating point stores!
325 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
326 Result = DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
327 ST->isVolatile(), ST->isNonTemporal(), Alignment);
328 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
331 // Do a (aligned) store to a stack slot, then copy from the stack slot
332 // to the final destination using (unaligned) integer loads and stores.
333 EVT StoredVT = ST->getMemoryVT();
335 TLI.getRegisterType(*DAG.getContext(),
336 EVT::getIntegerVT(*DAG.getContext(),
337 StoredVT.getSizeInBits()));
338 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
339 unsigned RegBytes = RegVT.getSizeInBits() / 8;
340 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
342 // Make sure the stack slot is also aligned for the register type.
343 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
345 // Perform the original store, only redirected to the stack slot.
346 SDValue Store = DAG.getTruncStore(Chain, dl,
347 Val, StackPtr, MachinePointerInfo(),
348 StoredVT, false, false, 0);
349 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy(AS));
350 SmallVector<SDValue, 8> Stores;
353 // Do all but one copies using the full register width.
354 for (unsigned i = 1; i < NumRegs; i++) {
355 // Load one integer register's worth from the stack slot.
356 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr,
357 MachinePointerInfo(),
358 false, false, false, 0);
359 // Store it to the final location. Remember the store.
360 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
361 ST->getPointerInfo().getWithOffset(Offset),
362 ST->isVolatile(), ST->isNonTemporal(),
363 MinAlign(ST->getAlignment(), Offset)));
364 // Increment the pointers.
366 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
368 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
371 // The last store may be partial. Do a truncating store. On big-endian
372 // machines this requires an extending load from the stack slot to ensure
373 // that the bits are in the right place.
374 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
375 8 * (StoredBytes - Offset));
377 // Load from the stack slot.
378 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
379 MachinePointerInfo(),
380 MemVT, false, false, 0);
382 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
384 .getWithOffset(Offset),
385 MemVT, ST->isVolatile(),
387 MinAlign(ST->getAlignment(), Offset),
389 // The order of the stores doesn't matter - say it with a TokenFactor.
390 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
391 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
394 assert(ST->getMemoryVT().isInteger() &&
395 !ST->getMemoryVT().isVector() &&
396 "Unaligned store of unknown type.");
397 // Get the half-size VT
398 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext());
399 int NumBits = NewStoredVT.getSizeInBits();
400 int IncrementSize = NumBits / 8;
402 // Divide the stored value in two parts.
403 SDValue ShiftAmount = DAG.getConstant(NumBits,
404 TLI.getShiftAmountTy(Val.getValueType()));
406 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
408 // Store the two parts
409 SDValue Store1, Store2;
410 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
411 ST->getPointerInfo(), NewStoredVT,
412 ST->isVolatile(), ST->isNonTemporal(), Alignment);
414 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
415 DAG.getConstant(IncrementSize, TLI.getPointerTy(AS)));
416 Alignment = MinAlign(Alignment, IncrementSize);
417 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
418 ST->getPointerInfo().getWithOffset(IncrementSize),
419 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(),
420 Alignment, ST->getTBAAInfo());
423 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
424 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
427 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
429 ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
430 const TargetLowering &TLI,
431 SDValue &ValResult, SDValue &ChainResult) {
432 assert(LD->getAddressingMode() == ISD::UNINDEXED &&
433 "unaligned indexed loads not implemented!");
434 SDValue Chain = LD->getChain();
435 SDValue Ptr = LD->getBasePtr();
436 EVT VT = LD->getValueType(0);
437 EVT LoadedVT = LD->getMemoryVT();
439 if (VT.isFloatingPoint() || VT.isVector()) {
440 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
441 if (TLI.isTypeLegal(intVT) && TLI.isTypeLegal(LoadedVT)) {
442 // Expand to a (misaligned) integer load of the same size,
443 // then bitconvert to floating point or vector.
444 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr,
445 LD->getMemOperand());
446 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad);
448 Result = DAG.getNode(VT.isFloatingPoint() ? ISD::FP_EXTEND :
449 ISD::ANY_EXTEND, dl, VT, Result);
456 // Copy the value to a (aligned) stack slot using (unaligned) integer
457 // loads and stores, then do a (aligned) load from the stack slot.
458 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
459 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
460 unsigned RegBytes = RegVT.getSizeInBits() / 8;
461 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
463 // Make sure the stack slot is also aligned for the register type.
464 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
466 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
467 SmallVector<SDValue, 8> Stores;
468 SDValue StackPtr = StackBase;
471 // Do all but one copies using the full register width.
472 for (unsigned i = 1; i < NumRegs; i++) {
473 // Load one integer register's worth from the original location.
474 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr,
475 LD->getPointerInfo().getWithOffset(Offset),
476 LD->isVolatile(), LD->isNonTemporal(),
478 MinAlign(LD->getAlignment(), Offset),
480 // Follow the load with a store to the stack slot. Remember the store.
481 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
482 MachinePointerInfo(), false, false, 0));
483 // Increment the pointers.
485 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
486 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
490 // The last copy may be partial. Do an extending load.
491 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
492 8 * (LoadedBytes - Offset));
493 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
494 LD->getPointerInfo().getWithOffset(Offset),
495 MemVT, LD->isVolatile(),
497 MinAlign(LD->getAlignment(), Offset),
499 // Follow the load with a store to the stack slot. Remember the store.
500 // On big-endian machines this requires a truncating store to ensure
501 // that the bits end up in the right place.
502 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
503 MachinePointerInfo(), MemVT,
506 // The order of the stores doesn't matter - say it with a TokenFactor.
507 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
509 // Finally, perform the original load only redirected to the stack slot.
510 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
511 MachinePointerInfo(), LoadedVT, false, false, 0);
513 // Callers expect a MERGE_VALUES node.
518 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
519 "Unaligned load of unsupported type.");
521 // Compute the new VT that is half the size of the old one. This is an
523 unsigned NumBits = LoadedVT.getSizeInBits();
525 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
528 unsigned Alignment = LD->getAlignment();
529 unsigned IncrementSize = NumBits / 8;
530 ISD::LoadExtType HiExtType = LD->getExtensionType();
532 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
533 if (HiExtType == ISD::NON_EXTLOAD)
534 HiExtType = ISD::ZEXTLOAD;
536 // Load the value in two parts
538 if (TLI.isLittleEndian()) {
539 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
540 NewLoadedVT, LD->isVolatile(),
541 LD->isNonTemporal(), Alignment, LD->getTBAAInfo());
542 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
543 DAG.getConstant(IncrementSize, Ptr.getValueType()));
544 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr,
545 LD->getPointerInfo().getWithOffset(IncrementSize),
546 NewLoadedVT, LD->isVolatile(),
547 LD->isNonTemporal(), MinAlign(Alignment, IncrementSize),
550 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(),
551 NewLoadedVT, LD->isVolatile(),
552 LD->isNonTemporal(), Alignment, LD->getTBAAInfo());
553 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
554 DAG.getConstant(IncrementSize, Ptr.getValueType()));
555 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
556 LD->getPointerInfo().getWithOffset(IncrementSize),
557 NewLoadedVT, LD->isVolatile(),
558 LD->isNonTemporal(), MinAlign(Alignment, IncrementSize),
562 // aggregate the two parts
563 SDValue ShiftAmount = DAG.getConstant(NumBits,
564 TLI.getShiftAmountTy(Hi.getValueType()));
565 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
566 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
568 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
575 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
576 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
577 /// is necessary to spill the vector being inserted into to memory, perform
578 /// the insert there, and then read the result back.
579 SDValue SelectionDAGLegalize::
580 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
586 // If the target doesn't support this, we have to spill the input vector
587 // to a temporary stack slot, update the element, then reload it. This is
588 // badness. We could also load the value into a vector register (either
589 // with a "move to register" or "extload into register" instruction, then
590 // permute it into place, if the idx is a constant and if the idx is
591 // supported by the target.
592 EVT VT = Tmp1.getValueType();
593 EVT EltVT = VT.getVectorElementType();
594 EVT IdxVT = Tmp3.getValueType();
595 EVT PtrVT = TLI.getPointerTy();
596 SDValue StackPtr = DAG.CreateStackTemporary(VT);
598 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
601 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
602 MachinePointerInfo::getFixedStack(SPFI),
605 // Truncate or zero extend offset to target pointer type.
606 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
607 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
608 // Add the offset to the index.
609 unsigned EltSize = EltVT.getSizeInBits()/8;
610 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
611 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
612 // Store the scalar value.
613 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT,
615 // Load the updated vector.
616 return DAG.getLoad(VT, dl, Ch, StackPtr,
617 MachinePointerInfo::getFixedStack(SPFI), false, false,
622 SDValue SelectionDAGLegalize::
623 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, SDLoc dl) {
624 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
625 // SCALAR_TO_VECTOR requires that the type of the value being inserted
626 // match the element type of the vector being created, except for
627 // integers in which case the inserted value can be over width.
628 EVT EltVT = Vec.getValueType().getVectorElementType();
629 if (Val.getValueType() == EltVT ||
630 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
631 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
632 Vec.getValueType(), Val);
634 unsigned NumElts = Vec.getValueType().getVectorNumElements();
635 // We generate a shuffle of InVec and ScVec, so the shuffle mask
636 // should be 0,1,2,3,4,5... with the appropriate element replaced with
638 SmallVector<int, 8> ShufOps;
639 for (unsigned i = 0; i != NumElts; ++i)
640 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
642 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
646 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
649 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
650 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
651 // FIXME: We shouldn't do this for TargetConstantFP's.
652 // FIXME: move this to the DAG Combiner! Note that we can't regress due
653 // to phase ordering between legalized code and the dag combiner. This
654 // probably means that we need to integrate dag combiner and legalizer
656 // We generally can't do this one for long doubles.
657 SDValue Chain = ST->getChain();
658 SDValue Ptr = ST->getBasePtr();
659 unsigned Alignment = ST->getAlignment();
660 bool isVolatile = ST->isVolatile();
661 bool isNonTemporal = ST->isNonTemporal();
662 const MDNode *TBAAInfo = ST->getTBAAInfo();
664 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
665 if (CFP->getValueType(0) == MVT::f32 &&
666 TLI.isTypeLegal(MVT::i32)) {
667 SDValue Con = DAG.getConstant(CFP->getValueAPF().
668 bitcastToAPInt().zextOrTrunc(32),
670 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
671 isVolatile, isNonTemporal, Alignment, TBAAInfo);
674 if (CFP->getValueType(0) == MVT::f64) {
675 // If this target supports 64-bit registers, do a single 64-bit store.
676 if (TLI.isTypeLegal(MVT::i64)) {
677 SDValue Con = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
678 zextOrTrunc(64), MVT::i64);
679 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
680 isVolatile, isNonTemporal, Alignment, TBAAInfo);
683 if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) {
684 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
685 // stores. If the target supports neither 32- nor 64-bits, this
686 // xform is certainly not worth it.
687 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
688 SDValue Lo = DAG.getConstant(IntVal.trunc(32), MVT::i32);
689 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
690 if (TLI.isBigEndian()) std::swap(Lo, Hi);
692 Lo = DAG.getStore(Chain, dl, Lo, Ptr, ST->getPointerInfo(), isVolatile,
693 isNonTemporal, Alignment, TBAAInfo);
694 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
695 DAG.getConstant(4, Ptr.getValueType()));
696 Hi = DAG.getStore(Chain, dl, Hi, Ptr,
697 ST->getPointerInfo().getWithOffset(4),
698 isVolatile, isNonTemporal, MinAlign(Alignment, 4U),
701 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
705 return SDValue(nullptr, 0);
708 void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
709 StoreSDNode *ST = cast<StoreSDNode>(Node);
710 SDValue Chain = ST->getChain();
711 SDValue Ptr = ST->getBasePtr();
714 unsigned Alignment = ST->getAlignment();
715 bool isVolatile = ST->isVolatile();
716 bool isNonTemporal = ST->isNonTemporal();
717 const MDNode *TBAAInfo = ST->getTBAAInfo();
719 if (!ST->isTruncatingStore()) {
720 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
721 ReplaceNode(ST, OptStore);
726 SDValue Value = ST->getValue();
727 MVT VT = Value.getSimpleValueType();
728 switch (TLI.getOperationAction(ISD::STORE, VT)) {
729 default: llvm_unreachable("This action is not supported yet!");
730 case TargetLowering::Legal: {
731 // If this is an unaligned store and the target doesn't support it,
733 unsigned AS = ST->getAddressSpace();
734 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT(), AS)) {
735 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
736 unsigned ABIAlignment= TLI.getDataLayout()->getABITypeAlignment(Ty);
737 if (ST->getAlignment() < ABIAlignment)
738 ExpandUnalignedStore(cast<StoreSDNode>(Node),
743 case TargetLowering::Custom: {
744 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
746 ReplaceNode(SDValue(Node, 0), Res);
749 case TargetLowering::Promote: {
750 MVT NVT = TLI.getTypeToPromoteTo(ISD::STORE, VT);
751 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
752 "Can only promote stores to same size type");
753 Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value);
755 DAG.getStore(Chain, dl, Value, Ptr,
756 ST->getPointerInfo(), isVolatile,
757 isNonTemporal, Alignment, TBAAInfo);
758 ReplaceNode(SDValue(Node, 0), Result);
765 SDValue Value = ST->getValue();
767 EVT StVT = ST->getMemoryVT();
768 unsigned StWidth = StVT.getSizeInBits();
770 if (StWidth != StVT.getStoreSizeInBits()) {
771 // Promote to a byte-sized store with upper bits zero if not
772 // storing an integral number of bytes. For example, promote
773 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
774 EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
775 StVT.getStoreSizeInBits());
776 Value = DAG.getZeroExtendInReg(Value, dl, StVT);
778 DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
779 NVT, isVolatile, isNonTemporal, Alignment,
781 ReplaceNode(SDValue(Node, 0), Result);
782 } else if (StWidth & (StWidth - 1)) {
783 // If not storing a power-of-2 number of bits, expand as two stores.
784 assert(!StVT.isVector() && "Unsupported truncstore!");
785 unsigned RoundWidth = 1 << Log2_32(StWidth);
786 assert(RoundWidth < StWidth);
787 unsigned ExtraWidth = StWidth - RoundWidth;
788 assert(ExtraWidth < RoundWidth);
789 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
790 "Store size not an integral number of bytes!");
791 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
792 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
794 unsigned IncrementSize;
796 if (TLI.isLittleEndian()) {
797 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
798 // Store the bottom RoundWidth bits.
799 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
801 isVolatile, isNonTemporal, Alignment,
804 // Store the remaining ExtraWidth bits.
805 IncrementSize = RoundWidth / 8;
806 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
807 DAG.getConstant(IncrementSize, Ptr.getValueType()));
808 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
809 DAG.getConstant(RoundWidth,
810 TLI.getShiftAmountTy(Value.getValueType())));
811 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr,
812 ST->getPointerInfo().getWithOffset(IncrementSize),
813 ExtraVT, isVolatile, isNonTemporal,
814 MinAlign(Alignment, IncrementSize), TBAAInfo);
816 // Big endian - avoid unaligned stores.
817 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
818 // Store the top RoundWidth bits.
819 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
820 DAG.getConstant(ExtraWidth,
821 TLI.getShiftAmountTy(Value.getValueType())));
822 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, ST->getPointerInfo(),
823 RoundVT, isVolatile, isNonTemporal, Alignment,
826 // Store the remaining ExtraWidth bits.
827 IncrementSize = RoundWidth / 8;
828 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
829 DAG.getConstant(IncrementSize, Ptr.getValueType()));
830 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr,
831 ST->getPointerInfo().getWithOffset(IncrementSize),
832 ExtraVT, isVolatile, isNonTemporal,
833 MinAlign(Alignment, IncrementSize), TBAAInfo);
836 // The order of the stores doesn't matter.
837 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
838 ReplaceNode(SDValue(Node, 0), Result);
840 switch (TLI.getTruncStoreAction(ST->getValue().getSimpleValueType(),
841 StVT.getSimpleVT())) {
842 default: llvm_unreachable("This action is not supported yet!");
843 case TargetLowering::Legal: {
844 unsigned AS = ST->getAddressSpace();
845 // If this is an unaligned store and the target doesn't support it,
847 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT(), AS)) {
848 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
849 unsigned ABIAlignment= TLI.getDataLayout()->getABITypeAlignment(Ty);
850 if (ST->getAlignment() < ABIAlignment)
851 ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this);
855 case TargetLowering::Custom: {
856 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
858 ReplaceNode(SDValue(Node, 0), Res);
861 case TargetLowering::Expand:
862 assert(!StVT.isVector() &&
863 "Vector Stores are handled in LegalizeVectorOps");
865 // TRUNCSTORE:i16 i32 -> STORE i16
866 assert(TLI.isTypeLegal(StVT) &&
867 "Do not know how to expand this store!");
868 Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value);
870 DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
871 isVolatile, isNonTemporal, Alignment, TBAAInfo);
872 ReplaceNode(SDValue(Node, 0), Result);
879 void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
880 LoadSDNode *LD = cast<LoadSDNode>(Node);
881 SDValue Chain = LD->getChain(); // The chain.
882 SDValue Ptr = LD->getBasePtr(); // The base pointer.
883 SDValue Value; // The value returned by the load op.
886 ISD::LoadExtType ExtType = LD->getExtensionType();
887 if (ExtType == ISD::NON_EXTLOAD) {
888 MVT VT = Node->getSimpleValueType(0);
889 SDValue RVal = SDValue(Node, 0);
890 SDValue RChain = SDValue(Node, 1);
892 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
893 default: llvm_unreachable("This action is not supported yet!");
894 case TargetLowering::Legal: {
895 unsigned AS = LD->getAddressSpace();
896 // If this is an unaligned load and the target doesn't support it,
898 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT(), AS)) {
899 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
900 unsigned ABIAlignment =
901 TLI.getDataLayout()->getABITypeAlignment(Ty);
902 if (LD->getAlignment() < ABIAlignment){
903 ExpandUnalignedLoad(cast<LoadSDNode>(Node), DAG, TLI, RVal, RChain);
908 case TargetLowering::Custom: {
909 SDValue Res = TLI.LowerOperation(RVal, DAG);
912 RChain = Res.getValue(1);
916 case TargetLowering::Promote: {
917 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
918 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
919 "Can only promote loads to same size type");
921 SDValue Res = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getMemOperand());
922 RVal = DAG.getNode(ISD::BITCAST, dl, VT, Res);
923 RChain = Res.getValue(1);
927 if (RChain.getNode() != Node) {
928 assert(RVal.getNode() != Node && "Load must be completely replaced");
929 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), RVal);
930 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), RChain);
936 EVT SrcVT = LD->getMemoryVT();
937 unsigned SrcWidth = SrcVT.getSizeInBits();
938 unsigned Alignment = LD->getAlignment();
939 bool isVolatile = LD->isVolatile();
940 bool isNonTemporal = LD->isNonTemporal();
941 const MDNode *TBAAInfo = LD->getTBAAInfo();
943 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
944 // Some targets pretend to have an i1 loading operation, and actually
945 // load an i8. This trick is correct for ZEXTLOAD because the top 7
946 // bits are guaranteed to be zero; it helps the optimizers understand
947 // that these bits are zero. It is also useful for EXTLOAD, since it
948 // tells the optimizers that those bits are undefined. It would be
949 // nice to have an effective generic way of getting these benefits...
950 // Until such a way is found, don't insist on promoting i1 here.
952 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
953 // Promote to a byte-sized load if not loading an integral number of
954 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
955 unsigned NewWidth = SrcVT.getStoreSizeInBits();
956 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
959 // The extra bits are guaranteed to be zero, since we stored them that
960 // way. A zext load from NVT thus automatically gives zext from SrcVT.
962 ISD::LoadExtType NewExtType =
963 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
966 DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
967 Chain, Ptr, LD->getPointerInfo(),
968 NVT, isVolatile, isNonTemporal, Alignment, TBAAInfo);
970 Ch = Result.getValue(1); // The chain.
972 if (ExtType == ISD::SEXTLOAD)
973 // Having the top bits zero doesn't help when sign extending.
974 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
975 Result.getValueType(),
976 Result, DAG.getValueType(SrcVT));
977 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
978 // All the top bits are guaranteed to be zero - inform the optimizers.
979 Result = DAG.getNode(ISD::AssertZext, dl,
980 Result.getValueType(), Result,
981 DAG.getValueType(SrcVT));
985 } else if (SrcWidth & (SrcWidth - 1)) {
986 // If not loading a power-of-2 number of bits, expand as two loads.
987 assert(!SrcVT.isVector() && "Unsupported extload!");
988 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
989 assert(RoundWidth < SrcWidth);
990 unsigned ExtraWidth = SrcWidth - RoundWidth;
991 assert(ExtraWidth < RoundWidth);
992 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
993 "Load size not an integral number of bytes!");
994 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
995 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
997 unsigned IncrementSize;
999 if (TLI.isLittleEndian()) {
1000 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1001 // Load the bottom RoundWidth bits.
1002 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0),
1004 LD->getPointerInfo(), RoundVT, isVolatile,
1005 isNonTemporal, Alignment, TBAAInfo);
1007 // Load the remaining ExtraWidth bits.
1008 IncrementSize = RoundWidth / 8;
1009 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1010 DAG.getConstant(IncrementSize, Ptr.getValueType()));
1011 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
1012 LD->getPointerInfo().getWithOffset(IncrementSize),
1013 ExtraVT, isVolatile, isNonTemporal,
1014 MinAlign(Alignment, IncrementSize), TBAAInfo);
1016 // Build a factor node to remember that this load is independent of
1018 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1021 // Move the top bits to the right place.
1022 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1023 DAG.getConstant(RoundWidth,
1024 TLI.getShiftAmountTy(Hi.getValueType())));
1026 // Join the hi and lo parts.
1027 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1029 // Big endian - avoid unaligned loads.
1030 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1031 // Load the top RoundWidth bits.
1032 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
1033 LD->getPointerInfo(), RoundVT, isVolatile,
1034 isNonTemporal, Alignment, TBAAInfo);
1036 // Load the remaining ExtraWidth bits.
1037 IncrementSize = RoundWidth / 8;
1038 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1039 DAG.getConstant(IncrementSize, Ptr.getValueType()));
1040 Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
1041 dl, Node->getValueType(0), Chain, Ptr,
1042 LD->getPointerInfo().getWithOffset(IncrementSize),
1043 ExtraVT, isVolatile, isNonTemporal,
1044 MinAlign(Alignment, IncrementSize), TBAAInfo);
1046 // Build a factor node to remember that this load is independent of
1048 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1051 // Move the top bits to the right place.
1052 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1053 DAG.getConstant(ExtraWidth,
1054 TLI.getShiftAmountTy(Hi.getValueType())));
1056 // Join the hi and lo parts.
1057 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1062 bool isCustom = false;
1063 switch (TLI.getLoadExtAction(ExtType, SrcVT.getSimpleVT())) {
1064 default: llvm_unreachable("This action is not supported yet!");
1065 case TargetLowering::Custom:
1068 case TargetLowering::Legal: {
1069 Value = SDValue(Node, 0);
1070 Chain = SDValue(Node, 1);
1073 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1074 if (Res.getNode()) {
1076 Chain = Res.getValue(1);
1079 // If this is an unaligned load and the target doesn't support
1081 EVT MemVT = LD->getMemoryVT();
1082 unsigned AS = LD->getAddressSpace();
1083 if (!TLI.allowsUnalignedMemoryAccesses(MemVT, AS)) {
1085 LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1086 unsigned ABIAlignment =
1087 TLI.getDataLayout()->getABITypeAlignment(Ty);
1088 if (LD->getAlignment() < ABIAlignment){
1089 ExpandUnalignedLoad(cast<LoadSDNode>(Node),
1090 DAG, TLI, Value, Chain);
1096 case TargetLowering::Expand:
1097 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) &&
1098 TLI.isTypeLegal(SrcVT)) {
1099 SDValue Load = DAG.getLoad(SrcVT, dl, Chain, Ptr,
1100 LD->getMemOperand());
1104 ExtendOp = (SrcVT.isFloatingPoint() ?
1105 ISD::FP_EXTEND : ISD::ANY_EXTEND);
1107 case ISD::SEXTLOAD: ExtendOp = ISD::SIGN_EXTEND; break;
1108 case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break;
1109 default: llvm_unreachable("Unexpected extend load type!");
1111 Value = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
1112 Chain = Load.getValue(1);
1116 assert(!SrcVT.isVector() &&
1117 "Vector Loads are handled in LegalizeVectorOps");
1119 // FIXME: This does not work for vectors on most targets. Sign-
1120 // and zero-extend operations are currently folded into extending
1121 // loads, whether they are legal or not, and then we end up here
1122 // without any support for legalizing them.
1123 assert(ExtType != ISD::EXTLOAD &&
1124 "EXTLOAD should always be supported!");
1125 // Turn the unsupported load into an EXTLOAD followed by an
1126 // explicit zero/sign extend inreg.
1127 SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl,
1128 Node->getValueType(0),
1130 LD->getMemOperand());
1132 if (ExtType == ISD::SEXTLOAD)
1133 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1134 Result.getValueType(),
1135 Result, DAG.getValueType(SrcVT));
1137 ValRes = DAG.getZeroExtendInReg(Result, dl,
1138 SrcVT.getScalarType());
1140 Chain = Result.getValue(1);
1145 // Since loads produce two values, make sure to remember that we legalized
1147 if (Chain.getNode() != Node) {
1148 assert(Value.getNode() != Node && "Load must be completely replaced");
1149 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Value);
1150 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
1155 /// LegalizeOp - Return a legal replacement for the given operation, with
1156 /// all legal operands.
1157 void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
1158 if (Node->getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
1161 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1162 assert(TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) ==
1163 TargetLowering::TypeLegal &&
1164 "Unexpected illegal type!");
1166 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1167 assert((TLI.getTypeAction(*DAG.getContext(),
1168 Node->getOperand(i).getValueType()) ==
1169 TargetLowering::TypeLegal ||
1170 Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
1171 "Unexpected illegal type!");
1173 // Figure out the correct action; the way to query this varies by opcode
1174 TargetLowering::LegalizeAction Action = TargetLowering::Legal;
1175 bool SimpleFinishLegalizing = true;
1176 switch (Node->getOpcode()) {
1177 case ISD::INTRINSIC_W_CHAIN:
1178 case ISD::INTRINSIC_WO_CHAIN:
1179 case ISD::INTRINSIC_VOID:
1180 case ISD::STACKSAVE:
1181 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1184 Action = TLI.getOperationAction(Node->getOpcode(),
1185 Node->getValueType(0));
1186 if (Action != TargetLowering::Promote)
1187 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1189 case ISD::SINT_TO_FP:
1190 case ISD::UINT_TO_FP:
1191 case ISD::EXTRACT_VECTOR_ELT:
1192 Action = TLI.getOperationAction(Node->getOpcode(),
1193 Node->getOperand(0).getValueType());
1195 case ISD::FP_ROUND_INREG:
1196 case ISD::SIGN_EXTEND_INREG: {
1197 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
1198 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
1201 case ISD::ATOMIC_STORE: {
1202 Action = TLI.getOperationAction(Node->getOpcode(),
1203 Node->getOperand(2).getValueType());
1206 case ISD::SELECT_CC:
1209 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
1210 Node->getOpcode() == ISD::SETCC ? 2 : 1;
1211 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
1212 MVT OpVT = Node->getOperand(CompareOperand).getSimpleValueType();
1213 ISD::CondCode CCCode =
1214 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
1215 Action = TLI.getCondCodeAction(CCCode, OpVT);
1216 if (Action == TargetLowering::Legal) {
1217 if (Node->getOpcode() == ISD::SELECT_CC)
1218 Action = TLI.getOperationAction(Node->getOpcode(),
1219 Node->getValueType(0));
1221 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
1227 // FIXME: Model these properly. LOAD and STORE are complicated, and
1228 // STORE expects the unlegalized operand in some cases.
1229 SimpleFinishLegalizing = false;
1231 case ISD::CALLSEQ_START:
1232 case ISD::CALLSEQ_END:
1233 // FIXME: This shouldn't be necessary. These nodes have special properties
1234 // dealing with the recursive nature of legalization. Removing this
1235 // special case should be done as part of making LegalizeDAG non-recursive.
1236 SimpleFinishLegalizing = false;
1238 case ISD::EXTRACT_ELEMENT:
1239 case ISD::FLT_ROUNDS_:
1247 case ISD::MERGE_VALUES:
1248 case ISD::EH_RETURN:
1249 case ISD::FRAME_TO_ARGS_OFFSET:
1250 case ISD::EH_SJLJ_SETJMP:
1251 case ISD::EH_SJLJ_LONGJMP:
1252 // These operations lie about being legal: when they claim to be legal,
1253 // they should actually be expanded.
1254 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1255 if (Action == TargetLowering::Legal)
1256 Action = TargetLowering::Expand;
1258 case ISD::INIT_TRAMPOLINE:
1259 case ISD::ADJUST_TRAMPOLINE:
1260 case ISD::FRAMEADDR:
1261 case ISD::RETURNADDR:
1262 // These operations lie about being legal: when they claim to be legal,
1263 // they should actually be custom-lowered.
1264 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1265 if (Action == TargetLowering::Legal)
1266 Action = TargetLowering::Custom;
1268 case ISD::READ_REGISTER:
1269 case ISD::WRITE_REGISTER:
1270 // Named register is legal in the DAG, but blocked by register name
1271 // selection if not implemented by target (to chose the correct register)
1272 // They'll be converted to Copy(To/From)Reg.
1273 Action = TargetLowering::Legal;
1275 case ISD::DEBUGTRAP:
1276 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1277 if (Action == TargetLowering::Expand) {
1278 // replace ISD::DEBUGTRAP with ISD::TRAP
1280 NewVal = DAG.getNode(ISD::TRAP, SDLoc(Node), Node->getVTList(),
1281 Node->getOperand(0));
1282 ReplaceNode(Node, NewVal.getNode());
1283 LegalizeOp(NewVal.getNode());
1289 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1290 Action = TargetLowering::Legal;
1292 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1297 if (SimpleFinishLegalizing) {
1298 SDNode *NewNode = Node;
1299 switch (Node->getOpcode()) {
1306 // Legalizing shifts/rotates requires adjusting the shift amount
1307 // to the appropriate width.
1308 if (!Node->getOperand(1).getValueType().isVector()) {
1310 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1311 Node->getOperand(1));
1312 HandleSDNode Handle(SAO);
1313 LegalizeOp(SAO.getNode());
1314 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1318 case ISD::SRL_PARTS:
1319 case ISD::SRA_PARTS:
1320 case ISD::SHL_PARTS:
1321 // Legalizing shifts/rotates requires adjusting the shift amount
1322 // to the appropriate width.
1323 if (!Node->getOperand(2).getValueType().isVector()) {
1325 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1326 Node->getOperand(2));
1327 HandleSDNode Handle(SAO);
1328 LegalizeOp(SAO.getNode());
1329 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1330 Node->getOperand(1),
1336 if (NewNode != Node) {
1337 DAG.ReplaceAllUsesWith(Node, NewNode);
1338 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1339 DAG.TransferDbgValues(SDValue(Node, i), SDValue(NewNode, i));
1344 case TargetLowering::Legal:
1346 case TargetLowering::Custom: {
1347 // FIXME: The handling for custom lowering with multiple results is
1349 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1350 if (Res.getNode()) {
1351 SmallVector<SDValue, 8> ResultVals;
1352 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
1354 ResultVals.push_back(Res);
1356 ResultVals.push_back(Res.getValue(i));
1358 if (Res.getNode() != Node || Res.getResNo() != 0) {
1359 DAG.ReplaceAllUsesWith(Node, ResultVals.data());
1360 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1361 DAG.TransferDbgValues(SDValue(Node, i), ResultVals[i]);
1368 case TargetLowering::Expand:
1371 case TargetLowering::Promote:
1377 switch (Node->getOpcode()) {
1384 llvm_unreachable("Do not know how to legalize this operator!");
1386 case ISD::CALLSEQ_START:
1387 case ISD::CALLSEQ_END:
1390 return LegalizeLoadOps(Node);
1393 return LegalizeStoreOps(Node);
1398 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1399 SDValue Vec = Op.getOperand(0);
1400 SDValue Idx = Op.getOperand(1);
1403 // Before we generate a new store to a temporary stack slot, see if there is
1404 // already one that we can use. There often is because when we scalarize
1405 // vector operations (using SelectionDAG::UnrollVectorOp for example) a whole
1406 // series of EXTRACT_VECTOR_ELT nodes are generated, one for each element in
1407 // the vector. If all are expanded here, we don't want one store per vector
1409 SDValue StackPtr, Ch;
1410 for (SDNode::use_iterator UI = Vec.getNode()->use_begin(),
1411 UE = Vec.getNode()->use_end(); UI != UE; ++UI) {
1413 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(User)) {
1414 if (ST->isIndexed() || ST->isTruncatingStore() ||
1415 ST->getValue() != Vec)
1418 // Make sure that nothing else could have stored into the destination of
1420 if (!ST->getChain().reachesChainWithoutSideEffects(DAG.getEntryNode()))
1423 StackPtr = ST->getBasePtr();
1424 Ch = SDValue(ST, 0);
1429 if (!Ch.getNode()) {
1430 // Store the value to a temporary stack slot, then LOAD the returned part.
1431 StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1432 Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1433 MachinePointerInfo(), false, false, 0);
1436 // Add the offset to the index.
1438 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1439 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1440 DAG.getConstant(EltSize, Idx.getValueType()));
1442 Idx = DAG.getZExtOrTrunc(Idx, dl, TLI.getPointerTy());
1443 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1445 if (Op.getValueType().isVector())
1446 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,MachinePointerInfo(),
1447 false, false, false, 0);
1448 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
1449 MachinePointerInfo(),
1450 Vec.getValueType().getVectorElementType(),
1454 SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
1455 assert(Op.getValueType().isVector() && "Non-vector insert subvector!");
1457 SDValue Vec = Op.getOperand(0);
1458 SDValue Part = Op.getOperand(1);
1459 SDValue Idx = Op.getOperand(2);
1462 // Store the value to a temporary stack slot, then LOAD the returned part.
1464 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1465 int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1466 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1468 // First store the whole vector.
1469 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo,
1472 // Then store the inserted part.
1474 // Add the offset to the index.
1476 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1478 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1479 DAG.getConstant(EltSize, Idx.getValueType()));
1480 Idx = DAG.getZExtOrTrunc(Idx, dl, TLI.getPointerTy());
1482 SDValue SubStackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
1485 // Store the subvector.
1486 Ch = DAG.getStore(DAG.getEntryNode(), dl, Part, SubStackPtr,
1487 MachinePointerInfo(), false, false, 0);
1489 // Finally, load the updated vector.
1490 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo,
1491 false, false, false, 0);
1494 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1495 // We can't handle this case efficiently. Allocate a sufficiently
1496 // aligned object on the stack, store each element into it, then load
1497 // the result as a vector.
1498 // Create the stack frame object.
1499 EVT VT = Node->getValueType(0);
1500 EVT EltVT = VT.getVectorElementType();
1502 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1503 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1504 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1506 // Emit a store of each element to the stack slot.
1507 SmallVector<SDValue, 8> Stores;
1508 unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1509 // Store (in the right endianness) the elements to memory.
1510 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1511 // Ignore undef elements.
1512 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1514 unsigned Offset = TypeByteSize*i;
1516 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
1517 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1519 // If the destination vector element type is narrower than the source
1520 // element type, only store the bits necessary.
1521 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1522 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1523 Node->getOperand(i), Idx,
1524 PtrInfo.getWithOffset(Offset),
1525 EltVT, false, false, 0));
1527 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
1528 Node->getOperand(i), Idx,
1529 PtrInfo.getWithOffset(Offset),
1534 if (!Stores.empty()) // Not all undef elements?
1535 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
1537 StoreChain = DAG.getEntryNode();
1539 // Result is a load from the stack slot.
1540 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo,
1541 false, false, false, 0);
1544 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
1546 SDValue Tmp1 = Node->getOperand(0);
1547 SDValue Tmp2 = Node->getOperand(1);
1549 // Get the sign bit of the RHS. First obtain a value that has the same
1550 // sign as the sign bit, i.e. negative if and only if the sign bit is 1.
1552 EVT FloatVT = Tmp2.getValueType();
1553 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits());
1554 if (TLI.isTypeLegal(IVT)) {
1555 // Convert to an integer with the same sign bit.
1556 SignBit = DAG.getNode(ISD::BITCAST, dl, IVT, Tmp2);
1558 // Store the float to memory, then load the sign part out as an integer.
1559 MVT LoadTy = TLI.getPointerTy();
1560 // First create a temporary that is aligned for both the load and store.
1561 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1562 // Then store the float to it.
1564 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, MachinePointerInfo(),
1566 if (TLI.isBigEndian()) {
1567 assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1568 // Load out a legal integer with the same sign bit as the float.
1569 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, MachinePointerInfo(),
1570 false, false, false, 0);
1571 } else { // Little endian
1572 SDValue LoadPtr = StackPtr;
1573 // The float may be wider than the integer we are going to load. Advance
1574 // the pointer so that the loaded integer will contain the sign bit.
1575 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits();
1576 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8;
1577 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(), LoadPtr,
1578 DAG.getConstant(ByteOffset, LoadPtr.getValueType()));
1579 // Load a legal integer containing the sign bit.
1580 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(),
1581 false, false, false, 0);
1582 // Move the sign bit to the top bit of the loaded integer.
1583 unsigned BitShift = LoadTy.getSizeInBits() -
1584 (FloatVT.getSizeInBits() - 8 * ByteOffset);
1585 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?");
1587 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit,
1588 DAG.getConstant(BitShift,
1589 TLI.getShiftAmountTy(SignBit.getValueType())));
1592 // Now get the sign bit proper, by seeing whether the value is negative.
1593 SignBit = DAG.getSetCC(dl, getSetCCResultType(SignBit.getValueType()),
1594 SignBit, DAG.getConstant(0, SignBit.getValueType()),
1596 // Get the absolute value of the result.
1597 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1598 // Select between the nabs and abs value based on the sign bit of
1600 return DAG.getSelect(dl, AbsVal.getValueType(), SignBit,
1601 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1605 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1606 SmallVectorImpl<SDValue> &Results) {
1607 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1608 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1609 " not tell us which reg is the stack pointer!");
1611 EVT VT = Node->getValueType(0);
1612 SDValue Tmp1 = SDValue(Node, 0);
1613 SDValue Tmp2 = SDValue(Node, 1);
1614 SDValue Tmp3 = Node->getOperand(2);
1615 SDValue Chain = Tmp1.getOperand(0);
1617 // Chain the dynamic stack allocation so that it doesn't modify the stack
1618 // pointer when other instructions are using the stack.
1619 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
1622 SDValue Size = Tmp2.getOperand(1);
1623 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1624 Chain = SP.getValue(1);
1625 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1626 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
1627 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1628 if (Align > StackAlign)
1629 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
1630 DAG.getConstant(-(uint64_t)Align, VT));
1631 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1633 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1634 DAG.getIntPtrConstant(0, true), SDValue(),
1637 Results.push_back(Tmp1);
1638 Results.push_back(Tmp2);
1641 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
1642 /// condition code CC on the current target.
1644 /// If the SETCC has been legalized using AND / OR, then the legalized node
1645 /// will be stored in LHS. RHS and CC will be set to SDValue(). NeedInvert
1646 /// will be set to false.
1648 /// If the SETCC has been legalized by using getSetCCSwappedOperands(),
1649 /// then the values of LHS and RHS will be swapped, CC will be set to the
1650 /// new condition, and NeedInvert will be set to false.
1652 /// If the SETCC has been legalized using the inverse condcode, then LHS and
1653 /// RHS will be unchanged, CC will set to the inverted condcode, and NeedInvert
1654 /// will be set to true. The caller must invert the result of the SETCC with
1655 /// SelectionDAG::getLogicalNOT() or take equivalent action to swap the effect
1656 /// of a true/false result.
1658 /// \returns true if the SetCC has been legalized, false if it hasn't.
1659 bool SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1660 SDValue &LHS, SDValue &RHS,
1664 MVT OpVT = LHS.getSimpleValueType();
1665 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1667 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1668 default: llvm_unreachable("Unknown condition code action!");
1669 case TargetLowering::Legal:
1672 case TargetLowering::Expand: {
1673 ISD::CondCode InvCC = ISD::getSetCCSwappedOperands(CCCode);
1674 if (TLI.isCondCodeLegal(InvCC, OpVT)) {
1675 std::swap(LHS, RHS);
1676 CC = DAG.getCondCode(InvCC);
1679 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1682 default: llvm_unreachable("Don't know how to expand this condition!");
1684 assert(TLI.getCondCodeAction(ISD::SETOEQ, OpVT)
1685 == TargetLowering::Legal
1686 && "If SETO is expanded, SETOEQ must be legal!");
1687 CC1 = ISD::SETOEQ; CC2 = ISD::SETOEQ; Opc = ISD::AND; break;
1689 assert(TLI.getCondCodeAction(ISD::SETUNE, OpVT)
1690 == TargetLowering::Legal
1691 && "If SETUO is expanded, SETUNE must be legal!");
1692 CC1 = ISD::SETUNE; CC2 = ISD::SETUNE; Opc = ISD::OR; break;
1705 // If we are floating point, assign and break, otherwise fall through.
1706 if (!OpVT.isInteger()) {
1707 // We can use the 4th bit to tell if we are the unordered
1708 // or ordered version of the opcode.
1709 CC2 = ((unsigned)CCCode & 0x8U) ? ISD::SETUO : ISD::SETO;
1710 Opc = ((unsigned)CCCode & 0x8U) ? ISD::OR : ISD::AND;
1711 CC1 = (ISD::CondCode)(((int)CCCode & 0x7) | 0x10);
1714 // Fallthrough if we are unsigned integer.
1719 // We only support using the inverted operation, which is computed above
1720 // and not a different manner of supporting expanding these cases.
1721 llvm_unreachable("Don't know how to expand this condition!");
1724 // Try inverting the result of the inverse condition.
1725 InvCC = CCCode == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ;
1726 if (TLI.isCondCodeLegal(InvCC, OpVT)) {
1727 CC = DAG.getCondCode(InvCC);
1731 // If inverting the condition didn't work then we have no means to expand
1733 llvm_unreachable("Don't know how to expand this condition!");
1736 SDValue SetCC1, SetCC2;
1737 if (CCCode != ISD::SETO && CCCode != ISD::SETUO) {
1738 // If we aren't the ordered or unorder operation,
1739 // then the pattern is (LHS CC1 RHS) Opc (LHS CC2 RHS).
1740 SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1741 SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1743 // Otherwise, the pattern is (LHS CC1 LHS) Opc (RHS CC2 RHS)
1744 SetCC1 = DAG.getSetCC(dl, VT, LHS, LHS, CC1);
1745 SetCC2 = DAG.getSetCC(dl, VT, RHS, RHS, CC2);
1747 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1756 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
1757 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1758 /// a load from the stack slot to DestVT, extending it if needed.
1759 /// The resultant code need not be legal.
1760 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
1764 // Create the stack frame object.
1766 TLI.getDataLayout()->getPrefTypeAlignment(SrcOp.getValueType().
1767 getTypeForEVT(*DAG.getContext()));
1768 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1770 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1771 int SPFI = StackPtrFI->getIndex();
1772 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(SPFI);
1774 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
1775 unsigned SlotSize = SlotVT.getSizeInBits();
1776 unsigned DestSize = DestVT.getSizeInBits();
1777 Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
1778 unsigned DestAlign = TLI.getDataLayout()->getPrefTypeAlignment(DestType);
1780 // Emit a store to the stack slot. Use a truncstore if the input value is
1781 // later than DestVT.
1784 if (SrcSize > SlotSize)
1785 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1786 PtrInfo, SlotVT, false, false, SrcAlign);
1788 assert(SrcSize == SlotSize && "Invalid store");
1789 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1790 PtrInfo, false, false, SrcAlign);
1793 // Result is a load from the stack slot.
1794 if (SlotSize == DestSize)
1795 return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo,
1796 false, false, false, DestAlign);
1798 assert(SlotSize < DestSize && "Unknown extension!");
1799 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr,
1800 PtrInfo, SlotVT, false, false, DestAlign);
1803 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1805 // Create a vector sized/aligned stack slot, store the value to element #0,
1806 // then load the whole vector back out.
1807 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1809 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1810 int SPFI = StackPtrFI->getIndex();
1812 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0),
1814 MachinePointerInfo::getFixedStack(SPFI),
1815 Node->getValueType(0).getVectorElementType(),
1817 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
1818 MachinePointerInfo::getFixedStack(SPFI),
1819 false, false, false, 0);
1823 ExpandBVWithShuffles(SDNode *Node, SelectionDAG &DAG,
1824 const TargetLowering &TLI, SDValue &Res) {
1825 unsigned NumElems = Node->getNumOperands();
1827 EVT VT = Node->getValueType(0);
1829 // Try to group the scalars into pairs, shuffle the pairs together, then
1830 // shuffle the pairs of pairs together, etc. until the vector has
1831 // been built. This will work only if all of the necessary shuffle masks
1834 // We do this in two phases; first to check the legality of the shuffles,
1835 // and next, assuming that all shuffles are legal, to create the new nodes.
1836 for (int Phase = 0; Phase < 2; ++Phase) {
1837 SmallVector<std::pair<SDValue, SmallVector<int, 16> >, 16> IntermedVals,
1839 for (unsigned i = 0; i < NumElems; ++i) {
1840 SDValue V = Node->getOperand(i);
1841 if (V.getOpcode() == ISD::UNDEF)
1846 Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, V);
1847 IntermedVals.push_back(std::make_pair(Vec, SmallVector<int, 16>(1, i)));
1850 while (IntermedVals.size() > 2) {
1851 NewIntermedVals.clear();
1852 for (unsigned i = 0, e = (IntermedVals.size() & ~1u); i < e; i += 2) {
1853 // This vector and the next vector are shuffled together (simply to
1854 // append the one to the other).
1855 SmallVector<int, 16> ShuffleVec(NumElems, -1);
1857 SmallVector<int, 16> FinalIndices;
1858 FinalIndices.reserve(IntermedVals[i].second.size() +
1859 IntermedVals[i+1].second.size());
1862 for (unsigned j = 0, f = IntermedVals[i].second.size(); j != f;
1865 FinalIndices.push_back(IntermedVals[i].second[j]);
1867 for (unsigned j = 0, f = IntermedVals[i+1].second.size(); j != f;
1869 ShuffleVec[k] = NumElems + j;
1870 FinalIndices.push_back(IntermedVals[i+1].second[j]);
1875 Shuffle = DAG.getVectorShuffle(VT, dl, IntermedVals[i].first,
1876 IntermedVals[i+1].first,
1878 else if (!TLI.isShuffleMaskLegal(ShuffleVec, VT))
1880 NewIntermedVals.push_back(std::make_pair(Shuffle, FinalIndices));
1883 // If we had an odd number of defined values, then append the last
1884 // element to the array of new vectors.
1885 if ((IntermedVals.size() & 1) != 0)
1886 NewIntermedVals.push_back(IntermedVals.back());
1888 IntermedVals.swap(NewIntermedVals);
1891 assert(IntermedVals.size() <= 2 && IntermedVals.size() > 0 &&
1892 "Invalid number of intermediate vectors");
1893 SDValue Vec1 = IntermedVals[0].first;
1895 if (IntermedVals.size() > 1)
1896 Vec2 = IntermedVals[1].first;
1898 Vec2 = DAG.getUNDEF(VT);
1900 SmallVector<int, 16> ShuffleVec(NumElems, -1);
1901 for (unsigned i = 0, e = IntermedVals[0].second.size(); i != e; ++i)
1902 ShuffleVec[IntermedVals[0].second[i]] = i;
1903 for (unsigned i = 0, e = IntermedVals[1].second.size(); i != e; ++i)
1904 ShuffleVec[IntermedVals[1].second[i]] = NumElems + i;
1907 Res = DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
1908 else if (!TLI.isShuffleMaskLegal(ShuffleVec, VT))
1915 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
1916 /// support the operation, but do support the resultant vector type.
1917 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1918 unsigned NumElems = Node->getNumOperands();
1919 SDValue Value1, Value2;
1921 EVT VT = Node->getValueType(0);
1922 EVT OpVT = Node->getOperand(0).getValueType();
1923 EVT EltVT = VT.getVectorElementType();
1925 // If the only non-undef value is the low element, turn this into a
1926 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1927 bool isOnlyLowElement = true;
1928 bool MoreThanTwoValues = false;
1929 bool isConstant = true;
1930 for (unsigned i = 0; i < NumElems; ++i) {
1931 SDValue V = Node->getOperand(i);
1932 if (V.getOpcode() == ISD::UNDEF)
1935 isOnlyLowElement = false;
1936 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1939 if (!Value1.getNode()) {
1941 } else if (!Value2.getNode()) {
1944 } else if (V != Value1 && V != Value2) {
1945 MoreThanTwoValues = true;
1949 if (!Value1.getNode())
1950 return DAG.getUNDEF(VT);
1952 if (isOnlyLowElement)
1953 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1955 // If all elements are constants, create a load from the constant pool.
1957 SmallVector<Constant*, 16> CV;
1958 for (unsigned i = 0, e = NumElems; i != e; ++i) {
1959 if (ConstantFPSDNode *V =
1960 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1961 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1962 } else if (ConstantSDNode *V =
1963 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1965 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1967 // If OpVT and EltVT don't match, EltVT is not legal and the
1968 // element values have been promoted/truncated earlier. Undo this;
1969 // we don't want a v16i8 to become a v16i32 for example.
1970 const ConstantInt *CI = V->getConstantIntValue();
1971 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
1972 CI->getZExtValue()));
1975 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
1976 Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
1977 CV.push_back(UndefValue::get(OpNTy));
1980 Constant *CP = ConstantVector::get(CV);
1981 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
1982 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
1983 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
1984 MachinePointerInfo::getConstantPool(),
1985 false, false, false, Alignment);
1988 SmallSet<SDValue, 16> DefinedValues;
1989 for (unsigned i = 0; i < NumElems; ++i) {
1990 if (Node->getOperand(i).getOpcode() == ISD::UNDEF)
1992 DefinedValues.insert(Node->getOperand(i));
1995 if (TLI.shouldExpandBuildVectorWithShuffles(VT, DefinedValues.size())) {
1996 if (!MoreThanTwoValues) {
1997 SmallVector<int, 8> ShuffleVec(NumElems, -1);
1998 for (unsigned i = 0; i < NumElems; ++i) {
1999 SDValue V = Node->getOperand(i);
2000 if (V.getOpcode() == ISD::UNDEF)
2002 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
2004 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
2005 // Get the splatted value into the low element of a vector register.
2006 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
2008 if (Value2.getNode())
2009 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
2011 Vec2 = DAG.getUNDEF(VT);
2013 // Return shuffle(LowValVec, undef, <0,0,0,0>)
2014 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
2018 if (ExpandBVWithShuffles(Node, DAG, TLI, Res))
2023 // Otherwise, we can't handle this case efficiently.
2024 return ExpandVectorBuildThroughStack(Node);
2027 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
2028 // does not fit into a register, return the lo part and set the hi part to the
2029 // by-reg argument. If it does fit into a single register, return the result
2030 // and leave the Hi part unset.
2031 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
2033 TargetLowering::ArgListTy Args;
2034 TargetLowering::ArgListEntry Entry;
2035 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2036 EVT ArgVT = Node->getOperand(i).getValueType();
2037 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2038 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
2039 Entry.isSExt = isSigned;
2040 Entry.isZExt = !isSigned;
2041 Args.push_back(Entry);
2043 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2044 TLI.getPointerTy());
2046 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2048 // By default, the input chain to this libcall is the entry node of the
2049 // function. If the libcall is going to be emitted as a tail call then
2050 // TLI.isUsedByReturnOnly will change it to the right chain if the return
2051 // node which is being folded has a non-entry input chain.
2052 SDValue InChain = DAG.getEntryNode();
2054 // isTailCall may be true since the callee does not reference caller stack
2055 // frame. Check if it's in the right position.
2056 SDValue TCChain = InChain;
2057 bool isTailCall = TLI.isInTailCallPosition(DAG, Node, TCChain);
2061 TargetLowering::CallLoweringInfo CLI(DAG);
2062 CLI.setDebugLoc(SDLoc(Node)).setChain(InChain)
2063 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
2064 .setTailCall(isTailCall).setSExtResult(isSigned).setZExtResult(!isSigned);
2066 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2068 if (!CallInfo.second.getNode())
2069 // It's a tailcall, return the chain (which is the DAG root).
2070 return DAG.getRoot();
2072 return CallInfo.first;
2075 /// ExpandLibCall - Generate a libcall taking the given operands as arguments
2076 /// and returning a result of type RetVT.
2077 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, EVT RetVT,
2078 const SDValue *Ops, unsigned NumOps,
2079 bool isSigned, SDLoc dl) {
2080 TargetLowering::ArgListTy Args;
2081 Args.reserve(NumOps);
2083 TargetLowering::ArgListEntry Entry;
2084 for (unsigned i = 0; i != NumOps; ++i) {
2085 Entry.Node = Ops[i];
2086 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
2087 Entry.isSExt = isSigned;
2088 Entry.isZExt = !isSigned;
2089 Args.push_back(Entry);
2091 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2092 TLI.getPointerTy());
2094 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2096 TargetLowering::CallLoweringInfo CLI(DAG);
2097 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
2098 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
2099 .setSExtResult(isSigned).setZExtResult(!isSigned);
2101 std::pair<SDValue,SDValue> CallInfo = TLI.LowerCallTo(CLI);
2103 return CallInfo.first;
2106 // ExpandChainLibCall - Expand a node into a call to a libcall. Similar to
2107 // ExpandLibCall except that the first operand is the in-chain.
2108 std::pair<SDValue, SDValue>
2109 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
2112 SDValue InChain = Node->getOperand(0);
2114 TargetLowering::ArgListTy Args;
2115 TargetLowering::ArgListEntry Entry;
2116 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) {
2117 EVT ArgVT = Node->getOperand(i).getValueType();
2118 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2119 Entry.Node = Node->getOperand(i);
2121 Entry.isSExt = isSigned;
2122 Entry.isZExt = !isSigned;
2123 Args.push_back(Entry);
2125 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2126 TLI.getPointerTy());
2128 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2130 TargetLowering::CallLoweringInfo CLI(DAG);
2131 CLI.setDebugLoc(SDLoc(Node)).setChain(InChain)
2132 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
2133 .setSExtResult(isSigned).setZExtResult(!isSigned);
2135 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2140 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
2141 RTLIB::Libcall Call_F32,
2142 RTLIB::Libcall Call_F64,
2143 RTLIB::Libcall Call_F80,
2144 RTLIB::Libcall Call_F128,
2145 RTLIB::Libcall Call_PPCF128) {
2147 switch (Node->getSimpleValueType(0).SimpleTy) {
2148 default: llvm_unreachable("Unexpected request for libcall!");
2149 case MVT::f32: LC = Call_F32; break;
2150 case MVT::f64: LC = Call_F64; break;
2151 case MVT::f80: LC = Call_F80; break;
2152 case MVT::f128: LC = Call_F128; break;
2153 case MVT::ppcf128: LC = Call_PPCF128; break;
2155 return ExpandLibCall(LC, Node, false);
2158 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
2159 RTLIB::Libcall Call_I8,
2160 RTLIB::Libcall Call_I16,
2161 RTLIB::Libcall Call_I32,
2162 RTLIB::Libcall Call_I64,
2163 RTLIB::Libcall Call_I128) {
2165 switch (Node->getSimpleValueType(0).SimpleTy) {
2166 default: llvm_unreachable("Unexpected request for libcall!");
2167 case MVT::i8: LC = Call_I8; break;
2168 case MVT::i16: LC = Call_I16; break;
2169 case MVT::i32: LC = Call_I32; break;
2170 case MVT::i64: LC = Call_I64; break;
2171 case MVT::i128: LC = Call_I128; break;
2173 return ExpandLibCall(LC, Node, isSigned);
2176 /// isDivRemLibcallAvailable - Return true if divmod libcall is available.
2177 static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
2178 const TargetLowering &TLI) {
2180 switch (Node->getSimpleValueType(0).SimpleTy) {
2181 default: llvm_unreachable("Unexpected request for libcall!");
2182 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2183 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2184 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2185 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2186 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2189 return TLI.getLibcallName(LC) != nullptr;
2192 /// useDivRem - Only issue divrem libcall if both quotient and remainder are
2194 static bool useDivRem(SDNode *Node, bool isSigned, bool isDIV) {
2195 // The other use might have been replaced with a divrem already.
2196 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2197 unsigned OtherOpcode = 0;
2199 OtherOpcode = isDIV ? ISD::SREM : ISD::SDIV;
2201 OtherOpcode = isDIV ? ISD::UREM : ISD::UDIV;
2203 SDValue Op0 = Node->getOperand(0);
2204 SDValue Op1 = Node->getOperand(1);
2205 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2206 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2210 if ((User->getOpcode() == OtherOpcode || User->getOpcode() == DivRemOpc) &&
2211 User->getOperand(0) == Op0 &&
2212 User->getOperand(1) == Op1)
2218 /// ExpandDivRemLibCall - Issue libcalls to __{u}divmod to compute div / rem
2221 SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
2222 SmallVectorImpl<SDValue> &Results) {
2223 unsigned Opcode = Node->getOpcode();
2224 bool isSigned = Opcode == ISD::SDIVREM;
2227 switch (Node->getSimpleValueType(0).SimpleTy) {
2228 default: llvm_unreachable("Unexpected request for libcall!");
2229 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2230 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2231 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2232 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2233 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2236 // The input chain to this libcall is the entry node of the function.
2237 // Legalizing the call will automatically add the previous call to the
2239 SDValue InChain = DAG.getEntryNode();
2241 EVT RetVT = Node->getValueType(0);
2242 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2244 TargetLowering::ArgListTy Args;
2245 TargetLowering::ArgListEntry Entry;
2246 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2247 EVT ArgVT = Node->getOperand(i).getValueType();
2248 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2249 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
2250 Entry.isSExt = isSigned;
2251 Entry.isZExt = !isSigned;
2252 Args.push_back(Entry);
2255 // Also pass the return address of the remainder.
2256 SDValue FIPtr = DAG.CreateStackTemporary(RetVT);
2258 Entry.Ty = RetTy->getPointerTo();
2259 Entry.isSExt = isSigned;
2260 Entry.isZExt = !isSigned;
2261 Args.push_back(Entry);
2263 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2264 TLI.getPointerTy());
2267 TargetLowering::CallLoweringInfo CLI(DAG);
2268 CLI.setDebugLoc(dl).setChain(InChain)
2269 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
2270 .setSExtResult(isSigned).setZExtResult(!isSigned);
2272 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2274 // Remainder is loaded back from the stack frame.
2275 SDValue Rem = DAG.getLoad(RetVT, dl, CallInfo.second, FIPtr,
2276 MachinePointerInfo(), false, false, false, 0);
2277 Results.push_back(CallInfo.first);
2278 Results.push_back(Rem);
2281 /// isSinCosLibcallAvailable - Return true if sincos libcall is available.
2282 static bool isSinCosLibcallAvailable(SDNode *Node, const TargetLowering &TLI) {
2284 switch (Node->getSimpleValueType(0).SimpleTy) {
2285 default: llvm_unreachable("Unexpected request for libcall!");
2286 case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2287 case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2288 case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2289 case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2290 case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2292 return TLI.getLibcallName(LC) != nullptr;
2295 /// canCombineSinCosLibcall - Return true if sincos libcall is available and
2296 /// can be used to combine sin and cos.
2297 static bool canCombineSinCosLibcall(SDNode *Node, const TargetLowering &TLI,
2298 const TargetMachine &TM) {
2299 if (!isSinCosLibcallAvailable(Node, TLI))
2301 // GNU sin/cos functions set errno while sincos does not. Therefore
2302 // combining sin and cos is only safe if unsafe-fpmath is enabled.
2303 bool isGNU = Triple(TM.getTargetTriple()).getEnvironment() == Triple::GNU;
2304 if (isGNU && !TM.Options.UnsafeFPMath)
2309 /// useSinCos - Only issue sincos libcall if both sin and cos are
2311 static bool useSinCos(SDNode *Node) {
2312 unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN
2313 ? ISD::FCOS : ISD::FSIN;
2315 SDValue Op0 = Node->getOperand(0);
2316 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2317 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2321 // The other user might have been turned into sincos already.
2322 if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS)
2328 /// ExpandSinCosLibCall - Issue libcalls to sincos to compute sin / cos
2331 SelectionDAGLegalize::ExpandSinCosLibCall(SDNode *Node,
2332 SmallVectorImpl<SDValue> &Results) {
2334 switch (Node->getSimpleValueType(0).SimpleTy) {
2335 default: llvm_unreachable("Unexpected request for libcall!");
2336 case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2337 case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2338 case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2339 case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2340 case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2343 // The input chain to this libcall is the entry node of the function.
2344 // Legalizing the call will automatically add the previous call to the
2346 SDValue InChain = DAG.getEntryNode();
2348 EVT RetVT = Node->getValueType(0);
2349 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2351 TargetLowering::ArgListTy Args;
2352 TargetLowering::ArgListEntry Entry;
2354 // Pass the argument.
2355 Entry.Node = Node->getOperand(0);
2357 Entry.isSExt = false;
2358 Entry.isZExt = false;
2359 Args.push_back(Entry);
2361 // Pass the return address of sin.
2362 SDValue SinPtr = DAG.CreateStackTemporary(RetVT);
2363 Entry.Node = SinPtr;
2364 Entry.Ty = RetTy->getPointerTo();
2365 Entry.isSExt = false;
2366 Entry.isZExt = false;
2367 Args.push_back(Entry);
2369 // Also pass the return address of the cos.
2370 SDValue CosPtr = DAG.CreateStackTemporary(RetVT);
2371 Entry.Node = CosPtr;
2372 Entry.Ty = RetTy->getPointerTo();
2373 Entry.isSExt = false;
2374 Entry.isZExt = false;
2375 Args.push_back(Entry);
2377 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2378 TLI.getPointerTy());
2381 TargetLowering::CallLoweringInfo CLI(DAG);
2382 CLI.setDebugLoc(dl).setChain(InChain)
2383 .setCallee(TLI.getLibcallCallingConv(LC),
2384 Type::getVoidTy(*DAG.getContext()), Callee, std::move(Args), 0);
2386 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2388 Results.push_back(DAG.getLoad(RetVT, dl, CallInfo.second, SinPtr,
2389 MachinePointerInfo(), false, false, false, 0));
2390 Results.push_back(DAG.getLoad(RetVT, dl, CallInfo.second, CosPtr,
2391 MachinePointerInfo(), false, false, false, 0));
2394 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
2395 /// INT_TO_FP operation of the specified operand when the target requests that
2396 /// we expand it. At this point, we know that the result and operand types are
2397 /// legal for the target.
2398 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
2402 if (Op0.getValueType() == MVT::i32 && TLI.isTypeLegal(MVT::f64)) {
2403 // simple 32-bit [signed|unsigned] integer to float/double expansion
2405 // Get the stack frame index of a 8 byte buffer.
2406 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2408 // word offset constant for Hi/Lo address computation
2409 SDValue WordOff = DAG.getConstant(sizeof(int), StackSlot.getValueType());
2410 // set up Hi and Lo (into buffer) address based on endian
2411 SDValue Hi = StackSlot;
2412 SDValue Lo = DAG.getNode(ISD::ADD, dl, StackSlot.getValueType(),
2413 StackSlot, WordOff);
2414 if (TLI.isLittleEndian())
2417 // if signed map to unsigned space
2420 // constant used to invert sign bit (signed to unsigned mapping)
2421 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
2422 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2426 // store the lo of the constructed double - based on integer input
2427 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
2428 Op0Mapped, Lo, MachinePointerInfo(),
2430 // initial hi portion of constructed double
2431 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
2432 // store the hi of the constructed double - biased exponent
2433 SDValue Store2 = DAG.getStore(Store1, dl, InitialHi, Hi,
2434 MachinePointerInfo(),
2436 // load the constructed double
2437 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot,
2438 MachinePointerInfo(), false, false, false, 0);
2439 // FP constant to bias correct the final result
2440 SDValue Bias = DAG.getConstantFP(isSigned ?
2441 BitsToDouble(0x4330000080000000ULL) :
2442 BitsToDouble(0x4330000000000000ULL),
2444 // subtract the bias
2445 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2448 // handle final rounding
2449 if (DestVT == MVT::f64) {
2452 } else if (DestVT.bitsLT(MVT::f64)) {
2453 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2454 DAG.getIntPtrConstant(0));
2455 } else if (DestVT.bitsGT(MVT::f64)) {
2456 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2460 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2461 // Code below here assumes !isSigned without checking again.
2463 // Implementation of unsigned i64 to f64 following the algorithm in
2464 // __floatundidf in compiler_rt. This implementation has the advantage
2465 // of performing rounding correctly, both in the default rounding mode
2466 // and in all alternate rounding modes.
2467 // TODO: Generalize this for use with other types.
2468 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
2470 DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64);
2471 SDValue TwoP84PlusTwoP52 =
2472 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64);
2474 DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64);
2476 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32);
2477 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2478 DAG.getConstant(32, MVT::i64));
2479 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2480 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2481 SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr);
2482 SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr);
2483 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
2485 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
2488 // Implementation of unsigned i64 to f32.
2489 // TODO: Generalize this for use with other types.
2490 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) {
2491 // For unsigned conversions, convert them to signed conversions using the
2492 // algorithm from the x86_64 __floatundidf in compiler_rt.
2494 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0);
2496 SDValue ShiftConst =
2497 DAG.getConstant(1, TLI.getShiftAmountTy(Op0.getValueType()));
2498 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
2499 SDValue AndConst = DAG.getConstant(1, MVT::i64);
2500 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst);
2501 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr);
2503 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or);
2504 SDValue Slow = DAG.getNode(ISD::FADD, dl, MVT::f32, SignCvt, SignCvt);
2506 // TODO: This really should be implemented using a branch rather than a
2507 // select. We happen to get lucky and machinesink does the right
2508 // thing most of the time. This would be a good candidate for a
2509 //pseudo-op, or, even better, for whole-function isel.
2510 SDValue SignBitTest = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
2511 Op0, DAG.getConstant(0, MVT::i64), ISD::SETLT);
2512 return DAG.getSelect(dl, MVT::f32, SignBitTest, Slow, Fast);
2515 // Otherwise, implement the fully general conversion.
2517 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2518 DAG.getConstant(UINT64_C(0xfffffffffffff800), MVT::i64));
2519 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
2520 DAG.getConstant(UINT64_C(0x800), MVT::i64));
2521 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2522 DAG.getConstant(UINT64_C(0x7ff), MVT::i64));
2523 SDValue Ne = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
2524 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE);
2525 SDValue Sel = DAG.getSelect(dl, MVT::i64, Ne, Or, Op0);
2526 SDValue Ge = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
2527 Op0, DAG.getConstant(UINT64_C(0x0020000000000000), MVT::i64),
2529 SDValue Sel2 = DAG.getSelect(dl, MVT::i64, Ge, Sel, Op0);
2530 EVT SHVT = TLI.getShiftAmountTy(Sel2.getValueType());
2532 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2533 DAG.getConstant(32, SHVT));
2534 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh);
2535 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc);
2537 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), MVT::f64);
2538 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt);
2539 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2);
2540 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo);
2541 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2);
2542 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd,
2543 DAG.getIntPtrConstant(0));
2546 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2548 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(Op0.getValueType()),
2549 Op0, DAG.getConstant(0, Op0.getValueType()),
2551 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
2552 SDValue CstOffset = DAG.getSelect(dl, Zero.getValueType(),
2553 SignSet, Four, Zero);
2555 // If the sign bit of the integer is set, the large number will be treated
2556 // as a negative number. To counteract this, the dynamic code adds an
2557 // offset depending on the data type.
2559 switch (Op0.getSimpleValueType().SimpleTy) {
2560 default: llvm_unreachable("Unsupported integer type!");
2561 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2562 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2563 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2564 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2566 if (TLI.isLittleEndian()) FF <<= 32;
2567 Constant *FudgeFactor = ConstantInt::get(
2568 Type::getInt64Ty(*DAG.getContext()), FF);
2570 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
2571 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2572 CPIdx = DAG.getNode(ISD::ADD, dl, CPIdx.getValueType(), CPIdx, CstOffset);
2573 Alignment = std::min(Alignment, 4u);
2575 if (DestVT == MVT::f32)
2576 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2577 MachinePointerInfo::getConstantPool(),
2578 false, false, false, Alignment);
2580 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
2581 DAG.getEntryNode(), CPIdx,
2582 MachinePointerInfo::getConstantPool(),
2583 MVT::f32, false, false, Alignment);
2584 HandleSDNode Handle(Load);
2585 LegalizeOp(Load.getNode());
2586 FudgeInReg = Handle.getValue();
2589 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2592 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
2593 /// *INT_TO_FP operation of the specified operand when the target requests that
2594 /// we promote it. At this point, we know that the result and operand types are
2595 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2596 /// operation that takes a larger input.
2597 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2601 // First step, figure out the appropriate *INT_TO_FP operation to use.
2602 EVT NewInTy = LegalOp.getValueType();
2604 unsigned OpToUse = 0;
2606 // Scan for the appropriate larger type to use.
2608 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2609 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2611 // If the target supports SINT_TO_FP of this type, use it.
2612 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2613 OpToUse = ISD::SINT_TO_FP;
2616 if (isSigned) continue;
2618 // If the target supports UINT_TO_FP of this type, use it.
2619 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2620 OpToUse = ISD::UINT_TO_FP;
2624 // Otherwise, try a larger type.
2627 // Okay, we found the operation and type to use. Zero extend our input to the
2628 // desired type then run the operation on it.
2629 return DAG.getNode(OpToUse, dl, DestVT,
2630 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2631 dl, NewInTy, LegalOp));
2634 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
2635 /// FP_TO_*INT operation of the specified operand when the target requests that
2636 /// we promote it. At this point, we know that the result and operand types are
2637 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2638 /// operation that returns a larger result.
2639 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2643 // First step, figure out the appropriate FP_TO*INT operation to use.
2644 EVT NewOutTy = DestVT;
2646 unsigned OpToUse = 0;
2648 // Scan for the appropriate larger type to use.
2650 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2651 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2653 // A larger signed type can hold all unsigned values of the requested type,
2654 // so using FP_TO_SINT is valid
2655 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2656 OpToUse = ISD::FP_TO_SINT;
2660 // However, if the value may be < 0.0, we *must* use some FP_TO_SINT.
2661 if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2662 OpToUse = ISD::FP_TO_UINT;
2666 // Otherwise, try a larger type.
2670 // Okay, we found the operation and type to use.
2671 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2673 // Truncate the result of the extended FP_TO_*INT operation to the desired
2675 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2678 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
2680 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, SDLoc dl) {
2681 EVT VT = Op.getValueType();
2682 EVT SHVT = TLI.getShiftAmountTy(VT);
2683 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2684 switch (VT.getSimpleVT().SimpleTy) {
2685 default: llvm_unreachable("Unhandled Expand type in BSWAP!");
2687 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2688 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2689 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2691 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2692 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2693 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2694 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2695 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
2696 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
2697 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2698 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2699 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2701 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
2702 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
2703 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2704 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2705 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2706 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2707 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
2708 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
2709 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
2710 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
2711 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
2712 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
2713 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
2714 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
2715 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2716 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2717 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2718 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2719 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2720 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2721 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2725 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
2727 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2730 default: llvm_unreachable("Cannot expand this yet!");
2732 EVT VT = Op.getValueType();
2733 EVT ShVT = TLI.getShiftAmountTy(VT);
2734 unsigned Len = VT.getSizeInBits();
2736 assert(VT.isInteger() && Len <= 128 && Len % 8 == 0 &&
2737 "CTPOP not implemented for this type.");
2739 // This is the "best" algorithm from
2740 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
2742 SDValue Mask55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)), VT);
2743 SDValue Mask33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)), VT);
2744 SDValue Mask0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)), VT);
2745 SDValue Mask01 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x01)), VT);
2747 // v = v - ((v >> 1) & 0x55555555...)
2748 Op = DAG.getNode(ISD::SUB, dl, VT, Op,
2749 DAG.getNode(ISD::AND, dl, VT,
2750 DAG.getNode(ISD::SRL, dl, VT, Op,
2751 DAG.getConstant(1, ShVT)),
2753 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
2754 Op = DAG.getNode(ISD::ADD, dl, VT,
2755 DAG.getNode(ISD::AND, dl, VT, Op, Mask33),
2756 DAG.getNode(ISD::AND, dl, VT,
2757 DAG.getNode(ISD::SRL, dl, VT, Op,
2758 DAG.getConstant(2, ShVT)),
2760 // v = (v + (v >> 4)) & 0x0F0F0F0F...
2761 Op = DAG.getNode(ISD::AND, dl, VT,
2762 DAG.getNode(ISD::ADD, dl, VT, Op,
2763 DAG.getNode(ISD::SRL, dl, VT, Op,
2764 DAG.getConstant(4, ShVT))),
2766 // v = (v * 0x01010101...) >> (Len - 8)
2767 Op = DAG.getNode(ISD::SRL, dl, VT,
2768 DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
2769 DAG.getConstant(Len - 8, ShVT));
2773 case ISD::CTLZ_ZERO_UNDEF:
2774 // This trivially expands to CTLZ.
2775 return DAG.getNode(ISD::CTLZ, dl, Op.getValueType(), Op);
2777 // for now, we do this:
2778 // x = x | (x >> 1);
2779 // x = x | (x >> 2);
2781 // x = x | (x >>16);
2782 // x = x | (x >>32); // for 64-bit input
2783 // return popcount(~x);
2785 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
2786 EVT VT = Op.getValueType();
2787 EVT ShVT = TLI.getShiftAmountTy(VT);
2788 unsigned len = VT.getSizeInBits();
2789 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2790 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2791 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2792 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2794 Op = DAG.getNOT(dl, Op, VT);
2795 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2797 case ISD::CTTZ_ZERO_UNDEF:
2798 // This trivially expands to CTTZ.
2799 return DAG.getNode(ISD::CTTZ, dl, Op.getValueType(), Op);
2801 // for now, we use: { return popcount(~x & (x - 1)); }
2802 // unless the target has ctlz but not ctpop, in which case we use:
2803 // { return 32 - nlz(~x & (x-1)); }
2804 // see also http://www.hackersdelight.org/HDcode/ntz.cc
2805 EVT VT = Op.getValueType();
2806 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2807 DAG.getNOT(dl, Op, VT),
2808 DAG.getNode(ISD::SUB, dl, VT, Op,
2809 DAG.getConstant(1, VT)));
2810 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2811 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2812 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2813 return DAG.getNode(ISD::SUB, dl, VT,
2814 DAG.getConstant(VT.getSizeInBits(), VT),
2815 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2816 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2821 std::pair <SDValue, SDValue> SelectionDAGLegalize::ExpandAtomic(SDNode *Node) {
2822 unsigned Opc = Node->getOpcode();
2823 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
2828 llvm_unreachable("Unhandled atomic intrinsic Expand!");
2829 case ISD::ATOMIC_SWAP:
2830 switch (VT.SimpleTy) {
2831 default: llvm_unreachable("Unexpected value type for atomic!");
2832 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break;
2833 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
2834 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
2835 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
2836 case MVT::i128:LC = RTLIB::SYNC_LOCK_TEST_AND_SET_16;break;
2839 case ISD::ATOMIC_CMP_SWAP:
2840 switch (VT.SimpleTy) {
2841 default: llvm_unreachable("Unexpected value type for atomic!");
2842 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break;
2843 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;
2844 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;
2845 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
2846 case MVT::i128:LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16;break;
2849 case ISD::ATOMIC_LOAD_ADD:
2850 switch (VT.SimpleTy) {
2851 default: llvm_unreachable("Unexpected value type for atomic!");
2852 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break;
2853 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;
2854 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;
2855 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
2856 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_ADD_16;break;
2859 case ISD::ATOMIC_LOAD_SUB:
2860 switch (VT.SimpleTy) {
2861 default: llvm_unreachable("Unexpected value type for atomic!");
2862 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break;
2863 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;
2864 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;
2865 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
2866 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_SUB_16;break;
2869 case ISD::ATOMIC_LOAD_AND:
2870 switch (VT.SimpleTy) {
2871 default: llvm_unreachable("Unexpected value type for atomic!");
2872 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break;
2873 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;
2874 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;
2875 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
2876 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_AND_16;break;
2879 case ISD::ATOMIC_LOAD_OR:
2880 switch (VT.SimpleTy) {
2881 default: llvm_unreachable("Unexpected value type for atomic!");
2882 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break;
2883 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;
2884 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;
2885 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
2886 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_OR_16;break;
2889 case ISD::ATOMIC_LOAD_XOR:
2890 switch (VT.SimpleTy) {
2891 default: llvm_unreachable("Unexpected value type for atomic!");
2892 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break;
2893 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;
2894 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;
2895 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
2896 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_XOR_16;break;
2899 case ISD::ATOMIC_LOAD_NAND:
2900 switch (VT.SimpleTy) {
2901 default: llvm_unreachable("Unexpected value type for atomic!");
2902 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break;
2903 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;
2904 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;
2905 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
2906 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_NAND_16;break;
2909 case ISD::ATOMIC_LOAD_MAX:
2910 switch (VT.SimpleTy) {
2911 default: llvm_unreachable("Unexpected value type for atomic!");
2912 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_MAX_1; break;
2913 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_MAX_2; break;
2914 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_MAX_4; break;
2915 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_MAX_8; break;
2916 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_MAX_16;break;
2919 case ISD::ATOMIC_LOAD_UMAX:
2920 switch (VT.SimpleTy) {
2921 default: llvm_unreachable("Unexpected value type for atomic!");
2922 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_UMAX_1; break;
2923 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_UMAX_2; break;
2924 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_UMAX_4; break;
2925 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_UMAX_8; break;
2926 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_UMAX_16;break;
2929 case ISD::ATOMIC_LOAD_MIN:
2930 switch (VT.SimpleTy) {
2931 default: llvm_unreachable("Unexpected value type for atomic!");
2932 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_MIN_1; break;
2933 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_MIN_2; break;
2934 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_MIN_4; break;
2935 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_MIN_8; break;
2936 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_MIN_16;break;
2939 case ISD::ATOMIC_LOAD_UMIN:
2940 switch (VT.SimpleTy) {
2941 default: llvm_unreachable("Unexpected value type for atomic!");
2942 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_UMIN_1; break;
2943 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_UMIN_2; break;
2944 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_UMIN_4; break;
2945 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_UMIN_8; break;
2946 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_UMIN_16;break;
2951 return ExpandChainLibCall(LC, Node, false);
2954 void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
2955 SmallVector<SDValue, 8> Results;
2957 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2959 switch (Node->getOpcode()) {
2962 case ISD::CTLZ_ZERO_UNDEF:
2964 case ISD::CTTZ_ZERO_UNDEF:
2965 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
2966 Results.push_back(Tmp1);
2969 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2971 case ISD::FRAMEADDR:
2972 case ISD::RETURNADDR:
2973 case ISD::FRAME_TO_ARGS_OFFSET:
2974 Results.push_back(DAG.getConstant(0, Node->getValueType(0)));
2976 case ISD::FLT_ROUNDS_:
2977 Results.push_back(DAG.getConstant(1, Node->getValueType(0)));
2979 case ISD::EH_RETURN:
2983 case ISD::EH_SJLJ_LONGJMP:
2984 // If the target didn't expand these, there's nothing to do, so just
2985 // preserve the chain and be done.
2986 Results.push_back(Node->getOperand(0));
2988 case ISD::EH_SJLJ_SETJMP:
2989 // If the target didn't expand this, just return 'zero' and preserve the
2991 Results.push_back(DAG.getConstant(0, MVT::i32));
2992 Results.push_back(Node->getOperand(0));
2994 case ISD::ATOMIC_FENCE: {
2995 // If the target didn't lower this, lower it to '__sync_synchronize()' call
2996 // FIXME: handle "fence singlethread" more efficiently.
2997 TargetLowering::ArgListTy Args;
2999 TargetLowering::CallLoweringInfo CLI(DAG);
3000 CLI.setDebugLoc(dl).setChain(Node->getOperand(0))
3001 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
3002 DAG.getExternalSymbol("__sync_synchronize",
3003 TLI.getPointerTy()), std::move(Args), 0);
3005 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
3007 Results.push_back(CallResult.second);
3010 case ISD::ATOMIC_LOAD: {
3011 // There is no libcall for atomic load; fake it with ATOMIC_CMP_SWAP.
3012 SDValue Zero = DAG.getConstant(0, Node->getValueType(0));
3013 SDVTList VTs = DAG.getVTList(Node->getValueType(0), MVT::Other);
3014 SDValue Swap = DAG.getAtomicCmpSwap(
3015 ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
3016 Node->getOperand(0), Node->getOperand(1), Zero, Zero,
3017 cast<AtomicSDNode>(Node)->getMemOperand(),
3018 cast<AtomicSDNode>(Node)->getOrdering(),
3019 cast<AtomicSDNode>(Node)->getOrdering(),
3020 cast<AtomicSDNode>(Node)->getSynchScope());
3021 Results.push_back(Swap.getValue(0));
3022 Results.push_back(Swap.getValue(1));
3025 case ISD::ATOMIC_STORE: {
3026 // There is no libcall for atomic store; fake it with ATOMIC_SWAP.
3027 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
3028 cast<AtomicSDNode>(Node)->getMemoryVT(),
3029 Node->getOperand(0),
3030 Node->getOperand(1), Node->getOperand(2),
3031 cast<AtomicSDNode>(Node)->getMemOperand(),
3032 cast<AtomicSDNode>(Node)->getOrdering(),
3033 cast<AtomicSDNode>(Node)->getSynchScope());
3034 Results.push_back(Swap.getValue(1));
3037 // By default, atomic intrinsics are marked Legal and lowered. Targets
3038 // which don't support them directly, however, may want libcalls, in which
3039 // case they mark them Expand, and we get here.
3040 case ISD::ATOMIC_SWAP:
3041 case ISD::ATOMIC_LOAD_ADD:
3042 case ISD::ATOMIC_LOAD_SUB:
3043 case ISD::ATOMIC_LOAD_AND:
3044 case ISD::ATOMIC_LOAD_OR:
3045 case ISD::ATOMIC_LOAD_XOR:
3046 case ISD::ATOMIC_LOAD_NAND:
3047 case ISD::ATOMIC_LOAD_MIN:
3048 case ISD::ATOMIC_LOAD_MAX:
3049 case ISD::ATOMIC_LOAD_UMIN:
3050 case ISD::ATOMIC_LOAD_UMAX:
3051 case ISD::ATOMIC_CMP_SWAP: {
3052 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node);
3053 Results.push_back(Tmp.first);
3054 Results.push_back(Tmp.second);
3057 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
3058 // Expanding an ATOMIC_CMP_SWAP_WITH_SUCCESS produces an ATOMIC_CMP_SWAP and
3059 // splits out the success value as a comparison. Expanding the resulting
3060 // ATOMIC_CMP_SWAP will produce a libcall.
3061 SDVTList VTs = DAG.getVTList(Node->getValueType(0), MVT::Other);
3062 SDValue Res = DAG.getAtomicCmpSwap(
3063 ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
3064 Node->getOperand(0), Node->getOperand(1), Node->getOperand(2),
3065 Node->getOperand(3), cast<MemSDNode>(Node)->getMemOperand(),
3066 cast<AtomicSDNode>(Node)->getSuccessOrdering(),
3067 cast<AtomicSDNode>(Node)->getFailureOrdering(),
3068 cast<AtomicSDNode>(Node)->getSynchScope());
3070 SDValue Success = DAG.getSetCC(SDLoc(Node), Node->getValueType(1),
3071 Res, Node->getOperand(2), ISD::SETEQ);
3073 Results.push_back(Res.getValue(0));
3074 Results.push_back(Success);
3075 Results.push_back(Res.getValue(1));
3078 case ISD::DYNAMIC_STACKALLOC:
3079 ExpandDYNAMIC_STACKALLOC(Node, Results);
3081 case ISD::MERGE_VALUES:
3082 for (unsigned i = 0; i < Node->getNumValues(); i++)
3083 Results.push_back(Node->getOperand(i));
3086 EVT VT = Node->getValueType(0);
3088 Results.push_back(DAG.getConstant(0, VT));
3090 assert(VT.isFloatingPoint() && "Unknown value type!");
3091 Results.push_back(DAG.getConstantFP(0, VT));
3096 // If this operation is not supported, lower it to 'abort()' call
3097 TargetLowering::ArgListTy Args;
3098 TargetLowering::CallLoweringInfo CLI(DAG);
3099 CLI.setDebugLoc(dl).setChain(Node->getOperand(0))
3100 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
3101 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
3102 std::move(Args), 0);
3103 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
3105 Results.push_back(CallResult.second);
3110 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3111 Node->getValueType(0), dl);
3112 Results.push_back(Tmp1);
3114 case ISD::FP_EXTEND:
3115 Tmp1 = EmitStackConvert(Node->getOperand(0),
3116 Node->getOperand(0).getValueType(),
3117 Node->getValueType(0), dl);
3118 Results.push_back(Tmp1);
3120 case ISD::SIGN_EXTEND_INREG: {
3121 // NOTE: we could fall back on load/store here too for targets without
3122 // SAR. However, it is doubtful that any exist.
3123 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3124 EVT VT = Node->getValueType(0);
3125 EVT ShiftAmountTy = TLI.getShiftAmountTy(VT);
3128 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
3129 ExtraVT.getScalarType().getSizeInBits();
3130 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy);
3131 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
3132 Node->getOperand(0), ShiftCst);
3133 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
3134 Results.push_back(Tmp1);
3137 case ISD::FP_ROUND_INREG: {
3138 // The only way we can lower this is to turn it into a TRUNCSTORE,
3139 // EXTLOAD pair, targeting a temporary location (a stack slot).
3141 // NOTE: there is a choice here between constantly creating new stack
3142 // slots and always reusing the same one. We currently always create
3143 // new ones, as reuse may inhibit scheduling.
3144 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3145 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
3146 Node->getValueType(0), dl);
3147 Results.push_back(Tmp1);
3150 case ISD::SINT_TO_FP:
3151 case ISD::UINT_TO_FP:
3152 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
3153 Node->getOperand(0), Node->getValueType(0), dl);
3154 Results.push_back(Tmp1);
3156 case ISD::FP_TO_SINT:
3157 if (TLI.expandFP_TO_SINT(Node, Tmp1, DAG))
3158 Results.push_back(Tmp1);
3160 case ISD::FP_TO_UINT: {
3161 SDValue True, False;
3162 EVT VT = Node->getOperand(0).getValueType();
3163 EVT NVT = Node->getValueType(0);
3164 APFloat apf(DAG.EVTToAPFloatSemantics(VT),
3165 APInt::getNullValue(VT.getSizeInBits()));
3166 APInt x = APInt::getSignBit(NVT.getSizeInBits());
3167 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
3168 Tmp1 = DAG.getConstantFP(apf, VT);
3169 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(VT),
3170 Node->getOperand(0),
3172 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
3173 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
3174 DAG.getNode(ISD::FSUB, dl, VT,
3175 Node->getOperand(0), Tmp1));
3176 False = DAG.getNode(ISD::XOR, dl, NVT, False,
3177 DAG.getConstant(x, NVT));
3178 Tmp1 = DAG.getSelect(dl, NVT, Tmp2, True, False);
3179 Results.push_back(Tmp1);
3183 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3184 EVT VT = Node->getValueType(0);
3185 Tmp1 = Node->getOperand(0);
3186 Tmp2 = Node->getOperand(1);
3187 unsigned Align = Node->getConstantOperandVal(3);
3189 SDValue VAListLoad = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2,
3190 MachinePointerInfo(V),
3191 false, false, false, 0);
3192 SDValue VAList = VAListLoad;
3194 if (Align > TLI.getMinStackArgumentAlignment()) {
3195 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
3197 VAList = DAG.getNode(ISD::ADD, dl, VAList.getValueType(), VAList,
3198 DAG.getConstant(Align - 1,
3199 VAList.getValueType()));
3201 VAList = DAG.getNode(ISD::AND, dl, VAList.getValueType(), VAList,
3202 DAG.getConstant(-(int64_t)Align,
3203 VAList.getValueType()));
3206 // Increment the pointer, VAList, to the next vaarg
3207 Tmp3 = DAG.getNode(ISD::ADD, dl, VAList.getValueType(), VAList,
3208 DAG.getConstant(TLI.getDataLayout()->
3209 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())),
3210 VAList.getValueType()));
3211 // Store the incremented VAList to the legalized pointer
3212 Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2,
3213 MachinePointerInfo(V), false, false, 0);
3214 // Load the actual argument out of the pointer VAList
3215 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(),
3216 false, false, false, 0));
3217 Results.push_back(Results[0].getValue(1));
3221 // This defaults to loading a pointer from the input and storing it to the
3222 // output, returning the chain.
3223 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3224 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3225 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0),
3226 Node->getOperand(2), MachinePointerInfo(VS),
3227 false, false, false, 0);
3228 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1),
3229 MachinePointerInfo(VD), false, false, 0);
3230 Results.push_back(Tmp1);
3233 case ISD::EXTRACT_VECTOR_ELT:
3234 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
3235 // This must be an access of the only element. Return it.
3236 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
3237 Node->getOperand(0));
3239 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
3240 Results.push_back(Tmp1);
3242 case ISD::EXTRACT_SUBVECTOR:
3243 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
3245 case ISD::INSERT_SUBVECTOR:
3246 Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0)));
3248 case ISD::CONCAT_VECTORS: {
3249 Results.push_back(ExpandVectorBuildThroughStack(Node));
3252 case ISD::SCALAR_TO_VECTOR:
3253 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
3255 case ISD::INSERT_VECTOR_ELT:
3256 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
3257 Node->getOperand(1),
3258 Node->getOperand(2), dl));
3260 case ISD::VECTOR_SHUFFLE: {
3261 SmallVector<int, 32> NewMask;
3262 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
3264 EVT VT = Node->getValueType(0);
3265 EVT EltVT = VT.getVectorElementType();
3266 SDValue Op0 = Node->getOperand(0);
3267 SDValue Op1 = Node->getOperand(1);
3268 if (!TLI.isTypeLegal(EltVT)) {
3270 EVT NewEltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
3272 // BUILD_VECTOR operands are allowed to be wider than the element type.
3273 // But if NewEltVT is smaller that EltVT the BUILD_VECTOR does not accept
3275 if (NewEltVT.bitsLT(EltVT)) {
3277 // Convert shuffle node.
3278 // If original node was v4i64 and the new EltVT is i32,
3279 // cast operands to v8i32 and re-build the mask.
3281 // Calculate new VT, the size of the new VT should be equal to original.
3283 EVT::getVectorVT(*DAG.getContext(), NewEltVT,
3284 VT.getSizeInBits() / NewEltVT.getSizeInBits());
3285 assert(NewVT.bitsEq(VT));
3287 // cast operands to new VT
3288 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0);
3289 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1);
3291 // Convert the shuffle mask
3292 unsigned int factor =
3293 NewVT.getVectorNumElements()/VT.getVectorNumElements();
3295 // EltVT gets smaller
3298 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
3300 for (unsigned fi = 0; fi < factor; ++fi)
3301 NewMask.push_back(Mask[i]);
3304 for (unsigned fi = 0; fi < factor; ++fi)
3305 NewMask.push_back(Mask[i]*factor+fi);
3313 unsigned NumElems = VT.getVectorNumElements();
3314 SmallVector<SDValue, 16> Ops;
3315 for (unsigned i = 0; i != NumElems; ++i) {
3317 Ops.push_back(DAG.getUNDEF(EltVT));
3320 unsigned Idx = Mask[i];
3322 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3324 DAG.getConstant(Idx, TLI.getVectorIdxTy())));
3326 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3328 DAG.getConstant(Idx - NumElems,
3329 TLI.getVectorIdxTy())));
3332 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
3333 // We may have changed the BUILD_VECTOR type. Cast it back to the Node type.
3334 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), Tmp1);
3335 Results.push_back(Tmp1);
3338 case ISD::EXTRACT_ELEMENT: {
3339 EVT OpTy = Node->getOperand(0).getValueType();
3340 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
3342 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
3343 DAG.getConstant(OpTy.getSizeInBits()/2,
3344 TLI.getShiftAmountTy(Node->getOperand(0).getValueType())));
3345 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
3348 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
3349 Node->getOperand(0));
3351 Results.push_back(Tmp1);
3354 case ISD::STACKSAVE:
3355 // Expand to CopyFromReg if the target set
3356 // StackPointerRegisterToSaveRestore.
3357 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3358 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
3359 Node->getValueType(0)));
3360 Results.push_back(Results[0].getValue(1));
3362 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
3363 Results.push_back(Node->getOperand(0));
3366 case ISD::STACKRESTORE:
3367 // Expand to CopyToReg if the target set
3368 // StackPointerRegisterToSaveRestore.
3369 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3370 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
3371 Node->getOperand(1)));
3373 Results.push_back(Node->getOperand(0));
3376 case ISD::FCOPYSIGN:
3377 Results.push_back(ExpandFCOPYSIGN(Node));
3380 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3381 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3382 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
3383 Node->getOperand(0));
3384 Results.push_back(Tmp1);
3387 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3388 EVT VT = Node->getValueType(0);
3389 Tmp1 = Node->getOperand(0);
3390 Tmp2 = DAG.getConstantFP(0.0, VT);
3391 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(Tmp1.getValueType()),
3392 Tmp1, Tmp2, ISD::SETUGT);
3393 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
3394 Tmp1 = DAG.getSelect(dl, VT, Tmp2, Tmp1, Tmp3);
3395 Results.push_back(Tmp1);
3399 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3400 RTLIB::SQRT_F80, RTLIB::SQRT_F128,
3401 RTLIB::SQRT_PPCF128));
3405 EVT VT = Node->getValueType(0);
3406 bool isSIN = Node->getOpcode() == ISD::FSIN;
3407 // Turn fsin / fcos into ISD::FSINCOS node if there are a pair of fsin /
3408 // fcos which share the same operand and both are used.
3409 if ((TLI.isOperationLegalOrCustom(ISD::FSINCOS, VT) ||
3410 canCombineSinCosLibcall(Node, TLI, TM))
3411 && useSinCos(Node)) {
3412 SDVTList VTs = DAG.getVTList(VT, VT);
3413 Tmp1 = DAG.getNode(ISD::FSINCOS, dl, VTs, Node->getOperand(0));
3415 Tmp1 = Tmp1.getValue(1);
3416 Results.push_back(Tmp1);
3418 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
3419 RTLIB::SIN_F80, RTLIB::SIN_F128,
3420 RTLIB::SIN_PPCF128));
3422 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
3423 RTLIB::COS_F80, RTLIB::COS_F128,
3424 RTLIB::COS_PPCF128));
3429 // Expand into sincos libcall.
3430 ExpandSinCosLibCall(Node, Results);
3433 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
3434 RTLIB::LOG_F80, RTLIB::LOG_F128,
3435 RTLIB::LOG_PPCF128));
3438 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3439 RTLIB::LOG2_F80, RTLIB::LOG2_F128,
3440 RTLIB::LOG2_PPCF128));
3443 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3444 RTLIB::LOG10_F80, RTLIB::LOG10_F128,
3445 RTLIB::LOG10_PPCF128));
3448 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
3449 RTLIB::EXP_F80, RTLIB::EXP_F128,
3450 RTLIB::EXP_PPCF128));
3453 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3454 RTLIB::EXP2_F80, RTLIB::EXP2_F128,
3455 RTLIB::EXP2_PPCF128));
3458 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3459 RTLIB::TRUNC_F80, RTLIB::TRUNC_F128,
3460 RTLIB::TRUNC_PPCF128));
3463 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3464 RTLIB::FLOOR_F80, RTLIB::FLOOR_F128,
3465 RTLIB::FLOOR_PPCF128));
3468 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3469 RTLIB::CEIL_F80, RTLIB::CEIL_F128,
3470 RTLIB::CEIL_PPCF128));
3473 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
3474 RTLIB::RINT_F80, RTLIB::RINT_F128,
3475 RTLIB::RINT_PPCF128));
3477 case ISD::FNEARBYINT:
3478 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
3479 RTLIB::NEARBYINT_F64,
3480 RTLIB::NEARBYINT_F80,
3481 RTLIB::NEARBYINT_F128,
3482 RTLIB::NEARBYINT_PPCF128));
3485 Results.push_back(ExpandFPLibCall(Node, RTLIB::ROUND_F32,
3489 RTLIB::ROUND_PPCF128));
3492 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
3493 RTLIB::POWI_F80, RTLIB::POWI_F128,
3494 RTLIB::POWI_PPCF128));
3497 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
3498 RTLIB::POW_F80, RTLIB::POW_F128,
3499 RTLIB::POW_PPCF128));
3502 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
3503 RTLIB::DIV_F80, RTLIB::DIV_F128,
3504 RTLIB::DIV_PPCF128));
3507 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
3508 RTLIB::REM_F80, RTLIB::REM_F128,
3509 RTLIB::REM_PPCF128));
3512 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMA_F32, RTLIB::FMA_F64,
3513 RTLIB::FMA_F80, RTLIB::FMA_F128,
3514 RTLIB::FMA_PPCF128));
3516 case ISD::FP16_TO_FP32:
3517 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
3519 case ISD::FP32_TO_FP16:
3520 Results.push_back(ExpandLibCall(RTLIB::FPROUND_F32_F16, Node, false));
3522 case ISD::ConstantFP: {
3523 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
3524 // Check to see if this FP immediate is already legal.
3525 // If this is a legal constant, turn it into a TargetConstantFP node.
3526 if (!TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
3527 Results.push_back(ExpandConstantFP(CFP, true));
3531 EVT VT = Node->getValueType(0);
3532 assert(TLI.isOperationLegalOrCustom(ISD::FADD, VT) &&
3533 TLI.isOperationLegalOrCustom(ISD::FNEG, VT) &&
3534 "Don't know how to expand this FP subtraction!");
3535 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1));
3536 Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1);
3537 Results.push_back(Tmp1);
3541 EVT VT = Node->getValueType(0);
3542 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3543 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3544 "Don't know how to expand this subtraction!");
3545 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3546 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
3547 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, VT));
3548 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3553 EVT VT = Node->getValueType(0);
3554 bool isSigned = Node->getOpcode() == ISD::SREM;
3555 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3556 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3557 Tmp2 = Node->getOperand(0);
3558 Tmp3 = Node->getOperand(1);
3559 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3560 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3561 // If div is legal, it's better to do the normal expansion
3562 !TLI.isOperationLegalOrCustom(DivOpc, Node->getValueType(0)) &&
3563 useDivRem(Node, isSigned, false))) {
3564 SDVTList VTs = DAG.getVTList(VT, VT);
3565 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
3566 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
3568 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
3569 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3570 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3571 } else if (isSigned)
3572 Tmp1 = ExpandIntLibCall(Node, true,
3574 RTLIB::SREM_I16, RTLIB::SREM_I32,
3575 RTLIB::SREM_I64, RTLIB::SREM_I128);
3577 Tmp1 = ExpandIntLibCall(Node, false,
3579 RTLIB::UREM_I16, RTLIB::UREM_I32,
3580 RTLIB::UREM_I64, RTLIB::UREM_I128);
3581 Results.push_back(Tmp1);
3586 bool isSigned = Node->getOpcode() == ISD::SDIV;
3587 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3588 EVT VT = Node->getValueType(0);
3589 SDVTList VTs = DAG.getVTList(VT, VT);
3590 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3591 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3592 useDivRem(Node, isSigned, true)))
3593 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
3594 Node->getOperand(1));
3596 Tmp1 = ExpandIntLibCall(Node, true,
3598 RTLIB::SDIV_I16, RTLIB::SDIV_I32,
3599 RTLIB::SDIV_I64, RTLIB::SDIV_I128);
3601 Tmp1 = ExpandIntLibCall(Node, false,
3603 RTLIB::UDIV_I16, RTLIB::UDIV_I32,
3604 RTLIB::UDIV_I64, RTLIB::UDIV_I128);
3605 Results.push_back(Tmp1);
3610 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
3612 EVT VT = Node->getValueType(0);
3613 SDVTList VTs = DAG.getVTList(VT, VT);
3614 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
3615 "If this wasn't legal, it shouldn't have been created!");
3616 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
3617 Node->getOperand(1));
3618 Results.push_back(Tmp1.getValue(1));
3623 // Expand into divrem libcall
3624 ExpandDivRemLibCall(Node, Results);
3627 EVT VT = Node->getValueType(0);
3628 SDVTList VTs = DAG.getVTList(VT, VT);
3629 // See if multiply or divide can be lowered using two-result operations.
3630 // We just need the low half of the multiply; try both the signed
3631 // and unsigned forms. If the target supports both SMUL_LOHI and
3632 // UMUL_LOHI, form a preference by checking which forms of plain
3633 // MULH it supports.
3634 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3635 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3636 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3637 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3638 unsigned OpToUse = 0;
3639 if (HasSMUL_LOHI && !HasMULHS) {
3640 OpToUse = ISD::SMUL_LOHI;
3641 } else if (HasUMUL_LOHI && !HasMULHU) {
3642 OpToUse = ISD::UMUL_LOHI;
3643 } else if (HasSMUL_LOHI) {
3644 OpToUse = ISD::SMUL_LOHI;
3645 } else if (HasUMUL_LOHI) {
3646 OpToUse = ISD::UMUL_LOHI;
3649 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
3650 Node->getOperand(1)));
3655 EVT HalfType = VT.getHalfSizedIntegerVT(*DAG.getContext());
3656 if (TLI.isOperationLegalOrCustom(ISD::ZERO_EXTEND, VT) &&
3657 TLI.isOperationLegalOrCustom(ISD::ANY_EXTEND, VT) &&
3658 TLI.isOperationLegalOrCustom(ISD::SHL, VT) &&
3659 TLI.isOperationLegalOrCustom(ISD::OR, VT) &&
3660 TLI.expandMUL(Node, Lo, Hi, HalfType, DAG)) {
3661 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Lo);
3662 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Hi);
3663 SDValue Shift = DAG.getConstant(HalfType.getSizeInBits(),
3664 TLI.getShiftAmountTy(HalfType));
3665 Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift);
3666 Results.push_back(DAG.getNode(ISD::OR, dl, VT, Lo, Hi));
3670 Tmp1 = ExpandIntLibCall(Node, false,
3672 RTLIB::MUL_I16, RTLIB::MUL_I32,
3673 RTLIB::MUL_I64, RTLIB::MUL_I128);
3674 Results.push_back(Tmp1);
3679 SDValue LHS = Node->getOperand(0);
3680 SDValue RHS = Node->getOperand(1);
3681 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3682 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3684 Results.push_back(Sum);
3685 EVT ResultType = Node->getValueType(1);
3686 EVT OType = getSetCCResultType(Node->getValueType(0));
3688 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
3690 // LHSSign -> LHS >= 0
3691 // RHSSign -> RHS >= 0
3692 // SumSign -> Sum >= 0
3695 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3697 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3699 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3700 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3701 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
3702 Node->getOpcode() == ISD::SADDO ?
3703 ISD::SETEQ : ISD::SETNE);
3705 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3706 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3708 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3709 Results.push_back(DAG.getBoolExtOrTrunc(Cmp, dl, ResultType, ResultType));
3714 SDValue LHS = Node->getOperand(0);
3715 SDValue RHS = Node->getOperand(1);
3716 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
3717 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3719 Results.push_back(Sum);
3721 EVT ResultType = Node->getValueType(1);
3722 EVT SetCCType = getSetCCResultType(Node->getValueType(0));
3724 = Node->getOpcode() == ISD::UADDO ? ISD::SETULT : ISD::SETUGT;
3725 SDValue SetCC = DAG.getSetCC(dl, SetCCType, Sum, LHS, CC);
3727 Results.push_back(DAG.getBoolExtOrTrunc(SetCC, dl, ResultType, ResultType));
3732 EVT VT = Node->getValueType(0);
3733 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
3734 SDValue LHS = Node->getOperand(0);
3735 SDValue RHS = Node->getOperand(1);
3738 static const unsigned Ops[2][3] =
3739 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
3740 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
3741 bool isSigned = Node->getOpcode() == ISD::SMULO;
3742 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3743 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3744 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3745 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3746 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3748 TopHalf = BottomHalf.getValue(1);
3749 } else if (TLI.isTypeLegal(WideVT)) {
3750 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
3751 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
3752 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
3753 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3754 DAG.getIntPtrConstant(0));
3755 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3756 DAG.getIntPtrConstant(1));
3758 // We can fall back to a libcall with an illegal type for the MUL if we
3759 // have a libcall big enough.
3760 // Also, we can fall back to a division in some cases, but that's a big
3761 // performance hit in the general case.
3762 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3763 if (WideVT == MVT::i16)
3764 LC = RTLIB::MUL_I16;
3765 else if (WideVT == MVT::i32)
3766 LC = RTLIB::MUL_I32;
3767 else if (WideVT == MVT::i64)
3768 LC = RTLIB::MUL_I64;
3769 else if (WideVT == MVT::i128)
3770 LC = RTLIB::MUL_I128;
3771 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!");
3773 // The high part is obtained by SRA'ing all but one of the bits of low
3775 unsigned LoSize = VT.getSizeInBits();
3776 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, RHS,
3777 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
3778 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, VT, LHS,
3779 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
3781 // Here we're passing the 2 arguments explicitly as 4 arguments that are
3782 // pre-lowered to the correct types. This all depends upon WideVT not
3783 // being a legal type for the architecture and thus has to be split to
3785 SDValue Args[] = { LHS, HiLHS, RHS, HiRHS };
3786 SDValue Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl);
3787 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3788 DAG.getIntPtrConstant(0));
3789 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3790 DAG.getIntPtrConstant(1));
3791 // Ret is a node with an illegal type. Because such things are not
3792 // generally permitted during this phase of legalization, delete the
3793 // node. The above EXTRACT_ELEMENT nodes should have been folded.
3794 DAG.DeleteNode(Ret.getNode());
3798 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1,
3799 TLI.getShiftAmountTy(BottomHalf.getValueType()));
3800 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3801 TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf, Tmp1,
3804 TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf,
3805 DAG.getConstant(0, VT), ISD::SETNE);
3807 Results.push_back(BottomHalf);
3808 Results.push_back(TopHalf);
3811 case ISD::BUILD_PAIR: {
3812 EVT PairTy = Node->getValueType(0);
3813 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3814 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3815 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
3816 DAG.getConstant(PairTy.getSizeInBits()/2,
3817 TLI.getShiftAmountTy(PairTy)));
3818 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3822 Tmp1 = Node->getOperand(0);
3823 Tmp2 = Node->getOperand(1);
3824 Tmp3 = Node->getOperand(2);
3825 if (Tmp1.getOpcode() == ISD::SETCC) {
3826 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3828 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3830 Tmp1 = DAG.getSelectCC(dl, Tmp1,
3831 DAG.getConstant(0, Tmp1.getValueType()),
3832 Tmp2, Tmp3, ISD::SETNE);
3834 Results.push_back(Tmp1);
3837 SDValue Chain = Node->getOperand(0);
3838 SDValue Table = Node->getOperand(1);
3839 SDValue Index = Node->getOperand(2);
3841 EVT PTy = TLI.getPointerTy();
3843 const DataLayout &TD = *TLI.getDataLayout();
3844 unsigned EntrySize =
3845 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
3847 Index = DAG.getNode(ISD::MUL, dl, Index.getValueType(),
3848 Index, DAG.getConstant(EntrySize, Index.getValueType()));
3849 SDValue Addr = DAG.getNode(ISD::ADD, dl, Index.getValueType(),
3852 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
3853 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
3854 MachinePointerInfo::getJumpTable(), MemVT,
3857 if (TM.getRelocationModel() == Reloc::PIC_) {
3858 // For PIC, the sequence is:
3859 // BRIND(load(Jumptable + index) + RelocBase)
3860 // RelocBase can be JumpTable, GOT or some sort of global base.
3861 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3862 TLI.getPICJumpTableRelocBase(Table, DAG));
3864 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
3865 Results.push_back(Tmp1);
3869 // Expand brcond's setcc into its constituent parts and create a BR_CC
3871 Tmp1 = Node->getOperand(0);
3872 Tmp2 = Node->getOperand(1);
3873 if (Tmp2.getOpcode() == ISD::SETCC) {
3874 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3875 Tmp1, Tmp2.getOperand(2),
3876 Tmp2.getOperand(0), Tmp2.getOperand(1),
3877 Node->getOperand(2));
3879 // We test only the i1 bit. Skip the AND if UNDEF.
3880 Tmp3 = (Tmp2.getOpcode() == ISD::UNDEF) ? Tmp2 :
3881 DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2,
3882 DAG.getConstant(1, Tmp2.getValueType()));
3883 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3884 DAG.getCondCode(ISD::SETNE), Tmp3,
3885 DAG.getConstant(0, Tmp3.getValueType()),
3886 Node->getOperand(2));
3888 Results.push_back(Tmp1);
3891 Tmp1 = Node->getOperand(0);
3892 Tmp2 = Node->getOperand(1);
3893 Tmp3 = Node->getOperand(2);
3894 bool Legalized = LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2,
3895 Tmp3, NeedInvert, dl);
3898 // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3899 // condition code, create a new SETCC node.
3901 Tmp1 = DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3904 // If we expanded the SETCC by inverting the condition code, then wrap
3905 // the existing SETCC in a NOT to restore the intended condition.
3907 Tmp1 = DAG.getLogicalNOT(dl, Tmp1, Tmp1->getValueType(0));
3909 Results.push_back(Tmp1);
3913 // Otherwise, SETCC for the given comparison type must be completely
3914 // illegal; expand it into a SELECT_CC.
3915 EVT VT = Node->getValueType(0);
3917 switch (TLI.getBooleanContents(Tmp1->getValueType(0))) {
3918 case TargetLowering::ZeroOrOneBooleanContent:
3919 case TargetLowering::UndefinedBooleanContent:
3922 case TargetLowering::ZeroOrNegativeOneBooleanContent:
3926 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3927 DAG.getConstant(TrueValue, VT), DAG.getConstant(0, VT),
3929 Results.push_back(Tmp1);
3932 case ISD::SELECT_CC: {
3933 Tmp1 = Node->getOperand(0); // LHS
3934 Tmp2 = Node->getOperand(1); // RHS
3935 Tmp3 = Node->getOperand(2); // True
3936 Tmp4 = Node->getOperand(3); // False
3937 EVT VT = Node->getValueType(0);
3938 SDValue CC = Node->getOperand(4);
3939 ISD::CondCode CCOp = cast<CondCodeSDNode>(CC)->get();
3941 if (TLI.isCondCodeLegal(CCOp, Tmp1.getSimpleValueType())) {
3942 // If the condition code is legal, then we need to expand this
3943 // node using SETCC and SELECT.
3944 EVT CmpVT = Tmp1.getValueType();
3945 assert(!TLI.isOperationExpand(ISD::SELECT, VT) &&
3946 "Cannot expand ISD::SELECT_CC when ISD::SELECT also needs to be "
3948 EVT CCVT = TLI.getSetCCResultType(*DAG.getContext(), CmpVT);
3949 SDValue Cond = DAG.getNode(ISD::SETCC, dl, CCVT, Tmp1, Tmp2, CC);
3950 Results.push_back(DAG.getSelect(dl, VT, Cond, Tmp3, Tmp4));
3954 // SELECT_CC is legal, so the condition code must not be.
3955 bool Legalized = false;
3956 // Try to legalize by inverting the condition. This is for targets that
3957 // might support an ordered version of a condition, but not the unordered
3958 // version (or vice versa).
3959 ISD::CondCode InvCC = ISD::getSetCCInverse(CCOp,
3960 Tmp1.getValueType().isInteger());
3961 if (TLI.isCondCodeLegal(InvCC, Tmp1.getSimpleValueType())) {
3962 // Use the new condition code and swap true and false
3964 Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp4, Tmp3, InvCC);
3966 // If The inverse is not legal, then try to swap the arguments using
3967 // the inverse condition code.
3968 ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(InvCC);
3969 if (TLI.isCondCodeLegal(SwapInvCC, Tmp1.getSimpleValueType())) {
3970 // The swapped inverse condition is legal, so swap true and false,
3973 Tmp1 = DAG.getSelectCC(dl, Tmp2, Tmp1, Tmp4, Tmp3, SwapInvCC);
3978 Legalized = LegalizeSetCCCondCode(
3979 getSetCCResultType(Tmp1.getValueType()), Tmp1, Tmp2, CC, NeedInvert,
3982 assert(Legalized && "Can't legalize SELECT_CC with legal condition!");
3984 // If we expanded the SETCC by inverting the condition code, then swap
3985 // the True/False operands to match.
3987 std::swap(Tmp3, Tmp4);
3989 // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3990 // condition code, create a new SELECT_CC node.
3992 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0),
3993 Tmp1, Tmp2, Tmp3, Tmp4, CC);
3995 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3996 CC = DAG.getCondCode(ISD::SETNE);
3997 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1,
3998 Tmp2, Tmp3, Tmp4, CC);
4001 Results.push_back(Tmp1);
4005 Tmp1 = Node->getOperand(0); // Chain
4006 Tmp2 = Node->getOperand(2); // LHS
4007 Tmp3 = Node->getOperand(3); // RHS
4008 Tmp4 = Node->getOperand(1); // CC
4010 bool Legalized = LegalizeSetCCCondCode(getSetCCResultType(
4011 Tmp2.getValueType()), Tmp2, Tmp3, Tmp4, NeedInvert, dl);
4013 assert(Legalized && "Can't legalize BR_CC with legal condition!");
4015 // If we expanded the SETCC by inverting the condition code, then wrap
4016 // the existing SETCC in a NOT to restore the intended condition.
4018 Tmp4 = DAG.getNOT(dl, Tmp4, Tmp4->getValueType(0));
4020 // If we expanded the SETCC by swapping LHS and RHS, create a new BR_CC
4022 if (Tmp4.getNode()) {
4023 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1,
4024 Tmp4, Tmp2, Tmp3, Node->getOperand(4));
4026 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
4027 Tmp4 = DAG.getCondCode(ISD::SETNE);
4028 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4,
4029 Tmp2, Tmp3, Node->getOperand(4));
4031 Results.push_back(Tmp1);
4034 case ISD::BUILD_VECTOR:
4035 Results.push_back(ExpandBUILD_VECTOR(Node));
4040 // Scalarize vector SRA/SRL/SHL.
4041 EVT VT = Node->getValueType(0);
4042 assert(VT.isVector() && "Unable to legalize non-vector shift");
4043 assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
4044 unsigned NumElem = VT.getVectorNumElements();
4046 SmallVector<SDValue, 8> Scalars;
4047 for (unsigned Idx = 0; Idx < NumElem; Idx++) {
4048 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
4050 Node->getOperand(0), DAG.getConstant(Idx,
4051 TLI.getVectorIdxTy()));
4052 SDValue Sh = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
4054 Node->getOperand(1), DAG.getConstant(Idx,
4055 TLI.getVectorIdxTy()));
4056 Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
4057 VT.getScalarType(), Ex, Sh));
4060 DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0), Scalars);
4061 ReplaceNode(SDValue(Node, 0), Result);
4064 case ISD::GLOBAL_OFFSET_TABLE:
4065 case ISD::GlobalAddress:
4066 case ISD::GlobalTLSAddress:
4067 case ISD::ExternalSymbol:
4068 case ISD::ConstantPool:
4069 case ISD::JumpTable:
4070 case ISD::INTRINSIC_W_CHAIN:
4071 case ISD::INTRINSIC_WO_CHAIN:
4072 case ISD::INTRINSIC_VOID:
4073 // FIXME: Custom lowering for these operations shouldn't return null!
4077 // Replace the original node with the legalized result.
4078 if (!Results.empty())
4079 ReplaceNode(Node, Results.data());
4082 void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
4083 SmallVector<SDValue, 8> Results;
4084 MVT OVT = Node->getSimpleValueType(0);
4085 if (Node->getOpcode() == ISD::UINT_TO_FP ||
4086 Node->getOpcode() == ISD::SINT_TO_FP ||
4087 Node->getOpcode() == ISD::SETCC) {
4088 OVT = Node->getOperand(0).getSimpleValueType();
4090 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
4092 SDValue Tmp1, Tmp2, Tmp3;
4093 switch (Node->getOpcode()) {
4095 case ISD::CTTZ_ZERO_UNDEF:
4097 case ISD::CTLZ_ZERO_UNDEF:
4099 // Zero extend the argument.
4100 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4101 // Perform the larger operation. For CTPOP and CTTZ_ZERO_UNDEF, this is
4102 // already the correct result.
4103 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4104 if (Node->getOpcode() == ISD::CTTZ) {
4105 // FIXME: This should set a bit in the zero extended value instead.
4106 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT),
4107 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
4109 Tmp1 = DAG.getSelect(dl, NVT, Tmp2,
4110 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
4111 } else if (Node->getOpcode() == ISD::CTLZ ||
4112 Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) {
4113 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4114 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
4115 DAG.getConstant(NVT.getSizeInBits() -
4116 OVT.getSizeInBits(), NVT));
4118 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
4121 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
4122 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4123 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
4124 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
4125 DAG.getConstant(DiffBits, TLI.getShiftAmountTy(NVT)));
4126 Results.push_back(Tmp1);
4129 case ISD::FP_TO_UINT:
4130 case ISD::FP_TO_SINT:
4131 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
4132 Node->getOpcode() == ISD::FP_TO_SINT, dl);
4133 Results.push_back(Tmp1);
4135 case ISD::UINT_TO_FP:
4136 case ISD::SINT_TO_FP:
4137 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
4138 Node->getOpcode() == ISD::SINT_TO_FP, dl);
4139 Results.push_back(Tmp1);
4142 SDValue Chain = Node->getOperand(0); // Get the chain.
4143 SDValue Ptr = Node->getOperand(1); // Get the pointer.
4146 if (OVT.isVector()) {
4147 TruncOp = ISD::BITCAST;
4149 assert(OVT.isInteger()
4150 && "VAARG promotion is supported only for vectors or integer types");
4151 TruncOp = ISD::TRUNCATE;
4154 // Perform the larger operation, then convert back
4155 Tmp1 = DAG.getVAArg(NVT, dl, Chain, Ptr, Node->getOperand(2),
4156 Node->getConstantOperandVal(3));
4157 Chain = Tmp1.getValue(1);
4159 Tmp2 = DAG.getNode(TruncOp, dl, OVT, Tmp1);
4161 // Modified the chain result - switch anything that used the old chain to
4163 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp2);
4164 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
4171 unsigned ExtOp, TruncOp;
4172 if (OVT.isVector()) {
4173 ExtOp = ISD::BITCAST;
4174 TruncOp = ISD::BITCAST;
4176 assert(OVT.isInteger() && "Cannot promote logic operation");
4177 ExtOp = ISD::ANY_EXTEND;
4178 TruncOp = ISD::TRUNCATE;
4180 // Promote each of the values to the new type.
4181 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4182 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4183 // Perform the larger operation, then convert back
4184 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4185 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
4189 unsigned ExtOp, TruncOp;
4190 if (Node->getValueType(0).isVector() ||
4191 Node->getValueType(0).getSizeInBits() == NVT.getSizeInBits()) {
4192 ExtOp = ISD::BITCAST;
4193 TruncOp = ISD::BITCAST;
4194 } else if (Node->getValueType(0).isInteger()) {
4195 ExtOp = ISD::ANY_EXTEND;
4196 TruncOp = ISD::TRUNCATE;
4198 ExtOp = ISD::FP_EXTEND;
4199 TruncOp = ISD::FP_ROUND;
4201 Tmp1 = Node->getOperand(0);
4202 // Promote each of the values to the new type.
4203 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4204 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
4205 // Perform the larger operation, then round down.
4206 Tmp1 = DAG.getSelect(dl, NVT, Tmp1, Tmp2, Tmp3);
4207 if (TruncOp != ISD::FP_ROUND)
4208 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
4210 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
4211 DAG.getIntPtrConstant(0));
4212 Results.push_back(Tmp1);
4215 case ISD::VECTOR_SHUFFLE: {
4216 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
4218 // Cast the two input vectors.
4219 Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
4220 Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
4222 // Convert the shuffle mask to the right # elements.
4223 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
4224 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
4225 Results.push_back(Tmp1);
4229 unsigned ExtOp = ISD::FP_EXTEND;
4230 if (NVT.isInteger()) {
4231 ISD::CondCode CCCode =
4232 cast<CondCodeSDNode>(Node->getOperand(2))->get();
4233 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4235 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4236 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4237 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
4238 Tmp1, Tmp2, Node->getOperand(2)));
4244 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4245 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
4246 Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4247 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4248 Tmp3, DAG.getIntPtrConstant(0)));
4255 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4256 Tmp2 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4257 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4258 Tmp2, DAG.getIntPtrConstant(0)));
4263 // Replace the original node with the legalized result.
4264 if (!Results.empty())
4265 ReplaceNode(Node, Results.data());
4268 // SelectionDAG::Legalize - This is the entry point for the file.
4270 void SelectionDAG::Legalize() {
4271 /// run - This is the main entry point to this class.
4273 SelectionDAGLegalize(*this).LegalizeDAG();