1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/CodeGen/PseudoSourceValue.h"
20 #include "llvm/Target/TargetFrameInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/Target/TargetData.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/Constants.h"
27 #include "llvm/DerivedTypes.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/Compiler.h"
30 #include "llvm/Support/MathExtras.h"
31 #include "llvm/ADT/DenseMap.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/SmallPtrSet.h"
39 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
40 cl::desc("Pop up a window to show dags before legalize"));
42 static const bool ViewLegalizeDAGs = 0;
45 //===----------------------------------------------------------------------===//
46 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
47 /// hacks on it until the target machine can handle it. This involves
48 /// eliminating value sizes the machine cannot handle (promoting small sizes to
49 /// large sizes or splitting up large values into small values) as well as
50 /// eliminating operations the machine cannot handle.
52 /// This code also does a small amount of optimization and recognition of idioms
53 /// as part of its processing. For example, if a target does not support a
54 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
55 /// will attempt merge setcc and brc instructions into brcc's.
58 class VISIBILITY_HIDDEN SelectionDAGLegalize {
62 // Libcall insertion helpers.
64 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
65 /// legalized. We use this to ensure that calls are properly serialized
66 /// against each other, including inserted libcalls.
67 SDOperand LastCALLSEQ_END;
69 /// IsLegalizingCall - This member is used *only* for purposes of providing
70 /// helpful assertions that a libcall isn't created while another call is
71 /// being legalized (which could lead to non-serialized call sequences).
72 bool IsLegalizingCall;
75 Legal, // The target natively supports this operation.
76 Promote, // This operation should be executed in a larger type.
77 Expand // Try to expand this to other ops, otherwise use a libcall.
80 /// ValueTypeActions - This is a bitvector that contains two bits for each
81 /// value type, where the two bits correspond to the LegalizeAction enum.
82 /// This can be queried with "getTypeAction(VT)".
83 TargetLowering::ValueTypeActionImpl ValueTypeActions;
85 /// LegalizedNodes - For nodes that are of legal width, and that have more
86 /// than one use, this map indicates what regularized operand to use. This
87 /// allows us to avoid legalizing the same thing more than once.
88 DenseMap<SDOperand, SDOperand> LegalizedNodes;
90 /// PromotedNodes - For nodes that are below legal width, and that have more
91 /// than one use, this map indicates what promoted value to use. This allows
92 /// us to avoid promoting the same thing more than once.
93 DenseMap<SDOperand, SDOperand> PromotedNodes;
95 /// ExpandedNodes - For nodes that need to be expanded this map indicates
96 /// which which operands are the expanded version of the input. This allows
97 /// us to avoid expanding the same node more than once.
98 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
100 /// SplitNodes - For vector nodes that need to be split, this map indicates
101 /// which which operands are the split version of the input. This allows us
102 /// to avoid splitting the same node more than once.
103 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
105 /// ScalarizedNodes - For nodes that need to be converted from vector types to
106 /// scalar types, this contains the mapping of ones we have already
107 /// processed to the result.
108 std::map<SDOperand, SDOperand> ScalarizedNodes;
110 void AddLegalizedOperand(SDOperand From, SDOperand To) {
111 LegalizedNodes.insert(std::make_pair(From, To));
112 // If someone requests legalization of the new node, return itself.
114 LegalizedNodes.insert(std::make_pair(To, To));
116 void AddPromotedOperand(SDOperand From, SDOperand To) {
117 bool isNew = PromotedNodes.insert(std::make_pair(From, To));
118 assert(isNew && "Got into the map somehow?");
119 // If someone requests legalization of the new node, return itself.
120 LegalizedNodes.insert(std::make_pair(To, To));
125 SelectionDAGLegalize(SelectionDAG &DAG);
127 /// getTypeAction - Return how we should legalize values of this type, either
128 /// it is already legal or we need to expand it into multiple registers of
129 /// smaller integer type, or we need to promote it to a larger type.
130 LegalizeAction getTypeAction(MVT::ValueType VT) const {
131 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
134 /// isTypeLegal - Return true if this type is legal on this target.
136 bool isTypeLegal(MVT::ValueType VT) const {
137 return getTypeAction(VT) == Legal;
143 /// HandleOp - Legalize, Promote, or Expand the specified operand as
144 /// appropriate for its type.
145 void HandleOp(SDOperand Op);
147 /// LegalizeOp - We know that the specified value has a legal type.
148 /// Recursively ensure that the operands have legal types, then return the
150 SDOperand LegalizeOp(SDOperand O);
152 /// UnrollVectorOp - We know that the given vector has a legal type, however
153 /// the operation it performs is not legal and is an operation that we have
154 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
155 /// operating on each element individually.
156 SDOperand UnrollVectorOp(SDOperand O);
158 /// PromoteOp - Given an operation that produces a value in an invalid type,
159 /// promote it to compute the value into a larger type. The produced value
160 /// will have the correct bits for the low portion of the register, but no
161 /// guarantee is made about the top bits: it may be zero, sign-extended, or
163 SDOperand PromoteOp(SDOperand O);
165 /// ExpandOp - Expand the specified SDOperand into its two component pieces
166 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
167 /// the LegalizeNodes map is filled in for any results that are not expanded,
168 /// the ExpandedNodes map is filled in for any results that are expanded, and
169 /// the Lo/Hi values are returned. This applies to integer types and Vector
171 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
173 /// SplitVectorOp - Given an operand of vector type, break it down into
174 /// two smaller values.
175 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
177 /// ScalarizeVectorOp - Given an operand of single-element vector type
178 /// (e.g. v1f32), convert it into the equivalent operation that returns a
179 /// scalar (e.g. f32) value.
180 SDOperand ScalarizeVectorOp(SDOperand O);
182 /// isShuffleLegal - Return true if a vector shuffle is legal with the
183 /// specified mask and type. Targets can specify exactly which masks they
184 /// support and the code generator is tasked with not creating illegal masks.
186 /// Note that this will also return true for shuffles that are promoted to a
189 /// If this is a legal shuffle, this method returns the (possibly promoted)
190 /// build_vector Mask. If it's not a legal shuffle, it returns null.
191 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
193 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
194 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
196 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
198 SDOperand ExpandLibCall(const char *Name, SDNode *Node, bool isSigned,
200 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
203 SDOperand EmitStackConvert(SDOperand SrcOp, MVT::ValueType SlotVT,
204 MVT::ValueType DestVT);
205 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
206 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
207 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
209 MVT::ValueType DestVT);
210 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
212 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
215 SDOperand ExpandBSWAP(SDOperand Op);
216 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
217 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
218 SDOperand &Lo, SDOperand &Hi);
219 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
220 SDOperand &Lo, SDOperand &Hi);
222 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op);
223 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
227 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
228 /// specified mask and type. Targets can specify exactly which masks they
229 /// support and the code generator is tasked with not creating illegal masks.
231 /// Note that this will also return true for shuffles that are promoted to a
233 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
234 SDOperand Mask) const {
235 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
237 case TargetLowering::Legal:
238 case TargetLowering::Custom:
240 case TargetLowering::Promote: {
241 // If this is promoted to a different type, convert the shuffle mask and
242 // ask if it is legal in the promoted type!
243 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
245 // If we changed # elements, change the shuffle mask.
246 unsigned NumEltsGrowth =
247 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
248 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
249 if (NumEltsGrowth > 1) {
250 // Renumber the elements.
251 SmallVector<SDOperand, 8> Ops;
252 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
253 SDOperand InOp = Mask.getOperand(i);
254 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
255 if (InOp.getOpcode() == ISD::UNDEF)
256 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
258 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
259 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
263 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
269 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
272 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
273 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
274 ValueTypeActions(TLI.getValueTypeActions()) {
275 assert(MVT::LAST_VALUETYPE <= 32 &&
276 "Too many value types for ValueTypeActions to hold!");
279 /// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order
280 /// contains all of a nodes operands before it contains the node.
281 static void ComputeTopDownOrdering(SelectionDAG &DAG,
282 SmallVector<SDNode*, 64> &Order) {
284 DenseMap<SDNode*, unsigned> Visited;
285 std::vector<SDNode*> Worklist;
286 Worklist.reserve(128);
288 // Compute ordering from all of the leaves in the graphs, those (like the
289 // entry node) that have no operands.
290 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
291 E = DAG.allnodes_end(); I != E; ++I) {
292 if (I->getNumOperands() == 0) {
294 Worklist.push_back(I);
298 while (!Worklist.empty()) {
299 SDNode *N = Worklist.back();
302 if (++Visited[N] != N->getNumOperands())
303 continue; // Haven't visited all operands yet
307 // Now that we have N in, add anything that uses it if all of their operands
309 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
311 Worklist.push_back(*UI);
314 assert(Order.size() == Visited.size() &&
316 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
317 "Error: DAG is cyclic!");
321 void SelectionDAGLegalize::LegalizeDAG() {
322 LastCALLSEQ_END = DAG.getEntryNode();
323 IsLegalizingCall = false;
325 // The legalize process is inherently a bottom-up recursive process (users
326 // legalize their uses before themselves). Given infinite stack space, we
327 // could just start legalizing on the root and traverse the whole graph. In
328 // practice however, this causes us to run out of stack space on large basic
329 // blocks. To avoid this problem, compute an ordering of the nodes where each
330 // node is only legalized after all of its operands are legalized.
331 SmallVector<SDNode*, 64> Order;
332 ComputeTopDownOrdering(DAG, Order);
334 for (unsigned i = 0, e = Order.size(); i != e; ++i)
335 HandleOp(SDOperand(Order[i], 0));
337 // Finally, it's possible the root changed. Get the new root.
338 SDOperand OldRoot = DAG.getRoot();
339 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
340 DAG.setRoot(LegalizedNodes[OldRoot]);
342 ExpandedNodes.clear();
343 LegalizedNodes.clear();
344 PromotedNodes.clear();
346 ScalarizedNodes.clear();
348 // Remove dead nodes now.
349 DAG.RemoveDeadNodes();
353 /// FindCallEndFromCallStart - Given a chained node that is part of a call
354 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
355 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
356 if (Node->getOpcode() == ISD::CALLSEQ_END)
358 if (Node->use_empty())
359 return 0; // No CallSeqEnd
361 // The chain is usually at the end.
362 SDOperand TheChain(Node, Node->getNumValues()-1);
363 if (TheChain.getValueType() != MVT::Other) {
364 // Sometimes it's at the beginning.
365 TheChain = SDOperand(Node, 0);
366 if (TheChain.getValueType() != MVT::Other) {
367 // Otherwise, hunt for it.
368 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
369 if (Node->getValueType(i) == MVT::Other) {
370 TheChain = SDOperand(Node, i);
374 // Otherwise, we walked into a node without a chain.
375 if (TheChain.getValueType() != MVT::Other)
380 for (SDNode::use_iterator UI = Node->use_begin(),
381 E = Node->use_end(); UI != E; ++UI) {
383 // Make sure to only follow users of our token chain.
385 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
386 if (User->getOperand(i) == TheChain)
387 if (SDNode *Result = FindCallEndFromCallStart(User))
393 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
394 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
395 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
396 assert(Node && "Didn't find callseq_start for a call??");
397 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
399 assert(Node->getOperand(0).getValueType() == MVT::Other &&
400 "Node doesn't have a token chain argument!");
401 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
404 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
405 /// see if any uses can reach Dest. If no dest operands can get to dest,
406 /// legalize them, legalize ourself, and return false, otherwise, return true.
408 /// Keep track of the nodes we fine that actually do lead to Dest in
409 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
411 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
412 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
413 if (N == Dest) return true; // N certainly leads to Dest :)
415 // If we've already processed this node and it does lead to Dest, there is no
416 // need to reprocess it.
417 if (NodesLeadingTo.count(N)) return true;
419 // If the first result of this node has been already legalized, then it cannot
421 switch (getTypeAction(N->getValueType(0))) {
423 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
426 if (PromotedNodes.count(SDOperand(N, 0))) return false;
429 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
433 // Okay, this node has not already been legalized. Check and legalize all
434 // operands. If none lead to Dest, then we can legalize this node.
435 bool OperandsLeadToDest = false;
436 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
437 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
438 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
440 if (OperandsLeadToDest) {
441 NodesLeadingTo.insert(N);
445 // Okay, this node looks safe, legalize it and return false.
446 HandleOp(SDOperand(N, 0));
450 /// HandleOp - Legalize, Promote, or Expand the specified operand as
451 /// appropriate for its type.
452 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
453 MVT::ValueType VT = Op.getValueType();
454 switch (getTypeAction(VT)) {
455 default: assert(0 && "Bad type action!");
456 case Legal: (void)LegalizeOp(Op); break;
457 case Promote: (void)PromoteOp(Op); break;
459 if (!MVT::isVector(VT)) {
460 // If this is an illegal scalar, expand it into its two component
463 if (Op.getOpcode() == ISD::TargetConstant)
464 break; // Allow illegal target nodes.
466 } else if (MVT::getVectorNumElements(VT) == 1) {
467 // If this is an illegal single element vector, convert it to a
469 (void)ScalarizeVectorOp(Op);
471 // Otherwise, this is an illegal multiple element vector.
472 // Split it in half and legalize both parts.
474 SplitVectorOp(Op, X, Y);
480 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
481 /// a load from the constant pool.
482 static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
483 SelectionDAG &DAG, TargetLowering &TLI) {
486 // If a FP immediate is precise when represented as a float and if the
487 // target can do an extending load from float to double, we put it into
488 // the constant pool as a float, even if it's is statically typed as a
490 MVT::ValueType VT = CFP->getValueType(0);
491 bool isDouble = VT == MVT::f64;
492 ConstantFP *LLVMC = ConstantFP::get(MVT::getTypeForValueType(VT),
495 if (VT!=MVT::f64 && VT!=MVT::f32)
496 assert(0 && "Invalid type expansion");
497 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt().getZExtValue(),
498 isDouble ? MVT::i64 : MVT::i32);
501 if (isDouble && CFP->isValueValidForType(MVT::f32, CFP->getValueAPF()) &&
502 // Only do this if the target has a native EXTLOAD instruction from f32.
503 // Do not try to be clever about long doubles (so far)
504 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) {
505 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC,Type::FloatTy));
510 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
512 return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
513 CPIdx, PseudoSourceValue::getConstantPool(),
516 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
517 PseudoSourceValue::getConstantPool(), 0);
522 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
525 SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT,
526 SelectionDAG &DAG, TargetLowering &TLI) {
527 MVT::ValueType VT = Node->getValueType(0);
528 MVT::ValueType SrcVT = Node->getOperand(1).getValueType();
529 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
530 "fcopysign expansion only supported for f32 and f64");
531 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
533 // First get the sign bit of second operand.
534 SDOperand Mask1 = (SrcVT == MVT::f64)
535 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
536 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
537 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
538 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
539 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
540 // Shift right or sign-extend it if the two operands have different types.
541 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT);
543 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
544 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
545 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
546 } else if (SizeDiff < 0)
547 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit);
549 // Clear the sign bit of first operand.
550 SDOperand Mask2 = (VT == MVT::f64)
551 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
552 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
553 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
554 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
555 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
557 // Or the value with the sign bit.
558 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
562 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
564 SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
565 TargetLowering &TLI) {
566 SDOperand Chain = ST->getChain();
567 SDOperand Ptr = ST->getBasePtr();
568 SDOperand Val = ST->getValue();
569 MVT::ValueType VT = Val.getValueType();
570 int Alignment = ST->getAlignment();
571 int SVOffset = ST->getSrcValueOffset();
572 if (MVT::isFloatingPoint(ST->getMemoryVT()) ||
573 MVT::isVector(ST->getMemoryVT())) {
574 // Expand to a bitconvert of the value to the integer type of the
575 // same size, then a (misaligned) int store.
576 MVT::ValueType intVT;
577 if (MVT::is128BitVector(VT) || VT == MVT::ppcf128 || VT == MVT::f128)
579 else if (MVT::is64BitVector(VT) || VT==MVT::f64)
581 else if (VT==MVT::f32)
584 assert(0 && "Unaligned store of unsupported type");
586 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val);
587 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(),
588 SVOffset, ST->isVolatile(), Alignment);
590 assert(MVT::isInteger(ST->getMemoryVT()) &&
591 !MVT::isVector(ST->getMemoryVT()) &&
592 "Unaligned store of unknown type.");
593 // Get the half-size VT
594 MVT::ValueType NewStoredVT = ST->getMemoryVT() - 1;
595 int NumBits = MVT::getSizeInBits(NewStoredVT);
596 int IncrementSize = NumBits / 8;
598 // Divide the stored value in two parts.
599 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
601 SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
603 // Store the two parts
604 SDOperand Store1, Store2;
605 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr,
606 ST->getSrcValue(), SVOffset, NewStoredVT,
607 ST->isVolatile(), Alignment);
608 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
609 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
610 Alignment = MinAlign(Alignment, IncrementSize);
611 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr,
612 ST->getSrcValue(), SVOffset + IncrementSize,
613 NewStoredVT, ST->isVolatile(), Alignment);
615 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2);
618 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
620 SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
621 TargetLowering &TLI) {
622 int SVOffset = LD->getSrcValueOffset();
623 SDOperand Chain = LD->getChain();
624 SDOperand Ptr = LD->getBasePtr();
625 MVT::ValueType VT = LD->getValueType(0);
626 MVT::ValueType LoadedVT = LD->getMemoryVT();
627 if (MVT::isFloatingPoint(VT) || MVT::isVector(VT)) {
628 // Expand to a (misaligned) integer load of the same size,
629 // then bitconvert to floating point or vector.
630 MVT::ValueType intVT;
631 if (MVT::is128BitVector(LoadedVT) ||
632 LoadedVT == MVT::ppcf128 || LoadedVT == MVT::f128)
634 else if (MVT::is64BitVector(LoadedVT) || LoadedVT == MVT::f64)
636 else if (LoadedVT == MVT::f32)
639 assert(0 && "Unaligned load of unsupported type");
641 SDOperand newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(),
642 SVOffset, LD->isVolatile(),
644 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad);
645 if (MVT::isFloatingPoint(VT) && LoadedVT != VT)
646 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result);
648 SDOperand Ops[] = { Result, Chain };
649 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
652 assert(MVT::isInteger(LoadedVT) && !MVT::isVector(LoadedVT) &&
653 "Unaligned load of unsupported type.");
655 // Compute the new VT that is half the size of the old one. This is an
657 unsigned NumBits = MVT::getSizeInBits(LoadedVT);
658 MVT::ValueType NewLoadedVT;
659 NewLoadedVT = MVT::getIntegerType(NumBits/2);
662 unsigned Alignment = LD->getAlignment();
663 unsigned IncrementSize = NumBits / 8;
664 ISD::LoadExtType HiExtType = LD->getExtensionType();
666 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
667 if (HiExtType == ISD::NON_EXTLOAD)
668 HiExtType = ISD::ZEXTLOAD;
670 // Load the value in two parts
672 if (TLI.isLittleEndian()) {
673 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
674 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
675 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
676 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
677 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(),
678 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
679 MinAlign(Alignment, IncrementSize));
681 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset,
682 NewLoadedVT,LD->isVolatile(), Alignment);
683 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
684 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
685 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
686 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
687 MinAlign(Alignment, IncrementSize));
690 // aggregate the two parts
691 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
692 SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
693 Result = DAG.getNode(ISD::OR, VT, Result, Lo);
695 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
698 SDOperand Ops[] = { Result, TF };
699 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2);
702 /// UnrollVectorOp - We know that the given vector has a legal type, however
703 /// the operation it performs is not legal and is an operation that we have
704 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
705 /// operating on each element individually.
706 SDOperand SelectionDAGLegalize::UnrollVectorOp(SDOperand Op) {
707 MVT::ValueType VT = Op.getValueType();
708 assert(isTypeLegal(VT) &&
709 "Caller should expand or promote operands that are not legal!");
710 assert(Op.Val->getNumValues() == 1 &&
711 "Can't unroll a vector with multiple results!");
712 unsigned NE = MVT::getVectorNumElements(VT);
713 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
715 SmallVector<SDOperand, 8> Scalars;
716 SmallVector<SDOperand, 4> Operands(Op.getNumOperands());
717 for (unsigned i = 0; i != NE; ++i) {
718 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
719 SDOperand Operand = Op.getOperand(j);
720 MVT::ValueType OperandVT = Operand.getValueType();
721 if (MVT::isVector(OperandVT)) {
722 // A vector operand; extract a single element.
723 MVT::ValueType OperandEltVT = MVT::getVectorElementType(OperandVT);
724 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
727 DAG.getConstant(i, MVT::i32));
729 // A scalar operand; just use it as is.
730 Operands[j] = Operand;
733 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT,
734 &Operands[0], Operands.size()));
737 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size());
740 /// GetFPLibCall - Return the right libcall for the given floating point type.
741 static RTLIB::Libcall GetFPLibCall(MVT::ValueType VT,
742 RTLIB::Libcall Call_F32,
743 RTLIB::Libcall Call_F64,
744 RTLIB::Libcall Call_F80,
745 RTLIB::Libcall Call_PPCF128) {
747 VT == MVT::f32 ? Call_F32 :
748 VT == MVT::f64 ? Call_F64 :
749 VT == MVT::f80 ? Call_F80 :
750 VT == MVT::ppcf128 ? Call_PPCF128 :
751 RTLIB::UNKNOWN_LIBCALL;
754 /// LegalizeOp - We know that the specified value has a legal type, and
755 /// that its operands are legal. Now ensure that the operation itself
756 /// is legal, recursively ensuring that the operands' operations remain
758 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
759 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
762 assert(isTypeLegal(Op.getValueType()) &&
763 "Caller should expand or promote operands that are not legal!");
764 SDNode *Node = Op.Val;
766 // If this operation defines any values that cannot be represented in a
767 // register on this target, make sure to expand or promote them.
768 if (Node->getNumValues() > 1) {
769 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
770 if (getTypeAction(Node->getValueType(i)) != Legal) {
771 HandleOp(Op.getValue(i));
772 assert(LegalizedNodes.count(Op) &&
773 "Handling didn't add legal operands!");
774 return LegalizedNodes[Op];
778 // Note that LegalizeOp may be reentered even from single-use nodes, which
779 // means that we always must cache transformed nodes.
780 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
781 if (I != LegalizedNodes.end()) return I->second;
783 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
784 SDOperand Result = Op;
785 bool isCustom = false;
787 switch (Node->getOpcode()) {
788 case ISD::FrameIndex:
789 case ISD::EntryToken:
791 case ISD::BasicBlock:
792 case ISD::TargetFrameIndex:
793 case ISD::TargetJumpTable:
794 case ISD::TargetConstant:
795 case ISD::TargetConstantFP:
796 case ISD::TargetConstantPool:
797 case ISD::TargetGlobalAddress:
798 case ISD::TargetGlobalTLSAddress:
799 case ISD::TargetExternalSymbol:
802 case ISD::MEMOPERAND:
805 // Primitives must all be legal.
806 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
807 "This must be legal!");
810 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
811 // If this is a target node, legalize it by legalizing the operands then
812 // passing it through.
813 SmallVector<SDOperand, 8> Ops;
814 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
815 Ops.push_back(LegalizeOp(Node->getOperand(i)));
817 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
819 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
820 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
821 return Result.getValue(Op.ResNo);
823 // Otherwise this is an unhandled builtin node. splat.
825 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
827 assert(0 && "Do not know how to legalize this operator!");
829 case ISD::GLOBAL_OFFSET_TABLE:
830 case ISD::GlobalAddress:
831 case ISD::GlobalTLSAddress:
832 case ISD::ExternalSymbol:
833 case ISD::ConstantPool:
834 case ISD::JumpTable: // Nothing to do.
835 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
836 default: assert(0 && "This action is not supported yet!");
837 case TargetLowering::Custom:
838 Tmp1 = TLI.LowerOperation(Op, DAG);
839 if (Tmp1.Val) Result = Tmp1;
840 // FALLTHROUGH if the target doesn't want to lower this op after all.
841 case TargetLowering::Legal:
846 case ISD::RETURNADDR:
847 // The only option for these nodes is to custom lower them. If the target
848 // does not custom lower them, then return zero.
849 Tmp1 = TLI.LowerOperation(Op, DAG);
853 Result = DAG.getConstant(0, TLI.getPointerTy());
855 case ISD::FRAME_TO_ARGS_OFFSET: {
856 MVT::ValueType VT = Node->getValueType(0);
857 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
858 default: assert(0 && "This action is not supported yet!");
859 case TargetLowering::Custom:
860 Result = TLI.LowerOperation(Op, DAG);
861 if (Result.Val) break;
863 case TargetLowering::Legal:
864 Result = DAG.getConstant(0, VT);
869 case ISD::EXCEPTIONADDR: {
870 Tmp1 = LegalizeOp(Node->getOperand(0));
871 MVT::ValueType VT = Node->getValueType(0);
872 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
873 default: assert(0 && "This action is not supported yet!");
874 case TargetLowering::Expand: {
875 unsigned Reg = TLI.getExceptionAddressRegister();
876 Result = DAG.getCopyFromReg(Tmp1, Reg, VT);
879 case TargetLowering::Custom:
880 Result = TLI.LowerOperation(Op, DAG);
881 if (Result.Val) break;
883 case TargetLowering::Legal: {
884 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 };
885 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
891 if (Result.Val->getNumValues() == 1) break;
893 assert(Result.Val->getNumValues() == 2 &&
894 "Cannot return more than two values!");
896 // Since we produced two values, make sure to remember that we
897 // legalized both of them.
898 Tmp1 = LegalizeOp(Result);
899 Tmp2 = LegalizeOp(Result.getValue(1));
900 AddLegalizedOperand(Op.getValue(0), Tmp1);
901 AddLegalizedOperand(Op.getValue(1), Tmp2);
902 return Op.ResNo ? Tmp2 : Tmp1;
903 case ISD::EHSELECTION: {
904 Tmp1 = LegalizeOp(Node->getOperand(0));
905 Tmp2 = LegalizeOp(Node->getOperand(1));
906 MVT::ValueType VT = Node->getValueType(0);
907 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
908 default: assert(0 && "This action is not supported yet!");
909 case TargetLowering::Expand: {
910 unsigned Reg = TLI.getExceptionSelectorRegister();
911 Result = DAG.getCopyFromReg(Tmp2, Reg, VT);
914 case TargetLowering::Custom:
915 Result = TLI.LowerOperation(Op, DAG);
916 if (Result.Val) break;
918 case TargetLowering::Legal: {
919 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 };
920 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
926 if (Result.Val->getNumValues() == 1) break;
928 assert(Result.Val->getNumValues() == 2 &&
929 "Cannot return more than two values!");
931 // Since we produced two values, make sure to remember that we
932 // legalized both of them.
933 Tmp1 = LegalizeOp(Result);
934 Tmp2 = LegalizeOp(Result.getValue(1));
935 AddLegalizedOperand(Op.getValue(0), Tmp1);
936 AddLegalizedOperand(Op.getValue(1), Tmp2);
937 return Op.ResNo ? Tmp2 : Tmp1;
938 case ISD::EH_RETURN: {
939 MVT::ValueType VT = Node->getValueType(0);
940 // The only "good" option for this node is to custom lower it.
941 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
942 default: assert(0 && "This action is not supported at all!");
943 case TargetLowering::Custom:
944 Result = TLI.LowerOperation(Op, DAG);
945 if (Result.Val) break;
947 case TargetLowering::Legal:
948 // Target does not know, how to lower this, lower to noop
949 Result = LegalizeOp(Node->getOperand(0));
954 case ISD::AssertSext:
955 case ISD::AssertZext:
956 Tmp1 = LegalizeOp(Node->getOperand(0));
957 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
959 case ISD::MERGE_VALUES:
960 // Legalize eliminates MERGE_VALUES nodes.
961 Result = Node->getOperand(Op.ResNo);
963 case ISD::CopyFromReg:
964 Tmp1 = LegalizeOp(Node->getOperand(0));
965 Result = Op.getValue(0);
966 if (Node->getNumValues() == 2) {
967 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
969 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
970 if (Node->getNumOperands() == 3) {
971 Tmp2 = LegalizeOp(Node->getOperand(2));
972 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
974 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
976 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
978 // Since CopyFromReg produces two values, make sure to remember that we
979 // legalized both of them.
980 AddLegalizedOperand(Op.getValue(0), Result);
981 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
982 return Result.getValue(Op.ResNo);
984 MVT::ValueType VT = Op.getValueType();
985 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
986 default: assert(0 && "This action is not supported yet!");
987 case TargetLowering::Expand:
988 if (MVT::isInteger(VT))
989 Result = DAG.getConstant(0, VT);
990 else if (MVT::isFloatingPoint(VT))
991 Result = DAG.getConstantFP(APFloat(APInt(MVT::getSizeInBits(VT), 0)),
994 assert(0 && "Unknown value type!");
996 case TargetLowering::Legal:
1002 case ISD::INTRINSIC_W_CHAIN:
1003 case ISD::INTRINSIC_WO_CHAIN:
1004 case ISD::INTRINSIC_VOID: {
1005 SmallVector<SDOperand, 8> Ops;
1006 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1007 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1008 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1010 // Allow the target to custom lower its intrinsics if it wants to.
1011 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
1012 TargetLowering::Custom) {
1013 Tmp3 = TLI.LowerOperation(Result, DAG);
1014 if (Tmp3.Val) Result = Tmp3;
1017 if (Result.Val->getNumValues() == 1) break;
1019 // Must have return value and chain result.
1020 assert(Result.Val->getNumValues() == 2 &&
1021 "Cannot return more than two values!");
1023 // Since loads produce two values, make sure to remember that we
1024 // legalized both of them.
1025 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1026 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1027 return Result.getValue(Op.ResNo);
1031 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
1032 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
1034 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
1035 case TargetLowering::Promote:
1036 default: assert(0 && "This action is not supported yet!");
1037 case TargetLowering::Expand: {
1038 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
1039 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
1040 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other);
1042 if (MMI && (useDEBUG_LOC || useLABEL)) {
1043 const std::string &FName =
1044 cast<StringSDNode>(Node->getOperand(3))->getValue();
1045 const std::string &DirName =
1046 cast<StringSDNode>(Node->getOperand(4))->getValue();
1047 unsigned SrcFile = MMI->RecordSource(DirName, FName);
1049 SmallVector<SDOperand, 8> Ops;
1050 Ops.push_back(Tmp1); // chain
1051 SDOperand LineOp = Node->getOperand(1);
1052 SDOperand ColOp = Node->getOperand(2);
1055 Ops.push_back(LineOp); // line #
1056 Ops.push_back(ColOp); // col #
1057 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
1058 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
1060 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
1061 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
1062 unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile);
1063 Ops.push_back(DAG.getConstant(ID, MVT::i32));
1064 Ops.push_back(DAG.getConstant(0, MVT::i32)); // a debug label
1065 Result = DAG.getNode(ISD::LABEL, MVT::Other, &Ops[0], Ops.size());
1068 Result = Tmp1; // chain
1072 case TargetLowering::Legal:
1073 if (Tmp1 != Node->getOperand(0) ||
1074 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
1075 SmallVector<SDOperand, 8> Ops;
1076 Ops.push_back(Tmp1);
1077 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
1078 Ops.push_back(Node->getOperand(1)); // line # must be legal.
1079 Ops.push_back(Node->getOperand(2)); // col # must be legal.
1081 // Otherwise promote them.
1082 Ops.push_back(PromoteOp(Node->getOperand(1)));
1083 Ops.push_back(PromoteOp(Node->getOperand(2)));
1085 Ops.push_back(Node->getOperand(3)); // filename must be legal.
1086 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
1087 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1094 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!");
1095 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) {
1096 default: assert(0 && "This action is not supported yet!");
1097 case TargetLowering::Legal:
1098 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1099 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1100 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable.
1101 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1103 case TargetLowering::Expand:
1104 Result = LegalizeOp(Node->getOperand(0));
1109 case ISD::DEBUG_LOC:
1110 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
1111 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
1112 default: assert(0 && "This action is not supported yet!");
1113 case TargetLowering::Legal:
1114 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1115 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1116 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1117 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1118 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1124 assert(Node->getNumOperands() == 3 && "Invalid LABEL node!");
1125 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) {
1126 default: assert(0 && "This action is not supported yet!");
1127 case TargetLowering::Legal:
1128 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1129 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
1130 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the "flavor" operand.
1131 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1133 case TargetLowering::Expand:
1134 Result = LegalizeOp(Node->getOperand(0));
1139 case ISD::MEMBARRIER: {
1140 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!");
1141 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) {
1142 default: assert(0 && "This action is not supported yet!");
1143 case TargetLowering::Legal: {
1145 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1146 for (int x = 1; x < 6; ++x) {
1147 Ops[x] = Node->getOperand(x);
1148 if (!isTypeLegal(Ops[x].getValueType()))
1149 Ops[x] = PromoteOp(Ops[x]);
1151 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6);
1154 case TargetLowering::Expand:
1155 //There is no libgcc call for this op
1156 Result = Node->getOperand(0); // Noop
1162 case ISD::ATOMIC_LCS:
1163 case ISD::ATOMIC_LAS:
1164 case ISD::ATOMIC_SWAP: {
1165 assert(((Node->getNumOperands() == 4 && Node->getOpcode() == ISD::ATOMIC_LCS) ||
1166 (Node->getNumOperands() == 3 && Node->getOpcode() == ISD::ATOMIC_LAS) ||
1167 (Node->getNumOperands() == 3 && Node->getOpcode() == ISD::ATOMIC_SWAP)) &&
1168 "Invalid Atomic node!");
1169 int num = Node->getOpcode() == ISD::ATOMIC_LCS ? 4 : 3;
1171 for (int x = 0; x < num; ++x)
1172 Ops[x] = LegalizeOp(Node->getOperand(x));
1173 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num);
1175 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1176 default: assert(0 && "This action is not supported yet!");
1177 case TargetLowering::Custom:
1178 Result = TLI.LowerOperation(Result, DAG);
1180 case TargetLowering::Legal:
1183 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1184 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1185 return Result.getValue(Op.ResNo);
1188 case ISD::Constant: {
1189 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1191 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1193 // We know we don't need to expand constants here, constants only have one
1194 // value and we check that it is fine above.
1196 if (opAction == TargetLowering::Custom) {
1197 Tmp1 = TLI.LowerOperation(Result, DAG);
1203 case ISD::ConstantFP: {
1204 // Spill FP immediates to the constant pool if the target cannot directly
1205 // codegen them. Targets often have some immediate values that can be
1206 // efficiently generated into an FP register without a load. We explicitly
1207 // leave these constants as ConstantFP nodes for the target to deal with.
1208 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1210 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1211 default: assert(0 && "This action is not supported yet!");
1212 case TargetLowering::Legal:
1214 case TargetLowering::Custom:
1215 Tmp3 = TLI.LowerOperation(Result, DAG);
1221 case TargetLowering::Expand: {
1222 // Check to see if this FP immediate is already legal.
1223 bool isLegal = false;
1224 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1225 E = TLI.legal_fpimm_end(); I != E; ++I) {
1226 if (CFP->isExactlyValue(*I)) {
1231 // If this is a legal constant, turn it into a TargetConstantFP node.
1234 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1239 case ISD::TokenFactor:
1240 if (Node->getNumOperands() == 2) {
1241 Tmp1 = LegalizeOp(Node->getOperand(0));
1242 Tmp2 = LegalizeOp(Node->getOperand(1));
1243 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1244 } else if (Node->getNumOperands() == 3) {
1245 Tmp1 = LegalizeOp(Node->getOperand(0));
1246 Tmp2 = LegalizeOp(Node->getOperand(1));
1247 Tmp3 = LegalizeOp(Node->getOperand(2));
1248 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1250 SmallVector<SDOperand, 8> Ops;
1251 // Legalize the operands.
1252 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1253 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1254 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1258 case ISD::FORMAL_ARGUMENTS:
1260 // The only option for this is to custom lower it.
1261 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1262 assert(Tmp3.Val && "Target didn't custom lower this node!");
1264 // The number of incoming and outgoing values should match; unless the final
1265 // outgoing value is a flag.
1266 assert((Tmp3.Val->getNumValues() == Result.Val->getNumValues() ||
1267 (Tmp3.Val->getNumValues() == Result.Val->getNumValues() + 1 &&
1268 Tmp3.Val->getValueType(Tmp3.Val->getNumValues() - 1) ==
1270 "Lowering call/formal_arguments produced unexpected # results!");
1272 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1273 // remember that we legalized all of them, so it doesn't get relegalized.
1274 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
1275 if (Tmp3.Val->getValueType(i) == MVT::Flag)
1277 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1280 AddLegalizedOperand(SDOperand(Node, i), Tmp1);
1283 case ISD::EXTRACT_SUBREG: {
1284 Tmp1 = LegalizeOp(Node->getOperand(0));
1285 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1286 assert(idx && "Operand must be a constant");
1287 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1288 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1291 case ISD::INSERT_SUBREG: {
1292 Tmp1 = LegalizeOp(Node->getOperand(0));
1293 Tmp2 = LegalizeOp(Node->getOperand(1));
1294 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1295 assert(idx && "Operand must be a constant");
1296 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1297 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1300 case ISD::BUILD_VECTOR:
1301 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1302 default: assert(0 && "This action is not supported yet!");
1303 case TargetLowering::Custom:
1304 Tmp3 = TLI.LowerOperation(Result, DAG);
1310 case TargetLowering::Expand:
1311 Result = ExpandBUILD_VECTOR(Result.Val);
1315 case ISD::INSERT_VECTOR_ELT:
1316 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1317 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1319 // The type of the value to insert may not be legal, even though the vector
1320 // type is legal. Legalize/Promote accordingly. We do not handle Expand
1322 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1323 default: assert(0 && "Cannot expand insert element operand");
1324 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
1325 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
1327 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1329 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1330 Node->getValueType(0))) {
1331 default: assert(0 && "This action is not supported yet!");
1332 case TargetLowering::Legal:
1334 case TargetLowering::Custom:
1335 Tmp4 = TLI.LowerOperation(Result, DAG);
1341 case TargetLowering::Expand: {
1342 // If the insert index is a constant, codegen this as a scalar_to_vector,
1343 // then a shuffle that inserts it into the right position in the vector.
1344 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1345 // SCALAR_TO_VECTOR requires that the type of the value being inserted
1346 // match the element type of the vector being created.
1347 if (Tmp2.getValueType() ==
1348 MVT::getVectorElementType(Op.getValueType())) {
1349 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
1350 Tmp1.getValueType(), Tmp2);
1352 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
1353 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
1354 MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT);
1356 // We generate a shuffle of InVec and ScVec, so the shuffle mask
1357 // should be 0,1,2,3,4,5... with the appropriate element replaced with
1358 // elt 0 of the RHS.
1359 SmallVector<SDOperand, 8> ShufOps;
1360 for (unsigned i = 0; i != NumElts; ++i) {
1361 if (i != InsertPos->getValue())
1362 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1364 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1366 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1367 &ShufOps[0], ShufOps.size());
1369 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1370 Tmp1, ScVec, ShufMask);
1371 Result = LegalizeOp(Result);
1376 // If the target doesn't support this, we have to spill the input vector
1377 // to a temporary stack slot, update the element, then reload it. This is
1378 // badness. We could also load the value into a vector register (either
1379 // with a "move to register" or "extload into register" instruction, then
1380 // permute it into place, if the idx is a constant and if the idx is
1381 // supported by the target.
1382 MVT::ValueType VT = Tmp1.getValueType();
1383 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
1384 MVT::ValueType IdxVT = Tmp3.getValueType();
1385 MVT::ValueType PtrVT = TLI.getPointerTy();
1386 SDOperand StackPtr = DAG.CreateStackTemporary(VT);
1388 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr.Val);
1389 int SPFI = StackPtrFI->getIndex();
1391 // Store the vector.
1392 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr,
1393 PseudoSourceValue::getFixedStack(),
1396 // Truncate or zero extend offset to target pointer type.
1397 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
1398 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
1399 // Add the offset to the index.
1400 unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
1401 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
1402 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
1403 // Store the scalar value.
1404 Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2,
1405 PseudoSourceValue::getFixedStack(), SPFI, EltVT);
1406 // Load the updated vector.
1407 Result = DAG.getLoad(VT, Ch, StackPtr,
1408 PseudoSourceValue::getFixedStack(), SPFI);
1413 case ISD::SCALAR_TO_VECTOR:
1414 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1415 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1419 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1420 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1421 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1422 Node->getValueType(0))) {
1423 default: assert(0 && "This action is not supported yet!");
1424 case TargetLowering::Legal:
1426 case TargetLowering::Custom:
1427 Tmp3 = TLI.LowerOperation(Result, DAG);
1433 case TargetLowering::Expand:
1434 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1438 case ISD::VECTOR_SHUFFLE:
1439 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1440 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1441 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1443 // Allow targets to custom lower the SHUFFLEs they support.
1444 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1445 default: assert(0 && "Unknown operation action!");
1446 case TargetLowering::Legal:
1447 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1448 "vector shuffle should not be created if not legal!");
1450 case TargetLowering::Custom:
1451 Tmp3 = TLI.LowerOperation(Result, DAG);
1457 case TargetLowering::Expand: {
1458 MVT::ValueType VT = Node->getValueType(0);
1459 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
1460 MVT::ValueType PtrVT = TLI.getPointerTy();
1461 SDOperand Mask = Node->getOperand(2);
1462 unsigned NumElems = Mask.getNumOperands();
1463 SmallVector<SDOperand,8> Ops;
1464 for (unsigned i = 0; i != NumElems; ++i) {
1465 SDOperand Arg = Mask.getOperand(i);
1466 if (Arg.getOpcode() == ISD::UNDEF) {
1467 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1469 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1470 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
1472 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1473 DAG.getConstant(Idx, PtrVT)));
1475 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1476 DAG.getConstant(Idx - NumElems, PtrVT)));
1479 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1482 case TargetLowering::Promote: {
1483 // Change base type to a different vector type.
1484 MVT::ValueType OVT = Node->getValueType(0);
1485 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1487 // Cast the two input vectors.
1488 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1489 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1491 // Convert the shuffle mask to the right # elements.
1492 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1493 assert(Tmp3.Val && "Shuffle not legal?");
1494 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1495 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1501 case ISD::EXTRACT_VECTOR_ELT:
1502 Tmp1 = Node->getOperand(0);
1503 Tmp2 = LegalizeOp(Node->getOperand(1));
1504 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1505 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1508 case ISD::EXTRACT_SUBVECTOR:
1509 Tmp1 = Node->getOperand(0);
1510 Tmp2 = LegalizeOp(Node->getOperand(1));
1511 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1512 Result = ExpandEXTRACT_SUBVECTOR(Result);
1515 case ISD::CALLSEQ_START: {
1516 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1518 // Recursively Legalize all of the inputs of the call end that do not lead
1519 // to this call start. This ensures that any libcalls that need be inserted
1520 // are inserted *before* the CALLSEQ_START.
1521 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1522 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1523 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
1527 // Now that we legalized all of the inputs (which may have inserted
1528 // libcalls) create the new CALLSEQ_START node.
1529 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1531 // Merge in the last call, to ensure that this call start after the last
1533 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1534 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1535 Tmp1 = LegalizeOp(Tmp1);
1538 // Do not try to legalize the target-specific arguments (#1+).
1539 if (Tmp1 != Node->getOperand(0)) {
1540 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1542 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1545 // Remember that the CALLSEQ_START is legalized.
1546 AddLegalizedOperand(Op.getValue(0), Result);
1547 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1548 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1550 // Now that the callseq_start and all of the non-call nodes above this call
1551 // sequence have been legalized, legalize the call itself. During this
1552 // process, no libcalls can/will be inserted, guaranteeing that no calls
1554 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1555 SDOperand InCallSEQ = LastCALLSEQ_END;
1556 // Note that we are selecting this call!
1557 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1558 IsLegalizingCall = true;
1560 // Legalize the call, starting from the CALLSEQ_END.
1561 LegalizeOp(LastCALLSEQ_END);
1562 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1565 case ISD::CALLSEQ_END:
1566 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1567 // will cause this node to be legalized as well as handling libcalls right.
1568 if (LastCALLSEQ_END.Val != Node) {
1569 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1570 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1571 assert(I != LegalizedNodes.end() &&
1572 "Legalizing the call start should have legalized this node!");
1576 // Otherwise, the call start has been legalized and everything is going
1577 // according to plan. Just legalize ourselves normally here.
1578 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1579 // Do not try to legalize the target-specific arguments (#1+), except for
1580 // an optional flag input.
1581 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1582 if (Tmp1 != Node->getOperand(0)) {
1583 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1585 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1588 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1589 if (Tmp1 != Node->getOperand(0) ||
1590 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1591 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1594 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1597 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1598 // This finishes up call legalization.
1599 IsLegalizingCall = false;
1601 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1602 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1603 if (Node->getNumValues() == 2)
1604 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1605 return Result.getValue(Op.ResNo);
1606 case ISD::DYNAMIC_STACKALLOC: {
1607 MVT::ValueType VT = Node->getValueType(0);
1608 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1609 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1610 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1611 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1613 Tmp1 = Result.getValue(0);
1614 Tmp2 = Result.getValue(1);
1615 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1616 default: assert(0 && "This action is not supported yet!");
1617 case TargetLowering::Expand: {
1618 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1619 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1620 " not tell us which reg is the stack pointer!");
1621 SDOperand Chain = Tmp1.getOperand(0);
1623 // Chain the dynamic stack allocation so that it doesn't modify the stack
1624 // pointer when other instructions are using the stack.
1625 Chain = DAG.getCALLSEQ_START(Chain,
1626 DAG.getConstant(0, TLI.getPointerTy()));
1628 SDOperand Size = Tmp2.getOperand(1);
1629 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT);
1630 Chain = SP.getValue(1);
1631 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue();
1632 unsigned StackAlign =
1633 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1634 if (Align > StackAlign)
1635 SP = DAG.getNode(ISD::AND, VT, SP,
1636 DAG.getConstant(-(uint64_t)Align, VT));
1637 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value
1638 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
1641 DAG.getCALLSEQ_END(Chain,
1642 DAG.getConstant(0, TLI.getPointerTy()),
1643 DAG.getConstant(0, TLI.getPointerTy()),
1646 Tmp1 = LegalizeOp(Tmp1);
1647 Tmp2 = LegalizeOp(Tmp2);
1650 case TargetLowering::Custom:
1651 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1653 Tmp1 = LegalizeOp(Tmp3);
1654 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1657 case TargetLowering::Legal:
1660 // Since this op produce two values, make sure to remember that we
1661 // legalized both of them.
1662 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1663 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1664 return Op.ResNo ? Tmp2 : Tmp1;
1666 case ISD::INLINEASM: {
1667 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1668 bool Changed = false;
1669 // Legalize all of the operands of the inline asm, in case they are nodes
1670 // that need to be expanded or something. Note we skip the asm string and
1671 // all of the TargetConstant flags.
1672 SDOperand Op = LegalizeOp(Ops[0]);
1673 Changed = Op != Ops[0];
1676 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1677 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1678 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1679 for (++i; NumVals; ++i, --NumVals) {
1680 SDOperand Op = LegalizeOp(Ops[i]);
1689 Op = LegalizeOp(Ops.back());
1690 Changed |= Op != Ops.back();
1695 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1697 // INLINE asm returns a chain and flag, make sure to add both to the map.
1698 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1699 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1700 return Result.getValue(Op.ResNo);
1703 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1704 // Ensure that libcalls are emitted before a branch.
1705 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1706 Tmp1 = LegalizeOp(Tmp1);
1707 LastCALLSEQ_END = DAG.getEntryNode();
1709 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1712 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1713 // Ensure that libcalls are emitted before a branch.
1714 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1715 Tmp1 = LegalizeOp(Tmp1);
1716 LastCALLSEQ_END = DAG.getEntryNode();
1718 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1719 default: assert(0 && "Indirect target must be legal type (pointer)!");
1721 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1724 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1727 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1728 // Ensure that libcalls are emitted before a branch.
1729 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1730 Tmp1 = LegalizeOp(Tmp1);
1731 LastCALLSEQ_END = DAG.getEntryNode();
1733 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1734 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1736 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1737 default: assert(0 && "This action is not supported yet!");
1738 case TargetLowering::Legal: break;
1739 case TargetLowering::Custom:
1740 Tmp1 = TLI.LowerOperation(Result, DAG);
1741 if (Tmp1.Val) Result = Tmp1;
1743 case TargetLowering::Expand: {
1744 SDOperand Chain = Result.getOperand(0);
1745 SDOperand Table = Result.getOperand(1);
1746 SDOperand Index = Result.getOperand(2);
1748 MVT::ValueType PTy = TLI.getPointerTy();
1749 MachineFunction &MF = DAG.getMachineFunction();
1750 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
1751 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1752 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1755 switch (EntrySize) {
1756 default: assert(0 && "Size of jump table not supported yet."); break;
1757 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr,
1758 PseudoSourceValue::getJumpTable(), 0); break;
1759 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr,
1760 PseudoSourceValue::getJumpTable(), 0); break;
1764 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1765 // For PIC, the sequence is:
1766 // BRIND(load(Jumptable + index) + RelocBase)
1767 // RelocBase can be JumpTable, GOT or some sort of global base.
1768 if (PTy != MVT::i32)
1769 Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr);
1770 Addr = DAG.getNode(ISD::ADD, PTy, Addr,
1771 TLI.getPICJumpTableRelocBase(Table, DAG));
1773 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1778 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1779 // Ensure that libcalls are emitted before a return.
1780 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1781 Tmp1 = LegalizeOp(Tmp1);
1782 LastCALLSEQ_END = DAG.getEntryNode();
1784 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1785 case Expand: assert(0 && "It's impossible to expand bools");
1787 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1790 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1792 // The top bits of the promoted condition are not necessarily zero, ensure
1793 // that the value is properly zero extended.
1794 unsigned BitWidth = Tmp2.getValueSizeInBits();
1795 if (!DAG.MaskedValueIsZero(Tmp2,
1796 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
1797 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1802 // Basic block destination (Op#2) is always legal.
1803 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1805 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1806 default: assert(0 && "This action is not supported yet!");
1807 case TargetLowering::Legal: break;
1808 case TargetLowering::Custom:
1809 Tmp1 = TLI.LowerOperation(Result, DAG);
1810 if (Tmp1.Val) Result = Tmp1;
1812 case TargetLowering::Expand:
1813 // Expand brcond's setcc into its constituent parts and create a BR_CC
1815 if (Tmp2.getOpcode() == ISD::SETCC) {
1816 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1817 Tmp2.getOperand(0), Tmp2.getOperand(1),
1818 Node->getOperand(2));
1820 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1821 DAG.getCondCode(ISD::SETNE), Tmp2,
1822 DAG.getConstant(0, Tmp2.getValueType()),
1823 Node->getOperand(2));
1829 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1830 // Ensure that libcalls are emitted before a branch.
1831 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1832 Tmp1 = LegalizeOp(Tmp1);
1833 Tmp2 = Node->getOperand(2); // LHS
1834 Tmp3 = Node->getOperand(3); // RHS
1835 Tmp4 = Node->getOperand(1); // CC
1837 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1838 LastCALLSEQ_END = DAG.getEntryNode();
1840 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1841 // the LHS is a legal SETCC itself. In this case, we need to compare
1842 // the result against zero to select between true and false values.
1843 if (Tmp3.Val == 0) {
1844 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1845 Tmp4 = DAG.getCondCode(ISD::SETNE);
1848 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1849 Node->getOperand(4));
1851 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1852 default: assert(0 && "Unexpected action for BR_CC!");
1853 case TargetLowering::Legal: break;
1854 case TargetLowering::Custom:
1855 Tmp4 = TLI.LowerOperation(Result, DAG);
1856 if (Tmp4.Val) Result = Tmp4;
1861 LoadSDNode *LD = cast<LoadSDNode>(Node);
1862 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1863 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1865 ISD::LoadExtType ExtType = LD->getExtensionType();
1866 if (ExtType == ISD::NON_EXTLOAD) {
1867 MVT::ValueType VT = Node->getValueType(0);
1868 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1869 Tmp3 = Result.getValue(0);
1870 Tmp4 = Result.getValue(1);
1872 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1873 default: assert(0 && "This action is not supported yet!");
1874 case TargetLowering::Legal:
1875 // If this is an unaligned load and the target doesn't support it,
1877 if (!TLI.allowsUnalignedMemoryAccesses()) {
1878 unsigned ABIAlignment = TLI.getTargetData()->
1879 getABITypeAlignment(MVT::getTypeForValueType(LD->getMemoryVT()));
1880 if (LD->getAlignment() < ABIAlignment){
1881 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
1883 Tmp3 = Result.getOperand(0);
1884 Tmp4 = Result.getOperand(1);
1885 Tmp3 = LegalizeOp(Tmp3);
1886 Tmp4 = LegalizeOp(Tmp4);
1890 case TargetLowering::Custom:
1891 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1893 Tmp3 = LegalizeOp(Tmp1);
1894 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1897 case TargetLowering::Promote: {
1898 // Only promote a load of vector type to another.
1899 assert(MVT::isVector(VT) && "Cannot promote this load!");
1900 // Change base type to a different vector type.
1901 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1903 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1904 LD->getSrcValueOffset(),
1905 LD->isVolatile(), LD->getAlignment());
1906 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1907 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1911 // Since loads produce two values, make sure to remember that we
1912 // legalized both of them.
1913 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1914 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1915 return Op.ResNo ? Tmp4 : Tmp3;
1917 MVT::ValueType SrcVT = LD->getMemoryVT();
1918 unsigned SrcWidth = MVT::getSizeInBits(SrcVT);
1919 int SVOffset = LD->getSrcValueOffset();
1920 unsigned Alignment = LD->getAlignment();
1921 bool isVolatile = LD->isVolatile();
1923 if (SrcWidth != MVT::getStoreSizeInBits(SrcVT) &&
1924 // Some targets pretend to have an i1 loading operation, and actually
1925 // load an i8. This trick is correct for ZEXTLOAD because the top 7
1926 // bits are guaranteed to be zero; it helps the optimizers understand
1927 // that these bits are zero. It is also useful for EXTLOAD, since it
1928 // tells the optimizers that those bits are undefined. It would be
1929 // nice to have an effective generic way of getting these benefits...
1930 // Until such a way is found, don't insist on promoting i1 here.
1931 (SrcVT != MVT::i1 ||
1932 TLI.getLoadXAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
1933 // Promote to a byte-sized load if not loading an integral number of
1934 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
1935 unsigned NewWidth = MVT::getStoreSizeInBits(SrcVT);
1936 MVT::ValueType NVT = MVT::getIntegerType(NewWidth);
1939 // The extra bits are guaranteed to be zero, since we stored them that
1940 // way. A zext load from NVT thus automatically gives zext from SrcVT.
1942 ISD::LoadExtType NewExtType =
1943 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
1945 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0),
1946 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
1947 NVT, isVolatile, Alignment);
1949 Ch = Result.getValue(1); // The chain.
1951 if (ExtType == ISD::SEXTLOAD)
1952 // Having the top bits zero doesn't help when sign extending.
1953 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1954 Result, DAG.getValueType(SrcVT));
1955 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
1956 // All the top bits are guaranteed to be zero - inform the optimizers.
1957 Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result,
1958 DAG.getValueType(SrcVT));
1960 Tmp1 = LegalizeOp(Result);
1961 Tmp2 = LegalizeOp(Ch);
1962 } else if (SrcWidth & (SrcWidth - 1)) {
1963 // If not loading a power-of-2 number of bits, expand as two loads.
1964 assert(MVT::isExtendedVT(SrcVT) && !MVT::isVector(SrcVT) &&
1965 "Unsupported extload!");
1966 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
1967 assert(RoundWidth < SrcWidth);
1968 unsigned ExtraWidth = SrcWidth - RoundWidth;
1969 assert(ExtraWidth < RoundWidth);
1970 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1971 "Load size not an integral number of bytes!");
1972 MVT::ValueType RoundVT = MVT::getIntegerType(RoundWidth);
1973 MVT::ValueType ExtraVT = MVT::getIntegerType(ExtraWidth);
1974 SDOperand Lo, Hi, Ch;
1975 unsigned IncrementSize;
1977 if (TLI.isLittleEndian()) {
1978 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1979 // Load the bottom RoundWidth bits.
1980 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
1981 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
1984 // Load the remaining ExtraWidth bits.
1985 IncrementSize = RoundWidth / 8;
1986 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1987 DAG.getIntPtrConstant(IncrementSize));
1988 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
1989 LD->getSrcValue(), SVOffset + IncrementSize,
1990 ExtraVT, isVolatile,
1991 MinAlign(Alignment, IncrementSize));
1993 // Build a factor node to remember that this load is independent of the
1995 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
1998 // Move the top bits to the right place.
1999 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2000 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2002 // Join the hi and lo parts.
2003 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2005 // Big endian - avoid unaligned loads.
2006 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
2007 // Load the top RoundWidth bits.
2008 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2009 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2012 // Load the remaining ExtraWidth bits.
2013 IncrementSize = RoundWidth / 8;
2014 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2015 DAG.getIntPtrConstant(IncrementSize));
2016 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2017 LD->getSrcValue(), SVOffset + IncrementSize,
2018 ExtraVT, isVolatile,
2019 MinAlign(Alignment, IncrementSize));
2021 // Build a factor node to remember that this load is independent of the
2023 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2026 // Move the top bits to the right place.
2027 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2028 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2030 // Join the hi and lo parts.
2031 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2034 Tmp1 = LegalizeOp(Result);
2035 Tmp2 = LegalizeOp(Ch);
2037 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
2038 default: assert(0 && "This action is not supported yet!");
2039 case TargetLowering::Custom:
2042 case TargetLowering::Legal:
2043 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2044 Tmp1 = Result.getValue(0);
2045 Tmp2 = Result.getValue(1);
2048 Tmp3 = TLI.LowerOperation(Result, DAG);
2050 Tmp1 = LegalizeOp(Tmp3);
2051 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2054 // If this is an unaligned load and the target doesn't support it,
2056 if (!TLI.allowsUnalignedMemoryAccesses()) {
2057 unsigned ABIAlignment = TLI.getTargetData()->
2058 getABITypeAlignment(MVT::getTypeForValueType(LD->getMemoryVT()));
2059 if (LD->getAlignment() < ABIAlignment){
2060 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
2062 Tmp1 = Result.getOperand(0);
2063 Tmp2 = Result.getOperand(1);
2064 Tmp1 = LegalizeOp(Tmp1);
2065 Tmp2 = LegalizeOp(Tmp2);
2070 case TargetLowering::Expand:
2071 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
2072 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
2073 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
2074 LD->getSrcValueOffset(),
2075 LD->isVolatile(), LD->getAlignment());
2076 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
2077 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
2078 Tmp2 = LegalizeOp(Load.getValue(1));
2081 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
2082 // Turn the unsupported load into an EXTLOAD followed by an explicit
2083 // zero/sign extend inreg.
2084 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2085 Tmp1, Tmp2, LD->getSrcValue(),
2086 LD->getSrcValueOffset(), SrcVT,
2087 LD->isVolatile(), LD->getAlignment());
2089 if (ExtType == ISD::SEXTLOAD)
2090 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2091 Result, DAG.getValueType(SrcVT));
2093 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
2094 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
2095 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
2100 // Since loads produce two values, make sure to remember that we legalized
2102 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2103 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2104 return Op.ResNo ? Tmp2 : Tmp1;
2107 case ISD::EXTRACT_ELEMENT: {
2108 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
2109 switch (getTypeAction(OpTy)) {
2110 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
2112 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
2114 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
2115 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
2116 TLI.getShiftAmountTy()));
2117 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
2120 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
2121 Node->getOperand(0));
2125 // Get both the low and high parts.
2126 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2127 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
2128 Result = Tmp2; // 1 -> Hi
2130 Result = Tmp1; // 0 -> Lo
2136 case ISD::CopyToReg:
2137 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2139 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
2140 "Register type must be legal!");
2141 // Legalize the incoming value (must be a legal type).
2142 Tmp2 = LegalizeOp(Node->getOperand(2));
2143 if (Node->getNumValues() == 1) {
2144 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
2146 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
2147 if (Node->getNumOperands() == 4) {
2148 Tmp3 = LegalizeOp(Node->getOperand(3));
2149 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
2152 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
2155 // Since this produces two values, make sure to remember that we legalized
2157 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2158 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2164 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2166 // Ensure that libcalls are emitted before a return.
2167 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2168 Tmp1 = LegalizeOp(Tmp1);
2169 LastCALLSEQ_END = DAG.getEntryNode();
2171 switch (Node->getNumOperands()) {
2173 Tmp2 = Node->getOperand(1);
2174 Tmp3 = Node->getOperand(2); // Signness
2175 switch (getTypeAction(Tmp2.getValueType())) {
2177 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
2180 if (!MVT::isVector(Tmp2.getValueType())) {
2182 ExpandOp(Tmp2, Lo, Hi);
2184 // Big endian systems want the hi reg first.
2185 if (TLI.isBigEndian())
2189 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2191 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
2192 Result = LegalizeOp(Result);
2194 SDNode *InVal = Tmp2.Val;
2195 int InIx = Tmp2.ResNo;
2196 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx));
2197 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx));
2199 // Figure out if there is a simple type corresponding to this Vector
2200 // type. If so, convert to the vector type.
2201 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2202 if (TLI.isTypeLegal(TVT)) {
2203 // Turn this into a return of the vector type.
2204 Tmp2 = LegalizeOp(Tmp2);
2205 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2206 } else if (NumElems == 1) {
2207 // Turn this into a return of the scalar type.
2208 Tmp2 = ScalarizeVectorOp(Tmp2);
2209 Tmp2 = LegalizeOp(Tmp2);
2210 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2212 // FIXME: Returns of gcc generic vectors smaller than a legal type
2213 // should be returned in integer registers!
2215 // The scalarized value type may not be legal, e.g. it might require
2216 // promotion or expansion. Relegalize the return.
2217 Result = LegalizeOp(Result);
2219 // FIXME: Returns of gcc generic vectors larger than a legal vector
2220 // type should be returned by reference!
2222 SplitVectorOp(Tmp2, Lo, Hi);
2223 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2224 Result = LegalizeOp(Result);
2229 Tmp2 = PromoteOp(Node->getOperand(1));
2230 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2231 Result = LegalizeOp(Result);
2236 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2238 default: { // ret <values>
2239 SmallVector<SDOperand, 8> NewValues;
2240 NewValues.push_back(Tmp1);
2241 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
2242 switch (getTypeAction(Node->getOperand(i).getValueType())) {
2244 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
2245 NewValues.push_back(Node->getOperand(i+1));
2249 assert(!MVT::isExtendedVT(Node->getOperand(i).getValueType()) &&
2250 "FIXME: TODO: implement returning non-legal vector types!");
2251 ExpandOp(Node->getOperand(i), Lo, Hi);
2252 NewValues.push_back(Lo);
2253 NewValues.push_back(Node->getOperand(i+1));
2255 NewValues.push_back(Hi);
2256 NewValues.push_back(Node->getOperand(i+1));
2261 assert(0 && "Can't promote multiple return value yet!");
2264 if (NewValues.size() == Node->getNumOperands())
2265 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
2267 Result = DAG.getNode(ISD::RET, MVT::Other,
2268 &NewValues[0], NewValues.size());
2273 if (Result.getOpcode() == ISD::RET) {
2274 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
2275 default: assert(0 && "This action is not supported yet!");
2276 case TargetLowering::Legal: break;
2277 case TargetLowering::Custom:
2278 Tmp1 = TLI.LowerOperation(Result, DAG);
2279 if (Tmp1.Val) Result = Tmp1;
2285 StoreSDNode *ST = cast<StoreSDNode>(Node);
2286 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
2287 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
2288 int SVOffset = ST->getSrcValueOffset();
2289 unsigned Alignment = ST->getAlignment();
2290 bool isVolatile = ST->isVolatile();
2292 if (!ST->isTruncatingStore()) {
2293 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
2294 // FIXME: We shouldn't do this for TargetConstantFP's.
2295 // FIXME: move this to the DAG Combiner! Note that we can't regress due
2296 // to phase ordering between legalized code and the dag combiner. This
2297 // probably means that we need to integrate dag combiner and legalizer
2299 // We generally can't do this one for long doubles.
2300 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
2301 if (CFP->getValueType(0) == MVT::f32 &&
2302 getTypeAction(MVT::i32) == Legal) {
2303 Tmp3 = DAG.getConstant((uint32_t)CFP->getValueAPF().
2304 convertToAPInt().getZExtValue(),
2306 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2307 SVOffset, isVolatile, Alignment);
2309 } else if (CFP->getValueType(0) == MVT::f64) {
2310 // If this target supports 64-bit registers, do a single 64-bit store.
2311 if (getTypeAction(MVT::i64) == Legal) {
2312 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt().
2313 getZExtValue(), MVT::i64);
2314 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2315 SVOffset, isVolatile, Alignment);
2317 } else if (getTypeAction(MVT::i32) == Legal) {
2318 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
2319 // stores. If the target supports neither 32- nor 64-bits, this
2320 // xform is certainly not worth it.
2321 uint64_t IntVal =CFP->getValueAPF().convertToAPInt().getZExtValue();
2322 SDOperand Lo = DAG.getConstant(uint32_t(IntVal), MVT::i32);
2323 SDOperand Hi = DAG.getConstant(uint32_t(IntVal >>32), MVT::i32);
2324 if (TLI.isBigEndian()) std::swap(Lo, Hi);
2326 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2327 SVOffset, isVolatile, Alignment);
2328 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2329 DAG.getIntPtrConstant(4));
2330 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
2331 isVolatile, MinAlign(Alignment, 4U));
2333 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2339 switch (getTypeAction(ST->getMemoryVT())) {
2341 Tmp3 = LegalizeOp(ST->getValue());
2342 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2345 MVT::ValueType VT = Tmp3.getValueType();
2346 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2347 default: assert(0 && "This action is not supported yet!");
2348 case TargetLowering::Legal:
2349 // If this is an unaligned store and the target doesn't support it,
2351 if (!TLI.allowsUnalignedMemoryAccesses()) {
2352 unsigned ABIAlignment = TLI.getTargetData()->
2353 getABITypeAlignment(MVT::getTypeForValueType(ST->getMemoryVT()));
2354 if (ST->getAlignment() < ABIAlignment)
2355 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2359 case TargetLowering::Custom:
2360 Tmp1 = TLI.LowerOperation(Result, DAG);
2361 if (Tmp1.Val) Result = Tmp1;
2363 case TargetLowering::Promote:
2364 assert(MVT::isVector(VT) && "Unknown legal promote case!");
2365 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
2366 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2367 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
2368 ST->getSrcValue(), SVOffset, isVolatile,
2375 // Truncate the value and store the result.
2376 Tmp3 = PromoteOp(ST->getValue());
2377 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2378 SVOffset, ST->getMemoryVT(),
2379 isVolatile, Alignment);
2383 unsigned IncrementSize = 0;
2386 // If this is a vector type, then we have to calculate the increment as
2387 // the product of the element size in bytes, and the number of elements
2388 // in the high half of the vector.
2389 if (MVT::isVector(ST->getValue().getValueType())) {
2390 SDNode *InVal = ST->getValue().Val;
2391 int InIx = ST->getValue().ResNo;
2392 MVT::ValueType InVT = InVal->getValueType(InIx);
2393 unsigned NumElems = MVT::getVectorNumElements(InVT);
2394 MVT::ValueType EVT = MVT::getVectorElementType(InVT);
2396 // Figure out if there is a simple type corresponding to this Vector
2397 // type. If so, convert to the vector type.
2398 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2399 if (TLI.isTypeLegal(TVT)) {
2400 // Turn this into a normal store of the vector type.
2401 Tmp3 = LegalizeOp(ST->getValue());
2402 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2403 SVOffset, isVolatile, Alignment);
2404 Result = LegalizeOp(Result);
2406 } else if (NumElems == 1) {
2407 // Turn this into a normal store of the scalar type.
2408 Tmp3 = ScalarizeVectorOp(ST->getValue());
2409 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2410 SVOffset, isVolatile, Alignment);
2411 // The scalarized value type may not be legal, e.g. it might require
2412 // promotion or expansion. Relegalize the scalar store.
2413 Result = LegalizeOp(Result);
2416 SplitVectorOp(ST->getValue(), Lo, Hi);
2417 IncrementSize = MVT::getVectorNumElements(Lo.Val->getValueType(0)) *
2418 MVT::getSizeInBits(EVT)/8;
2421 ExpandOp(ST->getValue(), Lo, Hi);
2422 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0;
2424 if (TLI.isBigEndian())
2428 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2429 SVOffset, isVolatile, Alignment);
2431 if (Hi.Val == NULL) {
2432 // Must be int <-> float one-to-one expansion.
2437 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2438 DAG.getIntPtrConstant(IncrementSize));
2439 assert(isTypeLegal(Tmp2.getValueType()) &&
2440 "Pointers must be legal!");
2441 SVOffset += IncrementSize;
2442 Alignment = MinAlign(Alignment, IncrementSize);
2443 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2444 SVOffset, isVolatile, Alignment);
2445 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2449 switch (getTypeAction(ST->getValue().getValueType())) {
2451 Tmp3 = LegalizeOp(ST->getValue());
2454 // We can promote the value, the truncstore will still take care of it.
2455 Tmp3 = PromoteOp(ST->getValue());
2458 // Just store the low part. This may become a non-trunc store, so make
2459 // sure to use getTruncStore, not UpdateNodeOperands below.
2460 ExpandOp(ST->getValue(), Tmp3, Tmp4);
2461 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2462 SVOffset, MVT::i8, isVolatile, Alignment);
2465 MVT::ValueType StVT = ST->getMemoryVT();
2466 unsigned StWidth = MVT::getSizeInBits(StVT);
2468 if (StWidth != MVT::getStoreSizeInBits(StVT)) {
2469 // Promote to a byte-sized store with upper bits zero if not
2470 // storing an integral number of bytes. For example, promote
2471 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
2472 MVT::ValueType NVT = MVT::getIntegerType(MVT::getStoreSizeInBits(StVT));
2473 Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT);
2474 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2475 SVOffset, NVT, isVolatile, Alignment);
2476 } else if (StWidth & (StWidth - 1)) {
2477 // If not storing a power-of-2 number of bits, expand as two stores.
2478 assert(MVT::isExtendedVT(StVT) && !MVT::isVector(StVT) &&
2479 "Unsupported truncstore!");
2480 unsigned RoundWidth = 1 << Log2_32(StWidth);
2481 assert(RoundWidth < StWidth);
2482 unsigned ExtraWidth = StWidth - RoundWidth;
2483 assert(ExtraWidth < RoundWidth);
2484 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2485 "Store size not an integral number of bytes!");
2486 MVT::ValueType RoundVT = MVT::getIntegerType(RoundWidth);
2487 MVT::ValueType ExtraVT = MVT::getIntegerType(ExtraWidth);
2489 unsigned IncrementSize;
2491 if (TLI.isLittleEndian()) {
2492 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
2493 // Store the bottom RoundWidth bits.
2494 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2496 isVolatile, Alignment);
2498 // Store the remaining ExtraWidth bits.
2499 IncrementSize = RoundWidth / 8;
2500 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2501 DAG.getIntPtrConstant(IncrementSize));
2502 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2503 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2504 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2505 SVOffset + IncrementSize, ExtraVT, isVolatile,
2506 MinAlign(Alignment, IncrementSize));
2508 // Big endian - avoid unaligned stores.
2509 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
2510 // Store the top RoundWidth bits.
2511 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2512 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2513 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset,
2514 RoundVT, isVolatile, Alignment);
2516 // Store the remaining ExtraWidth bits.
2517 IncrementSize = RoundWidth / 8;
2518 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2519 DAG.getIntPtrConstant(IncrementSize));
2520 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2521 SVOffset + IncrementSize, ExtraVT, isVolatile,
2522 MinAlign(Alignment, IncrementSize));
2525 // The order of the stores doesn't matter.
2526 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2528 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2529 Tmp2 != ST->getBasePtr())
2530 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2533 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
2534 default: assert(0 && "This action is not supported yet!");
2535 case TargetLowering::Legal:
2536 // If this is an unaligned store and the target doesn't support it,
2538 if (!TLI.allowsUnalignedMemoryAccesses()) {
2539 unsigned ABIAlignment = TLI.getTargetData()->
2540 getABITypeAlignment(MVT::getTypeForValueType(ST->getMemoryVT()));
2541 if (ST->getAlignment() < ABIAlignment)
2542 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2546 case TargetLowering::Custom:
2547 Result = TLI.LowerOperation(Result, DAG);
2550 // TRUNCSTORE:i16 i32 -> STORE i16
2551 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
2552 Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3);
2553 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset,
2554 isVolatile, Alignment);
2562 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2563 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2565 case ISD::STACKSAVE:
2566 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2567 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2568 Tmp1 = Result.getValue(0);
2569 Tmp2 = Result.getValue(1);
2571 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2572 default: assert(0 && "This action is not supported yet!");
2573 case TargetLowering::Legal: break;
2574 case TargetLowering::Custom:
2575 Tmp3 = TLI.LowerOperation(Result, DAG);
2577 Tmp1 = LegalizeOp(Tmp3);
2578 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2581 case TargetLowering::Expand:
2582 // Expand to CopyFromReg if the target set
2583 // StackPointerRegisterToSaveRestore.
2584 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2585 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
2586 Node->getValueType(0));
2587 Tmp2 = Tmp1.getValue(1);
2589 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
2590 Tmp2 = Node->getOperand(0);
2595 // Since stacksave produce two values, make sure to remember that we
2596 // legalized both of them.
2597 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2598 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2599 return Op.ResNo ? Tmp2 : Tmp1;
2601 case ISD::STACKRESTORE:
2602 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2603 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2604 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2606 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2607 default: assert(0 && "This action is not supported yet!");
2608 case TargetLowering::Legal: break;
2609 case TargetLowering::Custom:
2610 Tmp1 = TLI.LowerOperation(Result, DAG);
2611 if (Tmp1.Val) Result = Tmp1;
2613 case TargetLowering::Expand:
2614 // Expand to CopyToReg if the target set
2615 // StackPointerRegisterToSaveRestore.
2616 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2617 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
2625 case ISD::READCYCLECOUNTER:
2626 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2627 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2628 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2629 Node->getValueType(0))) {
2630 default: assert(0 && "This action is not supported yet!");
2631 case TargetLowering::Legal:
2632 Tmp1 = Result.getValue(0);
2633 Tmp2 = Result.getValue(1);
2635 case TargetLowering::Custom:
2636 Result = TLI.LowerOperation(Result, DAG);
2637 Tmp1 = LegalizeOp(Result.getValue(0));
2638 Tmp2 = LegalizeOp(Result.getValue(1));
2642 // Since rdcc produce two values, make sure to remember that we legalized
2644 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2645 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2649 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2650 case Expand: assert(0 && "It's impossible to expand bools");
2652 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2655 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2656 // Make sure the condition is either zero or one.
2657 unsigned BitWidth = Tmp1.getValueSizeInBits();
2658 if (!DAG.MaskedValueIsZero(Tmp1,
2659 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2660 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2664 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2665 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2667 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2669 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2670 default: assert(0 && "This action is not supported yet!");
2671 case TargetLowering::Legal: break;
2672 case TargetLowering::Custom: {
2673 Tmp1 = TLI.LowerOperation(Result, DAG);
2674 if (Tmp1.Val) Result = Tmp1;
2677 case TargetLowering::Expand:
2678 if (Tmp1.getOpcode() == ISD::SETCC) {
2679 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2681 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2683 Result = DAG.getSelectCC(Tmp1,
2684 DAG.getConstant(0, Tmp1.getValueType()),
2685 Tmp2, Tmp3, ISD::SETNE);
2688 case TargetLowering::Promote: {
2689 MVT::ValueType NVT =
2690 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2691 unsigned ExtOp, TruncOp;
2692 if (MVT::isVector(Tmp2.getValueType())) {
2693 ExtOp = ISD::BIT_CONVERT;
2694 TruncOp = ISD::BIT_CONVERT;
2695 } else if (MVT::isInteger(Tmp2.getValueType())) {
2696 ExtOp = ISD::ANY_EXTEND;
2697 TruncOp = ISD::TRUNCATE;
2699 ExtOp = ISD::FP_EXTEND;
2700 TruncOp = ISD::FP_ROUND;
2702 // Promote each of the values to the new type.
2703 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2704 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2705 // Perform the larger operation, then round down.
2706 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2707 if (TruncOp != ISD::FP_ROUND)
2708 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2710 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result,
2711 DAG.getIntPtrConstant(0));
2716 case ISD::SELECT_CC: {
2717 Tmp1 = Node->getOperand(0); // LHS
2718 Tmp2 = Node->getOperand(1); // RHS
2719 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2720 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2721 SDOperand CC = Node->getOperand(4);
2723 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
2725 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
2726 // the LHS is a legal SETCC itself. In this case, we need to compare
2727 // the result against zero to select between true and false values.
2728 if (Tmp2.Val == 0) {
2729 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2730 CC = DAG.getCondCode(ISD::SETNE);
2732 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
2734 // Everything is legal, see if we should expand this op or something.
2735 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
2736 default: assert(0 && "This action is not supported yet!");
2737 case TargetLowering::Legal: break;
2738 case TargetLowering::Custom:
2739 Tmp1 = TLI.LowerOperation(Result, DAG);
2740 if (Tmp1.Val) Result = Tmp1;
2746 Tmp1 = Node->getOperand(0);
2747 Tmp2 = Node->getOperand(1);
2748 Tmp3 = Node->getOperand(2);
2749 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
2751 // If we had to Expand the SetCC operands into a SELECT node, then it may
2752 // not always be possible to return a true LHS & RHS. In this case, just
2753 // return the value we legalized, returned in the LHS
2754 if (Tmp2.Val == 0) {
2759 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
2760 default: assert(0 && "Cannot handle this action for SETCC yet!");
2761 case TargetLowering::Custom:
2764 case TargetLowering::Legal:
2765 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2767 Tmp4 = TLI.LowerOperation(Result, DAG);
2768 if (Tmp4.Val) Result = Tmp4;
2771 case TargetLowering::Promote: {
2772 // First step, figure out the appropriate operation to use.
2773 // Allow SETCC to not be supported for all legal data types
2774 // Mostly this targets FP
2775 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
2776 MVT::ValueType OldVT = NewInTy; OldVT = OldVT;
2778 // Scan for the appropriate larger type to use.
2780 NewInTy = (MVT::ValueType)(NewInTy+1);
2782 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
2783 "Fell off of the edge of the integer world");
2784 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
2785 "Fell off of the edge of the floating point world");
2787 // If the target supports SETCC of this type, use it.
2788 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2791 if (MVT::isInteger(NewInTy))
2792 assert(0 && "Cannot promote Legal Integer SETCC yet");
2794 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2795 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2797 Tmp1 = LegalizeOp(Tmp1);
2798 Tmp2 = LegalizeOp(Tmp2);
2799 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2800 Result = LegalizeOp(Result);
2803 case TargetLowering::Expand:
2804 // Expand a setcc node into a select_cc of the same condition, lhs, and
2805 // rhs that selects between const 1 (true) and const 0 (false).
2806 MVT::ValueType VT = Node->getValueType(0);
2807 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2808 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2815 case ISD::MEMMOVE: {
2816 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
2817 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
2819 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
2820 switch (getTypeAction(Node->getOperand(2).getValueType())) {
2821 case Expand: assert(0 && "Cannot expand a byte!");
2823 Tmp3 = LegalizeOp(Node->getOperand(2));
2826 Tmp3 = PromoteOp(Node->getOperand(2));
2830 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
2834 switch (getTypeAction(Node->getOperand(3).getValueType())) {
2836 // Length is too big, just take the lo-part of the length.
2838 ExpandOp(Node->getOperand(3), Tmp4, HiPart);
2842 Tmp4 = LegalizeOp(Node->getOperand(3));
2845 Tmp4 = PromoteOp(Node->getOperand(3));
2850 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
2851 case Expand: assert(0 && "Cannot expand this yet!");
2853 Tmp5 = LegalizeOp(Node->getOperand(4));
2856 Tmp5 = PromoteOp(Node->getOperand(4));
2861 switch (getTypeAction(Node->getOperand(5).getValueType())) { // bool
2862 case Expand: assert(0 && "Cannot expand this yet!");
2864 Tmp6 = LegalizeOp(Node->getOperand(5));
2867 Tmp6 = PromoteOp(Node->getOperand(5));
2871 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2872 default: assert(0 && "This action not implemented for this operation!");
2873 case TargetLowering::Custom:
2876 case TargetLowering::Legal: {
2877 SDOperand Ops[] = { Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6 };
2878 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
2880 Tmp1 = TLI.LowerOperation(Result, DAG);
2881 if (Tmp1.Val) Result = Tmp1;
2885 case TargetLowering::Expand: {
2886 // Otherwise, the target does not support this operation. Lower the
2887 // operation to an explicit libcall as appropriate.
2888 MVT::ValueType IntPtr = TLI.getPointerTy();
2889 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType();
2890 TargetLowering::ArgListTy Args;
2891 TargetLowering::ArgListEntry Entry;
2893 const char *FnName = 0;
2894 if (Node->getOpcode() == ISD::MEMSET) {
2895 Entry.Node = Tmp2; Entry.Ty = IntPtrTy;
2896 Args.push_back(Entry);
2897 // Extend the (previously legalized) ubyte argument to be an int value
2899 if (Tmp3.getValueType() > MVT::i32)
2900 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
2902 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
2903 Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSExt = true;
2904 Args.push_back(Entry);
2905 Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSExt = false;
2906 Args.push_back(Entry);
2909 } else if (Node->getOpcode() == ISD::MEMCPY ||
2910 Node->getOpcode() == ISD::MEMMOVE) {
2911 Entry.Ty = IntPtrTy;
2912 Entry.Node = Tmp2; Args.push_back(Entry);
2913 Entry.Node = Tmp3; Args.push_back(Entry);
2914 Entry.Node = Tmp4; Args.push_back(Entry);
2915 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
2917 assert(0 && "Unknown op!");
2920 std::pair<SDOperand,SDOperand> CallResult =
2921 TLI.LowerCallTo(Tmp1, Type::VoidTy,
2922 false, false, false, CallingConv::C, false,
2923 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
2924 Result = CallResult.second;
2931 case ISD::SHL_PARTS:
2932 case ISD::SRA_PARTS:
2933 case ISD::SRL_PARTS: {
2934 SmallVector<SDOperand, 8> Ops;
2935 bool Changed = false;
2936 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2937 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2938 Changed |= Ops.back() != Node->getOperand(i);
2941 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2943 switch (TLI.getOperationAction(Node->getOpcode(),
2944 Node->getValueType(0))) {
2945 default: assert(0 && "This action is not supported yet!");
2946 case TargetLowering::Legal: break;
2947 case TargetLowering::Custom:
2948 Tmp1 = TLI.LowerOperation(Result, DAG);
2950 SDOperand Tmp2, RetVal(0, 0);
2951 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2952 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2953 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2957 assert(RetVal.Val && "Illegal result number");
2963 // Since these produce multiple values, make sure to remember that we
2964 // legalized all of them.
2965 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2966 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2967 return Result.getValue(Op.ResNo);
2989 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2990 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2991 case Expand: assert(0 && "Not possible");
2993 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2996 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3000 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3002 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3003 default: assert(0 && "BinOp legalize operation not supported");
3004 case TargetLowering::Legal: break;
3005 case TargetLowering::Custom:
3006 Tmp1 = TLI.LowerOperation(Result, DAG);
3007 if (Tmp1.Val) Result = Tmp1;
3009 case TargetLowering::Expand: {
3010 MVT::ValueType VT = Op.getValueType();
3012 // See if multiply or divide can be lowered using two-result operations.
3013 SDVTList VTs = DAG.getVTList(VT, VT);
3014 if (Node->getOpcode() == ISD::MUL) {
3015 // We just need the low half of the multiply; try both the signed
3016 // and unsigned forms. If the target supports both SMUL_LOHI and
3017 // UMUL_LOHI, form a preference by checking which forms of plain
3018 // MULH it supports.
3019 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT);
3020 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT);
3021 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT);
3022 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT);
3023 unsigned OpToUse = 0;
3024 if (HasSMUL_LOHI && !HasMULHS) {
3025 OpToUse = ISD::SMUL_LOHI;
3026 } else if (HasUMUL_LOHI && !HasMULHU) {
3027 OpToUse = ISD::UMUL_LOHI;
3028 } else if (HasSMUL_LOHI) {
3029 OpToUse = ISD::SMUL_LOHI;
3030 } else if (HasUMUL_LOHI) {
3031 OpToUse = ISD::UMUL_LOHI;
3034 Result = SDOperand(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).Val, 0);
3038 if (Node->getOpcode() == ISD::MULHS &&
3039 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) {
3040 Result = SDOperand(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
3043 if (Node->getOpcode() == ISD::MULHU &&
3044 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) {
3045 Result = SDOperand(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
3048 if (Node->getOpcode() == ISD::SDIV &&
3049 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3050 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 0);
3053 if (Node->getOpcode() == ISD::UDIV &&
3054 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3055 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 0);
3059 // Check to see if we have a libcall for this operator.
3060 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3061 bool isSigned = false;
3062 switch (Node->getOpcode()) {
3065 if (VT == MVT::i32) {
3066 LC = Node->getOpcode() == ISD::UDIV
3067 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
3068 isSigned = Node->getOpcode() == ISD::SDIV;
3072 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
3073 RTLIB::POW_PPCF128);
3077 if (LC != RTLIB::UNKNOWN_LIBCALL) {
3079 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
3083 assert(MVT::isVector(Node->getValueType(0)) &&
3084 "Cannot expand this binary operator!");
3085 // Expand the operation into a bunch of nasty scalar code.
3086 Result = LegalizeOp(UnrollVectorOp(Op));
3089 case TargetLowering::Promote: {
3090 switch (Node->getOpcode()) {
3091 default: assert(0 && "Do not know how to promote this BinOp!");
3095 MVT::ValueType OVT = Node->getValueType(0);
3096 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3097 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
3098 // Bit convert each of the values to the new type.
3099 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
3100 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
3101 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3102 // Bit convert the result back the original type.
3103 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
3111 case ISD::SMUL_LOHI:
3112 case ISD::UMUL_LOHI:
3115 // These nodes will only be produced by target-specific lowering, so
3116 // they shouldn't be here if they aren't legal.
3117 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
3118 "This must be legal!");
3120 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3121 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3122 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3125 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
3126 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3127 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3128 case Expand: assert(0 && "Not possible");
3130 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3133 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3137 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3139 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3140 default: assert(0 && "Operation not supported");
3141 case TargetLowering::Custom:
3142 Tmp1 = TLI.LowerOperation(Result, DAG);
3143 if (Tmp1.Val) Result = Tmp1;
3145 case TargetLowering::Legal: break;
3146 case TargetLowering::Expand: {
3147 // If this target supports fabs/fneg natively and select is cheap,
3148 // do this efficiently.
3149 if (!TLI.isSelectExpensive() &&
3150 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
3151 TargetLowering::Legal &&
3152 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
3153 TargetLowering::Legal) {
3154 // Get the sign bit of the RHS.
3155 MVT::ValueType IVT =
3156 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
3157 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
3158 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
3159 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
3160 // Get the absolute value of the result.
3161 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
3162 // Select between the nabs and abs value based on the sign bit of
3164 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
3165 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
3168 Result = LegalizeOp(Result);
3172 // Otherwise, do bitwise ops!
3173 MVT::ValueType NVT =
3174 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
3175 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
3176 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
3177 Result = LegalizeOp(Result);
3185 Tmp1 = LegalizeOp(Node->getOperand(0));
3186 Tmp2 = LegalizeOp(Node->getOperand(1));
3187 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3188 // Since this produces two values, make sure to remember that we legalized
3190 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
3191 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
3196 Tmp1 = LegalizeOp(Node->getOperand(0));
3197 Tmp2 = LegalizeOp(Node->getOperand(1));
3198 Tmp3 = LegalizeOp(Node->getOperand(2));
3199 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3200 // Since this produces two values, make sure to remember that we legalized
3202 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
3203 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
3206 case ISD::BUILD_PAIR: {
3207 MVT::ValueType PairTy = Node->getValueType(0);
3208 // TODO: handle the case where the Lo and Hi operands are not of legal type
3209 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
3210 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
3211 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
3212 case TargetLowering::Promote:
3213 case TargetLowering::Custom:
3214 assert(0 && "Cannot promote/custom this yet!");
3215 case TargetLowering::Legal:
3216 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
3217 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
3219 case TargetLowering::Expand:
3220 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
3221 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
3222 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
3223 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
3224 TLI.getShiftAmountTy()));
3225 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
3234 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3235 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3237 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3238 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
3239 case TargetLowering::Custom:
3242 case TargetLowering::Legal:
3243 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3245 Tmp1 = TLI.LowerOperation(Result, DAG);
3246 if (Tmp1.Val) Result = Tmp1;
3249 case TargetLowering::Expand: {
3250 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
3251 bool isSigned = DivOpc == ISD::SDIV;
3252 MVT::ValueType VT = Node->getValueType(0);
3254 // See if remainder can be lowered using two-result operations.
3255 SDVTList VTs = DAG.getVTList(VT, VT);
3256 if (Node->getOpcode() == ISD::SREM &&
3257 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3258 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 1);
3261 if (Node->getOpcode() == ISD::UREM &&
3262 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3263 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 1);
3267 if (MVT::isInteger(VT)) {
3268 if (TLI.getOperationAction(DivOpc, VT) ==
3269 TargetLowering::Legal) {
3271 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
3272 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
3273 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
3274 } else if (MVT::isVector(VT)) {
3275 Result = LegalizeOp(UnrollVectorOp(Op));
3277 assert(VT == MVT::i32 &&
3278 "Cannot expand this binary operator!");
3279 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
3280 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
3282 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
3285 assert(MVT::isFloatingPoint(VT) &&
3286 "remainder op must have integer or floating-point type");
3287 if (MVT::isVector(VT)) {
3288 Result = LegalizeOp(UnrollVectorOp(Op));
3290 // Floating point mod -> fmod libcall.
3291 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
3292 RTLIB::REM_F80, RTLIB::REM_PPCF128);
3294 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3295 false/*sign irrelevant*/, Dummy);
3303 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3304 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3306 MVT::ValueType VT = Node->getValueType(0);
3307 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
3308 default: assert(0 && "This action is not supported yet!");
3309 case TargetLowering::Custom:
3312 case TargetLowering::Legal:
3313 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3314 Result = Result.getValue(0);
3315 Tmp1 = Result.getValue(1);
3318 Tmp2 = TLI.LowerOperation(Result, DAG);
3320 Result = LegalizeOp(Tmp2);
3321 Tmp1 = LegalizeOp(Tmp2.getValue(1));
3325 case TargetLowering::Expand: {
3326 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3327 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
3328 // Increment the pointer, VAList, to the next vaarg
3329 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3330 DAG.getConstant(MVT::getSizeInBits(VT)/8,
3331 TLI.getPointerTy()));
3332 // Store the incremented VAList to the legalized pointer
3333 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
3334 // Load the actual argument out of the pointer VAList
3335 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
3336 Tmp1 = LegalizeOp(Result.getValue(1));
3337 Result = LegalizeOp(Result);
3341 // Since VAARG produces two values, make sure to remember that we
3342 // legalized both of them.
3343 AddLegalizedOperand(SDOperand(Node, 0), Result);
3344 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
3345 return Op.ResNo ? Tmp1 : Result;
3349 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3350 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
3351 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
3353 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
3354 default: assert(0 && "This action is not supported yet!");
3355 case TargetLowering::Custom:
3358 case TargetLowering::Legal:
3359 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
3360 Node->getOperand(3), Node->getOperand(4));
3362 Tmp1 = TLI.LowerOperation(Result, DAG);
3363 if (Tmp1.Val) Result = Tmp1;
3366 case TargetLowering::Expand:
3367 // This defaults to loading a pointer from the input and storing it to the
3368 // output, returning the chain.
3369 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3370 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3371 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VD, 0);
3372 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VS, 0);
3378 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3379 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3381 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
3382 default: assert(0 && "This action is not supported yet!");
3383 case TargetLowering::Custom:
3386 case TargetLowering::Legal:
3387 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3389 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
3390 if (Tmp1.Val) Result = Tmp1;
3393 case TargetLowering::Expand:
3394 Result = Tmp1; // Default to a no-op, return the chain
3400 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3401 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3403 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3405 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
3406 default: assert(0 && "This action is not supported yet!");
3407 case TargetLowering::Legal: break;
3408 case TargetLowering::Custom:
3409 Tmp1 = TLI.LowerOperation(Result, DAG);
3410 if (Tmp1.Val) Result = Tmp1;
3417 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3418 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3419 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3420 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3422 assert(0 && "ROTL/ROTR legalize operation not supported");
3424 case TargetLowering::Legal:
3426 case TargetLowering::Custom:
3427 Tmp1 = TLI.LowerOperation(Result, DAG);
3428 if (Tmp1.Val) Result = Tmp1;
3430 case TargetLowering::Promote:
3431 assert(0 && "Do not know how to promote ROTL/ROTR");
3433 case TargetLowering::Expand:
3434 assert(0 && "Do not know how to expand ROTL/ROTR");
3440 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3441 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3442 case TargetLowering::Custom:
3443 assert(0 && "Cannot custom legalize this yet!");
3444 case TargetLowering::Legal:
3445 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3447 case TargetLowering::Promote: {
3448 MVT::ValueType OVT = Tmp1.getValueType();
3449 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3450 unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT);
3452 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3453 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3454 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3455 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3458 case TargetLowering::Expand:
3459 Result = ExpandBSWAP(Tmp1);
3467 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3468 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3469 case TargetLowering::Custom:
3470 case TargetLowering::Legal:
3471 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3472 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3473 TargetLowering::Custom) {
3474 Tmp1 = TLI.LowerOperation(Result, DAG);
3480 case TargetLowering::Promote: {
3481 MVT::ValueType OVT = Tmp1.getValueType();
3482 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3484 // Zero extend the argument.
3485 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3486 // Perform the larger operation, then subtract if needed.
3487 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
3488 switch (Node->getOpcode()) {
3493 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3494 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
3495 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
3497 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3498 DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1);
3501 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3502 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3503 DAG.getConstant(MVT::getSizeInBits(NVT) -
3504 MVT::getSizeInBits(OVT), NVT));
3509 case TargetLowering::Expand:
3510 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
3521 Tmp1 = LegalizeOp(Node->getOperand(0));
3522 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3523 case TargetLowering::Promote:
3524 case TargetLowering::Custom:
3527 case TargetLowering::Legal:
3528 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3530 Tmp1 = TLI.LowerOperation(Result, DAG);
3531 if (Tmp1.Val) Result = Tmp1;
3534 case TargetLowering::Expand:
3535 switch (Node->getOpcode()) {
3536 default: assert(0 && "Unreachable!");
3538 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3539 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3540 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
3543 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3544 MVT::ValueType VT = Node->getValueType(0);
3545 Tmp2 = DAG.getConstantFP(0.0, VT);
3546 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
3547 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
3548 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
3554 MVT::ValueType VT = Node->getValueType(0);
3556 // Expand unsupported unary vector operators by unrolling them.
3557 if (MVT::isVector(VT)) {
3558 Result = LegalizeOp(UnrollVectorOp(Op));
3562 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3563 switch(Node->getOpcode()) {
3565 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3566 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
3569 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
3570 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
3573 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
3574 RTLIB::COS_F80, RTLIB::COS_PPCF128);
3576 default: assert(0 && "Unreachable!");
3579 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3580 false/*sign irrelevant*/, Dummy);
3588 MVT::ValueType VT = Node->getValueType(0);
3590 // Expand unsupported unary vector operators by unrolling them.
3591 if (MVT::isVector(VT)) {
3592 Result = LegalizeOp(UnrollVectorOp(Op));
3596 // We always lower FPOWI into a libcall. No target support for it yet.
3597 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
3598 RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
3600 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3601 false/*sign irrelevant*/, Dummy);
3604 case ISD::BIT_CONVERT:
3605 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3606 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3607 Node->getValueType(0));
3608 } else if (MVT::isVector(Op.getOperand(0).getValueType())) {
3609 // The input has to be a vector type, we have to either scalarize it, pack
3610 // it, or convert it based on whether the input vector type is legal.
3611 SDNode *InVal = Node->getOperand(0).Val;
3612 int InIx = Node->getOperand(0).ResNo;
3613 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx));
3614 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx));
3616 // Figure out if there is a simple type corresponding to this Vector
3617 // type. If so, convert to the vector type.
3618 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
3619 if (TLI.isTypeLegal(TVT)) {
3620 // Turn this into a bit convert of the vector input.
3621 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3622 LegalizeOp(Node->getOperand(0)));
3624 } else if (NumElems == 1) {
3625 // Turn this into a bit convert of the scalar input.
3626 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3627 ScalarizeVectorOp(Node->getOperand(0)));
3630 // FIXME: UNIMP! Store then reload
3631 assert(0 && "Cast from unsupported vector type not implemented yet!");
3634 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3635 Node->getOperand(0).getValueType())) {
3636 default: assert(0 && "Unknown operation action!");
3637 case TargetLowering::Expand:
3638 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3639 Node->getValueType(0));
3641 case TargetLowering::Legal:
3642 Tmp1 = LegalizeOp(Node->getOperand(0));
3643 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3649 // Conversion operators. The source and destination have different types.
3650 case ISD::SINT_TO_FP:
3651 case ISD::UINT_TO_FP: {
3652 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
3653 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3655 switch (TLI.getOperationAction(Node->getOpcode(),
3656 Node->getOperand(0).getValueType())) {
3657 default: assert(0 && "Unknown operation action!");
3658 case TargetLowering::Custom:
3661 case TargetLowering::Legal:
3662 Tmp1 = LegalizeOp(Node->getOperand(0));
3663 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3665 Tmp1 = TLI.LowerOperation(Result, DAG);
3666 if (Tmp1.Val) Result = Tmp1;
3669 case TargetLowering::Expand:
3670 Result = ExpandLegalINT_TO_FP(isSigned,
3671 LegalizeOp(Node->getOperand(0)),
3672 Node->getValueType(0));
3674 case TargetLowering::Promote:
3675 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
3676 Node->getValueType(0),
3682 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
3683 Node->getValueType(0), Node->getOperand(0));
3686 Tmp1 = PromoteOp(Node->getOperand(0));
3688 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
3689 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
3691 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
3692 Node->getOperand(0).getValueType());
3694 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3695 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
3701 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3703 Tmp1 = LegalizeOp(Node->getOperand(0));
3704 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3707 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3709 // Since the result is legal, we should just be able to truncate the low
3710 // part of the source.
3711 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
3714 Result = PromoteOp(Node->getOperand(0));
3715 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
3720 case ISD::FP_TO_SINT:
3721 case ISD::FP_TO_UINT:
3722 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3724 Tmp1 = LegalizeOp(Node->getOperand(0));
3726 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
3727 default: assert(0 && "Unknown operation action!");
3728 case TargetLowering::Custom:
3731 case TargetLowering::Legal:
3732 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3734 Tmp1 = TLI.LowerOperation(Result, DAG);
3735 if (Tmp1.Val) Result = Tmp1;
3738 case TargetLowering::Promote:
3739 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
3740 Node->getOpcode() == ISD::FP_TO_SINT);
3742 case TargetLowering::Expand:
3743 if (Node->getOpcode() == ISD::FP_TO_UINT) {
3744 SDOperand True, False;
3745 MVT::ValueType VT = Node->getOperand(0).getValueType();
3746 MVT::ValueType NVT = Node->getValueType(0);
3747 const uint64_t zero[] = {0, 0};
3748 APFloat apf = APFloat(APInt(MVT::getSizeInBits(VT), 2, zero));
3749 APInt x = APInt::getSignBit(MVT::getSizeInBits(NVT));
3750 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
3751 Tmp2 = DAG.getConstantFP(apf, VT);
3752 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
3753 Node->getOperand(0), Tmp2, ISD::SETLT);
3754 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
3755 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
3756 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
3758 False = DAG.getNode(ISD::XOR, NVT, False,
3759 DAG.getConstant(x, NVT));
3760 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
3763 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
3769 MVT::ValueType VT = Op.getValueType();
3770 MVT::ValueType OVT = Node->getOperand(0).getValueType();
3771 // Convert ppcf128 to i32
3772 if (OVT == MVT::ppcf128 && VT == MVT::i32) {
3773 if (Node->getOpcode() == ISD::FP_TO_SINT) {
3774 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128,
3775 Node->getOperand(0), DAG.getValueType(MVT::f64));
3776 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result,
3777 DAG.getIntPtrConstant(1));
3778 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result);
3780 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
3781 APFloat apf = APFloat(APInt(128, 2, TwoE31));
3782 Tmp2 = DAG.getConstantFP(apf, OVT);
3783 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
3784 // FIXME: generated code sucks.
3785 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2,
3786 DAG.getNode(ISD::ADD, MVT::i32,
3787 DAG.getNode(ISD::FP_TO_SINT, VT,
3788 DAG.getNode(ISD::FSUB, OVT,
3789 Node->getOperand(0), Tmp2)),
3790 DAG.getConstant(0x80000000, MVT::i32)),
3791 DAG.getNode(ISD::FP_TO_SINT, VT,
3792 Node->getOperand(0)),
3793 DAG.getCondCode(ISD::SETGE));
3797 // Convert f32 / f64 to i32 / i64.
3798 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3799 switch (Node->getOpcode()) {
3800 case ISD::FP_TO_SINT: {
3801 if (OVT == MVT::f32)
3802 LC = (VT == MVT::i32)
3803 ? RTLIB::FPTOSINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3804 else if (OVT == MVT::f64)
3805 LC = (VT == MVT::i32)
3806 ? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3807 else if (OVT == MVT::f80) {
3808 assert(VT == MVT::i64);
3809 LC = RTLIB::FPTOSINT_F80_I64;
3811 else if (OVT == MVT::ppcf128) {
3812 assert(VT == MVT::i64);
3813 LC = RTLIB::FPTOSINT_PPCF128_I64;
3817 case ISD::FP_TO_UINT: {
3818 if (OVT == MVT::f32)
3819 LC = (VT == MVT::i32)
3820 ? RTLIB::FPTOUINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3821 else if (OVT == MVT::f64)
3822 LC = (VT == MVT::i32)
3823 ? RTLIB::FPTOUINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3824 else if (OVT == MVT::f80) {
3825 LC = (VT == MVT::i32)
3826 ? RTLIB::FPTOUINT_F80_I32 : RTLIB::FPTOUINT_F80_I64;
3828 else if (OVT == MVT::ppcf128) {
3829 assert(VT == MVT::i64);
3830 LC = RTLIB::FPTOUINT_PPCF128_I64;
3834 default: assert(0 && "Unreachable!");
3837 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3838 false/*sign irrelevant*/, Dummy);
3842 Tmp1 = PromoteOp(Node->getOperand(0));
3843 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
3844 Result = LegalizeOp(Result);
3849 case ISD::FP_EXTEND: {
3850 MVT::ValueType DstVT = Op.getValueType();
3851 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3852 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3853 // The only other way we can lower this is to turn it into a STORE,
3854 // LOAD pair, targetting a temporary location (a stack slot).
3855 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT);
3858 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3859 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3861 Tmp1 = LegalizeOp(Node->getOperand(0));
3862 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3865 Tmp1 = PromoteOp(Node->getOperand(0));
3866 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1);
3871 case ISD::FP_ROUND: {
3872 MVT::ValueType DstVT = Op.getValueType();
3873 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3874 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3875 if (SrcVT == MVT::ppcf128) {
3877 ExpandOp(Node->getOperand(0), Lo, Result);
3878 // Round it the rest of the way (e.g. to f32) if needed.
3879 if (DstVT!=MVT::f64)
3880 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1));
3883 // The only other way we can lower this is to turn it into a STORE,
3884 // LOAD pair, targetting a temporary location (a stack slot).
3885 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT);
3888 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3889 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3891 Tmp1 = LegalizeOp(Node->getOperand(0));
3892 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3895 Tmp1 = PromoteOp(Node->getOperand(0));
3896 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1,
3897 Node->getOperand(1));
3902 case ISD::ANY_EXTEND:
3903 case ISD::ZERO_EXTEND:
3904 case ISD::SIGN_EXTEND:
3905 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3906 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3908 Tmp1 = LegalizeOp(Node->getOperand(0));
3909 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3910 TargetLowering::Custom) {
3911 Tmp2 = TLI.LowerOperation(Result, DAG);
3916 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3919 switch (Node->getOpcode()) {
3920 case ISD::ANY_EXTEND:
3921 Tmp1 = PromoteOp(Node->getOperand(0));
3922 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
3924 case ISD::ZERO_EXTEND:
3925 Result = PromoteOp(Node->getOperand(0));
3926 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3927 Result = DAG.getZeroExtendInReg(Result,
3928 Node->getOperand(0).getValueType());
3930 case ISD::SIGN_EXTEND:
3931 Result = PromoteOp(Node->getOperand(0));
3932 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3933 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3935 DAG.getValueType(Node->getOperand(0).getValueType()));
3940 case ISD::FP_ROUND_INREG:
3941 case ISD::SIGN_EXTEND_INREG: {
3942 Tmp1 = LegalizeOp(Node->getOperand(0));
3943 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3945 // If this operation is not supported, convert it to a shl/shr or load/store
3947 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
3948 default: assert(0 && "This action not supported for this op yet!");
3949 case TargetLowering::Legal:
3950 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3952 case TargetLowering::Expand:
3953 // If this is an integer extend and shifts are supported, do that.
3954 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
3955 // NOTE: we could fall back on load/store here too for targets without
3956 // SAR. However, it is doubtful that any exist.
3957 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
3958 MVT::getSizeInBits(ExtraVT);
3959 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
3960 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
3961 Node->getOperand(0), ShiftCst);
3962 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
3964 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
3965 // The only way we can lower this is to turn it into a TRUNCSTORE,
3966 // EXTLOAD pair, targetting a temporary location (a stack slot).
3968 // NOTE: there is a choice here between constantly creating new stack
3969 // slots and always reusing the same one. We currently always create
3970 // new ones, as reuse may inhibit scheduling.
3971 Result = EmitStackConvert(Node->getOperand(0), ExtraVT,
3972 Node->getValueType(0));
3974 assert(0 && "Unknown op");
3980 case ISD::TRAMPOLINE: {
3982 for (unsigned i = 0; i != 6; ++i)
3983 Ops[i] = LegalizeOp(Node->getOperand(i));
3984 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
3985 // The only option for this node is to custom lower it.
3986 Result = TLI.LowerOperation(Result, DAG);
3987 assert(Result.Val && "Should always custom lower!");
3989 // Since trampoline produces two values, make sure to remember that we
3990 // legalized both of them.
3991 Tmp1 = LegalizeOp(Result.getValue(1));
3992 Result = LegalizeOp(Result);
3993 AddLegalizedOperand(SDOperand(Node, 0), Result);
3994 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
3995 return Op.ResNo ? Tmp1 : Result;
3997 case ISD::FLT_ROUNDS_: {
3998 MVT::ValueType VT = Node->getValueType(0);
3999 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4000 default: assert(0 && "This action not supported for this op yet!");
4001 case TargetLowering::Custom:
4002 Result = TLI.LowerOperation(Op, DAG);
4003 if (Result.Val) break;
4005 case TargetLowering::Legal:
4006 // If this operation is not supported, lower it to constant 1
4007 Result = DAG.getConstant(1, VT);
4012 MVT::ValueType VT = Node->getValueType(0);
4013 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4014 default: assert(0 && "This action not supported for this op yet!");
4015 case TargetLowering::Legal:
4016 Tmp1 = LegalizeOp(Node->getOperand(0));
4017 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4019 case TargetLowering::Custom:
4020 Result = TLI.LowerOperation(Op, DAG);
4021 if (Result.Val) break;
4023 case TargetLowering::Expand:
4024 // If this operation is not supported, lower it to 'abort()' call
4025 Tmp1 = LegalizeOp(Node->getOperand(0));
4026 TargetLowering::ArgListTy Args;
4027 std::pair<SDOperand,SDOperand> CallResult =
4028 TLI.LowerCallTo(Tmp1, Type::VoidTy,
4029 false, false, false, CallingConv::C, false,
4030 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
4032 Result = CallResult.second;
4039 assert(Result.getValueType() == Op.getValueType() &&
4040 "Bad legalization!");
4042 // Make sure that the generated code is itself legal.
4044 Result = LegalizeOp(Result);
4046 // Note that LegalizeOp may be reentered even from single-use nodes, which
4047 // means that we always must cache transformed nodes.
4048 AddLegalizedOperand(Op, Result);
4052 /// PromoteOp - Given an operation that produces a value in an invalid type,
4053 /// promote it to compute the value into a larger type. The produced value will
4054 /// have the correct bits for the low portion of the register, but no guarantee
4055 /// is made about the top bits: it may be zero, sign-extended, or garbage.
4056 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
4057 MVT::ValueType VT = Op.getValueType();
4058 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4059 assert(getTypeAction(VT) == Promote &&
4060 "Caller should expand or legalize operands that are not promotable!");
4061 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
4062 "Cannot promote to smaller type!");
4064 SDOperand Tmp1, Tmp2, Tmp3;
4066 SDNode *Node = Op.Val;
4068 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
4069 if (I != PromotedNodes.end()) return I->second;
4071 switch (Node->getOpcode()) {
4072 case ISD::CopyFromReg:
4073 assert(0 && "CopyFromReg must be legal!");
4076 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
4078 assert(0 && "Do not know how to promote this operator!");
4081 Result = DAG.getNode(ISD::UNDEF, NVT);
4085 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
4087 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
4088 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
4090 case ISD::ConstantFP:
4091 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
4092 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
4096 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
4097 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
4098 Node->getOperand(1), Node->getOperand(2));
4102 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4104 Result = LegalizeOp(Node->getOperand(0));
4105 assert(Result.getValueType() >= NVT &&
4106 "This truncation doesn't make sense!");
4107 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
4108 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
4111 // The truncation is not required, because we don't guarantee anything
4112 // about high bits anyway.
4113 Result = PromoteOp(Node->getOperand(0));
4116 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4117 // Truncate the low part of the expanded value to the result type
4118 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
4121 case ISD::SIGN_EXTEND:
4122 case ISD::ZERO_EXTEND:
4123 case ISD::ANY_EXTEND:
4124 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4125 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
4127 // Input is legal? Just do extend all the way to the larger type.
4128 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4131 // Promote the reg if it's smaller.
4132 Result = PromoteOp(Node->getOperand(0));
4133 // The high bits are not guaranteed to be anything. Insert an extend.
4134 if (Node->getOpcode() == ISD::SIGN_EXTEND)
4135 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4136 DAG.getValueType(Node->getOperand(0).getValueType()));
4137 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
4138 Result = DAG.getZeroExtendInReg(Result,
4139 Node->getOperand(0).getValueType());
4143 case ISD::BIT_CONVERT:
4144 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
4145 Node->getValueType(0));
4146 Result = PromoteOp(Result);
4149 case ISD::FP_EXTEND:
4150 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
4152 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4153 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
4154 case Promote: assert(0 && "Unreachable with 2 FP types!");
4156 if (Node->getConstantOperandVal(1) == 0) {
4157 // Input is legal? Do an FP_ROUND_INREG.
4158 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
4159 DAG.getValueType(VT));
4161 // Just remove the truncate, it isn't affecting the value.
4162 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0),
4163 Node->getOperand(1));
4168 case ISD::SINT_TO_FP:
4169 case ISD::UINT_TO_FP:
4170 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4172 // No extra round required here.
4173 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4177 Result = PromoteOp(Node->getOperand(0));
4178 if (Node->getOpcode() == ISD::SINT_TO_FP)
4179 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
4181 DAG.getValueType(Node->getOperand(0).getValueType()));
4183 Result = DAG.getZeroExtendInReg(Result,
4184 Node->getOperand(0).getValueType());
4185 // No extra round required here.
4186 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
4189 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
4190 Node->getOperand(0));
4191 // Round if we cannot tolerate excess precision.
4192 if (NoExcessFPPrecision)
4193 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4194 DAG.getValueType(VT));
4199 case ISD::SIGN_EXTEND_INREG:
4200 Result = PromoteOp(Node->getOperand(0));
4201 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4202 Node->getOperand(1));
4204 case ISD::FP_TO_SINT:
4205 case ISD::FP_TO_UINT:
4206 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4209 Tmp1 = Node->getOperand(0);
4212 // The input result is prerounded, so we don't have to do anything
4214 Tmp1 = PromoteOp(Node->getOperand(0));
4217 // If we're promoting a UINT to a larger size, check to see if the new node
4218 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
4219 // we can use that instead. This allows us to generate better code for
4220 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
4221 // legal, such as PowerPC.
4222 if (Node->getOpcode() == ISD::FP_TO_UINT &&
4223 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
4224 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
4225 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
4226 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
4228 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4234 Tmp1 = PromoteOp(Node->getOperand(0));
4235 assert(Tmp1.getValueType() == NVT);
4236 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4237 // NOTE: we do not have to do any extra rounding here for
4238 // NoExcessFPPrecision, because we know the input will have the appropriate
4239 // precision, and these operations don't modify precision at all.
4245 Tmp1 = PromoteOp(Node->getOperand(0));
4246 assert(Tmp1.getValueType() == NVT);
4247 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4248 if (NoExcessFPPrecision)
4249 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4250 DAG.getValueType(VT));
4254 // Promote f32 powi to f64 powi. Note that this could insert a libcall
4255 // directly as well, which may be better.
4256 Tmp1 = PromoteOp(Node->getOperand(0));
4257 assert(Tmp1.getValueType() == NVT);
4258 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1));
4259 if (NoExcessFPPrecision)
4260 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4261 DAG.getValueType(VT));
4265 case ISD::ATOMIC_LCS: {
4266 Tmp2 = PromoteOp(Node->getOperand(2));
4267 Tmp3 = PromoteOp(Node->getOperand(3));
4268 Result = DAG.getAtomic(Node->getOpcode(), Node->getOperand(0),
4269 Node->getOperand(1), Tmp2, Tmp3,
4270 cast<AtomicSDNode>(Node)->getVT());
4271 // Remember that we legalized the chain.
4272 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4275 case ISD::ATOMIC_LAS:
4276 case ISD::ATOMIC_SWAP: {
4277 Tmp2 = PromoteOp(Node->getOperand(2));
4278 Result = DAG.getAtomic(Node->getOpcode(), Node->getOperand(0),
4279 Node->getOperand(1), Tmp2,
4280 cast<AtomicSDNode>(Node)->getVT());
4281 // Remember that we legalized the chain.
4282 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4292 // The input may have strange things in the top bits of the registers, but
4293 // these operations don't care. They may have weird bits going out, but
4294 // that too is okay if they are integer operations.
4295 Tmp1 = PromoteOp(Node->getOperand(0));
4296 Tmp2 = PromoteOp(Node->getOperand(1));
4297 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4298 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4303 Tmp1 = PromoteOp(Node->getOperand(0));
4304 Tmp2 = PromoteOp(Node->getOperand(1));
4305 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4306 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4308 // Floating point operations will give excess precision that we may not be
4309 // able to tolerate. If we DO allow excess precision, just leave it,
4310 // otherwise excise it.
4311 // FIXME: Why would we need to round FP ops more than integer ones?
4312 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
4313 if (NoExcessFPPrecision)
4314 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4315 DAG.getValueType(VT));
4320 // These operators require that their input be sign extended.
4321 Tmp1 = PromoteOp(Node->getOperand(0));
4322 Tmp2 = PromoteOp(Node->getOperand(1));
4323 if (MVT::isInteger(NVT)) {
4324 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4325 DAG.getValueType(VT));
4326 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4327 DAG.getValueType(VT));
4329 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4331 // Perform FP_ROUND: this is probably overly pessimistic.
4332 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
4333 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4334 DAG.getValueType(VT));
4338 case ISD::FCOPYSIGN:
4339 // These operators require that their input be fp extended.
4340 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4341 case Expand: assert(0 && "not implemented");
4342 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break;
4343 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break;
4345 switch (getTypeAction(Node->getOperand(1).getValueType())) {
4346 case Expand: assert(0 && "not implemented");
4347 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
4348 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
4350 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4352 // Perform FP_ROUND: this is probably overly pessimistic.
4353 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
4354 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4355 DAG.getValueType(VT));
4360 // These operators require that their input be zero extended.
4361 Tmp1 = PromoteOp(Node->getOperand(0));
4362 Tmp2 = PromoteOp(Node->getOperand(1));
4363 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
4364 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4365 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4366 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4370 Tmp1 = PromoteOp(Node->getOperand(0));
4371 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
4374 // The input value must be properly sign extended.
4375 Tmp1 = PromoteOp(Node->getOperand(0));
4376 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4377 DAG.getValueType(VT));
4378 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
4381 // The input value must be properly zero extended.
4382 Tmp1 = PromoteOp(Node->getOperand(0));
4383 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4384 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
4388 Tmp1 = Node->getOperand(0); // Get the chain.
4389 Tmp2 = Node->getOperand(1); // Get the pointer.
4390 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
4391 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
4392 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
4394 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
4395 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
4396 // Increment the pointer, VAList, to the next vaarg
4397 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
4398 DAG.getConstant(MVT::getSizeInBits(VT)/8,
4399 TLI.getPointerTy()));
4400 // Store the incremented VAList to the legalized pointer
4401 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
4402 // Load the actual argument out of the pointer VAList
4403 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
4405 // Remember that we legalized the chain.
4406 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4410 LoadSDNode *LD = cast<LoadSDNode>(Node);
4411 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
4412 ? ISD::EXTLOAD : LD->getExtensionType();
4413 Result = DAG.getExtLoad(ExtType, NVT,
4414 LD->getChain(), LD->getBasePtr(),
4415 LD->getSrcValue(), LD->getSrcValueOffset(),
4418 LD->getAlignment());
4419 // Remember that we legalized the chain.
4420 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4424 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
4425 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
4426 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
4428 case ISD::SELECT_CC:
4429 Tmp2 = PromoteOp(Node->getOperand(2)); // True
4430 Tmp3 = PromoteOp(Node->getOperand(3)); // False
4431 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4432 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
4435 Tmp1 = Node->getOperand(0);
4436 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
4437 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
4438 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
4439 DAG.getConstant(MVT::getSizeInBits(NVT) -
4440 MVT::getSizeInBits(VT),
4441 TLI.getShiftAmountTy()));
4446 // Zero extend the argument
4447 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4448 // Perform the larger operation, then subtract if needed.
4449 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4450 switch(Node->getOpcode()) {
4455 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
4456 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
4457 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
4459 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
4460 DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1);
4463 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4464 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
4465 DAG.getConstant(MVT::getSizeInBits(NVT) -
4466 MVT::getSizeInBits(VT), NVT));
4470 case ISD::EXTRACT_SUBVECTOR:
4471 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
4473 case ISD::EXTRACT_VECTOR_ELT:
4474 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
4478 assert(Result.Val && "Didn't set a result!");
4480 // Make sure the result is itself legal.
4481 Result = LegalizeOp(Result);
4483 // Remember that we promoted this!
4484 AddPromotedOperand(Op, Result);
4488 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
4489 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
4490 /// based on the vector type. The return type of this matches the element type
4491 /// of the vector, which may not be legal for the target.
4492 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
4493 // We know that operand #0 is the Vec vector. If the index is a constant
4494 // or if the invec is a supported hardware type, we can use it. Otherwise,
4495 // lower to a store then an indexed load.
4496 SDOperand Vec = Op.getOperand(0);
4497 SDOperand Idx = Op.getOperand(1);
4499 MVT::ValueType TVT = Vec.getValueType();
4500 unsigned NumElems = MVT::getVectorNumElements(TVT);
4502 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
4503 default: assert(0 && "This action is not supported yet!");
4504 case TargetLowering::Custom: {
4505 Vec = LegalizeOp(Vec);
4506 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4507 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG);
4512 case TargetLowering::Legal:
4513 if (isTypeLegal(TVT)) {
4514 Vec = LegalizeOp(Vec);
4515 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4519 case TargetLowering::Expand:
4523 if (NumElems == 1) {
4524 // This must be an access of the only element. Return it.
4525 Op = ScalarizeVectorOp(Vec);
4526 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
4527 unsigned NumLoElts = 1 << Log2_32(NumElems-1);
4528 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4530 SplitVectorOp(Vec, Lo, Hi);
4531 if (CIdx->getValue() < NumLoElts) {
4535 Idx = DAG.getConstant(CIdx->getValue() - NumLoElts,
4536 Idx.getValueType());
4539 // It's now an extract from the appropriate high or low part. Recurse.
4540 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4541 Op = ExpandEXTRACT_VECTOR_ELT(Op);
4543 // Store the value to a temporary stack slot, then LOAD the scalar
4544 // element back out.
4545 SDOperand StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
4546 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
4548 // Add the offset to the index.
4549 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
4550 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
4551 DAG.getConstant(EltSize, Idx.getValueType()));
4553 if (MVT::getSizeInBits(Idx.getValueType()) >
4554 MVT::getSizeInBits(TLI.getPointerTy()))
4555 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx);
4557 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
4559 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
4561 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
4566 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
4567 /// we assume the operation can be split if it is not already legal.
4568 SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) {
4569 // We know that operand #0 is the Vec vector. For now we assume the index
4570 // is a constant and that the extracted result is a supported hardware type.
4571 SDOperand Vec = Op.getOperand(0);
4572 SDOperand Idx = LegalizeOp(Op.getOperand(1));
4574 unsigned NumElems = MVT::getVectorNumElements(Vec.getValueType());
4576 if (NumElems == MVT::getVectorNumElements(Op.getValueType())) {
4577 // This must be an access of the desired vector length. Return it.
4581 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4583 SplitVectorOp(Vec, Lo, Hi);
4584 if (CIdx->getValue() < NumElems/2) {
4588 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
4591 // It's now an extract from the appropriate high or low part. Recurse.
4592 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4593 return ExpandEXTRACT_SUBVECTOR(Op);
4596 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
4597 /// with condition CC on the current target. This usually involves legalizing
4598 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
4599 /// there may be no choice but to create a new SetCC node to represent the
4600 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
4601 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
4602 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
4605 SDOperand Tmp1, Tmp2, Tmp3, Result;
4607 switch (getTypeAction(LHS.getValueType())) {
4609 Tmp1 = LegalizeOp(LHS); // LHS
4610 Tmp2 = LegalizeOp(RHS); // RHS
4613 Tmp1 = PromoteOp(LHS); // LHS
4614 Tmp2 = PromoteOp(RHS); // RHS
4616 // If this is an FP compare, the operands have already been extended.
4617 if (MVT::isInteger(LHS.getValueType())) {
4618 MVT::ValueType VT = LHS.getValueType();
4619 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4621 // Otherwise, we have to insert explicit sign or zero extends. Note
4622 // that we could insert sign extends for ALL conditions, but zero extend
4623 // is cheaper on many machines (an AND instead of two shifts), so prefer
4625 switch (cast<CondCodeSDNode>(CC)->get()) {
4626 default: assert(0 && "Unknown integer comparison!");
4633 // ALL of these operations will work if we either sign or zero extend
4634 // the operands (including the unsigned comparisons!). Zero extend is
4635 // usually a simpler/cheaper operation, so prefer it.
4636 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4637 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4643 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4644 DAG.getValueType(VT));
4645 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4646 DAG.getValueType(VT));
4652 MVT::ValueType VT = LHS.getValueType();
4653 if (VT == MVT::f32 || VT == MVT::f64) {
4654 // Expand into one or more soft-fp libcall(s).
4655 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL;
4656 switch (cast<CondCodeSDNode>(CC)->get()) {
4659 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4663 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
4667 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4671 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4675 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4679 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4682 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4685 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
4688 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4689 switch (cast<CondCodeSDNode>(CC)->get()) {
4691 // SETONE = SETOLT | SETOGT
4692 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4695 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4698 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4701 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4704 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4707 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4709 default: assert(0 && "Unsupported FP setcc!");
4714 Tmp1 = ExpandLibCall(TLI.getLibcallName(LC1),
4715 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4716 false /*sign irrelevant*/, Dummy);
4717 Tmp2 = DAG.getConstant(0, MVT::i32);
4718 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
4719 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
4720 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC);
4721 LHS = ExpandLibCall(TLI.getLibcallName(LC2),
4722 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4723 false /*sign irrelevant*/, Dummy);
4724 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2,
4725 DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
4726 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4734 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
4735 ExpandOp(LHS, LHSLo, LHSHi);
4736 ExpandOp(RHS, RHSLo, RHSHi);
4737 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
4739 if (VT==MVT::ppcf128) {
4740 // FIXME: This generated code sucks. We want to generate
4741 // FCMP crN, hi1, hi2
4743 // FCMP crN, lo1, lo2
4744 // The following can be improved, but not that much.
4745 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
4746 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, CCCode);
4747 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4748 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETNE);
4749 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, CCCode);
4750 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4751 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
4760 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
4761 if (RHSCST->isAllOnesValue()) {
4762 // Comparison to -1.
4763 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
4768 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
4769 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
4770 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4771 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
4774 // If this is a comparison of the sign bit, just look at the top part.
4776 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
4777 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
4778 CST->getValue() == 0) || // X < 0
4779 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
4780 CST->isAllOnesValue())) { // X > -1
4786 // FIXME: This generated code sucks.
4787 ISD::CondCode LowCC;
4789 default: assert(0 && "Unknown integer setcc!");
4791 case ISD::SETULT: LowCC = ISD::SETULT; break;
4793 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
4795 case ISD::SETULE: LowCC = ISD::SETULE; break;
4797 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
4800 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
4801 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
4802 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
4804 // NOTE: on targets without efficient SELECT of bools, we can always use
4805 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
4806 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
4807 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC,
4808 false, DagCombineInfo);
4810 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
4811 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
4812 CCCode, false, DagCombineInfo);
4814 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi,CC);
4816 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
4817 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
4818 if ((Tmp1C && Tmp1C->getValue() == 0) ||
4819 (Tmp2C && Tmp2C->getValue() == 0 &&
4820 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
4821 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
4822 (Tmp2C && Tmp2C->getValue() == 1 &&
4823 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
4824 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
4825 // low part is known false, returns high part.
4826 // For LE / GE, if high part is known false, ignore the low part.
4827 // For LT / GT, if high part is known true, ignore the low part.
4831 Result = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
4832 ISD::SETEQ, false, DagCombineInfo);
4834 Result=DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
4835 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
4836 Result, Tmp1, Tmp2));
4847 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
4848 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
4849 /// a load from the stack slot to DestVT, extending it if needed.
4850 /// The resultant code need not be legal.
4851 SDOperand SelectionDAGLegalize::EmitStackConvert(SDOperand SrcOp,
4852 MVT::ValueType SlotVT,
4853 MVT::ValueType DestVT) {
4854 // Create the stack frame object.
4855 SDOperand FIPtr = DAG.CreateStackTemporary(SlotVT);
4857 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
4858 int SPFI = StackPtrFI->getIndex();
4860 unsigned SrcSize = MVT::getSizeInBits(SrcOp.getValueType());
4861 unsigned SlotSize = MVT::getSizeInBits(SlotVT);
4862 unsigned DestSize = MVT::getSizeInBits(DestVT);
4864 // Emit a store to the stack slot. Use a truncstore if the input value is
4865 // later than DestVT.
4867 if (SrcSize > SlotSize)
4868 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr,
4869 PseudoSourceValue::getFixedStack(),
4872 assert(SrcSize == SlotSize && "Invalid store");
4873 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr,
4874 PseudoSourceValue::getFixedStack(),
4878 // Result is a load from the stack slot.
4879 if (SlotSize == DestSize)
4880 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0);
4882 assert(SlotSize < DestSize && "Unknown extension!");
4883 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT);
4886 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
4887 // Create a vector sized/aligned stack slot, store the value to element #0,
4888 // then load the whole vector back out.
4889 SDOperand StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
4891 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
4892 int SPFI = StackPtrFI->getIndex();
4894 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
4895 PseudoSourceValue::getFixedStack(), SPFI);
4896 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,
4897 PseudoSourceValue::getFixedStack(), SPFI);
4901 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
4902 /// support the operation, but do support the resultant vector type.
4903 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
4905 // If the only non-undef value is the low element, turn this into a
4906 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
4907 unsigned NumElems = Node->getNumOperands();
4908 bool isOnlyLowElement = true;
4909 SDOperand SplatValue = Node->getOperand(0);
4910 std::map<SDOperand, std::vector<unsigned> > Values;
4911 Values[SplatValue].push_back(0);
4912 bool isConstant = true;
4913 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
4914 SplatValue.getOpcode() != ISD::UNDEF)
4917 for (unsigned i = 1; i < NumElems; ++i) {
4918 SDOperand V = Node->getOperand(i);
4919 Values[V].push_back(i);
4920 if (V.getOpcode() != ISD::UNDEF)
4921 isOnlyLowElement = false;
4922 if (SplatValue != V)
4923 SplatValue = SDOperand(0,0);
4925 // If this isn't a constant element or an undef, we can't use a constant
4927 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
4928 V.getOpcode() != ISD::UNDEF)
4932 if (isOnlyLowElement) {
4933 // If the low element is an undef too, then this whole things is an undef.
4934 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
4935 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
4936 // Otherwise, turn this into a scalar_to_vector node.
4937 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4938 Node->getOperand(0));
4941 // If all elements are constants, create a load from the constant pool.
4943 MVT::ValueType VT = Node->getValueType(0);
4945 MVT::getTypeForValueType(Node->getOperand(0).getValueType());
4946 std::vector<Constant*> CV;
4947 for (unsigned i = 0, e = NumElems; i != e; ++i) {
4948 if (ConstantFPSDNode *V =
4949 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
4950 CV.push_back(ConstantFP::get(OpNTy, V->getValueAPF()));
4951 } else if (ConstantSDNode *V =
4952 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
4953 CV.push_back(ConstantInt::get(OpNTy, V->getValue()));
4955 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
4956 CV.push_back(UndefValue::get(OpNTy));
4959 Constant *CP = ConstantVector::get(CV);
4960 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
4961 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4962 PseudoSourceValue::getConstantPool(), 0);
4965 if (SplatValue.Val) { // Splat of one value?
4966 // Build the shuffle constant vector: <0, 0, 0, 0>
4967 MVT::ValueType MaskVT =
4968 MVT::getIntVectorWithNumElements(NumElems);
4969 SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT));
4970 std::vector<SDOperand> ZeroVec(NumElems, Zero);
4971 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4972 &ZeroVec[0], ZeroVec.size());
4974 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4975 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
4976 // Get the splatted value into the low element of a vector register.
4977 SDOperand LowValVec =
4978 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
4980 // Return shuffle(LowValVec, undef, <0,0,0,0>)
4981 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
4982 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
4987 // If there are only two unique elements, we may be able to turn this into a
4989 if (Values.size() == 2) {
4990 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
4991 MVT::ValueType MaskVT =
4992 MVT::getIntVectorWithNumElements(NumElems);
4993 std::vector<SDOperand> MaskVec(NumElems);
4995 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
4996 E = Values.end(); I != E; ++I) {
4997 for (std::vector<unsigned>::iterator II = I->second.begin(),
4998 EE = I->second.end(); II != EE; ++II)
4999 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorElementType(MaskVT));
5002 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
5003 &MaskVec[0], MaskVec.size());
5005 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
5006 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
5007 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
5008 SmallVector<SDOperand, 8> Ops;
5009 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
5010 E = Values.end(); I != E; ++I) {
5011 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
5015 Ops.push_back(ShuffleMask);
5017 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
5018 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0),
5019 &Ops[0], Ops.size());
5023 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
5024 // aligned object on the stack, store each element into it, then load
5025 // the result as a vector.
5026 MVT::ValueType VT = Node->getValueType(0);
5027 // Create the stack frame object.
5028 SDOperand FIPtr = DAG.CreateStackTemporary(VT);
5030 // Emit a store of each element to the stack slot.
5031 SmallVector<SDOperand, 8> Stores;
5032 unsigned TypeByteSize =
5033 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
5034 // Store (in the right endianness) the elements to memory.
5035 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5036 // Ignore undef elements.
5037 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
5039 unsigned Offset = TypeByteSize*i;
5041 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
5042 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
5044 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
5048 SDOperand StoreChain;
5049 if (!Stores.empty()) // Not all undef elements?
5050 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
5051 &Stores[0], Stores.size());
5053 StoreChain = DAG.getEntryNode();
5055 // Result is a load from the stack slot.
5056 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
5059 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
5060 SDOperand Op, SDOperand Amt,
5061 SDOperand &Lo, SDOperand &Hi) {
5062 // Expand the subcomponents.
5063 SDOperand LHSL, LHSH;
5064 ExpandOp(Op, LHSL, LHSH);
5066 SDOperand Ops[] = { LHSL, LHSH, Amt };
5067 MVT::ValueType VT = LHSL.getValueType();
5068 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
5069 Hi = Lo.getValue(1);
5073 /// ExpandShift - Try to find a clever way to expand this shift operation out to
5074 /// smaller elements. If we can't find a way that is more efficient than a
5075 /// libcall on this target, return false. Otherwise, return true with the
5076 /// low-parts expanded into Lo and Hi.
5077 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
5078 SDOperand &Lo, SDOperand &Hi) {
5079 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
5080 "This is not a shift!");
5082 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
5083 SDOperand ShAmt = LegalizeOp(Amt);
5084 MVT::ValueType ShTy = ShAmt.getValueType();
5085 unsigned ShBits = MVT::getSizeInBits(ShTy);
5086 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
5087 unsigned NVTBits = MVT::getSizeInBits(NVT);
5089 // Handle the case when Amt is an immediate.
5090 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
5091 unsigned Cst = CN->getValue();
5092 // Expand the incoming operand to be shifted, so that we have its parts
5094 ExpandOp(Op, InL, InH);
5098 Lo = DAG.getConstant(0, NVT);
5099 Hi = DAG.getConstant(0, NVT);
5100 } else if (Cst > NVTBits) {
5101 Lo = DAG.getConstant(0, NVT);
5102 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
5103 } else if (Cst == NVTBits) {
5104 Lo = DAG.getConstant(0, NVT);
5107 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
5108 Hi = DAG.getNode(ISD::OR, NVT,
5109 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
5110 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
5115 Lo = DAG.getConstant(0, NVT);
5116 Hi = DAG.getConstant(0, NVT);
5117 } else if (Cst > NVTBits) {
5118 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
5119 Hi = DAG.getConstant(0, NVT);
5120 } else if (Cst == NVTBits) {
5122 Hi = DAG.getConstant(0, NVT);
5124 Lo = DAG.getNode(ISD::OR, NVT,
5125 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5126 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5127 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
5132 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
5133 DAG.getConstant(NVTBits-1, ShTy));
5134 } else if (Cst > NVTBits) {
5135 Lo = DAG.getNode(ISD::SRA, NVT, InH,
5136 DAG.getConstant(Cst-NVTBits, ShTy));
5137 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5138 DAG.getConstant(NVTBits-1, ShTy));
5139 } else if (Cst == NVTBits) {
5141 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5142 DAG.getConstant(NVTBits-1, ShTy));
5144 Lo = DAG.getNode(ISD::OR, NVT,
5145 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5146 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5147 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
5153 // Okay, the shift amount isn't constant. However, if we can tell that it is
5154 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
5155 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
5156 APInt KnownZero, KnownOne;
5157 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
5159 // If we know that if any of the high bits of the shift amount are one, then
5160 // we can do this as a couple of simple shifts.
5161 if (KnownOne.intersects(Mask)) {
5162 // Mask out the high bit, which we know is set.
5163 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
5164 DAG.getConstant(~Mask, Amt.getValueType()));
5166 // Expand the incoming operand to be shifted, so that we have its parts
5168 ExpandOp(Op, InL, InH);
5171 Lo = DAG.getConstant(0, NVT); // Low part is zero.
5172 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
5175 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
5176 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
5179 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
5180 DAG.getConstant(NVTBits-1, Amt.getValueType()));
5181 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
5186 // If we know that the high bits of the shift amount are all zero, then we can
5187 // do this as a couple of simple shifts.
5188 if ((KnownZero & Mask) == Mask) {
5190 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
5191 DAG.getConstant(NVTBits, Amt.getValueType()),
5194 // Expand the incoming operand to be shifted, so that we have its parts
5196 ExpandOp(Op, InL, InH);
5199 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
5200 Hi = DAG.getNode(ISD::OR, NVT,
5201 DAG.getNode(ISD::SHL, NVT, InH, Amt),
5202 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
5205 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
5206 Lo = DAG.getNode(ISD::OR, NVT,
5207 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5208 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5211 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
5212 Lo = DAG.getNode(ISD::OR, NVT,
5213 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5214 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5223 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
5224 // does not fit into a register, return the lo part and set the hi part to the
5225 // by-reg argument. If it does fit into a single register, return the result
5226 // and leave the Hi part unset.
5227 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
5228 bool isSigned, SDOperand &Hi) {
5229 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
5230 // The input chain to this libcall is the entry node of the function.
5231 // Legalizing the call will automatically add the previous call to the
5233 SDOperand InChain = DAG.getEntryNode();
5235 TargetLowering::ArgListTy Args;
5236 TargetLowering::ArgListEntry Entry;
5237 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5238 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
5239 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
5240 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
5241 Entry.isSExt = isSigned;
5242 Entry.isZExt = !isSigned;
5243 Args.push_back(Entry);
5245 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
5247 // Splice the libcall in wherever FindInputOutputChains tells us to.
5248 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
5249 std::pair<SDOperand,SDOperand> CallInfo =
5250 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, CallingConv::C,
5251 false, Callee, Args, DAG);
5253 // Legalize the call sequence, starting with the chain. This will advance
5254 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
5255 // was added by LowerCallTo (guaranteeing proper serialization of calls).
5256 LegalizeOp(CallInfo.second);
5258 switch (getTypeAction(CallInfo.first.getValueType())) {
5259 default: assert(0 && "Unknown thing");
5261 Result = CallInfo.first;
5264 ExpandOp(CallInfo.first, Result, Hi);
5271 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
5273 SDOperand SelectionDAGLegalize::
5274 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
5275 assert(getTypeAction(Source.getValueType()) == Expand &&
5276 "This is not an expansion!");
5277 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
5280 assert(Source.getValueType() == MVT::i64 &&
5281 "This only works for 64-bit -> FP");
5282 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
5283 // incoming integer is set. To handle this, we dynamically test to see if
5284 // it is set, and, if so, add a fudge factor.
5286 ExpandOp(Source, Lo, Hi);
5288 // If this is unsigned, and not supported, first perform the conversion to
5289 // signed, then adjust the result if the sign bit is set.
5290 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
5291 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
5293 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
5294 DAG.getConstant(0, Hi.getValueType()),
5296 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5297 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5298 SignSet, Four, Zero);
5299 uint64_t FF = 0x5f800000ULL;
5300 if (TLI.isLittleEndian()) FF <<= 32;
5301 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5303 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5304 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5305 SDOperand FudgeInReg;
5306 if (DestTy == MVT::f32)
5307 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5308 PseudoSourceValue::getConstantPool(), 0);
5309 else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32))
5310 // FIXME: Avoid the extend by construction the right constantpool?
5311 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
5313 PseudoSourceValue::getConstantPool(), 0,
5316 assert(0 && "Unexpected conversion");
5318 MVT::ValueType SCVT = SignedConv.getValueType();
5319 if (SCVT != DestTy) {
5320 // Destination type needs to be expanded as well. The FADD now we are
5321 // constructing will be expanded into a libcall.
5322 if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) {
5323 assert(SCVT == MVT::i32 && DestTy == MVT::f64);
5324 SignedConv = DAG.getNode(ISD::BUILD_PAIR, MVT::i64,
5325 SignedConv, SignedConv.getValue(1));
5327 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
5329 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
5332 // Check to see if the target has a custom way to lower this. If so, use it.
5333 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
5334 default: assert(0 && "This action not implemented for this operation!");
5335 case TargetLowering::Legal:
5336 case TargetLowering::Expand:
5337 break; // This case is handled below.
5338 case TargetLowering::Custom: {
5339 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
5342 return LegalizeOp(NV);
5343 break; // The target decided this was legal after all
5347 // Expand the source, then glue it back together for the call. We must expand
5348 // the source in case it is shared (this pass of legalize must traverse it).
5349 SDOperand SrcLo, SrcHi;
5350 ExpandOp(Source, SrcLo, SrcHi);
5351 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
5354 if (DestTy == MVT::f32)
5355 LC = RTLIB::SINTTOFP_I64_F32;
5357 assert(DestTy == MVT::f64 && "Unknown fp value type!");
5358 LC = RTLIB::SINTTOFP_I64_F64;
5361 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!");
5362 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
5363 SDOperand UnusedHiPart;
5364 return ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned,
5368 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
5369 /// INT_TO_FP operation of the specified operand when the target requests that
5370 /// we expand it. At this point, we know that the result and operand types are
5371 /// legal for the target.
5372 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
5374 MVT::ValueType DestVT) {
5375 if (Op0.getValueType() == MVT::i32) {
5376 // simple 32-bit [signed|unsigned] integer to float/double expansion
5378 // Get the stack frame index of a 8 byte buffer.
5379 SDOperand StackSlot = DAG.CreateStackTemporary(MVT::f64);
5381 // word offset constant for Hi/Lo address computation
5382 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
5383 // set up Hi and Lo (into buffer) address based on endian
5384 SDOperand Hi = StackSlot;
5385 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
5386 if (TLI.isLittleEndian())
5389 // if signed map to unsigned space
5390 SDOperand Op0Mapped;
5392 // constant used to invert sign bit (signed to unsigned mapping)
5393 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
5394 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
5398 // store the lo of the constructed double - based on integer input
5399 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(),
5400 Op0Mapped, Lo, NULL, 0);
5401 // initial hi portion of constructed double
5402 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
5403 // store the hi of the constructed double - biased exponent
5404 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
5405 // load the constructed double
5406 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
5407 // FP constant to bias correct the final result
5408 SDOperand Bias = DAG.getConstantFP(isSigned ?
5409 BitsToDouble(0x4330000080000000ULL)
5410 : BitsToDouble(0x4330000000000000ULL),
5412 // subtract the bias
5413 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
5416 // handle final rounding
5417 if (DestVT == MVT::f64) {
5420 } else if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(MVT::f64)) {
5421 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub,
5422 DAG.getIntPtrConstant(0));
5423 } else if (MVT::getSizeInBits(DestVT) > MVT::getSizeInBits(MVT::f64)) {
5424 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
5428 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
5429 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
5431 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
5432 DAG.getConstant(0, Op0.getValueType()),
5434 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5435 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5436 SignSet, Four, Zero);
5438 // If the sign bit of the integer is set, the large number will be treated
5439 // as a negative number. To counteract this, the dynamic code adds an
5440 // offset depending on the data type.
5442 switch (Op0.getValueType()) {
5443 default: assert(0 && "Unsupported integer type!");
5444 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
5445 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
5446 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
5447 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
5449 if (TLI.isLittleEndian()) FF <<= 32;
5450 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5452 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5453 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5454 SDOperand FudgeInReg;
5455 if (DestVT == MVT::f32)
5456 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5457 PseudoSourceValue::getConstantPool(), 0);
5460 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT,
5461 DAG.getEntryNode(), CPIdx,
5462 PseudoSourceValue::getConstantPool(), 0,
5466 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
5469 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
5470 /// *INT_TO_FP operation of the specified operand when the target requests that
5471 /// we promote it. At this point, we know that the result and operand types are
5472 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
5473 /// operation that takes a larger input.
5474 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
5475 MVT::ValueType DestVT,
5477 // First step, figure out the appropriate *INT_TO_FP operation to use.
5478 MVT::ValueType NewInTy = LegalOp.getValueType();
5480 unsigned OpToUse = 0;
5482 // Scan for the appropriate larger type to use.
5484 NewInTy = (MVT::ValueType)(NewInTy+1);
5485 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
5487 // If the target supports SINT_TO_FP of this type, use it.
5488 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
5490 case TargetLowering::Legal:
5491 if (!TLI.isTypeLegal(NewInTy))
5492 break; // Can't use this datatype.
5494 case TargetLowering::Custom:
5495 OpToUse = ISD::SINT_TO_FP;
5499 if (isSigned) continue;
5501 // If the target supports UINT_TO_FP of this type, use it.
5502 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
5504 case TargetLowering::Legal:
5505 if (!TLI.isTypeLegal(NewInTy))
5506 break; // Can't use this datatype.
5508 case TargetLowering::Custom:
5509 OpToUse = ISD::UINT_TO_FP;
5514 // Otherwise, try a larger type.
5517 // Okay, we found the operation and type to use. Zero extend our input to the
5518 // desired type then run the operation on it.
5519 return DAG.getNode(OpToUse, DestVT,
5520 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
5524 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
5525 /// FP_TO_*INT operation of the specified operand when the target requests that
5526 /// we promote it. At this point, we know that the result and operand types are
5527 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
5528 /// operation that returns a larger result.
5529 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
5530 MVT::ValueType DestVT,
5532 // First step, figure out the appropriate FP_TO*INT operation to use.
5533 MVT::ValueType NewOutTy = DestVT;
5535 unsigned OpToUse = 0;
5537 // Scan for the appropriate larger type to use.
5539 NewOutTy = (MVT::ValueType)(NewOutTy+1);
5540 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
5542 // If the target supports FP_TO_SINT returning this type, use it.
5543 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
5545 case TargetLowering::Legal:
5546 if (!TLI.isTypeLegal(NewOutTy))
5547 break; // Can't use this datatype.
5549 case TargetLowering::Custom:
5550 OpToUse = ISD::FP_TO_SINT;
5555 // If the target supports FP_TO_UINT of this type, use it.
5556 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
5558 case TargetLowering::Legal:
5559 if (!TLI.isTypeLegal(NewOutTy))
5560 break; // Can't use this datatype.
5562 case TargetLowering::Custom:
5563 OpToUse = ISD::FP_TO_UINT;
5568 // Otherwise, try a larger type.
5572 // Okay, we found the operation and type to use.
5573 SDOperand Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp);
5575 // If the operation produces an invalid type, it must be custom lowered. Use
5576 // the target lowering hooks to expand it. Just keep the low part of the
5577 // expanded operation, we know that we're truncating anyway.
5578 if (getTypeAction(NewOutTy) == Expand) {
5579 Operation = SDOperand(TLI.ExpandOperationResult(Operation.Val, DAG), 0);
5580 assert(Operation.Val && "Didn't return anything");
5583 // Truncate the result of the extended FP_TO_*INT operation to the desired
5585 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation);
5588 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
5590 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
5591 MVT::ValueType VT = Op.getValueType();
5592 MVT::ValueType SHVT = TLI.getShiftAmountTy();
5593 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
5595 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
5597 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5598 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5599 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
5601 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5602 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5603 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5604 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5605 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
5606 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
5607 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5608 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5609 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5611 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
5612 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
5613 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5614 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5615 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5616 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5617 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
5618 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
5619 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
5620 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
5621 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
5622 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
5623 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
5624 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
5625 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
5626 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
5627 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5628 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5629 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
5630 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5631 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
5635 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
5637 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
5639 default: assert(0 && "Cannot expand this yet!");
5641 static const uint64_t mask[6] = {
5642 0x5555555555555555ULL, 0x3333333333333333ULL,
5643 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
5644 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
5646 MVT::ValueType VT = Op.getValueType();
5647 MVT::ValueType ShVT = TLI.getShiftAmountTy();
5648 unsigned len = MVT::getSizeInBits(VT);
5649 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5650 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
5651 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
5652 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5653 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
5654 DAG.getNode(ISD::AND, VT,
5655 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
5660 // for now, we do this:
5661 // x = x | (x >> 1);
5662 // x = x | (x >> 2);
5664 // x = x | (x >>16);
5665 // x = x | (x >>32); // for 64-bit input
5666 // return popcount(~x);
5668 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
5669 MVT::ValueType VT = Op.getValueType();
5670 MVT::ValueType ShVT = TLI.getShiftAmountTy();
5671 unsigned len = MVT::getSizeInBits(VT);
5672 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5673 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5674 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
5676 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
5677 return DAG.getNode(ISD::CTPOP, VT, Op);
5680 // for now, we use: { return popcount(~x & (x - 1)); }
5681 // unless the target has ctlz but not ctpop, in which case we use:
5682 // { return 32 - nlz(~x & (x-1)); }
5683 // see also http://www.hackersdelight.org/HDcode/ntz.cc
5684 MVT::ValueType VT = Op.getValueType();
5685 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
5686 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
5687 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
5688 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
5689 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
5690 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
5691 TLI.isOperationLegal(ISD::CTLZ, VT))
5692 return DAG.getNode(ISD::SUB, VT,
5693 DAG.getConstant(MVT::getSizeInBits(VT), VT),
5694 DAG.getNode(ISD::CTLZ, VT, Tmp3));
5695 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
5700 /// ExpandOp - Expand the specified SDOperand into its two component pieces
5701 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
5702 /// LegalizeNodes map is filled in for any results that are not expanded, the
5703 /// ExpandedNodes map is filled in for any results that are expanded, and the
5704 /// Lo/Hi values are returned.
5705 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
5706 MVT::ValueType VT = Op.getValueType();
5707 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
5708 SDNode *Node = Op.Val;
5709 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
5710 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) ||
5711 MVT::isVector(VT)) &&
5712 "Cannot expand to FP value or to larger int value!");
5714 // See if we already expanded it.
5715 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
5716 = ExpandedNodes.find(Op);
5717 if (I != ExpandedNodes.end()) {
5718 Lo = I->second.first;
5719 Hi = I->second.second;
5723 switch (Node->getOpcode()) {
5724 case ISD::CopyFromReg:
5725 assert(0 && "CopyFromReg must be legal!");
5726 case ISD::FP_ROUND_INREG:
5727 if (VT == MVT::ppcf128 &&
5728 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
5729 TargetLowering::Custom) {
5730 SDOperand SrcLo, SrcHi, Src;
5731 ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
5732 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi);
5733 SDOperand Result = TLI.LowerOperation(
5734 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG);
5735 assert(Result.Val->getOpcode() == ISD::BUILD_PAIR);
5736 Lo = Result.Val->getOperand(0);
5737 Hi = Result.Val->getOperand(1);
5743 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
5745 assert(0 && "Do not know how to expand this operator!");
5747 case ISD::EXTRACT_ELEMENT:
5748 ExpandOp(Node->getOperand(0), Lo, Hi);
5749 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
5750 return ExpandOp(Hi, Lo, Hi);
5751 return ExpandOp(Lo, Lo, Hi);
5752 case ISD::EXTRACT_VECTOR_ELT:
5753 assert(VT==MVT::i64 && "Do not know how to expand this operator!");
5754 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types.
5755 Lo = ExpandEXTRACT_VECTOR_ELT(Op);
5756 return ExpandOp(Lo, Lo, Hi);
5758 NVT = TLI.getTypeToExpandTo(VT);
5759 Lo = DAG.getNode(ISD::UNDEF, NVT);
5760 Hi = DAG.getNode(ISD::UNDEF, NVT);
5762 case ISD::Constant: {
5763 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
5764 Lo = DAG.getConstant(Cst, NVT);
5765 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
5768 case ISD::ConstantFP: {
5769 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
5770 if (CFP->getValueType(0) == MVT::ppcf128) {
5771 APInt api = CFP->getValueAPF().convertToAPInt();
5772 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
5774 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
5778 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
5779 if (getTypeAction(Lo.getValueType()) == Expand)
5780 ExpandOp(Lo, Lo, Hi);
5783 case ISD::BUILD_PAIR:
5784 // Return the operands.
5785 Lo = Node->getOperand(0);
5786 Hi = Node->getOperand(1);
5789 case ISD::MERGE_VALUES:
5790 if (Node->getNumValues() == 1) {
5791 ExpandOp(Op.getOperand(0), Lo, Hi);
5794 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y)
5795 assert(Op.ResNo == 0 && Node->getNumValues() == 2 &&
5796 Op.getValue(1).getValueType() == MVT::Other &&
5797 "unhandled MERGE_VALUES");
5798 ExpandOp(Op.getOperand(0), Lo, Hi);
5799 // Remember that we legalized the chain.
5800 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1)));
5803 case ISD::SIGN_EXTEND_INREG:
5804 ExpandOp(Node->getOperand(0), Lo, Hi);
5805 // sext_inreg the low part if needed.
5806 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
5808 // The high part gets the sign extension from the lo-part. This handles
5809 // things like sextinreg V:i64 from i8.
5810 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5811 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
5812 TLI.getShiftAmountTy()));
5816 ExpandOp(Node->getOperand(0), Lo, Hi);
5817 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
5818 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
5824 ExpandOp(Node->getOperand(0), Lo, Hi);
5825 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
5826 DAG.getNode(ISD::CTPOP, NVT, Lo),
5827 DAG.getNode(ISD::CTPOP, NVT, Hi));
5828 Hi = DAG.getConstant(0, NVT);
5832 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
5833 ExpandOp(Node->getOperand(0), Lo, Hi);
5834 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5835 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
5836 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
5838 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
5839 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
5841 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
5842 Hi = DAG.getConstant(0, NVT);
5847 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
5848 ExpandOp(Node->getOperand(0), Lo, Hi);
5849 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5850 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
5851 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
5853 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
5854 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
5856 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
5857 Hi = DAG.getConstant(0, NVT);
5862 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
5863 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
5864 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
5865 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
5867 // Remember that we legalized the chain.
5868 Hi = LegalizeOp(Hi);
5869 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
5870 if (TLI.isBigEndian())
5876 LoadSDNode *LD = cast<LoadSDNode>(Node);
5877 SDOperand Ch = LD->getChain(); // Legalize the chain.
5878 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer.
5879 ISD::LoadExtType ExtType = LD->getExtensionType();
5880 int SVOffset = LD->getSrcValueOffset();
5881 unsigned Alignment = LD->getAlignment();
5882 bool isVolatile = LD->isVolatile();
5884 if (ExtType == ISD::NON_EXTLOAD) {
5885 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5886 isVolatile, Alignment);
5887 if (VT == MVT::f32 || VT == MVT::f64) {
5888 // f32->i32 or f64->i64 one to one expansion.
5889 // Remember that we legalized the chain.
5890 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5891 // Recursively expand the new load.
5892 if (getTypeAction(NVT) == Expand)
5893 ExpandOp(Lo, Lo, Hi);
5897 // Increment the pointer to the other half.
5898 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
5899 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
5900 DAG.getIntPtrConstant(IncrementSize));
5901 SVOffset += IncrementSize;
5902 Alignment = MinAlign(Alignment, IncrementSize);
5903 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5904 isVolatile, Alignment);
5906 // Build a factor node to remember that this load is independent of the
5908 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
5911 // Remember that we legalized the chain.
5912 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
5913 if (TLI.isBigEndian())
5916 MVT::ValueType EVT = LD->getMemoryVT();
5918 if ((VT == MVT::f64 && EVT == MVT::f32) ||
5919 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
5920 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
5921 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(),
5922 SVOffset, isVolatile, Alignment);
5923 // Remember that we legalized the chain.
5924 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1)));
5925 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
5930 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),
5931 SVOffset, isVolatile, Alignment);
5933 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(),
5934 SVOffset, EVT, isVolatile,
5937 // Remember that we legalized the chain.
5938 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5940 if (ExtType == ISD::SEXTLOAD) {
5941 // The high part is obtained by SRA'ing all but one of the bits of the
5943 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
5944 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5945 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5946 } else if (ExtType == ISD::ZEXTLOAD) {
5947 // The high part is just a zero.
5948 Hi = DAG.getConstant(0, NVT);
5949 } else /* if (ExtType == ISD::EXTLOAD) */ {
5950 // The high part is undefined.
5951 Hi = DAG.getNode(ISD::UNDEF, NVT);
5958 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
5959 SDOperand LL, LH, RL, RH;
5960 ExpandOp(Node->getOperand(0), LL, LH);
5961 ExpandOp(Node->getOperand(1), RL, RH);
5962 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
5963 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
5967 SDOperand LL, LH, RL, RH;
5968 ExpandOp(Node->getOperand(1), LL, LH);
5969 ExpandOp(Node->getOperand(2), RL, RH);
5970 if (getTypeAction(NVT) == Expand)
5971 NVT = TLI.getTypeToExpandTo(NVT);
5972 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
5974 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
5977 case ISD::SELECT_CC: {
5978 SDOperand TL, TH, FL, FH;
5979 ExpandOp(Node->getOperand(2), TL, TH);
5980 ExpandOp(Node->getOperand(3), FL, FH);
5981 if (getTypeAction(NVT) == Expand)
5982 NVT = TLI.getTypeToExpandTo(NVT);
5983 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
5984 Node->getOperand(1), TL, FL, Node->getOperand(4));
5986 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
5987 Node->getOperand(1), TH, FH, Node->getOperand(4));
5990 case ISD::ANY_EXTEND:
5991 // The low part is any extension of the input (which degenerates to a copy).
5992 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
5993 // The high part is undefined.
5994 Hi = DAG.getNode(ISD::UNDEF, NVT);
5996 case ISD::SIGN_EXTEND: {
5997 // The low part is just a sign extension of the input (which degenerates to
5999 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
6001 // The high part is obtained by SRA'ing all but one of the bits of the lo
6003 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
6004 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6005 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6008 case ISD::ZERO_EXTEND:
6009 // The low part is just a zero extension of the input (which degenerates to
6011 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
6013 // The high part is just a zero.
6014 Hi = DAG.getConstant(0, NVT);
6017 case ISD::TRUNCATE: {
6018 // The input value must be larger than this value. Expand *it*.
6020 ExpandOp(Node->getOperand(0), NewLo, Hi);
6022 // The low part is now either the right size, or it is closer. If not the
6023 // right size, make an illegal truncate so we recursively expand it.
6024 if (NewLo.getValueType() != Node->getValueType(0))
6025 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
6026 ExpandOp(NewLo, Lo, Hi);
6030 case ISD::BIT_CONVERT: {
6032 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
6033 // If the target wants to, allow it to lower this itself.
6034 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6035 case Expand: assert(0 && "cannot expand FP!");
6036 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
6037 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
6039 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
6042 // f32 / f64 must be expanded to i32 / i64.
6043 if (VT == MVT::f32 || VT == MVT::f64) {
6044 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6045 if (getTypeAction(NVT) == Expand)
6046 ExpandOp(Lo, Lo, Hi);
6050 // If source operand will be expanded to the same type as VT, i.e.
6051 // i64 <- f64, i32 <- f32, expand the source operand instead.
6052 MVT::ValueType VT0 = Node->getOperand(0).getValueType();
6053 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
6054 ExpandOp(Node->getOperand(0), Lo, Hi);
6058 // Turn this into a load/store pair by default.
6060 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT);
6062 ExpandOp(Tmp, Lo, Hi);
6066 case ISD::READCYCLECOUNTER: {
6067 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
6068 TargetLowering::Custom &&
6069 "Must custom expand ReadCycleCounter");
6070 SDOperand Tmp = TLI.LowerOperation(Op, DAG);
6071 assert(Tmp.Val && "Node must be custom expanded!");
6072 ExpandOp(Tmp.getValue(0), Lo, Hi);
6073 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
6074 LegalizeOp(Tmp.getValue(1)));
6078 // These operators cannot be expanded directly, emit them as calls to
6079 // library functions.
6080 case ISD::FP_TO_SINT: {
6081 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
6083 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6084 case Expand: assert(0 && "cannot expand FP!");
6085 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6086 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6089 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
6091 // Now that the custom expander is done, expand the result, which is still
6094 ExpandOp(Op, Lo, Hi);
6099 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6100 if (Node->getOperand(0).getValueType() == MVT::f32)
6101 LC = RTLIB::FPTOSINT_F32_I64;
6102 else if (Node->getOperand(0).getValueType() == MVT::f64)
6103 LC = RTLIB::FPTOSINT_F64_I64;
6104 else if (Node->getOperand(0).getValueType() == MVT::f80)
6105 LC = RTLIB::FPTOSINT_F80_I64;
6106 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
6107 LC = RTLIB::FPTOSINT_PPCF128_I64;
6108 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
6109 false/*sign irrelevant*/, Hi);
6113 case ISD::FP_TO_UINT: {
6114 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
6116 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6117 case Expand: assert(0 && "cannot expand FP!");
6118 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6119 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6122 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
6124 // Now that the custom expander is done, expand the result.
6126 ExpandOp(Op, Lo, Hi);
6131 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6132 if (Node->getOperand(0).getValueType() == MVT::f32)
6133 LC = RTLIB::FPTOUINT_F32_I64;
6134 else if (Node->getOperand(0).getValueType() == MVT::f64)
6135 LC = RTLIB::FPTOUINT_F64_I64;
6136 else if (Node->getOperand(0).getValueType() == MVT::f80)
6137 LC = RTLIB::FPTOUINT_F80_I64;
6138 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
6139 LC = RTLIB::FPTOUINT_PPCF128_I64;
6140 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
6141 false/*sign irrelevant*/, Hi);
6146 // If the target wants custom lowering, do so.
6147 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6148 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
6149 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
6150 Op = TLI.LowerOperation(Op, DAG);
6152 // Now that the custom expander is done, expand the result, which is
6154 ExpandOp(Op, Lo, Hi);
6159 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
6160 // this X << 1 as X+X.
6161 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
6162 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
6163 TLI.isOperationLegal(ISD::ADDE, NVT)) {
6164 SDOperand LoOps[2], HiOps[3];
6165 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
6166 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
6167 LoOps[1] = LoOps[0];
6168 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6170 HiOps[1] = HiOps[0];
6171 HiOps[2] = Lo.getValue(1);
6172 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6177 // If we can emit an efficient shift operation, do so now.
6178 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6181 // If this target supports SHL_PARTS, use it.
6182 TargetLowering::LegalizeAction Action =
6183 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
6184 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6185 Action == TargetLowering::Custom) {
6186 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6190 // Otherwise, emit a libcall.
6191 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SHL_I64), Node,
6192 false/*left shift=unsigned*/, Hi);
6197 // If the target wants custom lowering, do so.
6198 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6199 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
6200 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
6201 Op = TLI.LowerOperation(Op, DAG);
6203 // Now that the custom expander is done, expand the result, which is
6205 ExpandOp(Op, Lo, Hi);
6210 // If we can emit an efficient shift operation, do so now.
6211 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
6214 // If this target supports SRA_PARTS, use it.
6215 TargetLowering::LegalizeAction Action =
6216 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
6217 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6218 Action == TargetLowering::Custom) {
6219 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6223 // Otherwise, emit a libcall.
6224 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRA_I64), Node,
6225 true/*ashr is signed*/, Hi);
6230 // If the target wants custom lowering, do so.
6231 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6232 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
6233 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
6234 Op = TLI.LowerOperation(Op, DAG);
6236 // Now that the custom expander is done, expand the result, which is
6238 ExpandOp(Op, Lo, Hi);
6243 // If we can emit an efficient shift operation, do so now.
6244 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6247 // If this target supports SRL_PARTS, use it.
6248 TargetLowering::LegalizeAction Action =
6249 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
6250 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6251 Action == TargetLowering::Custom) {
6252 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6256 // Otherwise, emit a libcall.
6257 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), Node,
6258 false/*lshr is unsigned*/, Hi);
6264 // If the target wants to custom expand this, let them.
6265 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
6266 TargetLowering::Custom) {
6267 Op = TLI.LowerOperation(Op, DAG);
6269 ExpandOp(Op, Lo, Hi);
6274 // Expand the subcomponents.
6275 SDOperand LHSL, LHSH, RHSL, RHSH;
6276 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6277 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6278 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6279 SDOperand LoOps[2], HiOps[3];
6284 if (Node->getOpcode() == ISD::ADD) {
6285 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6286 HiOps[2] = Lo.getValue(1);
6287 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6289 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6290 HiOps[2] = Lo.getValue(1);
6291 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6298 // Expand the subcomponents.
6299 SDOperand LHSL, LHSH, RHSL, RHSH;
6300 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6301 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6302 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6303 SDOperand LoOps[2] = { LHSL, RHSL };
6304 SDOperand HiOps[3] = { LHSH, RHSH };
6306 if (Node->getOpcode() == ISD::ADDC) {
6307 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6308 HiOps[2] = Lo.getValue(1);
6309 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6311 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6312 HiOps[2] = Lo.getValue(1);
6313 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6315 // Remember that we legalized the flag.
6316 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6321 // Expand the subcomponents.
6322 SDOperand LHSL, LHSH, RHSL, RHSH;
6323 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6324 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6325 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6326 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
6327 SDOperand HiOps[3] = { LHSH, RHSH };
6329 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
6330 HiOps[2] = Lo.getValue(1);
6331 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
6333 // Remember that we legalized the flag.
6334 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6338 // If the target wants to custom expand this, let them.
6339 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
6340 SDOperand New = TLI.LowerOperation(Op, DAG);
6342 ExpandOp(New, Lo, Hi);
6347 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
6348 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
6349 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
6350 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
6351 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
6352 SDOperand LL, LH, RL, RH;
6353 ExpandOp(Node->getOperand(0), LL, LH);
6354 ExpandOp(Node->getOperand(1), RL, RH);
6355 unsigned OuterBitSize = Op.getValueSizeInBits();
6356 unsigned InnerBitSize = RH.getValueSizeInBits();
6357 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
6358 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
6359 if (DAG.MaskedValueIsZero(Op.getOperand(0),
6360 APInt::getHighBitsSet(OuterBitSize, LHSSB)) &&
6361 DAG.MaskedValueIsZero(Op.getOperand(1),
6362 APInt::getHighBitsSet(OuterBitSize, RHSSB))) {
6363 // The inputs are both zero-extended.
6365 // We can emit a umul_lohi.
6366 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6367 Hi = SDOperand(Lo.Val, 1);
6371 // We can emit a mulhu+mul.
6372 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6373 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6377 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
6378 // The input values are both sign-extended.
6380 // We can emit a smul_lohi.
6381 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6382 Hi = SDOperand(Lo.Val, 1);
6386 // We can emit a mulhs+mul.
6387 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6388 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
6393 // Lo,Hi = umul LHS, RHS.
6394 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
6395 DAG.getVTList(NVT, NVT), LL, RL);
6397 Hi = UMulLOHI.getValue(1);
6398 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6399 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6400 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6401 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6405 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6406 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6407 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6408 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6409 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6410 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6415 // If nothing else, we can make a libcall.
6416 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), Node,
6417 false/*sign irrelevant*/, Hi);
6421 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SDIV_I64), Node, true, Hi);
6424 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UDIV_I64), Node, true, Hi);
6427 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SREM_I64), Node, true, Hi);
6430 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UREM_I64), Node, true, Hi);
6434 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::ADD_F32,
6437 RTLIB::ADD_PPCF128)),
6441 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::SUB_F32,
6444 RTLIB::SUB_PPCF128)),
6448 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::MUL_F32,
6451 RTLIB::MUL_PPCF128)),
6455 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::DIV_F32,
6458 RTLIB::DIV_PPCF128)),
6461 case ISD::FP_EXTEND:
6462 if (VT == MVT::ppcf128) {
6463 assert(Node->getOperand(0).getValueType()==MVT::f32 ||
6464 Node->getOperand(0).getValueType()==MVT::f64);
6465 const uint64_t zero = 0;
6466 if (Node->getOperand(0).getValueType()==MVT::f32)
6467 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0));
6469 Hi = Node->getOperand(0);
6470 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6473 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPEXT_F32_F64), Node, true,Hi);
6476 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi);
6479 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::POWI_F32,
6482 RTLIB::POWI_PPCF128)),
6488 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6489 switch(Node->getOpcode()) {
6491 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
6492 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
6495 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
6496 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
6499 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
6500 RTLIB::COS_F80, RTLIB::COS_PPCF128);
6502 default: assert(0 && "Unreachable!");
6504 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false, Hi);
6508 if (VT == MVT::ppcf128) {
6510 ExpandOp(Node->getOperand(0), Lo, Tmp);
6511 Hi = DAG.getNode(ISD::FABS, NVT, Tmp);
6512 // lo = hi==fabs(hi) ? lo : -lo;
6513 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp,
6514 Lo, DAG.getNode(ISD::FNEG, NVT, Lo),
6515 DAG.getCondCode(ISD::SETEQ));
6518 SDOperand Mask = (VT == MVT::f64)
6519 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
6520 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
6521 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6522 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6523 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
6524 if (getTypeAction(NVT) == Expand)
6525 ExpandOp(Lo, Lo, Hi);
6529 if (VT == MVT::ppcf128) {
6530 ExpandOp(Node->getOperand(0), Lo, Hi);
6531 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo);
6532 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi);
6535 SDOperand Mask = (VT == MVT::f64)
6536 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
6537 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
6538 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6539 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6540 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
6541 if (getTypeAction(NVT) == Expand)
6542 ExpandOp(Lo, Lo, Hi);
6545 case ISD::FCOPYSIGN: {
6546 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
6547 if (getTypeAction(NVT) == Expand)
6548 ExpandOp(Lo, Lo, Hi);
6551 case ISD::SINT_TO_FP:
6552 case ISD::UINT_TO_FP: {
6553 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
6554 MVT::ValueType SrcVT = Node->getOperand(0).getValueType();
6555 if (VT == MVT::ppcf128 && SrcVT != MVT::i64) {
6556 static const uint64_t zero = 0;
6558 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6559 Node->getOperand(0)));
6560 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6562 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
6563 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6564 Node->getOperand(0)));
6565 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6566 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6567 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
6568 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6569 DAG.getConstant(0, MVT::i32),
6570 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6572 APFloat(APInt(128, 2, TwoE32)),
6575 DAG.getCondCode(ISD::SETLT)),
6580 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) {
6581 // si64->ppcf128 done by libcall, below
6582 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
6583 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)),
6585 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6586 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
6587 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6588 DAG.getConstant(0, MVT::i64),
6589 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6591 APFloat(APInt(128, 2, TwoE64)),
6594 DAG.getCondCode(ISD::SETLT)),
6598 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6599 if (Node->getOperand(0).getValueType() == MVT::i64) {
6601 LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32;
6602 else if (VT == MVT::f64)
6603 LC = isSigned ? RTLIB::SINTTOFP_I64_F64 : RTLIB::UINTTOFP_I64_F64;
6604 else if (VT == MVT::f80) {
6606 LC = RTLIB::SINTTOFP_I64_F80;
6608 else if (VT == MVT::ppcf128) {
6610 LC = RTLIB::SINTTOFP_I64_PPCF128;
6614 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32;
6616 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64;
6619 // Promote the operand if needed.
6620 if (getTypeAction(SrcVT) == Promote) {
6621 SDOperand Tmp = PromoteOp(Node->getOperand(0));
6623 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
6624 DAG.getValueType(SrcVT))
6625 : DAG.getZeroExtendInReg(Tmp, SrcVT);
6626 Node = DAG.UpdateNodeOperands(Op, Tmp).Val;
6629 const char *LibCall = TLI.getLibcallName(LC);
6631 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Hi);
6633 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
6634 Node->getOperand(0));
6635 if (getTypeAction(Lo.getValueType()) == Expand)
6636 ExpandOp(Lo, Lo, Hi);
6642 // Make sure the resultant values have been legalized themselves, unless this
6643 // is a type that requires multi-step expansion.
6644 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
6645 Lo = LegalizeOp(Lo);
6647 // Don't legalize the high part if it is expanded to a single node.
6648 Hi = LegalizeOp(Hi);
6651 // Remember in a map if the values will be reused later.
6652 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi)));
6653 assert(isNew && "Value already expanded?!?");
6656 /// SplitVectorOp - Given an operand of vector type, break it down into
6657 /// two smaller values, still of vector type.
6658 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
6660 assert(MVT::isVector(Op.getValueType()) && "Cannot split non-vector type!");
6661 SDNode *Node = Op.Val;
6662 unsigned NumElements = MVT::getVectorNumElements(Op.getValueType());
6663 assert(NumElements > 1 && "Cannot split a single element vector!");
6665 MVT::ValueType NewEltVT = MVT::getVectorElementType(Op.getValueType());
6667 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
6668 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
6670 MVT::ValueType NewVT_Lo = MVT::getVectorType(NewEltVT, NewNumElts_Lo);
6671 MVT::ValueType NewVT_Hi = MVT::getVectorType(NewEltVT, NewNumElts_Hi);
6673 // See if we already split it.
6674 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
6675 = SplitNodes.find(Op);
6676 if (I != SplitNodes.end()) {
6677 Lo = I->second.first;
6678 Hi = I->second.second;
6682 switch (Node->getOpcode()) {
6687 assert(0 && "Unhandled operation in SplitVectorOp!");
6689 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo);
6690 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi);
6692 case ISD::BUILD_PAIR:
6693 Lo = Node->getOperand(0);
6694 Hi = Node->getOperand(1);
6696 case ISD::INSERT_VECTOR_ELT: {
6697 SplitVectorOp(Node->getOperand(0), Lo, Hi);
6698 unsigned Index = cast<ConstantSDNode>(Node->getOperand(2))->getValue();
6699 SDOperand ScalarOp = Node->getOperand(1);
6700 if (Index < NewNumElts_Lo)
6701 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp,
6702 DAG.getConstant(Index, TLI.getPointerTy()));
6704 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp,
6705 DAG.getConstant(Index - NewNumElts_Lo,
6706 TLI.getPointerTy()));
6709 case ISD::VECTOR_SHUFFLE: {
6710 // Build the low part.
6711 SDOperand Mask = Node->getOperand(2);
6712 SmallVector<SDOperand, 8> Ops;
6713 MVT::ValueType PtrVT = TLI.getPointerTy();
6715 // Insert all of the elements from the input that are needed. We use
6716 // buildvector of extractelement here because the input vectors will have
6717 // to be legalized, so this makes the code simpler.
6718 for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
6719 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
6720 SDOperand InVec = Node->getOperand(0);
6721 if (Idx >= NumElements) {
6722 InVec = Node->getOperand(1);
6725 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6726 DAG.getConstant(Idx, PtrVT)));
6728 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6731 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
6732 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
6733 SDOperand InVec = Node->getOperand(0);
6734 if (Idx >= NumElements) {
6735 InVec = Node->getOperand(1);
6738 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6739 DAG.getConstant(Idx, PtrVT)));
6741 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6744 case ISD::BUILD_VECTOR: {
6745 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
6746 Node->op_begin()+NewNumElts_Lo);
6747 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size());
6749 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
6751 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size());
6754 case ISD::CONCAT_VECTORS: {
6755 // FIXME: Handle non-power-of-two vectors?
6756 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
6757 if (NewNumSubvectors == 1) {
6758 Lo = Node->getOperand(0);
6759 Hi = Node->getOperand(1);
6761 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
6762 Node->op_begin()+NewNumSubvectors);
6763 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size());
6765 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors,
6767 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size());
6772 SDOperand Cond = Node->getOperand(0);
6774 SDOperand LL, LH, RL, RH;
6775 SplitVectorOp(Node->getOperand(1), LL, LH);
6776 SplitVectorOp(Node->getOperand(2), RL, RH);
6778 if (MVT::isVector(Cond.getValueType())) {
6779 // Handle a vector merge.
6781 SplitVectorOp(Cond, CL, CH);
6782 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL);
6783 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH);
6785 // Handle a simple select with vector operands.
6786 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL);
6787 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH);
6807 SDOperand LL, LH, RL, RH;
6808 SplitVectorOp(Node->getOperand(0), LL, LH);
6809 SplitVectorOp(Node->getOperand(1), RL, RH);
6811 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL);
6812 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH);
6817 SplitVectorOp(Node->getOperand(0), L, H);
6819 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1));
6820 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1));
6831 case ISD::FP_TO_SINT:
6832 case ISD::FP_TO_UINT:
6833 case ISD::SINT_TO_FP:
6834 case ISD::UINT_TO_FP: {
6836 SplitVectorOp(Node->getOperand(0), L, H);
6838 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L);
6839 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H);
6843 LoadSDNode *LD = cast<LoadSDNode>(Node);
6844 SDOperand Ch = LD->getChain();
6845 SDOperand Ptr = LD->getBasePtr();
6846 const Value *SV = LD->getSrcValue();
6847 int SVOffset = LD->getSrcValueOffset();
6848 unsigned Alignment = LD->getAlignment();
6849 bool isVolatile = LD->isVolatile();
6851 Lo = DAG.getLoad(NewVT_Lo, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
6852 unsigned IncrementSize = NewNumElts_Lo * MVT::getSizeInBits(NewEltVT)/8;
6853 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
6854 DAG.getIntPtrConstant(IncrementSize));
6855 SVOffset += IncrementSize;
6856 Alignment = MinAlign(Alignment, IncrementSize);
6857 Hi = DAG.getLoad(NewVT_Hi, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
6859 // Build a factor node to remember that this load is independent of the
6861 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
6864 // Remember that we legalized the chain.
6865 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
6868 case ISD::BIT_CONVERT: {
6869 // We know the result is a vector. The input may be either a vector or a
6871 SDOperand InOp = Node->getOperand(0);
6872 if (!MVT::isVector(InOp.getValueType()) ||
6873 MVT::getVectorNumElements(InOp.getValueType()) == 1) {
6874 // The input is a scalar or single-element vector.
6875 // Lower to a store/load so that it can be split.
6876 // FIXME: this could be improved probably.
6877 SDOperand Ptr = DAG.CreateStackTemporary(InOp.getValueType());
6878 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(Ptr.Val);
6880 SDOperand St = DAG.getStore(DAG.getEntryNode(),
6882 PseudoSourceValue::getFixedStack(),
6884 InOp = DAG.getLoad(Op.getValueType(), St, Ptr,
6885 PseudoSourceValue::getFixedStack(),
6888 // Split the vector and convert each of the pieces now.
6889 SplitVectorOp(InOp, Lo, Hi);
6890 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo);
6891 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi);
6896 // Remember in a map if the values will be reused later.
6898 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
6899 assert(isNew && "Value already split?!?");
6903 /// ScalarizeVectorOp - Given an operand of single-element vector type
6904 /// (e.g. v1f32), convert it into the equivalent operation that returns a
6905 /// scalar (e.g. f32) value.
6906 SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) {
6907 assert(MVT::isVector(Op.getValueType()) &&
6908 "Bad ScalarizeVectorOp invocation!");
6909 SDNode *Node = Op.Val;
6910 MVT::ValueType NewVT = MVT::getVectorElementType(Op.getValueType());
6911 assert(MVT::getVectorNumElements(Op.getValueType()) == 1);
6913 // See if we already scalarized it.
6914 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op);
6915 if (I != ScalarizedNodes.end()) return I->second;
6918 switch (Node->getOpcode()) {
6921 Node->dump(&DAG); cerr << "\n";
6923 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
6940 Result = DAG.getNode(Node->getOpcode(),
6942 ScalarizeVectorOp(Node->getOperand(0)),
6943 ScalarizeVectorOp(Node->getOperand(1)));
6950 Result = DAG.getNode(Node->getOpcode(),
6952 ScalarizeVectorOp(Node->getOperand(0)));
6955 Result = DAG.getNode(Node->getOpcode(),
6957 ScalarizeVectorOp(Node->getOperand(0)),
6958 Node->getOperand(1));
6961 LoadSDNode *LD = cast<LoadSDNode>(Node);
6962 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
6963 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
6965 const Value *SV = LD->getSrcValue();
6966 int SVOffset = LD->getSrcValueOffset();
6967 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset,
6968 LD->isVolatile(), LD->getAlignment());
6970 // Remember that we legalized the chain.
6971 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
6974 case ISD::BUILD_VECTOR:
6975 Result = Node->getOperand(0);
6977 case ISD::INSERT_VECTOR_ELT:
6978 // Returning the inserted scalar element.
6979 Result = Node->getOperand(1);
6981 case ISD::CONCAT_VECTORS:
6982 assert(Node->getOperand(0).getValueType() == NewVT &&
6983 "Concat of non-legal vectors not yet supported!");
6984 Result = Node->getOperand(0);
6986 case ISD::VECTOR_SHUFFLE: {
6987 // Figure out if the scalar is the LHS or RHS and return it.
6988 SDOperand EltNum = Node->getOperand(2).getOperand(0);
6989 if (cast<ConstantSDNode>(EltNum)->getValue())
6990 Result = ScalarizeVectorOp(Node->getOperand(1));
6992 Result = ScalarizeVectorOp(Node->getOperand(0));
6995 case ISD::EXTRACT_SUBVECTOR:
6996 Result = Node->getOperand(0);
6997 assert(Result.getValueType() == NewVT);
6999 case ISD::BIT_CONVERT:
7000 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));
7003 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
7004 ScalarizeVectorOp(Op.getOperand(1)),
7005 ScalarizeVectorOp(Op.getOperand(2)));
7009 if (TLI.isTypeLegal(NewVT))
7010 Result = LegalizeOp(Result);
7011 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
7012 assert(isNew && "Value already scalarized?");
7017 // SelectionDAG::Legalize - This is the entry point for the file.
7019 void SelectionDAG::Legalize() {
7020 if (ViewLegalizeDAGs) viewGraph();
7022 /// run - This is the main entry point to this class.
7024 SelectionDAGLegalize(*this).LegalizeDAG();